From ca8a7514c15d4dd9869bfbfbe3423006d21f0415 Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Tue, 10 Feb 2026 11:12:42 -0500 Subject: [PATCH 01/58] Prototype of custom kernels from anywhere --- .../Tensile/Common/GlobalParameters.py | 1 + .../Tensile/Common/ValidParameters.py | 1 + .../tensilelite/Tensile/Contractions.py | 20 +- .../tensilelite/Tensile/LibraryIO.py | 4 +- .../Tensile/SolutionStructs/Naming.py | 6 +- .../include/Tensile/ContractionSolution.hpp | 41 ++- .../include/Tensile/Serialization/Base.hpp | 15 + .../Serialization/ContractionSolution.hpp | 15 +- .../tensilelite/src/ContractionSolution.cpp | 257 +++++++++++++++++- 9 files changed, 347 insertions(+), 13 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py index 5448f86a8cf3..46a270ee8b3e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py @@ -426,6 +426,7 @@ {"NonTemporal": [-1]}, {"PreloadKernArgs": [True]}, {"CustomKernelName": [""]}, + {"CustomKernel": [{"name": "", "args": []}]}, {"NoReject": [False]}, {"StoreRemapVectorWidth": [0]}, {"SourceSwap": [False]}, diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py index bdc3b1cc3378..e9c26a368f42 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py @@ -877,6 +877,7 @@ def makeValidMatrixInstructions(): # Custom kernels can be included in a BenchmarkProblemSizeGroup by having their name (without file extension) listed under the "CustomKernels" # category alongside InitialSolutionParameters, BenchmarkCommonParameters, etc... "CustomKernelName": -1, + "CustomKernel": -1, # Will allow a kernel to be accepted even when checks determine it's not viable. # Intended for use with custom kernels which have confirmed to be correct "NoReject": [False, True], diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index be298c95b7db..db860d242683 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -581,6 +581,17 @@ def FromOriginalState(cls, d, problemType, morePreds=[]): predicates = [p for p in map(cls.FromOriginalKeyPair, d.items()) if p is not None] + extraPreds return cls.And(predicates) +class CustomKernel: + StateKeys = ['name', 'args'] + + @classmethod + def FromOriginalState(cls, d): + return cls(name=d['name'], args=d['args']) + + def __init__(self, **kwargs): + for (key, value) in list(kwargs.items()): + setattr(self, key, value) + class SizeMapping: StateKeys = ['waveNum', 'workGroup', @@ -607,7 +618,7 @@ class SizeMapping: 'workspaceSizePerElemC', 'workspaceSizePerElemBias', 'activationFused', - 'CustomKernelName', + 'customKernel', 'workGroupMappingXCC', 'workGroupMappingXCCGroup', 'globalSplitUCoalesced', @@ -670,6 +681,11 @@ def convertSFCWGMListToHex(value): dtlA = bool(d['DirectToLdsA']) dtlB = bool(d['DirectToLdsB']) + if 'CustomKernel' in d: + customKernel = CustomKernel.FromOriginalState(d['CustomKernel']) + else: + customKernel = CustomKernel(name="", args=[]) + return cls(waveNum = d['NumThreads'] // d['WavefrontSize'], workGroup = d['WorkGroup'], macroTile = cls.ReadOriginalMacroTile(d), @@ -695,7 +711,7 @@ def convertSFCWGMListToHex(value): workspaceSizePerElemC = d['_WorkspaceSizePerElemC'], workspaceSizePerElemBias = d['_WorkspaceSizePerElemBias'], activationFused = d['ActivationFused'], - CustomKernelName = d['CustomKernelName'], + customKernel = customKernel, workGroupMappingXCC = d['WorkGroupMappingXCC'], workGroupMappingXCCGroup = d['WorkGroupMappingXCCGroup'], globalSplitUCoalesced = d['GlobalSplitUCoalesced'], diff --git a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py index 8d89015fde6c..6b6b6ae8c023 100644 --- a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py +++ b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py @@ -345,11 +345,11 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Solution: # force redo the deriving of parameters, make sure old version logic yamls can be validated solutionState["AssignedProblemIndependentDerivedParameters"] = False solutionState["AssignedDerivedParameters"] = False - if solutionState["CustomKernelName"]: + if "CustomKernel" in solutionState and solutionState["CustomKernel"]["name"]: isp = {} if "InternalSupportParams" in solutionState: isp = solutionState["InternalSupportParams"] - customConfig = getCustomKernelConfig(solutionState["CustomKernelName"], isp) + customConfig = getCustomKernelConfig(solutionState["CustomKernel"]["name"], isp) for key, value in customConfig.items(): solutionState[key] = value diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py index fc597560d5bf..dc07955c7ed8 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py @@ -95,8 +95,8 @@ def getParameterValueAbbreviation(key, value): def _getName(state, requiredParameters: frozenset, splitGSU: bool, ignoreInternalArgs): - if "CustomKernelName" in state and state["CustomKernelName"]: - return state["CustomKernelName"] + if "CustomKernel" in state and state["CustomKernel"]["name"]: + return state["CustomKernel"]["name"] gsuBackup = state["GlobalSplitU"] ggBackup = state["ProblemType"]["GroupedGemm"] @@ -145,7 +145,7 @@ def _getName(state, requiredParameters: frozenset, splitGSU: bool, ignoreInterna # Skip SFA tag if using default wgm algo if key == "SpaceFillingAlgo" and len(state[key]) == 0: continue - if key[0] != '_' and key != "CustomKernelName" and key in requiredParametersTemp: + if key[0] != '_' and key != "CustomKernel" and key in requiredParametersTemp: components.append(f'{getParameterNameAbbreviation(key)}{getParameterValueAbbreviation(key, state[key])}') state["GlobalSplitU"] = gsuBackup diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index c51e814e22cc..d43244fb4083 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -50,6 +50,33 @@ namespace TensileLite { + enum KernelArgumentType + { + SizeFree0, // 0 + SizeFree1, // 1 + SizeFree2, // 2 + SizeSum, // 3 + AddressA, // 4 + AddressB, // 5 + AddressC, // 6 + AddressD, // 7 + StrideA0, // 8 + StrideA1, // 9 + StrideB0, // 10 + StrideB1, // 11 + StrideC0, // 12 + StrideC1, // 13 + StrideD0, // 14 + StrideD1, // 15 + Alpha, // 16 + Beta, // 17 + Count, // 18 + }; + + std::string toString(KernelArgumentType arg); + std::ostream& operator<<(std::ostream& stream, const KernelArgumentType& t); + std::istream& operator>>(std::istream& stream, KernelArgumentType& t); + template struct DeviceUserArguments { @@ -111,6 +138,12 @@ namespace TensileLite size_t depthUorMT1; }; + struct CustomKernel + { + std::string name; + std::vector args; + }; + struct SizeMapping { size_t waveNum; @@ -149,7 +182,7 @@ namespace TensileLite bool activationFused = true; - std::string customKernelName; + CustomKernel customKernel; int workGroupMappingXCC = 0; int workGroupMappingXCCGroup = 0; @@ -450,6 +483,12 @@ namespace TensileLite KA& h_args, uint32_t autoGsuVal) const; + template + KernelInvocation generateCustomCall(Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk) const; + template KernelInvocation generateSingleCall(Problem const& problem, ContractionInputs const& inputs, diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index ea244a43b756..823d028d3138 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -366,6 +366,21 @@ namespace TensileLite } }; + template + struct EnumTraits + { + using iot = IOTraits; + + static void enumeration(IO& io, KernelArgumentType& value) + { + for(int i = 0; i < static_cast(KernelArgumentType::Count); i++) + { + auto const& info = static_cast(i); + iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); + } + } + }; + template struct EnumTraits { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 7f8901742302..4d69f096946f 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -73,6 +73,19 @@ namespace TensileLite const static bool flow = false; }; + template + struct MappingTraits + { + using iot = IOTraits; + static void mapping(IO& io, CustomKernel& s) + { + iot::mapOptional(io, "name", s.name); + iot::mapOptional(io, "args", s.args); + } + + const static bool flow = false; + }; + template struct MappingTraits { @@ -113,7 +126,7 @@ namespace TensileLite iot::mapOptional(io, "activationFused", s.activationFused); - iot::mapOptional(io, "CustomKernelName", s.customKernelName); + iot::mapOptional(io, "customKernel", s.customKernel); iot::mapRequired(io, "workGroupMappingXCC", s.workGroupMappingXCC); iot::mapRequired(io, "workGroupMappingXCCGroup", s.workGroupMappingXCCGroup); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 7ebed2ff958e..77355f10d325 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -53,6 +53,143 @@ namespace TensileLite { + + std::string toString(KernelArgumentType arg) + { + switch(arg) + { + case KernelArgumentType::SizeFree0: + return "SizeFree0"; + case KernelArgumentType::SizeFree1: + return "SizeFree1"; + case KernelArgumentType::SizeFree2: + return "SizeFree2"; + case KernelArgumentType::SizeSum: + return "SizeSum"; + case KernelArgumentType::AddressA: + return "AddressA"; + case KernelArgumentType::AddressB: + return "AddressB"; + case KernelArgumentType::AddressC: + return "AddressC"; + case KernelArgumentType::AddressD: + return "AddressD"; + case KernelArgumentType::StrideA0: + return "StrideA0"; + case KernelArgumentType::StrideA1: + return "StrideA1"; + case KernelArgumentType::StrideB0: + return "StrideB0"; + case KernelArgumentType::StrideB1: + return "StrideB1"; + case KernelArgumentType::StrideC0: + return "StrideC0"; + case KernelArgumentType::StrideC1: + return "StrideC1"; + case KernelArgumentType::StrideD0: + return "StrideD0"; + case KernelArgumentType::StrideD1: + return "StrideD1"; + case KernelArgumentType::Alpha: + return "Alpha"; + case KernelArgumentType::Beta: + return "Beta"; + case KernelArgumentType::Count: + break; + } + + throw std::runtime_error( + concatenate("Invalid KernelArgumentType value: ", static_cast(arg))); + } + + std::ostream& operator<<(std::ostream& stream, const KernelArgumentType& t) + { + return stream << toString(t); + } + + std::istream& operator>>(std::istream& stream, KernelArgumentType& t) + { + std::string strValue; + stream >> strValue; + if(strValue == toString(KernelArgumentType::SizeFree0)) + { + t = KernelArgumentType::SizeFree0; + } + else if(strValue == toString(KernelArgumentType::SizeFree1)) + { + t = KernelArgumentType::SizeFree1; + } + else if(strValue == toString(KernelArgumentType::SizeFree2)) + { + t = KernelArgumentType::SizeFree2; + } + else if(strValue == toString(KernelArgumentType::SizeSum)) + { + t = KernelArgumentType::SizeSum; + } + else if(strValue == toString(KernelArgumentType::AddressA)) + { + t = KernelArgumentType::AddressA; + } + else if(strValue == toString(KernelArgumentType::AddressB)) + { + t = KernelArgumentType::AddressB; + } + else if(strValue == toString(KernelArgumentType::AddressC)) + { + t = KernelArgumentType::AddressC; + } + else if(strValue == toString(KernelArgumentType::AddressD)) + { + t = KernelArgumentType::AddressD; + } + else if(strValue == toString(KernelArgumentType::StrideA0)) + { + t = KernelArgumentType::StrideA0; + } + else if(strValue == toString(KernelArgumentType::StrideA1)) + { + t = KernelArgumentType::StrideA1; + } + else if(strValue == toString(KernelArgumentType::StrideB0)) + { + t = KernelArgumentType::StrideB0; + } + else if(strValue == toString(KernelArgumentType::StrideB1)) + { + t = KernelArgumentType::StrideB1; + } + else if(strValue == toString(KernelArgumentType::StrideC0)) + { + t = KernelArgumentType::StrideC0; + } + else if(strValue == toString(KernelArgumentType::StrideC1)) + { + t = KernelArgumentType::StrideC1; + } + else if(strValue == toString(KernelArgumentType::StrideD0)) + { + t = KernelArgumentType::StrideD0; + } + else if(strValue == toString(KernelArgumentType::StrideD1)) + { + t = KernelArgumentType::StrideD1; + } + else if(strValue == toString(KernelArgumentType::Alpha)) + { + t = KernelArgumentType::Alpha; + } + else if(strValue == toString(KernelArgumentType::Beta)) + { + t = KernelArgumentType::Beta; + } + else + { + throw std::runtime_error(concatenate("Invalid argument type: ", strValue)); + } + return stream; + } + enum class KERNELARGTYPE { NORMAL = 0, @@ -1390,6 +1527,104 @@ namespace TensileLite numWorkGroups.y = CeilDivide(numWorkGroups.y, sizeMapping.macroTile.y); } + template + KernelInvocation ContractionSolution::generateCustomCall(ContractionSolution::Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk) const + { + KernelInvocation rv; + rv.isSingleCall = true; + rv.args = KernelArguments(T_Debug); + rv.args.reserve(1024, 128); + rv.kernelName = kernelName; + + calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); + rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + rv.numWorkGroups.y = 1; + rv.numWorkGroups.z = 1; + + rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; + rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; + rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; + + // Temporarily set internal args manually + uint32_t gemmCount = 1; + gemmCount = gemmCount & 0x3FFFFFFF; + rv.args.template append("gemm_count", gemmCount); + uint32_t internalArg0 = 1048577; + rv.args.template append("internalArgs", internalArg0); + int32_t internalArg1 = 436731905; + rv.args.template append("internalArgs1", internalArg1); + + uint32_t numWorkGroups = getNumWorkGroups(rv); + rv.args.template append("numWorkGroups", numWorkGroups); + + for(auto arg : sizeMapping.customKernel.args) + { + switch(arg) + { + case KernelArgumentType::SizeFree0: + rv.args.template append("SizeFree0", problem.problemSizes()[0]); + break; + case KernelArgumentType::SizeFree1: + rv.args.template append("SizeFree1", problem.problemSizes()[1]); + break; + case KernelArgumentType::SizeFree2: + rv.args.template append("SizeFree2", problem.problemSizes()[2]); + break; + case KernelArgumentType::SizeSum: + rv.args.template append("SizeSum", problem.problemSizes()[3]); + break; + case KernelArgumentType::AddressA: + rv.args.template append("AddressA", inputs.a); + break; + case KernelArgumentType::AddressB: + rv.args.template append("AddressB", inputs.b); + break; + case KernelArgumentType::AddressC: + rv.args.template append("AddressC", inputs.c); + break; + case KernelArgumentType::AddressD: + rv.args.template append("AddressD", inputs.d); + break; + case KernelArgumentType::StrideA0: + rv.args.template append("StrideA0", problem.a().strides()[1]); + break; + case KernelArgumentType::StrideA1: + rv.args.template append("StrideA1", problem.a().strides()[2]); + break; + case KernelArgumentType::StrideB0: + rv.args.template append("StrideB0", problem.b().strides()[1]); + break; + case KernelArgumentType::StrideB1: + rv.args.template append("StrideB1", problem.b().strides()[2]); + break; + case KernelArgumentType::StrideC0: + rv.args.template append("StrideC0", problem.c().strides()[1]); + break; + case KernelArgumentType::StrideC1: + rv.args.template append("StrideC1", problem.c().strides()[2]); + break; + case KernelArgumentType::StrideD0: + rv.args.template append("StrideD0", problem.d().strides()[1]); + break; + case KernelArgumentType::StrideD1: + rv.args.template append("StrideD1", problem.d().strides()[2]); + break; + case KernelArgumentType::Alpha: + rv.args.append("Alpha", inputs.alpha, problem.alphaType()); + break; + case KernelArgumentType::Beta: + rv.args.append("Beta", inputs.beta, problem.betaType()); + break; + default: + throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); + } + } + return rv; + } + template KernelInvocation ContractionSolution::generateSingleCall(ContractionSolution::Problem const& problem, @@ -2769,10 +3004,24 @@ namespace TensileLite } } - if(debug) - rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); + if(sizeMapping.customKernel.name.empty()) + { + // Regular generated kernel + if(debug) + rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); + else + rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); + } else - rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); + { + // Custom kernel + if(debug) + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + else + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + } + + if(((sizeMapping.globalAccumulation != 3) && gsu > 1 && sizeMapping.globalAccumulation) || sk.reduction == origami::reduction_t::parallel) @@ -3292,7 +3541,7 @@ namespace TensileLite AMDGPU const* pAMDGPU = dynamic_cast(&hardware); assert(pAMDGPU != nullptr && pAMDGPU->computeUnitCount != 0); - if(!sizeMapping.customKernelName.empty()) + if(!sizeMapping.customKernel.name.empty()) { // Custom kernel currently only supports single-kernel reduction reductionStrat = origami::reduction_t::tree; From 275b28872086134c3f0a0f6897d15292ac0adfa7 Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Tue, 10 Feb 2026 12:58:25 -0500 Subject: [PATCH 02/58] Fix KernelArgumentType serialization by name --- .../tensilelite/include/Tensile/ContractionSolution.hpp | 2 +- .../include/Tensile/Serialization/Containers.hpp | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index d43244fb4083..222f08c1b14d 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -141,7 +141,7 @@ namespace TensileLite struct CustomKernel { std::string name; - std::vector args; + std::vector args; }; struct SizeMapping diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp index cd18e2aee050..96b866873273 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp @@ -201,6 +201,12 @@ namespace TensileLite TENSILE_SERIALIZE_VECTOR(true, TensileLite::MLPClassification::ResBlock); + template + struct SequenceTraits, IO> + : public DefaultSequenceTraits, IO, false> + { + }; + template struct SequenceTraits>, IO> : public DefaultSequenceTraits>, IO, false> From 602cfeb819f5249c0f0d90a2e1764c02f9a4dcee Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Wed, 25 Feb 2026 14:14:13 -0500 Subject: [PATCH 03/58] Demo calling CK kernel. Add code object V6. Fix some build/packaging issues with new custom kernel format. Add DebugPattern argument which puts easy to spot data in the argument buffer for debugging. --- .../tensilelite/Tensile/Common/Constants.py | 2 + .../Tensile/Common/GlobalParameters.py | 1 - .../Tensile/Common/ValidParameters.py | 1 - .../tensilelite/Tensile/CustomKernels.py | 4 +- .../Tensile/CustomKernels/README.md | 2 +- ..._gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s | 179819 +++++++++++++++ .../Tensile/SolutionStructs/Naming.py | 4 +- .../Tensile/SolutionStructs/Solution.py | 4 +- .../hipblaslt/tensilelite/Tensile/Tensile.py | 2 +- .../TensileCreateLibrary/ParseArguments.py | 2 +- .../TensileLogic/HandleCustomKernel.py | 4 +- .../Tensile/Tests/custom/custom_ck.yaml | 98 + .../include/Tensile/ContractionSolution.hpp | 3 +- .../tensilelite/src/ContractionSolution.cpp | 32 +- 14 files changed, 179954 insertions(+), 24 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/Constants.py b/projects/hipblaslt/tensilelite/Tensile/Common/Constants.py index 2045e2049a68..f6ddfe167f53 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/Constants.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/Constants.py @@ -5,6 +5,8 @@ "V4": "4", "5": "5", "V5": "5", + "6": "6", + "V6": "6", "default": "4", } diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py index 46a270ee8b3e..6228ffb3ce47 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py @@ -425,7 +425,6 @@ {"NonTemporalMetadata": [0]}, {"NonTemporal": [-1]}, {"PreloadKernArgs": [True]}, - {"CustomKernelName": [""]}, {"CustomKernel": [{"name": "", "args": []}]}, {"NoReject": [False]}, {"StoreRemapVectorWidth": [0]}, diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py index e9c26a368f42..eb5444c6d910 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py @@ -876,7 +876,6 @@ def makeValidMatrixInstructions(): # # Custom kernels can be included in a BenchmarkProblemSizeGroup by having their name (without file extension) listed under the "CustomKernels" # category alongside InitialSolutionParameters, BenchmarkCommonParameters, etc... - "CustomKernelName": -1, "CustomKernel": -1, # Will allow a kernel to be accepted even when checks determine it's not viable. # Intended for use with custom kernels which have confirmed to be correct diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index ffceb636f5e4..8e02cde22a35 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -30,7 +30,7 @@ import os def isCustomKernelConfig(config): - return "CustomKernelName" in config and config["CustomKernelName"] + return "CustomKernel" in config and config["CustomKernel"]["name"] def getCustomKernelFilepath(name, directory=CUSTOM_KERNEL_PATH): return os.path.join(directory, (name + ".s")) @@ -101,6 +101,6 @@ def getCustomKernelConfig( checkParametersAreValid((k, [v]), validParameters) kernelConfig["KernelLanguage"] = "Assembly" - kernelConfig["CustomKernelName"] = kernelName + kernelConfig["CustomKernel"]["name"] = kernelName return kernelConfig diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md index 34f0c0246e8a..18d69d85be73 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md @@ -18,4 +18,4 @@ Tensile/bin/TensileLogic --check-only-custom-kernels ``` where `` is a path to a logic file containing a solution where -`CustomKernelName` references the custom kernel requiring validation. +`CustomKernel` references the custom kernel requiring validation. diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s new file mode 100644 index 000000000000..c81b2cc61262 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s @@ -0,0 +1,179819 @@ + .amdgcn_target "amdgcn-amd-amdhsa--gfx942" + .amdhsa_code_object_version 6 + .section .text._ZN7ck_tileL11flush_cacheEv,"axG",@progbits,_ZN7ck_tileL11flush_cacheEv,comdat + .globl _ZN7ck_tileL11flush_cacheEv ; -- Begin function _ZN7ck_tileL11flush_cacheEv + .p2align 8 + .type _ZN7ck_tileL11flush_cacheEv,@function +_ZN7ck_tileL11flush_cacheEv: ; @_ZN7ck_tileL11flush_cacheEv +; %bb.0: + ;;#ASMSTART + s_icache_inv + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + + ;;#ASMEND + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tileL11flush_cacheEv + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 0 + .amdhsa_user_sgpr_count 0 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 0 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 1 + .amdhsa_next_free_sgpr 0 + .amdhsa_accum_offset 4 + .amdhsa_reserve_vcc 0 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tileL11flush_cacheEv,"axG",@progbits,_ZN7ck_tileL11flush_cacheEv,comdat +.Lfunc_end0: + .size _ZN7ck_tileL11flush_cacheEv, .Lfunc_end0-_ZN7ck_tileL11flush_cacheEv + ; -- End function + .set _ZN7ck_tileL11flush_cacheEv.num_vgpr, 0 + .set _ZN7ck_tileL11flush_cacheEv.num_agpr, 0 + .set _ZN7ck_tileL11flush_cacheEv.numbered_sgpr, 0 + .set _ZN7ck_tileL11flush_cacheEv.num_named_barrier, 0 + .set _ZN7ck_tileL11flush_cacheEv.private_seg_size, 0 + .set _ZN7ck_tileL11flush_cacheEv.uses_vcc, 0 + .set _ZN7ck_tileL11flush_cacheEv.uses_flat_scratch, 0 + .set _ZN7ck_tileL11flush_cacheEv.has_dyn_sized_stack, 0 + .set _ZN7ck_tileL11flush_cacheEv.has_recursion, 0 + .set _ZN7ck_tileL11flush_cacheEv.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 140 +; TotalNumSgprs: 6 +; NumVgprs: 0 +; NumAgprs: 0 +; TotalNumVgprs: 0 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 0 +; VGPRBlocks: 0 +; NumSGPRsForWavesPerEU: 6 +; NumVGPRsForWavesPerEU: 1 +; AccumOffset: 4 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 0 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 0 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s2, s12, s2 + s_mul_i32 s12, s2, s7 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[12:13], s[12:13], 1 + s_add_u32 s8, s8, s12 + s_addc_u32 s9, s9, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s22, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s20, s3 + s_add_u32 s2, s2, s3 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v226, -1, v0 + v_and_b32_e32 v72, 31, v226 + v_lshrrev_b32_e32 v2, 5, v226 + v_and_b32_e32 v69, 7, v226 + v_lshrrev_b32_e32 v3, 2, v226 + s_cbranch_scc0 .LBB1_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + s_lshr_b32 s24, s15, 2 + v_lshlrev_b32_e32 v1, 3, v2 + s_and_b32 s23, s24, 0x3ffffff0 + v_lshl_or_b32 v0, v72, 3, s18 + v_add_u32_e32 v4, s23, v1 + v_mad_u64_u32 v[4:5], s[10:11], v4, s7, v[0:1] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[8:11], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v4 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v5, 1, v0 + buffer_load_dwordx4 v[16:19], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[20:23], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v5, 1, v0 + buffer_load_dwordx4 v[24:27], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[28:31], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[32:35], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[36:39], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v4, 12, v2 + v_lshlrev_b32_e32 v68, 3, v69 + v_and_b32_e32 v5, 0x78, v226 + v_xor_b32_e32 v0, v2, v69 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s25, 0x1000504 + s_mov_b32 s26, 0x3020706 + v_lshl_or_b32 v7, v69, 8, v4 + s_and_b32 s10, s15, 0xffffffc0 + s_lshr_b32 s27, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s24, 0x3fffffe0 + v_add_u32_e32 v5, s10, v5 + v_and_or_b32 v70, s27, 32, v72 + v_or_b32_e32 v4, s11, v72 + v_add_u32_e32 v40, s19, v5 + v_lshrrev_b32_e32 v6, 3, v4 + v_mad_u64_u32 v[40:41], s[10:11], v40, s20, v[68:69] + v_xor_b32_e32 v71, v6, v69 + v_lshlrev_b32_e32 v48, 1, v40 + v_add_u32_e32 v40, s20, v40 + v_lshl_add_u32 v7, v71, 3, v7 + v_lshlrev_b32_e32 v49, 1, v40 + v_add_u32_e32 v50, s20, v40 + buffer_load_dwordx4 v[40:43], v48, s[12:15], 0 offen + buffer_load_dwordx4 v[44:47], v49, s[12:15], 0 offen + v_lshlrev_b32_e32 v56, 1, v50 + v_add_u32_e32 v48, s20, v50 + v_lshlrev_b32_e32 v57, 1, v48 + v_add_u32_e32 v58, s20, v48 + buffer_load_dwordx4 v[48:51], v56, s[12:15], 0 offen + buffer_load_dwordx4 v[52:55], v57, s[12:15], 0 offen + v_lshlrev_b32_e32 v64, 1, v58 + v_add_u32_e32 v56, s20, v58 + v_lshlrev_b32_e32 v65, 1, v56 + v_add_u32_e32 v66, s20, v56 + buffer_load_dwordx4 v[56:59], v64, s[12:15], 0 offen + buffer_load_dwordx4 v[60:63], v65, s[12:15], 0 offen + v_lshlrev_b32_e32 v73, 1, v66 + v_add_lshl_u32 v78, v66, s20, 1 + buffer_load_dwordx4 v[64:67], v73, s[12:15], 0 offen + buffer_load_dwordx4 v[74:77], v78, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v78, v8, v12, s25 + v_perm_b32 v82, v8, v12, s26 + v_perm_b32 v86, v9, v13, s25 + v_perm_b32 v90, v9, v13, s26 + v_perm_b32 v94, v10, v14, s25 + v_perm_b32 v98, v10, v14, s26 + s_waitcnt vmcnt(12) + v_perm_b32 v79, v16, v20, s25 + v_perm_b32 v83, v16, v20, s26 + v_perm_b32 v87, v17, v21, s25 + v_perm_b32 v91, v17, v21, s26 + s_waitcnt vmcnt(10) + v_perm_b32 v80, v24, v28, s25 + v_perm_b32 v84, v24, v28, s26 + v_perm_b32 v88, v25, v29, s25 + v_perm_b32 v92, v25, v29, s26 + s_waitcnt vmcnt(8) + v_perm_b32 v81, v32, v36, s25 + v_perm_b32 v85, v32, v36, s26 + v_perm_b32 v89, v33, v37, s25 + v_perm_b32 v93, v33, v37, s26 + v_perm_b32 v95, v18, v22, s25 + v_perm_b32 v99, v18, v22, s26 + v_perm_b32 v96, v26, v30, s25 + v_perm_b32 v100, v26, v30, s26 + v_perm_b32 v97, v34, v38, s25 + v_perm_b32 v101, v34, v38, s26 + v_perm_b32 v8, v11, v15, s25 + v_perm_b32 v12, v11, v15, s26 + v_perm_b32 v9, v19, v23, s25 + v_perm_b32 v13, v19, v23, s26 + v_perm_b32 v10, v27, v31, s25 + v_perm_b32 v14, v27, v31, s26 + v_perm_b32 v11, v35, v39, s25 + v_perm_b32 v15, v35, v39, s26 + v_and_b32_e32 v16, 24, v3 + v_add_u32_e32 v16, s23, v16 + v_lshrrev_b32_e32 v17, 2, v16 + v_and_b32_e32 v17, 24, v17 + v_xor_b32_e32 v18, v17, v72 + v_lshlrev_b32_e32 v19, 9, v16 + v_and_b32_e32 v19, 0x3000, v19 + v_lshlrev_b32_e32 v16, 6, v16 + v_and_b32_e32 v16, 0xfffff800, v16 + v_add_u32_e32 v16, v16, v19 + v_lshl_or_b32 v16, v18, 3, v16 + v_lshlrev_b32_e32 v19, 1, v16 + ds_write_b128 v19, v[78:81] + v_or_b32_e32 v20, 1, v17 + v_xor_b32_e32 v20, v20, v72 + v_sub_u32_e32 v18, v20, v18 + v_lshlrev_b32_e32 v21, 3, v18 + v_or_b32_e32 v22, 2, v17 + v_xor_b32_e32 v22, v22, v72 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v23, 3, v20 + v_add3_u32 v16, v21, v16, v23 + v_lshl_add_u32 v18, v18, 4, v19 + ds_write_b128 v18, v[82:85] offset:512 + v_or_b32_e32 v19, 3, v17 + v_xor_b32_e32 v19, v19, v72 + v_sub_u32_e32 v21, v19, v22 + v_lshlrev_b32_e32 v22, 3, v21 + v_or_b32_e32 v23, 4, v17 + v_xor_b32_e32 v23, v23, v72 + v_sub_u32_e32 v19, v23, v19 + v_lshlrev_b32_e32 v24, 3, v19 + v_add3_u32 v16, v16, v22, v24 + v_lshlrev_b32_e32 v20, 4, v20 + s_movk_i32 s10, 0x200 + v_add3_u32 v18, v18, s10, v20 + ds_write_b128 v18, v[86:89] offset:512 + v_or_b32_e32 v20, 5, v17 + v_xor_b32_e32 v20, v20, v72 + v_sub_u32_e32 v22, v20, v23 + v_lshlrev_b32_e32 v23, 3, v22 + v_or_b32_e32 v24, 6, v17 + v_xor_b32_e32 v24, v24, v72 + v_sub_u32_e32 v20, v24, v20 + v_lshlrev_b32_e32 v25, 3, v20 + v_add3_u32 v16, v16, v23, v25 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v18, v18, s10, v21 + ds_write_b128 v18, v[90:93] offset:512 + v_or_b32_e32 v17, 7, v17 + v_xor_b32_e32 v17, v17, v72 + v_sub_u32_e32 v17, v17, v24 + v_lshlrev_b32_e32 v17, 4, v17 + v_lshl_add_u32 v16, v16, 1, v17 + v_lshlrev_b32_e32 v17, 4, v19 + v_add3_u32 v17, v18, s10, v17 + ds_write_b128 v17, v[94:97] offset:512 + v_lshlrev_b32_e32 v18, 4, v22 + v_add3_u32 v17, v17, s10, v18 + ds_write_b128 v17, v[98:101] offset:512 + v_lshlrev_b32_e32 v18, 4, v20 + v_add3_u32 v17, v17, s10, v18 + ds_write_b128 v17, v[8:11] offset:512 + ds_write_b128 v16, v[12:15] offset:3584 + v_lshl_or_b32 v8, v5, 6, v68 + v_lshlrev_b32_e32 v9, 1, v8 + s_waitcnt vmcnt(7) + ds_write_b128 v9, v[40:43] offset:32768 + v_or_b32_e32 v10, 1, v5 + v_ashrrev_i32_e32 v11, 31, v5 + v_lshrrev_b32_e32 v11, 29, v11 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v12, v10, v69 + v_lshl_add_u32 v8, v12, 3, v8 + v_lshl_add_u32 v9, v12, 4, v9 + s_waitcnt vmcnt(6) + ds_write_b128 v9, v[44:47] offset:32896 + v_or_b32_e32 v9, 2, v5 + v_add_u32_e32 v12, v9, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v9, v9, v12 + v_xor_b32_e32 v9, v9, v69 + v_sub_u32_e32 v10, v9, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v8, v8, v10, 64 + v_lshlrev_b32_e32 v10, 1, v8 + s_waitcnt vmcnt(5) + ds_write_b128 v10, v[48:51] offset:32896 + v_or_b32_e32 v10, 3, v5 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v9, v10, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v8, v8, v9, 64 + v_lshlrev_b32_e32 v9, 1, v8 + s_waitcnt vmcnt(4) + ds_write_b128 v9, v[52:55] offset:32896 + v_or_b32_e32 v9, 4, v5 + v_add_u32_e32 v12, v9, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v9, v9, v12 + v_xor_b32_e32 v9, v9, v69 + v_sub_u32_e32 v10, v9, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v8, v8, v10, 64 + v_lshlrev_b32_e32 v10, 1, v8 + s_waitcnt vmcnt(3) + ds_write_b128 v10, v[56:59] offset:32896 + v_or_b32_e32 v10, 5, v5 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v9, v10, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v8, v8, v9, 64 + v_lshlrev_b32_e32 v9, 1, v8 + s_waitcnt vmcnt(2) + ds_write_b128 v9, v[60:63] offset:32896 + v_or_b32_e32 v9, 6, v5 + v_add_u32_e32 v12, v9, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v9, v9, v12 + v_xor_b32_e32 v9, v9, v69 + v_sub_u32_e32 v10, v9, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add_lshl_u32 v8, v8, v10, 1 + v_or_b32_e32 v5, 7, v5 + v_add_u32_e32 v10, v5, v11 + v_and_b32_e32 v10, 0xffffff8, v10 + v_sub_u32_e32 v5, v5, v10 + v_xor_b32_e32 v5, v5, v69 + v_sub_u32_e32 v5, v5, v9 + v_lshl_add_u32 v5, v5, 4, v8 + s_waitcnt vmcnt(1) + ds_write_b128 v8, v[64:67] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v5, v[74:77] offset:33152 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v5, 1, v7 + ds_read_b128 v[26:29], v5 + v_add_u32_e32 v5, 16, v1 + v_lshrrev_b32_e32 v8, 5, v5 + v_bfe_u32 v9, v5, 3, 2 + v_lshl_or_b32 v10, v8, 3, v69 + v_and_b32_e32 v11, 31, v10 + v_xor_b32_e32 v12, v6, v11 + v_sub_u32_e32 v5, v12, v71 + v_lshlrev_b32_e32 v13, 11, v8 + v_lshlrev_b32_e32 v5, 3, v5 + v_sub_u32_e32 v14, v9, v2 + v_lshl_or_b32 v13, v14, 12, v13 + v_add3_u32 v5, v7, v13, v5 + v_lshlrev_b32_e32 v7, 1, v5 + v_lshlrev_b32_e32 v14, 7, v70 + v_lshl_or_b32 v15, v0, 4, v14 + ds_read_b128 v[34:37], v15 offset:32768 + ds_read_b128 v[38:41], v7 + v_xor_b32_e32 v8, 1, v8 + v_sub_u32_e32 v9, v2, v9 + v_lshl_add_u32 v10, v8, 3, v10 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[26:27], v[34:35], 0 + v_and_b32_e32 v15, 31, v10 + v_xor_b32_e32 v16, v6, v15 + v_sub_u32_e32 v12, v16, v12 + v_lshlrev_b32_e32 v8, 11, v8 + v_add_u32_e32 v17, 6, v2 + v_xor_b32_e32 v17, v17, v69 + v_lshl_add_u32 v18, v17, 4, v14 + v_mfma_f32_32x32x8_f16 a[0:15], v[28:29], v[36:37], a[0:15] + v_sub_u32_e32 v19, v0, v17 + v_lshl_add_u32 v19, v19, 4, v18 + ds_read_b128 v[42:45], v19 offset:40960 + v_lshl_add_u32 v8, v9, 12, v8 + v_lshl_add_u32 v9, v12, 3, v8 + v_lshl_add_u32 v7, v9, 1, v7 + v_add_u32_e32 v1, 48, v1 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[26:27], v[42:43], 0 + v_lshrrev_b32_e32 v12, 5, v1 + v_add_u32_e32 v20, -1, v12 + v_bfe_u32 v1, v1, 3, 2 + v_sub_u32_e32 v21, v1, v2 + v_lshl_add_u32 v10, v20, 3, v10 + v_ashrrev_i32_e32 v22, 31, v10 + v_lshrrev_b32_e32 v22, 27, v22 + v_mfma_f32_32x32x8_f16 a[32:47], v[28:29], v[44:45], a[32:47] + v_add_u32_e32 v22, v10, v22 + v_and_b32_e32 v22, 0xffffffe0, v22 + ds_read_b128 v[46:49], v19 offset:49152 + v_sub_u32_e32 v22, v10, v22 + v_xor_b32_e32 v6, v6, v22 + v_sub_u32_e32 v16, v6, v16 + ds_read_b128 v[50:53], v19 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[26:27], v[46:47], 0 + v_lshlrev_b32_e32 v20, 11, v20 + v_lshl_add_u32 v20, v21, 12, v20 + v_lshl_add_u32 v16, v16, 3, v20 + v_lshl_add_u32 v21, v16, 1, v7 + v_add_u32_e32 v23, 64, v4 + v_lshrrev_b32_e32 v23, 3, v23 + v_sub_u32_e32 v1, v2, v1 + v_mfma_f32_32x32x8_f16 a[112:127], v[28:29], v[48:49], a[112:127] + v_lshlrev_b32_e32 v24, 3, v12 + v_sub_u32_e32 v10, v10, v24 + v_ashrrev_i32_e32 v24, 31, v10 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v10, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v10, v10, v24 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[26:27], v[50:51], 0 + v_xor_b32_e32 v24, v23, v10 + v_sub_u32_e32 v6, v24, v6 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v12, 11, v12 + v_sub_u32_e32 v1, v1, v12 + v_lshl_add_u32 v6, v6, 3, v1 + v_lshl_add_u32 v12, v6, 1, v21 + v_mfma_f32_32x32x8_f16 a[208:223], v[28:29], v[52:53], a[208:223] + ds_read_b128 v[30:33], v12 + v_xor_b32_e32 v25, v23, v11 + v_sub_u32_e32 v24, v25, v24 + v_lshl_add_u32 v24, v24, 3, v13 + v_lshl_add_u32 v12, v24, 1, v12 + ds_read_b128 v[54:57], v12 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[30:31], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[32:33], v[36:37], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[30:31], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[32:33], v[44:45], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[30:31], v[46:47], 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[32:33], v[48:49], a[160:175] + v_xor_b32_e32 v26, v23, v15 + v_sub_u32_e32 v25, v26, v25 + v_lshl_add_u32 v25, v25, 3, v8 + v_lshl_add_u32 v12, v25, 1, v12 + v_xor_b32_e32 v23, v23, v22 + v_sub_u32_e32 v26, v23, v26 + v_lshl_add_u32 v26, v26, 3, v20 + v_mfma_f32_32x32x8_f16 a[144:159], v[30:31], v[50:51], 0 + v_lshl_add_u32 v27, v26, 1, v12 + v_add_u32_e32 v28, 0x80, v4 + v_lshrrev_b32_e32 v28, 3, v28 + v_xor_b32_e32 v29, v28, v10 + v_sub_u32_e32 v23, v29, v23 + v_lshl_add_u32 v23, v23, 3, v1 + v_lshl_add_u32 v30, v23, 1, v27 + v_mfma_f32_32x32x8_f16 a[144:159], v[32:33], v[52:53], a[144:159] + ds_read_b128 v[58:61], v30 + v_xor_b32_e32 v31, v28, v11 + v_sub_u32_e32 v29, v31, v29 + v_lshl_add_u32 v29, v29, 3, v13 + v_lshl_add_u32 v30, v29, 1, v30 + ds_read_b128 v[62:65], v30 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[58:59], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[60:61], v[36:37], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[58:59], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[60:61], v[44:45], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[58:59], v[46:47], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[60:61], v[48:49], a[80:95] + v_xor_b32_e32 v32, v28, v15 + v_sub_u32_e32 v31, v32, v31 + v_lshl_add_u32 v31, v31, 3, v8 + v_lshl_add_u32 v30, v31, 1, v30 + v_xor_b32_e32 v28, v28, v22 + v_sub_u32_e32 v32, v28, v32 + v_lshl_add_u32 v32, v32, 3, v20 + v_mfma_f32_32x32x8_f16 a[64:79], v[58:59], v[50:51], 0 + v_lshl_add_u32 v33, v32, 1, v30 + v_add_u32_e32 v4, 0xc0, v4 + v_lshrrev_b32_e32 v4, 3, v4 + v_xor_b32_e32 v10, v4, v10 + v_sub_u32_e32 v28, v10, v28 + v_lshl_add_u32 v1, v28, 3, v1 + v_lshl_add_u32 v28, v1, 1, v33 + v_mfma_f32_32x32x8_f16 a[64:79], v[60:61], v[52:53], a[64:79] + ds_read_b128 v[58:61], v28 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[58:59], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[60:61], v[36:37], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[58:59], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[60:61], v[44:45], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[58:59], v[46:47], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[60:61], v[48:49], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[58:59], v[50:51], 0 + v_add_u32_e32 v34, 2, v2 + v_mfma_f32_32x32x8_f16 a[240:255], v[60:61], v[52:53], a[240:255] + v_xor_b32_e32 v34, v34, v69 + v_lshl_or_b32 v35, v34, 4, v14 + ds_read_b128 v[42:45], v35 offset:32768 + v_or_b32_e32 v35, 4, v2 + v_xor_b32_e32 v35, v35, v69 + v_lshl_or_b32 v14, v35, 4, v14 + ds_read_b128 v[46:49], v14 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[38:39], v[42:43], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[40:41], v[44:45], a[0:15] + v_sub_u32_e32 v14, v34, v0 + v_lshl_add_u32 v14, v14, 4, v19 + ds_read_b128 v[50:53], v14 offset:40960 + ds_read_b128 v[58:61], v14 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[38:39], v[50:51], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[40:41], v[52:53], a[32:47] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[38:39], v[58:59], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[40:41], v[60:61], a[112:127] + ds_read_b128 v[74:77], v14 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[38:39], v[74:75], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[40:41], v[76:77], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[54:55], v[42:43], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[56:57], v[44:45], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[54:55], v[50:51], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[56:57], v[52:53], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[54:55], v[58:59], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[56:57], v[60:61], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[54:55], v[74:75], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[56:57], v[76:77], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[62:63], v[42:43], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[64:65], v[44:45], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[62:63], v[50:51], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[64:65], v[52:53], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[62:63], v[58:59], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[64:65], v[60:61], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[62:63], v[74:75], a[64:79] + v_xor_b32_e32 v11, v4, v11 + v_sub_u32_e32 v10, v11, v10 + v_lshl_add_u32 v10, v10, 3, v13 + v_lshl_add_u32 v13, v10, 1, v28 + v_mfma_f32_32x32x8_f16 a[64:79], v[64:65], v[76:77], a[64:79] + ds_read_b128 v[36:39], v13 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[36:37], v[42:43], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[38:39], v[44:45], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[36:37], v[50:51], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[38:39], v[52:53], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[36:37], v[58:59], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[38:39], v[60:61], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[36:37], v[74:75], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[38:39], v[76:77], a[240:255] + ds_read_b128 v[36:39], v7 + ds_read_b128 v[40:43], v21 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[36:37], v[46:47], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[38:39], v[48:49], a[0:15] + v_sub_u32_e32 v7, v35, v0 + v_lshl_add_u32 v7, v7, 4, v19 + ds_read_b128 v[50:53], v7 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[36:37], v[50:51], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[38:39], v[52:53], a[32:47] + ds_read_b128 v[54:57], v7 offset:49152 + ds_read_b128 v[58:61], v7 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[36:37], v[54:55], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[38:39], v[56:57], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[36:37], v[58:59], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[38:39], v[60:61], a[208:223] + ds_read_b128 v[34:37], v12 + ds_read_b128 v[62:65], v27 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[34:35], v[46:47], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[36:37], v[48:49], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[34:35], v[50:51], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[36:37], v[52:53], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[34:35], v[54:55], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[36:37], v[56:57], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[34:35], v[58:59], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[36:37], v[60:61], a[144:159] + ds_read_b128 v[34:37], v30 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[34:35], v[46:47], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[36:37], v[48:49], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[34:35], v[50:51], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[36:37], v[52:53], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[34:35], v[54:55], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[36:37], v[56:57], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[34:35], v[58:59], a[64:79] + v_xor_b32_e32 v7, v4, v15 + v_sub_u32_e32 v11, v7, v11 + v_lshl_add_u32 v8, v11, 3, v8 + v_lshl_add_u32 v11, v8, 1, v13 + v_mfma_f32_32x32x8_f16 a[64:79], v[36:37], v[60:61], a[64:79] + ds_read_b128 v[12:15], v11 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[12:13], v[46:47], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[14:15], v[48:49], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[12:13], v[50:51], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[14:15], v[52:53], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[12:13], v[54:55], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[14:15], v[56:57], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[12:13], v[58:59], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[14:15], v[60:61], a[240:255] + ds_read_b128 v[12:15], v18 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[40:41], v[12:13], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[42:43], v[14:15], a[0:15] + v_sub_u32_e32 v0, v17, v0 + v_lshl_add_u32 v0, v0, 4, v19 + ds_read_b128 v[34:37], v0 offset:40960 + ds_read_b128 v[44:47], v0 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[40:41], v[34:35], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[42:43], v[36:37], a[32:47] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[40:41], v[44:45], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[42:43], v[46:47], a[112:127] + ds_read_b128 v[48:51], v0 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[40:41], v[48:49], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[42:43], v[50:51], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[62:63], v[12:13], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[64:65], v[14:15], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[62:63], v[34:35], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[64:65], v[36:37], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[62:63], v[44:45], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[64:65], v[46:47], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[62:63], v[48:49], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[64:65], v[50:51], a[144:159] + ds_read_b128 v[38:41], v33 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[38:39], v[12:13], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[40:41], v[14:15], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[38:39], v[34:35], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[40:41], v[36:37], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[38:39], v[44:45], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[40:41], v[46:47], a[80:95] + v_add3_u32 v0, v9, v5, v16 + v_add3_u32 v0, v6, v0, v24 + v_add3_u32 v0, v25, v0, v26 + v_add3_u32 v0, v23, v0, v29 + v_add3_u32 v0, v31, v0, v32 + v_mfma_f32_32x32x8_f16 a[64:79], v[38:39], v[48:49], a[64:79] + v_add3_u32 v0, v1, v0, v10 + v_xor_b32_e32 v1, v4, v22 + v_sub_u32_e32 v1, v1, v7 + v_lshlrev_b32_e32 v1, 4, v1 + v_lshlrev_b32_e32 v4, 1, v20 + v_add_lshl_u32 v0, v8, v0, 1 + v_add3_u32 v0, v1, v4, v0 + v_mfma_f32_32x32x8_f16 a[64:79], v[40:41], v[50:51], a[64:79] + ds_read_b128 v[4:7], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[12:13], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[6:7], v[14:15], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[34:35], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[6:7], v[36:37], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[44:45], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[6:7], v[46:47], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[48:49], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[6:7], v[50:51], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB1_3 + s_branch .LBB1_10 +.LBB1_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr63 + ; implicit-def: $agpr111 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr143 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr127 + ; implicit-def: $agpr47 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB1_3: + v_readfirstlane_b32 s15, v227 + s_lshr_b32 s24, s15, 2 + s_and_b32 s23, s24, 0x3ffffff0 + v_lshl_or_b32 v0, v72, 3, s18 + v_lshlrev_b32_e32 v1, 3, v2 + v_add_u32_e32 v4, s23, v1 + v_mad_u64_u32 v[66:67], s[10:11], v4, s7, v[0:1] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v4, s7, v66 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v4 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v5, 1, v0 + buffer_load_dwordx4 v[18:21], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[22:25], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v5, 1, v0 + buffer_load_dwordx4 v[26:29], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[30:33], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[34:37], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 12, v2 + v_lshlrev_b32_e32 v68, 3, v69 + v_and_b32_e32 v103, 0x78, v226 + v_xor_b32_e32 v4, v2, v69 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + v_lshl_or_b32 v0, v69, 8, v0 + s_and_b32 s25, s15, 0xffffffc0 + s_lshr_b32 s26, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s24, s24, 0x3fffffe0 + v_add_u32_e32 v67, s25, v103 + v_and_or_b32 v5, s26, 32, v72 + v_or_b32_e32 v6, s24, v72 + v_add_u32_e32 v8, s19, v67 + v_lshlrev_b32_e32 v5, 6, v5 + v_lshrrev_b32_e32 v7, 3, v6 + v_mad_u64_u32 v[70:71], s[24:25], v8, s20, v[68:69] + v_xor_b32_e32 v9, v7, v69 + v_lshlrev_b32_e32 v50, 1, v70 + v_add_u32_e32 v42, s20, v70 + v_lshl_add_u32 v8, v9, 3, v0 + v_lshlrev_b32_e32 v0, 1, v42 + v_add_u32_e32 v51, s20, v42 + buffer_load_dwordx4 v[42:45], v50, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v0, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v51 + v_add_u32_e32 v50, s20, v51 + v_lshlrev_b32_e32 v58, 1, v50 + v_add_u32_e32 v59, s20, v50 + buffer_load_dwordx4 v[50:53], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[54:57], v58, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v59 + v_add_u32_e32 v58, s20, v59 + v_lshlrev_b32_e32 v71, 1, v58 + v_add_u32_e32 v73, s20, v58 + buffer_load_dwordx4 v[58:61], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v71, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v73 + v_add_lshl_u32 v71, v73, s20, 1 + buffer_load_dwordx4 v[74:77], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[78:81], v71, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v82, v10, v14, s21 + v_perm_b32 v86, v10, v14, s22 + v_perm_b32 v90, v11, v15, s21 + v_perm_b32 v94, v11, v15, s22 + v_perm_b32 v98, v12, v16, s21 + s_waitcnt vmcnt(12) + v_perm_b32 v83, v18, v22, s21 + v_perm_b32 v87, v18, v22, s22 + v_perm_b32 v91, v19, v23, s21 + v_perm_b32 v95, v19, v23, s22 + s_waitcnt vmcnt(10) + v_perm_b32 v84, v26, v30, s21 + v_perm_b32 v88, v26, v30, s22 + v_perm_b32 v92, v27, v31, s21 + v_perm_b32 v96, v27, v31, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v85, v34, v38, s21 + v_perm_b32 v89, v34, v38, s22 + v_perm_b32 v93, v35, v39, s21 + v_perm_b32 v97, v35, v39, s22 + v_perm_b32 v106, v12, v16, s22 + v_perm_b32 v99, v20, v24, s21 + v_perm_b32 v107, v20, v24, s22 + v_perm_b32 v100, v28, v32, s21 + v_perm_b32 v108, v28, v32, s22 + v_perm_b32 v101, v36, v40, s21 + v_perm_b32 v109, v36, v40, s22 + v_perm_b32 v10, v13, v17, s21 + v_perm_b32 v14, v13, v17, s22 + v_perm_b32 v11, v21, v25, s21 + v_perm_b32 v15, v21, v25, s22 + v_perm_b32 v12, v29, v33, s21 + v_perm_b32 v16, v29, v33, s22 + v_perm_b32 v13, v37, v41, s21 + v_perm_b32 v17, v37, v41, s22 + v_and_b32_e32 v104, 24, v3 + v_add_u32_e32 v0, s23, v104 + v_lshrrev_b32_e32 v3, 2, v0 + v_and_b32_e32 v3, 24, v3 + v_xor_b32_e32 v18, v3, v72 + v_lshlrev_b32_e32 v19, 9, v0 + v_and_b32_e32 v19, 0x3000, v19 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v0, 0xfffff800, v0 + v_add_u32_e32 v0, v0, v19 + v_lshl_or_b32 v0, v18, 3, v0 + v_lshlrev_b32_e32 v19, 1, v0 + ds_write_b128 v19, v[82:85] + v_or_b32_e32 v20, 1, v3 + v_xor_b32_e32 v20, v20, v72 + v_sub_u32_e32 v18, v20, v18 + v_lshlrev_b32_e32 v21, 3, v18 + v_or_b32_e32 v22, 2, v3 + v_xor_b32_e32 v22, v22, v72 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v23, 3, v20 + v_add3_u32 v0, v21, v0, v23 + v_lshl_add_u32 v18, v18, 4, v19 + ds_write_b128 v18, v[86:89] offset:512 + v_or_b32_e32 v19, 3, v3 + v_xor_b32_e32 v19, v19, v72 + v_sub_u32_e32 v21, v19, v22 + v_lshlrev_b32_e32 v22, 3, v21 + v_or_b32_e32 v23, 4, v3 + v_xor_b32_e32 v23, v23, v72 + v_sub_u32_e32 v19, v23, v19 + v_lshlrev_b32_e32 v24, 3, v19 + v_add3_u32 v0, v0, v22, v24 + v_lshlrev_b32_e32 v20, 4, v20 + s_movk_i32 s21, 0x200 + v_add3_u32 v18, v18, s21, v20 + ds_write_b128 v18, v[90:93] offset:512 + v_or_b32_e32 v20, 5, v3 + v_xor_b32_e32 v20, v20, v72 + v_sub_u32_e32 v22, v20, v23 + v_lshlrev_b32_e32 v23, 3, v22 + v_or_b32_e32 v24, 6, v3 + v_xor_b32_e32 v24, v24, v72 + v_sub_u32_e32 v20, v24, v20 + v_lshlrev_b32_e32 v25, 3, v20 + v_add3_u32 v0, v0, v23, v25 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v18, v18, s21, v21 + ds_write_b128 v18, v[94:97] offset:512 + v_or_b32_e32 v3, 7, v3 + v_xor_b32_e32 v3, v3, v72 + v_sub_u32_e32 v3, v3, v24 + v_lshlrev_b32_e32 v3, 4, v3 + v_lshl_add_u32 v0, v0, 1, v3 + v_lshlrev_b32_e32 v3, 4, v19 + v_add3_u32 v3, v18, s21, v3 + ds_write_b128 v3, v[98:101] offset:512 + v_lshlrev_b32_e32 v18, 4, v22 + v_add3_u32 v3, v3, s21, v18 + ds_write_b128 v3, v[106:109] offset:512 + v_lshlrev_b32_e32 v18, 4, v20 + v_add3_u32 v3, v3, s21, v18 + ds_write_b128 v3, v[10:13] offset:512 + ds_write_b128 v0, v[14:17] offset:3584 + v_lshl_or_b32 v0, v67, 6, v68 + v_lshlrev_b32_e32 v3, 1, v0 + s_waitcnt vmcnt(7) + ds_write_b128 v3, v[42:45] offset:32768 + v_or_b32_e32 v10, 1, v67 + v_ashrrev_i32_e32 v11, 31, v67 + v_lshrrev_b32_e32 v11, 29, v11 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v12, v10, v69 + v_lshl_add_u32 v0, v12, 3, v0 + v_lshl_add_u32 v3, v12, 4, v3 + s_waitcnt vmcnt(6) + ds_write_b128 v3, v[46:49] offset:32896 + v_or_b32_e32 v3, 2, v67 + v_add_u32_e32 v12, v3, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v3, v3, v12 + v_xor_b32_e32 v3, v3, v69 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v0, v0, v10, 64 + v_lshlrev_b32_e32 v10, 1, v0 + s_waitcnt vmcnt(5) + ds_write_b128 v10, v[50:53] offset:32896 + v_or_b32_e32 v10, 3, v67 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v3, v10, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v0, v0, v3, 64 + v_lshlrev_b32_e32 v3, 1, v0 + s_waitcnt vmcnt(4) + ds_write_b128 v3, v[54:57] offset:32896 + v_or_b32_e32 v3, 4, v67 + v_add_u32_e32 v12, v3, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v3, v3, v12 + v_xor_b32_e32 v3, v3, v69 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v0, v0, v10, 64 + v_lshlrev_b32_e32 v10, 1, v0 + s_waitcnt vmcnt(3) + ds_write_b128 v10, v[58:61] offset:32896 + v_or_b32_e32 v10, 5, v67 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v10, v10, v12 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v3, v10, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v0, v0, v3, 64 + v_lshlrev_b32_e32 v3, 1, v0 + s_waitcnt vmcnt(2) + ds_write_b128 v3, v[62:65] offset:32896 + v_or_b32_e32 v3, 6, v67 + v_add_u32_e32 v12, v3, v11 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v3, v3, v12 + v_xor_b32_e32 v3, v3, v69 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add_lshl_u32 v0, v0, v10, 1 + v_or_b32_e32 v10, 7, v67 + v_add_u32_e32 v11, v10, v11 + v_and_b32_e32 v11, 0xffffff8, v11 + v_sub_u32_e32 v10, v10, v11 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v3, v10, v3 + v_lshl_add_u32 v3, v3, 4, v0 + s_waitcnt vmcnt(1) + ds_write_b128 v0, v[74:77] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v3, v[78:81] offset:33152 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v12, 16, v1 + v_add_u32_e32 v1, 48, v1 + v_add_u32_e32 v0, 64, v6 + v_add_u32_e32 v11, 2, v2 + v_or_b32_e32 v10, 4, v2 + v_add_u32_e32 v3, 6, v2 + s_cbranch_vccnz .LBB1_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit194.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_lshrrev_b32_e32 v13, 5, v12 + v_bfe_u32 v14, v12, 3, 2 + v_lshl_or_b32 v15, v13, 3, v69 + v_xor_b32_e32 v16, v7, v15 + v_sub_u32_e32 v17, v16, v9 + v_lshlrev_b32_e32 v18, 11, v13 + v_lshlrev_b32_e32 v17, 3, v17 + v_sub_u32_e32 v19, v14, v2 + v_lshl_or_b32 v18, v19, 12, v18 + v_add3_u32 v75, v8, v18, v17 + v_xor_b32_e32 v13, 1, v13 + v_sub_u32_e32 v14, v2, v14 + v_lshl_add_u32 v17, v13, 3, v15 + v_xor_b32_e32 v19, v7, v17 + v_sub_u32_e32 v16, v19, v16 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshl_or_b32 v13, v14, 12, v13 + v_add3_u32 v76, v16, v13, v75 + v_lshrrev_b32_e32 v14, 5, v1 + v_add_u32_e32 v16, -1, v14 + v_bfe_u32 v20, v1, 3, 2 + v_sub_u32_e32 v21, v20, v2 + v_lshl_add_u32 v22, v16, 3, v17 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshrrev_b32_e32 v23, 27, v23 + v_add_u32_e32 v23, v22, v23 + v_and_b32_e32 v23, 0xffffffe0, v23 + v_sub_u32_e32 v23, v22, v23 + v_xor_b32_e32 v24, v7, v23 + v_sub_u32_e32 v19, v24, v19 + v_lshlrev_b32_e32 v16, 11, v16 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshl_add_u32 v16, v21, 12, v16 + v_add3_u32 v67, v19, v16, v76 + v_lshrrev_b32_e32 v19, 3, v0 + v_sub_u32_e32 v20, v2, v20 + v_lshlrev_b32_e32 v21, 3, v14 + v_sub_u32_e32 v21, v22, v21 + v_ashrrev_i32_e32 v22, 31, v21 + v_lshrrev_b32_e32 v22, 27, v22 + v_add_u32_e32 v22, v21, v22 + v_and_b32_e32 v22, 0xffffffe0, v22 + v_sub_u32_e32 v21, v21, v22 + v_xor_b32_e32 v22, v19, v21 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_lshlrev_b32_e32 v20, 12, v20 + v_lshlrev_b32_e32 v14, 11, v14 + v_sub_u32_e32 v14, v20, v14 + v_add3_u32 v94, v24, v14, v67 + v_xor_b32_e32 v20, v19, v15 + v_sub_u32_e32 v22, v20, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v77, v22, v18, v94 + v_xor_b32_e32 v22, v19, v17 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v78, v20, v13, v77 + v_xor_b32_e32 v19, v19, v23 + v_sub_u32_e32 v20, v19, v22 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v71, v20, v16, v78 + v_add_u32_e32 v20, 0x80, v6 + v_lshrrev_b32_e32 v20, 3, v20 + v_xor_b32_e32 v22, v20, v21 + v_sub_u32_e32 v19, v22, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_add3_u32 v93, v19, v14, v71 + v_xor_b32_e32 v19, v20, v15 + v_sub_u32_e32 v22, v19, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v79, v22, v18, v93 + v_xor_b32_e32 v22, v20, v17 + v_sub_u32_e32 v19, v22, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_add3_u32 v80, v19, v13, v79 + v_xor_b32_e32 v19, v20, v23 + v_sub_u32_e32 v20, v19, v22 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v73, v20, v16, v80 + v_add_u32_e32 v20, 0xc0, v6 + v_lshrrev_b32_e32 v20, 3, v20 + v_xor_b32_e32 v21, v20, v21 + v_sub_u32_e32 v19, v21, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_add3_u32 v92, v19, v14, v73 + v_xor_b32_e32 v14, v20, v15 + v_sub_u32_e32 v15, v14, v21 + v_lshlrev_b32_e32 v15, 3, v15 + v_add3_u32 v81, v15, v18, v92 + v_xor_b32_e32 v15, v20, v17 + v_sub_u32_e32 v14, v15, v14 + v_lshlrev_b32_e32 v14, 3, v14 + v_add3_u32 v82, v14, v13, v81 + v_xor_b32_e32 v13, v20, v23 + v_sub_u32_e32 v13, v13, v15 + v_lshlrev_b32_e32 v13, 3, v13 + v_add3_u32 v74, v13, v16, v82 + v_xor_b32_e32 v13, v11, v69 + v_lshl_add_u32 v91, v13, 3, v5 + v_xor_b32_e32 v14, v10, v69 + v_lshl_add_u32 v83, v14, 3, v5 + v_xor_b32_e32 v15, v3, v69 + v_lshl_add_u32 v84, v15, 3, v5 + v_sub_u32_e32 v16, v4, v15 + v_mov_b32_e32 v17, 0x1000 + v_lshl_add_u32 v16, v16, 3, v17 + v_add_u32_e32 v97, v84, v16 + v_sub_u32_e32 v13, v13, v4 + v_lshlrev_b32_e32 v13, 3, v13 + v_add_u32_e32 v100, v97, v13 + v_sub_u32_e32 v14, v14, v4 + v_lshlrev_b32_e32 v14, 3, v14 + v_add_u32_e32 v85, v97, v14 + v_sub_u32_e32 v15, v15, v4 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v86, v97, v15 + v_add_u32_e32 v98, v86, v16 + v_add_u32_e32 v99, v98, v13 + v_add_u32_e32 v87, v98, v14 + v_add_u32_e32 v88, v98, v15 + v_add_u32_e32 v95, v88, v16 + v_add_u32_e32 v96, v95, v13 + v_add_u32_e32 v89, v95, v14 + v_add_u32_e32 v90, v95, v15 + s_mov_b64 s[2:3], 0 + s_branch .LBB1_6 +.LBB1_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr90 +.LBB1_6: ; %Flow42 + v_lshl_or_b32 v13, v4, 3, v5 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a96, 0 + v_lshlrev_b32_e32 v102, 1, v8 + v_lshlrev_b32_e32 v101, 1, v13 + s_cbranch_vccnz .LBB1_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i529.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_lshrrev_b32_e32 v13, 5, v12 + v_bfe_u32 v12, v12, 3, 2 + v_lshl_or_b32 v14, v13, 3, v69 + v_xor_b32_e32 v15, v7, v14 + v_sub_u32_e32 v9, v15, v9 + v_lshlrev_b32_e32 v16, 11, v13 + v_lshlrev_b32_e32 v9, 3, v9 + v_sub_u32_e32 v17, v12, v2 + v_lshl_or_b32 v16, v17, 12, v16 + v_add3_u32 v75, v8, v16, v9 + v_xor_b32_e32 v8, 1, v13 + v_sub_u32_e32 v9, v2, v12 + v_lshl_add_u32 v12, v8, 3, v14 + v_xor_b32_e32 v13, v7, v12 + v_sub_u32_e32 v15, v13, v15 + v_lshlrev_b32_e32 v8, 11, v8 + v_lshlrev_b32_e32 v15, 3, v15 + v_lshl_or_b32 v8, v9, 12, v8 + v_add3_u32 v76, v15, v8, v75 + v_lshrrev_b32_e32 v9, 5, v1 + v_add_u32_e32 v15, -1, v9 + v_bfe_u32 v1, v1, 3, 2 + v_sub_u32_e32 v17, v1, v2 + v_lshl_add_u32 v18, v15, 3, v12 + v_ashrrev_i32_e32 v19, 31, v18 + v_lshrrev_b32_e32 v19, 27, v19 + v_add_u32_e32 v19, v18, v19 + v_and_b32_e32 v19, 0xffffffe0, v19 + v_sub_u32_e32 v19, v18, v19 + v_xor_b32_e32 v7, v7, v19 + v_sub_u32_e32 v13, v7, v13 + v_lshlrev_b32_e32 v15, 11, v15 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshl_add_u32 v15, v17, 12, v15 + v_add3_u32 v67, v13, v15, v76 + v_lshrrev_b32_e32 v0, 3, v0 + v_sub_u32_e32 v1, v2, v1 + v_lshlrev_b32_e32 v2, 3, v9 + v_sub_u32_e32 v2, v18, v2 + v_ashrrev_i32_e32 v13, 31, v2 + v_lshrrev_b32_e32 v13, 27, v13 + v_add_u32_e32 v13, v2, v13 + v_and_b32_e32 v13, 0xffffffe0, v13 + v_sub_u32_e32 v2, v2, v13 + v_xor_b32_e32 v13, v0, v2 + v_sub_u32_e32 v7, v13, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v9, 11, v9 + v_sub_u32_e32 v1, v1, v9 + v_add3_u32 v94, v7, v1, v67 + v_xor_b32_e32 v7, v0, v14 + v_sub_u32_e32 v9, v7, v13 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v77, v9, v16, v94 + v_xor_b32_e32 v9, v0, v12 + v_sub_u32_e32 v7, v9, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v78, v7, v8, v77 + v_xor_b32_e32 v0, v0, v19 + v_sub_u32_e32 v7, v0, v9 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v71, v7, v15, v78 + v_add_u32_e32 v7, 0x80, v6 + v_lshrrev_b32_e32 v7, 3, v7 + v_xor_b32_e32 v9, v7, v2 + v_sub_u32_e32 v0, v9, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v93, v0, v1, v71 + v_xor_b32_e32 v0, v7, v14 + v_sub_u32_e32 v9, v0, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v79, v9, v16, v93 + v_xor_b32_e32 v9, v7, v12 + v_sub_u32_e32 v0, v9, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v80, v0, v8, v79 + v_xor_b32_e32 v0, v7, v19 + v_sub_u32_e32 v7, v0, v9 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v73, v7, v15, v80 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 3, v6 + v_xor_b32_e32 v2, v6, v2 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v92, v0, v1, v73 + v_xor_b32_e32 v0, v6, v14 + v_sub_u32_e32 v1, v0, v2 + v_lshlrev_b32_e32 v1, 3, v1 + v_add3_u32 v81, v1, v16, v92 + v_xor_b32_e32 v1, v6, v12 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v82, v0, v8, v81 + v_xor_b32_e32 v0, v6, v19 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v74, v0, v15, v82 + v_xor_b32_e32 v0, v11, v69 + v_lshl_add_u32 v91, v0, 3, v5 + v_xor_b32_e32 v1, v10, v69 + v_lshl_add_u32 v83, v1, 3, v5 + v_xor_b32_e32 v2, v3, v69 + v_lshl_add_u32 v84, v2, 3, v5 + v_sub_u32_e32 v3, v4, v2 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v5, 0x1000, v3 + v_add_u32_e32 v97, v84, v5 + v_add_u32_e32 v3, v84, v3 + v_lshlrev_b32_e32 v105, 1, v3 + v_sub_u32_e32 v0, v0, v4 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v100, v97, v0 + v_add_lshl_u32 v106, v3, v0, 1 + v_sub_u32_e32 v1, v1, v4 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v85, v97, v1 + v_add_lshl_u32 v107, v3, v1, 1 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v86, v97, v2 + v_add_u32_e32 v3, v3, v2 + v_lshlrev_b32_e32 v108, 1, v3 + v_add_u32_e32 v98, v86, v5 + v_add_lshl_u32 v109, v3, v5, 1 + v_add_u32_e32 v99, v98, v0 + v_add_u32_e32 v87, v98, v1 + v_add_u32_e32 v88, v98, v2 + v_add_u32_e32 v95, v88, v5 + v_add_u32_e32 v96, v95, v0 + v_add_u32_e32 v89, v95, v1 + v_add_u32_e32 v90, v95, v2 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + s_mov_b32 s6, 0x1000504 + s_mov_b32 s21, 0x3020706 + s_movk_i32 s22, 0x200 +.LBB1_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i529.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v70, 64, v70 + v_add_u32_e32 v66, s2, v66 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v1, s7, v66 + v_lshlrev_b32_e32 v2, 1, v70 + v_add_u32_e32 v6, s20, v70 + v_lshlrev_b32_e32 v7, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[2:5], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v8, 1, v6 + v_add_u32_e32 v10, s20, v6 + buffer_load_dwordx4 v[34:37], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v7, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[6:9], v8, s[12:15], 0 offen + v_lshlrev_b32_e32 v11, 1, v10 + v_add_u32_e32 v14, s20, v10 + v_lshlrev_b32_e32 v15, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[10:13], v11, s[12:15], 0 offen + v_lshlrev_b32_e32 v16, 1, v14 + v_add_u32_e32 v18, s20, v14 + buffer_load_dwordx4 v[42:45], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[46:49], v15, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[14:17], v16, s[12:15], 0 offen + v_lshlrev_b32_e32 v19, 1, v18 + v_add_u32_e32 v22, s20, v18 + v_lshlrev_b32_e32 v23, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[18:21], v19, s[12:15], 0 offen + v_lshlrev_b32_e32 v24, 1, v22 + v_add_u32_e32 v26, s20, v22 + buffer_load_dwordx4 v[54:57], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v23, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_lshl_u32 v1, v1, s7, 1 + buffer_load_dwordx4 v[22:25], v24, s[12:15], 0 offen + v_lshlrev_b32_e32 v27, 1, v26 + v_add_lshl_u32 v30, v26, s20, 1 + buffer_load_dwordx4 v[50:53], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[58:61], v1, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[26:29], v27, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[30:33], v30, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[114:117], v102 + ds_read_b128 v[110:113], v101 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[114:115], v[110:111], a[96:111] + ds_read_b128 v[118:121], v105 offset:40960 + ds_read_b128 v[122:125], v106 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[114:115], v[118:119], a[80:95] + ds_read_b128 v[126:129], v109 offset:40960 + v_lshlrev_b32_e32 v0, 1, v100 + ds_read_b128 v[130:133], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[114:115], v[126:127], a[64:79] + v_lshlrev_b32_e32 v0, 1, v98 + ds_read_b128 v[134:137], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v99 + ds_read_b128 v[138:141], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[114:115], v[134:135], a[128:143] + v_lshlrev_b32_e32 v0, 1, v94 + ds_read_b128 v[142:145], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[142:143], v[110:111], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[142:143], v[118:119], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[142:143], v[126:127], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[142:143], v[134:135], a[176:191] + v_lshlrev_b32_e32 v0, 1, v93 + ds_read_b128 v[146:149], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[110:111], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[118:119], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[126:127], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[134:135], a[240:255] + v_lshlrev_b32_e32 v0, 1, v92 + ds_read_b128 v[150:153], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[110:111], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[118:119], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[126:127], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[134:135], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[116:117], v[112:113], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[116:117], v[120:121], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[116:117], v[128:129], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[116:117], v[136:137], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[144:145], v[112:113], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[144:145], v[120:121], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[144:145], v[128:129], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[144:145], v[136:137], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[112:113], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[120:121], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[128:129], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[136:137], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[112:113], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[120:121], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[128:129], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[136:137], a[48:63] + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[110:113], v0 + v_lshlrev_b32_e32 v0, 1, v91 + ds_read_b128 v[114:117], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[126:129], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[110:111], v[114:115], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[110:111], v[122:123], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[110:111], v[130:131], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[110:111], v[138:139], a[128:143] + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[118:121], v0 + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[134:137], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[118:119], v[114:115], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[118:119], v[122:123], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[118:119], v[130:131], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[118:119], v[138:139], a[176:191] + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[142:145], v0 + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[146:149], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[114:115], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[122:123], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[130:131], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[142:143], v[138:139], a[240:255] + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[150:153], v0 + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[154:157], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[114:115], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[122:123], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[130:131], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[138:139], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[112:113], v[116:117], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[112:113], v[124:125], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[112:113], v[132:133], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[112:113], v[140:141], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[116:117], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[120:121], v[124:125], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[120:121], v[132:133], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[120:121], v[140:141], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[144:145], v[116:117], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[144:145], v[124:125], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[144:145], v[132:133], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[140:141], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[116:117], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[124:125], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[132:133], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[140:141], a[48:63] + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[130:133], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[122:125], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[126:127], v[130:131], a[96:111] + ds_read_b128 v[138:141], v107 offset:40960 + ds_read_b128 v[118:121], v108 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[126:127], v[138:139], a[80:95] + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[142:145], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[114:117], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[142:143], a[64:79] + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[150:153], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[110:113], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[126:127], v[150:151], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[134:135], v[130:131], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[134:135], v[138:139], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[134:135], v[142:143], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[134:135], v[150:151], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[130:131], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[138:139], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[142:143], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[150:151], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[154:155], v[130:131], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[138:139], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[154:155], v[142:143], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[154:155], v[150:151], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[128:129], v[132:133], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[128:129], v[140:141], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[128:129], v[144:145], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[152:153], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[136:137], v[132:133], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[136:137], v[140:141], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[136:137], v[144:145], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[136:137], v[152:153], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[132:133], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[140:141], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[144:145], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[152:153], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[156:157], v[132:133], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[156:157], v[140:141], a[32:47] + v_mfma_f32_32x32x8_f16 a[0:15], v[156:157], v[144:145], a[0:15] + v_mfma_f32_32x32x8_f16 a[48:63], v[156:157], v[152:153], a[48:63] + v_lshlrev_b32_e32 v0, 1, v67 + ds_read_b128 v[126:129], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[126:127], v[122:123], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[126:127], v[118:119], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[126:127], v[110:111], a[128:143] + v_lshlrev_b32_e32 v0, 1, v71 + ds_read_b128 v[142:145], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[142:143], v[122:123], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[142:143], v[118:119], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[142:143], v[114:115], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[142:143], v[110:111], a[176:191] + v_lshlrev_b32_e32 v0, 1, v73 + ds_read_b128 v[146:149], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[122:123], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[118:119], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[114:115], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[110:111], a[240:255] + v_lshlrev_b32_e32 v0, 1, v74 + ds_read_b128 v[150:153], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[122:123], a[16:31] + s_add_i32 s23, s3, -1 + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[118:119], a[32:47] + v_readfirstlane_b32 s24, v227 + s_lshr_b32 s25, s24, 2 + s_andn2_b32 s24, s24, 63 + s_and_b32 s25, s25, 0x3ffffff0 + v_add_u32_e32 v0, s24, v103 + v_add_u32_e32 v1, s25, v104 + v_lshl_or_b32 v118, v0, 6, v68 + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[114:115], a[0:15] + v_or_b32_e32 v114, 1, v0 + v_ashrrev_i32_e32 v115, 31, v0 + v_or_b32_e32 v119, 2, v0 + v_or_b32_e32 v122, 3, v0 + v_or_b32_e32 v123, 4, v0 + v_or_b32_e32 v126, 5, v0 + v_or_b32_e32 v127, 6, v0 + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[110:111], a[48:63] + v_or_b32_e32 v0, 7, v0 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s23 + v_lshrrev_b32_e32 v110, 2, v1 + v_lshlrev_b32_e32 v111, 9, v1 + v_lshlrev_b32_e32 v1, 6, v1 + v_lshlrev_b32_e32 v134, 1, v118 + v_mfma_f32_32x32x8_f16 a[96:111], v[128:129], v[124:125], a[96:111] + v_lshrrev_b32_e32 v115, 29, v115 + v_and_b32_e32 v110, 24, v110 + v_and_b32_e32 v111, 0x3000, v111 + v_and_b32_e32 v1, 0xfffff800, v1 + v_add_u32_e32 v130, v114, v115 + v_add_u32_e32 v131, v119, v115 + v_add_u32_e32 v132, v122, v115 + v_mfma_f32_32x32x8_f16 a[80:95], v[128:129], v[120:121], a[80:95] + v_add_u32_e32 v133, v123, v115 + v_add_u32_e32 v135, v126, v115 + v_add_u32_e32 v136, v127, v115 + v_add_u32_e32 v115, v0, v115 + v_xor_b32_e32 v137, v110, v72 + v_add_u32_e32 v1, v1, v111 + v_or_b32_e32 v111, 1, v110 + v_mfma_f32_32x32x8_f16 a[64:79], v[128:129], v[116:117], a[64:79] + v_or_b32_e32 v138, 2, v110 + v_or_b32_e32 v139, 3, v110 + v_or_b32_e32 v140, 4, v110 + v_or_b32_e32 v141, 5, v110 + v_or_b32_e32 v142, 6, v110 + v_or_b32_e32 v110, 7, v110 + v_and_b32_e32 v130, -8, v130 + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[112:113], a[128:143] + v_and_b32_e32 v128, -8, v131 + v_and_b32_e32 v129, -8, v132 + v_and_b32_e32 v131, -8, v133 + v_and_b32_e32 v132, -8, v135 + v_and_b32_e32 v133, -8, v136 + v_and_b32_e32 v115, 0xffffff8, v115 + v_lshl_or_b32 v1, v137, 3, v1 + v_mfma_f32_32x32x8_f16 a[112:127], v[144:145], v[124:125], a[112:127] + v_xor_b32_e32 v111, v111, v72 + v_xor_b32_e32 v135, v138, v72 + v_xor_b32_e32 v136, v139, v72 + v_xor_b32_e32 v138, v140, v72 + v_xor_b32_e32 v139, v141, v72 + v_xor_b32_e32 v140, v142, v72 + v_xor_b32_e32 v110, v110, v72 + v_mfma_f32_32x32x8_f16 a[144:159], v[144:145], v[120:121], a[144:159] + v_sub_u32_e32 v114, v114, v130 + v_sub_u32_e32 v119, v119, v128 + v_sub_u32_e32 v122, v122, v129 + v_sub_u32_e32 v123, v123, v131 + v_sub_u32_e32 v126, v126, v132 + v_sub_u32_e32 v127, v127, v133 + v_sub_u32_e32 v0, v0, v115 + v_mfma_f32_32x32x8_f16 a[160:175], v[144:145], v[116:117], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v141, 1, v1 + v_sub_u32_e32 v115, v111, v137 + v_sub_u32_e32 v111, v135, v111 + v_sub_u32_e32 v128, v136, v135 + v_sub_u32_e32 v129, v138, v136 + v_mfma_f32_32x32x8_f16 a[176:191], v[144:145], v[112:113], a[176:191] + v_sub_u32_e32 v130, v139, v138 + v_sub_u32_e32 v131, v140, v139 + v_sub_u32_e32 v110, v110, v140 + v_xor_b32_e32 v114, v114, v69 + v_xor_b32_e32 v119, v119, v69 + v_xor_b32_e32 v122, v122, v69 + v_xor_b32_e32 v123, v123, v69 + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[124:125], a[192:207] + v_xor_b32_e32 v126, v126, v69 + v_xor_b32_e32 v127, v127, v69 + v_xor_b32_e32 v0, v0, v69 + v_lshlrev_b32_e32 v132, 3, v115 + v_lshlrev_b32_e32 v133, 3, v111 + v_lshl_add_u32 v135, v115, 4, v141 + v_lshlrev_b32_e32 v115, 3, v128 + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[120:121], a[208:223] + v_lshlrev_b32_e32 v136, 3, v129 + v_lshlrev_b32_e32 v111, 4, v111 + v_lshlrev_b32_e32 v137, 3, v130 + v_lshlrev_b32_e32 v138, 3, v131 + v_lshlrev_b32_e32 v128, 4, v128 + v_lshlrev_b32_e32 v110, 4, v110 + v_lshlrev_b32_e32 v129, 4, v129 + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[116:117], a[224:239] + v_lshlrev_b32_e32 v130, 4, v130 + v_lshlrev_b32_e32 v131, 4, v131 + v_sub_u32_e32 v139, v114, v69 + v_sub_u32_e32 v114, v119, v114 + v_sub_u32_e32 v119, v122, v119 + v_sub_u32_e32 v122, v123, v122 + v_sub_u32_e32 v123, v126, v123 + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[112:113], a[240:255] + v_sub_u32_e32 v126, v127, v126 + v_sub_u32_e32 v0, v0, v127 + v_add3_u32 v1, v132, v1, v133 + v_add3_u32 v140, v135, s22, v111 + v_lshl_add_u32 v111, v139, 3, v118 + v_lshl_add_u32 v139, v139, 4, v134 + v_lshlrev_b32_e32 v114, 3, v114 + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[124:125], a[16:31] + v_lshlrev_b32_e32 v118, 3, v119 + v_lshlrev_b32_e32 v119, 3, v122 + v_lshlrev_b32_e32 v122, 3, v123 + v_lshlrev_b32_e32 v123, 3, v126 + v_add3_u32 v1, v1, v115, v136 + v_add3_u32 v136, v140, s22, v128 + v_add3_u32 v111, v111, v114, 64 + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[120:121], a[32:47] + v_add3_u32 v1, v1, v137, v138 + v_add3_u32 v137, v136, s22, v129 + v_lshlrev_b32_e32 v138, 1, v111 + v_add3_u32 v111, v111, v118, 64 + v_lshl_add_u32 v1, v1, 1, v110 + v_add3_u32 v142, v137, s22, v130 + v_lshlrev_b32_e32 v143, 1, v111 + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[116:117], a[0:15] + v_add3_u32 v110, v111, v119, 64 + v_add3_u32 v144, v142, s22, v131 + v_lshlrev_b32_e32 v145, 1, v110 + v_add3_u32 v110, v110, v122, 64 + v_lshlrev_b32_e32 v146, 1, v110 + v_add_lshl_u32 v147, v110, v123, 1 + v_lshl_add_u32 v0, v0, 4, v147 + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[112:113], a[48:63] + s_waitcnt vmcnt(13) + v_perm_b32 v110, v34, v38, s6 + v_perm_b32 v34, v34, v38, s21 + v_perm_b32 v38, v35, v39, s6 + v_perm_b32 v114, v35, v39, s21 + v_perm_b32 v118, v36, v40, s6 + v_perm_b32 v122, v36, v40, s21 + v_perm_b32 v126, v37, v41, s6 + v_perm_b32 v130, v37, v41, s21 + s_waitcnt vmcnt(9) + v_perm_b32 v111, v42, v46, s6 + v_perm_b32 v35, v42, v46, s21 + v_perm_b32 v39, v43, v47, s6 + v_perm_b32 v115, v43, v47, s21 + v_perm_b32 v119, v44, v48, s6 + v_perm_b32 v123, v44, v48, s21 + v_perm_b32 v127, v45, v49, s6 + v_perm_b32 v131, v45, v49, s21 + s_waitcnt vmcnt(5) + v_perm_b32 v112, v54, v62, s6 + v_perm_b32 v36, v54, v62, s21 + v_perm_b32 v40, v55, v63, s6 + v_perm_b32 v116, v55, v63, s21 + v_perm_b32 v120, v56, v64, s6 + v_perm_b32 v124, v56, v64, s21 + v_perm_b32 v128, v57, v65, s6 + v_perm_b32 v132, v57, v65, s21 + s_waitcnt vmcnt(2) + v_perm_b32 v113, v50, v58, s6 + v_perm_b32 v37, v50, v58, s21 + v_perm_b32 v41, v51, v59, s6 + v_perm_b32 v117, v51, v59, s21 + v_perm_b32 v121, v52, v60, s6 + v_perm_b32 v125, v52, v60, s21 + v_perm_b32 v129, v53, v61, s6 + v_perm_b32 v133, v53, v61, s21 + ds_write_b128 v141, v[110:113] + ds_write_b128 v135, v[34:37] offset:512 + ds_write_b128 v140, v[38:41] offset:512 + ds_write_b128 v136, v[114:117] offset:512 + ds_write_b128 v137, v[118:121] offset:512 + ds_write_b128 v142, v[122:125] offset:512 + ds_write_b128 v144, v[126:129] offset:512 + ds_write_b128 v1, v[130:133] offset:3584 + ds_write_b128 v134, v[2:5] offset:32768 + ds_write_b128 v139, v[6:9] offset:32896 + ds_write_b128 v138, v[10:13] offset:32896 + ds_write_b128 v143, v[14:17] offset:32896 + ds_write_b128 v145, v[18:21] offset:32896 + ds_write_b128 v146, v[22:25] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v147, v[26:29] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v0, v[30:33] offset:33152 + s_cbranch_scc1 .LBB1_8 +.LBB1_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE + v_accvgpr_read_b32 v140, a116 + v_accvgpr_read_b32 v141, a117 + v_accvgpr_read_b32 v142, a118 + v_accvgpr_read_b32 v143, a119 + v_accvgpr_read_b32 v144, a120 + v_accvgpr_read_b32 v145, a121 + v_accvgpr_read_b32 v146, a122 + v_accvgpr_read_b32 v147, a123 + v_accvgpr_read_b32 v148, a124 + v_accvgpr_read_b32 v149, a125 + v_accvgpr_read_b32 v150, a126 + v_accvgpr_read_b32 v151, a127 + v_accvgpr_read_b32 v120, a144 + v_accvgpr_read_b32 v121, a145 + v_accvgpr_read_b32 v122, a146 + v_accvgpr_read_b32 v123, a147 + v_accvgpr_read_b32 v124, a148 + v_accvgpr_read_b32 v125, a149 + v_accvgpr_read_b32 v126, a150 + v_accvgpr_read_b32 v127, a151 + v_accvgpr_read_b32 v128, a152 + v_accvgpr_read_b32 v129, a153 + v_accvgpr_read_b32 v130, a154 + v_accvgpr_read_b32 v131, a155 + v_accvgpr_read_b32 v132, a156 + v_accvgpr_read_b32 v133, a157 + v_accvgpr_read_b32 v134, a158 + v_accvgpr_read_b32 v135, a159 + v_accvgpr_mov_b32 a144, a176 + v_accvgpr_mov_b32 a145, a177 + v_accvgpr_mov_b32 a146, a178 + v_accvgpr_mov_b32 a147, a179 + v_accvgpr_mov_b32 a148, a180 + v_accvgpr_mov_b32 a149, a181 + v_accvgpr_mov_b32 a150, a182 + v_accvgpr_mov_b32 a151, a183 + v_accvgpr_mov_b32 a152, a184 + v_accvgpr_mov_b32 a153, a185 + v_accvgpr_mov_b32 a154, a186 + v_accvgpr_mov_b32 a155, a187 + v_accvgpr_mov_b32 a156, a188 + v_accvgpr_mov_b32 a157, a189 + v_accvgpr_mov_b32 a158, a190 + v_accvgpr_mov_b32 a159, a191 + v_accvgpr_mov_b32 a176, a192 + v_accvgpr_mov_b32 a177, a193 + v_accvgpr_mov_b32 a178, a194 + v_accvgpr_mov_b32 a179, a195 + v_accvgpr_mov_b32 a180, a196 + v_accvgpr_mov_b32 a181, a197 + v_accvgpr_mov_b32 a182, a198 + v_accvgpr_mov_b32 a183, a199 + v_accvgpr_mov_b32 a184, a200 + v_accvgpr_mov_b32 a185, a201 + v_accvgpr_mov_b32 a186, a202 + v_accvgpr_mov_b32 a187, a203 + v_accvgpr_mov_b32 a188, a204 + v_accvgpr_mov_b32 a189, a205 + v_accvgpr_mov_b32 a190, a206 + v_accvgpr_mov_b32 a191, a207 + v_accvgpr_read_b32 v104, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v106, a210 + v_accvgpr_read_b32 v107, a211 + v_accvgpr_read_b32 v108, a212 + v_accvgpr_read_b32 v109, a213 + v_accvgpr_read_b32 v110, a214 + v_accvgpr_read_b32 v111, a215 + v_accvgpr_read_b32 v112, a216 + v_accvgpr_read_b32 v113, a217 + v_accvgpr_read_b32 v114, a218 + v_accvgpr_read_b32 v115, a219 + v_accvgpr_read_b32 v116, a220 + v_accvgpr_read_b32 v117, a221 + v_accvgpr_read_b32 v118, a222 + v_accvgpr_read_b32 v119, a223 + v_accvgpr_read_b32 v48, a224 + v_accvgpr_read_b32 v49, a225 + v_accvgpr_read_b32 v50, a226 + v_accvgpr_read_b32 v51, a227 + v_accvgpr_read_b32 v52, a228 + v_accvgpr_read_b32 v53, a229 + v_accvgpr_read_b32 v54, a230 + v_accvgpr_read_b32 v55, a231 + v_accvgpr_read_b32 v56, a232 + v_accvgpr_read_b32 v57, a233 + v_accvgpr_read_b32 v58, a234 + v_accvgpr_read_b32 v59, a235 + v_accvgpr_read_b32 v60, a236 + v_accvgpr_read_b32 v61, a237 + v_accvgpr_read_b32 v62, a238 + v_accvgpr_read_b32 v63, a239 + v_accvgpr_read_b32 v32, a240 + v_accvgpr_read_b32 v33, a241 + v_accvgpr_read_b32 v34, a242 + v_accvgpr_read_b32 v35, a243 + v_accvgpr_read_b32 v36, a244 + v_accvgpr_read_b32 v37, a245 + v_accvgpr_read_b32 v38, a246 + v_accvgpr_read_b32 v39, a247 + v_accvgpr_read_b32 v40, a248 + v_accvgpr_read_b32 v41, a249 + v_accvgpr_read_b32 v42, a250 + v_accvgpr_read_b32 v43, a251 + v_accvgpr_read_b32 v44, a252 + v_accvgpr_read_b32 v45, a253 + v_accvgpr_read_b32 v46, a254 + v_accvgpr_read_b32 v47, a255 + v_accvgpr_read_b32 v16, a16 + v_accvgpr_read_b32 v17, a17 + v_accvgpr_read_b32 v18, a18 + v_accvgpr_read_b32 v19, a19 + v_accvgpr_read_b32 v20, a20 + v_accvgpr_read_b32 v21, a21 + v_accvgpr_read_b32 v22, a22 + v_accvgpr_read_b32 v23, a23 + v_accvgpr_read_b32 v24, a24 + v_accvgpr_read_b32 v25, a25 + v_accvgpr_read_b32 v26, a26 + v_accvgpr_read_b32 v27, a27 + v_accvgpr_read_b32 v28, a28 + v_accvgpr_read_b32 v29, a29 + v_accvgpr_read_b32 v30, a30 + v_accvgpr_read_b32 v31, a31 + v_accvgpr_read_b32 v0, a32 + v_accvgpr_read_b32 v1, a33 + v_accvgpr_read_b32 v2, a34 + v_accvgpr_read_b32 v3, a35 + v_accvgpr_read_b32 v4, a36 + v_accvgpr_read_b32 v5, a37 + v_accvgpr_read_b32 v6, a38 + v_accvgpr_read_b32 v7, a39 + v_accvgpr_read_b32 v8, a40 + v_accvgpr_read_b32 v9, a41 + v_accvgpr_read_b32 v10, a42 + v_accvgpr_read_b32 v11, a43 + v_accvgpr_read_b32 v12, a44 + v_accvgpr_read_b32 v13, a45 + v_accvgpr_read_b32 v14, a46 + v_accvgpr_read_b32 v15, a47 + v_accvgpr_mov_b32 a16, a0 + v_accvgpr_mov_b32 a17, a1 + v_accvgpr_mov_b32 a18, a2 + v_accvgpr_mov_b32 a19, a3 + v_accvgpr_mov_b32 a20, a4 + v_accvgpr_mov_b32 a21, a5 + v_accvgpr_mov_b32 a22, a6 + v_accvgpr_mov_b32 a23, a7 + v_accvgpr_mov_b32 a24, a8 + v_accvgpr_mov_b32 a25, a9 + v_accvgpr_mov_b32 a26, a10 + v_accvgpr_mov_b32 a27, a11 + v_accvgpr_mov_b32 a28, a12 + v_accvgpr_mov_b32 a29, a13 + v_accvgpr_mov_b32 a30, a14 + v_accvgpr_mov_b32 a31, a15 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + v_accvgpr_read_b32 v139, a115 + v_accvgpr_read_b32 v138, a114 + v_accvgpr_read_b32 v137, a113 + v_accvgpr_read_b32 v136, a112 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[152:155], v102 + ds_read_b128 v[156:159], v101 offset:32768 + v_accvgpr_mov_b32 a0, a96 + v_accvgpr_mov_b32 a1, a97 + v_accvgpr_mov_b32 a2, a98 + v_accvgpr_mov_b32 a3, a99 + v_accvgpr_mov_b32 a4, a100 + v_accvgpr_mov_b32 a5, a101 + v_accvgpr_mov_b32 a6, a102 + v_accvgpr_mov_b32 a7, a103 + v_accvgpr_mov_b32 a8, a104 + v_accvgpr_mov_b32 a9, a105 + v_accvgpr_mov_b32 a10, a106 + v_accvgpr_mov_b32 a11, a107 + v_accvgpr_mov_b32 a12, a108 + v_accvgpr_mov_b32 a13, a109 + v_accvgpr_mov_b32 a14, a110 + v_accvgpr_mov_b32 a15, a111 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[156:157], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[154:155], v[158:159], a[0:15] + v_lshlrev_b32_e32 v64, 1, v97 + ds_read_b128 v[160:163], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v100 + v_accvgpr_mov_b32 a32, a80 + v_accvgpr_mov_b32 a33, a81 + v_accvgpr_mov_b32 a34, a82 + v_accvgpr_mov_b32 a35, a83 + v_accvgpr_mov_b32 a36, a84 + v_accvgpr_mov_b32 a37, a85 + v_accvgpr_mov_b32 a38, a86 + v_accvgpr_mov_b32 a39, a87 + v_accvgpr_mov_b32 a40, a88 + v_accvgpr_mov_b32 a41, a89 + v_accvgpr_mov_b32 a42, a90 + v_accvgpr_mov_b32 a43, a91 + v_accvgpr_mov_b32 a44, a92 + v_accvgpr_mov_b32 a45, a93 + v_accvgpr_mov_b32 a46, a94 + v_accvgpr_mov_b32 a47, a95 + ds_read_b128 v[100:103], v64 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[160:161], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[162:163], a[32:47] + v_lshlrev_b32_e32 v64, 1, v98 + ds_read_b128 v[164:167], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v99 + ds_read_b128 v[168:171], v64 offset:32768 + v_accvgpr_mov_b32 a127, a79 + v_accvgpr_mov_b32 a126, a78 + v_accvgpr_mov_b32 a125, a77 + v_accvgpr_mov_b32 a124, a76 + v_accvgpr_mov_b32 a123, a75 + v_accvgpr_mov_b32 a122, a74 + v_accvgpr_mov_b32 a121, a73 + v_accvgpr_mov_b32 a120, a72 + v_accvgpr_mov_b32 a119, a71 + v_accvgpr_mov_b32 a118, a70 + v_accvgpr_mov_b32 a117, a69 + v_accvgpr_mov_b32 a116, a68 + v_accvgpr_mov_b32 a115, a67 + v_accvgpr_mov_b32 a114, a66 + v_accvgpr_mov_b32 a113, a65 + v_accvgpr_mov_b32 a112, a64 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[152:153], v[164:165], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[154:155], v[166:167], a[112:127] + v_lshlrev_b32_e32 v64, 1, v95 + ds_read_b128 v[172:175], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v96 + ds_read_b128 v[96:99], v64 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[152:153], v[172:173], a[208:223] + v_lshlrev_b32_e32 v64, 1, v94 + v_mfma_f32_32x32x8_f16 a[208:223], v[154:155], v[174:175], a[208:223] + ds_read_b128 v[152:155], v64 + v_accvgpr_write_b32 a239, v151 + v_accvgpr_write_b32 a238, v150 + v_accvgpr_write_b32 a237, v149 + v_accvgpr_write_b32 a236, v148 + v_accvgpr_write_b32 a235, v147 + v_accvgpr_write_b32 a234, v146 + v_accvgpr_write_b32 a233, v145 + v_accvgpr_write_b32 a232, v144 + v_accvgpr_write_b32 a231, v143 + v_accvgpr_write_b32 a230, v142 + v_accvgpr_write_b32 a229, v141 + v_accvgpr_write_b32 a228, v140 + v_accvgpr_write_b32 a227, v139 + v_accvgpr_write_b32 a226, v138 + v_accvgpr_write_b32 a225, v137 + v_accvgpr_write_b32 a224, v136 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[152:153], v[156:157], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[154:155], v[158:159], a[224:239] + v_accvgpr_write_b32 a207, v135 + v_accvgpr_write_b32 a206, v134 + v_accvgpr_write_b32 a205, v133 + v_accvgpr_write_b32 a204, v132 + v_accvgpr_write_b32 a203, v131 + v_accvgpr_write_b32 a202, v130 + v_accvgpr_write_b32 a201, v129 + v_accvgpr_write_b32 a200, v128 + v_accvgpr_write_b32 a199, v127 + v_accvgpr_write_b32 a198, v126 + v_accvgpr_write_b32 a197, v125 + v_accvgpr_write_b32 a196, v124 + v_accvgpr_write_b32 a195, v123 + v_accvgpr_write_b32 a194, v122 + v_accvgpr_write_b32 a193, v121 + v_accvgpr_write_b32 a192, v120 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[192:207], v[152:153], v[160:161], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[154:155], v[162:163], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[152:153], v[164:165], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[154:155], v[166:167], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[152:153], v[172:173], a[144:159] + v_lshlrev_b32_e32 v64, 1, v93 + v_mfma_f32_32x32x8_f16 a[144:159], v[154:155], v[174:175], a[144:159] + ds_read_b128 v[120:123], v64 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[120:121], v[156:157], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[122:123], v[158:159], a[176:191] + v_accvgpr_write_b32 a143, v119 + v_accvgpr_write_b32 a142, v118 + v_accvgpr_write_b32 a141, v117 + v_accvgpr_write_b32 a140, v116 + v_accvgpr_write_b32 a139, v115 + v_accvgpr_write_b32 a138, v114 + v_accvgpr_write_b32 a137, v113 + v_accvgpr_write_b32 a136, v112 + v_accvgpr_write_b32 a135, v111 + v_accvgpr_write_b32 a134, v110 + v_accvgpr_write_b32 a133, v109 + v_accvgpr_write_b32 a132, v108 + v_accvgpr_write_b32 a131, v107 + v_accvgpr_write_b32 a130, v106 + v_accvgpr_write_b32 a129, v105 + v_accvgpr_write_b32 a128, v104 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[128:143], v[120:121], v[160:161], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[122:123], v[162:163], a[128:143] + v_accvgpr_write_b32 a95, v63 + v_accvgpr_write_b32 a94, v62 + v_accvgpr_write_b32 a93, v61 + v_accvgpr_write_b32 a92, v60 + v_accvgpr_write_b32 a91, v59 + v_accvgpr_write_b32 a90, v58 + v_accvgpr_write_b32 a89, v57 + v_accvgpr_write_b32 a88, v56 + v_accvgpr_write_b32 a87, v55 + v_accvgpr_write_b32 a86, v54 + v_accvgpr_write_b32 a85, v53 + v_accvgpr_write_b32 a84, v52 + v_accvgpr_write_b32 a83, v51 + v_accvgpr_write_b32 a82, v50 + v_accvgpr_write_b32 a81, v49 + v_accvgpr_write_b32 a80, v48 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[80:95], v[120:121], v[164:165], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[122:123], v[166:167], a[80:95] + v_accvgpr_write_b32 a79, v47 + v_accvgpr_write_b32 a78, v46 + v_accvgpr_write_b32 a77, v45 + v_accvgpr_write_b32 a76, v44 + v_accvgpr_write_b32 a75, v43 + v_accvgpr_write_b32 a74, v42 + v_accvgpr_write_b32 a73, v41 + v_accvgpr_write_b32 a72, v40 + v_accvgpr_write_b32 a71, v39 + v_accvgpr_write_b32 a70, v38 + v_accvgpr_write_b32 a69, v37 + v_accvgpr_write_b32 a68, v36 + v_accvgpr_write_b32 a67, v35 + v_accvgpr_write_b32 a66, v34 + v_accvgpr_write_b32 a65, v33 + v_accvgpr_write_b32 a64, v32 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], v[120:121], v[172:173], a[64:79] + v_lshlrev_b32_e32 v32, 1, v92 + v_mfma_f32_32x32x8_f16 a[64:79], v[122:123], v[174:175], a[64:79] + ds_read_b128 v[32:35], v32 + v_accvgpr_write_b32 a111, v31 + v_accvgpr_write_b32 a110, v30 + v_accvgpr_write_b32 a109, v29 + v_accvgpr_write_b32 a108, v28 + v_accvgpr_write_b32 a107, v27 + v_accvgpr_write_b32 a106, v26 + v_accvgpr_write_b32 a105, v25 + v_accvgpr_write_b32 a104, v24 + v_accvgpr_write_b32 a103, v23 + v_accvgpr_write_b32 a102, v22 + v_accvgpr_write_b32 a101, v21 + v_accvgpr_write_b32 a100, v20 + v_accvgpr_write_b32 a99, v19 + v_accvgpr_write_b32 a98, v18 + v_accvgpr_write_b32 a97, v17 + v_accvgpr_write_b32 a96, v16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[32:33], v[156:157], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[34:35], v[158:159], a[96:111] + v_accvgpr_write_b32 a63, v15 + v_accvgpr_write_b32 a62, v14 + v_accvgpr_write_b32 a61, v13 + v_accvgpr_write_b32 a60, v12 + v_accvgpr_write_b32 a59, v11 + v_accvgpr_write_b32 a58, v10 + v_accvgpr_write_b32 a57, v9 + v_accvgpr_write_b32 a56, v8 + v_accvgpr_write_b32 a55, v7 + v_accvgpr_write_b32 a54, v6 + v_accvgpr_write_b32 a53, v5 + v_accvgpr_write_b32 a52, v4 + v_accvgpr_write_b32 a51, v3 + v_accvgpr_write_b32 a50, v2 + v_accvgpr_write_b32 a49, v1 + v_accvgpr_write_b32 a48, v0 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[48:63], v[32:33], v[160:161], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[34:35], v[162:163], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[32:33], v[164:165], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[34:35], v[166:167], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[32:33], v[172:173], a[240:255] + v_lshlrev_b32_e32 v0, 1, v75 + v_mfma_f32_32x32x8_f16 a[240:255], v[34:35], v[174:175], a[240:255] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v91 + ds_read_b128 v[6:9], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[10:13], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[6:7], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[4:5], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[100:101], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[4:5], v[102:103], a[32:47] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[168:169], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[4:5], v[170:171], a[112:127] + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[96:97], a[208:223] + v_lshlrev_b32_e32 v0, 1, v77 + v_mfma_f32_32x32x8_f16 a[208:223], v[4:5], v[98:99], a[208:223] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[14:17], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[100:101], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[4:5], v[102:103], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[168:169], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[4:5], v[170:171], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[96:97], a[144:159] + v_lshlrev_b32_e32 v0, 1, v79 + v_mfma_f32_32x32x8_f16 a[144:159], v[4:5], v[98:99], a[144:159] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[18:21], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[100:101], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[4:5], v[102:103], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[168:169], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[4:5], v[170:171], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[96:97], a[64:79] + v_lshlrev_b32_e32 v0, 1, v81 + v_mfma_f32_32x32x8_f16 a[64:79], v[4:5], v[98:99], a[64:79] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[22:25], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[100:101], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[102:103], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[168:169], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[170:171], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[96:97], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[98:99], a[240:255] + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[2:5], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[6:9], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[10:11], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[12:13], v[4:5], a[0:15] + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[26:29], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[30:33], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[10:11], v[26:27], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[12:13], v[28:29], a[32:47] + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[34:37], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[38:41], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[10:11], v[34:35], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[36:37], a[112:127] + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[42:45], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v90 + ds_read_b128 v[46:49], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[208:223], v[10:11], v[42:43], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[26:27], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[34:35], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[14:15], v[42:43], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[16:17], v[44:45], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[18:19], v[2:3], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[20:21], v[4:5], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[18:19], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[20:21], v[28:29], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[18:19], v[34:35], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[20:21], v[36:37], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[18:19], v[42:43], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[20:21], v[44:45], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[22:23], v[2:3], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[24:25], v[4:5], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[22:23], v[26:27], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[24:25], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[22:23], v[34:35], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[24:25], v[36:37], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[22:23], v[42:43], a[240:255] + v_lshlrev_b32_e32 v0, 1, v67 + v_mfma_f32_32x32x8_f16 a[240:255], v[24:25], v[44:45], a[240:255] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[0:1], v[30:31], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[32:33], a[32:47] + v_mfma_f32_32x32x8_f16 a[112:127], v[0:1], v[38:39], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[40:41], a[112:127] + v_mfma_f32_32x32x8_f16 a[208:223], v[0:1], v[46:47], a[208:223] + v_lshlrev_b32_e32 v0, 1, v71 + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[48:49], a[208:223] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[0:1], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[0:1], v[30:31], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[0:1], v[38:39], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[0:1], v[46:47], a[144:159] + v_lshlrev_b32_e32 v0, 1, v73 + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[48:49], a[144:159] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[0:1], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[0:1], v[30:31], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[32:33], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[0:1], v[38:39], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[40:41], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[0:1], v[46:47], a[64:79] + v_lshlrev_b32_e32 v0, 1, v74 + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[48:49], a[64:79] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[0:1], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[0:1], v[30:31], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[32:33], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[0:1], v[38:39], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[40:41], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[0:1], v[46:47], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[48:49], a[240:255] +.LBB1_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4 + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v139, a4 + v_accvgpr_read_b32 v1, a5 + v_accvgpr_read_b32 v18, a6 + v_accvgpr_read_b32 v138, a7 + v_accvgpr_read_b32 v137, a8 + v_accvgpr_read_b32 v136, a9 + v_accvgpr_read_b32 v135, a10 + v_accvgpr_read_b32 v134, a11 + v_accvgpr_read_b32 v133, a12 + v_accvgpr_read_b32 v132, a13 + v_accvgpr_read_b32 v131, a14 + v_accvgpr_read_b32 v130, a15 + v_accvgpr_read_b32 v107, a32 + v_accvgpr_read_b32 v106, a33 + v_accvgpr_read_b32 v105, a34 + v_accvgpr_read_b32 v104, a35 + v_accvgpr_read_b32 v103, a36 + v_accvgpr_read_b32 v102, a37 + v_accvgpr_read_b32 v101, a38 + v_accvgpr_read_b32 v100, a39 + v_accvgpr_read_b32 v99, a40 + v_accvgpr_read_b32 v98, a41 + v_accvgpr_read_b32 v97, a42 + v_accvgpr_read_b32 v96, a43 + v_accvgpr_read_b32 v95, a44 + v_accvgpr_read_b32 v94, a45 + v_accvgpr_read_b32 v93, a46 + v_accvgpr_read_b32 v92, a47 + v_accvgpr_read_b32 v91, a112 + v_accvgpr_read_b32 v90, a113 + v_accvgpr_read_b32 v89, a114 + v_accvgpr_read_b32 v88, a115 + v_accvgpr_read_b32 v87, a116 + v_accvgpr_read_b32 v86, a117 + v_accvgpr_read_b32 v85, a118 + v_accvgpr_read_b32 v84, a119 + v_accvgpr_read_b32 v83, a120 + v_accvgpr_read_b32 v82, a121 + v_accvgpr_read_b32 v81, a122 + v_accvgpr_read_b32 v80, a123 + v_accvgpr_read_b32 v79, a124 + v_accvgpr_read_b32 v78, a125 + v_accvgpr_read_b32 v77, a126 + v_accvgpr_read_b32 v76, a127 + v_accvgpr_read_b32 v75, a208 + v_accvgpr_read_b32 v74, a209 + v_accvgpr_read_b32 v73, a210 + v_accvgpr_read_b32 v72, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v70, a213 + v_accvgpr_read_b32 v68, a214 + v_accvgpr_read_b32 v67, a215 + v_accvgpr_read_b32 v66, a216 + v_accvgpr_read_b32 v65, a217 + v_accvgpr_read_b32 v64, a218 + v_accvgpr_read_b32 v63, a219 + v_accvgpr_read_b32 v62, a220 + v_accvgpr_read_b32 v61, a221 + v_accvgpr_read_b32 v60, a222 + v_accvgpr_read_b32 v19, a223 + v_accvgpr_read_b32 v225, a224 + v_accvgpr_read_b32 v224, a225 + v_accvgpr_read_b32 v223, a226 + v_accvgpr_read_b32 v222, a227 + v_accvgpr_read_b32 v221, a228 + v_accvgpr_read_b32 v220, a229 + v_accvgpr_read_b32 v219, a230 + v_accvgpr_read_b32 v218, a231 + v_accvgpr_read_b32 v217, a232 + v_accvgpr_read_b32 v216, a233 + v_accvgpr_read_b32 v215, a234 + v_accvgpr_read_b32 v214, a235 + v_accvgpr_read_b32 v213, a236 + v_accvgpr_read_b32 v212, a237 + v_accvgpr_read_b32 v211, a238 + v_accvgpr_read_b32 v210, a239 + v_accvgpr_read_b32 v177, a192 + v_accvgpr_read_b32 v176, a193 + v_accvgpr_read_b32 v175, a194 + v_accvgpr_read_b32 v174, a195 + v_accvgpr_read_b32 v173, a196 + v_accvgpr_read_b32 v172, a197 + v_accvgpr_read_b32 v171, a198 + v_accvgpr_read_b32 v170, a199 + v_accvgpr_read_b32 v169, a200 + v_accvgpr_read_b32 v168, a201 + v_accvgpr_read_b32 v167, a202 + v_accvgpr_read_b32 v166, a203 + v_accvgpr_read_b32 v165, a204 + v_accvgpr_read_b32 v164, a205 + v_accvgpr_read_b32 v163, a206 + v_accvgpr_read_b32 v162, a207 + v_accvgpr_read_b32 v161, a160 + v_accvgpr_read_b32 v160, a161 + v_accvgpr_read_b32 v159, a162 + v_accvgpr_read_b32 v158, a163 + v_accvgpr_read_b32 v157, a164 + v_accvgpr_read_b32 v156, a165 + v_accvgpr_read_b32 v155, a166 + v_accvgpr_read_b32 v154, a167 + v_accvgpr_read_b32 v153, a168 + v_accvgpr_read_b32 v152, a169 + v_accvgpr_read_b32 v151, a170 + v_accvgpr_read_b32 v150, a171 + v_accvgpr_read_b32 v149, a172 + v_accvgpr_read_b32 v148, a173 + v_accvgpr_read_b32 v145, a174 + v_accvgpr_read_b32 v144, a175 + v_accvgpr_read_b32 v146, a144 + v_accvgpr_read_b32 v147, a145 + v_accvgpr_read_b32 v129, a146 + v_accvgpr_read_b32 v128, a147 + v_accvgpr_read_b32 v127, a148 + v_accvgpr_read_b32 v126, a149 + v_accvgpr_read_b32 v125, a150 + v_accvgpr_read_b32 v124, a151 + v_accvgpr_read_b32 v123, a152 + v_accvgpr_read_b32 v122, a153 + v_accvgpr_read_b32 v121, a154 + v_accvgpr_read_b32 v120, a155 + v_accvgpr_read_b32 v119, a156 + v_accvgpr_read_b32 v118, a157 + v_accvgpr_read_b32 v117, a158 + v_accvgpr_read_b32 v116, a159 + v_accvgpr_mov_b32 a15, a176 + v_accvgpr_mov_b32 a14, a177 + v_accvgpr_mov_b32 a13, a178 + v_accvgpr_mov_b32 a12, a179 + v_accvgpr_mov_b32 a11, a180 + v_accvgpr_mov_b32 a10, a181 + v_accvgpr_mov_b32 a9, a182 + v_accvgpr_mov_b32 a8, a183 + v_accvgpr_mov_b32 a7, a184 + v_accvgpr_mov_b32 a6, a185 + v_accvgpr_mov_b32 a5, a186 + v_accvgpr_mov_b32 a4, a187 + v_accvgpr_mov_b32 a3, a188 + v_accvgpr_mov_b32 a2, a189 + v_accvgpr_mov_b32 a1, a190 + v_accvgpr_mov_b32 a0, a191 + v_accvgpr_read_b32 v59, a128 + v_accvgpr_read_b32 v58, a129 + v_accvgpr_read_b32 v57, a130 + v_accvgpr_read_b32 v56, a131 + v_accvgpr_read_b32 v55, a132 + v_accvgpr_read_b32 v54, a133 + v_accvgpr_read_b32 v53, a134 + v_accvgpr_read_b32 v52, a135 + v_accvgpr_read_b32 v51, a136 + v_accvgpr_read_b32 v50, a137 + v_accvgpr_read_b32 v25, a138 + v_accvgpr_read_b32 v24, a139 + v_accvgpr_read_b32 v23, a140 + v_accvgpr_read_b32 v22, a141 + v_accvgpr_read_b32 v21, a142 + v_accvgpr_read_b32 v20, a143 + v_accvgpr_read_b32 v115, a80 + v_accvgpr_read_b32 v114, a81 + v_accvgpr_read_b32 v113, a82 + v_accvgpr_read_b32 v112, a83 + v_accvgpr_read_b32 v111, a84 + v_accvgpr_read_b32 v110, a85 + v_accvgpr_read_b32 v109, a86 + v_accvgpr_read_b32 v108, a87 + v_accvgpr_read_b32 v49, a88 + v_accvgpr_read_b32 v48, a89 + v_accvgpr_read_b32 v47, a90 + v_accvgpr_read_b32 v46, a91 + v_accvgpr_read_b32 v45, a92 + v_accvgpr_read_b32 v44, a93 + v_accvgpr_read_b32 v43, a94 + v_accvgpr_read_b32 v42, a95 + v_accvgpr_read_b32 v209, a64 + v_accvgpr_read_b32 v208, a65 + v_accvgpr_read_b32 v207, a66 + v_accvgpr_read_b32 v206, a67 + v_accvgpr_read_b32 v205, a68 + v_accvgpr_read_b32 v204, a69 + v_accvgpr_read_b32 v203, a70 + v_accvgpr_read_b32 v202, a71 + v_accvgpr_read_b32 v201, a72 + v_accvgpr_read_b32 v200, a73 + v_accvgpr_read_b32 v199, a74 + v_accvgpr_read_b32 v198, a75 + v_accvgpr_read_b32 v197, a76 + v_accvgpr_read_b32 v196, a77 + v_accvgpr_read_b32 v195, a78 + v_accvgpr_read_b32 v194, a79 + v_accvgpr_mov_b32 a47, a96 + v_accvgpr_mov_b32 a46, a97 + v_accvgpr_mov_b32 a45, a98 + v_accvgpr_mov_b32 a44, a99 + v_accvgpr_mov_b32 a43, a100 + v_accvgpr_mov_b32 a42, a101 + v_accvgpr_mov_b32 a41, a102 + v_accvgpr_mov_b32 a40, a103 + v_accvgpr_mov_b32 a39, a104 + v_accvgpr_mov_b32 a38, a105 + v_accvgpr_mov_b32 a37, a106 + v_accvgpr_mov_b32 a36, a107 + v_accvgpr_mov_b32 a35, a108 + v_accvgpr_mov_b32 a34, a109 + v_accvgpr_mov_b32 a33, a110 + v_accvgpr_mov_b32 a32, a111 + v_accvgpr_read_b32 v41, a48 + v_accvgpr_read_b32 v40, a49 + v_accvgpr_read_b32 v39, a50 + v_accvgpr_read_b32 v38, a51 + v_accvgpr_read_b32 v37, a52 + v_accvgpr_read_b32 v36, a53 + v_accvgpr_read_b32 v35, a54 + v_accvgpr_read_b32 v34, a55 + v_accvgpr_read_b32 v33, a56 + v_accvgpr_read_b32 v32, a57 + v_accvgpr_read_b32 v31, a58 + v_accvgpr_read_b32 v30, a59 + v_accvgpr_read_b32 v29, a60 + v_accvgpr_read_b32 v28, a61 + v_accvgpr_read_b32 v27, a62 + v_accvgpr_read_b32 v26, a63 + v_accvgpr_read_b32 v193, a16 + v_accvgpr_read_b32 v192, a17 + v_accvgpr_read_b32 v191, a18 + v_accvgpr_read_b32 v190, a19 + v_accvgpr_read_b32 v189, a20 + v_accvgpr_read_b32 v188, a21 + v_accvgpr_read_b32 v187, a22 + v_accvgpr_read_b32 v186, a23 + v_accvgpr_read_b32 v185, a24 + v_accvgpr_read_b32 v184, a25 + v_accvgpr_read_b32 v183, a26 + v_accvgpr_read_b32 v182, a27 + v_accvgpr_read_b32 v181, a28 + v_accvgpr_read_b32 v180, a29 + v_accvgpr_read_b32 v179, a30 + v_accvgpr_read_b32 v178, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s2, s4, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_u32 s2, s5, s3 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v226 + v_lshrrev_b32_e32 v0, 3, v226 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v130, v130 + v_cvt_f16_f32_e32 v132, v225 + v_cvt_f16_f32_e32 v229, v224 + v_cvt_f16_f32_e32 v230, v223 + v_cvt_f16_f32_e32 v231, v222 + v_cvt_f16_f32_e32 v232, v221 + v_cvt_f16_f32_e32 v233, v220 + v_cvt_f16_f32_e32 v234, v219 + v_cvt_f16_f32_e32 v235, v218 + v_cvt_f16_f32_e32 v236, v217 + v_cvt_f16_f32_e32 v237, v216 + v_cvt_f16_f32_e32 v238, v215 + v_cvt_f16_f32_e32 v239, v214 + v_cvt_f16_f32_e32 v240, v213 + v_cvt_f16_f32_e32 v241, v212 + v_cvt_f16_f32_e32 v242, v211 + v_cvt_f16_f32_e32 v243, v210 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v92, v92 + v_cvt_f16_f32_e32 v210, v177 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v225, v162 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v177, v76 + v_cvt_f16_f32_e32 v76, v161 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v133, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v68 + v_cvt_f16_f32_e32 v137, v67 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v19 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v129 + v_cvt_f16_f32_e32 v149, v128 + v_cvt_f16_f32_e32 v150, v127 + v_cvt_f16_f32_e32 v151, v126 + v_cvt_f16_f32_e32 v152, v125 + v_cvt_f16_f32_e32 v153, v124 + v_cvt_f16_f32_e32 v154, v123 + v_cvt_f16_f32_e32 v155, v122 + v_cvt_f16_f32_e32 v156, v121 + v_cvt_f16_f32_e32 v157, v120 + v_cvt_f16_f32_e32 v158, v119 + v_cvt_f16_f32_e32 v159, v118 + v_cvt_f16_f32_e32 v160, v117 + v_cvt_f16_f32_e32 v161, v116 + v_cvt_f16_f32_e32 v209, v209 + v_cvt_f16_f32_e32 v19, v208 + v_accvgpr_write_b32 a16, v19 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v72, v205 + v_cvt_f16_f32_e32 v71, v204 + v_cvt_f16_f32_e32 v70, v203 + v_cvt_f16_f32_e32 v68, v202 + v_cvt_f16_f32_e32 v67, v201 + v_cvt_f16_f32_e32 v66, v200 + v_cvt_f16_f32_e32 v60, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v3, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v19, 1, v69 + v_cvt_f16_f32_e32 v194, v115 + v_cvt_f16_f32_e32 v195, v114 + v_cvt_f16_f32_e32 v196, v113 + v_cvt_f16_f32_e32 v69, v112 + v_cvt_f16_f32_e32 v197, v111 + v_cvt_f16_f32_e32 v198, v110 + v_cvt_f16_f32_e32 v199, v109 + v_cvt_f16_f32_e32 v200, v108 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v48, v43 + v_cvt_f16_f32_e32 v49, v42 + v_cvt_f16_f32_e32 v108, v193 + v_cvt_f16_f32_e32 v109, v192 + v_cvt_f16_f32_e32 v110, v191 + v_cvt_f16_f32_e32 v111, v190 + v_cvt_f16_f32_e32 v112, v189 + v_cvt_f16_f32_e32 v113, v188 + v_cvt_f16_f32_e32 v114, v187 + v_cvt_f16_f32_e32 v115, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v43, v58 + v_cvt_f16_f32_e32 v4, v57 + v_cvt_f16_f32_e32 v5, v56 + v_cvt_f16_f32_e32 v6, v55 + v_cvt_f16_f32_e32 v7, v54 + v_cvt_f16_f32_e32 v8, v53 + v_cvt_f16_f32_e32 v9, v52 + v_cvt_f16_f32_e32 v10, v51 + v_cvt_f16_f32_e32 v11, v50 + v_cvt_f16_f32_e32 v12, v25 + v_cvt_f16_f32_e32 v13, v24 + v_cvt_f16_f32_e32 v14, v23 + v_cvt_f16_f32_e32 v15, v22 + v_cvt_f16_f32_e32 v16, v21 + v_cvt_f16_f32_e32 v17, v20 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v31, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v226 + v_lshrrev_b32_e32 v20, 1, v226 + s_cbranch_scc1 .LBB1_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB1_14 +.LBB1_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESE_NSD_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB1_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v23, s5, v0 + v_lshl_add_u32 v23, v23, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v1 offset:1152 + ds_write_b16 v23, v18 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v130 offset:3456 + ds_write_b16 v23, v132 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 60, v20 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v32, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v32, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v32 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v41, v40, s16 + v_add_u32_e32 v203, v41, v25 + v_lshlrev_b32_e32 v204, 1, v203 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v203 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v92 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v203, 64, v25 + v_add_u32_e32 v204, v41, v203 + v_lshlrev_b32_e32 v205, 1, v204 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v204 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v177 offset:3456 + ds_write_b16 v23, v76 offset:8192 + ds_write_b16 v23, v77 offset:8320 + ds_write_b16 v23, v78 offset:8448 + ds_write_b16 v23, v79 offset:8576 + ds_write_b16 v23, v80 offset:9216 + ds_write_b16 v23, v81 offset:9344 + ds_write_b16 v23, v82 offset:9472 + ds_write_b16 v23, v83 offset:9600 + ds_write_b16 v23, v84 offset:10240 + ds_write_b16 v23, v85 offset:10368 + ds_write_b16 v23, v86 offset:10496 + ds_write_b16 v23, v87 offset:10624 + ds_write_b16 v23, v88 offset:11264 + ds_write_b16 v23, v89 offset:11392 + ds_write_b16 v23, v90 offset:11520 + ds_write_b16 v23, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v204, 0x80, v25 + v_add_u32_e32 v205, v41, v204 + v_mov_b32_e32 v226, v206 + v_lshlrev_b32_e32 v206, 1, v205 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v205 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v133 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v205, 0xc0, v25 + v_add_u32_e32 v41, v41, v205 + v_lshlrev_b32_e32 v206, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_mov_b32_e32 v206, v226 + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v209 + ds_write_b16 v23, a16 offset:128 + ds_write_b16 v23, v207 offset:256 + ds_write_b16 v23, v226 offset:384 + ds_write_b16 v23, v72 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v68 offset:1408 + ds_write_b16 v23, v67 offset:2048 + ds_write_b16 v23, v66 offset:2176 + ds_write_b16 v23, v60 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v3 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, 0x80, v40 + v_mul_lo_u32 v40, v32, s16 + v_add_u32_e32 v41, v40, v205 + v_lshlrev_b32_e32 v205, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v194 + ds_write_b16 v23, v195 offset:128 + ds_write_b16 v23, v196 offset:256 + ds_write_b16 v23, v69 offset:384 + ds_write_b16 v23, v197 offset:1024 + ds_write_b16 v23, v198 offset:1152 + ds_write_b16 v23, v199 offset:1280 + ds_write_b16 v23, v200 offset:1408 + ds_write_b16 v23, v201 offset:2048 + ds_write_b16 v23, v202 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v48 offset:3328 + ds_write_b16 v23, v49 offset:3456 + ds_write_b16 v23, v108 offset:8192 + ds_write_b16 v23, v109 offset:8320 + ds_write_b16 v23, v110 offset:8448 + ds_write_b16 v23, v111 offset:8576 + ds_write_b16 v23, v112 offset:9216 + ds_write_b16 v23, v113 offset:9344 + ds_write_b16 v23, v114 offset:9472 + ds_write_b16 v23, v115 offset:9600 + ds_write_b16 v23, v185 offset:10240 + ds_write_b16 v23, v184 offset:10368 + ds_write_b16 v23, v183 offset:10496 + ds_write_b16 v23, v182 offset:10624 + ds_write_b16 v23, v181 offset:11264 + ds_write_b16 v23, v180 offset:11392 + ds_write_b16 v23, v179 offset:11520 + ds_write_b16 v23, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v204 + v_lshlrev_b32_e32 v204, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v43 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v31 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v203 + v_lshlrev_b32_e32 v203, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v203, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v203, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v203, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v203, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a47 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a46 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a45 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a44 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a43 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a42 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a41 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a40 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v40, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB1_12 +.LBB1_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_add_u32 v0, v0, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v40, v0, v22, s2 + ds_write_b16 v40, v251 + ds_write_b16 v40, v252 offset:128 + ds_write_b16 v40, v253 offset:256 + ds_write_b16 v40, v254 offset:384 + ds_write_b16 v40, v255 offset:1024 + ds_write_b16 v40, v1 offset:1152 + ds_write_b16 v40, v18 offset:1280 + ds_write_b16 v40, v244 offset:1408 + ds_write_b16 v40, v245 offset:2048 + ds_write_b16 v40, v246 offset:2176 + ds_write_b16 v40, v247 offset:2304 + ds_write_b16 v40, v248 offset:2432 + ds_write_b16 v40, v249 offset:3072 + ds_write_b16 v40, v250 offset:3200 + ds_write_b16 v40, v131 offset:3328 + ds_write_b16 v40, v130 offset:3456 + ds_write_b16 v40, v132 offset:8192 + ds_write_b16 v40, v229 offset:8320 + ds_write_b16 v40, v230 offset:8448 + ds_write_b16 v40, v231 offset:8576 + ds_write_b16 v40, v232 offset:9216 + ds_write_b16 v40, v233 offset:9344 + ds_write_b16 v40, v234 offset:9472 + ds_write_b16 v40, v235 offset:9600 + ds_write_b16 v40, v236 offset:10240 + ds_write_b16 v40, v237 offset:10368 + ds_write_b16 v40, v238 offset:10496 + ds_write_b16 v40, v239 offset:10624 + ds_write_b16 v40, v240 offset:11264 + ds_write_b16 v40, v241 offset:11392 + ds_write_b16 v40, v242 offset:11520 + ds_write_b16 v40, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v20 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v41, v0, 1, v18 + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v131, s18, v1 + v_or_b32_e32 v186, s19, v0 + v_mul_lo_u32 v0, v131, s16 + v_add_u32_e32 v1, v0, v186 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v187, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v187, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v107 + ds_write_b16 v40, v106 offset:128 + ds_write_b16 v40, v105 offset:256 + ds_write_b16 v40, v104 offset:384 + ds_write_b16 v40, v103 offset:1024 + ds_write_b16 v40, v102 offset:1152 + ds_write_b16 v40, v101 offset:1280 + ds_write_b16 v40, v100 offset:1408 + ds_write_b16 v40, v99 offset:2048 + ds_write_b16 v40, v98 offset:2176 + ds_write_b16 v40, v97 offset:2304 + ds_write_b16 v40, v96 offset:2432 + ds_write_b16 v40, v95 offset:3072 + ds_write_b16 v40, v94 offset:3200 + ds_write_b16 v40, v93 offset:3328 + ds_write_b16 v40, v92 offset:3456 + ds_write_b16 v40, v210 offset:8192 + ds_write_b16 v40, v211 offset:8320 + ds_write_b16 v40, v212 offset:8448 + ds_write_b16 v40, v213 offset:8576 + ds_write_b16 v40, v214 offset:9216 + ds_write_b16 v40, v215 offset:9344 + ds_write_b16 v40, v216 offset:9472 + ds_write_b16 v40, v217 offset:9600 + ds_write_b16 v40, v218 offset:10240 + ds_write_b16 v40, v219 offset:10368 + ds_write_b16 v40, v220 offset:10496 + ds_write_b16 v40, v221 offset:10624 + ds_write_b16 v40, v222 offset:11264 + ds_write_b16 v40, v223 offset:11392 + ds_write_b16 v40, v224 offset:11520 + ds_write_b16 v40, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v92, 64, v186 + v_add_u32_e32 v1, v0, v92 + v_lshlrev_b32_e32 v93, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v93, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v162 + ds_write_b16 v40, v163 offset:128 + ds_write_b16 v40, v164 offset:256 + ds_write_b16 v40, v165 offset:384 + ds_write_b16 v40, v166 offset:1024 + ds_write_b16 v40, v167 offset:1152 + ds_write_b16 v40, v168 offset:1280 + ds_write_b16 v40, v169 offset:1408 + ds_write_b16 v40, v170 offset:2048 + ds_write_b16 v40, v171 offset:2176 + ds_write_b16 v40, v172 offset:2304 + ds_write_b16 v40, v173 offset:2432 + ds_write_b16 v40, v174 offset:3072 + ds_write_b16 v40, v175 offset:3200 + ds_write_b16 v40, v176 offset:3328 + ds_write_b16 v40, v177 offset:3456 + ds_write_b16 v40, v76 offset:8192 + ds_write_b16 v40, v77 offset:8320 + ds_write_b16 v40, v78 offset:8448 + ds_write_b16 v40, v79 offset:8576 + ds_write_b16 v40, v80 offset:9216 + ds_write_b16 v40, v81 offset:9344 + ds_write_b16 v40, v82 offset:9472 + ds_write_b16 v40, v83 offset:9600 + ds_write_b16 v40, v84 offset:10240 + ds_write_b16 v40, v85 offset:10368 + ds_write_b16 v40, v86 offset:10496 + ds_write_b16 v40, v87 offset:10624 + ds_write_b16 v40, v88 offset:11264 + ds_write_b16 v40, v89 offset:11392 + ds_write_b16 v40, v90 offset:11520 + ds_write_b16 v40, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v76, 0x80, v186 + v_add_u32_e32 v1, v0, v76 + v_lshlrev_b32_e32 v77, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v75 + ds_write_b16 v40, v74 offset:128 + ds_write_b16 v40, v73 offset:256 + ds_write_b16 v40, v133 offset:384 + ds_write_b16 v40, v134 offset:1024 + ds_write_b16 v40, v135 offset:1152 + ds_write_b16 v40, v136 offset:1280 + ds_write_b16 v40, v137 offset:1408 + ds_write_b16 v40, v138 offset:2048 + ds_write_b16 v40, v139 offset:2176 + ds_write_b16 v40, v140 offset:2304 + ds_write_b16 v40, v141 offset:2432 + ds_write_b16 v40, v142 offset:3072 + ds_write_b16 v40, v143 offset:3200 + ds_write_b16 v40, v144 offset:3328 + ds_write_b16 v40, v145 offset:3456 + ds_write_b16 v40, v146 offset:8192 + ds_write_b16 v40, v147 offset:8320 + ds_write_b16 v40, v148 offset:8448 + ds_write_b16 v40, v149 offset:8576 + ds_write_b16 v40, v150 offset:9216 + ds_write_b16 v40, v151 offset:9344 + ds_write_b16 v40, v152 offset:9472 + ds_write_b16 v40, v153 offset:9600 + ds_write_b16 v40, v154 offset:10240 + ds_write_b16 v40, v155 offset:10368 + ds_write_b16 v40, v156 offset:10496 + ds_write_b16 v40, v157 offset:10624 + ds_write_b16 v40, v158 offset:11264 + ds_write_b16 v40, v159 offset:11392 + ds_write_b16 v40, v160 offset:11520 + ds_write_b16 v40, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v74, 0xc0, v186 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v209 + ds_write_b16 v40, a16 offset:128 + ds_write_b16 v40, v207 offset:256 + ds_write_b16 v40, v206 offset:384 + ds_write_b16 v40, v72 offset:1024 + ds_write_b16 v40, v71 offset:1152 + ds_write_b16 v40, v70 offset:1280 + ds_write_b16 v40, v68 offset:1408 + ds_write_b16 v40, v67 offset:2048 + ds_write_b16 v40, v66 offset:2176 + ds_write_b16 v40, v60 offset:2304 + ds_write_b16 v40, v61 offset:2432 + ds_write_b16 v40, v62 offset:3072 + ds_write_b16 v40, v63 offset:3200 + ds_write_b16 v40, v64 offset:3328 + ds_write_b16 v40, v65 offset:3456 + ds_write_b16 v40, v2 offset:8192 + ds_write_b16 v40, v3 offset:8320 + ds_write_b16 v40, v116 offset:8448 + ds_write_b16 v40, v117 offset:8576 + ds_write_b16 v40, v118 offset:9216 + ds_write_b16 v40, v119 offset:9344 + ds_write_b16 v40, v120 offset:9472 + ds_write_b16 v40, v121 offset:9600 + ds_write_b16 v40, v122 offset:10240 + ds_write_b16 v40, v123 offset:10368 + ds_write_b16 v40, v124 offset:10496 + ds_write_b16 v40, v125 offset:10624 + ds_write_b16 v40, v126 offset:11264 + ds_write_b16 v40, v127 offset:11392 + ds_write_b16 v40, v128 offset:11520 + ds_write_b16 v40, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[18:21], v41 offset:128 + ds_read_b128 v[22:25], v41 offset:256 + ds_read_b128 v[32:35], v41 offset:384 + v_add_u32_e32 v36, 0x80, v131 + v_mul_lo_u32 v36, v36, s16 + v_add_u32_e32 v37, v36, v74 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v194 + ds_write_b16 v40, v195 offset:128 + ds_write_b16 v40, v196 offset:256 + ds_write_b16 v40, v69 offset:384 + ds_write_b16 v40, v197 offset:1024 + ds_write_b16 v40, v198 offset:1152 + ds_write_b16 v40, v199 offset:1280 + ds_write_b16 v40, v200 offset:1408 + ds_write_b16 v40, v201 offset:2048 + ds_write_b16 v40, v202 offset:2176 + ds_write_b16 v40, v47 offset:2304 + ds_write_b16 v40, v46 offset:2432 + ds_write_b16 v40, v45 offset:3072 + ds_write_b16 v40, v44 offset:3200 + ds_write_b16 v40, v48 offset:3328 + ds_write_b16 v40, v49 offset:3456 + ds_write_b16 v40, v108 offset:8192 + ds_write_b16 v40, v109 offset:8320 + ds_write_b16 v40, v110 offset:8448 + ds_write_b16 v40, v111 offset:8576 + ds_write_b16 v40, v112 offset:9216 + ds_write_b16 v40, v113 offset:9344 + ds_write_b16 v40, v114 offset:9472 + ds_write_b16 v40, v115 offset:9600 + ds_write_b16 v40, v185 offset:10240 + ds_write_b16 v40, v184 offset:10368 + ds_write_b16 v40, v183 offset:10496 + ds_write_b16 v40, v182 offset:10624 + ds_write_b16 v40, v181 offset:11264 + ds_write_b16 v40, v180 offset:11392 + ds_write_b16 v40, v179 offset:11520 + ds_write_b16 v40, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[18:21], v41 offset:128 + ds_read_b128 v[22:25], v41 offset:256 + ds_read_b128 v[32:35], v41 offset:384 + v_add_u32_e32 v37, v36, v76 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v42 + ds_write_b16 v40, v43 offset:128 + ds_write_b16 v40, v4 offset:256 + ds_write_b16 v40, v5 offset:384 + ds_write_b16 v40, v6 offset:1024 + ds_write_b16 v40, v7 offset:1152 + ds_write_b16 v40, v8 offset:1280 + ds_write_b16 v40, v9 offset:1408 + ds_write_b16 v40, v10 offset:2048 + ds_write_b16 v40, v11 offset:2176 + ds_write_b16 v40, v12 offset:2304 + ds_write_b16 v40, v13 offset:2432 + ds_write_b16 v40, v14 offset:3072 + ds_write_b16 v40, v15 offset:3200 + ds_write_b16 v40, v16 offset:3328 + ds_write_b16 v40, v17 offset:3456 + ds_write_b16 v40, v50 offset:8192 + ds_write_b16 v40, v51 offset:8320 + ds_write_b16 v40, v52 offset:8448 + ds_write_b16 v40, v53 offset:8576 + ds_write_b16 v40, v54 offset:9216 + ds_write_b16 v40, v55 offset:9344 + ds_write_b16 v40, v56 offset:9472 + ds_write_b16 v40, v57 offset:9600 + ds_write_b16 v40, v58 offset:10240 + ds_write_b16 v40, v59 offset:10368 + ds_write_b16 v40, v31 offset:10496 + ds_write_b16 v40, v30 offset:10624 + ds_write_b16 v40, v29 offset:11264 + ds_write_b16 v40, v28 offset:11392 + ds_write_b16 v40, v27 offset:11520 + ds_write_b16 v40, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v36, v92 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a47 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a46 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a45 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a44 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a43 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a42 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a41 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a40 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a32 + v_cvt_f16_f32_e32 v31, v31 + ds_write_b16 v40, v0 + ds_write_b16 v40, v1 offset:128 + ds_write_b16 v40, v2 offset:256 + ds_write_b16 v40, v3 offset:384 + ds_write_b16 v40, v4 offset:1024 + ds_write_b16 v40, v5 offset:1152 + ds_write_b16 v40, v6 offset:1280 + ds_write_b16 v40, v7 offset:1408 + ds_write_b16 v40, v8 offset:2048 + ds_write_b16 v40, v9 offset:2176 + ds_write_b16 v40, v10 offset:2304 + ds_write_b16 v40, v11 offset:2432 + ds_write_b16 v40, v12 offset:3072 + ds_write_b16 v40, v13 offset:3200 + ds_write_b16 v40, v14 offset:3328 + ds_write_b16 v40, v15 offset:3456 + ds_write_b16 v40, v16 offset:8192 + ds_write_b16 v40, v17 offset:8320 + ds_write_b16 v40, v18 offset:8448 + ds_write_b16 v40, v19 offset:8576 + ds_write_b16 v40, v20 offset:9216 + ds_write_b16 v40, v21 offset:9344 + ds_write_b16 v40, v22 offset:9472 + ds_write_b16 v40, v23 offset:9600 + ds_write_b16 v40, v24 offset:10240 + ds_write_b16 v40, v25 offset:10368 + ds_write_b16 v40, v26 offset:10496 + ds_write_b16 v40, v27 offset:10624 + ds_write_b16 v40, v28 offset:11264 + ds_write_b16 v40, v29 offset:11392 + ds_write_b16 v40, v30 offset:11520 + ds_write_b16 v40, v31 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v36, v186 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end1: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end1-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 28612 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB2_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB2_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s10 + v_mov_b32_e32 v3, s11 + v_mul_lo_u32 v4, v0, s2 + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v6 +.LBB2_3: ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_ushort v7, v[2:3], off + v_lshl_add_u64 v[8:9], v[4:5], 1, s[8:9] + global_load_ushort v5, v[8:9], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_add_u32_e32 v4, s7, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v1, v5, v7, v1 op_sel_hi:[1,1,0] + s_cbranch_scc0 .LBB2_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB2_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB2_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end2: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end2-_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 432 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v226, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s22, s12, s2 + s_mul_i32 s2, s22, s7 + s_mul_i32 s12, s22, s20 + s_sub_i32 s6, s6, s22 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[2:3], s[12:13], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s22, s3, 1 + s_mul_i32 s2, s20, s2 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v225, -1, v0 + v_and_b32_e32 v71, 31, v225 + v_lshrrev_b32_e32 v2, 5, v225 + v_and_b32_e32 v228, 7, v225 + v_lshrrev_b32_e32 v3, 2, v225 + s_cbranch_scc0 .LBB3_2 +; %bb.1: + v_readfirstlane_b32 s15, v226 + s_lshr_b32 s25, s15, 2 + v_lshlrev_b32_e32 v68, 3, v2 + s_and_b32 s23, s25, 0x3ffffff0 + v_lshlrev_b32_e32 v4, 3, v71 + v_or_b32_e32 v0, s18, v4 + v_add_u32_e32 v5, s23, v68 + v_mad_u64_u32 v[0:1], s[10:11], v5, s7, v[0:1] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v1, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v6, 1, v0 + buffer_load_dwordx4 v[8:11], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v1, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v6, 1, v0 + buffer_load_dwordx4 v[16:19], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[20:23], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v1, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v6, 1, v0 + buffer_load_dwordx4 v[24:27], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[28:31], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v1, 1, v0 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[32:35], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[36:39], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 12, v2 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s10, 0x1000504 + s_mov_b32 s24, 0x3020706 + v_lshl_or_b32 v1, v228, 8, v0 + v_or_b32_e32 v4, s19, v4 + s_lshr_b32 s26, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s25, 0x3fffffe0 + v_and_or_b32 v6, s26, 32, v71 + v_or_b32_e32 v0, s11, v71 + v_lshrrev_b32_e32 v7, 3, v6 + v_lshrrev_b32_e32 v6, 3, v0 + v_mad_u64_u32 v[4:5], s[26:27], v5, s20, v[4:5] + v_xor_b32_e32 v69, v7, v228 + v_xor_b32_e32 v5, v6, v228 + v_lshl_or_b32 v70, v69, 3, v1 + v_lshlrev_b32_e32 v48, 1, v4 + v_add_u32_e32 v4, s20, v4 + v_lshl_add_u32 v1, v5, 3, v1 + v_lshlrev_b32_e32 v49, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[40:43], v48, s[12:15], 0 offen + buffer_load_dwordx4 v[44:47], v49, s[12:15], 0 offen + v_lshlrev_b32_e32 v56, 1, v4 + v_add_u32_e32 v4, s20, v4 + v_lshlrev_b32_e32 v57, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[48:51], v56, s[12:15], 0 offen + buffer_load_dwordx4 v[52:55], v57, s[12:15], 0 offen + v_lshlrev_b32_e32 v64, 1, v4 + v_add_u32_e32 v4, s20, v4 + v_lshlrev_b32_e32 v65, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[56:59], v64, s[12:15], 0 offen + buffer_load_dwordx4 v[60:63], v65, s[12:15], 0 offen + v_lshlrev_b32_e32 v76, 1, v4 + v_add_lshl_u32 v4, v4, s20, 1 + buffer_load_dwordx4 v[64:67], v76, s[12:15], 0 offen + buffer_load_dwordx4 v[72:75], v4, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v76, v8, v12, s10 + v_perm_b32 v80, v8, v12, s24 + v_perm_b32 v84, v9, v13, s10 + v_perm_b32 v88, v9, v13, s24 + v_perm_b32 v92, v10, v14, s10 + v_perm_b32 v96, v10, v14, s24 + s_waitcnt vmcnt(12) + v_perm_b32 v77, v16, v20, s10 + v_perm_b32 v81, v16, v20, s24 + v_perm_b32 v85, v17, v21, s10 + v_perm_b32 v89, v17, v21, s24 + v_perm_b32 v93, v18, v22, s10 + s_waitcnt vmcnt(10) + v_perm_b32 v78, v24, v28, s10 + v_perm_b32 v82, v24, v28, s24 + v_perm_b32 v86, v25, v29, s10 + v_perm_b32 v90, v25, v29, s24 + s_waitcnt vmcnt(8) + v_perm_b32 v79, v32, v36, s10 + v_perm_b32 v83, v32, v36, s24 + v_perm_b32 v87, v33, v37, s10 + v_perm_b32 v91, v33, v37, s24 + v_perm_b32 v97, v18, v22, s24 + v_perm_b32 v94, v26, v30, s10 + v_perm_b32 v98, v26, v30, s24 + v_perm_b32 v95, v34, v38, s10 + v_perm_b32 v99, v34, v38, s24 + v_perm_b32 v8, v11, v15, s10 + v_perm_b32 v12, v11, v15, s24 + v_perm_b32 v9, v19, v23, s10 + v_perm_b32 v13, v19, v23, s24 + v_perm_b32 v10, v27, v31, s10 + v_perm_b32 v14, v27, v31, s24 + v_perm_b32 v11, v35, v39, s10 + v_perm_b32 v15, v35, v39, s24 + v_and_b32_e32 v4, 24, v3 + v_add_u32_e32 v4, s23, v4 + v_lshrrev_b32_e32 v16, 2, v4 + v_and_b32_e32 v16, 24, v16 + v_xor_b32_e32 v17, v16, v71 + v_lshlrev_b32_e32 v18, 9, v4 + v_and_b32_e32 v18, 0x3000, v18 + v_lshlrev_b32_e32 v4, 6, v4 + v_and_b32_e32 v4, 0x7ffff800, v4 + v_add_lshl_u32 v4, v4, v18, 1 + v_lshl_or_b32 v4, v17, 4, v4 + ds_write_b128 v4, v[76:79] + v_or_b32_e32 v18, 1, v16 + v_xor_b32_e32 v18, v18, v71 + v_sub_u32_e32 v17, v18, v17 + v_lshl_add_u32 v76, v17, 4, v4 + ds_write_b128 v76, v[80:83] offset:512 + v_or_b32_e32 v17, 2, v16 + v_xor_b32_e32 v17, v17, v71 + v_sub_u32_e32 v18, v17, v18 + v_lshlrev_b32_e32 v18, 4, v18 + s_movk_i32 s11, 0x200 + v_add3_u32 v77, v76, s11, v18 + ds_write_b128 v77, v[84:87] offset:512 + v_or_b32_e32 v18, 3, v16 + v_xor_b32_e32 v18, v18, v71 + v_sub_u32_e32 v17, v18, v17 + v_lshlrev_b32_e32 v17, 4, v17 + v_add3_u32 v78, v77, s11, v17 + ds_write_b128 v78, v[88:91] offset:512 + v_or_b32_e32 v17, 4, v16 + v_xor_b32_e32 v17, v17, v71 + v_sub_u32_e32 v18, v17, v18 + v_lshlrev_b32_e32 v18, 4, v18 + v_add3_u32 v79, v78, s11, v18 + ds_write_b128 v79, v[92:95] offset:512 + v_or_b32_e32 v18, 5, v16 + v_xor_b32_e32 v18, v18, v71 + v_sub_u32_e32 v17, v18, v17 + v_lshlrev_b32_e32 v17, 4, v17 + v_add3_u32 v80, v79, s11, v17 + ds_write_b128 v80, v[96:99] offset:512 + v_or_b32_e32 v17, 6, v16 + v_xor_b32_e32 v17, v17, v71 + v_sub_u32_e32 v18, v17, v18 + v_lshlrev_b32_e32 v18, 4, v18 + v_add3_u32 v81, v80, s11, v18 + ds_write_b128 v81, v[8:11] offset:512 + v_or_b32_e32 v8, 7, v16 + v_xor_b32_e32 v8, v8, v71 + v_sub_u32_e32 v8, v8, v17 + v_lshlrev_b32_e32 v8, 4, v8 + v_add3_u32 v82, v81, s11, v8 + ds_write_b128 v82, v[12:15] offset:512 + s_waitcnt vmcnt(6) + v_perm_b32 v8, v40, v44, s10 + v_perm_b32 v12, v40, v44, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v9, v48, v52, s10 + v_perm_b32 v13, v48, v52, s24 + s_waitcnt vmcnt(2) + v_perm_b32 v10, v56, v60, s10 + v_perm_b32 v14, v56, v60, s24 + s_waitcnt vmcnt(0) + v_perm_b32 v11, v64, v72, s10 + v_perm_b32 v15, v64, v72, s24 + v_perm_b32 v16, v41, v45, s10 + v_perm_b32 v20, v41, v45, s24 + v_perm_b32 v17, v49, v53, s10 + v_perm_b32 v21, v49, v53, s24 + v_perm_b32 v18, v57, v61, s10 + v_perm_b32 v22, v57, v61, s24 + v_perm_b32 v19, v65, v73, s10 + v_perm_b32 v23, v65, v73, s24 + v_perm_b32 v24, v42, v46, s10 + v_perm_b32 v28, v42, v46, s24 + v_perm_b32 v25, v50, v54, s10 + v_perm_b32 v29, v50, v54, s24 + v_perm_b32 v26, v58, v62, s10 + v_perm_b32 v30, v58, v62, s24 + v_perm_b32 v27, v66, v74, s10 + v_perm_b32 v31, v66, v74, s24 + v_perm_b32 v32, v43, v47, s10 + v_perm_b32 v36, v43, v47, s24 + v_perm_b32 v33, v51, v55, s10 + v_perm_b32 v37, v51, v55, s24 + v_perm_b32 v34, v59, v63, s10 + v_perm_b32 v38, v59, v63, s24 + v_perm_b32 v35, v67, v75, s10 + v_perm_b32 v39, v67, v75, s24 + ds_write_b128 v4, v[8:11] offset:32768 + ds_write_b128 v76, v[12:15] offset:33280 + ds_write_b128 v77, v[16:19] offset:33280 + ds_write_b128 v78, v[20:23] offset:33280 + ds_write_b128 v79, v[24:27] offset:33280 + ds_write_b128 v80, v[28:31] offset:33280 + ds_write_b128 v81, v[32:35] offset:33280 + ds_write_b128 v82, v[36:39] offset:33280 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v4, 1, v1 + v_add_u32_e32 v8, 16, v68 + v_lshrrev_b32_e32 v9, 5, v8 + v_bfe_u32 v8, v8, 3, 2 + v_lshl_or_b32 v10, v9, 3, v228 + v_and_b32_e32 v11, 31, v10 + v_xor_b32_e32 v13, v6, v11 + v_sub_u32_e32 v5, v13, v5 + v_lshlrev_b32_e32 v12, 11, v9 + v_lshlrev_b32_e32 v5, 3, v5 + v_sub_u32_e32 v14, v8, v2 + v_lshl_or_b32 v12, v14, 12, v12 + v_add3_u32 v1, v1, v12, v5 + v_lshlrev_b32_e32 v14, 1, v1 + ds_read_b128 v[42:45], v4 + ds_read_b128 v[54:57], v14 + v_xor_b32_e32 v4, 1, v9 + v_sub_u32_e32 v5, v2, v8 + v_lshl_add_u32 v8, v4, 3, v10 + v_and_b32_e32 v9, 31, v8 + v_xor_b32_e32 v15, v6, v9 + v_sub_u32_e32 v13, v15, v13 + v_lshlrev_b32_e32 v4, 11, v4 + v_lshl_add_u32 v10, v5, 12, v4 + v_lshl_add_u32 v4, v13, 3, v10 + v_add_u32_e32 v5, 48, v68 + v_lshrrev_b32_e32 v13, 5, v5 + v_add_u32_e32 v16, -1, v13 + v_bfe_u32 v17, v5, 3, 2 + v_sub_u32_e32 v18, v17, v2 + v_lshl_add_u32 v19, v16, 3, v8 + v_ashrrev_i32_e32 v5, 31, v19 + v_lshrrev_b32_e32 v5, 27, v5 + v_add_u32_e32 v5, v19, v5 + v_and_b32_e32 v5, 0xffffffe0, v5 + v_sub_u32_e32 v5, v19, v5 + v_lshlrev_b32_e32 v8, 11, v16 + v_lshl_add_u32 v8, v18, 12, v8 + v_sub_u32_e32 v16, v2, v17 + v_lshlrev_b32_e32 v17, 3, v13 + v_sub_u32_e32 v17, v19, v17 + v_ashrrev_i32_e32 v18, 31, v17 + v_lshrrev_b32_e32 v18, 27, v18 + v_add_u32_e32 v18, v17, v18 + v_and_b32_e32 v18, 0xffffffe0, v18 + v_sub_u32_e32 v17, v17, v18 + v_lshlrev_b32_e32 v16, 12, v16 + v_lshlrev_b32_e32 v13, 11, v13 + v_sub_u32_e32 v13, v16, v13 + v_lshlrev_b32_e32 v16, 1, v70 + ds_read_b128 v[58:61], v16 offset:32768 + v_xor_b32_e32 v16, v7, v11 + v_sub_u32_e32 v18, v16, v69 + v_lshlrev_b32_e32 v18, 3, v18 + v_add3_u32 v18, v70, v12, v18 + v_lshlrev_b32_e32 v19, 1, v18 + v_xor_b32_e32 v20, v7, v9 + v_sub_u32_e32 v16, v20, v16 + v_lshl_add_u32 v16, v16, 3, v10 + v_lshl_add_u32 v21, v16, 1, v19 + v_xor_b32_e32 v22, v7, v5 + v_sub_u32_e32 v20, v22, v20 + v_lshl_add_u32 v20, v20, 3, v8 + v_lshl_add_u32 v23, v20, 1, v21 + v_or_b32_e32 v24, 8, v7 + v_xor_b32_e32 v25, v24, v17 + v_sub_u32_e32 v22, v25, v22 + v_lshl_add_u32 v22, v22, 3, v13 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[42:43], v[58:59], 0 + v_lshl_add_u32 v26, v22, 1, v23 + ds_read_b128 v[62:65], v26 offset:32768 + v_xor_b32_e32 v27, v24, v11 + v_sub_u32_e32 v25, v27, v25 + v_lshl_add_u32 v25, v25, 3, v12 + v_lshl_add_u32 v26, v25, 1, v26 + v_xor_b32_e32 v28, v24, v9 + v_mfma_f32_32x32x8_f16 a[0:15], v[44:45], v[60:61], a[0:15] + v_sub_u32_e32 v27, v28, v27 + v_lshl_add_u32 v27, v27, 3, v10 + v_lshl_add_u32 v29, v27, 1, v26 + v_xor_b32_e32 v24, v24, v5 + v_sub_u32_e32 v28, v24, v28 + v_lshl_add_u32 v28, v28, 3, v8 + v_lshl_add_u32 v30, v28, 1, v29 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[42:43], v[62:63], 0 + v_or_b32_e32 v31, 16, v7 + v_xor_b32_e32 v32, v31, v17 + v_sub_u32_e32 v24, v32, v24 + v_lshl_add_u32 v24, v24, 3, v13 + v_lshl_add_u32 v33, v24, 1, v30 + ds_read_b128 v[66:69], v33 offset:32768 + v_xor_b32_e32 v34, v31, v11 + v_mfma_f32_32x32x8_f16 a[32:47], v[44:45], v[64:65], a[32:47] + v_sub_u32_e32 v32, v34, v32 + v_lshl_add_u32 v32, v32, 3, v12 + v_lshl_add_u32 v33, v32, 1, v33 + v_xor_b32_e32 v35, v31, v9 + v_sub_u32_e32 v34, v35, v34 + v_lshl_add_u32 v34, v34, 3, v10 + v_lshl_add_u32 v36, v34, 1, v33 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[42:43], v[66:67], 0 + v_xor_b32_e32 v31, v31, v5 + v_sub_u32_e32 v35, v31, v35 + v_lshl_add_u32 v35, v35, 3, v8 + v_lshl_add_u32 v37, v35, 1, v36 + v_or_b32_e32 v7, 24, v7 + v_xor_b32_e32 v38, v7, v17 + v_sub_u32_e32 v31, v38, v31 + v_mfma_f32_32x32x8_f16 a[112:127], v[44:45], v[68:69], a[112:127] + v_lshl_add_u32 v31, v31, 3, v13 + v_lshl_add_u32 v39, v31, 1, v37 + ds_read_b128 v[72:75], v39 offset:32768 + v_lshl_add_u32 v14, v4, 1, v14 + v_xor_b32_e32 v6, v6, v5 + v_sub_u32_e32 v15, v6, v15 + v_lshl_add_u32 v15, v15, 3, v8 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[42:43], v[72:73], 0 + v_lshl_add_u32 v40, v15, 1, v14 + v_add_u32_e32 v41, 64, v0 + v_lshrrev_b32_e32 v41, 3, v41 + v_xor_b32_e32 v42, v41, v17 + v_sub_u32_e32 v6, v42, v6 + v_lshl_add_u32 v6, v6, 3, v13 + v_lshl_add_u32 v43, v6, 1, v40 + v_mfma_f32_32x32x8_f16 a[208:223], v[44:45], v[74:75], a[208:223] + ds_read_b128 v[48:51], v43 + v_xor_b32_e32 v44, v41, v11 + v_sub_u32_e32 v42, v44, v42 + v_lshl_add_u32 v42, v42, 3, v12 + v_lshl_add_u32 v43, v42, 1, v43 + ds_read_b128 v[76:79], v43 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[48:49], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[50:51], v[60:61], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[48:49], v[62:63], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[50:51], v[64:65], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[48:49], v[66:67], 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[50:51], v[68:69], a[160:175] + v_xor_b32_e32 v45, v41, v9 + v_sub_u32_e32 v44, v45, v44 + v_lshl_add_u32 v44, v44, 3, v10 + v_lshl_add_u32 v43, v44, 1, v43 + v_xor_b32_e32 v41, v41, v5 + v_sub_u32_e32 v45, v41, v45 + v_lshl_add_u32 v45, v45, 3, v8 + v_mfma_f32_32x32x8_f16 a[144:159], v[48:49], v[72:73], 0 + v_lshl_add_u32 v46, v45, 1, v43 + v_add_u32_e32 v47, 0x80, v0 + v_lshrrev_b32_e32 v47, 3, v47 + v_xor_b32_e32 v48, v47, v17 + v_sub_u32_e32 v41, v48, v41 + v_lshl_add_u32 v41, v41, 3, v13 + v_lshl_add_u32 v49, v41, 1, v46 + v_mfma_f32_32x32x8_f16 a[144:159], v[50:51], v[74:75], a[144:159] + ds_read_b128 v[80:83], v49 + v_xor_b32_e32 v50, v47, v11 + v_sub_u32_e32 v48, v50, v48 + v_lshl_add_u32 v48, v48, 3, v12 + v_lshl_add_u32 v49, v48, 1, v49 + ds_read_b128 v[84:87], v49 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[80:81], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[82:83], v[60:61], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[80:81], v[62:63], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[82:83], v[64:65], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[80:81], v[66:67], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[82:83], v[68:69], a[80:95] + v_xor_b32_e32 v51, v47, v9 + v_sub_u32_e32 v50, v51, v50 + v_lshl_add_u32 v50, v50, 3, v10 + v_lshl_add_u32 v49, v50, 1, v49 + v_xor_b32_e32 v47, v47, v5 + v_sub_u32_e32 v51, v47, v51 + v_lshl_add_u32 v51, v51, 3, v8 + v_mfma_f32_32x32x8_f16 a[64:79], v[80:81], v[72:73], 0 + v_lshl_add_u32 v52, v51, 1, v49 + v_add_u32_e32 v0, 0xc0, v0 + v_lshrrev_b32_e32 v0, 3, v0 + v_xor_b32_e32 v17, v0, v17 + v_sub_u32_e32 v47, v17, v47 + v_lshl_add_u32 v13, v47, 3, v13 + v_lshl_add_u32 v47, v13, 1, v52 + v_mfma_f32_32x32x8_f16 a[64:79], v[82:83], v[74:75], a[64:79] + ds_read_b128 v[80:83], v47 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[80:81], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[82:83], v[60:61], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[80:81], v[62:63], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[82:83], v[64:65], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[80:81], v[66:67], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[82:83], v[68:69], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[80:81], v[72:73], 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[82:83], v[74:75], a[240:255] + ds_read_b128 v[58:61], v19 offset:32768 + ds_read_b128 v[62:65], v21 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[54:55], v[58:59], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[56:57], v[60:61], a[0:15] + ds_read_b128 v[66:69], v26 offset:32768 + ds_read_b128 v[72:75], v29 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[54:55], v[66:67], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[56:57], v[68:69], a[32:47] + ds_read_b128 v[80:83], v33 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[54:55], v[80:81], a[112:127] + v_xor_b32_e32 v19, v7, v11 + v_sub_u32_e32 v21, v19, v38 + v_mfma_f32_32x32x8_f16 a[112:127], v[56:57], v[82:83], a[112:127] + v_lshl_add_u32 v21, v21, 3, v12 + v_lshl_add_u32 v26, v21, 1, v39 + ds_read_b128 v[88:91], v26 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[54:55], v[88:89], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[56:57], v[90:91], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[76:77], v[58:59], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[78:79], v[60:61], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[76:77], v[66:67], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[78:79], v[68:69], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[76:77], v[80:81], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[78:79], v[82:83], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[76:77], v[88:89], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[78:79], v[90:91], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[84:85], v[58:59], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[86:87], v[60:61], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[84:85], v[66:67], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[86:87], v[68:69], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[84:85], v[80:81], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[86:87], v[82:83], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[84:85], v[88:89], a[64:79] + v_xor_b32_e32 v11, v0, v11 + v_sub_u32_e32 v17, v11, v17 + v_lshl_add_u32 v12, v17, 3, v12 + v_lshl_add_u32 v17, v12, 1, v47 + v_mfma_f32_32x32x8_f16 a[64:79], v[86:87], v[90:91], a[64:79] + ds_read_b128 v[54:57], v17 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[54:55], v[58:59], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[56:57], v[60:61], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[54:55], v[66:67], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[56:57], v[68:69], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[54:55], v[80:81], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[56:57], v[82:83], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[54:55], v[88:89], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[56:57], v[90:91], a[240:255] + ds_read_b128 v[54:57], v14 + ds_read_b128 v[58:61], v40 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[54:55], v[62:63], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[56:57], v[64:65], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[54:55], v[72:73], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[56:57], v[74:75], a[32:47] + ds_read_b128 v[66:69], v36 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[54:55], v[66:67], a[112:127] + v_xor_b32_e32 v14, v7, v9 + v_sub_u32_e32 v19, v14, v19 + v_mfma_f32_32x32x8_f16 a[112:127], v[56:57], v[68:69], a[112:127] + v_lshl_add_u32 v19, v19, 3, v10 + v_lshl_add_u32 v26, v19, 1, v26 + ds_read_b128 v[76:79], v26 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[54:55], v[76:77], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[56:57], v[78:79], a[208:223] + ds_read_b128 v[54:57], v43 + ds_read_b128 v[80:83], v46 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[54:55], v[62:63], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[56:57], v[64:65], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[54:55], v[72:73], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[56:57], v[74:75], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[54:55], v[66:67], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[56:57], v[68:69], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[54:55], v[76:77], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[56:57], v[78:79], a[144:159] + ds_read_b128 v[54:57], v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[54:55], v[62:63], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[56:57], v[64:65], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[54:55], v[72:73], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[56:57], v[74:75], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[54:55], v[66:67], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[56:57], v[68:69], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[54:55], v[76:77], a[64:79] + v_xor_b32_e32 v9, v0, v9 + v_sub_u32_e32 v11, v9, v11 + v_lshl_add_u32 v10, v11, 3, v10 + v_lshl_add_u32 v11, v10, 1, v17 + v_mfma_f32_32x32x8_f16 a[64:79], v[56:57], v[78:79], a[64:79] + ds_read_b128 v[54:57], v11 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[54:55], v[62:63], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[56:57], v[64:65], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[54:55], v[72:73], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[56:57], v[74:75], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[54:55], v[66:67], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[56:57], v[68:69], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[54:55], v[76:77], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[56:57], v[78:79], a[240:255] + ds_read_b128 v[54:57], v23 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[58:59], v[54:55], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[60:61], v[56:57], a[0:15] + ds_read_b128 v[62:65], v30 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[58:59], v[62:63], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[60:61], v[64:65], a[32:47] + ds_read_b128 v[36:39], v37 offset:32768 + v_lshlrev_b32_e32 v8, 1, v8 + v_add3_u32 v11, v16, v18, v20 + v_add3_u32 v11, v22, v11, v25 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[58:59], v[36:37], a[112:127] + v_add3_u32 v11, v27, v11, v28 + v_add3_u32 v11, v24, v11, v32 + v_add3_u32 v11, v34, v11, v35 + v_add3_u32 v11, v31, v11, v21 + v_xor_b32_e32 v7, v7, v5 + v_sub_u32_e32 v7, v7, v14 + v_lshlrev_b32_e32 v7, 4, v7 + v_mfma_f32_32x32x8_f16 a[112:127], v[60:61], v[38:39], a[112:127] + v_add_lshl_u32 v11, v19, v11, 1 + v_add3_u32 v7, v7, v8, v11 + ds_read_b128 v[16:19], v7 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[58:59], v[16:17], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[60:61], v[18:19], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[80:81], v[54:55], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[82:83], v[56:57], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[80:81], v[62:63], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[82:83], v[64:65], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[80:81], v[36:37], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[82:83], v[38:39], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[80:81], v[16:17], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[82:83], v[18:19], a[144:159] + ds_read_b128 v[20:23], v52 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[20:21], v[54:55], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[22:23], v[56:57], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[20:21], v[62:63], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[22:23], v[64:65], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[20:21], v[36:37], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[22:23], v[38:39], a[80:95] + v_add3_u32 v1, v4, v1, v15 + v_add3_u32 v1, v6, v1, v42 + v_add3_u32 v1, v44, v1, v45 + v_add3_u32 v1, v41, v1, v48 + v_mfma_f32_32x32x8_f16 a[64:79], v[20:21], v[16:17], a[64:79] + v_add3_u32 v1, v50, v1, v51 + v_add3_u32 v1, v13, v1, v12 + v_xor_b32_e32 v0, v0, v5 + v_sub_u32_e32 v0, v0, v9 + v_lshlrev_b32_e32 v0, 4, v0 + v_add_lshl_u32 v1, v10, v1, 1 + v_add3_u32 v0, v0, v8, v1 + v_mfma_f32_32x32x8_f16 a[64:79], v[22:23], v[18:19], a[64:79] + ds_read_b128 v[4:7], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[54:55], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[6:7], v[56:57], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[62:63], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[6:7], v[64:65], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[36:37], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[6:7], v[38:39], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[16:17], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[6:7], v[18:19], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB3_3 + s_branch .LBB3_10 +.LBB3_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr63 + ; implicit-def: $agpr111 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr143 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr127 + ; implicit-def: $agpr47 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB3_3: + v_readfirstlane_b32 s15, v226 + v_lshlrev_b32_e32 v1, 3, v71 + s_lshr_b32 s24, s15, 2 + s_and_b32 s23, s24, 0x3ffffff0 + v_or_b32_e32 v0, s18, v1 + v_lshlrev_b32_e32 v11, 3, v2 + v_add_u32_e32 v5, s23, v11 + v_mad_u64_u32 v[66:67], s[10:11], v5, s7, v[0:1] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v4, s7, v66 + v_lshlrev_b32_e32 v6, 1, v4 + buffer_load_dwordx4 v[12:15], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[16:19], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v4 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v6, 1, v0 + buffer_load_dwordx4 v[20:23], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[24:27], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v6, 1, v0 + buffer_load_dwordx4 v[28:31], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[32:35], v6, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[36:39], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[40:43], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 12, v2 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + v_lshl_or_b32 v9, v228, 8, v0 + v_or_b32_e32 v0, s19, v1 + s_lshr_b32 s25, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s24, s24, 0x3fffffe0 + v_and_or_b32 v1, s25, 32, v71 + v_or_b32_e32 v7, s24, v71 + v_lshrrev_b32_e32 v4, 3, v1 + v_lshrrev_b32_e32 v8, 3, v7 + v_mad_u64_u32 v[68:69], s[24:25], v5, s20, v[0:1] + v_xor_b32_e32 v5, v4, v228 + v_xor_b32_e32 v10, v8, v228 + v_lshl_or_b32 v6, v5, 3, v9 + v_lshlrev_b32_e32 v0, 1, v68 + v_add_u32_e32 v1, s20, v68 + v_lshl_add_u32 v9, v10, 3, v9 + v_lshlrev_b32_e32 v52, 1, v1 + v_add_u32_e32 v1, s20, v1 + buffer_load_dwordx4 v[44:47], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v52, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s20, v1 + v_lshlrev_b32_e32 v60, 1, v1 + v_add_u32_e32 v1, s20, v1 + buffer_load_dwordx4 v[52:55], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[56:59], v60, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s20, v1 + v_lshlrev_b32_e32 v64, 1, v1 + v_add_u32_e32 v1, s20, v1 + buffer_load_dwordx4 v[60:63], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[72:75], v64, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_lshl_u32 v1, v1, s20, 1 + buffer_load_dwordx4 v[76:79], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[80:83], v1, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v84, v12, v16, s21 + v_perm_b32 v88, v12, v16, s22 + v_perm_b32 v92, v13, v17, s21 + v_perm_b32 v96, v13, v17, s22 + v_perm_b32 v104, v14, v18, s21 + v_perm_b32 v108, v14, v18, s22 + s_waitcnt vmcnt(12) + v_perm_b32 v85, v20, v24, s21 + v_perm_b32 v89, v20, v24, s22 + v_perm_b32 v93, v21, v25, s21 + v_perm_b32 v97, v21, v25, s22 + v_perm_b32 v105, v22, v26, s21 + s_waitcnt vmcnt(10) + v_perm_b32 v86, v28, v32, s21 + v_perm_b32 v90, v28, v32, s22 + v_perm_b32 v94, v29, v33, s21 + v_perm_b32 v98, v29, v33, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v87, v36, v40, s21 + v_perm_b32 v91, v36, v40, s22 + v_perm_b32 v95, v37, v41, s21 + v_perm_b32 v99, v37, v41, s22 + v_perm_b32 v109, v22, v26, s22 + v_perm_b32 v106, v30, v34, s21 + v_perm_b32 v110, v30, v34, s22 + v_perm_b32 v107, v38, v42, s21 + v_perm_b32 v111, v38, v42, s22 + v_perm_b32 v12, v15, v19, s21 + v_perm_b32 v16, v15, v19, s22 + v_perm_b32 v13, v23, v27, s21 + v_perm_b32 v17, v23, v27, s22 + v_perm_b32 v14, v31, v35, s21 + v_perm_b32 v18, v31, v35, s22 + v_perm_b32 v15, v39, v43, s21 + v_perm_b32 v19, v39, v43, s22 + v_and_b32_e32 v102, 24, v3 + v_add_u32_e32 v0, s23, v102 + v_lshrrev_b32_e32 v1, 2, v0 + v_and_b32_e32 v1, 24, v1 + v_xor_b32_e32 v3, v1, v71 + v_lshlrev_b32_e32 v20, 9, v0 + v_and_b32_e32 v20, 0x3000, v20 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v0, 0x7ffff800, v0 + v_add_lshl_u32 v0, v0, v20, 1 + v_lshl_or_b32 v0, v3, 4, v0 + ds_write_b128 v0, v[84:87] + v_or_b32_e32 v20, 1, v1 + v_xor_b32_e32 v20, v20, v71 + v_sub_u32_e32 v3, v20, v3 + v_lshl_add_u32 v3, v3, 4, v0 + ds_write_b128 v3, v[88:91] offset:512 + v_or_b32_e32 v21, 2, v1 + v_xor_b32_e32 v21, v21, v71 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 4, v20 + s_movk_i32 s23, 0x200 + v_add3_u32 v64, v3, s23, v20 + ds_write_b128 v64, v[92:95] offset:512 + v_or_b32_e32 v20, 3, v1 + v_xor_b32_e32 v20, v20, v71 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v65, v64, s23, v21 + ds_write_b128 v65, v[96:99] offset:512 + v_or_b32_e32 v21, 4, v1 + v_xor_b32_e32 v21, v21, v71 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 4, v20 + v_add3_u32 v67, v65, s23, v20 + ds_write_b128 v67, v[104:107] offset:512 + v_or_b32_e32 v20, 5, v1 + v_xor_b32_e32 v20, v20, v71 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v69, v67, s23, v21 + ds_write_b128 v69, v[108:111] offset:512 + v_or_b32_e32 v21, 6, v1 + v_xor_b32_e32 v21, v21, v71 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 4, v20 + v_add3_u32 v70, v69, s23, v20 + ds_write_b128 v70, v[12:15] offset:512 + v_or_b32_e32 v1, 7, v1 + v_xor_b32_e32 v1, v1, v71 + v_sub_u32_e32 v1, v1, v21 + v_lshlrev_b32_e32 v1, 4, v1 + v_add3_u32 v1, v70, s23, v1 + ds_write_b128 v1, v[16:19] offset:512 + s_waitcnt vmcnt(6) + v_perm_b32 v12, v44, v48, s21 + v_perm_b32 v16, v44, v48, s22 + s_waitcnt vmcnt(4) + v_perm_b32 v13, v52, v56, s21 + v_perm_b32 v17, v52, v56, s22 + s_waitcnt vmcnt(2) + v_perm_b32 v14, v60, v72, s21 + v_perm_b32 v18, v60, v72, s22 + s_waitcnt vmcnt(0) + v_perm_b32 v15, v76, v80, s21 + v_perm_b32 v19, v76, v80, s22 + v_perm_b32 v20, v45, v49, s21 + v_perm_b32 v24, v45, v49, s22 + v_perm_b32 v21, v53, v57, s21 + v_perm_b32 v25, v53, v57, s22 + v_perm_b32 v22, v61, v73, s21 + v_perm_b32 v26, v61, v73, s22 + v_perm_b32 v23, v77, v81, s21 + v_perm_b32 v27, v77, v81, s22 + v_perm_b32 v28, v46, v50, s21 + v_perm_b32 v32, v46, v50, s22 + v_perm_b32 v29, v54, v58, s21 + v_perm_b32 v33, v54, v58, s22 + v_perm_b32 v30, v62, v74, s21 + v_perm_b32 v34, v62, v74, s22 + v_perm_b32 v31, v78, v82, s21 + v_perm_b32 v35, v78, v82, s22 + v_perm_b32 v36, v47, v51, s21 + v_perm_b32 v40, v47, v51, s22 + v_perm_b32 v37, v55, v59, s21 + v_perm_b32 v41, v55, v59, s22 + v_perm_b32 v38, v63, v75, s21 + v_perm_b32 v42, v63, v75, s22 + v_perm_b32 v39, v79, v83, s21 + v_perm_b32 v43, v79, v83, s22 + ds_write_b128 v0, v[12:15] offset:32768 + ds_write_b128 v3, v[16:19] offset:33280 + ds_write_b128 v64, v[20:23] offset:33280 + ds_write_b128 v65, v[24:27] offset:33280 + ds_write_b128 v67, v[28:31] offset:33280 + ds_write_b128 v69, v[32:35] offset:33280 + ds_write_b128 v70, v[36:39] offset:33280 + ds_write_b128 v1, v[40:43] offset:33280 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v13, 16, v11 + v_add_u32_e32 v1, 48, v11 + v_add_u32_e32 v0, 64, v7 + v_or_b32_e32 v12, 8, v4 + v_or_b32_e32 v11, 16, v4 + v_or_b32_e32 v3, 24, v4 + s_cbranch_vccnz .LBB3_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit768.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_lshrrev_b32_e32 v14, 5, v13 + v_bfe_u32 v15, v13, 3, 2 + v_lshl_or_b32 v16, v14, 3, v228 + v_xor_b32_e32 v17, v8, v16 + v_sub_u32_e32 v18, v17, v10 + v_lshlrev_b32_e32 v19, 11, v14 + v_lshlrev_b32_e32 v18, 3, v18 + v_sub_u32_e32 v20, v15, v2 + v_lshl_or_b32 v19, v20, 12, v19 + v_add3_u32 v74, v9, v19, v18 + v_xor_b32_e32 v14, 1, v14 + v_sub_u32_e32 v15, v2, v15 + v_lshl_add_u32 v18, v14, 3, v16 + v_xor_b32_e32 v20, v8, v18 + v_sub_u32_e32 v17, v20, v17 + v_lshlrev_b32_e32 v14, 11, v14 + v_lshlrev_b32_e32 v17, 3, v17 + v_lshl_or_b32 v14, v15, 12, v14 + v_add3_u32 v75, v17, v14, v74 + v_lshrrev_b32_e32 v15, 5, v1 + v_add_u32_e32 v17, -1, v15 + v_bfe_u32 v21, v1, 3, 2 + v_sub_u32_e32 v22, v21, v2 + v_lshl_add_u32 v23, v17, 3, v18 + v_ashrrev_i32_e32 v24, 31, v23 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v23, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v24, v23, v24 + v_xor_b32_e32 v25, v8, v24 + v_sub_u32_e32 v20, v25, v20 + v_lshlrev_b32_e32 v17, 11, v17 + v_lshlrev_b32_e32 v20, 3, v20 + v_lshl_add_u32 v17, v22, 12, v17 + v_add3_u32 v67, v20, v17, v75 + v_lshrrev_b32_e32 v20, 3, v0 + v_sub_u32_e32 v21, v2, v21 + v_lshlrev_b32_e32 v22, 3, v15 + v_sub_u32_e32 v22, v23, v22 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshrrev_b32_e32 v23, 27, v23 + v_add_u32_e32 v23, v22, v23 + v_and_b32_e32 v23, 0xffffffe0, v23 + v_sub_u32_e32 v22, v22, v23 + v_xor_b32_e32 v23, v20, v22 + v_sub_u32_e32 v25, v23, v25 + v_lshlrev_b32_e32 v25, 3, v25 + v_lshlrev_b32_e32 v21, 12, v21 + v_lshlrev_b32_e32 v15, 11, v15 + v_sub_u32_e32 v15, v21, v15 + v_add3_u32 v93, v25, v15, v67 + v_xor_b32_e32 v21, v20, v16 + v_sub_u32_e32 v23, v21, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v76, v23, v19, v93 + v_xor_b32_e32 v23, v20, v18 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v77, v21, v14, v76 + v_xor_b32_e32 v20, v20, v24 + v_sub_u32_e32 v21, v20, v23 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v69, v21, v17, v77 + v_add_u32_e32 v21, 0x80, v7 + v_lshrrev_b32_e32 v21, 3, v21 + v_xor_b32_e32 v23, v21, v22 + v_sub_u32_e32 v20, v23, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v92, v20, v15, v69 + v_xor_b32_e32 v20, v21, v16 + v_sub_u32_e32 v23, v20, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v78, v23, v19, v92 + v_xor_b32_e32 v23, v21, v18 + v_sub_u32_e32 v20, v23, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v79, v20, v14, v78 + v_xor_b32_e32 v20, v21, v24 + v_sub_u32_e32 v21, v20, v23 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v72, v21, v17, v79 + v_add_u32_e32 v21, 0xc0, v7 + v_lshrrev_b32_e32 v21, 3, v21 + v_xor_b32_e32 v23, v21, v22 + v_sub_u32_e32 v20, v23, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v91, v20, v15, v72 + v_xor_b32_e32 v20, v21, v16 + v_sub_u32_e32 v23, v20, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v80, v23, v19, v91 + v_xor_b32_e32 v23, v21, v18 + v_sub_u32_e32 v20, v23, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v81, v20, v14, v80 + v_xor_b32_e32 v20, v21, v24 + v_sub_u32_e32 v20, v20, v23 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v73, v20, v17, v81 + v_xor_b32_e32 v20, v4, v16 + v_sub_u32_e32 v21, v20, v5 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v88, v6, v19, v21 + v_xor_b32_e32 v21, v4, v18 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v82, v20, v14, v88 + v_xor_b32_e32 v20, v4, v24 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v83, v21, v17, v82 + v_xor_b32_e32 v21, v12, v22 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v94, v20, v15, v83 + v_xor_b32_e32 v20, v12, v16 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v95, v21, v19, v94 + v_xor_b32_e32 v21, v12, v18 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v84, v20, v14, v95 + v_xor_b32_e32 v20, v12, v24 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v85, v21, v17, v84 + v_xor_b32_e32 v21, v11, v22 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v96, v20, v15, v85 + v_xor_b32_e32 v20, v11, v16 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v97, v21, v19, v96 + v_xor_b32_e32 v21, v11, v18 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v86, v20, v14, v97 + v_xor_b32_e32 v20, v11, v24 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v87, v21, v17, v86 + v_xor_b32_e32 v21, v3, v22 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v98, v20, v15, v87 + v_xor_b32_e32 v15, v3, v16 + v_sub_u32_e32 v16, v15, v21 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v99, v16, v19, v98 + v_xor_b32_e32 v16, v3, v18 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 3, v15 + v_add3_u32 v89, v15, v14, v99 + v_xor_b32_e32 v14, v3, v24 + v_sub_u32_e32 v14, v14, v16 + v_lshlrev_b32_e32 v14, 3, v14 + v_add3_u32 v90, v14, v17, v89 + s_mov_b64 s[2:3], 0 + s_branch .LBB3_6 +.LBB3_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr90 +.LBB3_6: ; %Flow42 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_lshlrev_b32_e32 v101, 1, v9 + v_lshlrev_b32_e32 v100, 1, v6 + s_cbranch_vccnz .LBB3_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1666.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s20, 6 + s_lshl_b32 s6, s7, 6 + v_lshrrev_b32_e32 v14, 5, v13 + v_bfe_u32 v13, v13, 3, 2 + v_lshl_or_b32 v15, v14, 3, v228 + v_xor_b32_e32 v16, v8, v15 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v17, 11, v14 + v_lshlrev_b32_e32 v10, 3, v10 + v_sub_u32_e32 v18, v13, v2 + v_lshl_or_b32 v17, v18, 12, v17 + v_add3_u32 v74, v9, v17, v10 + v_xor_b32_e32 v9, 1, v14 + v_sub_u32_e32 v10, v2, v13 + v_lshl_add_u32 v13, v9, 3, v15 + v_xor_b32_e32 v14, v8, v13 + v_sub_u32_e32 v16, v14, v16 + v_lshlrev_b32_e32 v9, 11, v9 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshl_or_b32 v9, v10, 12, v9 + v_add3_u32 v75, v16, v9, v74 + v_lshrrev_b32_e32 v10, 5, v1 + v_add_u32_e32 v16, -1, v10 + v_bfe_u32 v1, v1, 3, 2 + v_sub_u32_e32 v18, v1, v2 + v_lshl_add_u32 v19, v16, 3, v13 + v_ashrrev_i32_e32 v20, 31, v19 + v_lshrrev_b32_e32 v20, 27, v20 + v_add_u32_e32 v20, v19, v20 + v_and_b32_e32 v20, 0xffffffe0, v20 + v_sub_u32_e32 v20, v19, v20 + v_xor_b32_e32 v8, v8, v20 + v_sub_u32_e32 v14, v8, v14 + v_lshlrev_b32_e32 v16, 11, v16 + v_lshlrev_b32_e32 v14, 3, v14 + v_lshl_add_u32 v16, v18, 12, v16 + v_add3_u32 v67, v14, v16, v75 + v_lshrrev_b32_e32 v0, 3, v0 + v_sub_u32_e32 v1, v2, v1 + v_lshlrev_b32_e32 v2, 3, v10 + v_sub_u32_e32 v2, v19, v2 + v_ashrrev_i32_e32 v14, 31, v2 + v_lshrrev_b32_e32 v14, 27, v14 + v_add_u32_e32 v14, v2, v14 + v_and_b32_e32 v14, 0xffffffe0, v14 + v_sub_u32_e32 v2, v2, v14 + v_xor_b32_e32 v14, v0, v2 + v_sub_u32_e32 v8, v14, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v10, 11, v10 + v_sub_u32_e32 v1, v1, v10 + v_add3_u32 v93, v8, v1, v67 + v_xor_b32_e32 v8, v0, v15 + v_sub_u32_e32 v10, v8, v14 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v76, v10, v17, v93 + v_xor_b32_e32 v10, v0, v13 + v_sub_u32_e32 v8, v10, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v77, v8, v9, v76 + v_xor_b32_e32 v0, v0, v20 + v_sub_u32_e32 v8, v0, v10 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v69, v8, v16, v77 + v_add_u32_e32 v8, 0x80, v7 + v_lshrrev_b32_e32 v8, 3, v8 + v_xor_b32_e32 v10, v8, v2 + v_sub_u32_e32 v0, v10, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v92, v0, v1, v69 + v_xor_b32_e32 v0, v8, v15 + v_sub_u32_e32 v10, v0, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v78, v10, v17, v92 + v_xor_b32_e32 v10, v8, v13 + v_sub_u32_e32 v0, v10, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v79, v0, v9, v78 + v_xor_b32_e32 v0, v8, v20 + v_sub_u32_e32 v8, v0, v10 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v72, v8, v16, v79 + v_add_u32_e32 v7, 0xc0, v7 + v_lshrrev_b32_e32 v7, 3, v7 + v_xor_b32_e32 v8, v7, v2 + v_sub_u32_e32 v0, v8, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v91, v0, v1, v72 + v_xor_b32_e32 v0, v7, v15 + v_sub_u32_e32 v8, v0, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v80, v8, v17, v91 + v_xor_b32_e32 v8, v7, v13 + v_sub_u32_e32 v0, v8, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v81, v0, v9, v80 + v_xor_b32_e32 v0, v7, v20 + v_sub_u32_e32 v0, v0, v8 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v73, v0, v16, v81 + v_xor_b32_e32 v0, v4, v15 + v_sub_u32_e32 v5, v0, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v88, v6, v17, v5 + v_xor_b32_e32 v5, v4, v13 + v_sub_u32_e32 v0, v5, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v82, v0, v9, v88 + v_xor_b32_e32 v0, v4, v20 + v_sub_u32_e32 v4, v0, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v83, v4, v16, v82 + v_xor_b32_e32 v4, v12, v2 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v94, v0, v1, v83 + v_xor_b32_e32 v0, v12, v15 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v95, v4, v17, v94 + v_xor_b32_e32 v4, v12, v13 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v84, v0, v9, v95 + v_xor_b32_e32 v0, v12, v20 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v85, v4, v16, v84 + v_xor_b32_e32 v4, v11, v2 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v96, v0, v1, v85 + v_xor_b32_e32 v0, v11, v15 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v97, v4, v17, v96 + v_xor_b32_e32 v4, v11, v13 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v86, v0, v9, v97 + v_xor_b32_e32 v0, v11, v20 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v87, v4, v16, v86 + v_xor_b32_e32 v2, v3, v2 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v98, v0, v1, v87 + v_xor_b32_e32 v0, v3, v15 + v_sub_u32_e32 v1, v0, v2 + v_lshlrev_b32_e32 v1, 3, v1 + v_add3_u32 v99, v1, v17, v98 + v_xor_b32_e32 v1, v3, v13 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v89, v0, v9, v99 + v_xor_b32_e32 v0, v3, v20 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v90, v0, v16, v89 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 +.LBB3_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1666.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v68, s2, v68 + v_add_u32_e32 v66, s6, v66 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v1, s7, v66 + v_lshlrev_b32_e32 v2, 1, v68 + v_add_u32_e32 v3, s20, v68 + v_lshlrev_b32_e32 v4, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[30:33], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s20, v3 + buffer_load_dwordx4 v[58:61], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[50:53], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s20, v3 + v_lshlrev_b32_e32 v4, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[22:25], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s20, v3 + buffer_load_dwordx4 v[46:49], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[38:41], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s20, v3 + v_lshlrev_b32_e32 v4, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[10:13], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s20, v3 + buffer_load_dwordx4 v[34:37], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[42:45], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_lshl_u32 v1, v1, s7, 1 + buffer_load_dwordx4 v[26:29], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_lshl_u32 v6, v3, s20, 1 + buffer_load_dwordx4 v[14:17], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[18:21], v1, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v2, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[6:9], v6, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[108:111], v101 + ds_read_b128 v[104:107], v100 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[108:109], v[104:105], a[112:127] + v_lshlrev_b32_e32 v0, 1, v94 + ds_read_b128 v[112:115], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v95 + ds_read_b128 v[116:119], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[108:109], v[112:113], a[96:111] + v_lshlrev_b32_e32 v0, 1, v96 + ds_read_b128 v[120:123], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v97 + ds_read_b128 v[124:127], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[108:109], v[120:121], a[80:95] + v_lshlrev_b32_e32 v0, 1, v98 + ds_read_b128 v[128:131], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v99 + ds_read_b128 v[132:135], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[108:109], v[128:129], a[128:143] + v_lshlrev_b32_e32 v0, 1, v93 + ds_read_b128 v[136:139], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[144:159], v[136:137], v[104:105], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[136:137], v[112:113], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[136:137], v[120:121], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[136:137], v[128:129], a[160:175] + v_lshlrev_b32_e32 v0, 1, v92 + ds_read_b128 v[140:143], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[140:141], v[104:105], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[140:141], v[112:113], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[140:141], v[120:121], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[140:141], v[128:129], a[224:239] + v_lshlrev_b32_e32 v0, 1, v91 + ds_read_b128 v[144:147], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[104:105], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[144:145], v[112:113], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[144:145], v[120:121], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[144:145], v[128:129], a[48:63] + v_mfma_f32_32x32x8_f16 a[112:127], v[110:111], v[106:107], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[110:111], v[114:115], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[110:111], v[122:123], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[110:111], v[130:131], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[138:139], v[106:107], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[138:139], v[114:115], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[138:139], v[122:123], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[138:139], v[130:131], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[142:143], v[106:107], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[114:115], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[122:123], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[130:131], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[106:107], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[146:147], v[114:115], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[146:147], v[122:123], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[146:147], v[130:131], a[48:63] + v_lshlrev_b32_e32 v0, 1, v74 + ds_read_b128 v[104:107], v0 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[108:111], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[120:123], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[104:105], v[108:109], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[104:105], v[116:117], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[104:105], v[124:125], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[104:105], v[132:133], a[128:143] + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[112:115], v0 + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[128:131], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[144:159], v[112:113], v[108:109], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[112:113], v[116:117], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[112:113], v[124:125], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[112:113], v[132:133], a[160:175] + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[136:139], v0 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[140:143], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[136:137], v[108:109], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[136:137], v[116:117], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[136:137], v[124:125], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[136:137], v[132:133], a[224:239] + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[144:147], v0 + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[148:151], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[108:109], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[144:145], v[116:117], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[144:145], v[124:125], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[144:145], v[132:133], a[48:63] + v_mfma_f32_32x32x8_f16 a[112:127], v[106:107], v[110:111], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[106:107], v[118:119], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[106:107], v[126:127], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[106:107], v[134:135], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[114:115], v[110:111], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[114:115], v[118:119], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[114:115], v[126:127], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[114:115], v[134:135], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[138:139], v[110:111], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[138:139], v[118:119], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[138:139], v[126:127], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[138:139], v[134:135], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[110:111], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[146:147], v[118:119], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[146:147], v[126:127], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[146:147], v[134:135], a[48:63] + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[124:127], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[116:119], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[124:125], a[112:127] + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[132:135], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[112:115], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[120:121], v[132:133], a[96:111] + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[136:139], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[108:111], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[120:121], v[136:137], a[80:95] + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[144:147], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v90 + ds_read_b128 v[104:107], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[120:121], v[144:145], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[128:129], v[124:125], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[128:129], v[132:133], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[128:129], v[136:137], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[128:129], v[144:145], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[140:141], v[124:125], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[140:141], v[132:133], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[140:141], v[136:137], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[140:141], v[144:145], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[124:125], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[148:149], v[132:133], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[148:149], v[136:137], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[148:149], v[144:145], a[48:63] + v_mfma_f32_32x32x8_f16 a[112:127], v[122:123], v[126:127], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[122:123], v[134:135], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[122:123], v[138:139], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[122:123], v[146:147], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[130:131], v[126:127], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[130:131], v[134:135], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[130:131], v[138:139], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[130:131], v[146:147], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[142:143], v[126:127], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[134:135], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[138:139], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[146:147], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[150:151], v[126:127], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[134:135], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[138:139], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[146:147], a[48:63] + v_lshlrev_b32_e32 v0, 1, v67 + ds_read_b128 v[120:123], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[116:117], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[120:121], v[112:113], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[120:121], v[108:109], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[120:121], v[104:105], a[128:143] + v_lshlrev_b32_e32 v0, 1, v69 + ds_read_b128 v[124:127], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[144:159], v[124:125], v[116:117], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[124:125], v[112:113], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[124:125], v[108:109], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[124:125], v[104:105], a[160:175] + v_lshlrev_b32_e32 v0, 1, v72 + ds_read_b128 v[128:131], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[128:129], v[116:117], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[128:129], v[112:113], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[128:129], v[108:109], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[128:129], v[104:105], a[224:239] + v_lshlrev_b32_e32 v0, 1, v73 + ds_read_b128 v[132:135], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[240:255], v[132:133], v[116:117], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[132:133], v[112:113], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[132:133], v[108:109], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[132:133], v[104:105], a[48:63] + v_mfma_f32_32x32x8_f16 a[112:127], v[122:123], v[118:119], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[122:123], v[114:115], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[122:123], v[110:111], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[122:123], v[106:107], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[126:127], v[118:119], a[144:159] + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_f32_32x32x8_f16 a[0:15], v[126:127], v[110:111], a[0:15] + v_mfma_f32_32x32x8_f16 a[160:175], v[126:127], v[106:107], a[160:175] + s_add_i32 s24, s3, -1 + v_readfirstlane_b32 s25, v226 + s_lshr_b32 s25, s25, 2 + v_mfma_f32_32x32x8_f16 a[176:191], v[130:131], v[118:119], a[176:191] + s_and_b32 s25, s25, 0x3ffffff0 + v_add_u32_e32 v0, s25, v102 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s24 + v_lshrrev_b32_e32 v1, 2, v0 + v_lshlrev_b32_e32 v70, 9, v0 + v_lshlrev_b32_e32 v0, 6, v0 + v_mfma_f32_32x32x8_f16 a[192:207], v[130:131], v[114:115], a[192:207] + v_and_b32_e32 v1, 24, v1 + v_and_b32_e32 v70, 0x3000, v70 + v_and_b32_e32 v0, 0x7ffff800, v0 + v_xor_b32_e32 v103, v1, v71 + v_add_lshl_u32 v0, v0, v70, 1 + v_or_b32_e32 v70, 1, v1 + v_or_b32_e32 v104, 2, v1 + v_mfma_f32_32x32x8_f16 a[208:223], v[130:131], v[110:111], a[208:223] + v_or_b32_e32 v105, 3, v1 + v_or_b32_e32 v108, 4, v1 + v_or_b32_e32 v109, 5, v1 + v_or_b32_e32 v112, 6, v1 + v_or_b32_e32 v1, 7, v1 + v_lshl_or_b32 v0, v103, 4, v0 + v_xor_b32_e32 v70, v70, v71 + v_mfma_f32_32x32x8_f16 a[224:239], v[130:131], v[106:107], a[224:239] + v_xor_b32_e32 v104, v104, v71 + v_xor_b32_e32 v105, v105, v71 + v_xor_b32_e32 v108, v108, v71 + v_xor_b32_e32 v109, v109, v71 + v_xor_b32_e32 v112, v112, v71 + v_xor_b32_e32 v1, v1, v71 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[240:255], v[134:135], v[118:119], a[240:255] + s_barrier + v_sub_u32_e32 v103, v70, v103 + v_sub_u32_e32 v70, v104, v70 + v_sub_u32_e32 v104, v105, v104 + v_sub_u32_e32 v105, v108, v105 + v_sub_u32_e32 v108, v109, v108 + v_sub_u32_e32 v109, v112, v109 + v_mfma_f32_32x32x8_f16 a[32:47], v[134:135], v[114:115], a[32:47] + v_sub_u32_e32 v1, v1, v112 + v_lshl_add_u32 v103, v103, 4, v0 + v_lshlrev_b32_e32 v70, 4, v70 + v_lshlrev_b32_e32 v104, 4, v104 + v_lshlrev_b32_e32 v105, 4, v105 + v_lshlrev_b32_e32 v108, 4, v108 + v_lshlrev_b32_e32 v109, 4, v109 + v_mfma_f32_32x32x8_f16 a[16:31], v[134:135], v[110:111], a[16:31] + v_lshlrev_b32_e32 v1, 4, v1 + v_add3_u32 v70, v103, s23, v70 + v_add3_u32 v152, v70, s23, v104 + v_add3_u32 v153, v152, s23, v105 + v_add3_u32 v154, v153, s23, v108 + v_add3_u32 v155, v154, s23, v109 + v_add3_u32 v1, v155, s23, v1 + v_mfma_f32_32x32x8_f16 a[48:63], v[134:135], v[106:107], a[48:63] + s_waitcnt vmcnt(13) + v_perm_b32 v104, v58, v62, s21 + v_perm_b32 v58, v58, v62, s22 + v_perm_b32 v62, v59, v63, s21 + v_perm_b32 v108, v59, v63, s22 + v_perm_b32 v112, v60, v64, s21 + v_perm_b32 v116, v60, v64, s22 + v_perm_b32 v120, v61, v65, s21 + v_perm_b32 v124, v61, v65, s22 + s_waitcnt vmcnt(12) + v_perm_b32 v128, v30, v50, s21 + v_perm_b32 v30, v30, v50, s22 + v_perm_b32 v50, v31, v51, s21 + v_perm_b32 v132, v31, v51, s22 + v_perm_b32 v136, v32, v52, s21 + v_perm_b32 v140, v32, v52, s22 + v_perm_b32 v144, v33, v53, s21 + v_perm_b32 v148, v33, v53, s22 + s_waitcnt vmcnt(9) + v_perm_b32 v105, v46, v54, s21 + v_perm_b32 v59, v46, v54, s22 + v_perm_b32 v63, v47, v55, s21 + v_perm_b32 v109, v47, v55, s22 + v_perm_b32 v113, v48, v56, s21 + v_perm_b32 v117, v48, v56, s22 + v_perm_b32 v121, v49, v57, s21 + v_perm_b32 v125, v49, v57, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v129, v22, v38, s21 + v_perm_b32 v31, v22, v38, s22 + v_perm_b32 v51, v23, v39, s21 + v_perm_b32 v133, v23, v39, s22 + v_perm_b32 v137, v24, v40, s21 + v_perm_b32 v141, v24, v40, s22 + v_perm_b32 v145, v25, v41, s21 + v_perm_b32 v149, v25, v41, s22 + s_waitcnt vmcnt(5) + v_perm_b32 v106, v34, v42, s21 + v_perm_b32 v60, v34, v42, s22 + v_perm_b32 v64, v35, v43, s21 + v_perm_b32 v110, v35, v43, s22 + v_perm_b32 v114, v36, v44, s21 + v_perm_b32 v118, v36, v44, s22 + v_perm_b32 v122, v37, v45, s21 + v_perm_b32 v126, v37, v45, s22 + s_waitcnt vmcnt(4) + v_perm_b32 v130, v10, v26, s21 + v_perm_b32 v32, v10, v26, s22 + v_perm_b32 v52, v11, v27, s21 + v_perm_b32 v134, v11, v27, s22 + v_perm_b32 v138, v12, v28, s21 + v_perm_b32 v142, v12, v28, s22 + v_perm_b32 v146, v13, v29, s21 + v_perm_b32 v150, v13, v29, s22 + s_waitcnt vmcnt(2) + v_perm_b32 v107, v14, v18, s21 + v_perm_b32 v61, v14, v18, s22 + v_perm_b32 v65, v15, v19, s21 + v_perm_b32 v111, v15, v19, s22 + v_perm_b32 v115, v16, v20, s21 + v_perm_b32 v119, v16, v20, s22 + v_perm_b32 v123, v17, v21, s21 + v_perm_b32 v127, v17, v21, s22 + s_waitcnt vmcnt(0) + v_perm_b32 v131, v2, v6, s21 + v_perm_b32 v33, v2, v6, s22 + v_perm_b32 v53, v3, v7, s21 + v_perm_b32 v135, v3, v7, s22 + v_perm_b32 v139, v4, v8, s21 + v_perm_b32 v143, v4, v8, s22 + v_perm_b32 v147, v5, v9, s21 + v_perm_b32 v151, v5, v9, s22 + ds_write_b128 v0, v[104:107] + ds_write_b128 v103, v[58:61] offset:512 + ds_write_b128 v70, v[62:65] offset:512 + ds_write_b128 v152, v[108:111] offset:512 + ds_write_b128 v153, v[112:115] offset:512 + ds_write_b128 v154, v[116:119] offset:512 + ds_write_b128 v155, v[120:123] offset:512 + ds_write_b128 v1, v[124:127] offset:512 + ds_write_b128 v0, v[128:131] offset:32768 + ds_write_b128 v103, v[30:33] offset:33280 + ds_write_b128 v70, v[50:53] offset:33280 + ds_write_b128 v152, v[132:135] offset:33280 + ds_write_b128 v153, v[136:139] offset:33280 + ds_write_b128 v154, v[140:143] offset:33280 + ds_write_b128 v155, v[144:147] offset:33280 + ds_write_b128 v1, v[148:151] offset:33280 + s_cbranch_scc1 .LBB3_8 +.LBB3_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_R + v_accvgpr_read_b32 v137, a3 + v_accvgpr_read_b32 v138, a4 + v_accvgpr_read_b32 v139, a5 + v_accvgpr_read_b32 v140, a6 + v_accvgpr_read_b32 v141, a7 + v_accvgpr_read_b32 v142, a8 + v_accvgpr_read_b32 v143, a9 + v_accvgpr_read_b32 v144, a10 + v_accvgpr_read_b32 v145, a11 + v_accvgpr_read_b32 v146, a12 + v_accvgpr_read_b32 v147, a13 + v_accvgpr_read_b32 v148, a14 + v_accvgpr_read_b32 v149, a15 + v_accvgpr_read_b32 v118, a160 + v_accvgpr_read_b32 v119, a161 + v_accvgpr_read_b32 v120, a162 + v_accvgpr_read_b32 v121, a163 + v_accvgpr_read_b32 v122, a164 + v_accvgpr_read_b32 v123, a165 + v_accvgpr_read_b32 v124, a166 + v_accvgpr_read_b32 v125, a167 + v_accvgpr_read_b32 v126, a168 + v_accvgpr_read_b32 v127, a169 + v_accvgpr_read_b32 v128, a170 + v_accvgpr_read_b32 v129, a171 + v_accvgpr_read_b32 v130, a172 + v_accvgpr_read_b32 v131, a173 + v_accvgpr_read_b32 v132, a174 + v_accvgpr_read_b32 v133, a175 + v_accvgpr_read_b32 v102, a192 + v_accvgpr_read_b32 v103, a193 + v_accvgpr_read_b32 v104, a194 + v_accvgpr_read_b32 v105, a195 + v_accvgpr_read_b32 v106, a196 + v_accvgpr_read_b32 v107, a197 + v_accvgpr_read_b32 v108, a198 + v_accvgpr_read_b32 v109, a199 + v_accvgpr_read_b32 v110, a200 + v_accvgpr_read_b32 v111, a201 + v_accvgpr_read_b32 v112, a202 + v_accvgpr_read_b32 v113, a203 + v_accvgpr_read_b32 v114, a204 + v_accvgpr_read_b32 v115, a205 + v_accvgpr_read_b32 v116, a206 + v_accvgpr_read_b32 v117, a207 + v_accvgpr_read_b32 v48, a208 + v_accvgpr_read_b32 v49, a209 + v_accvgpr_read_b32 v50, a210 + v_accvgpr_read_b32 v51, a211 + v_accvgpr_read_b32 v52, a212 + v_accvgpr_read_b32 v53, a213 + v_accvgpr_read_b32 v54, a214 + v_accvgpr_read_b32 v55, a215 + v_accvgpr_read_b32 v56, a216 + v_accvgpr_read_b32 v57, a217 + v_accvgpr_read_b32 v58, a218 + v_accvgpr_read_b32 v59, a219 + v_accvgpr_read_b32 v60, a220 + v_accvgpr_read_b32 v61, a221 + v_accvgpr_read_b32 v62, a222 + v_accvgpr_read_b32 v63, a223 + v_accvgpr_read_b32 v32, a224 + v_accvgpr_read_b32 v33, a225 + v_accvgpr_read_b32 v34, a226 + v_accvgpr_read_b32 v35, a227 + v_accvgpr_read_b32 v36, a228 + v_accvgpr_read_b32 v37, a229 + v_accvgpr_read_b32 v38, a230 + v_accvgpr_read_b32 v39, a231 + v_accvgpr_read_b32 v40, a232 + v_accvgpr_read_b32 v41, a233 + v_accvgpr_read_b32 v42, a234 + v_accvgpr_read_b32 v43, a235 + v_accvgpr_read_b32 v44, a236 + v_accvgpr_read_b32 v45, a237 + v_accvgpr_read_b32 v46, a238 + v_accvgpr_read_b32 v47, a239 + v_accvgpr_read_b32 v16, a240 + v_accvgpr_read_b32 v17, a241 + v_accvgpr_read_b32 v18, a242 + v_accvgpr_read_b32 v19, a243 + v_accvgpr_read_b32 v20, a244 + v_accvgpr_read_b32 v21, a245 + v_accvgpr_read_b32 v22, a246 + v_accvgpr_read_b32 v23, a247 + v_accvgpr_read_b32 v24, a248 + v_accvgpr_read_b32 v25, a249 + v_accvgpr_read_b32 v26, a250 + v_accvgpr_read_b32 v27, a251 + v_accvgpr_read_b32 v28, a252 + v_accvgpr_read_b32 v29, a253 + v_accvgpr_read_b32 v30, a254 + v_accvgpr_read_b32 v31, a255 + v_accvgpr_read_b32 v0, a32 + v_accvgpr_read_b32 v1, a33 + v_accvgpr_read_b32 v2, a34 + v_accvgpr_read_b32 v3, a35 + v_accvgpr_read_b32 v4, a36 + v_accvgpr_read_b32 v5, a37 + v_accvgpr_read_b32 v6, a38 + v_accvgpr_read_b32 v7, a39 + v_accvgpr_read_b32 v8, a40 + v_accvgpr_read_b32 v9, a41 + v_accvgpr_read_b32 v10, a42 + v_accvgpr_read_b32 v11, a43 + v_accvgpr_read_b32 v12, a44 + v_accvgpr_read_b32 v13, a45 + v_accvgpr_read_b32 v14, a46 + v_accvgpr_read_b32 v15, a47 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + v_accvgpr_read_b32 v136, a2 + v_accvgpr_read_b32 v135, a1 + v_accvgpr_read_b32 v134, a0 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[150:153], v101 + ds_read_b128 v[154:157], v100 offset:32768 + v_accvgpr_mov_b32 a0, a112 + v_accvgpr_mov_b32 a1, a113 + v_accvgpr_mov_b32 a2, a114 + v_accvgpr_mov_b32 a3, a115 + v_accvgpr_mov_b32 a4, a116 + v_accvgpr_mov_b32 a5, a117 + v_accvgpr_mov_b32 a6, a118 + v_accvgpr_mov_b32 a7, a119 + v_accvgpr_mov_b32 a8, a120 + v_accvgpr_mov_b32 a9, a121 + v_accvgpr_mov_b32 a10, a122 + v_accvgpr_mov_b32 a11, a123 + v_accvgpr_mov_b32 a12, a124 + v_accvgpr_mov_b32 a13, a125 + v_accvgpr_mov_b32 a14, a126 + v_accvgpr_mov_b32 a15, a127 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[154:155], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[156:157], a[0:15] + v_lshlrev_b32_e32 v64, 1, v94 + ds_read_b128 v[158:161], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v95 + v_accvgpr_mov_b32 a32, a96 + v_accvgpr_mov_b32 a33, a97 + v_accvgpr_mov_b32 a34, a98 + v_accvgpr_mov_b32 a35, a99 + v_accvgpr_mov_b32 a36, a100 + v_accvgpr_mov_b32 a37, a101 + v_accvgpr_mov_b32 a38, a102 + v_accvgpr_mov_b32 a39, a103 + v_accvgpr_mov_b32 a40, a104 + v_accvgpr_mov_b32 a41, a105 + v_accvgpr_mov_b32 a42, a106 + v_accvgpr_mov_b32 a43, a107 + v_accvgpr_mov_b32 a44, a108 + v_accvgpr_mov_b32 a45, a109 + v_accvgpr_mov_b32 a46, a110 + v_accvgpr_mov_b32 a47, a111 + ds_read_b128 v[162:165], v64 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[158:159], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[160:161], a[32:47] + v_lshlrev_b32_e32 v64, 1, v96 + ds_read_b128 v[166:169], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v97 + ds_read_b128 v[94:97], v64 offset:32768 + v_accvgpr_mov_b32 a127, a95 + v_accvgpr_mov_b32 a126, a94 + v_accvgpr_mov_b32 a125, a93 + v_accvgpr_mov_b32 a124, a92 + v_accvgpr_mov_b32 a123, a91 + v_accvgpr_mov_b32 a122, a90 + v_accvgpr_mov_b32 a121, a89 + v_accvgpr_mov_b32 a120, a88 + v_accvgpr_mov_b32 a119, a87 + v_accvgpr_mov_b32 a118, a86 + v_accvgpr_mov_b32 a117, a85 + v_accvgpr_mov_b32 a116, a84 + v_accvgpr_mov_b32 a115, a83 + v_accvgpr_mov_b32 a114, a82 + v_accvgpr_mov_b32 a113, a81 + v_accvgpr_mov_b32 a112, a80 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[150:151], v[166:167], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[152:153], v[168:169], a[112:127] + v_lshlrev_b32_e32 v64, 1, v98 + ds_read_b128 v[170:173], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v99 + ds_read_b128 v[98:101], v64 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[150:151], v[170:171], a[208:223] + v_lshlrev_b32_e32 v64, 1, v93 + v_mfma_f32_32x32x8_f16 a[208:223], v[152:153], v[172:173], a[208:223] + ds_read_b128 v[150:153], v64 + v_accvgpr_mov_b32 a239, a159 + v_accvgpr_mov_b32 a238, a158 + v_accvgpr_mov_b32 a237, a157 + v_accvgpr_mov_b32 a236, a156 + v_accvgpr_mov_b32 a235, a155 + v_accvgpr_mov_b32 a234, a154 + v_accvgpr_mov_b32 a233, a153 + v_accvgpr_mov_b32 a232, a152 + v_accvgpr_mov_b32 a231, a151 + v_accvgpr_mov_b32 a230, a150 + v_accvgpr_mov_b32 a229, a149 + v_accvgpr_mov_b32 a228, a148 + v_accvgpr_mov_b32 a227, a147 + v_accvgpr_mov_b32 a226, a146 + v_accvgpr_mov_b32 a225, a145 + v_accvgpr_mov_b32 a224, a144 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[150:151], v[154:155], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[152:153], v[156:157], a[224:239] + v_accvgpr_mov_b32 a207, a79 + v_accvgpr_mov_b32 a206, a78 + v_accvgpr_mov_b32 a205, a77 + v_accvgpr_mov_b32 a204, a76 + v_accvgpr_mov_b32 a203, a75 + v_accvgpr_mov_b32 a202, a74 + v_accvgpr_mov_b32 a201, a73 + v_accvgpr_mov_b32 a200, a72 + v_accvgpr_mov_b32 a199, a71 + v_accvgpr_mov_b32 a198, a70 + v_accvgpr_mov_b32 a197, a69 + v_accvgpr_mov_b32 a196, a68 + v_accvgpr_mov_b32 a195, a67 + v_accvgpr_mov_b32 a194, a66 + v_accvgpr_mov_b32 a193, a65 + v_accvgpr_mov_b32 a192, a64 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[192:207], v[150:151], v[158:159], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[152:153], v[160:161], a[192:207] + v_accvgpr_write_b32 a175, v149 + v_accvgpr_write_b32 a174, v148 + v_accvgpr_write_b32 a173, v147 + v_accvgpr_write_b32 a172, v146 + v_accvgpr_write_b32 a171, v145 + v_accvgpr_write_b32 a170, v144 + v_accvgpr_write_b32 a169, v143 + v_accvgpr_write_b32 a168, v142 + v_accvgpr_write_b32 a167, v141 + v_accvgpr_write_b32 a166, v140 + v_accvgpr_write_b32 a165, v139 + v_accvgpr_write_b32 a164, v138 + v_accvgpr_write_b32 a163, v137 + v_accvgpr_write_b32 a162, v136 + v_accvgpr_write_b32 a161, v135 + v_accvgpr_write_b32 a160, v134 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[160:175], v[150:151], v[166:167], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[152:153], v[168:169], a[160:175] + v_accvgpr_write_b32 a159, v133 + v_accvgpr_write_b32 a158, v132 + v_accvgpr_write_b32 a157, v131 + v_accvgpr_write_b32 a156, v130 + v_accvgpr_write_b32 a155, v129 + v_accvgpr_write_b32 a154, v128 + v_accvgpr_write_b32 a153, v127 + v_accvgpr_write_b32 a152, v126 + v_accvgpr_write_b32 a151, v125 + v_accvgpr_write_b32 a150, v124 + v_accvgpr_write_b32 a149, v123 + v_accvgpr_write_b32 a148, v122 + v_accvgpr_write_b32 a147, v121 + v_accvgpr_write_b32 a146, v120 + v_accvgpr_write_b32 a145, v119 + v_accvgpr_write_b32 a144, v118 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[144:159], v[150:151], v[170:171], a[144:159] + v_lshlrev_b32_e32 v64, 1, v92 + v_mfma_f32_32x32x8_f16 a[144:159], v[152:153], v[172:173], a[144:159] + ds_read_b128 v[118:121], v64 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[118:119], v[154:155], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[120:121], v[156:157], a[176:191] + v_accvgpr_write_b32 a143, v117 + v_accvgpr_write_b32 a142, v116 + v_accvgpr_write_b32 a141, v115 + v_accvgpr_write_b32 a140, v114 + v_accvgpr_write_b32 a139, v113 + v_accvgpr_write_b32 a138, v112 + v_accvgpr_write_b32 a137, v111 + v_accvgpr_write_b32 a136, v110 + v_accvgpr_write_b32 a135, v109 + v_accvgpr_write_b32 a134, v108 + v_accvgpr_write_b32 a133, v107 + v_accvgpr_write_b32 a132, v106 + v_accvgpr_write_b32 a131, v105 + v_accvgpr_write_b32 a130, v104 + v_accvgpr_write_b32 a129, v103 + v_accvgpr_write_b32 a128, v102 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[128:143], v[118:119], v[158:159], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[120:121], v[160:161], a[128:143] + v_accvgpr_write_b32 a95, v63 + v_accvgpr_write_b32 a94, v62 + v_accvgpr_write_b32 a93, v61 + v_accvgpr_write_b32 a92, v60 + v_accvgpr_write_b32 a91, v59 + v_accvgpr_write_b32 a90, v58 + v_accvgpr_write_b32 a89, v57 + v_accvgpr_write_b32 a88, v56 + v_accvgpr_write_b32 a87, v55 + v_accvgpr_write_b32 a86, v54 + v_accvgpr_write_b32 a85, v53 + v_accvgpr_write_b32 a84, v52 + v_accvgpr_write_b32 a83, v51 + v_accvgpr_write_b32 a82, v50 + v_accvgpr_write_b32 a81, v49 + v_accvgpr_write_b32 a80, v48 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[80:95], v[118:119], v[166:167], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[120:121], v[168:169], a[80:95] + v_accvgpr_write_b32 a79, v47 + v_accvgpr_write_b32 a78, v46 + v_accvgpr_write_b32 a77, v45 + v_accvgpr_write_b32 a76, v44 + v_accvgpr_write_b32 a75, v43 + v_accvgpr_write_b32 a74, v42 + v_accvgpr_write_b32 a73, v41 + v_accvgpr_write_b32 a72, v40 + v_accvgpr_write_b32 a71, v39 + v_accvgpr_write_b32 a70, v38 + v_accvgpr_write_b32 a69, v37 + v_accvgpr_write_b32 a68, v36 + v_accvgpr_write_b32 a67, v35 + v_accvgpr_write_b32 a66, v34 + v_accvgpr_write_b32 a65, v33 + v_accvgpr_write_b32 a64, v32 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], v[118:119], v[170:171], a[64:79] + v_lshlrev_b32_e32 v32, 1, v91 + v_mfma_f32_32x32x8_f16 a[64:79], v[120:121], v[172:173], a[64:79] + ds_read_b128 v[32:35], v32 + v_accvgpr_write_b32 a111, v31 + v_accvgpr_write_b32 a110, v30 + v_accvgpr_write_b32 a109, v29 + v_accvgpr_write_b32 a108, v28 + v_accvgpr_write_b32 a107, v27 + v_accvgpr_write_b32 a106, v26 + v_accvgpr_write_b32 a105, v25 + v_accvgpr_write_b32 a104, v24 + v_accvgpr_write_b32 a103, v23 + v_accvgpr_write_b32 a102, v22 + v_accvgpr_write_b32 a101, v21 + v_accvgpr_write_b32 a100, v20 + v_accvgpr_write_b32 a99, v19 + v_accvgpr_write_b32 a98, v18 + v_accvgpr_write_b32 a97, v17 + v_accvgpr_write_b32 a96, v16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[32:33], v[154:155], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[34:35], v[156:157], a[96:111] + v_accvgpr_write_b32 a63, v15 + v_accvgpr_write_b32 a62, v14 + v_accvgpr_write_b32 a61, v13 + v_accvgpr_write_b32 a60, v12 + v_accvgpr_write_b32 a59, v11 + v_accvgpr_write_b32 a58, v10 + v_accvgpr_write_b32 a57, v9 + v_accvgpr_write_b32 a56, v8 + v_accvgpr_write_b32 a55, v7 + v_accvgpr_write_b32 a54, v6 + v_accvgpr_write_b32 a53, v5 + v_accvgpr_write_b32 a52, v4 + v_accvgpr_write_b32 a51, v3 + v_accvgpr_write_b32 a50, v2 + v_accvgpr_write_b32 a49, v1 + v_accvgpr_write_b32 a48, v0 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[48:63], v[32:33], v[158:159], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[34:35], v[160:161], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[32:33], v[166:167], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[34:35], v[168:169], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[32:33], v[170:171], a[240:255] + v_lshlrev_b32_e32 v0, 1, v74 + v_mfma_f32_32x32x8_f16 a[240:255], v[34:35], v[172:173], a[240:255] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[6:9], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[10:13], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[6:7], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[4:5], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[162:163], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[4:5], v[164:165], a[32:47] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[94:95], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[4:5], v[96:97], a[112:127] + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[98:99], a[208:223] + v_lshlrev_b32_e32 v0, 1, v76 + v_mfma_f32_32x32x8_f16 a[208:223], v[4:5], v[100:101], a[208:223] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[14:17], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[162:163], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[4:5], v[164:165], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[94:95], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[4:5], v[96:97], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[98:99], a[144:159] + v_lshlrev_b32_e32 v0, 1, v78 + v_mfma_f32_32x32x8_f16 a[144:159], v[4:5], v[100:101], a[144:159] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[18:21], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[162:163], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[4:5], v[164:165], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[94:95], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[4:5], v[96:97], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[98:99], a[64:79] + v_lshlrev_b32_e32 v0, 1, v80 + v_mfma_f32_32x32x8_f16 a[64:79], v[4:5], v[100:101], a[64:79] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[22:25], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[162:163], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[164:165], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[94:95], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[96:97], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[98:99], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[100:101], a[240:255] + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[2:5], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[6:9], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[10:11], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[12:13], v[4:5], a[0:15] + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[26:29], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[30:33], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[10:11], v[26:27], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[12:13], v[28:29], a[32:47] + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[34:37], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[38:41], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[10:11], v[34:35], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[36:37], a[112:127] + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[42:45], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v90 + ds_read_b128 v[46:49], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[208:223], v[10:11], v[42:43], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[26:27], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[34:35], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[14:15], v[42:43], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[16:17], v[44:45], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[18:19], v[2:3], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[20:21], v[4:5], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[18:19], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[20:21], v[28:29], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[18:19], v[34:35], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[20:21], v[36:37], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[18:19], v[42:43], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[20:21], v[44:45], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[22:23], v[2:3], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[24:25], v[4:5], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[22:23], v[26:27], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[24:25], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[22:23], v[34:35], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[24:25], v[36:37], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[22:23], v[42:43], a[240:255] + v_lshlrev_b32_e32 v0, 1, v67 + v_mfma_f32_32x32x8_f16 a[240:255], v[24:25], v[44:45], a[240:255] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[0:1], v[30:31], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[32:33], a[32:47] + v_mfma_f32_32x32x8_f16 a[112:127], v[0:1], v[38:39], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[40:41], a[112:127] + v_mfma_f32_32x32x8_f16 a[208:223], v[0:1], v[46:47], a[208:223] + v_lshlrev_b32_e32 v0, 1, v69 + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[48:49], a[208:223] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[0:1], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[0:1], v[30:31], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[0:1], v[38:39], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_f16 a[144:159], v[0:1], v[46:47], a[144:159] + v_lshlrev_b32_e32 v0, 1, v72 + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[48:49], a[144:159] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[0:1], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[128:143], v[0:1], v[30:31], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[32:33], a[128:143] + v_mfma_f32_32x32x8_f16 a[80:95], v[0:1], v[38:39], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[40:41], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[0:1], v[46:47], a[64:79] + v_lshlrev_b32_e32 v0, 1, v73 + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[48:49], a[64:79] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[0:1], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[48:63], v[0:1], v[30:31], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[32:33], a[48:63] + v_mfma_f32_32x32x8_f16 a[16:31], v[0:1], v[38:39], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[40:41], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[0:1], v[46:47], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[48:49], a[240:255] +.LBB3_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RK + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v139, a4 + v_accvgpr_read_b32 v1, a5 + v_accvgpr_read_b32 v18, a6 + v_accvgpr_read_b32 v138, a7 + v_accvgpr_read_b32 v137, a8 + v_accvgpr_read_b32 v136, a9 + v_accvgpr_read_b32 v135, a10 + v_accvgpr_read_b32 v134, a11 + v_accvgpr_read_b32 v133, a12 + v_accvgpr_read_b32 v132, a13 + v_accvgpr_read_b32 v131, a14 + v_accvgpr_read_b32 v130, a15 + v_accvgpr_read_b32 v107, a32 + v_accvgpr_read_b32 v106, a33 + v_accvgpr_read_b32 v105, a34 + v_accvgpr_read_b32 v104, a35 + v_accvgpr_read_b32 v103, a36 + v_accvgpr_read_b32 v102, a37 + v_accvgpr_read_b32 v101, a38 + v_accvgpr_read_b32 v100, a39 + v_accvgpr_read_b32 v99, a40 + v_accvgpr_read_b32 v98, a41 + v_accvgpr_read_b32 v97, a42 + v_accvgpr_read_b32 v96, a43 + v_accvgpr_read_b32 v95, a44 + v_accvgpr_read_b32 v94, a45 + v_accvgpr_read_b32 v93, a46 + v_accvgpr_read_b32 v92, a47 + v_accvgpr_read_b32 v91, a112 + v_accvgpr_read_b32 v90, a113 + v_accvgpr_read_b32 v89, a114 + v_accvgpr_read_b32 v88, a115 + v_accvgpr_read_b32 v87, a116 + v_accvgpr_read_b32 v86, a117 + v_accvgpr_read_b32 v85, a118 + v_accvgpr_read_b32 v84, a119 + v_accvgpr_read_b32 v83, a120 + v_accvgpr_read_b32 v82, a121 + v_accvgpr_read_b32 v81, a122 + v_accvgpr_read_b32 v80, a123 + v_accvgpr_read_b32 v79, a124 + v_accvgpr_read_b32 v78, a125 + v_accvgpr_read_b32 v77, a126 + v_accvgpr_read_b32 v76, a127 + v_accvgpr_read_b32 v75, a208 + v_accvgpr_read_b32 v74, a209 + v_accvgpr_read_b32 v73, a210 + v_accvgpr_read_b32 v72, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v69, a213 + v_accvgpr_read_b32 v68, a214 + v_accvgpr_read_b32 v67, a215 + v_accvgpr_read_b32 v66, a216 + v_accvgpr_read_b32 v65, a217 + v_accvgpr_read_b32 v64, a218 + v_accvgpr_read_b32 v63, a219 + v_accvgpr_read_b32 v62, a220 + v_accvgpr_read_b32 v61, a221 + v_accvgpr_read_b32 v60, a222 + v_accvgpr_read_b32 v19, a223 + v_accvgpr_read_b32 v224, a224 + v_accvgpr_read_b32 v223, a225 + v_accvgpr_read_b32 v222, a226 + v_accvgpr_read_b32 v221, a227 + v_accvgpr_read_b32 v220, a228 + v_accvgpr_read_b32 v219, a229 + v_accvgpr_read_b32 v218, a230 + v_accvgpr_read_b32 v217, a231 + v_accvgpr_read_b32 v216, a232 + v_accvgpr_read_b32 v215, a233 + v_accvgpr_read_b32 v214, a234 + v_accvgpr_read_b32 v213, a235 + v_accvgpr_read_b32 v212, a236 + v_accvgpr_read_b32 v211, a237 + v_accvgpr_read_b32 v210, a238 + v_accvgpr_read_b32 v209, a239 + v_accvgpr_read_b32 v176, a192 + v_accvgpr_read_b32 v175, a193 + v_accvgpr_read_b32 v174, a194 + v_accvgpr_read_b32 v173, a195 + v_accvgpr_read_b32 v172, a196 + v_accvgpr_read_b32 v171, a197 + v_accvgpr_read_b32 v170, a198 + v_accvgpr_read_b32 v169, a199 + v_accvgpr_read_b32 v168, a200 + v_accvgpr_read_b32 v167, a201 + v_accvgpr_read_b32 v166, a202 + v_accvgpr_read_b32 v165, a203 + v_accvgpr_read_b32 v164, a204 + v_accvgpr_read_b32 v163, a205 + v_accvgpr_read_b32 v162, a206 + v_accvgpr_read_b32 v161, a207 + v_accvgpr_read_b32 v160, a160 + v_accvgpr_read_b32 v159, a161 + v_accvgpr_read_b32 v158, a162 + v_accvgpr_read_b32 v157, a163 + v_accvgpr_read_b32 v156, a164 + v_accvgpr_read_b32 v155, a165 + v_accvgpr_read_b32 v154, a166 + v_accvgpr_read_b32 v153, a167 + v_accvgpr_read_b32 v152, a168 + v_accvgpr_read_b32 v151, a169 + v_accvgpr_read_b32 v150, a170 + v_accvgpr_read_b32 v149, a171 + v_accvgpr_read_b32 v148, a172 + v_accvgpr_read_b32 v147, a173 + v_accvgpr_read_b32 v145, a174 + v_accvgpr_read_b32 v144, a175 + v_accvgpr_read_b32 v146, a144 + v_accvgpr_read_b32 v129, a145 + v_accvgpr_read_b32 v128, a146 + v_accvgpr_read_b32 v127, a147 + v_accvgpr_read_b32 v126, a148 + v_accvgpr_read_b32 v125, a149 + v_accvgpr_read_b32 v124, a150 + v_accvgpr_read_b32 v123, a151 + v_accvgpr_read_b32 v122, a152 + v_accvgpr_read_b32 v121, a153 + v_accvgpr_read_b32 v120, a154 + v_accvgpr_read_b32 v119, a155 + v_accvgpr_read_b32 v118, a156 + v_accvgpr_read_b32 v117, a157 + v_accvgpr_read_b32 v116, a158 + v_accvgpr_read_b32 v115, a159 + v_accvgpr_mov_b32 a15, a176 + v_accvgpr_mov_b32 a14, a177 + v_accvgpr_mov_b32 a13, a178 + v_accvgpr_mov_b32 a12, a179 + v_accvgpr_mov_b32 a11, a180 + v_accvgpr_mov_b32 a10, a181 + v_accvgpr_mov_b32 a9, a182 + v_accvgpr_mov_b32 a8, a183 + v_accvgpr_mov_b32 a7, a184 + v_accvgpr_mov_b32 a6, a185 + v_accvgpr_mov_b32 a5, a186 + v_accvgpr_mov_b32 a4, a187 + v_accvgpr_mov_b32 a3, a188 + v_accvgpr_mov_b32 a2, a189 + v_accvgpr_mov_b32 a1, a190 + v_accvgpr_mov_b32 a0, a191 + v_accvgpr_read_b32 v59, a128 + v_accvgpr_read_b32 v58, a129 + v_accvgpr_read_b32 v57, a130 + v_accvgpr_read_b32 v56, a131 + v_accvgpr_read_b32 v55, a132 + v_accvgpr_read_b32 v54, a133 + v_accvgpr_read_b32 v53, a134 + v_accvgpr_read_b32 v52, a135 + v_accvgpr_read_b32 v51, a136 + v_accvgpr_read_b32 v50, a137 + v_accvgpr_read_b32 v25, a138 + v_accvgpr_read_b32 v24, a139 + v_accvgpr_read_b32 v23, a140 + v_accvgpr_read_b32 v22, a141 + v_accvgpr_read_b32 v21, a142 + v_accvgpr_read_b32 v20, a143 + v_accvgpr_read_b32 v114, a80 + v_accvgpr_read_b32 v113, a81 + v_accvgpr_read_b32 v112, a82 + v_accvgpr_read_b32 v111, a83 + v_accvgpr_read_b32 v110, a84 + v_accvgpr_read_b32 v109, a85 + v_accvgpr_read_b32 v108, a86 + v_accvgpr_read_b32 v70, a87 + v_accvgpr_read_b32 v49, a88 + v_accvgpr_read_b32 v48, a89 + v_accvgpr_read_b32 v47, a90 + v_accvgpr_read_b32 v46, a91 + v_accvgpr_read_b32 v45, a92 + v_accvgpr_read_b32 v44, a93 + v_accvgpr_read_b32 v43, a94 + v_accvgpr_read_b32 v42, a95 + v_accvgpr_read_b32 v208, a64 + v_accvgpr_read_b32 v207, a65 + v_accvgpr_read_b32 v206, a66 + v_accvgpr_read_b32 v205, a67 + v_accvgpr_read_b32 v204, a68 + v_accvgpr_read_b32 v203, a69 + v_accvgpr_read_b32 v202, a70 + v_accvgpr_read_b32 v201, a71 + v_accvgpr_read_b32 v200, a72 + v_accvgpr_read_b32 v199, a73 + v_accvgpr_read_b32 v198, a74 + v_accvgpr_read_b32 v197, a75 + v_accvgpr_read_b32 v196, a76 + v_accvgpr_read_b32 v195, a77 + v_accvgpr_read_b32 v194, a78 + v_accvgpr_read_b32 v193, a79 + v_accvgpr_mov_b32 a47, a96 + v_accvgpr_mov_b32 a46, a97 + v_accvgpr_mov_b32 a45, a98 + v_accvgpr_mov_b32 a44, a99 + v_accvgpr_mov_b32 a43, a100 + v_accvgpr_mov_b32 a42, a101 + v_accvgpr_mov_b32 a41, a102 + v_accvgpr_mov_b32 a40, a103 + v_accvgpr_mov_b32 a39, a104 + v_accvgpr_mov_b32 a38, a105 + v_accvgpr_mov_b32 a37, a106 + v_accvgpr_mov_b32 a36, a107 + v_accvgpr_mov_b32 a35, a108 + v_accvgpr_mov_b32 a34, a109 + v_accvgpr_mov_b32 a33, a110 + v_accvgpr_mov_b32 a32, a111 + v_accvgpr_read_b32 v41, a48 + v_accvgpr_read_b32 v40, a49 + v_accvgpr_read_b32 v39, a50 + v_accvgpr_read_b32 v38, a51 + v_accvgpr_read_b32 v37, a52 + v_accvgpr_read_b32 v36, a53 + v_accvgpr_read_b32 v35, a54 + v_accvgpr_read_b32 v34, a55 + v_accvgpr_read_b32 v33, a56 + v_accvgpr_read_b32 v32, a57 + v_accvgpr_read_b32 v31, a58 + v_accvgpr_read_b32 v30, a59 + v_accvgpr_read_b32 v29, a60 + v_accvgpr_read_b32 v28, a61 + v_accvgpr_read_b32 v27, a62 + v_accvgpr_read_b32 v26, a63 + v_accvgpr_read_b32 v192, a16 + v_accvgpr_read_b32 v191, a17 + v_accvgpr_read_b32 v190, a18 + v_accvgpr_read_b32 v189, a19 + v_accvgpr_read_b32 v188, a20 + v_accvgpr_read_b32 v187, a21 + v_accvgpr_read_b32 v186, a22 + v_accvgpr_read_b32 v185, a23 + v_accvgpr_read_b32 v184, a24 + v_accvgpr_read_b32 v183, a25 + v_accvgpr_read_b32 v182, a26 + v_accvgpr_read_b32 v181, a27 + v_accvgpr_read_b32 v180, a28 + v_accvgpr_read_b32 v179, a29 + v_accvgpr_read_b32 v178, a30 + v_accvgpr_read_b32 v177, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s3, s4, s16 + s_mul_hi_u32 s4, 0, s16 + s_add_i32 s4, s4, s3 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v227, 24, v225 + v_lshrrev_b32_e32 v0, 3, v225 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v209, v92 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v147 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v69 + v_cvt_f16_f32_e32 v136, v68 + v_cvt_f16_f32_e32 v137, v67 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v19 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v19, v206 + v_accvgpr_write_b32 a16, v19 + v_cvt_f16_f32_e32 v19, v205 + v_accvgpr_write_b32 a17, v19 + v_cvt_f16_f32_e32 v19, v204 + v_accvgpr_write_b32 a18, v19 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v69, v202 + v_cvt_f16_f32_e32 v68, v201 + v_cvt_f16_f32_e32 v67, v200 + v_cvt_f16_f32_e32 v66, v199 + v_cvt_f16_f32_e32 v60, v198 + v_cvt_f16_f32_e32 v61, v197 + v_cvt_f16_f32_e32 v62, v196 + v_cvt_f16_f32_e32 v63, v195 + v_cvt_f16_f32_e32 v64, v194 + v_cvt_f16_f32_e32 v65, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v19, 1, v228 + v_cvt_f16_f32_e32 v193, v114 + v_cvt_f16_f32_e32 v194, v113 + v_cvt_f16_f32_e32 v195, v112 + v_cvt_f16_f32_e32 v196, v111 + v_cvt_f16_f32_e32 v110, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v70 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v201, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v70, v191 + v_cvt_f16_f32_e32 v108, v190 + v_cvt_f16_f32_e32 v109, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v114, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v3, v58 + v_cvt_f16_f32_e32 v4, v57 + v_cvt_f16_f32_e32 v5, v56 + v_cvt_f16_f32_e32 v6, v55 + v_cvt_f16_f32_e32 v7, v54 + v_cvt_f16_f32_e32 v8, v53 + v_cvt_f16_f32_e32 v9, v52 + v_cvt_f16_f32_e32 v10, v51 + v_cvt_f16_f32_e32 v11, v50 + v_cvt_f16_f32_e32 v12, v25 + v_cvt_f16_f32_e32 v13, v24 + v_cvt_f16_f32_e32 v14, v23 + v_cvt_f16_f32_e32 v15, v22 + v_cvt_f16_f32_e32 v16, v21 + v_cvt_f16_f32_e32 v17, v20 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v31, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v227 + v_lshlrev_b32_e32 v21, 3, v225 + v_lshrrev_b32_e32 v20, 1, v225 + s_cbranch_scc1 .LBB3_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB3_14 +.LBB3_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSD_8RowMajorESF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB3_13: + v_readfirstlane_b32 s2, v226 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v23, s5, v0 + v_lshl_add_u32 v23, v23, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v1 offset:1152 + ds_write_b16 v23, v18 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v132 offset:3456 + ds_write_b16 v23, v133 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 60, v20 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v32, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v32, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v32 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v41, v40, s16 + v_add_u32_e32 v185, v41, v25 + v_lshlrev_b32_e32 v190, 1, v185 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v185 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v185, 64, v25 + v_add_u32_e32 v190, v41, v185 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v76 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 0x80, v25 + v_add_u32_e32 v191, v41, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v72 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0xc0, v25 + v_add_u32_e32 v41, v41, v191 + v_lshlrev_b32_e32 v192, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v207 offset:128 + ds_write_b16 v23, a16 offset:256 + ds_write_b16 v23, a17 offset:384 + ds_write_b16 v23, a18 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v69 offset:1280 + ds_write_b16 v23, v68 offset:1408 + ds_write_b16 v23, v67 offset:2048 + ds_write_b16 v23, v66 offset:2176 + ds_write_b16 v23, v60 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v115 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, 0x80, v40 + v_mul_lo_u32 v40, v32, s16 + v_add_u32_e32 v41, v40, v191 + v_lshlrev_b32_e32 v191, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v193 + ds_write_b16 v23, v194 offset:128 + ds_write_b16 v23, v195 offset:256 + ds_write_b16 v23, v196 offset:384 + ds_write_b16 v23, v110 offset:1024 + ds_write_b16 v23, v197 offset:1152 + ds_write_b16 v23, v198 offset:1280 + ds_write_b16 v23, v199 offset:1408 + ds_write_b16 v23, v200 offset:2048 + ds_write_b16 v23, v201 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v43 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v70 offset:8320 + ds_write_b16 v23, v108 offset:8448 + ds_write_b16 v23, v109 offset:8576 + ds_write_b16 v23, v111 offset:9216 + ds_write_b16 v23, v112 offset:9344 + ds_write_b16 v23, v113 offset:9472 + ds_write_b16 v23, v114 offset:9600 + ds_write_b16 v23, v184 offset:10240 + ds_write_b16 v23, v183 offset:10368 + ds_write_b16 v23, v182 offset:10496 + ds_write_b16 v23, v181 offset:10624 + ds_write_b16 v23, v180 offset:11264 + ds_write_b16 v23, v179 offset:11392 + ds_write_b16 v23, v178 offset:11520 + ds_write_b16 v23, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v190 + v_lshlrev_b32_e32 v190, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v3 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v31 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v185 + v_lshlrev_b32_e32 v185, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v185, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v185, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v185, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v185, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a47 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a46 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a45 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a44 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a43 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a42 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a41 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a40 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v40, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB3_12 +.LBB3_14: + v_readfirstlane_b32 s2, v226 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_add_u32 v0, v0, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v40, v0, v22, s2 + ds_write_b16 v40, v251 + ds_write_b16 v40, v252 offset:128 + ds_write_b16 v40, v253 offset:256 + ds_write_b16 v40, v254 offset:384 + ds_write_b16 v40, v255 offset:1024 + ds_write_b16 v40, v1 offset:1152 + ds_write_b16 v40, v18 offset:1280 + ds_write_b16 v40, v244 offset:1408 + ds_write_b16 v40, v245 offset:2048 + ds_write_b16 v40, v246 offset:2176 + ds_write_b16 v40, v247 offset:2304 + ds_write_b16 v40, v248 offset:2432 + ds_write_b16 v40, v249 offset:3072 + ds_write_b16 v40, v250 offset:3200 + ds_write_b16 v40, v131 offset:3328 + ds_write_b16 v40, v132 offset:3456 + ds_write_b16 v40, v133 offset:8192 + ds_write_b16 v40, v229 offset:8320 + ds_write_b16 v40, v230 offset:8448 + ds_write_b16 v40, v231 offset:8576 + ds_write_b16 v40, v232 offset:9216 + ds_write_b16 v40, v233 offset:9344 + ds_write_b16 v40, v234 offset:9472 + ds_write_b16 v40, v235 offset:9600 + ds_write_b16 v40, v236 offset:10240 + ds_write_b16 v40, v237 offset:10368 + ds_write_b16 v40, v238 offset:10496 + ds_write_b16 v40, v239 offset:10624 + ds_write_b16 v40, v240 offset:11264 + ds_write_b16 v40, v241 offset:11392 + ds_write_b16 v40, v242 offset:11520 + ds_write_b16 v40, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v20 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v41, v0, 1, v18 + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v1, s18, v1 + v_or_b32_e32 v185, s19, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v186, v0, v185 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v187, 1, v186 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v187, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v186 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v107 + ds_write_b16 v40, v106 offset:128 + ds_write_b16 v40, v105 offset:256 + ds_write_b16 v40, v104 offset:384 + ds_write_b16 v40, v103 offset:1024 + ds_write_b16 v40, v102 offset:1152 + ds_write_b16 v40, v101 offset:1280 + ds_write_b16 v40, v100 offset:1408 + ds_write_b16 v40, v99 offset:2048 + ds_write_b16 v40, v98 offset:2176 + ds_write_b16 v40, v97 offset:2304 + ds_write_b16 v40, v96 offset:2432 + ds_write_b16 v40, v95 offset:3072 + ds_write_b16 v40, v94 offset:3200 + ds_write_b16 v40, v93 offset:3328 + ds_write_b16 v40, v209 offset:3456 + ds_write_b16 v40, v210 offset:8192 + ds_write_b16 v40, v211 offset:8320 + ds_write_b16 v40, v212 offset:8448 + ds_write_b16 v40, v213 offset:8576 + ds_write_b16 v40, v214 offset:9216 + ds_write_b16 v40, v215 offset:9344 + ds_write_b16 v40, v216 offset:9472 + ds_write_b16 v40, v217 offset:9600 + ds_write_b16 v40, v218 offset:10240 + ds_write_b16 v40, v219 offset:10368 + ds_write_b16 v40, v220 offset:10496 + ds_write_b16 v40, v221 offset:10624 + ds_write_b16 v40, v222 offset:11264 + ds_write_b16 v40, v223 offset:11392 + ds_write_b16 v40, v224 offset:11520 + ds_write_b16 v40, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v93, 64, v185 + v_add_u32_e32 v94, v0, v93 + v_lshlrev_b32_e32 v95, 1, v94 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v95, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v94 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v162 + ds_write_b16 v40, v163 offset:128 + ds_write_b16 v40, v164 offset:256 + ds_write_b16 v40, v165 offset:384 + ds_write_b16 v40, v166 offset:1024 + ds_write_b16 v40, v167 offset:1152 + ds_write_b16 v40, v168 offset:1280 + ds_write_b16 v40, v169 offset:1408 + ds_write_b16 v40, v170 offset:2048 + ds_write_b16 v40, v171 offset:2176 + ds_write_b16 v40, v172 offset:2304 + ds_write_b16 v40, v173 offset:2432 + ds_write_b16 v40, v174 offset:3072 + ds_write_b16 v40, v175 offset:3200 + ds_write_b16 v40, v176 offset:3328 + ds_write_b16 v40, v76 offset:3456 + ds_write_b16 v40, v77 offset:8192 + ds_write_b16 v40, v78 offset:8320 + ds_write_b16 v40, v79 offset:8448 + ds_write_b16 v40, v80 offset:8576 + ds_write_b16 v40, v81 offset:9216 + ds_write_b16 v40, v82 offset:9344 + ds_write_b16 v40, v83 offset:9472 + ds_write_b16 v40, v84 offset:9600 + ds_write_b16 v40, v85 offset:10240 + ds_write_b16 v40, v86 offset:10368 + ds_write_b16 v40, v87 offset:10496 + ds_write_b16 v40, v88 offset:10624 + ds_write_b16 v40, v89 offset:11264 + ds_write_b16 v40, v90 offset:11392 + ds_write_b16 v40, v91 offset:11520 + ds_write_b16 v40, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v76, 0x80, v185 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v75 + ds_write_b16 v40, v74 offset:128 + ds_write_b16 v40, v73 offset:256 + ds_write_b16 v40, v72 offset:384 + ds_write_b16 v40, v134 offset:1024 + ds_write_b16 v40, v135 offset:1152 + ds_write_b16 v40, v136 offset:1280 + ds_write_b16 v40, v137 offset:1408 + ds_write_b16 v40, v138 offset:2048 + ds_write_b16 v40, v139 offset:2176 + ds_write_b16 v40, v140 offset:2304 + ds_write_b16 v40, v141 offset:2432 + ds_write_b16 v40, v142 offset:3072 + ds_write_b16 v40, v143 offset:3200 + ds_write_b16 v40, v144 offset:3328 + ds_write_b16 v40, v145 offset:3456 + ds_write_b16 v40, v146 offset:8192 + ds_write_b16 v40, v147 offset:8320 + ds_write_b16 v40, v148 offset:8448 + ds_write_b16 v40, v149 offset:8576 + ds_write_b16 v40, v150 offset:9216 + ds_write_b16 v40, v151 offset:9344 + ds_write_b16 v40, v152 offset:9472 + ds_write_b16 v40, v153 offset:9600 + ds_write_b16 v40, v154 offset:10240 + ds_write_b16 v40, v155 offset:10368 + ds_write_b16 v40, v156 offset:10496 + ds_write_b16 v40, v157 offset:10624 + ds_write_b16 v40, v158 offset:11264 + ds_write_b16 v40, v159 offset:11392 + ds_write_b16 v40, v160 offset:11520 + ds_write_b16 v40, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v75, 0xc0, v185 + v_add_u32_e32 v0, v0, v75 + v_lshlrev_b32_e32 v77, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v208 + ds_write_b16 v40, v207 offset:128 + ds_write_b16 v40, a16 offset:256 + ds_write_b16 v40, a17 offset:384 + ds_write_b16 v40, a18 offset:1024 + ds_write_b16 v40, v71 offset:1152 + ds_write_b16 v40, v69 offset:1280 + ds_write_b16 v40, v68 offset:1408 + ds_write_b16 v40, v67 offset:2048 + ds_write_b16 v40, v66 offset:2176 + ds_write_b16 v40, v60 offset:2304 + ds_write_b16 v40, v61 offset:2432 + ds_write_b16 v40, v62 offset:3072 + ds_write_b16 v40, v63 offset:3200 + ds_write_b16 v40, v64 offset:3328 + ds_write_b16 v40, v65 offset:3456 + ds_write_b16 v40, v2 offset:8192 + ds_write_b16 v40, v115 offset:8320 + ds_write_b16 v40, v116 offset:8448 + ds_write_b16 v40, v117 offset:8576 + ds_write_b16 v40, v118 offset:9216 + ds_write_b16 v40, v119 offset:9344 + ds_write_b16 v40, v120 offset:9472 + ds_write_b16 v40, v121 offset:9600 + ds_write_b16 v40, v122 offset:10240 + ds_write_b16 v40, v123 offset:10368 + ds_write_b16 v40, v124 offset:10496 + ds_write_b16 v40, v125 offset:10624 + ds_write_b16 v40, v126 offset:11264 + ds_write_b16 v40, v127 offset:11392 + ds_write_b16 v40, v128 offset:11520 + ds_write_b16 v40, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v60, v0, s16 + v_add_u32_e32 v0, v60, v75 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v193 + ds_write_b16 v40, v194 offset:128 + ds_write_b16 v40, v195 offset:256 + ds_write_b16 v40, v196 offset:384 + ds_write_b16 v40, v110 offset:1024 + ds_write_b16 v40, v197 offset:1152 + ds_write_b16 v40, v198 offset:1280 + ds_write_b16 v40, v199 offset:1408 + ds_write_b16 v40, v200 offset:2048 + ds_write_b16 v40, v201 offset:2176 + ds_write_b16 v40, v47 offset:2304 + ds_write_b16 v40, v46 offset:2432 + ds_write_b16 v40, v45 offset:3072 + ds_write_b16 v40, v44 offset:3200 + ds_write_b16 v40, v43 offset:3328 + ds_write_b16 v40, v48 offset:3456 + ds_write_b16 v40, v49 offset:8192 + ds_write_b16 v40, v70 offset:8320 + ds_write_b16 v40, v108 offset:8448 + ds_write_b16 v40, v109 offset:8576 + ds_write_b16 v40, v111 offset:9216 + ds_write_b16 v40, v112 offset:9344 + ds_write_b16 v40, v113 offset:9472 + ds_write_b16 v40, v114 offset:9600 + ds_write_b16 v40, v184 offset:10240 + ds_write_b16 v40, v183 offset:10368 + ds_write_b16 v40, v182 offset:10496 + ds_write_b16 v40, v181 offset:10624 + ds_write_b16 v40, v180 offset:11264 + ds_write_b16 v40, v179 offset:11392 + ds_write_b16 v40, v178 offset:11520 + ds_write_b16 v40, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v0, v60, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v42 + ds_write_b16 v40, v3 offset:128 + ds_write_b16 v40, v4 offset:256 + ds_write_b16 v40, v5 offset:384 + ds_write_b16 v40, v6 offset:1024 + ds_write_b16 v40, v7 offset:1152 + ds_write_b16 v40, v8 offset:1280 + ds_write_b16 v40, v9 offset:1408 + ds_write_b16 v40, v10 offset:2048 + ds_write_b16 v40, v11 offset:2176 + ds_write_b16 v40, v12 offset:2304 + ds_write_b16 v40, v13 offset:2432 + ds_write_b16 v40, v14 offset:3072 + ds_write_b16 v40, v15 offset:3200 + ds_write_b16 v40, v16 offset:3328 + ds_write_b16 v40, v17 offset:3456 + ds_write_b16 v40, v50 offset:8192 + ds_write_b16 v40, v51 offset:8320 + ds_write_b16 v40, v52 offset:8448 + ds_write_b16 v40, v53 offset:8576 + ds_write_b16 v40, v54 offset:9216 + ds_write_b16 v40, v55 offset:9344 + ds_write_b16 v40, v56 offset:9472 + ds_write_b16 v40, v57 offset:9600 + ds_write_b16 v40, v58 offset:10240 + ds_write_b16 v40, v59 offset:10368 + ds_write_b16 v40, v31 offset:10496 + ds_write_b16 v40, v30 offset:10624 + ds_write_b16 v40, v29 offset:11264 + ds_write_b16 v40, v28 offset:11392 + ds_write_b16 v40, v27 offset:11520 + ds_write_b16 v40, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v60, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a47 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a46 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a45 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a44 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a43 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a42 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a41 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a40 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a32 + v_cvt_f16_f32_e32 v31, v31 + ds_write_b16 v40, v0 + ds_write_b16 v40, v1 offset:128 + ds_write_b16 v40, v2 offset:256 + ds_write_b16 v40, v3 offset:384 + ds_write_b16 v40, v4 offset:1024 + ds_write_b16 v40, v5 offset:1152 + ds_write_b16 v40, v6 offset:1280 + ds_write_b16 v40, v7 offset:1408 + ds_write_b16 v40, v8 offset:2048 + ds_write_b16 v40, v9 offset:2176 + ds_write_b16 v40, v10 offset:2304 + ds_write_b16 v40, v11 offset:2432 + ds_write_b16 v40, v12 offset:3072 + ds_write_b16 v40, v13 offset:3200 + ds_write_b16 v40, v14 offset:3328 + ds_write_b16 v40, v15 offset:3456 + ds_write_b16 v40, v16 offset:8192 + ds_write_b16 v40, v17 offset:8320 + ds_write_b16 v40, v18 offset:8448 + ds_write_b16 v40, v19 offset:8576 + ds_write_b16 v40, v20 offset:9216 + ds_write_b16 v40, v21 offset:9344 + ds_write_b16 v40, v22 offset:9472 + ds_write_b16 v40, v23 offset:9600 + ds_write_b16 v40, v24 offset:10240 + ds_write_b16 v40, v25 offset:10368 + ds_write_b16 v40, v26 offset:10496 + ds_write_b16 v40, v27 offset:10624 + ds_write_b16 v40, v28 offset:11264 + ds_write_b16 v40, v29 offset:11392 + ds_write_b16 v40, v30 offset:11520 + ds_write_b16 v40, v31 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v60, v185 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end3: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end3-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 28876 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB4_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB4_5 +; %bb.2: ; %.lr.ph.preheader + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v2, v6 + v_mov_b32_e32 v4, v0 +.LBB4_3: ; %.lr.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[8:9], v[2:3], 1, s[8:9] + global_load_ushort v3, v[8:9], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], v[4:5], 1, s[10:11] + global_load_ushort v5, v[8:9], off + s_add_i32 s6, s6, -1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v1, v3, v5, v1 op_sel_hi:[1,1,0] + v_add_u32_e32 v2, s7, v2 + s_cbranch_scc0 .LBB4_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB4_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB4_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end4: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end4-_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 416 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text.c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942,"axG",@progbits,c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942,comdat + .protected c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 ; -- Begin function c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 + .globl c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 + .p2align 8 + .type c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942,@function +c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942: ; @c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_waitcnt lgkmcnt(0) + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v0, s13 + s_lshl_b32 s18, s12, 8 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s12, s12, s15 + s_xor_b32 s2, s12, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s21, s12, s21 + s_mul_i32 s22, s21, s13 + s_sub_i32 s12, s12, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s12, s23, s12 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s12, s2, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s12, s2 + s_sub_i32 s21, s3, s14 + s_max_i32 s21, s21, 0 + s_mul_i32 s21, s13, s21 + s_add_i32 s2, s21, s2 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s12, s12, s13 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s12 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s3, s3, 1 + s_add_u32 s22, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s20, s2 + s_add_u32 s21, s2, s3 + s_add_i32 s6, s6, 63 + s_movk_i32 s23, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v226, -1, v0 + v_and_b32_e32 v6, 31, v226 + v_lshrrev_b32_e32 v3, 5, v226 + v_and_b32_e32 v69, 7, v226 + s_cbranch_scc0 .LBB5_2 +; %bb.1: + v_readfirstlane_b32 s26, v227 + v_and_b32_e32 v1, 7, v226 + v_lshlrev_b32_e32 v0, 3, v1 + v_and_b32_e32 v2, 0x78, v226 + s_and_b32 s10, s26, 0xffffffc0 + v_add_u32_e32 v2, s10, v2 + v_add_u32_e32 v4, s18, v2 + v_mad_u64_u32 v[4:5], s[10:11], v4, s7, v[0:1] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v7, 1, v4 + buffer_load_dwordx4 v[8:11], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[16:19], v5, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[20:23], v5, s[8:11], 0 offen + s_lshl_b32 s14, s21, 1 + v_add_u32_e32 v7, s7, v4 + v_lshlrev_b32_e32 v4, 1, v7 + buffer_load_dwordx4 v[24:27], v4, s[8:11], 0 offen + s_lshr_b32 s27, s26, 2 + s_mov_b32 s15, s11 + v_add_u32_e32 v4, s19, v2 + v_mad_u64_u32 v[4:5], s[24:25], v4, s20, v[0:1] + v_lshlrev_b32_e32 v0, 1, v4 + v_add_u32_e32 v5, s7, v7 + v_lshlrev_b32_e32 v7, 1, v5 + buffer_load_dwordx4 v[28:31], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s20, v4 + v_lshlrev_b32_e32 v7, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[32:35], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[36:39], v7, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v4 + v_add_u32_e32 v4, s20, v4 + v_add_u32_e32 v5, s7, v5 + v_lshlrev_b32_e32 v7, 1, v5 + buffer_load_dwordx4 v[40:43], v7, s[8:11], 0 offen + v_lshlrev_b32_e32 v7, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[44:47], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v7, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v4 + v_add_u32_e32 v4, s20, v4 + v_add_lshl_u32 v5, v5, s7, 1 + buffer_load_dwordx4 v[52:55], v5, s[8:11], 0 offen + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s20, v4 + buffer_load_dwordx4 v[56:59], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[60:63], v5, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v4 + v_add_lshl_u32 v4, v4, s20, 1 + buffer_load_dwordx4 v[64:67], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[70:73], v4, s[12:15], 0 offen + v_xor_b32_e32 v0, v3, v1 + s_lshr_b32 s10, s26, 1 + v_lshlrev_b32_e32 v4, 4, v1 + s_and_b32 s11, s27, 0x1ffffe0 + v_and_or_b32 v5, s10, 32, v6 + v_or_b32_e32 v7, s11, v6 + v_lshl_or_b32 v4, v2, 7, v4 + v_or_b32_e32 v68, 1, v2 + v_ashrrev_i32_e32 v74, 31, v2 + v_or_b32_e32 v75, 2, v2 + v_or_b32_e32 v76, 3, v2 + v_lshrrev_b32_e32 v74, 29, v74 + v_add_u32_e32 v77, v68, v74 + v_add_u32_e32 v78, v75, v74 + v_and_b32_e32 v77, -8, v77 + v_and_b32_e32 v78, -8, v78 + v_sub_u32_e32 v68, v68, v77 + v_sub_u32_e32 v75, v75, v78 + v_xor_b32_e32 v68, v68, v1 + v_xor_b32_e32 v75, v75, v1 + v_sub_u32_e32 v77, v68, v1 + v_sub_u32_e32 v68, v75, v68 + v_lshl_add_u32 v77, v77, 4, v4 + v_lshlrev_b32_e32 v68, 4, v68 + v_add3_u32 v68, v77, s23, v68 + s_waitcnt vmcnt(15) + ds_write_b128 v4, v[8:11] + s_waitcnt vmcnt(14) + ds_write_b128 v77, v[12:15] offset:128 + s_waitcnt vmcnt(13) + ds_write_b128 v68, v[16:19] offset:128 + v_add_u32_e32 v8, v76, v74 + v_and_b32_e32 v8, -8, v8 + v_sub_u32_e32 v8, v76, v8 + v_xor_b32_e32 v8, v8, v1 + v_sub_u32_e32 v9, v8, v75 + v_lshlrev_b32_e32 v9, 4, v9 + v_add3_u32 v9, v68, s23, v9 + s_waitcnt vmcnt(12) + ds_write_b128 v9, v[20:23] offset:128 + v_or_b32_e32 v10, 4, v2 + v_add_u32_e32 v11, v10, v74 + v_and_b32_e32 v11, -8, v11 + v_sub_u32_e32 v10, v10, v11 + v_xor_b32_e32 v10, v10, v1 + v_sub_u32_e32 v8, v10, v8 + v_lshlrev_b32_e32 v8, 4, v8 + v_add3_u32 v8, v9, s23, v8 + s_waitcnt vmcnt(11) + ds_write_b128 v8, v[24:27] offset:128 + v_or_b32_e32 v11, 5, v2 + v_add_u32_e32 v12, v11, v74 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v11, v11, v12 + v_xor_b32_e32 v11, v11, v1 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v10, v8, s23, v10 + s_waitcnt vmcnt(10) + ds_write_b128 v10, v[28:31] offset:128 + v_or_b32_e32 v12, 6, v2 + v_add_u32_e32 v13, v12, v74 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v1 + v_sub_u32_e32 v11, v12, v11 + v_lshlrev_b32_e32 v11, 4, v11 + v_add3_u32 v11, v10, s23, v11 + v_add_u32_e32 v13, 0x80, v11 + s_waitcnt vmcnt(7) + ds_write_b128 v11, v[40:43] offset:128 + v_or_b32_e32 v2, 7, v2 + v_add_u32_e32 v14, v2, v74 + v_and_b32_e32 v14, 0xffffff8, v14 + v_sub_u32_e32 v2, v2, v14 + v_xor_b32_e32 v2, v2, v1 + v_sub_u32_e32 v2, v2, v12 + v_lshl_add_u32 v2, v2, 4, v13 + s_waitcnt vmcnt(4) + ds_write_b128 v2, v[52:55] offset:128 + ds_write_b128 v4, v[32:35] offset:32768 + ds_write_b128 v77, v[36:39] offset:32896 + ds_write_b128 v68, v[44:47] offset:32896 + ds_write_b128 v9, v[48:51] offset:32896 + s_waitcnt vmcnt(3) + ds_write_b128 v8, v[56:59] offset:32896 + s_waitcnt vmcnt(2) + ds_write_b128 v10, v[60:63] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v11, v[64:67] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v2, v[70:73] offset:32896 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v2, 4, v0 + v_lshl_or_b32 v4, v7, 7, v2 + ds_read_b128 v[12:15], v4 + v_add_u32_e32 v7, 2, v3 + v_xor_b32_e32 v7, v7, v1 + v_sub_u32_e32 v7, v7, v0 + v_lshlrev_b32_e32 v7, 4, v7 + v_lshl_or_b32 v2, v5, 7, v2 + ds_read_b128 v[16:19], v2 offset:32768 + v_add_u32_e32 v5, v4, v7 + ds_read_b128 v[20:23], v5 + v_add_u32_e32 v7, v2, v7 + ds_read_b128 v[24:27], v7 offset:32768 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x8_f16 a[160:175], v[12:13], v[16:17], 0 + v_add_u32_e32 v8, 6, v3 + v_xor_b32_e32 v8, v8, v1 + v_sub_u32_e32 v9, v8, v0 + v_lshlrev_b32_e32 v9, 4, v9 + v_sub_u32_e32 v8, v0, v8 + v_lshlrev_b32_e32 v8, 4, v8 + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[18:19], a[160:175] + v_add_u32_e32 v10, v2, v9 + v_add_u32_e32 v11, v10, v8 + ds_read_b128 v[28:31], v11 offset:40960 + ds_read_b128 v[32:35], v10 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[12:13], v[28:29], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[30:31], a[192:207] + ds_read_b128 v[36:39], v11 offset:49152 + ds_read_b128 v[40:43], v11 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[12:13], v[36:37], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[38:39], a[224:239] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[40:41], 0 + v_add_u32_e32 v9, v4, v9 + v_add_u32_e32 v8, v9, v8 + v_mfma_f32_32x32x8_f16 a[208:223], v[14:15], v[42:43], a[208:223] + ds_read_b128 v[12:15], v8 offset:8192 + ds_read_b128 v[44:47], v9 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[12:13], v[16:17], 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[14:15], v[18:19], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[12:13], v[28:29], 0 + v_mfma_f32_32x32x8_f16 a[144:159], v[14:15], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[12:13], v[36:37], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[14:15], v[38:39], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[40:41], 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[14:15], v[42:43], a[112:127] + ds_read_b128 v[12:15], v8 offset:16384 + ds_read_b128 v[48:51], v8 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[12:13], v[16:17], 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[14:15], v[18:19], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[12:13], v[28:29], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[14:15], v[30:31], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[12:13], v[36:37], 0 + v_mfma_f32_32x32x8_f16 a[64:79], v[14:15], v[38:39], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[12:13], v[40:41], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[14:15], v[42:43], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[48:49], v[16:17], 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[50:51], v[18:19], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[48:49], v[28:29], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[50:51], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[48:49], v[36:37], 0 + v_mfma_f32_32x32x8_f16 a[0:15], v[50:51], v[38:39], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[48:49], v[40:41], 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[50:51], v[42:43], a[240:255] + v_mfma_f32_32x32x8_f16 a[160:175], v[20:21], v[24:25], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[22:23], v[26:27], a[160:175] + ds_read_b128 v[12:15], v7 offset:40960 + ds_read_b128 v[16:19], v7 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[20:21], v[12:13], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[22:23], v[14:15], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[20:21], v[16:17], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[22:23], v[18:19], a[224:239] + ds_read_b128 v[28:31], v7 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[20:21], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[22:23], v[30:31], a[208:223] + ds_read_b128 v[20:23], v5 offset:8192 + ds_read_b128 v[36:39], v5 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[20:21], v[24:25], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[22:23], v[26:27], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[20:21], v[12:13], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[22:23], v[14:15], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[20:21], v[16:17], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[22:23], v[18:19], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[20:21], v[28:29], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[22:23], v[30:31], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[36:37], v[24:25], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[38:39], v[26:27], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[36:37], v[12:13], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[38:39], v[14:15], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[36:37], v[16:17], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[38:39], v[18:19], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[36:37], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[38:39], v[30:31], a[48:63] + ds_read_b128 v[20:23], v5 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[20:21], v[24:25], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[22:23], v[26:27], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[20:21], v[12:13], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[22:23], v[14:15], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[20:21], v[16:17], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[22:23], v[18:19], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[20:21], v[28:29], a[240:255] + v_or_b32_e32 v5, 4, v3 + v_xor_b32_e32 v5, v5, v1 + v_sub_u32_e32 v0, v5, v0 + v_lshlrev_b32_e32 v0, 4, v0 + v_add_u32_e32 v4, v4, v0 + v_mfma_f32_32x32x8_f16 a[240:255], v[22:23], v[30:31], a[240:255] + ds_read_b128 v[12:15], v4 + v_add_u32_e32 v0, v2, v0 + ds_read_b128 v[16:19], v0 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[160:175], v[12:13], v[16:17], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[18:19], a[160:175] + ds_read_b128 v[20:23], v0 offset:40960 + ds_read_b128 v[24:27], v0 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[12:13], v[20:21], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[22:23], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[12:13], v[24:25], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[26:27], a[224:239] + ds_read_b128 v[28:31], v0 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[14:15], v[30:31], a[208:223] + ds_read_b128 v[12:15], v4 offset:8192 + ds_read_b128 v[36:39], v4 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[12:13], v[16:17], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[14:15], v[18:19], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[12:13], v[20:21], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[14:15], v[22:23], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[12:13], v[24:25], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[14:15], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[28:29], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[14:15], v[30:31], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[36:37], v[16:17], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[38:39], v[18:19], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[36:37], v[20:21], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[38:39], v[22:23], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[36:37], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[38:39], v[26:27], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[36:37], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[38:39], v[30:31], a[48:63] + ds_read_b128 v[12:15], v4 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[12:13], v[16:17], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[14:15], v[18:19], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[12:13], v[20:21], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[14:15], v[22:23], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[12:13], v[24:25], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[14:15], v[26:27], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[12:13], v[28:29], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[14:15], v[30:31], a[240:255] + ds_read_b128 v[12:15], v9 + ds_read_b128 v[16:19], v10 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[160:175], v[12:13], v[16:17], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[18:19], a[160:175] + ds_read_b128 v[20:23], v10 offset:40960 + ds_read_b128 v[24:27], v10 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[12:13], v[20:21], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[22:23], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[12:13], v[24:25], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[26:27], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[32:33], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[14:15], v[34:35], a[208:223] + ds_read_b128 v[10:13], v9 offset:8192 + ds_read_b128 v[28:31], v9 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[10:11], v[16:17], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[12:13], v[18:19], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[10:11], v[20:21], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[12:13], v[22:23], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[10:11], v[24:25], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[12:13], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[10:11], v[32:33], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[34:35], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[28:29], v[16:17], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[30:31], v[18:19], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[28:29], v[20:21], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[30:31], v[22:23], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[28:29], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[30:31], v[26:27], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[28:29], v[32:33], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[30:31], v[34:35], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[44:45], v[16:17], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[46:47], v[18:19], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[44:45], v[20:21], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[46:47], v[22:23], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[44:45], v[24:25], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[46:47], v[26:27], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[44:45], v[32:33], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[46:47], v[34:35], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB5_3 + s_branch .LBB5_10 +.LBB5_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr191 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr207 + ; implicit-def: $agpr175 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr1 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB5_3: + s_mov_b32 s10, s7 + v_readfirstlane_b32 s15, v227 + v_lshlrev_b32_e32 v2, 3, v69 + s_and_b32 s11, s15, 0xffffffc0 + v_and_b32_e32 v101, 0x78, v226 + v_add_u32_e32 v1, s11, v101 + v_add_u32_e32 v0, s18, v1 + v_mad_u64_u32 v[66:67], s[10:11], v0, s10, v[2:3] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v4, s7, v66 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[8:11], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v5, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v4 + v_lshlrev_b32_e32 v4, 1, v0 + buffer_load_dwordx4 v[16:19], v4, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + buffer_load_dwordx4 v[20:23], v4, s[8:11], 0 offen + v_xor_b32_e32 v7, v3, v69 + s_lshl_b32 s14, s21, 1 + v_lshlrev_b32_e32 v64, 4, v69 + s_lshr_b32 s21, s15, 2 + v_lshlrev_b32_e32 v65, 3, v7 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + buffer_load_dwordx4 v[24:27], v4, s[8:11], 0 offen + s_lshr_b32 s24, s15, 1 + s_mov_b32 s15, s11 + v_add_u32_e32 v4, s19, v1 + v_mad_u64_u32 v[4:5], s[22:23], v4, s20, v[2:3] + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v32, s20, v4 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v28, 1, v0 + buffer_load_dwordx4 v[28:31], v28, s[8:11], 0 offen + v_lshlrev_b32_e32 v40, 1, v32 + v_add_u32_e32 v41, s20, v32 + buffer_load_dwordx4 v[32:35], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[36:39], v40, s[12:15], 0 offen + v_lshlrev_b32_e32 v5, 1, v41 + v_add_u32_e32 v44, s20, v41 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v40, 1, v0 + buffer_load_dwordx4 v[40:43], v40, s[8:11], 0 offen + v_lshlrev_b32_e32 v52, 1, v44 + v_add_u32_e32 v53, s20, v44 + buffer_load_dwordx4 v[44:47], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v52, s[12:15], 0 offen + v_lshlrev_b32_e32 v5, 1, v53 + v_add_u32_e32 v56, s20, v53 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[52:55], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v56 + v_add_u32_e32 v67, s20, v56 + buffer_load_dwordx4 v[56:59], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[60:63], v0, s[12:15], 0 offen + v_lshlrev_b32_e32 v0, 1, v67 + v_add_lshl_u32 v5, v67, s20, 1 + buffer_load_dwordx4 v[70:73], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[74:77], v5, s[12:15], 0 offen + s_and_b32 s21, s21, 0x3ffffe0 + v_and_or_b32 v0, s24, 32, v6 + v_or_b32_e32 v5, s21, v6 + v_lshl_or_b32 v0, v0, 6, v65 + v_lshl_or_b32 v6, v1, 7, v64 + v_or_b32_e32 v64, 1, v1 + v_ashrrev_i32_e32 v67, 31, v1 + v_or_b32_e32 v68, 2, v1 + v_lshl_or_b32 v5, v5, 6, v65 + v_lshrrev_b32_e32 v65, 29, v67 + v_add_u32_e32 v67, v64, v65 + v_add_u32_e32 v78, v68, v65 + v_and_b32_e32 v67, -8, v67 + v_and_b32_e32 v78, -8, v78 + v_sub_u32_e32 v64, v64, v67 + v_sub_u32_e32 v67, v68, v78 + v_xor_b32_e32 v64, v64, v69 + v_xor_b32_e32 v67, v67, v69 + v_sub_u32_e32 v68, v64, v69 + v_sub_u32_e32 v64, v67, v64 + v_lshl_add_u32 v68, v68, 4, v6 + s_waitcnt vmcnt(15) + ds_write_b128 v6, v[8:11] + s_waitcnt vmcnt(14) + ds_write_b128 v68, v[12:15] offset:128 + v_lshlrev_b32_e32 v8, 4, v64 + s_movk_i32 s21, 0x80 + v_add3_u32 v8, v68, s21, v8 + s_waitcnt vmcnt(13) + ds_write_b128 v8, v[16:19] offset:128 + v_or_b32_e32 v9, 3, v1 + v_add_u32_e32 v10, v9, v65 + v_and_b32_e32 v10, -8, v10 + v_sub_u32_e32 v9, v9, v10 + v_xor_b32_e32 v9, v9, v69 + v_sub_u32_e32 v10, v9, v67 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v10, v8, s21, v10 + s_waitcnt vmcnt(12) + ds_write_b128 v10, v[20:23] offset:128 + v_or_b32_e32 v11, 4, v1 + v_add_u32_e32 v12, v11, v65 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v11, v11, v12 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v9, v11, v9 + v_lshlrev_b32_e32 v9, 4, v9 + v_add3_u32 v9, v10, s21, v9 + s_waitcnt vmcnt(11) + ds_write_b128 v9, v[24:27] offset:128 + v_or_b32_e32 v12, 5, v1 + v_add_u32_e32 v13, v12, v65 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v69 + v_sub_u32_e32 v11, v12, v11 + v_lshlrev_b32_e32 v11, 4, v11 + v_add3_u32 v11, v9, s21, v11 + v_add_u32_e32 v13, 0x80, v11 + s_waitcnt vmcnt(10) + ds_write_b128 v11, v[28:31] offset:128 + v_or_b32_e32 v14, 6, v1 + v_add_u32_e32 v15, v14, v65 + v_and_b32_e32 v15, -8, v15 + v_sub_u32_e32 v14, v14, v15 + v_xor_b32_e32 v14, v14, v69 + v_sub_u32_e32 v12, v14, v12 + v_lshl_add_u32 v12, v12, 4, v13 + v_add_u32_e32 v13, 0x80, v12 + s_waitcnt vmcnt(7) + ds_write_b128 v12, v[40:43] offset:128 + v_or_b32_e32 v1, 7, v1 + v_add_u32_e32 v15, v1, v65 + v_and_b32_e32 v15, 0xffffff8, v15 + v_sub_u32_e32 v1, v1, v15 + v_xor_b32_e32 v1, v1, v69 + v_sub_u32_e32 v1, v1, v14 + v_lshl_add_u32 v1, v1, 4, v13 + s_waitcnt vmcnt(4) + ds_write_b128 v1, v[52:55] offset:128 + ds_write_b128 v6, v[32:35] offset:32768 + ds_write_b128 v68, v[36:39] offset:32896 + ds_write_b128 v8, v[44:47] offset:32896 + ds_write_b128 v10, v[48:51] offset:32896 + s_waitcnt vmcnt(3) + ds_write_b128 v9, v[56:59] offset:32896 + s_waitcnt vmcnt(2) + ds_write_b128 v11, v[60:63] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v12, v[70:73] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v1, v[74:77] offset:32896 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v8, 2, v3 + v_or_b32_e32 v6, 4, v3 + v_add_u32_e32 v3, 6, v3 + s_cbranch_vccnz .LBB5_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit602.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v8, v69 + v_sub_u32_e32 v1, v1, v7 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v85, v5, v1 + v_xor_b32_e32 v9, v6, v69 + v_sub_u32_e32 v9, v9, v7 + v_lshlrev_b32_e32 v9, 3, v9 + v_add_u32_e32 v87, v5, v9 + v_xor_b32_e32 v10, v3, v69 + v_sub_u32_e32 v11, v10, v7 + v_lshlrev_b32_e32 v11, 3, v11 + v_add_u32_e32 v72, v5, v11 + v_sub_u32_e32 v10, v7, v10 + v_mov_b32_e32 v12, 0x1000 + v_lshl_add_u32 v10, v10, 3, v12 + v_add_u32_e32 v92, v72, v10 + v_add_u32_e32 v88, v92, v1 + v_add_u32_e32 v86, v92, v9 + v_add_u32_e32 v71, v92, v11 + v_add_u32_e32 v91, v71, v10 + v_add_u32_e32 v82, v91, v1 + v_add_u32_e32 v83, v91, v9 + v_add_u32_e32 v70, v91, v11 + v_add_u32_e32 v90, v70, v10 + v_add_u32_e32 v78, v90, v1 + v_add_u32_e32 v79, v90, v9 + v_add_u32_e32 v67, v90, v11 + v_add_u32_e32 v89, v0, v1 + v_add_u32_e32 v73, v0, v9 + v_add_u32_e32 v74, v0, v11 + v_add_u32_e32 v97, v74, v10 + v_add_u32_e32 v98, v97, v1 + v_add_u32_e32 v75, v97, v9 + v_add_u32_e32 v76, v97, v11 + v_add_u32_e32 v95, v76, v10 + v_add_u32_e32 v96, v95, v1 + v_add_u32_e32 v77, v95, v9 + v_add_u32_e32 v80, v95, v11 + v_add_u32_e32 v93, v80, v10 + v_add_u32_e32 v94, v93, v1 + v_add_u32_e32 v81, v93, v9 + v_add_u32_e32 v84, v93, v11 + s_mov_b64 s[2:3], 0 + s_branch .LBB5_6 +.LBB5_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr84 +.LBB5_6: ; %Flow53 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_lshlrev_b32_e32 v100, 1, v5 + v_lshlrev_b32_e32 v99, 1, v0 + s_cbranch_vccnz .LBB5_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1184.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v1, v4 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v4, v8, v69 + v_sub_u32_e32 v4, v4, v7 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v85, v5, v4 + v_lshlrev_b32_e32 v102, 1, v85 + v_xor_b32_e32 v6, v6, v69 + v_sub_u32_e32 v6, v6, v7 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_u32_e32 v87, v5, v6 + v_lshlrev_b32_e32 v103, 1, v87 + v_xor_b32_e32 v3, v3, v69 + v_sub_u32_e32 v8, v3, v7 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_u32_e32 v72, v5, v8 + v_lshlrev_b32_e32 v104, 1, v72 + v_sub_u32_e32 v3, v7, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v5, 0x1000, v3 + v_add_u32_e32 v92, v72, v5 + v_add_lshl_u32 v105, v72, v3, 1 + v_add_u32_e32 v88, v92, v4 + v_add_u32_e32 v86, v92, v6 + v_add_u32_e32 v71, v92, v8 + v_add_u32_e32 v91, v71, v5 + v_add_u32_e32 v82, v91, v4 + v_add_u32_e32 v83, v91, v6 + v_add_u32_e32 v70, v91, v8 + v_add_u32_e32 v90, v70, v5 + v_add_u32_e32 v78, v90, v4 + v_add_u32_e32 v79, v90, v6 + v_add_u32_e32 v67, v90, v8 + v_add_u32_e32 v89, v0, v4 + v_lshlrev_b32_e32 v106, 1, v89 + v_add_u32_e32 v73, v0, v6 + v_lshlrev_b32_e32 v107, 1, v73 + v_add_u32_e32 v74, v0, v8 + v_lshlrev_b32_e32 v108, 1, v74 + v_add_u32_e32 v97, v74, v5 + v_add_lshl_u32 v109, v74, v3, 1 + v_add_u32_e32 v98, v97, v4 + v_add_u32_e32 v75, v97, v6 + v_add_u32_e32 v76, v97, v8 + v_add_u32_e32 v95, v76, v5 + v_add_u32_e32 v96, v95, v4 + v_add_u32_e32 v77, v95, v6 + v_add_u32_e32 v80, v95, v8 + v_add_u32_e32 v93, v80, v5 + v_add_u32_e32 v94, v93, v4 + v_add_u32_e32 v81, v93, v6 + v_add_u32_e32 v84, v93, v8 + s_add_i32 s2, s2, 1 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_lshlrev_b32_e32 v110, 1, v2 + s_movk_i32 s3, 0x80 +.LBB5_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1184.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v1, 64, v1 + v_add_u32_e32 v66, 64, v66 + v_lshlrev_b32_e32 v0, 1, v66 + v_add_u32_e32 v2, s7, v66 + v_lshlrev_b32_e32 v3, 1, v1 + v_add_u32_e32 v6, s20, v1 + v_lshlrev_b32_e32 v7, 1, v2 + v_add_u32_e32 v8, s7, v2 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 0 offen + v_lshlrev_b32_e32 v9, 1, v6 + v_add_u32_e32 v10, s20, v6 + buffer_load_dwordx4 v[14:17], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[18:21], v7, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v8 + v_add_u32_e32 v11, s7, v8 + buffer_load_dwordx4 v[6:9], v9, s[12:15], 0 offen + v_lshlrev_b32_e32 v12, 1, v10 + v_add_u32_e32 v22, s20, v10 + v_lshlrev_b32_e32 v23, 1, v11 + v_add_u32_e32 v24, s7, v11 + buffer_load_dwordx4 v[10:13], v12, s[12:15], 0 offen + v_lshlrev_b32_e32 v25, 1, v22 + v_add_u32_e32 v26, s20, v22 + buffer_load_dwordx4 v[30:33], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[34:37], v23, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v24 + v_add_u32_e32 v27, s7, v24 + buffer_load_dwordx4 v[22:25], v25, s[12:15], 0 offen + v_lshlrev_b32_e32 v28, 1, v26 + v_add_u32_e32 v38, s20, v26 + v_lshlrev_b32_e32 v39, 1, v27 + v_add_u32_e32 v40, s7, v27 + buffer_load_dwordx4 v[26:29], v28, s[12:15], 0 offen + v_lshlrev_b32_e32 v41, 1, v38 + v_add_u32_e32 v42, s20, v38 + buffer_load_dwordx4 v[50:53], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v39, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v40 + v_add_lshl_u32 v43, v40, s7, 1 + buffer_load_dwordx4 v[38:41], v41, s[12:15], 0 offen + v_lshlrev_b32_e32 v44, 1, v42 + v_add_lshl_u32 v46, v42, s20, 1 + buffer_load_dwordx4 v[58:61], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v43, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[42:45], v44, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[46:49], v46, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[120:123], v100 + ds_read_b128 v[116:119], v99 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[64:79], v[120:121], v[116:117], a[64:79] + ds_read_b128 v[128:131], v109 offset:40960 + ds_read_b128 v[112:115], v108 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[48:63], v[120:121], v[128:129], a[48:63] + v_lshlrev_b32_e32 v0, 1, v97 + ds_read_b128 v[136:139], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v98 + ds_read_b128 v[124:127], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[120:121], v[136:137], a[0:15] + v_lshlrev_b32_e32 v0, 1, v95 + ds_read_b128 v[140:143], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v96 + ds_read_b128 v[132:135], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[140:141], a[112:127] + ds_read_b128 v[144:147], v105 offset:8192 + v_lshlrev_b32_e32 v0, 1, v92 + ds_read_b128 v[148:151], v0 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[144:145], v[116:117], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[144:145], v[128:129], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[144:145], v[136:137], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[144:145], v[140:141], a[176:191] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[116:117], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[128:129], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[136:137], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[140:141], a[240:255] + v_lshlrev_b32_e32 v0, 1, v91 + ds_read_b128 v[152:155], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[152:153], v[116:117], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[152:153], v[128:129], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[136:137], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[140:141], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[122:123], v[118:119], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[122:123], v[130:131], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[122:123], v[138:139], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[122:123], v[142:143], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[146:147], v[118:119], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[146:147], v[130:131], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[146:147], v[138:139], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[146:147], v[142:143], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[150:151], v[118:119], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[150:151], v[130:131], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[150:151], v[138:139], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[150:151], v[142:143], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[154:155], v[118:119], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[154:155], v[130:131], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[154:155], v[138:139], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[142:143], a[32:47] + ds_read_b128 v[116:119], v102 + ds_read_b128 v[120:123], v106 offset:32768 + ds_read_b128 v[128:131], v102 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[116:117], v[120:121], a[64:79] + ds_read_b128 v[136:139], v106 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[48:63], v[116:117], v[136:137], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[116:117], v[124:125], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[116:117], v[132:133], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[120:121], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[128:129], v[136:137], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[128:129], v[124:125], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[128:129], v[132:133], a[176:191] + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[140:143], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[144:147], v0 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[140:141], v[120:121], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[140:141], v[136:137], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[140:141], v[124:125], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[140:141], v[132:133], a[240:255] + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[148:151], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[152:155], v0 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[148:149], v[120:121], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[148:149], v[136:137], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[148:149], v[124:125], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[148:149], v[132:133], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[118:119], v[122:123], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[118:119], v[138:139], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[118:119], v[126:127], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[118:119], v[134:135], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[130:131], v[122:123], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[130:131], v[138:139], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[130:131], v[126:127], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[130:131], v[134:135], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[122:123], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[138:139], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[126:127], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[142:143], v[134:135], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[150:151], v[122:123], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[150:151], v[138:139], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[126:127], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[134:135], a[32:47] + ds_read_b128 v[124:127], v103 + ds_read_b128 v[128:131], v107 offset:32768 + ds_read_b128 v[132:135], v103 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[124:125], v[128:129], a[64:79] + ds_read_b128 v[136:139], v107 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[48:63], v[124:125], v[136:137], a[48:63] + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[140:143], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[120:123], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[124:125], v[140:141], a[0:15] + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[148:151], v0 offset:40960 + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[116:119], v0 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[124:125], v[148:149], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[132:133], v[128:129], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[132:133], v[136:137], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[132:133], v[140:141], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[132:133], v[148:149], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[144:145], v[128:129], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[144:145], v[136:137], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[144:145], v[140:141], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[148:149], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[152:153], v[128:129], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[152:153], v[136:137], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[140:141], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[148:149], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[130:131], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[126:127], v[138:139], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[126:127], v[142:143], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[126:127], v[150:151], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[134:135], v[130:131], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[134:135], v[138:139], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[134:135], v[142:143], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[134:135], v[150:151], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[130:131], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[138:139], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[142:143], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[150:151], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[154:155], v[130:131], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[154:155], v[138:139], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[154:155], v[142:143], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[150:151], a[32:47] + ds_read_b128 v[132:135], v104 + ds_read_b128 v[124:127], v108 offset:32768 + ds_read_b128 v[128:131], v104 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[132:133], v[124:125], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[132:133], v[112:113], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[132:133], v[120:121], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[132:133], v[116:117], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[124:125], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[128:129], v[112:113], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[128:129], v[120:121], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[128:129], v[116:117], a[176:191] + v_lshlrev_b32_e32 v0, 1, v71 + ds_read_b128 v[136:139], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[136:137], v[124:125], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[136:137], v[112:113], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[136:137], v[120:121], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[136:137], v[116:117], a[240:255] + v_lshlrev_b32_e32 v0, 1, v70 + ds_read_b128 v[140:143], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[140:141], v[124:125], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[140:141], v[112:113], a[80:95] + v_mfma_f32_32x32x8_f16 a[16:31], v[140:141], v[120:121], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[140:141], v[116:117], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[134:135], v[126:127], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[134:135], v[114:115], a[48:63] + v_mfma_f32_32x32x8_f16 a[0:15], v[134:135], v[122:123], a[0:15] + v_mfma_f32_32x32x8_f16 a[112:127], v[134:135], v[118:119], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[130:131], v[126:127], a[128:143] + v_mfma_f32_32x32x8_f16 a[144:159], v[130:131], v[114:115], a[144:159] + v_readfirstlane_b32 s6, v227 + s_add_i32 s2, s2, -1 + v_mfma_f32_32x32x8_f16 a[160:175], v[130:131], v[122:123], a[160:175] + s_andn2_b32 s6, s6, 63 + v_add_u32_e32 v0, s6, v101 + s_cmp_gt_u32 s2, 2 + v_lshl_or_b32 v68, v0, 7, v110 + v_or_b32_e32 v111, 1, v0 + v_ashrrev_i32_e32 v112, 31, v0 + v_or_b32_e32 v113, 2, v0 + v_mfma_f32_32x32x8_f16 a[176:191], v[130:131], v[118:119], a[176:191] + v_or_b32_e32 v116, 3, v0 + v_or_b32_e32 v117, 4, v0 + v_or_b32_e32 v120, 5, v0 + v_or_b32_e32 v121, 6, v0 + v_or_b32_e32 v0, 7, v0 + v_lshrrev_b32_e32 v112, 29, v112 + v_add_u32_e32 v124, v111, v112 + v_mfma_f32_32x32x8_f16 a[192:207], v[138:139], v[126:127], a[192:207] + v_add_u32_e32 v125, v113, v112 + v_add_u32_e32 v128, v116, v112 + v_add_u32_e32 v129, v117, v112 + v_add_u32_e32 v130, v120, v112 + v_add_u32_e32 v131, v121, v112 + v_add_u32_e32 v112, v0, v112 + v_and_b32_e32 v124, -8, v124 + v_mfma_f32_32x32x8_f16 a[208:223], v[138:139], v[114:115], a[208:223] + v_and_b32_e32 v125, -8, v125 + v_and_b32_e32 v128, -8, v128 + v_and_b32_e32 v129, -8, v129 + v_and_b32_e32 v130, -8, v130 + v_and_b32_e32 v131, -8, v131 + v_and_b32_e32 v112, 0xffffff8, v112 + v_sub_u32_e32 v111, v111, v124 + v_mfma_f32_32x32x8_f16 a[224:239], v[138:139], v[122:123], a[224:239] + v_sub_u32_e32 v113, v113, v125 + v_sub_u32_e32 v116, v116, v128 + v_sub_u32_e32 v117, v117, v129 + v_sub_u32_e32 v120, v120, v130 + v_sub_u32_e32 v121, v121, v131 + v_sub_u32_e32 v0, v0, v112 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[240:255], v[138:139], v[118:119], a[240:255] + s_barrier + v_xor_b32_e32 v111, v111, v69 + v_xor_b32_e32 v112, v113, v69 + v_xor_b32_e32 v113, v116, v69 + v_xor_b32_e32 v116, v117, v69 + v_xor_b32_e32 v117, v120, v69 + v_xor_b32_e32 v120, v121, v69 + v_mfma_f32_32x32x8_f16 a[96:111], v[142:143], v[126:127], a[96:111] + v_xor_b32_e32 v0, v0, v69 + v_sub_u32_e32 v121, v111, v69 + v_sub_u32_e32 v111, v112, v111 + v_sub_u32_e32 v112, v113, v112 + v_sub_u32_e32 v113, v116, v113 + v_sub_u32_e32 v116, v117, v116 + v_sub_u32_e32 v117, v120, v117 + v_mfma_f32_32x32x8_f16 a[80:95], v[142:143], v[114:115], a[80:95] + v_sub_u32_e32 v0, v0, v120 + v_lshl_add_u32 v114, v121, 4, v68 + v_lshlrev_b32_e32 v111, 4, v111 + v_lshlrev_b32_e32 v112, 4, v112 + v_lshlrev_b32_e32 v113, 4, v113 + v_lshlrev_b32_e32 v115, 4, v116 + v_lshlrev_b32_e32 v116, 4, v117 + v_mfma_f32_32x32x8_f16 a[16:31], v[142:143], v[122:123], a[16:31] + v_add3_u32 v111, v114, s3, v111 + v_add3_u32 v112, v111, s3, v112 + v_add3_u32 v113, v112, s3, v113 + v_add3_u32 v115, v113, s3, v115 + v_add3_u32 v116, v115, s3, v116 + v_add_u32_e32 v117, 0x80, v116 + v_lshl_add_u32 v0, v0, 4, v117 + v_mfma_f32_32x32x8_f16 a[32:47], v[142:143], v[118:119], a[32:47] + s_waitcnt vmcnt(14) + ds_write_b128 v68, v[14:17] + s_waitcnt vmcnt(13) + ds_write_b128 v114, v[18:21] offset:128 + s_waitcnt vmcnt(10) + ds_write_b128 v111, v[30:33] offset:128 + s_waitcnt vmcnt(9) + ds_write_b128 v112, v[34:37] offset:128 + s_waitcnt vmcnt(6) + ds_write_b128 v113, v[50:53] offset:128 + s_waitcnt vmcnt(5) + ds_write_b128 v115, v[54:57] offset:128 + s_waitcnt vmcnt(3) + ds_write_b128 v116, v[58:61] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v0, v[62:65] offset:128 + ds_write_b128 v68, v[2:5] offset:32768 + ds_write_b128 v114, v[6:9] offset:32896 + ds_write_b128 v111, v[10:13] offset:32896 + ds_write_b128 v112, v[22:25] offset:32896 + ds_write_b128 v113, v[26:29] offset:32896 + ds_write_b128 v115, v[38:41] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v116, v[42:45] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v0, v[46:49] offset:32896 + s_cbranch_scc1 .LBB5_8 +.LBB5_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_R + v_accvgpr_read_b32 v166, a112 + v_accvgpr_read_b32 v167, a113 + v_accvgpr_read_b32 v168, a114 + v_accvgpr_read_b32 v169, a115 + v_accvgpr_read_b32 v170, a116 + v_accvgpr_read_b32 v171, a117 + v_accvgpr_read_b32 v172, a118 + v_accvgpr_read_b32 v173, a119 + v_accvgpr_read_b32 v174, a120 + v_accvgpr_read_b32 v175, a121 + v_accvgpr_read_b32 v176, a122 + v_accvgpr_read_b32 v177, a123 + v_accvgpr_read_b32 v178, a124 + v_accvgpr_read_b32 v179, a125 + v_accvgpr_read_b32 v180, a126 + v_accvgpr_read_b32 v181, a127 + v_accvgpr_read_b32 v150, a128 + v_accvgpr_read_b32 v151, a129 + v_accvgpr_read_b32 v152, a130 + v_accvgpr_read_b32 v153, a131 + v_accvgpr_read_b32 v154, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v156, a134 + v_accvgpr_read_b32 v157, a135 + v_accvgpr_read_b32 v158, a136 + v_accvgpr_read_b32 v159, a137 + v_accvgpr_read_b32 v160, a138 + v_accvgpr_read_b32 v161, a139 + v_accvgpr_read_b32 v162, a140 + v_accvgpr_read_b32 v163, a141 + v_accvgpr_read_b32 v164, a142 + v_accvgpr_read_b32 v165, a143 + v_accvgpr_mov_b32 a128, a160 + v_accvgpr_mov_b32 a129, a161 + v_accvgpr_mov_b32 a130, a162 + v_accvgpr_mov_b32 a131, a163 + v_accvgpr_mov_b32 a132, a164 + v_accvgpr_mov_b32 a133, a165 + v_accvgpr_mov_b32 a134, a166 + v_accvgpr_mov_b32 a135, a167 + v_accvgpr_mov_b32 a136, a168 + v_accvgpr_mov_b32 a137, a169 + v_accvgpr_mov_b32 a138, a170 + v_accvgpr_mov_b32 a139, a171 + v_accvgpr_mov_b32 a140, a172 + v_accvgpr_mov_b32 a141, a173 + v_accvgpr_mov_b32 a142, a174 + v_accvgpr_mov_b32 a143, a175 + v_accvgpr_mov_b32 a112, a176 + v_accvgpr_mov_b32 a113, a177 + v_accvgpr_mov_b32 a114, a178 + v_accvgpr_mov_b32 a115, a179 + v_accvgpr_mov_b32 a116, a180 + v_accvgpr_mov_b32 a117, a181 + v_accvgpr_mov_b32 a118, a182 + v_accvgpr_mov_b32 a119, a183 + v_accvgpr_mov_b32 a120, a184 + v_accvgpr_mov_b32 a121, a185 + v_accvgpr_mov_b32 a122, a186 + v_accvgpr_mov_b32 a123, a187 + v_accvgpr_mov_b32 a124, a188 + v_accvgpr_mov_b32 a125, a189 + v_accvgpr_mov_b32 a126, a190 + v_accvgpr_mov_b32 a127, a191 + v_accvgpr_read_b32 v134, a192 + v_accvgpr_read_b32 v135, a193 + v_accvgpr_read_b32 v136, a194 + v_accvgpr_read_b32 v137, a195 + v_accvgpr_read_b32 v138, a196 + v_accvgpr_read_b32 v139, a197 + v_accvgpr_read_b32 v140, a198 + v_accvgpr_read_b32 v141, a199 + v_accvgpr_read_b32 v142, a200 + v_accvgpr_read_b32 v143, a201 + v_accvgpr_read_b32 v144, a202 + v_accvgpr_read_b32 v145, a203 + v_accvgpr_read_b32 v146, a204 + v_accvgpr_read_b32 v147, a205 + v_accvgpr_read_b32 v148, a206 + v_accvgpr_read_b32 v149, a207 + v_accvgpr_read_b32 v118, a208 + v_accvgpr_read_b32 v119, a209 + v_accvgpr_read_b32 v120, a210 + v_accvgpr_read_b32 v121, a211 + v_accvgpr_read_b32 v122, a212 + v_accvgpr_read_b32 v123, a213 + v_accvgpr_read_b32 v124, a214 + v_accvgpr_read_b32 v125, a215 + v_accvgpr_read_b32 v126, a216 + v_accvgpr_read_b32 v127, a217 + v_accvgpr_read_b32 v128, a218 + v_accvgpr_read_b32 v129, a219 + v_accvgpr_read_b32 v130, a220 + v_accvgpr_read_b32 v131, a221 + v_accvgpr_read_b32 v132, a222 + v_accvgpr_read_b32 v133, a223 + v_accvgpr_read_b32 v102, a224 + v_accvgpr_read_b32 v103, a225 + v_accvgpr_read_b32 v104, a226 + v_accvgpr_read_b32 v105, a227 + v_accvgpr_read_b32 v106, a228 + v_accvgpr_read_b32 v107, a229 + v_accvgpr_read_b32 v108, a230 + v_accvgpr_read_b32 v109, a231 + v_accvgpr_read_b32 v110, a232 + v_accvgpr_read_b32 v111, a233 + v_accvgpr_read_b32 v112, a234 + v_accvgpr_read_b32 v113, a235 + v_accvgpr_read_b32 v114, a236 + v_accvgpr_read_b32 v115, a237 + v_accvgpr_read_b32 v116, a238 + v_accvgpr_read_b32 v117, a239 + v_accvgpr_read_b32 v48, a240 + v_accvgpr_read_b32 v49, a241 + v_accvgpr_read_b32 v50, a242 + v_accvgpr_read_b32 v51, a243 + v_accvgpr_read_b32 v52, a244 + v_accvgpr_read_b32 v53, a245 + v_accvgpr_read_b32 v54, a246 + v_accvgpr_read_b32 v55, a247 + v_accvgpr_read_b32 v56, a248 + v_accvgpr_read_b32 v57, a249 + v_accvgpr_read_b32 v58, a250 + v_accvgpr_read_b32 v59, a251 + v_accvgpr_read_b32 v60, a252 + v_accvgpr_read_b32 v61, a253 + v_accvgpr_read_b32 v62, a254 + v_accvgpr_read_b32 v63, a255 + v_accvgpr_read_b32 v32, a96 + v_accvgpr_read_b32 v33, a97 + v_accvgpr_read_b32 v34, a98 + v_accvgpr_read_b32 v35, a99 + v_accvgpr_read_b32 v36, a100 + v_accvgpr_read_b32 v37, a101 + v_accvgpr_read_b32 v38, a102 + v_accvgpr_read_b32 v39, a103 + v_accvgpr_read_b32 v40, a104 + v_accvgpr_read_b32 v41, a105 + v_accvgpr_read_b32 v42, a106 + v_accvgpr_read_b32 v43, a107 + v_accvgpr_read_b32 v44, a108 + v_accvgpr_read_b32 v45, a109 + v_accvgpr_read_b32 v46, a110 + v_accvgpr_read_b32 v47, a111 + v_accvgpr_read_b32 v16, a80 + v_accvgpr_read_b32 v17, a81 + v_accvgpr_read_b32 v18, a82 + v_accvgpr_read_b32 v19, a83 + v_accvgpr_read_b32 v20, a84 + v_accvgpr_read_b32 v21, a85 + v_accvgpr_read_b32 v22, a86 + v_accvgpr_read_b32 v23, a87 + v_accvgpr_read_b32 v24, a88 + v_accvgpr_read_b32 v25, a89 + v_accvgpr_read_b32 v26, a90 + v_accvgpr_read_b32 v27, a91 + v_accvgpr_read_b32 v28, a92 + v_accvgpr_read_b32 v29, a93 + v_accvgpr_read_b32 v30, a94 + v_accvgpr_read_b32 v31, a95 + v_accvgpr_read_b32 v0, a16 + v_accvgpr_read_b32 v1, a17 + v_accvgpr_read_b32 v2, a18 + v_accvgpr_read_b32 v3, a19 + v_accvgpr_read_b32 v4, a20 + v_accvgpr_read_b32 v5, a21 + v_accvgpr_read_b32 v6, a22 + v_accvgpr_read_b32 v7, a23 + v_accvgpr_read_b32 v8, a24 + v_accvgpr_read_b32 v9, a25 + v_accvgpr_read_b32 v10, a26 + v_accvgpr_read_b32 v11, a27 + v_accvgpr_read_b32 v12, a28 + v_accvgpr_read_b32 v13, a29 + v_accvgpr_read_b32 v14, a30 + v_accvgpr_read_b32 v15, a31 + v_accvgpr_mov_b32 a240, a32 + v_accvgpr_mov_b32 a241, a33 + v_accvgpr_mov_b32 a242, a34 + v_accvgpr_mov_b32 a243, a35 + v_accvgpr_mov_b32 a244, a36 + v_accvgpr_mov_b32 a245, a37 + v_accvgpr_mov_b32 a246, a38 + v_accvgpr_mov_b32 a247, a39 + v_accvgpr_mov_b32 a248, a40 + v_accvgpr_mov_b32 a249, a41 + v_accvgpr_mov_b32 a250, a42 + v_accvgpr_mov_b32 a251, a43 + v_accvgpr_mov_b32 a252, a44 + v_accvgpr_mov_b32 a253, a45 + v_accvgpr_mov_b32 a254, a46 + v_accvgpr_mov_b32 a255, a47 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[182:185], v100 + ds_read_b128 v[186:189], v99 offset:32768 + v_accvgpr_mov_b32 a175, a79 + v_accvgpr_mov_b32 a174, a78 + v_accvgpr_mov_b32 a173, a77 + v_accvgpr_mov_b32 a172, a76 + v_accvgpr_mov_b32 a171, a75 + v_accvgpr_mov_b32 a170, a74 + v_accvgpr_mov_b32 a169, a73 + v_accvgpr_mov_b32 a168, a72 + v_accvgpr_mov_b32 a167, a71 + v_accvgpr_mov_b32 a166, a70 + v_accvgpr_mov_b32 a165, a69 + v_accvgpr_mov_b32 a164, a68 + v_accvgpr_mov_b32 a163, a67 + v_accvgpr_mov_b32 a162, a66 + v_accvgpr_mov_b32 a161, a65 + v_accvgpr_mov_b32 a160, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[182:183], v[186:187], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[184:185], v[188:189], a[160:175] + v_lshlrev_b32_e32 v64, 1, v97 + ds_read_b128 v[190:193], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v98 + v_accvgpr_mov_b32 a207, a63 + v_accvgpr_mov_b32 a206, a62 + v_accvgpr_mov_b32 a205, a61 + v_accvgpr_mov_b32 a204, a60 + v_accvgpr_mov_b32 a203, a59 + v_accvgpr_mov_b32 a202, a58 + v_accvgpr_mov_b32 a201, a57 + v_accvgpr_mov_b32 a200, a56 + v_accvgpr_mov_b32 a199, a55 + v_accvgpr_mov_b32 a198, a54 + v_accvgpr_mov_b32 a197, a53 + v_accvgpr_mov_b32 a196, a52 + v_accvgpr_mov_b32 a195, a51 + v_accvgpr_mov_b32 a194, a50 + v_accvgpr_mov_b32 a193, a49 + v_accvgpr_mov_b32 a192, a48 + ds_read_b128 v[98:101], v64 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[182:183], v[190:191], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[184:185], v[192:193], a[192:207] + v_lshlrev_b32_e32 v64, 1, v95 + ds_read_b128 v[194:197], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v96 + ds_read_b128 v[198:201], v64 offset:32768 + v_accvgpr_mov_b32 a239, a15 + v_accvgpr_mov_b32 a238, a14 + v_accvgpr_mov_b32 a237, a13 + v_accvgpr_mov_b32 a236, a12 + v_accvgpr_mov_b32 a235, a11 + v_accvgpr_mov_b32 a234, a10 + v_accvgpr_mov_b32 a233, a9 + v_accvgpr_mov_b32 a232, a8 + v_accvgpr_mov_b32 a231, a7 + v_accvgpr_mov_b32 a230, a6 + v_accvgpr_mov_b32 a229, a5 + v_accvgpr_mov_b32 a228, a4 + v_accvgpr_mov_b32 a227, a3 + v_accvgpr_mov_b32 a226, a2 + v_accvgpr_mov_b32 a225, a1 + v_accvgpr_mov_b32 a224, a0 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[182:183], v[194:195], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[184:185], v[196:197], a[224:239] + v_lshlrev_b32_e32 v64, 1, v93 + ds_read_b128 v[202:205], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v94 + ds_read_b128 v[94:97], v64 offset:32768 + v_accvgpr_write_b32 a223, v181 + v_accvgpr_write_b32 a222, v180 + v_accvgpr_write_b32 a221, v179 + v_accvgpr_write_b32 a220, v178 + v_accvgpr_write_b32 a219, v177 + v_accvgpr_write_b32 a218, v176 + v_accvgpr_write_b32 a217, v175 + v_accvgpr_write_b32 a216, v174 + v_accvgpr_write_b32 a215, v173 + v_accvgpr_write_b32 a214, v172 + v_accvgpr_write_b32 a213, v171 + v_accvgpr_write_b32 a212, v170 + v_accvgpr_write_b32 a211, v169 + v_accvgpr_write_b32 a210, v168 + v_accvgpr_write_b32 a209, v167 + v_accvgpr_write_b32 a208, v166 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[182:183], v[202:203], a[208:223] + v_lshlrev_b32_e32 v64, 1, v92 + v_mfma_f32_32x32x8_f16 a[208:223], v[184:185], v[204:205], a[208:223] + ds_read_b128 v[166:169], v64 + v_accvgpr_write_b32 a191, v165 + v_accvgpr_write_b32 a190, v164 + v_accvgpr_write_b32 a189, v163 + v_accvgpr_write_b32 a188, v162 + v_accvgpr_write_b32 a187, v161 + v_accvgpr_write_b32 a186, v160 + v_accvgpr_write_b32 a185, v159 + v_accvgpr_write_b32 a184, v158 + v_accvgpr_write_b32 a183, v157 + v_accvgpr_write_b32 a182, v156 + v_accvgpr_write_b32 a181, v155 + v_accvgpr_write_b32 a180, v154 + v_accvgpr_write_b32 a179, v153 + v_accvgpr_write_b32 a178, v152 + v_accvgpr_write_b32 a177, v151 + v_accvgpr_write_b32 a176, v150 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[166:167], v[186:187], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[168:169], v[188:189], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[166:167], v[190:191], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[168:169], v[192:193], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[166:167], v[194:195], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[168:169], v[196:197], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[166:167], v[202:203], a[112:127] + v_lshlrev_b32_e32 v64, 1, v91 + v_mfma_f32_32x32x8_f16 a[112:127], v[168:169], v[204:205], a[112:127] + ds_read_b128 v[150:153], v64 + v_accvgpr_write_b32 a96, v134 + v_accvgpr_write_b32 a97, v135 + v_accvgpr_write_b32 a98, v136 + v_accvgpr_write_b32 a99, v137 + v_accvgpr_write_b32 a100, v138 + v_accvgpr_write_b32 a101, v139 + v_accvgpr_write_b32 a102, v140 + v_accvgpr_write_b32 a103, v141 + v_accvgpr_write_b32 a104, v142 + v_accvgpr_write_b32 a105, v143 + v_accvgpr_write_b32 a106, v144 + v_accvgpr_write_b32 a107, v145 + v_accvgpr_write_b32 a108, v146 + v_accvgpr_write_b32 a109, v147 + v_accvgpr_write_b32 a110, v148 + v_accvgpr_write_b32 a111, v149 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[150:151], v[186:187], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[152:153], v[188:189], a[96:111] + v_accvgpr_write_b32 a80, v118 + v_accvgpr_write_b32 a81, v119 + v_accvgpr_write_b32 a82, v120 + v_accvgpr_write_b32 a83, v121 + v_accvgpr_write_b32 a84, v122 + v_accvgpr_write_b32 a85, v123 + v_accvgpr_write_b32 a86, v124 + v_accvgpr_write_b32 a87, v125 + v_accvgpr_write_b32 a88, v126 + v_accvgpr_write_b32 a89, v127 + v_accvgpr_write_b32 a90, v128 + v_accvgpr_write_b32 a91, v129 + v_accvgpr_write_b32 a92, v130 + v_accvgpr_write_b32 a93, v131 + v_accvgpr_write_b32 a94, v132 + v_accvgpr_write_b32 a95, v133 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[80:95], v[150:151], v[190:191], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[152:153], v[192:193], a[80:95] + v_accvgpr_write_b32 a64, v102 + v_accvgpr_write_b32 a65, v103 + v_accvgpr_write_b32 a66, v104 + v_accvgpr_write_b32 a67, v105 + v_accvgpr_write_b32 a68, v106 + v_accvgpr_write_b32 a69, v107 + v_accvgpr_write_b32 a70, v108 + v_accvgpr_write_b32 a71, v109 + v_accvgpr_write_b32 a72, v110 + v_accvgpr_write_b32 a73, v111 + v_accvgpr_write_b32 a74, v112 + v_accvgpr_write_b32 a75, v113 + v_accvgpr_write_b32 a76, v114 + v_accvgpr_write_b32 a77, v115 + v_accvgpr_write_b32 a78, v116 + v_accvgpr_write_b32 a79, v117 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], v[150:151], v[194:195], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[152:153], v[196:197], a[64:79] + v_accvgpr_write_b32 a48, v48 + v_accvgpr_write_b32 a49, v49 + v_accvgpr_write_b32 a50, v50 + v_accvgpr_write_b32 a51, v51 + v_accvgpr_write_b32 a52, v52 + v_accvgpr_write_b32 a53, v53 + v_accvgpr_write_b32 a54, v54 + v_accvgpr_write_b32 a55, v55 + v_accvgpr_write_b32 a56, v56 + v_accvgpr_write_b32 a57, v57 + v_accvgpr_write_b32 a58, v58 + v_accvgpr_write_b32 a59, v59 + v_accvgpr_write_b32 a60, v60 + v_accvgpr_write_b32 a61, v61 + v_accvgpr_write_b32 a62, v62 + v_accvgpr_write_b32 a63, v63 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[202:203], a[48:63] + v_lshlrev_b32_e32 v48, 1, v90 + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[204:205], a[48:63] + ds_read_b128 v[48:51], v48 + v_accvgpr_write_b32 a32, v32 + v_accvgpr_write_b32 a33, v33 + v_accvgpr_write_b32 a34, v34 + v_accvgpr_write_b32 a35, v35 + v_accvgpr_write_b32 a36, v36 + v_accvgpr_write_b32 a37, v37 + v_accvgpr_write_b32 a38, v38 + v_accvgpr_write_b32 a39, v39 + v_accvgpr_write_b32 a40, v40 + v_accvgpr_write_b32 a41, v41 + v_accvgpr_write_b32 a42, v42 + v_accvgpr_write_b32 a43, v43 + v_accvgpr_write_b32 a44, v44 + v_accvgpr_write_b32 a45, v45 + v_accvgpr_write_b32 a46, v46 + v_accvgpr_write_b32 a47, v47 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[48:49], v[186:187], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[50:51], v[188:189], a[32:47] + v_accvgpr_write_b32 a16, v16 + v_accvgpr_write_b32 a17, v17 + v_accvgpr_write_b32 a18, v18 + v_accvgpr_write_b32 a19, v19 + v_accvgpr_write_b32 a20, v20 + v_accvgpr_write_b32 a21, v21 + v_accvgpr_write_b32 a22, v22 + v_accvgpr_write_b32 a23, v23 + v_accvgpr_write_b32 a24, v24 + v_accvgpr_write_b32 a25, v25 + v_accvgpr_write_b32 a26, v26 + v_accvgpr_write_b32 a27, v27 + v_accvgpr_write_b32 a28, v28 + v_accvgpr_write_b32 a29, v29 + v_accvgpr_write_b32 a30, v30 + v_accvgpr_write_b32 a31, v31 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[16:31], v[48:49], v[190:191], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[50:51], v[192:193], a[16:31] + v_accvgpr_write_b32 a0, v0 + v_accvgpr_write_b32 a1, v1 + v_accvgpr_write_b32 a2, v2 + v_accvgpr_write_b32 a3, v3 + v_accvgpr_write_b32 a4, v4 + v_accvgpr_write_b32 a5, v5 + v_accvgpr_write_b32 a6, v6 + v_accvgpr_write_b32 a7, v7 + v_accvgpr_write_b32 a8, v8 + v_accvgpr_write_b32 a9, v9 + v_accvgpr_write_b32 a10, v10 + v_accvgpr_write_b32 a11, v11 + v_accvgpr_write_b32 a12, v12 + v_accvgpr_write_b32 a13, v13 + v_accvgpr_write_b32 a14, v14 + v_accvgpr_write_b32 a15, v15 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[0:15], v[48:49], v[194:195], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[50:51], v[196:197], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[48:49], v[202:203], a[240:255] + v_lshlrev_b32_e32 v0, 1, v85 + v_mfma_f32_32x32x8_f16 a[240:255], v[50:51], v[204:205], a[240:255] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[6:9], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[10:13], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[4:5], v[8:9], a[160:175] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[98:99], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[4:5], v[100:101], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[198:199], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[4:5], v[200:201], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[94:95], a[208:223] + v_lshlrev_b32_e32 v0, 1, v88 + v_mfma_f32_32x32x8_f16 a[208:223], v[4:5], v[96:97], a[208:223] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[14:17], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[98:99], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[4:5], v[100:101], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[198:199], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[4:5], v[200:201], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[94:95], a[112:127] + v_lshlrev_b32_e32 v0, 1, v82 + v_mfma_f32_32x32x8_f16 a[112:127], v[4:5], v[96:97], a[112:127] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[18:21], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[98:99], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[4:5], v[100:101], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[198:199], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[4:5], v[200:201], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[94:95], a[48:63] + v_lshlrev_b32_e32 v0, 1, v78 + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[96:97], a[48:63] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[22:25], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[4:5], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[98:99], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[100:101], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[198:199], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[4:5], v[200:201], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[94:95], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[96:97], a[240:255] + v_lshlrev_b32_e32 v0, 1, v73 + ds_read_b128 v[2:5], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v74 + ds_read_b128 v[6:9], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[12:13], v[4:5], a[160:175] + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[26:29], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[30:33], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[10:11], v[26:27], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[12:13], v[28:29], a[192:207] + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[34:37], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[38:41], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[10:11], v[34:35], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[12:13], v[36:37], a[224:239] + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[42:45], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[46:49], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[208:223], v[10:11], v[42:43], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_f16 a[176:191], v[14:15], v[2:3], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[16:17], v[4:5], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[14:15], v[26:27], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[16:17], v[28:29], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[14:15], v[34:35], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[16:17], v[36:37], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[14:15], v[42:43], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[16:17], v[44:45], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[18:19], v[2:3], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[20:21], v[4:5], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[18:19], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[20:21], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[18:19], v[34:35], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[20:21], v[36:37], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[18:19], v[42:43], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[20:21], v[44:45], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[22:23], v[2:3], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[24:25], v[4:5], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[22:23], v[26:27], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[24:25], v[28:29], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[22:23], v[34:35], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[24:25], v[36:37], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[22:23], v[42:43], a[240:255] + v_lshlrev_b32_e32 v0, 1, v72 + v_mfma_f32_32x32x8_f16 a[240:255], v[24:25], v[44:45], a[240:255] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[160:175], v[0:1], v[6:7], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[8:9], a[160:175] + v_mfma_f32_32x32x8_f16 a[192:207], v[0:1], v[30:31], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[0:1], v[38:39], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[40:41], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[0:1], v[46:47], a[208:223] + v_lshlrev_b32_e32 v0, 1, v71 + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[48:49], a[208:223] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[0:1], v[6:7], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[8:9], a[176:191] + v_mfma_f32_32x32x8_f16 a[144:159], v[0:1], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[32:33], a[144:159] + v_mfma_f32_32x32x8_f16 a[128:143], v[0:1], v[38:39], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[40:41], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[0:1], v[46:47], a[112:127] + v_lshlrev_b32_e32 v0, 1, v70 + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[48:49], a[112:127] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[0:1], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[0:1], v[30:31], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[32:33], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[0:1], v[38:39], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[40:41], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[0:1], v[46:47], a[48:63] + v_lshlrev_b32_e32 v0, 1, v67 + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[48:49], a[48:63] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[0:1], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[0:1], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[0:1], v[38:39], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[40:41], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[0:1], v[46:47], a[240:255] + v_mov_b32_e32 v1, v69 + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[48:49], a[240:255] +.LBB5_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEDF16_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RK + v_accvgpr_read_b32 v143, a160 + v_accvgpr_read_b32 v142, a161 + v_accvgpr_read_b32 v141, a162 + v_accvgpr_read_b32 v140, a163 + v_accvgpr_read_b32 v139, a164 + v_accvgpr_read_b32 v68, a165 + v_accvgpr_read_b32 v18, a166 + v_accvgpr_read_b32 v138, a167 + v_accvgpr_read_b32 v137, a168 + v_accvgpr_read_b32 v136, a169 + v_accvgpr_read_b32 v135, a170 + v_accvgpr_read_b32 v134, a171 + v_accvgpr_read_b32 v133, a172 + v_accvgpr_read_b32 v132, a173 + v_accvgpr_read_b32 v131, a174 + v_accvgpr_read_b32 v130, a175 + v_accvgpr_read_b32 v107, a192 + v_accvgpr_read_b32 v106, a193 + v_accvgpr_read_b32 v105, a194 + v_accvgpr_read_b32 v104, a195 + v_accvgpr_read_b32 v103, a196 + v_accvgpr_read_b32 v102, a197 + v_accvgpr_read_b32 v101, a198 + v_accvgpr_read_b32 v100, a199 + v_accvgpr_read_b32 v99, a200 + v_accvgpr_read_b32 v98, a201 + v_accvgpr_read_b32 v97, a202 + v_accvgpr_read_b32 v96, a203 + v_accvgpr_read_b32 v95, a204 + v_accvgpr_read_b32 v94, a205 + v_accvgpr_read_b32 v93, a206 + v_accvgpr_read_b32 v92, a207 + v_accvgpr_read_b32 v91, a224 + v_accvgpr_read_b32 v90, a225 + v_accvgpr_read_b32 v89, a226 + v_accvgpr_read_b32 v88, a227 + v_accvgpr_read_b32 v87, a228 + v_accvgpr_read_b32 v86, a229 + v_accvgpr_read_b32 v85, a230 + v_accvgpr_read_b32 v84, a231 + v_accvgpr_read_b32 v83, a232 + v_accvgpr_read_b32 v82, a233 + v_accvgpr_read_b32 v81, a234 + v_accvgpr_read_b32 v80, a235 + v_accvgpr_read_b32 v79, a236 + v_accvgpr_read_b32 v78, a237 + v_accvgpr_read_b32 v77, a238 + v_accvgpr_read_b32 v76, a239 + v_accvgpr_read_b32 v75, a208 + v_accvgpr_read_b32 v74, a209 + v_accvgpr_read_b32 v73, a210 + v_accvgpr_read_b32 v72, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v70, a213 + v_accvgpr_read_b32 v69, a214 + v_accvgpr_read_b32 v67, a215 + v_accvgpr_read_b32 v66, a216 + v_accvgpr_read_b32 v65, a217 + v_accvgpr_read_b32 v64, a218 + v_accvgpr_read_b32 v63, a219 + v_accvgpr_read_b32 v62, a220 + v_accvgpr_read_b32 v61, a221 + v_accvgpr_read_b32 v60, a222 + v_accvgpr_read_b32 v19, a223 + v_accvgpr_read_b32 v225, a176 + v_accvgpr_read_b32 v224, a177 + v_accvgpr_read_b32 v223, a178 + v_accvgpr_read_b32 v222, a179 + v_accvgpr_read_b32 v221, a180 + v_accvgpr_read_b32 v220, a181 + v_accvgpr_read_b32 v219, a182 + v_accvgpr_read_b32 v218, a183 + v_accvgpr_read_b32 v217, a184 + v_accvgpr_read_b32 v216, a185 + v_accvgpr_read_b32 v215, a186 + v_accvgpr_read_b32 v214, a187 + v_accvgpr_read_b32 v213, a188 + v_accvgpr_read_b32 v212, a189 + v_accvgpr_read_b32 v211, a190 + v_accvgpr_read_b32 v210, a191 + v_accvgpr_read_b32 v177, a144 + v_accvgpr_read_b32 v176, a145 + v_accvgpr_read_b32 v175, a146 + v_accvgpr_read_b32 v174, a147 + v_accvgpr_read_b32 v173, a148 + v_accvgpr_read_b32 v172, a149 + v_accvgpr_read_b32 v171, a150 + v_accvgpr_read_b32 v170, a151 + v_accvgpr_read_b32 v169, a152 + v_accvgpr_read_b32 v168, a153 + v_accvgpr_read_b32 v167, a154 + v_accvgpr_read_b32 v166, a155 + v_accvgpr_read_b32 v165, a156 + v_accvgpr_read_b32 v164, a157 + v_accvgpr_read_b32 v163, a158 + v_accvgpr_read_b32 v162, a159 + v_accvgpr_read_b32 v161, a128 + v_accvgpr_read_b32 v160, a129 + v_accvgpr_read_b32 v159, a130 + v_accvgpr_read_b32 v158, a131 + v_accvgpr_read_b32 v157, a132 + v_accvgpr_read_b32 v156, a133 + v_accvgpr_read_b32 v155, a134 + v_accvgpr_read_b32 v154, a135 + v_accvgpr_read_b32 v153, a136 + v_accvgpr_read_b32 v152, a137 + v_accvgpr_read_b32 v151, a138 + v_accvgpr_read_b32 v150, a139 + v_accvgpr_read_b32 v149, a140 + v_accvgpr_read_b32 v148, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v147, a113 + v_accvgpr_read_b32 v129, a114 + v_accvgpr_read_b32 v128, a115 + v_accvgpr_read_b32 v127, a116 + v_accvgpr_read_b32 v126, a117 + v_accvgpr_read_b32 v125, a118 + v_accvgpr_read_b32 v124, a119 + v_accvgpr_read_b32 v123, a120 + v_accvgpr_read_b32 v122, a121 + v_accvgpr_read_b32 v121, a122 + v_accvgpr_read_b32 v120, a123 + v_accvgpr_read_b32 v119, a124 + v_accvgpr_read_b32 v118, a125 + v_accvgpr_read_b32 v117, a126 + v_accvgpr_read_b32 v116, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v59, a80 + v_accvgpr_read_b32 v58, a81 + v_accvgpr_read_b32 v57, a82 + v_accvgpr_read_b32 v56, a83 + v_accvgpr_read_b32 v55, a84 + v_accvgpr_read_b32 v54, a85 + v_accvgpr_read_b32 v53, a86 + v_accvgpr_read_b32 v52, a87 + v_accvgpr_read_b32 v51, a88 + v_accvgpr_read_b32 v50, a89 + v_accvgpr_read_b32 v25, a90 + v_accvgpr_read_b32 v24, a91 + v_accvgpr_read_b32 v23, a92 + v_accvgpr_read_b32 v22, a93 + v_accvgpr_read_b32 v21, a94 + v_accvgpr_read_b32 v20, a95 + v_accvgpr_read_b32 v115, a64 + v_accvgpr_read_b32 v114, a65 + v_accvgpr_read_b32 v113, a66 + v_accvgpr_read_b32 v112, a67 + v_accvgpr_read_b32 v111, a68 + v_accvgpr_read_b32 v110, a69 + v_accvgpr_read_b32 v109, a70 + v_accvgpr_read_b32 v108, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v209, a48 + v_accvgpr_read_b32 v208, a49 + v_accvgpr_read_b32 v207, a50 + v_accvgpr_read_b32 v206, a51 + v_accvgpr_read_b32 v205, a52 + v_accvgpr_read_b32 v204, a53 + v_accvgpr_read_b32 v203, a54 + v_accvgpr_read_b32 v202, a55 + v_accvgpr_read_b32 v201, a56 + v_accvgpr_read_b32 v200, a57 + v_accvgpr_read_b32 v199, a58 + v_accvgpr_read_b32 v198, a59 + v_accvgpr_read_b32 v197, a60 + v_accvgpr_read_b32 v196, a61 + v_accvgpr_read_b32 v195, a62 + v_accvgpr_read_b32 v194, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v193, a0 + v_accvgpr_read_b32 v192, a1 + v_accvgpr_read_b32 v191, a2 + v_accvgpr_read_b32 v190, a3 + v_accvgpr_read_b32 v189, a4 + v_accvgpr_read_b32 v188, a5 + v_accvgpr_read_b32 v187, a6 + v_accvgpr_read_b32 v186, a7 + v_accvgpr_read_b32 v185, a8 + v_accvgpr_read_b32 v184, a9 + v_accvgpr_read_b32 v183, a10 + v_accvgpr_read_b32 v182, a11 + v_accvgpr_read_b32 v181, a12 + v_accvgpr_read_b32 v180, a13 + v_accvgpr_read_b32 v179, a14 + v_accvgpr_read_b32 v178, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s5, s4 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v226 + v_lshrrev_b32_e32 v0, 3, v226 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v68, v68 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v130, v130 + v_cvt_f16_f32_e32 v132, v225 + v_cvt_f16_f32_e32 v229, v224 + v_cvt_f16_f32_e32 v230, v223 + v_cvt_f16_f32_e32 v231, v222 + v_cvt_f16_f32_e32 v232, v221 + v_cvt_f16_f32_e32 v233, v220 + v_cvt_f16_f32_e32 v234, v219 + v_cvt_f16_f32_e32 v235, v218 + v_cvt_f16_f32_e32 v236, v217 + v_cvt_f16_f32_e32 v237, v216 + v_cvt_f16_f32_e32 v238, v215 + v_cvt_f16_f32_e32 v239, v214 + v_cvt_f16_f32_e32 v240, v213 + v_cvt_f16_f32_e32 v241, v212 + v_cvt_f16_f32_e32 v242, v211 + v_cvt_f16_f32_e32 v243, v210 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v92, v92 + v_cvt_f16_f32_e32 v210, v177 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v225, v162 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v177, v76 + v_cvt_f16_f32_e32 v76, v161 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v133, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v67 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v19 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v129 + v_cvt_f16_f32_e32 v149, v128 + v_cvt_f16_f32_e32 v150, v127 + v_cvt_f16_f32_e32 v151, v126 + v_cvt_f16_f32_e32 v152, v125 + v_cvt_f16_f32_e32 v153, v124 + v_cvt_f16_f32_e32 v154, v123 + v_cvt_f16_f32_e32 v155, v122 + v_cvt_f16_f32_e32 v156, v121 + v_cvt_f16_f32_e32 v157, v120 + v_cvt_f16_f32_e32 v158, v119 + v_cvt_f16_f32_e32 v159, v118 + v_cvt_f16_f32_e32 v160, v117 + v_cvt_f16_f32_e32 v161, v116 + v_cvt_f16_f32_e32 v209, v209 + v_cvt_f16_f32_e32 v19, v208 + v_accvgpr_write_b32 a0, v19 + v_cvt_f16_f32_e32 v208, v207 + v_cvt_f16_f32_e32 v19, v206 + v_accvgpr_write_b32 a1, v19 + v_cvt_f16_f32_e32 v72, v205 + v_cvt_f16_f32_e32 v71, v204 + v_cvt_f16_f32_e32 v70, v203 + v_cvt_f16_f32_e32 v69, v202 + v_cvt_f16_f32_e32 v67, v201 + v_cvt_f16_f32_e32 v66, v200 + v_cvt_f16_f32_e32 v60, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v3, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v19, 1, v1 + v_cvt_f16_f32_e32 v1, v115 + v_cvt_f16_f32_e32 v194, v114 + v_cvt_f16_f32_e32 v195, v113 + v_cvt_f16_f32_e32 v196, v112 + v_cvt_f16_f32_e32 v197, v111 + v_cvt_f16_f32_e32 v198, v110 + v_cvt_f16_f32_e32 v199, v109 + v_cvt_f16_f32_e32 v200, v108 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v48, v44 + v_cvt_f16_f32_e32 v49, v43 + v_cvt_f16_f32_e32 v108, v42 + v_cvt_f16_f32_e32 v109, v193 + v_cvt_f16_f32_e32 v110, v192 + v_cvt_f16_f32_e32 v111, v191 + v_cvt_f16_f32_e32 v112, v190 + v_cvt_f16_f32_e32 v113, v189 + v_cvt_f16_f32_e32 v114, v188 + v_cvt_f16_f32_e32 v115, v187 + v_cvt_f16_f32_e32 v186, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v43, v58 + v_cvt_f16_f32_e32 v44, v57 + v_cvt_f16_f32_e32 v4, v56 + v_cvt_f16_f32_e32 v5, v55 + v_cvt_f16_f32_e32 v6, v54 + v_cvt_f16_f32_e32 v7, v53 + v_cvt_f16_f32_e32 v8, v52 + v_cvt_f16_f32_e32 v9, v51 + v_cvt_f16_f32_e32 v10, v50 + v_cvt_f16_f32_e32 v11, v25 + v_cvt_f16_f32_e32 v12, v24 + v_cvt_f16_f32_e32 v13, v23 + v_cvt_f16_f32_e32 v14, v22 + v_cvt_f16_f32_e32 v15, v21 + v_cvt_f16_f32_e32 v16, v20 + v_cvt_f16_f32_e32 v17, v41 + v_cvt_f16_f32_e32 v50, v40 + v_cvt_f16_f32_e32 v51, v39 + v_cvt_f16_f32_e32 v52, v38 + v_cvt_f16_f32_e32 v53, v37 + v_cvt_f16_f32_e32 v54, v36 + v_cvt_f16_f32_e32 v55, v35 + v_cvt_f16_f32_e32 v56, v34 + v_cvt_f16_f32_e32 v57, v33 + v_cvt_f16_f32_e32 v58, v32 + v_cvt_f16_f32_e32 v59, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v226 + v_lshrrev_b32_e32 v20, 1, v226 + s_cbranch_scc1 .LBB5_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB5_14 +.LBB5_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSD_11ColumnMajorESE_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SE_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB5_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v23, s5, v0 + v_lshl_add_u32 v23, v23, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v68 offset:1152 + ds_write_b16 v23, v18 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v130 offset:3456 + ds_write_b16 v23, v132 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 60, v20 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v187, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v187, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v187, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v187, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v187, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v92 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v187, v31, v41 + v_lshlrev_b32_e32 v192, 1, v187 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v187 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v177 offset:3456 + ds_write_b16 v23, v76 offset:8192 + ds_write_b16 v23, v77 offset:8320 + ds_write_b16 v23, v78 offset:8448 + ds_write_b16 v23, v79 offset:8576 + ds_write_b16 v23, v80 offset:9216 + ds_write_b16 v23, v81 offset:9344 + ds_write_b16 v23, v82 offset:9472 + ds_write_b16 v23, v83 offset:9600 + ds_write_b16 v23, v84 offset:10240 + ds_write_b16 v23, v85 offset:10368 + ds_write_b16 v23, v86 offset:10496 + ds_write_b16 v23, v87 offset:10624 + ds_write_b16 v23, v88 offset:11264 + ds_write_b16 v23, v89 offset:11392 + ds_write_b16 v23, v90 offset:11520 + ds_write_b16 v23, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v187, 0x80, v25 + v_add_u32_e32 v192, v31, v187 + v_lshlrev_b32_e32 v193, 1, v192 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v193, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v193, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v193, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v193, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v192 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v133 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v192, 0xc0, v25 + v_add_u32_e32 v31, v31, v192 + v_lshlrev_b32_e32 v193, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v193, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v193, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v193, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v193, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v209 + ds_write_b16 v23, a0 offset:128 + ds_write_b16 v23, v208 offset:256 + ds_write_b16 v23, a1 offset:384 + ds_write_b16 v23, v72 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v67 offset:2048 + ds_write_b16 v23, v66 offset:2176 + ds_write_b16 v23, v60 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v3 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v192 + v_lshlrev_b32_e32 v192, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v1 + ds_write_b16 v23, v194 offset:128 + ds_write_b16 v23, v195 offset:256 + ds_write_b16 v23, v196 offset:384 + ds_write_b16 v23, v197 offset:1024 + ds_write_b16 v23, v198 offset:1152 + ds_write_b16 v23, v199 offset:1280 + ds_write_b16 v23, v200 offset:1408 + ds_write_b16 v23, v201 offset:2048 + ds_write_b16 v23, v202 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v48 offset:3200 + ds_write_b16 v23, v49 offset:3328 + ds_write_b16 v23, v108 offset:3456 + ds_write_b16 v23, v109 offset:8192 + ds_write_b16 v23, v110 offset:8320 + ds_write_b16 v23, v111 offset:8448 + ds_write_b16 v23, v112 offset:8576 + ds_write_b16 v23, v113 offset:9216 + ds_write_b16 v23, v114 offset:9344 + ds_write_b16 v23, v115 offset:9472 + ds_write_b16 v23, v186 offset:9600 + ds_write_b16 v23, v185 offset:10240 + ds_write_b16 v23, v184 offset:10368 + ds_write_b16 v23, v183 offset:10496 + ds_write_b16 v23, v182 offset:10624 + ds_write_b16 v23, v181 offset:11264 + ds_write_b16 v23, v180 offset:11392 + ds_write_b16 v23, v179 offset:11520 + ds_write_b16 v23, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v187 + v_lshlrev_b32_e32 v187, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v187, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v187, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v187, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v187, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v43 offset:128 + ds_write_b16 v23, v44 offset:256 + ds_write_b16 v23, v4 offset:384 + ds_write_b16 v23, v5 offset:1024 + ds_write_b16 v23, v6 offset:1152 + ds_write_b16 v23, v7 offset:1280 + ds_write_b16 v23, v8 offset:1408 + ds_write_b16 v23, v9 offset:2048 + ds_write_b16 v23, v10 offset:2176 + ds_write_b16 v23, v11 offset:2304 + ds_write_b16 v23, v12 offset:2432 + ds_write_b16 v23, v13 offset:3072 + ds_write_b16 v23, v14 offset:3200 + ds_write_b16 v23, v15 offset:3328 + ds_write_b16 v23, v16 offset:3456 + ds_write_b16 v23, v17 offset:8192 + ds_write_b16 v23, v50 offset:8320 + ds_write_b16 v23, v51 offset:8448 + ds_write_b16 v23, v52 offset:8576 + ds_write_b16 v23, v53 offset:9216 + ds_write_b16 v23, v54 offset:9344 + ds_write_b16 v23, v55 offset:9472 + ds_write_b16 v23, v56 offset:9600 + ds_write_b16 v23, v57 offset:10240 + ds_write_b16 v23, v58 offset:10368 + ds_write_b16 v23, v59 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB5_12 +.LBB5_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_add_u32 v0, v0, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v0, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v68 offset:1152 + ds_write_b16 v31, v18 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v130 offset:3456 + ds_write_b16 v31, v132 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v18, 60, v20 + v_add_u32_e32 v40, s2, v18 + v_lshlrev_b32_e32 v18, 7, v40 + v_lshl_or_b32 v41, v0, 1, v18 + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v40, s18, v40 + v_or_b32_e32 v68, s19, v0 + v_mul_lo_u32 v0, v40, s16 + v_add_u32_e32 v131, v0, v68 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v187, 1, v131 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v187, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v131 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v107 + ds_write_b16 v31, v106 offset:128 + ds_write_b16 v31, v105 offset:256 + ds_write_b16 v31, v104 offset:384 + ds_write_b16 v31, v103 offset:1024 + ds_write_b16 v31, v102 offset:1152 + ds_write_b16 v31, v101 offset:1280 + ds_write_b16 v31, v100 offset:1408 + ds_write_b16 v31, v99 offset:2048 + ds_write_b16 v31, v98 offset:2176 + ds_write_b16 v31, v97 offset:2304 + ds_write_b16 v31, v96 offset:2432 + ds_write_b16 v31, v95 offset:3072 + ds_write_b16 v31, v94 offset:3200 + ds_write_b16 v31, v93 offset:3328 + ds_write_b16 v31, v92 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v92, 64, v68 + v_add_u32_e32 v93, v0, v92 + v_lshlrev_b32_e32 v94, 1, v93 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v94, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v93 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v177 offset:3456 + ds_write_b16 v31, v76 offset:8192 + ds_write_b16 v31, v77 offset:8320 + ds_write_b16 v31, v78 offset:8448 + ds_write_b16 v31, v79 offset:8576 + ds_write_b16 v31, v80 offset:9216 + ds_write_b16 v31, v81 offset:9344 + ds_write_b16 v31, v82 offset:9472 + ds_write_b16 v31, v83 offset:9600 + ds_write_b16 v31, v84 offset:10240 + ds_write_b16 v31, v85 offset:10368 + ds_write_b16 v31, v86 offset:10496 + ds_write_b16 v31, v87 offset:10624 + ds_write_b16 v31, v88 offset:11264 + ds_write_b16 v31, v89 offset:11392 + ds_write_b16 v31, v90 offset:11520 + ds_write_b16 v31, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v76, 0x80, v68 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v75 + ds_write_b16 v31, v74 offset:128 + ds_write_b16 v31, v73 offset:256 + ds_write_b16 v31, v133 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v74, 0xc0, v68 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v77, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v209 + ds_write_b16 v31, a0 offset:128 + ds_write_b16 v31, v208 offset:256 + ds_write_b16 v31, a1 offset:384 + ds_write_b16 v31, v72 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v67 offset:2048 + ds_write_b16 v31, v66 offset:2176 + ds_write_b16 v31, v60 offset:2304 + ds_write_b16 v31, v61 offset:2432 + ds_write_b16 v31, v62 offset:3072 + ds_write_b16 v31, v63 offset:3200 + ds_write_b16 v31, v64 offset:3328 + ds_write_b16 v31, v65 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v3 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v0, 0x80, v40 + v_mul_lo_u32 v40, v0, s16 + v_add_u32_e32 v0, v40, v74 + v_lshlrev_b32_e32 v2, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v2, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v2, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v2, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v2, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v2, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v1 + ds_write_b16 v31, v194 offset:128 + ds_write_b16 v31, v195 offset:256 + ds_write_b16 v31, v196 offset:384 + ds_write_b16 v31, v197 offset:1024 + ds_write_b16 v31, v198 offset:1152 + ds_write_b16 v31, v199 offset:1280 + ds_write_b16 v31, v200 offset:1408 + ds_write_b16 v31, v201 offset:2048 + ds_write_b16 v31, v202 offset:2176 + ds_write_b16 v31, v47 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v48 offset:3200 + ds_write_b16 v31, v49 offset:3328 + ds_write_b16 v31, v108 offset:3456 + ds_write_b16 v31, v109 offset:8192 + ds_write_b16 v31, v110 offset:8320 + ds_write_b16 v31, v111 offset:8448 + ds_write_b16 v31, v112 offset:8576 + ds_write_b16 v31, v113 offset:9216 + ds_write_b16 v31, v114 offset:9344 + ds_write_b16 v31, v115 offset:9472 + ds_write_b16 v31, v186 offset:9600 + ds_write_b16 v31, v185 offset:10240 + ds_write_b16 v31, v184 offset:10368 + ds_write_b16 v31, v183 offset:10496 + ds_write_b16 v31, v182 offset:10624 + ds_write_b16 v31, v181 offset:11264 + ds_write_b16 v31, v180 offset:11392 + ds_write_b16 v31, v179 offset:11520 + ds_write_b16 v31, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[18:21], v41 offset:128 + ds_read_b128 v[22:25], v41 offset:256 + ds_read_b128 v[32:35], v41 offset:384 + v_add_u32_e32 v36, v40, v76 + v_lshlrev_b32_e32 v37, 1, v36 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v37, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v36 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v43 offset:128 + ds_write_b16 v31, v44 offset:256 + ds_write_b16 v31, v4 offset:384 + ds_write_b16 v31, v5 offset:1024 + ds_write_b16 v31, v6 offset:1152 + ds_write_b16 v31, v7 offset:1280 + ds_write_b16 v31, v8 offset:1408 + ds_write_b16 v31, v9 offset:2048 + ds_write_b16 v31, v10 offset:2176 + ds_write_b16 v31, v11 offset:2304 + ds_write_b16 v31, v12 offset:2432 + ds_write_b16 v31, v13 offset:3072 + ds_write_b16 v31, v14 offset:3200 + ds_write_b16 v31, v15 offset:3328 + ds_write_b16 v31, v16 offset:3456 + ds_write_b16 v31, v17 offset:8192 + ds_write_b16 v31, v50 offset:8320 + ds_write_b16 v31, v51 offset:8448 + ds_write_b16 v31, v52 offset:8576 + ds_write_b16 v31, v53 offset:9216 + ds_write_b16 v31, v54 offset:9344 + ds_write_b16 v31, v55 offset:9472 + ds_write_b16 v31, v56 offset:9600 + ds_write_b16 v31, v57 offset:10240 + ds_write_b16 v31, v58 offset:10368 + ds_write_b16 v31, v59 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v40, v92 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v40, v68 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text.c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942,"axG",@progbits,c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942,comdat +.Lfunc_end5: + .size c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942, .Lfunc_end5-c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942 + ; -- End function + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.num_vgpr, 256 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.num_agpr, 256 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.numbered_sgpr, 28 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.num_named_barrier, 0 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.private_seg_size, 0 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.uses_vcc, 1 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.uses_flat_scratch, 0 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.has_dyn_sized_stack, 0 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.has_recursion, 0 + .set c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 25624 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB6_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB6_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v4, s8 + v_mov_b32_e32 v5, s9 + v_mov_b32_e32 v2, s10 + v_mov_b32_e32 v3, s11 + v_mul_lo_u32 v8, v6, s7 + v_mul_lo_u32 v10, v0, s2 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshl_add_u64 v[2:3], v[10:11], 1, v[2:3] + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[4:5], v[8:9], 1, v[4:5] + v_mov_b32_e32 v1, 0 +.LBB6_3: ; =>This Inner Loop Header: Depth=1 + global_load_ushort v7, v[4:5], off + global_load_ushort v8, v[2:3], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_lshl_add_u64 v[4:5], v[4:5], 0, 2 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v1, v7, v8, v1 op_sel_hi:[1,1,0] + s_cbranch_scc0 .LBB6_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB6_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB6_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 12 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end6: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end6-_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 12 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 448 +; TotalNumSgprs: 20 +; NumVgprs: 12 +; NumAgprs: 0 +; TotalNumVgprs: 12 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 12 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s2, s12, s2 + s_mul_i32 s12, s2, s20 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[2:3], s[12:13], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s22, s2, 1 + s_mul_i32 s2, s20, s3 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s23, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v226, -1, v0 + v_and_b32_e32 v72, 0x78, v226 + v_and_b32_e32 v73, 31, v226 + v_lshrrev_b32_e32 v2, 5, v226 + v_and_b32_e32 v67, 7, v226 + v_lshrrev_b32_e32 v3, 2, v226 + s_cbranch_scc0 .LBB7_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_lshlrev_b32_e32 v18, 3, v67 + s_and_b32 s10, s15, 0xffffffc0 + v_add_u32_e32 v5, s10, v72 + v_add_u32_e32 v0, s18, v5 + v_mad_u64_u32 v[0:1], s[10:11], v0, s7, v[18:19] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v1, 1, v0 + s_nop 1 + buffer_load_dwordx4 v[6:9], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v0 + v_lshlrev_b32_e32 v0, 1, v1 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + v_xor_b32_e32 v4, v2, v67 + v_lshlrev_b32_e32 v66, 3, v2 + v_lshl_or_b32 v20, v73, 3, s19 + v_lshlrev_b32_e32 v0, 12, v2 + s_lshl_b32 s14, s21, 1 + s_lshr_b32 s24, s15, 2 + s_lshr_b32 s25, s15, 1 + v_lshl_or_b32 v74, v67, 8, v0 + s_mov_b32 s15, s11 + s_and_b32 s26, s24, 0x1ffffe0 + s_and_b32 s24, s24, 0x3ffffff0 + v_and_or_b32 v0, s25, 32, v73 + v_or_b32_e32 v75, s26, v73 + v_add_u32_e32 v19, s24, v66 + v_lshrrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v1, s7, v1 + v_lshlrev_b32_e32 v14, 1, v1 + buffer_load_dwordx4 v[14:17], v14, s[8:11], 0 offen + v_lshl_or_b32 v76, v5, 6, v18 + v_or_b32_e32 v77, 1, v5 + v_ashrrev_i32_e32 v21, 31, v5 + v_or_b32_e32 v78, 2, v5 + v_mad_u64_u32 v[18:19], s[26:27], v19, s20, v[20:21] + v_xor_b32_e32 v79, v0, v67 + v_lshlrev_b32_e32 v80, 1, v76 + v_lshrrev_b32_e32 v81, 29, v21 + v_lshlrev_b32_e32 v26, 1, v18 + v_add_u32_e32 v18, s20, v18 + v_lshlrev_b32_e32 v27, 1, v18 + v_add_u32_e32 v30, s20, v18 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[18:21], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[22:25], v27, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v1 + buffer_load_dwordx4 v[26:29], v26, s[8:11], 0 offen + v_lshlrev_b32_e32 v38, 1, v30 + v_add_u32_e32 v30, s20, v30 + v_add_u32_e32 v1, s7, v1 + v_lshlrev_b32_e32 v39, 1, v30 + v_add_u32_e32 v54, s20, v30 + v_lshlrev_b32_e32 v40, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[30:33], v38, s[12:15], 0 offen + buffer_load_dwordx4 v[34:37], v39, s[12:15], 0 offen + v_lshlrev_b32_e32 v62, 1, v54 + buffer_load_dwordx4 v[38:41], v40, s[8:11], 0 offen + v_lshlrev_b32_e32 v42, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[42:45], v42, s[8:11], 0 offen + v_lshlrev_b32_e32 v55, 1, v1 + v_add_lshl_u32 v1, v1, s7, 1 + buffer_load_dwordx4 v[46:49], v55, s[8:11], 0 offen + buffer_load_dwordx4 v[50:53], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s20, v54 + v_lshlrev_b32_e32 v63, 1, v1 + v_add_u32_e32 v1, s20, v1 + buffer_load_dwordx4 v[54:57], v62, s[12:15], 0 offen + buffer_load_dwordx4 v[58:61], v63, s[12:15], 0 offen + v_lshlrev_b32_e32 v82, 1, v1 + v_add_lshl_u32 v1, v1, s20, 1 + buffer_load_dwordx4 v[62:65], v82, s[12:15], 0 offen + buffer_load_dwordx4 v[68:71], v1, s[12:15], 0 offen + v_lshl_or_b32 v1, v79, 3, v74 + v_add_u32_e32 v74, v77, v81 + v_add_u32_e32 v82, v78, v81 + v_and_b32_e32 v74, -8, v74 + v_and_b32_e32 v82, -8, v82 + v_sub_u32_e32 v74, v77, v74 + v_xor_b32_e32 v74, v74, v67 + v_sub_u32_e32 v77, v74, v67 + v_lshlrev_b32_e32 v83, 3, v77 + s_waitcnt vmcnt(15) + ds_write_b128 v80, v[6:9] + v_sub_u32_e32 v6, v78, v82 + v_xor_b32_e32 v6, v6, v67 + v_sub_u32_e32 v7, v6, v74 + v_lshlrev_b32_e32 v8, 3, v7 + v_add3_u32 v8, v83, v76, v8 + v_lshl_add_u32 v9, v77, 4, v80 + s_waitcnt vmcnt(14) + ds_write_b128 v9, v[10:13] offset:128 + v_or_b32_e32 v10, 3, v5 + v_add_u32_e32 v11, v10, v81 + v_and_b32_e32 v11, -8, v11 + v_sub_u32_e32 v10, v10, v11 + v_xor_b32_e32 v10, v10, v67 + v_sub_u32_e32 v6, v10, v6 + v_lshlrev_b32_e32 v11, 3, v6 + v_or_b32_e32 v12, 4, v5 + v_add_u32_e32 v13, v12, v81 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v67 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v13, 3, v10 + v_add3_u32 v8, v8, v11, v13 + v_lshlrev_b32_e32 v7, 4, v7 + v_add3_u32 v7, v9, s23, v7 + s_waitcnt vmcnt(13) + ds_write_b128 v7, v[14:17] offset:128 + v_or_b32_e32 v9, 5, v5 + v_add_u32_e32 v11, v9, v81 + v_and_b32_e32 v11, -8, v11 + v_sub_u32_e32 v9, v9, v11 + v_xor_b32_e32 v9, v9, v67 + v_sub_u32_e32 v11, v9, v12 + v_lshlrev_b32_e32 v12, 3, v11 + v_or_b32_e32 v13, 6, v5 + v_add_u32_e32 v14, v13, v81 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v13, v13, v14 + v_xor_b32_e32 v13, v13, v67 + v_sub_u32_e32 v9, v13, v9 + v_lshlrev_b32_e32 v14, 3, v9 + v_add3_u32 v8, v8, v12, v14 + v_lshlrev_b32_e32 v6, 4, v6 + v_add3_u32 v6, v7, s23, v6 + s_waitcnt vmcnt(10) + ds_write_b128 v6, v[26:29] offset:128 + v_or_b32_e32 v5, 7, v5 + v_add_u32_e32 v7, v5, v81 + v_and_b32_e32 v7, 0xffffff8, v7 + v_sub_u32_e32 v5, v5, v7 + v_xor_b32_e32 v5, v5, v67 + v_sub_u32_e32 v5, v5, v13 + v_lshlrev_b32_e32 v5, 4, v5 + v_lshl_add_u32 v5, v8, 1, v5 + v_lshlrev_b32_e32 v7, 4, v10 + v_add3_u32 v6, v6, s23, v7 + s_waitcnt vmcnt(7) + ds_write_b128 v6, v[38:41] offset:128 + v_lshlrev_b32_e32 v7, 4, v11 + v_add3_u32 v6, v6, s23, v7 + s_waitcnt vmcnt(6) + ds_write_b128 v6, v[42:45] offset:128 + v_lshlrev_b32_e32 v7, 4, v9 + v_add3_u32 v6, v6, s23, v7 + s_waitcnt vmcnt(5) + ds_write_b128 v6, v[46:49] offset:128 + s_waitcnt vmcnt(4) + ds_write_b128 v5, v[50:53] offset:896 + s_mov_b32 s10, 0x1000504 + v_perm_b32 v6, v18, v22, s10 + s_mov_b32 s11, 0x3020706 + v_perm_b32 v10, v18, v22, s11 + v_perm_b32 v7, v30, v34, s10 + v_perm_b32 v11, v30, v34, s11 + s_waitcnt vmcnt(2) + v_perm_b32 v8, v54, v58, s10 + v_perm_b32 v12, v54, v58, s11 + s_waitcnt vmcnt(0) + v_perm_b32 v9, v62, v68, s10 + v_perm_b32 v13, v62, v68, s11 + v_perm_b32 v14, v19, v23, s10 + v_perm_b32 v26, v19, v23, s11 + v_perm_b32 v15, v31, v35, s10 + v_perm_b32 v27, v31, v35, s11 + v_perm_b32 v16, v55, v59, s10 + v_perm_b32 v28, v55, v59, s11 + v_perm_b32 v17, v63, v69, s10 + v_perm_b32 v29, v63, v69, s11 + v_perm_b32 v38, v20, v24, s10 + v_perm_b32 v42, v20, v24, s11 + v_perm_b32 v39, v32, v36, s10 + v_perm_b32 v43, v32, v36, s11 + v_perm_b32 v40, v56, v60, s10 + v_perm_b32 v44, v56, v60, s11 + v_perm_b32 v41, v64, v70, s10 + v_perm_b32 v45, v64, v70, s11 + v_perm_b32 v18, v21, v25, s10 + v_perm_b32 v22, v21, v25, s11 + v_perm_b32 v19, v33, v37, s10 + v_perm_b32 v23, v33, v37, s11 + v_perm_b32 v20, v57, v61, s10 + v_perm_b32 v24, v57, v61, s11 + v_perm_b32 v21, v65, v71, s10 + v_perm_b32 v25, v65, v71, s11 + v_and_b32_e32 v5, 24, v3 + v_add_u32_e32 v5, s24, v5 + v_lshrrev_b32_e32 v30, 2, v5 + v_and_b32_e32 v30, 24, v30 + v_xor_b32_e32 v31, v30, v73 + v_lshlrev_b32_e32 v32, 9, v5 + v_and_b32_e32 v32, 0x3000, v32 + v_lshlrev_b32_e32 v5, 6, v5 + v_and_b32_e32 v5, 0xfffff800, v5 + v_add_u32_e32 v5, v5, v32 + v_lshl_or_b32 v5, v31, 3, v5 + v_lshlrev_b32_e32 v32, 1, v5 + ds_write_b128 v32, v[6:9] offset:32768 + v_or_b32_e32 v6, 1, v30 + v_xor_b32_e32 v6, v6, v73 + v_sub_u32_e32 v7, v6, v31 + v_lshl_add_u32 v5, v7, 3, v5 + v_lshl_add_u32 v7, v7, 4, v32 + ds_write_b128 v7, v[10:13] offset:33280 + v_or_b32_e32 v7, 2, v30 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v6, v7, v6 + v_lshlrev_b32_e32 v6, 3, v6 + s_movk_i32 s10, 0x100 + v_add3_u32 v5, v5, v6, s10 + v_lshlrev_b32_e32 v6, 1, v5 + ds_write_b128 v6, v[14:17] offset:33280 + v_or_b32_e32 v6, 3, v30 + v_xor_b32_e32 v6, v6, v73 + v_sub_u32_e32 v7, v6, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v5, v5, v7, s10 + v_lshlrev_b32_e32 v7, 1, v5 + ds_write_b128 v7, v[26:29] offset:33280 + v_or_b32_e32 v7, 4, v30 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v6, v7, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v5, v5, v6, s10 + v_lshlrev_b32_e32 v6, 1, v5 + ds_write_b128 v6, v[38:41] offset:33280 + v_or_b32_e32 v6, 5, v30 + v_xor_b32_e32 v6, v6, v73 + v_sub_u32_e32 v7, v6, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v5, v5, v7, s10 + v_lshlrev_b32_e32 v7, 1, v5 + ds_write_b128 v7, v[42:45] offset:33280 + v_or_b32_e32 v7, 6, v30 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v6, v7, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_lshl_u32 v5, v5, v6, 1 + v_or_b32_e32 v6, 7, v30 + v_xor_b32_e32 v6, v6, v73 + v_sub_u32_e32 v6, v6, v7 + v_lshl_add_u32 v6, v6, 4, v5 + ds_write_b128 v5, v[18:21] offset:33792 + ds_write_b128 v6, v[22:25] offset:34304 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v5, 7, v75 + v_lshl_or_b32 v6, v4, 4, v5 + v_add_u32_e32 v7, 2, v2 + v_xor_b32_e32 v7, v7, v67 + v_lshl_or_b32 v8, v7, 4, v5 + ds_read_b128 v[34:37], v6 + ds_read_b128 v[38:41], v8 + v_lshlrev_b32_e32 v6, 1, v1 + v_add_u32_e32 v8, 16, v66 + v_lshrrev_b32_e32 v9, 5, v8 + v_bfe_u32 v8, v8, 3, 2 + v_lshl_or_b32 v10, v9, 3, v67 + v_and_b32_e32 v11, 31, v10 + v_xor_b32_e32 v12, v0, v11 + v_sub_u32_e32 v13, v12, v79 + v_lshlrev_b32_e32 v14, 11, v9 + v_lshlrev_b32_e32 v13, 3, v13 + v_sub_u32_e32 v15, v8, v2 + v_lshl_or_b32 v14, v15, 12, v14 + v_add3_u32 v1, v1, v14, v13 + v_lshlrev_b32_e32 v13, 1, v1 + ds_read_b128 v[42:45], v6 offset:32768 + ds_read_b128 v[46:49], v13 offset:32768 + v_xor_b32_e32 v6, 1, v9 + v_sub_u32_e32 v8, v2, v8 + v_lshl_add_u32 v9, v6, 3, v10 + v_and_b32_e32 v10, 31, v9 + v_xor_b32_e32 v15, v0, v10 + v_sub_u32_e32 v12, v15, v12 + v_lshlrev_b32_e32 v6, 11, v6 + v_lshl_add_u32 v6, v8, 12, v6 + v_lshl_add_u32 v8, v12, 3, v6 + v_lshl_add_u32 v12, v8, 1, v13 + v_add_u32_e32 v13, 48, v66 + v_lshrrev_b32_e32 v16, 5, v13 + v_add_u32_e32 v17, -1, v16 + v_bfe_u32 v13, v13, 3, 2 + v_sub_u32_e32 v18, v13, v2 + v_lshl_add_u32 v9, v17, 3, v9 + v_ashrrev_i32_e32 v19, 31, v9 + v_lshrrev_b32_e32 v19, 27, v19 + v_add_u32_e32 v19, v9, v19 + v_and_b32_e32 v19, 0xffffffe0, v19 + v_sub_u32_e32 v19, v9, v19 + v_xor_b32_e32 v20, v0, v19 + v_sub_u32_e32 v15, v20, v15 + v_lshlrev_b32_e32 v17, 11, v17 + v_lshl_add_u32 v17, v18, 12, v17 + v_lshl_add_u32 v15, v15, 3, v17 + v_lshl_add_u32 v18, v15, 1, v12 + v_or_b32_e32 v21, 8, v0 + v_sub_u32_e32 v13, v2, v13 + v_lshlrev_b32_e32 v22, 3, v16 + v_sub_u32_e32 v9, v9, v22 + v_ashrrev_i32_e32 v22, 31, v9 + v_lshrrev_b32_e32 v22, 27, v22 + v_add_u32_e32 v22, v9, v22 + v_and_b32_e32 v22, 0xffffffe0, v22 + v_sub_u32_e32 v9, v9, v22 + v_xor_b32_e32 v22, v21, v9 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v13, 12, v13 + v_lshlrev_b32_e32 v16, 11, v16 + v_sub_u32_e32 v13, v13, v16 + v_lshl_add_u32 v16, v20, 3, v13 + v_lshl_add_u32 v20, v16, 1, v18 + v_xor_b32_e32 v23, v21, v11 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[34:35], v[42:43], 0 + v_sub_u32_e32 v22, v23, v22 + v_lshl_add_u32 v22, v22, 3, v14 + v_lshl_add_u32 v24, v22, 1, v20 + ds_read_b128 v[50:53], v20 offset:32768 + ds_read_b128 v[54:57], v24 offset:32768 + v_xor_b32_e32 v20, v21, v10 + v_sub_u32_e32 v23, v20, v23 + v_mfma_f32_32x32x8_f16 a[96:111], v[36:37], v[44:45], a[96:111] + v_lshl_add_u32 v23, v23, 3, v6 + v_lshl_add_u32 v24, v23, 1, v24 + v_xor_b32_e32 v21, v21, v19 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v20, v20, 3, v17 + v_lshl_add_u32 v25, v20, 1, v24 + v_or_b32_e32 v26, 16, v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[144:159], v[34:35], v[50:51], 0 + v_xor_b32_e32 v27, v26, v9 + v_sub_u32_e32 v21, v27, v21 + v_lshl_add_u32 v21, v21, 3, v13 + v_lshl_add_u32 v28, v21, 1, v25 + v_xor_b32_e32 v29, v26, v11 + v_sub_u32_e32 v27, v29, v27 + v_lshl_add_u32 v27, v27, 3, v14 + v_mfma_f32_32x32x8_f16 a[144:159], v[36:37], v[52:53], a[144:159] + v_lshl_add_u32 v30, v27, 1, v28 + ds_read_b128 v[58:61], v28 offset:32768 + ds_read_b128 v[62:65], v30 offset:32768 + v_xor_b32_e32 v28, v26, v10 + v_sub_u32_e32 v29, v28, v29 + v_lshl_add_u32 v29, v29, 3, v6 + v_lshl_add_u32 v30, v29, 1, v30 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[34:35], v[58:59], 0 + v_xor_b32_e32 v26, v26, v19 + v_sub_u32_e32 v28, v26, v28 + v_lshl_add_u32 v28, v28, 3, v17 + v_lshl_add_u32 v31, v28, 1, v30 + v_or_b32_e32 v0, 24, v0 + v_xor_b32_e32 v9, v0, v9 + v_sub_u32_e32 v26, v9, v26 + v_mfma_f32_32x32x8_f16 a[176:191], v[36:37], v[60:61], a[176:191] + v_lshl_add_u32 v13, v26, 3, v13 + v_lshl_add_u32 v26, v13, 1, v31 + ds_read_b128 v[68:71], v26 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[34:35], v[68:69], 0 + v_add_u32_e32 v32, 6, v2 + v_xor_b32_e32 v32, v32, v67 + v_lshl_add_u32 v33, v32, 4, v5 + v_sub_u32_e32 v34, v4, v32 + v_lshl_add_u32 v34, v34, 4, v33 + v_mfma_f32_32x32x8_f16 a[208:223], v[36:37], v[70:71], a[208:223] + ds_read_b128 v[74:77], v34 offset:8192 + ds_read_b128 v[78:81], v34 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[74:75], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[76:77], v[44:45], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[74:75], v[50:51], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[76:77], v[52:53], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[74:75], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[76:77], v[60:61], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[74:75], v[68:69], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[76:77], v[70:71], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[78:79], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[80:81], v[44:45], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[78:79], v[50:51], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[80:81], v[52:53], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[78:79], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[64:79], v[80:81], v[60:61], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[78:79], v[68:69], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[80:81], v[70:71], a[48:63] + ds_read_b128 v[74:77], v34 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[74:75], v[42:43], 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[76:77], v[44:45], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[74:75], v[50:51], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[76:77], v[52:53], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[74:75], v[58:59], 0 + v_mfma_f32_32x32x8_f16 a[0:15], v[76:77], v[60:61], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[74:75], v[68:69], 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[76:77], v[70:71], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[38:39], v[46:47], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[40:41], v[48:49], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[38:39], v[54:55], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[40:41], v[56:57], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[38:39], v[62:63], a[176:191] + v_xor_b32_e32 v11, v0, v11 + v_sub_u32_e32 v9, v11, v9 + v_mfma_f32_32x32x8_f16 a[176:191], v[40:41], v[64:65], a[176:191] + v_lshl_add_u32 v9, v9, 3, v14 + v_lshl_add_u32 v14, v9, 1, v26 + ds_read_b128 v[42:45], v14 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[38:39], v[42:43], a[208:223] + v_sub_u32_e32 v7, v7, v4 + v_lshl_add_u32 v7, v7, 4, v34 + v_mfma_f32_32x32x8_f16 a[208:223], v[40:41], v[44:45], a[208:223] + ds_read_b128 v[36:39], v7 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[36:37], v[46:47], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[38:39], v[48:49], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[36:37], v[54:55], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[38:39], v[56:57], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[36:37], v[62:63], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[38:39], v[64:65], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[36:37], v[42:43], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[38:39], v[44:45], a[128:143] + ds_read_b128 v[36:39], v7 offset:16384 + ds_read_b128 v[50:53], v7 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[36:37], v[46:47], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[38:39], v[48:49], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[36:37], v[54:55], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[38:39], v[56:57], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[36:37], v[62:63], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[38:39], v[64:65], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[36:37], v[42:43], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[38:39], v[44:45], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[50:51], v[46:47], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[52:53], v[48:49], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[50:51], v[54:55], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[52:53], v[56:57], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[50:51], v[62:63], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[52:53], v[64:65], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[50:51], v[42:43], a[240:255] + v_or_b32_e32 v7, 4, v2 + v_xor_b32_e32 v7, v7, v67 + v_lshl_or_b32 v5, v7, 4, v5 + v_mfma_f32_32x32x8_f16 a[240:255], v[52:53], v[44:45], a[240:255] + ds_read_b128 v[36:39], v5 + ds_read_b128 v[40:43], v12 offset:32768 + ds_read_b128 v[44:47], v33 + ds_read_b128 v[48:51], v18 offset:32768 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x8_f16 a[96:111], v[36:37], v[40:41], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[38:39], v[42:43], a[96:111] + ds_read_b128 v[52:55], v24 offset:32768 + ds_read_b128 v[56:59], v25 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[144:159], v[36:37], v[52:53], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[38:39], v[54:55], a[144:159] + ds_read_b128 v[60:63], v30 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[36:37], v[60:61], a[176:191] + v_xor_b32_e32 v5, v0, v10 + v_sub_u32_e32 v10, v5, v11 + v_mfma_f32_32x32x8_f16 a[176:191], v[38:39], v[62:63], a[176:191] + v_lshl_add_u32 v6, v10, 3, v6 + v_lshl_add_u32 v10, v6, 1, v14 + ds_read_b128 v[68:71], v10 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[36:37], v[68:69], a[208:223] + v_sub_u32_e32 v7, v7, v4 + v_lshl_add_u32 v7, v7, 4, v34 + v_mfma_f32_32x32x8_f16 a[208:223], v[38:39], v[70:71], a[208:223] + ds_read_b128 v[36:39], v7 offset:8192 + ds_read_b128 v[74:77], v7 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[36:37], v[40:41], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[38:39], v[42:43], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[36:37], v[52:53], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[38:39], v[54:55], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[36:37], v[60:61], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[38:39], v[62:63], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[36:37], v[68:69], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[38:39], v[70:71], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[74:75], v[40:41], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[76:77], v[42:43], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[74:75], v[52:53], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[76:77], v[54:55], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[74:75], v[60:61], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[76:77], v[62:63], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[74:75], v[68:69], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[76:77], v[70:71], a[48:63] + ds_read_b128 v[36:39], v7 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[36:37], v[40:41], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[38:39], v[42:43], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[36:37], v[52:53], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[38:39], v[54:55], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[36:37], v[60:61], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[38:39], v[62:63], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[36:37], v[68:69], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[38:39], v[70:71], a[240:255] + v_mfma_f32_32x32x8_f16 a[96:111], v[44:45], v[48:49], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[46:47], v[50:51], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[44:45], v[56:57], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[46:47], v[58:59], a[144:159] + ds_read_b128 v[36:39], v31 offset:32768 + v_add3_u32 v1, v8, v1, v15 + v_add3_u32 v1, v16, v1, v22 + v_add3_u32 v1, v23, v1, v20 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[176:191], v[44:45], v[36:37], a[176:191] + v_add3_u32 v1, v21, v1, v27 + v_add3_u32 v1, v29, v1, v28 + v_add3_u32 v1, v13, v1, v9 + v_xor_b32_e32 v0, v0, v19 + v_sub_u32_e32 v0, v0, v5 + v_lshlrev_b32_e32 v0, 4, v0 + v_lshlrev_b32_e32 v5, 1, v17 + v_mfma_f32_32x32x8_f16 a[176:191], v[46:47], v[38:39], a[176:191] + v_add_lshl_u32 v1, v6, v1, 1 + v_add3_u32 v0, v0, v5, v1 + ds_read_b128 v[6:9], v0 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[208:223], v[44:45], v[6:7], a[208:223] + v_sub_u32_e32 v0, v32, v4 + v_lshl_add_u32 v0, v0, 4, v34 + v_mfma_f32_32x32x8_f16 a[208:223], v[46:47], v[8:9], a[208:223] + ds_read_b128 v[10:13], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[10:11], v[48:49], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[12:13], v[50:51], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[10:11], v[56:57], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[12:13], v[58:59], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[10:11], v[36:37], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[12:13], v[38:39], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[10:11], v[6:7], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[12:13], v[8:9], a[128:143] + ds_read_b128 v[10:13], v0 offset:16384 + ds_read_b128 v[14:17], v0 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[10:11], v[48:49], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[12:13], v[50:51], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[10:11], v[56:57], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[12:13], v[58:59], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[10:11], v[36:37], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[12:13], v[38:39], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[10:11], v[6:7], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[12:13], v[8:9], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[14:15], v[48:49], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[16:17], v[50:51], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[14:15], v[56:57], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[16:17], v[58:59], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[14:15], v[36:37], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[16:17], v[38:39], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[14:15], v[6:7], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[16:17], v[8:9], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB7_3 + s_branch .LBB7_10 +.LBB7_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr111 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB7_3: + v_readfirstlane_b32 s15, v227 + v_lshlrev_b32_e32 v66, 3, v67 + s_and_b32 s10, s15, 0xffffffc0 + v_add_u32_e32 v1, s10, v72 + v_add_u32_e32 v0, s18, v1 + v_mad_u64_u32 v[68:69], s[10:11], v0, s7, v[66:67] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v68 + s_nop 1 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + v_xor_b32_e32 v5, v2, v67 + v_add_u32_e32 v6, s7, v68 + v_lshlrev_b32_e32 v0, 1, v6 + buffer_load_dwordx4 v[14:17], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v9, 3, v2 + v_lshl_or_b32 v0, v73, 3, s19 + v_lshlrev_b32_e32 v4, 12, v2 + s_lshl_b32 s14, s21, 1 + s_lshr_b32 s21, s15, 2 + s_lshr_b32 s22, s15, 1 + v_lshl_or_b32 v22, v67, 8, v4 + s_mov_b32 s15, s11 + s_and_b32 s23, s21, 0x3ffffe0 + s_and_b32 s21, s21, 0x3ffffff0 + v_and_or_b32 v4, s22, 32, v73 + v_or_b32_e32 v7, s23, v73 + v_add_u32_e32 v23, s21, v9 + v_lshrrev_b32_e32 v4, 3, v4 + v_lshl_or_b32 v69, v1, 6, v66 + v_or_b32_e32 v82, 1, v1 + v_add_u32_e32 v24, s7, v6 + v_lshlrev_b32_e32 v6, 1, v24 + buffer_load_dwordx4 v[18:21], v6, s[8:11], 0 offen + v_ashrrev_i32_e32 v6, 31, v1 + v_or_b32_e32 v83, 2, v1 + v_lshlrev_b32_e32 v8, 6, v7 + v_mad_u64_u32 v[70:71], s[22:23], v23, s20, v[0:1] + v_xor_b32_e32 v7, v4, v67 + v_lshlrev_b32_e32 v0, 1, v69 + v_lshrrev_b32_e32 v71, 29, v6 + v_lshl_or_b32 v6, v7, 3, v22 + v_lshlrev_b32_e32 v30, 1, v70 + v_add_u32_e32 v22, s20, v70 + v_lshlrev_b32_e32 v31, 1, v22 + v_add_u32_e32 v34, s20, v22 + v_add_u32_e32 v35, s7, v24 + buffer_load_dwordx4 v[22:25], v30, s[12:15], 0 offen + buffer_load_dwordx4 v[26:29], v31, s[12:15], 0 offen + v_lshlrev_b32_e32 v30, 1, v35 + buffer_load_dwordx4 v[30:33], v30, s[8:11], 0 offen + v_lshlrev_b32_e32 v42, 1, v34 + v_add_u32_e32 v34, s20, v34 + v_add_u32_e32 v35, s7, v35 + v_lshlrev_b32_e32 v43, 1, v34 + v_add_u32_e32 v58, s20, v34 + v_lshlrev_b32_e32 v44, 1, v35 + v_add_u32_e32 v46, s7, v35 + buffer_load_dwordx4 v[34:37], v42, s[12:15], 0 offen + buffer_load_dwordx4 v[38:41], v43, s[12:15], 0 offen + v_lshlrev_b32_e32 v74, 1, v58 + buffer_load_dwordx4 v[42:45], v44, s[8:11], 0 offen + v_lshlrev_b32_e32 v47, 1, v46 + v_add_u32_e32 v50, s7, v46 + buffer_load_dwordx4 v[46:49], v47, s[8:11], 0 offen + v_lshlrev_b32_e32 v59, 1, v50 + v_add_lshl_u32 v60, v50, s7, 1 + buffer_load_dwordx4 v[50:53], v59, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v60, s[8:11], 0 offen + v_add_u32_e32 v58, s20, v58 + v_lshlrev_b32_e32 v75, 1, v58 + v_add_u32_e32 v76, s20, v58 + buffer_load_dwordx4 v[58:61], v74, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v75, s[12:15], 0 offen + v_lshlrev_b32_e32 v84, 1, v76 + v_add_lshl_u32 v85, v76, s20, 1 + buffer_load_dwordx4 v[74:77], v84, s[12:15], 0 offen + buffer_load_dwordx4 v[78:81], v85, s[12:15], 0 offen + v_add_u32_e32 v84, v82, v71 + v_add_u32_e32 v85, v83, v71 + v_and_b32_e32 v84, -8, v84 + v_sub_u32_e32 v82, v82, v84 + v_xor_b32_e32 v82, v82, v67 + v_sub_u32_e32 v84, v82, v67 + v_lshlrev_b32_e32 v86, 3, v84 + s_waitcnt vmcnt(15) + ds_write_b128 v0, v[10:13] + v_and_b32_e32 v10, -8, v85 + v_sub_u32_e32 v10, v83, v10 + v_xor_b32_e32 v10, v10, v67 + v_sub_u32_e32 v11, v10, v82 + v_lshlrev_b32_e32 v12, 3, v11 + v_add3_u32 v12, v86, v69, v12 + v_lshl_add_u32 v0, v84, 4, v0 + s_waitcnt vmcnt(14) + ds_write_b128 v0, v[14:17] offset:128 + v_or_b32_e32 v13, 3, v1 + v_add_u32_e32 v14, v13, v71 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v13, v13, v14 + v_xor_b32_e32 v13, v13, v67 + v_sub_u32_e32 v10, v13, v10 + v_lshlrev_b32_e32 v14, 3, v10 + v_or_b32_e32 v15, 4, v1 + v_add_u32_e32 v16, v15, v71 + v_and_b32_e32 v16, -8, v16 + v_sub_u32_e32 v15, v15, v16 + v_xor_b32_e32 v15, v15, v67 + v_sub_u32_e32 v13, v15, v13 + v_lshlrev_b32_e32 v16, 3, v13 + v_add3_u32 v12, v12, v14, v16 + v_lshlrev_b32_e32 v11, 4, v11 + s_movk_i32 s22, 0x80 + v_add3_u32 v0, v0, s22, v11 + s_waitcnt vmcnt(13) + ds_write_b128 v0, v[18:21] offset:128 + v_or_b32_e32 v11, 5, v1 + v_add_u32_e32 v14, v11, v71 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v11, v11, v14 + v_xor_b32_e32 v11, v11, v67 + v_sub_u32_e32 v14, v11, v15 + v_lshlrev_b32_e32 v15, 3, v14 + v_or_b32_e32 v16, 6, v1 + v_add_u32_e32 v17, v16, v71 + v_and_b32_e32 v17, -8, v17 + v_sub_u32_e32 v16, v16, v17 + v_xor_b32_e32 v16, v16, v67 + v_sub_u32_e32 v11, v16, v11 + v_lshlrev_b32_e32 v17, 3, v11 + v_add3_u32 v12, v12, v15, v17 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v0, v0, s22, v10 + s_waitcnt vmcnt(10) + ds_write_b128 v0, v[30:33] offset:128 + v_or_b32_e32 v1, 7, v1 + v_add_u32_e32 v10, v1, v71 + v_and_b32_e32 v10, 0xffffff8, v10 + v_sub_u32_e32 v1, v1, v10 + v_xor_b32_e32 v1, v1, v67 + v_sub_u32_e32 v1, v1, v16 + v_lshlrev_b32_e32 v1, 4, v1 + v_lshl_add_u32 v1, v12, 1, v1 + v_lshlrev_b32_e32 v10, 4, v13 + v_add3_u32 v0, v0, s22, v10 + s_waitcnt vmcnt(7) + ds_write_b128 v0, v[42:45] offset:128 + v_lshlrev_b32_e32 v10, 4, v14 + v_add3_u32 v0, v0, s22, v10 + s_waitcnt vmcnt(6) + ds_write_b128 v0, v[46:49] offset:128 + v_lshlrev_b32_e32 v10, 4, v11 + v_add3_u32 v0, v0, s22, v10 + s_waitcnt vmcnt(5) + ds_write_b128 v0, v[50:53] offset:128 + s_waitcnt vmcnt(4) + ds_write_b128 v1, v[54:57] offset:896 + s_mov_b32 s22, 0x1000504 + v_perm_b32 v10, v22, v26, s22 + s_mov_b32 s23, 0x3020706 + v_perm_b32 v14, v22, v26, s23 + v_perm_b32 v11, v34, v38, s22 + v_perm_b32 v15, v34, v38, s23 + s_waitcnt vmcnt(2) + v_perm_b32 v12, v58, v62, s22 + v_perm_b32 v16, v58, v62, s23 + s_waitcnt vmcnt(0) + v_perm_b32 v13, v74, v78, s22 + v_perm_b32 v17, v74, v78, s23 + v_perm_b32 v18, v23, v27, s22 + v_perm_b32 v30, v23, v27, s23 + v_perm_b32 v19, v35, v39, s22 + v_perm_b32 v31, v35, v39, s23 + v_perm_b32 v20, v59, v63, s22 + v_perm_b32 v32, v59, v63, s23 + v_perm_b32 v21, v75, v79, s22 + v_perm_b32 v33, v75, v79, s23 + v_perm_b32 v42, v24, v28, s22 + v_perm_b32 v46, v24, v28, s23 + v_perm_b32 v43, v36, v40, s22 + v_perm_b32 v47, v36, v40, s23 + v_perm_b32 v44, v60, v64, s22 + v_perm_b32 v48, v60, v64, s23 + v_perm_b32 v45, v76, v80, s22 + v_perm_b32 v49, v76, v80, s23 + v_perm_b32 v22, v25, v29, s22 + v_perm_b32 v26, v25, v29, s23 + v_perm_b32 v23, v37, v41, s22 + v_perm_b32 v27, v37, v41, s23 + v_perm_b32 v24, v61, v65, s22 + v_perm_b32 v28, v61, v65, s23 + v_perm_b32 v25, v77, v81, s22 + v_perm_b32 v29, v77, v81, s23 + v_and_b32_e32 v104, 24, v3 + v_add_u32_e32 v0, s21, v104 + v_lshrrev_b32_e32 v1, 2, v0 + v_and_b32_e32 v1, 24, v1 + v_xor_b32_e32 v3, v1, v73 + v_lshlrev_b32_e32 v34, 9, v0 + v_and_b32_e32 v34, 0x3000, v34 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v0, 0xfffff800, v0 + v_add_u32_e32 v0, v0, v34 + v_lshl_or_b32 v0, v3, 3, v0 + v_lshlrev_b32_e32 v34, 1, v0 + ds_write_b128 v34, v[10:13] offset:32768 + v_or_b32_e32 v10, 1, v1 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v3, v10, v3 + v_lshl_add_u32 v0, v3, 3, v0 + v_lshl_add_u32 v3, v3, 4, v34 + ds_write_b128 v3, v[14:17] offset:33280 + v_or_b32_e32 v3, 2, v1 + v_xor_b32_e32 v3, v3, v73 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + s_movk_i32 s21, 0x100 + v_add3_u32 v0, v0, v10, s21 + v_lshlrev_b32_e32 v10, 1, v0 + ds_write_b128 v10, v[18:21] offset:33280 + v_or_b32_e32 v10, 3, v1 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v3, v10, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v0, v0, v3, s21 + v_lshlrev_b32_e32 v3, 1, v0 + ds_write_b128 v3, v[30:33] offset:33280 + v_or_b32_e32 v3, 4, v1 + v_xor_b32_e32 v3, v3, v73 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v0, v0, v10, s21 + v_lshlrev_b32_e32 v10, 1, v0 + ds_write_b128 v10, v[42:45] offset:33280 + v_or_b32_e32 v10, 5, v1 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v3, v10, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v0, v0, v3, s21 + v_lshlrev_b32_e32 v3, 1, v0 + ds_write_b128 v3, v[46:49] offset:33280 + v_or_b32_e32 v3, 6, v1 + v_xor_b32_e32 v3, v3, v73 + v_sub_u32_e32 v10, v3, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add_lshl_u32 v0, v0, v10, 1 + v_or_b32_e32 v1, 7, v1 + v_xor_b32_e32 v1, v1, v73 + v_sub_u32_e32 v1, v1, v3 + v_lshl_add_u32 v1, v1, 4, v0 + ds_write_b128 v0, v[22:25] offset:33792 + ds_write_b128 v1, v[26:29] offset:34304 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v13, 2, v2 + v_or_b32_e32 v12, 4, v2 + v_add_u32_e32 v11, 6, v2 + v_add_u32_e32 v10, 16, v9 + v_add_u32_e32 v1, 48, v9 + v_or_b32_e32 v0, 8, v4 + v_or_b32_e32 v9, 16, v4 + v_or_b32_e32 v3, 24, v4 + s_cbranch_vccnz .LBB7_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit193.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v14, v13, v67 + v_lshl_add_u32 v78, v14, 3, v8 + v_xor_b32_e32 v15, v12, v67 + v_lshl_add_u32 v79, v15, 3, v8 + v_xor_b32_e32 v16, v11, v67 + v_lshl_add_u32 v69, v16, 3, v8 + v_sub_u32_e32 v17, v5, v16 + v_mov_b32_e32 v18, 0x1000 + v_lshl_add_u32 v17, v17, 3, v18 + v_add_u32_e32 v95, v69, v17 + v_sub_u32_e32 v14, v14, v5 + v_lshlrev_b32_e32 v14, 3, v14 + v_add_u32_e32 v80, v95, v14 + v_sub_u32_e32 v15, v15, v5 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v83, v95, v15 + v_sub_u32_e32 v16, v16, v5 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v75, v95, v16 + v_add_u32_e32 v94, v75, v17 + v_add_u32_e32 v81, v94, v14 + v_add_u32_e32 v82, v94, v15 + v_add_u32_e32 v74, v94, v16 + v_add_u32_e32 v91, v74, v17 + v_add_u32_e32 v76, v91, v14 + v_add_u32_e32 v77, v91, v15 + v_add_u32_e32 v71, v91, v16 + v_lshrrev_b32_e32 v14, 5, v10 + v_bfe_u32 v15, v10, 3, 2 + v_lshl_or_b32 v16, v14, 3, v67 + v_xor_b32_e32 v17, v4, v16 + v_sub_u32_e32 v18, v17, v7 + v_lshlrev_b32_e32 v19, 11, v14 + v_lshlrev_b32_e32 v18, 3, v18 + v_sub_u32_e32 v20, v15, v2 + v_lshl_or_b32 v19, v20, 12, v19 + v_add3_u32 v86, v6, v19, v18 + v_xor_b32_e32 v14, 1, v14 + v_sub_u32_e32 v15, v2, v15 + v_lshl_add_u32 v18, v14, 3, v16 + v_xor_b32_e32 v20, v4, v18 + v_sub_u32_e32 v17, v20, v17 + v_lshlrev_b32_e32 v14, 11, v14 + v_lshlrev_b32_e32 v17, 3, v17 + v_lshl_or_b32 v14, v15, 12, v14 + v_add3_u32 v84, v17, v14, v86 + v_lshrrev_b32_e32 v15, 5, v1 + v_add_u32_e32 v17, -1, v15 + v_bfe_u32 v21, v1, 3, 2 + v_sub_u32_e32 v22, v21, v2 + v_lshl_add_u32 v23, v17, 3, v18 + v_ashrrev_i32_e32 v24, 31, v23 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v23, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v24, v23, v24 + v_xor_b32_e32 v25, v4, v24 + v_sub_u32_e32 v20, v25, v20 + v_lshlrev_b32_e32 v17, 11, v17 + v_lshlrev_b32_e32 v20, 3, v20 + v_lshl_add_u32 v17, v22, 12, v17 + v_add3_u32 v85, v20, v17, v84 + v_sub_u32_e32 v20, v2, v21 + v_lshlrev_b32_e32 v21, 3, v15 + v_sub_u32_e32 v21, v23, v21 + v_ashrrev_i32_e32 v22, 31, v21 + v_lshrrev_b32_e32 v22, 27, v22 + v_add_u32_e32 v22, v21, v22 + v_and_b32_e32 v22, 0xffffffe0, v22 + v_sub_u32_e32 v21, v21, v22 + v_xor_b32_e32 v22, v0, v21 + v_sub_u32_e32 v23, v22, v25 + v_lshlrev_b32_e32 v23, 3, v23 + v_lshlrev_b32_e32 v20, 12, v20 + v_lshlrev_b32_e32 v15, 11, v15 + v_sub_u32_e32 v15, v20, v15 + v_add3_u32 v96, v23, v15, v85 + v_xor_b32_e32 v20, v0, v16 + v_sub_u32_e32 v22, v20, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v97, v22, v19, v96 + v_xor_b32_e32 v22, v0, v18 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v87, v20, v14, v97 + v_xor_b32_e32 v20, v0, v24 + v_sub_u32_e32 v22, v20, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v88, v22, v17, v87 + v_xor_b32_e32 v22, v9, v21 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v98, v20, v15, v88 + v_xor_b32_e32 v20, v9, v16 + v_sub_u32_e32 v22, v20, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v99, v22, v19, v98 + v_xor_b32_e32 v22, v9, v18 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v89, v20, v14, v99 + v_xor_b32_e32 v20, v9, v24 + v_sub_u32_e32 v22, v20, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v90, v22, v17, v89 + v_xor_b32_e32 v21, v3, v21 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v100, v20, v15, v90 + v_xor_b32_e32 v15, v3, v16 + v_sub_u32_e32 v16, v15, v21 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v101, v16, v19, v100 + v_xor_b32_e32 v16, v3, v18 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 3, v15 + v_add3_u32 v92, v15, v14, v101 + v_xor_b32_e32 v14, v3, v24 + v_sub_u32_e32 v14, v14, v16 + v_lshlrev_b32_e32 v14, 3, v14 + v_add3_u32 v93, v14, v17, v92 + s_mov_b64 s[2:3], 0 + s_branch .LBB7_6 +.LBB7_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr93 +.LBB7_6: ; %Flow54 + v_lshl_or_b32 v14, v5, 3, v8 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a96, 0 + v_lshlrev_b32_e32 v103, 1, v14 + v_lshlrev_b32_e32 v102, 1, v6 + s_cbranch_vccnz .LBB7_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i528.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s20, 6 + v_xor_b32_e32 v13, v13, v67 + v_lshl_add_u32 v78, v13, 3, v8 + v_xor_b32_e32 v12, v12, v67 + v_lshl_add_u32 v79, v12, 3, v8 + v_xor_b32_e32 v11, v11, v67 + v_lshl_add_u32 v69, v11, 3, v8 + v_sub_u32_e32 v8, v5, v11 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_u32_e32 v14, 0x1000, v8 + v_add_u32_e32 v95, v69, v14 + v_add_u32_e32 v8, v69, v8 + v_lshlrev_b32_e32 v105, 1, v8 + v_sub_u32_e32 v13, v13, v5 + v_lshlrev_b32_e32 v13, 3, v13 + v_add_u32_e32 v80, v95, v13 + v_add_lshl_u32 v106, v8, v13, 1 + v_sub_u32_e32 v12, v12, v5 + v_lshlrev_b32_e32 v12, 3, v12 + v_add_u32_e32 v83, v95, v12 + v_add_lshl_u32 v107, v8, v12, 1 + v_sub_u32_e32 v5, v11, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v75, v95, v5 + v_add_u32_e32 v8, v8, v5 + v_lshlrev_b32_e32 v108, 1, v8 + v_add_u32_e32 v94, v75, v14 + v_add_lshl_u32 v109, v8, v14, 1 + v_add_u32_e32 v81, v94, v13 + v_add_u32_e32 v82, v94, v12 + v_add_u32_e32 v74, v94, v5 + v_add_u32_e32 v91, v74, v14 + v_add_u32_e32 v76, v91, v13 + v_add_u32_e32 v77, v91, v12 + v_add_u32_e32 v71, v91, v5 + v_lshrrev_b32_e32 v5, 5, v10 + v_bfe_u32 v8, v10, 3, 2 + v_lshl_or_b32 v10, v5, 3, v67 + v_xor_b32_e32 v11, v4, v10 + v_sub_u32_e32 v7, v11, v7 + v_lshlrev_b32_e32 v12, 11, v5 + v_lshlrev_b32_e32 v7, 3, v7 + v_sub_u32_e32 v13, v8, v2 + v_lshl_or_b32 v12, v13, 12, v12 + v_add3_u32 v86, v6, v12, v7 + v_xor_b32_e32 v5, 1, v5 + v_sub_u32_e32 v6, v2, v8 + v_lshl_add_u32 v7, v5, 3, v10 + v_xor_b32_e32 v8, v4, v7 + v_sub_u32_e32 v11, v8, v11 + v_lshlrev_b32_e32 v5, 11, v5 + v_lshlrev_b32_e32 v11, 3, v11 + v_lshl_or_b32 v5, v6, 12, v5 + v_add3_u32 v84, v11, v5, v86 + v_lshrrev_b32_e32 v6, 5, v1 + v_add_u32_e32 v11, -1, v6 + v_bfe_u32 v1, v1, 3, 2 + v_sub_u32_e32 v13, v1, v2 + v_lshl_add_u32 v14, v11, 3, v7 + v_ashrrev_i32_e32 v15, 31, v14 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v14, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v15, v14, v15 + v_xor_b32_e32 v4, v4, v15 + v_sub_u32_e32 v8, v4, v8 + v_lshlrev_b32_e32 v11, 11, v11 + v_lshlrev_b32_e32 v8, 3, v8 + v_lshl_add_u32 v11, v13, 12, v11 + v_add3_u32 v85, v8, v11, v84 + v_sub_u32_e32 v1, v2, v1 + v_lshlrev_b32_e32 v2, 3, v6 + v_sub_u32_e32 v2, v14, v2 + v_ashrrev_i32_e32 v8, 31, v2 + v_lshrrev_b32_e32 v8, 27, v8 + v_add_u32_e32 v8, v2, v8 + v_and_b32_e32 v8, 0xffffffe0, v8 + v_sub_u32_e32 v2, v2, v8 + v_xor_b32_e32 v8, v0, v2 + v_sub_u32_e32 v4, v8, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v6, 11, v6 + v_sub_u32_e32 v1, v1, v6 + v_add3_u32 v96, v4, v1, v85 + v_xor_b32_e32 v4, v0, v10 + v_sub_u32_e32 v6, v4, v8 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v97, v6, v12, v96 + v_xor_b32_e32 v6, v0, v7 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v87, v4, v5, v97 + v_xor_b32_e32 v0, v0, v15 + v_sub_u32_e32 v4, v0, v6 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v88, v4, v11, v87 + v_xor_b32_e32 v4, v9, v2 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v98, v0, v1, v88 + v_xor_b32_e32 v0, v9, v10 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v99, v4, v12, v98 + v_xor_b32_e32 v4, v9, v7 + v_sub_u32_e32 v0, v4, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v89, v0, v5, v99 + v_xor_b32_e32 v0, v9, v15 + v_sub_u32_e32 v4, v0, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v90, v4, v11, v89 + v_xor_b32_e32 v2, v3, v2 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v100, v0, v1, v90 + v_xor_b32_e32 v0, v3, v10 + v_sub_u32_e32 v1, v0, v2 + v_lshlrev_b32_e32 v1, 3, v1 + v_add3_u32 v101, v1, v12, v100 + v_xor_b32_e32 v1, v3, v7 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v92, v0, v5, v101 + v_xor_b32_e32 v0, v3, v15 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v93, v0, v11, v92 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + s_movk_i32 s6, 0x80 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + s_movk_i32 s23, 0x100 +.LBB7_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i528.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v70, s2, v70 + v_add_u32_e32 v68, 64, v68 + v_lshlrev_b32_e32 v0, 1, v68 + v_add_u32_e32 v1, s7, v68 + v_lshlrev_b32_e32 v2, 1, v70 + v_add_u32_e32 v6, s20, v70 + v_lshlrev_b32_e32 v7, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[2:5], v2, s[12:15], 0 offen + v_lshlrev_b32_e32 v8, 1, v6 + v_add_u32_e32 v6, s20, v6 + buffer_load_dwordx4 v[34:37], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v7, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[18:21], v8, s[12:15], 0 offen + v_lshlrev_b32_e32 v7, 1, v6 + v_add_u32_e32 v10, s20, v6 + v_lshlrev_b32_e32 v11, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[6:9], v7, s[12:15], 0 offen + v_lshlrev_b32_e32 v12, 1, v10 + v_add_u32_e32 v10, s20, v10 + buffer_load_dwordx4 v[50:53], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v11, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[26:29], v12, s[12:15], 0 offen + v_lshlrev_b32_e32 v11, 1, v10 + v_add_u32_e32 v14, s20, v10 + v_lshlrev_b32_e32 v15, 1, v1 + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[10:13], v11, s[12:15], 0 offen + v_lshlrev_b32_e32 v16, 1, v14 + v_add_u32_e32 v14, s20, v14 + buffer_load_dwordx4 v[58:61], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v15, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v1 + v_add_lshl_u32 v1, v1, s7, 1 + buffer_load_dwordx4 v[30:33], v16, s[12:15], 0 offen + v_lshlrev_b32_e32 v15, 1, v14 + v_add_lshl_u32 v22, v14, s20, 1 + buffer_load_dwordx4 v[42:45], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[46:49], v1, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[14:17], v15, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[22:25], v22, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[114:117], v103 + ds_read_b128 v[110:113], v102 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[114:115], v[110:111], a[96:111] + v_lshlrev_b32_e32 v0, 1, v96 + ds_read_b128 v[118:121], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v97 + ds_read_b128 v[122:125], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[114:115], v[118:119], a[80:95] + v_lshlrev_b32_e32 v0, 1, v98 + ds_read_b128 v[126:129], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v99 + ds_read_b128 v[130:133], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[114:115], v[126:127], a[64:79] + v_lshlrev_b32_e32 v0, 1, v100 + ds_read_b128 v[134:137], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v101 + ds_read_b128 v[138:141], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[114:115], v[134:135], a[128:143] + ds_read_b128 v[142:145], v105 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[142:143], v[110:111], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[142:143], v[118:119], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[142:143], v[126:127], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[142:143], v[134:135], a[176:191] + ds_read_b128 v[146:149], v109 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[110:111], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[118:119], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[126:127], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[134:135], a[240:255] + v_lshlrev_b32_e32 v0, 1, v94 + ds_read_b128 v[150:153], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[110:111], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[118:119], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[126:127], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[134:135], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[116:117], v[112:113], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[116:117], v[120:121], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[116:117], v[128:129], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[116:117], v[136:137], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[144:145], v[112:113], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[144:145], v[120:121], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[144:145], v[128:129], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[144:145], v[136:137], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[112:113], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[120:121], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[128:129], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[136:137], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[112:113], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[120:121], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[128:129], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[136:137], a[48:63] + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[110:113], v0 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[114:117], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[126:129], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[110:111], v[114:115], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[110:111], v[122:123], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[110:111], v[130:131], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[110:111], v[138:139], a[128:143] + ds_read_b128 v[118:121], v106 offset:8192 + ds_read_b128 v[134:137], v107 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[118:119], v[114:115], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[118:119], v[122:123], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[118:119], v[130:131], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[118:119], v[138:139], a[176:191] + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[142:145], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[146:149], v0 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[114:115], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[122:123], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[130:131], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[142:143], v[138:139], a[240:255] + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[150:153], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[154:157], v0 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[114:115], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[150:151], v[122:123], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[150:151], v[130:131], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[150:151], v[138:139], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[112:113], v[116:117], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[112:113], v[124:125], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[112:113], v[132:133], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[112:113], v[140:141], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[116:117], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[120:121], v[124:125], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[120:121], v[132:133], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[120:121], v[140:141], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[144:145], v[116:117], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[144:145], v[124:125], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[144:145], v[132:133], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[140:141], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[152:153], v[116:117], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[124:125], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[132:133], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[152:153], v[140:141], a[48:63] + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[130:133], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[122:125], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[126:127], v[130:131], a[96:111] + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[138:141], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[118:121], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[80:95], v[126:127], v[138:139], a[80:95] + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[142:145], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v90 + ds_read_b128 v[114:117], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[142:143], a[64:79] + v_lshlrev_b32_e32 v0, 1, v92 + ds_read_b128 v[150:153], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v93 + ds_read_b128 v[110:113], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[128:143], v[126:127], v[150:151], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[134:135], v[130:131], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[134:135], v[138:139], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[134:135], v[142:143], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[134:135], v[150:151], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[146:147], v[130:131], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[146:147], v[138:139], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[142:143], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[150:151], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[154:155], v[130:131], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[138:139], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[154:155], v[142:143], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[154:155], v[150:151], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[128:129], v[132:133], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[128:129], v[140:141], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[128:129], v[144:145], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[152:153], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[136:137], v[132:133], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[136:137], v[140:141], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[136:137], v[144:145], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[136:137], v[152:153], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[148:149], v[132:133], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[148:149], v[140:141], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[144:145], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[152:153], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[156:157], v[132:133], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[156:157], v[140:141], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[156:157], v[144:145], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[156:157], v[152:153], a[48:63] + v_lshlrev_b32_e32 v0, 1, v69 + ds_read_b128 v[126:129], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[126:127], v[122:123], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[126:127], v[118:119], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_f32_32x32x8_f16 a[128:143], v[126:127], v[110:111], a[128:143] + ds_read_b128 v[130:133], v108 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[130:131], v[122:123], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[130:131], v[118:119], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[130:131], v[114:115], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[130:131], v[110:111], a[176:191] + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[142:145], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[192:207], v[142:143], v[122:123], a[192:207] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[118:119], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[142:143], v[114:115], a[224:239] + v_mfma_f32_32x32x8_f16 a[240:255], v[142:143], v[110:111], a[240:255] + v_lshlrev_b32_e32 v0, 1, v74 + ds_read_b128 v[146:149], v0 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[0:15], v[146:147], v[122:123], a[0:15] + s_add_i32 s24, s3, -1 + v_mfma_f32_32x32x8_f16 a[32:47], v[146:147], v[118:119], a[32:47] + v_readfirstlane_b32 s25, v227 + s_and_b32 s26, s25, 0xffffffc0 + s_lshr_b32 s25, s25, 2 + v_add_u32_e32 v0, s26, v72 + s_and_b32 s25, s25, 0x3ffffff0 + v_lshl_or_b32 v1, v0, 6, v66 + v_or_b32_e32 v118, 1, v0 + v_mfma_f32_32x32x8_f16 a[16:31], v[146:147], v[114:115], a[16:31] + v_ashrrev_i32_e32 v114, 31, v0 + v_or_b32_e32 v115, 2, v0 + v_or_b32_e32 v119, 3, v0 + v_or_b32_e32 v122, 4, v0 + v_or_b32_e32 v123, 5, v0 + v_or_b32_e32 v126, 6, v0 + v_or_b32_e32 v0, 7, v0 + v_mfma_f32_32x32x8_f16 a[48:63], v[146:147], v[110:111], a[48:63] + v_add_u32_e32 v110, s25, v104 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s24 + v_lshlrev_b32_e32 v111, 1, v1 + v_lshrrev_b32_e32 v114, 29, v114 + v_lshrrev_b32_e32 v127, 2, v110 + v_lshlrev_b32_e32 v130, 9, v110 + v_mfma_f32_32x32x8_f16 a[96:111], v[128:129], v[124:125], a[96:111] + v_lshlrev_b32_e32 v110, 6, v110 + v_add_u32_e32 v131, v118, v114 + v_add_u32_e32 v134, v115, v114 + v_add_u32_e32 v135, v119, v114 + v_add_u32_e32 v136, v122, v114 + v_add_u32_e32 v137, v123, v114 + v_add_u32_e32 v138, v126, v114 + v_mfma_f32_32x32x8_f16 a[80:95], v[128:129], v[120:121], a[80:95] + v_add_u32_e32 v114, v0, v114 + v_and_b32_e32 v127, 24, v127 + v_and_b32_e32 v130, 0x3000, v130 + v_and_b32_e32 v110, 0xfffff800, v110 + v_and_b32_e32 v131, -8, v131 + v_and_b32_e32 v134, -8, v134 + v_and_b32_e32 v135, -8, v135 + v_mfma_f32_32x32x8_f16 a[64:79], v[128:129], v[116:117], a[64:79] + v_and_b32_e32 v136, -8, v136 + v_and_b32_e32 v137, -8, v137 + v_and_b32_e32 v138, -8, v138 + v_and_b32_e32 v114, 0xffffff8, v114 + v_xor_b32_e32 v139, v127, v73 + v_add_u32_e32 v110, v110, v130 + v_or_b32_e32 v130, 1, v127 + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[112:113], a[128:143] + v_or_b32_e32 v128, 2, v127 + v_or_b32_e32 v129, 3, v127 + v_or_b32_e32 v140, 4, v127 + v_or_b32_e32 v141, 5, v127 + v_or_b32_e32 v142, 6, v127 + v_or_b32_e32 v127, 7, v127 + v_sub_u32_e32 v118, v118, v131 + v_mfma_f32_32x32x8_f16 a[112:127], v[132:133], v[124:125], a[112:127] + v_sub_u32_e32 v115, v115, v134 + v_sub_u32_e32 v119, v119, v135 + v_sub_u32_e32 v122, v122, v136 + v_sub_u32_e32 v123, v123, v137 + v_sub_u32_e32 v126, v126, v138 + v_sub_u32_e32 v0, v0, v114 + v_lshl_or_b32 v110, v139, 3, v110 + v_mfma_f32_32x32x8_f16 a[144:159], v[132:133], v[120:121], a[144:159] + v_xor_b32_e32 v114, v130, v73 + v_xor_b32_e32 v128, v128, v73 + v_xor_b32_e32 v129, v129, v73 + v_xor_b32_e32 v130, v140, v73 + v_xor_b32_e32 v131, v141, v73 + v_xor_b32_e32 v134, v142, v73 + v_xor_b32_e32 v127, v127, v73 + v_mfma_f32_32x32x8_f16 a[160:175], v[132:133], v[116:117], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_xor_b32_e32 v118, v118, v67 + v_xor_b32_e32 v115, v115, v67 + v_xor_b32_e32 v119, v119, v67 + v_xor_b32_e32 v122, v122, v67 + v_xor_b32_e32 v123, v123, v67 + v_mfma_f32_32x32x8_f16 a[176:191], v[132:133], v[112:113], a[176:191] + v_xor_b32_e32 v126, v126, v67 + v_xor_b32_e32 v0, v0, v67 + v_lshlrev_b32_e32 v132, 1, v110 + v_sub_u32_e32 v133, v114, v139 + v_sub_u32_e32 v114, v128, v114 + v_sub_u32_e32 v128, v129, v128 + v_sub_u32_e32 v129, v130, v129 + v_mfma_f32_32x32x8_f16 a[192:207], v[144:145], v[124:125], a[192:207] + v_sub_u32_e32 v130, v131, v130 + v_sub_u32_e32 v131, v134, v131 + v_sub_u32_e32 v127, v127, v134 + v_sub_u32_e32 v134, v118, v67 + v_sub_u32_e32 v118, v115, v118 + v_sub_u32_e32 v115, v119, v115 + v_sub_u32_e32 v119, v122, v119 + v_mfma_f32_32x32x8_f16 a[208:223], v[144:145], v[120:121], a[208:223] + v_sub_u32_e32 v122, v123, v122 + v_sub_u32_e32 v123, v126, v123 + v_sub_u32_e32 v0, v0, v126 + v_lshl_add_u32 v110, v133, 3, v110 + v_lshl_add_u32 v126, v133, 4, v132 + v_lshlrev_b32_e32 v114, 3, v114 + v_lshlrev_b32_e32 v128, 3, v128 + v_mfma_f32_32x32x8_f16 a[224:239], v[144:145], v[116:117], a[224:239] + v_lshlrev_b32_e32 v129, 3, v129 + v_lshlrev_b32_e32 v130, 3, v130 + v_lshlrev_b32_e32 v131, 3, v131 + v_lshlrev_b32_e32 v133, 3, v134 + v_lshlrev_b32_e32 v135, 3, v118 + v_lshl_add_u32 v134, v134, 4, v111 + v_lshlrev_b32_e32 v136, 3, v115 + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[112:113], a[240:255] + v_lshlrev_b32_e32 v137, 3, v119 + v_lshlrev_b32_e32 v118, 4, v118 + v_lshlrev_b32_e32 v138, 3, v122 + v_lshlrev_b32_e32 v139, 3, v123 + v_lshlrev_b32_e32 v115, 4, v115 + v_lshlrev_b32_e32 v0, 4, v0 + v_lshlrev_b32_e32 v119, 4, v119 + v_mfma_f32_32x32x8_f16 a[0:15], v[148:149], v[124:125], a[0:15] + v_lshlrev_b32_e32 v122, 4, v122 + v_add3_u32 v110, v110, v114, s23 + v_add3_u32 v1, v133, v1, v135 + v_add3_u32 v124, v134, s6, v118 + v_lshlrev_b32_e32 v125, 1, v110 + v_add3_u32 v110, v110, v128, s23 + v_add3_u32 v1, v1, v136, v137 + v_mfma_f32_32x32x8_f16 a[32:47], v[148:149], v[120:121], a[32:47] + v_add3_u32 v115, v124, s6, v115 + v_lshlrev_b32_e32 v128, 1, v110 + v_add3_u32 v110, v110, v129, s23 + v_add3_u32 v1, v1, v138, v139 + v_add3_u32 v120, v115, s6, v119 + v_lshlrev_b32_e32 v129, 1, v110 + v_add3_u32 v110, v110, v130, s23 + v_mfma_f32_32x32x8_f16 a[16:31], v[148:149], v[116:117], a[16:31] + v_lshl_add_u32 v117, v1, 1, v0 + v_add3_u32 v116, v120, s6, v122 + v_lshlrev_b32_e32 v122, 1, v110 + v_add_lshl_u32 v130, v110, v131, 1 + v_add_u32_e32 v0, 0x80, v116 + v_lshl_add_u32 v127, v127, 4, v130 + v_lshl_add_u32 v121, v123, 4, v0 + v_mfma_f32_32x32x8_f16 a[48:63], v[148:149], v[112:113], a[48:63] + s_waitcnt vmcnt(14) + ds_write_b128 v111, v[34:37] + s_waitcnt vmcnt(13) + ds_write_b128 v134, v[38:41] offset:128 + s_waitcnt vmcnt(12) + v_perm_b32 v0, v2, v18, s21 + v_perm_b32 v18, v2, v18, s22 + v_perm_b32 v34, v3, v19, s21 + v_perm_b32 v38, v3, v19, s22 + v_perm_b32 v110, v4, v20, s21 + v_perm_b32 v4, v4, v20, s22 + v_perm_b32 v114, v5, v21, s21 + v_perm_b32 v118, v5, v21, s22 + s_waitcnt vmcnt(10) + ds_write_b128 v124, v[50:53] offset:128 + s_waitcnt vmcnt(9) + ds_write_b128 v115, v[54:57] offset:128 + s_waitcnt vmcnt(8) + v_perm_b32 v1, v6, v26, s21 + v_perm_b32 v19, v6, v26, s22 + v_perm_b32 v35, v7, v27, s21 + v_perm_b32 v39, v7, v27, s22 + v_perm_b32 v111, v8, v28, s21 + v_perm_b32 v5, v8, v28, s22 + v_perm_b32 v115, v9, v29, s21 + v_perm_b32 v119, v9, v29, s22 + s_waitcnt vmcnt(6) + ds_write_b128 v120, v[58:61] offset:128 + s_waitcnt vmcnt(5) + ds_write_b128 v116, v[62:65] offset:128 + s_waitcnt vmcnt(4) + v_perm_b32 v2, v10, v30, s21 + v_perm_b32 v20, v10, v30, s22 + v_perm_b32 v36, v11, v31, s21 + v_perm_b32 v40, v11, v31, s22 + v_perm_b32 v112, v12, v32, s21 + v_perm_b32 v6, v12, v32, s22 + v_perm_b32 v116, v13, v33, s21 + v_perm_b32 v120, v13, v33, s22 + s_waitcnt vmcnt(3) + ds_write_b128 v121, v[42:45] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v117, v[46:49] offset:896 + s_waitcnt vmcnt(0) + v_perm_b32 v3, v14, v22, s21 + v_perm_b32 v21, v14, v22, s22 + v_perm_b32 v37, v15, v23, s21 + v_perm_b32 v41, v15, v23, s22 + v_perm_b32 v113, v16, v24, s21 + v_perm_b32 v7, v16, v24, s22 + v_perm_b32 v117, v17, v25, s21 + v_perm_b32 v121, v17, v25, s22 + ds_write_b128 v132, v[0:3] offset:32768 + ds_write_b128 v126, v[18:21] offset:33280 + ds_write_b128 v125, v[34:37] offset:33280 + ds_write_b128 v128, v[38:41] offset:33280 + ds_write_b128 v129, v[110:113] offset:33280 + ds_write_b128 v122, v[4:7] offset:33280 + ds_write_b128 v130, v[114:117] offset:33792 + ds_write_b128 v127, v[118:121] offset:34304 + s_cbranch_scc1 .LBB7_8 +.LBB7_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEDF16_NS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDa + v_accvgpr_read_b32 v152, a144 + v_accvgpr_read_b32 v153, a145 + v_accvgpr_read_b32 v154, a146 + v_accvgpr_read_b32 v155, a147 + v_accvgpr_read_b32 v156, a148 + v_accvgpr_read_b32 v157, a149 + v_accvgpr_read_b32 v158, a150 + v_accvgpr_read_b32 v159, a151 + v_accvgpr_read_b32 v160, a152 + v_accvgpr_read_b32 v161, a153 + v_accvgpr_read_b32 v162, a154 + v_accvgpr_read_b32 v163, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v165, a157 + v_accvgpr_read_b32 v166, a158 + v_accvgpr_read_b32 v167, a159 + v_accvgpr_read_b32 v136, a176 + v_accvgpr_read_b32 v137, a177 + v_accvgpr_read_b32 v138, a178 + v_accvgpr_read_b32 v139, a179 + v_accvgpr_read_b32 v140, a180 + v_accvgpr_read_b32 v141, a181 + v_accvgpr_read_b32 v142, a182 + v_accvgpr_read_b32 v143, a183 + v_accvgpr_read_b32 v144, a184 + v_accvgpr_read_b32 v145, a185 + v_accvgpr_read_b32 v146, a186 + v_accvgpr_read_b32 v147, a187 + v_accvgpr_read_b32 v148, a188 + v_accvgpr_read_b32 v149, a189 + v_accvgpr_read_b32 v150, a190 + v_accvgpr_read_b32 v151, a191 + v_accvgpr_read_b32 v120, a192 + v_accvgpr_read_b32 v121, a193 + v_accvgpr_read_b32 v122, a194 + v_accvgpr_read_b32 v123, a195 + v_accvgpr_read_b32 v124, a196 + v_accvgpr_read_b32 v125, a197 + v_accvgpr_read_b32 v126, a198 + v_accvgpr_read_b32 v127, a199 + v_accvgpr_read_b32 v128, a200 + v_accvgpr_read_b32 v129, a201 + v_accvgpr_read_b32 v130, a202 + v_accvgpr_read_b32 v131, a203 + v_accvgpr_read_b32 v132, a204 + v_accvgpr_read_b32 v133, a205 + v_accvgpr_read_b32 v134, a206 + v_accvgpr_read_b32 v135, a207 + v_accvgpr_read_b32 v104, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v106, a210 + v_accvgpr_read_b32 v107, a211 + v_accvgpr_read_b32 v108, a212 + v_accvgpr_read_b32 v109, a213 + v_accvgpr_read_b32 v110, a214 + v_accvgpr_read_b32 v111, a215 + v_accvgpr_read_b32 v112, a216 + v_accvgpr_read_b32 v113, a217 + v_accvgpr_read_b32 v114, a218 + v_accvgpr_read_b32 v115, a219 + v_accvgpr_read_b32 v116, a220 + v_accvgpr_read_b32 v117, a221 + v_accvgpr_read_b32 v118, a222 + v_accvgpr_read_b32 v119, a223 + v_accvgpr_read_b32 v48, a224 + v_accvgpr_read_b32 v49, a225 + v_accvgpr_read_b32 v50, a226 + v_accvgpr_read_b32 v51, a227 + v_accvgpr_read_b32 v52, a228 + v_accvgpr_read_b32 v53, a229 + v_accvgpr_read_b32 v54, a230 + v_accvgpr_read_b32 v55, a231 + v_accvgpr_read_b32 v56, a232 + v_accvgpr_read_b32 v57, a233 + v_accvgpr_read_b32 v58, a234 + v_accvgpr_read_b32 v59, a235 + v_accvgpr_read_b32 v60, a236 + v_accvgpr_read_b32 v61, a237 + v_accvgpr_read_b32 v62, a238 + v_accvgpr_read_b32 v63, a239 + v_accvgpr_read_b32 v32, a240 + v_accvgpr_read_b32 v33, a241 + v_accvgpr_read_b32 v34, a242 + v_accvgpr_read_b32 v35, a243 + v_accvgpr_read_b32 v36, a244 + v_accvgpr_read_b32 v37, a245 + v_accvgpr_read_b32 v38, a246 + v_accvgpr_read_b32 v39, a247 + v_accvgpr_read_b32 v40, a248 + v_accvgpr_read_b32 v41, a249 + v_accvgpr_read_b32 v42, a250 + v_accvgpr_read_b32 v43, a251 + v_accvgpr_read_b32 v44, a252 + v_accvgpr_read_b32 v45, a253 + v_accvgpr_read_b32 v46, a254 + v_accvgpr_read_b32 v47, a255 + v_accvgpr_read_b32 v16, a0 + v_accvgpr_read_b32 v17, a1 + v_accvgpr_read_b32 v18, a2 + v_accvgpr_read_b32 v19, a3 + v_accvgpr_read_b32 v20, a4 + v_accvgpr_read_b32 v21, a5 + v_accvgpr_read_b32 v22, a6 + v_accvgpr_read_b32 v23, a7 + v_accvgpr_read_b32 v24, a8 + v_accvgpr_read_b32 v25, a9 + v_accvgpr_read_b32 v26, a10 + v_accvgpr_read_b32 v27, a11 + v_accvgpr_read_b32 v28, a12 + v_accvgpr_read_b32 v29, a13 + v_accvgpr_read_b32 v30, a14 + v_accvgpr_read_b32 v31, a15 + v_accvgpr_read_b32 v0, a32 + v_accvgpr_read_b32 v1, a33 + v_accvgpr_read_b32 v2, a34 + v_accvgpr_read_b32 v3, a35 + v_accvgpr_read_b32 v4, a36 + v_accvgpr_read_b32 v5, a37 + v_accvgpr_read_b32 v6, a38 + v_accvgpr_read_b32 v7, a39 + v_accvgpr_read_b32 v8, a40 + v_accvgpr_read_b32 v9, a41 + v_accvgpr_read_b32 v10, a42 + v_accvgpr_read_b32 v11, a43 + v_accvgpr_read_b32 v12, a44 + v_accvgpr_read_b32 v13, a45 + v_accvgpr_read_b32 v14, a46 + v_accvgpr_read_b32 v15, a47 + v_accvgpr_mov_b32 a0, a16 + v_accvgpr_mov_b32 a1, a17 + v_accvgpr_mov_b32 a2, a18 + v_accvgpr_mov_b32 a3, a19 + v_accvgpr_mov_b32 a4, a20 + v_accvgpr_mov_b32 a5, a21 + v_accvgpr_mov_b32 a6, a22 + v_accvgpr_mov_b32 a7, a23 + v_accvgpr_mov_b32 a8, a24 + v_accvgpr_mov_b32 a9, a25 + v_accvgpr_mov_b32 a10, a26 + v_accvgpr_mov_b32 a11, a27 + v_accvgpr_mov_b32 a12, a28 + v_accvgpr_mov_b32 a13, a29 + v_accvgpr_mov_b32 a14, a30 + v_accvgpr_mov_b32 a15, a31 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[168:171], v103 + ds_read_b128 v[172:175], v102 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[168:169], v[172:173], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[170:171], v[174:175], a[96:111] + v_lshlrev_b32_e32 v64, 1, v96 + ds_read_b128 v[176:179], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v97 + v_accvgpr_mov_b32 a159, a95 + v_accvgpr_mov_b32 a158, a94 + v_accvgpr_mov_b32 a157, a93 + v_accvgpr_mov_b32 a156, a92 + v_accvgpr_mov_b32 a155, a91 + v_accvgpr_mov_b32 a154, a90 + v_accvgpr_mov_b32 a153, a89 + v_accvgpr_mov_b32 a152, a88 + v_accvgpr_mov_b32 a151, a87 + v_accvgpr_mov_b32 a150, a86 + v_accvgpr_mov_b32 a149, a85 + v_accvgpr_mov_b32 a148, a84 + v_accvgpr_mov_b32 a147, a83 + v_accvgpr_mov_b32 a146, a82 + v_accvgpr_mov_b32 a145, a81 + v_accvgpr_mov_b32 a144, a80 + ds_read_b128 v[180:183], v64 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[144:159], v[168:169], v[176:177], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[170:171], v[178:179], a[144:159] + v_lshlrev_b32_e32 v64, 1, v98 + ds_read_b128 v[184:187], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v99 + ds_read_b128 v[96:99], v64 offset:32768 + v_accvgpr_mov_b32 a191, a79 + v_accvgpr_mov_b32 a190, a78 + v_accvgpr_mov_b32 a189, a77 + v_accvgpr_mov_b32 a188, a76 + v_accvgpr_mov_b32 a187, a75 + v_accvgpr_mov_b32 a186, a74 + v_accvgpr_mov_b32 a185, a73 + v_accvgpr_mov_b32 a184, a72 + v_accvgpr_mov_b32 a183, a71 + v_accvgpr_mov_b32 a182, a70 + v_accvgpr_mov_b32 a181, a69 + v_accvgpr_mov_b32 a180, a68 + v_accvgpr_mov_b32 a179, a67 + v_accvgpr_mov_b32 a178, a66 + v_accvgpr_mov_b32 a177, a65 + v_accvgpr_mov_b32 a176, a64 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[168:169], v[184:185], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[170:171], v[186:187], a[176:191] + v_lshlrev_b32_e32 v64, 1, v100 + ds_read_b128 v[188:191], v64 offset:32768 + v_lshlrev_b32_e32 v64, 1, v101 + ds_read_b128 v[100:103], v64 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[168:169], v[188:189], a[208:223] + v_lshlrev_b32_e32 v64, 1, v95 + v_mfma_f32_32x32x8_f16 a[208:223], v[170:171], v[190:191], a[208:223] + ds_read_b128 v[168:171], v64 + v_accvgpr_mov_b32 a239, a127 + v_accvgpr_mov_b32 a238, a126 + v_accvgpr_mov_b32 a237, a125 + v_accvgpr_mov_b32 a236, a124 + v_accvgpr_mov_b32 a235, a123 + v_accvgpr_mov_b32 a234, a122 + v_accvgpr_mov_b32 a233, a121 + v_accvgpr_mov_b32 a232, a120 + v_accvgpr_mov_b32 a231, a119 + v_accvgpr_mov_b32 a230, a118 + v_accvgpr_mov_b32 a229, a117 + v_accvgpr_mov_b32 a228, a116 + v_accvgpr_mov_b32 a227, a115 + v_accvgpr_mov_b32 a226, a114 + v_accvgpr_mov_b32 a225, a113 + v_accvgpr_mov_b32 a224, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[168:169], v[172:173], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[170:171], v[174:175], a[224:239] + v_accvgpr_write_b32 a207, v167 + v_accvgpr_write_b32 a206, v166 + v_accvgpr_write_b32 a205, v165 + v_accvgpr_write_b32 a204, v164 + v_accvgpr_write_b32 a203, v163 + v_accvgpr_write_b32 a202, v162 + v_accvgpr_write_b32 a201, v161 + v_accvgpr_write_b32 a200, v160 + v_accvgpr_write_b32 a199, v159 + v_accvgpr_write_b32 a198, v158 + v_accvgpr_write_b32 a197, v157 + v_accvgpr_write_b32 a196, v156 + v_accvgpr_write_b32 a195, v155 + v_accvgpr_write_b32 a194, v154 + v_accvgpr_write_b32 a193, v153 + v_accvgpr_write_b32 a192, v152 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[192:207], v[168:169], v[176:177], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[170:171], v[178:179], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[168:169], v[184:185], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[170:171], v[186:187], a[160:175] + v_accvgpr_write_b32 a128, v136 + v_accvgpr_write_b32 a129, v137 + v_accvgpr_write_b32 a130, v138 + v_accvgpr_write_b32 a131, v139 + v_accvgpr_write_b32 a132, v140 + v_accvgpr_write_b32 a133, v141 + v_accvgpr_write_b32 a134, v142 + v_accvgpr_write_b32 a135, v143 + v_accvgpr_write_b32 a136, v144 + v_accvgpr_write_b32 a137, v145 + v_accvgpr_write_b32 a138, v146 + v_accvgpr_write_b32 a139, v147 + v_accvgpr_write_b32 a140, v148 + v_accvgpr_write_b32 a141, v149 + v_accvgpr_write_b32 a142, v150 + v_accvgpr_write_b32 a143, v151 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[128:143], v[168:169], v[188:189], a[128:143] + v_lshlrev_b32_e32 v64, 1, v94 + v_mfma_f32_32x32x8_f16 a[128:143], v[170:171], v[190:191], a[128:143] + ds_read_b128 v[136:139], v64 + v_accvgpr_write_b32 a112, v120 + v_accvgpr_write_b32 a113, v121 + v_accvgpr_write_b32 a114, v122 + v_accvgpr_write_b32 a115, v123 + v_accvgpr_write_b32 a116, v124 + v_accvgpr_write_b32 a117, v125 + v_accvgpr_write_b32 a118, v126 + v_accvgpr_write_b32 a119, v127 + v_accvgpr_write_b32 a120, v128 + v_accvgpr_write_b32 a121, v129 + v_accvgpr_write_b32 a122, v130 + v_accvgpr_write_b32 a123, v131 + v_accvgpr_write_b32 a124, v132 + v_accvgpr_write_b32 a125, v133 + v_accvgpr_write_b32 a126, v134 + v_accvgpr_write_b32 a127, v135 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[136:137], v[172:173], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[138:139], v[174:175], a[112:127] + v_accvgpr_write_b32 a80, v104 + v_accvgpr_write_b32 a81, v105 + v_accvgpr_write_b32 a82, v106 + v_accvgpr_write_b32 a83, v107 + v_accvgpr_write_b32 a84, v108 + v_accvgpr_write_b32 a85, v109 + v_accvgpr_write_b32 a86, v110 + v_accvgpr_write_b32 a87, v111 + v_accvgpr_write_b32 a88, v112 + v_accvgpr_write_b32 a89, v113 + v_accvgpr_write_b32 a90, v114 + v_accvgpr_write_b32 a91, v115 + v_accvgpr_write_b32 a92, v116 + v_accvgpr_write_b32 a93, v117 + v_accvgpr_write_b32 a94, v118 + v_accvgpr_write_b32 a95, v119 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[80:95], v[136:137], v[176:177], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[138:139], v[178:179], a[80:95] + v_accvgpr_write_b32 a79, v63 + v_accvgpr_write_b32 a78, v62 + v_accvgpr_write_b32 a77, v61 + v_accvgpr_write_b32 a76, v60 + v_accvgpr_write_b32 a75, v59 + v_accvgpr_write_b32 a74, v58 + v_accvgpr_write_b32 a73, v57 + v_accvgpr_write_b32 a72, v56 + v_accvgpr_write_b32 a71, v55 + v_accvgpr_write_b32 a70, v54 + v_accvgpr_write_b32 a69, v53 + v_accvgpr_write_b32 a68, v52 + v_accvgpr_write_b32 a67, v51 + v_accvgpr_write_b32 a66, v50 + v_accvgpr_write_b32 a65, v49 + v_accvgpr_write_b32 a64, v48 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], v[136:137], v[184:185], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[138:139], v[186:187], a[64:79] + v_accvgpr_write_b32 a63, v47 + v_accvgpr_write_b32 a62, v46 + v_accvgpr_write_b32 a61, v45 + v_accvgpr_write_b32 a60, v44 + v_accvgpr_write_b32 a59, v43 + v_accvgpr_write_b32 a58, v42 + v_accvgpr_write_b32 a57, v41 + v_accvgpr_write_b32 a56, v40 + v_accvgpr_write_b32 a55, v39 + v_accvgpr_write_b32 a54, v38 + v_accvgpr_write_b32 a53, v37 + v_accvgpr_write_b32 a52, v36 + v_accvgpr_write_b32 a51, v35 + v_accvgpr_write_b32 a50, v34 + v_accvgpr_write_b32 a49, v33 + v_accvgpr_write_b32 a48, v32 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[48:63], v[136:137], v[188:189], a[48:63] + v_lshlrev_b32_e32 v32, 1, v91 + v_mfma_f32_32x32x8_f16 a[48:63], v[138:139], v[190:191], a[48:63] + ds_read_b128 v[32:35], v32 + v_accvgpr_write_b32 a47, v31 + v_accvgpr_write_b32 a46, v30 + v_accvgpr_write_b32 a45, v29 + v_accvgpr_write_b32 a44, v28 + v_accvgpr_write_b32 a43, v27 + v_accvgpr_write_b32 a42, v26 + v_accvgpr_write_b32 a41, v25 + v_accvgpr_write_b32 a40, v24 + v_accvgpr_write_b32 a39, v23 + v_accvgpr_write_b32 a38, v22 + v_accvgpr_write_b32 a37, v21 + v_accvgpr_write_b32 a36, v20 + v_accvgpr_write_b32 a35, v19 + v_accvgpr_write_b32 a34, v18 + v_accvgpr_write_b32 a33, v17 + v_accvgpr_write_b32 a32, v16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[32:33], v[172:173], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[34:35], v[174:175], a[32:47] + v_accvgpr_write_b32 a31, v15 + v_accvgpr_write_b32 a30, v14 + v_accvgpr_write_b32 a29, v13 + v_accvgpr_write_b32 a28, v12 + v_accvgpr_write_b32 a27, v11 + v_accvgpr_write_b32 a26, v10 + v_accvgpr_write_b32 a25, v9 + v_accvgpr_write_b32 a24, v8 + v_accvgpr_write_b32 a23, v7 + v_accvgpr_write_b32 a22, v6 + v_accvgpr_write_b32 a21, v5 + v_accvgpr_write_b32 a20, v4 + v_accvgpr_write_b32 a19, v3 + v_accvgpr_write_b32 a18, v2 + v_accvgpr_write_b32 a17, v1 + v_accvgpr_write_b32 a16, v0 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[16:31], v[32:33], v[176:177], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[34:35], v[178:179], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[32:33], v[184:185], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[34:35], v[186:187], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[32:33], v[188:189], a[240:255] + v_lshlrev_b32_e32 v0, 1, v78 + v_mfma_f32_32x32x8_f16 a[240:255], v[34:35], v[190:191], a[240:255] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[6:9], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[10:13], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[180:181], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[4:5], v[182:183], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[96:97], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[4:5], v[98:99], a[176:191] + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[100:101], a[208:223] + v_lshlrev_b32_e32 v0, 1, v80 + v_mfma_f32_32x32x8_f16 a[208:223], v[4:5], v[102:103], a[208:223] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[14:17], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[180:181], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[4:5], v[182:183], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[96:97], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[4:5], v[98:99], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[100:101], a[128:143] + v_lshlrev_b32_e32 v0, 1, v81 + v_mfma_f32_32x32x8_f16 a[128:143], v[4:5], v[102:103], a[128:143] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[18:21], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[4:5], v[8:9], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[180:181], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[4:5], v[182:183], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[96:97], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[4:5], v[98:99], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[100:101], a[48:63] + v_lshlrev_b32_e32 v0, 1, v76 + v_mfma_f32_32x32x8_f16 a[48:63], v[4:5], v[102:103], a[48:63] + ds_read_b128 v[2:5], v0 + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[22:25], v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[4:5], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[180:181], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[4:5], v[182:183], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[96:97], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[4:5], v[98:99], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[100:101], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[4:5], v[102:103], a[240:255] + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[2:5], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[6:9], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[96:111], v[10:11], v[2:3], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[12:13], v[4:5], a[96:111] + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[26:29], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[30:33], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[144:159], v[10:11], v[26:27], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[12:13], v[28:29], a[144:159] + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[34:37], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v90 + ds_read_b128 v[38:41], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[176:191], v[10:11], v[34:35], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[12:13], v[36:37], a[176:191] + v_lshlrev_b32_e32 v0, 1, v92 + ds_read_b128 v[42:45], v0 offset:32768 + v_lshlrev_b32_e32 v0, 1, v93 + ds_read_b128 v[46:49], v0 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_f16 a[208:223], v[10:11], v[42:43], a[208:223] + v_mfma_f32_32x32x8_f16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[14:15], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[14:15], v[26:27], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[14:15], v[34:35], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[14:15], v[42:43], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[16:17], v[44:45], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[18:19], v[2:3], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[20:21], v[4:5], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[18:19], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[20:21], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[18:19], v[34:35], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[20:21], v[36:37], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[18:19], v[42:43], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[20:21], v[44:45], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[22:23], v[2:3], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[24:25], v[4:5], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[22:23], v[26:27], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[24:25], v[28:29], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[22:23], v[34:35], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[24:25], v[36:37], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[22:23], v[42:43], a[240:255] + v_lshlrev_b32_e32 v0, 1, v69 + v_mfma_f32_32x32x8_f16 a[240:255], v[24:25], v[44:45], a[240:255] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[96:111], v[0:1], v[6:7], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[0:1], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[2:3], v[32:33], a[144:159] + v_mfma_f32_32x32x8_f16 a[176:191], v[0:1], v[38:39], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[2:3], v[40:41], a[176:191] + v_mfma_f32_32x32x8_f16 a[208:223], v[0:1], v[46:47], a[208:223] + v_lshlrev_b32_e32 v0, 1, v75 + v_mfma_f32_32x32x8_f16 a[208:223], v[2:3], v[48:49], a[208:223] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[224:239], v[0:1], v[6:7], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[0:1], v[30:31], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_f16 a[160:175], v[0:1], v[38:39], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[0:1], v[46:47], a[128:143] + v_lshlrev_b32_e32 v0, 1, v74 + v_mfma_f32_32x32x8_f16 a[128:143], v[2:3], v[48:49], a[128:143] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[112:127], v[0:1], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[2:3], v[8:9], a[112:127] + v_mfma_f32_32x32x8_f16 a[80:95], v[0:1], v[30:31], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[2:3], v[32:33], a[80:95] + v_mfma_f32_32x32x8_f16 a[64:79], v[0:1], v[38:39], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[2:3], v[40:41], a[64:79] + v_mfma_f32_32x32x8_f16 a[48:63], v[0:1], v[46:47], a[48:63] + v_lshlrev_b32_e32 v0, 1, v71 + v_mfma_f32_32x32x8_f16 a[48:63], v[2:3], v[48:49], a[48:63] + ds_read_b128 v[0:3], v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[32:47], v[0:1], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[2:3], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[0:1], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[2:3], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[0:15], v[0:1], v[38:39], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[2:3], v[40:41], a[0:15] + v_mfma_f32_32x32x8_f16 a[240:255], v[0:1], v[46:47], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[2:3], v[48:49], a[240:255] +.LBB7_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEDF16_NS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDaR + v_accvgpr_read_b32 v143, a96 + v_accvgpr_read_b32 v142, a97 + v_accvgpr_read_b32 v141, a98 + v_accvgpr_read_b32 v140, a99 + v_accvgpr_read_b32 v139, a100 + v_accvgpr_read_b32 v1, a101 + v_accvgpr_read_b32 v18, a102 + v_accvgpr_read_b32 v138, a103 + v_accvgpr_read_b32 v137, a104 + v_accvgpr_read_b32 v136, a105 + v_accvgpr_read_b32 v135, a106 + v_accvgpr_read_b32 v134, a107 + v_accvgpr_read_b32 v133, a108 + v_accvgpr_read_b32 v132, a109 + v_accvgpr_read_b32 v131, a110 + v_accvgpr_read_b32 v130, a111 + v_accvgpr_read_b32 v107, a144 + v_accvgpr_read_b32 v106, a145 + v_accvgpr_read_b32 v105, a146 + v_accvgpr_read_b32 v104, a147 + v_accvgpr_read_b32 v103, a148 + v_accvgpr_read_b32 v102, a149 + v_accvgpr_read_b32 v101, a150 + v_accvgpr_read_b32 v100, a151 + v_accvgpr_read_b32 v99, a152 + v_accvgpr_read_b32 v98, a153 + v_accvgpr_read_b32 v97, a154 + v_accvgpr_read_b32 v96, a155 + v_accvgpr_read_b32 v95, a156 + v_accvgpr_read_b32 v94, a157 + v_accvgpr_read_b32 v93, a158 + v_accvgpr_read_b32 v92, a159 + v_accvgpr_read_b32 v91, a176 + v_accvgpr_read_b32 v90, a177 + v_accvgpr_read_b32 v89, a178 + v_accvgpr_read_b32 v88, a179 + v_accvgpr_read_b32 v87, a180 + v_accvgpr_read_b32 v86, a181 + v_accvgpr_read_b32 v85, a182 + v_accvgpr_read_b32 v84, a183 + v_accvgpr_read_b32 v83, a184 + v_accvgpr_read_b32 v82, a185 + v_accvgpr_read_b32 v81, a186 + v_accvgpr_read_b32 v80, a187 + v_accvgpr_read_b32 v79, a188 + v_accvgpr_read_b32 v78, a189 + v_accvgpr_read_b32 v77, a190 + v_accvgpr_read_b32 v76, a191 + v_accvgpr_read_b32 v75, a208 + v_accvgpr_read_b32 v74, a209 + v_accvgpr_read_b32 v73, a210 + v_accvgpr_read_b32 v72, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v70, a213 + v_accvgpr_read_b32 v69, a214 + v_accvgpr_read_b32 v68, a215 + v_accvgpr_read_b32 v66, a216 + v_accvgpr_read_b32 v65, a217 + v_accvgpr_read_b32 v64, a218 + v_accvgpr_read_b32 v63, a219 + v_accvgpr_read_b32 v62, a220 + v_accvgpr_read_b32 v61, a221 + v_accvgpr_read_b32 v60, a222 + v_accvgpr_read_b32 v19, a223 + v_accvgpr_read_b32 v225, a224 + v_accvgpr_read_b32 v224, a225 + v_accvgpr_read_b32 v223, a226 + v_accvgpr_read_b32 v222, a227 + v_accvgpr_read_b32 v221, a228 + v_accvgpr_read_b32 v220, a229 + v_accvgpr_read_b32 v219, a230 + v_accvgpr_read_b32 v218, a231 + v_accvgpr_read_b32 v217, a232 + v_accvgpr_read_b32 v216, a233 + v_accvgpr_read_b32 v215, a234 + v_accvgpr_read_b32 v214, a235 + v_accvgpr_read_b32 v213, a236 + v_accvgpr_read_b32 v212, a237 + v_accvgpr_read_b32 v211, a238 + v_accvgpr_read_b32 v210, a239 + v_accvgpr_read_b32 v177, a192 + v_accvgpr_read_b32 v176, a193 + v_accvgpr_read_b32 v175, a194 + v_accvgpr_read_b32 v174, a195 + v_accvgpr_read_b32 v173, a196 + v_accvgpr_read_b32 v172, a197 + v_accvgpr_read_b32 v171, a198 + v_accvgpr_read_b32 v170, a199 + v_accvgpr_read_b32 v169, a200 + v_accvgpr_read_b32 v168, a201 + v_accvgpr_read_b32 v167, a202 + v_accvgpr_read_b32 v166, a203 + v_accvgpr_read_b32 v165, a204 + v_accvgpr_read_b32 v164, a205 + v_accvgpr_read_b32 v163, a206 + v_accvgpr_read_b32 v162, a207 + v_accvgpr_read_b32 v161, a160 + v_accvgpr_read_b32 v160, a161 + v_accvgpr_read_b32 v159, a162 + v_accvgpr_read_b32 v158, a163 + v_accvgpr_read_b32 v157, a164 + v_accvgpr_read_b32 v156, a165 + v_accvgpr_read_b32 v155, a166 + v_accvgpr_read_b32 v154, a167 + v_accvgpr_read_b32 v153, a168 + v_accvgpr_read_b32 v152, a169 + v_accvgpr_read_b32 v151, a170 + v_accvgpr_read_b32 v150, a171 + v_accvgpr_read_b32 v149, a172 + v_accvgpr_read_b32 v148, a173 + v_accvgpr_read_b32 v145, a174 + v_accvgpr_read_b32 v144, a175 + v_accvgpr_read_b32 v146, a128 + v_accvgpr_read_b32 v147, a129 + v_accvgpr_read_b32 v129, a130 + v_accvgpr_read_b32 v128, a131 + v_accvgpr_read_b32 v127, a132 + v_accvgpr_read_b32 v126, a133 + v_accvgpr_read_b32 v125, a134 + v_accvgpr_read_b32 v124, a135 + v_accvgpr_read_b32 v123, a136 + v_accvgpr_read_b32 v122, a137 + v_accvgpr_read_b32 v121, a138 + v_accvgpr_read_b32 v120, a139 + v_accvgpr_read_b32 v119, a140 + v_accvgpr_read_b32 v118, a141 + v_accvgpr_read_b32 v117, a142 + v_accvgpr_read_b32 v116, a143 + v_accvgpr_mov_b32 a111, a112 + v_accvgpr_mov_b32 a110, a113 + v_accvgpr_mov_b32 a109, a114 + v_accvgpr_mov_b32 a108, a115 + v_accvgpr_mov_b32 a107, a116 + v_accvgpr_mov_b32 a106, a117 + v_accvgpr_mov_b32 a105, a118 + v_accvgpr_mov_b32 a104, a119 + v_accvgpr_mov_b32 a103, a120 + v_accvgpr_mov_b32 a102, a121 + v_accvgpr_mov_b32 a101, a122 + v_accvgpr_mov_b32 a100, a123 + v_accvgpr_mov_b32 a99, a124 + v_accvgpr_mov_b32 a98, a125 + v_accvgpr_mov_b32 a97, a126 + v_accvgpr_mov_b32 a96, a127 + v_accvgpr_read_b32 v59, a80 + v_accvgpr_read_b32 v58, a81 + v_accvgpr_read_b32 v57, a82 + v_accvgpr_read_b32 v56, a83 + v_accvgpr_read_b32 v55, a84 + v_accvgpr_read_b32 v54, a85 + v_accvgpr_read_b32 v53, a86 + v_accvgpr_read_b32 v52, a87 + v_accvgpr_read_b32 v51, a88 + v_accvgpr_read_b32 v50, a89 + v_accvgpr_read_b32 v25, a90 + v_accvgpr_read_b32 v24, a91 + v_accvgpr_read_b32 v23, a92 + v_accvgpr_read_b32 v22, a93 + v_accvgpr_read_b32 v21, a94 + v_accvgpr_read_b32 v20, a95 + v_accvgpr_read_b32 v115, a64 + v_accvgpr_read_b32 v114, a65 + v_accvgpr_read_b32 v113, a66 + v_accvgpr_read_b32 v112, a67 + v_accvgpr_read_b32 v111, a68 + v_accvgpr_read_b32 v110, a69 + v_accvgpr_read_b32 v109, a70 + v_accvgpr_read_b32 v108, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v209, a48 + v_accvgpr_read_b32 v208, a49 + v_accvgpr_read_b32 v207, a50 + v_accvgpr_read_b32 v206, a51 + v_accvgpr_read_b32 v205, a52 + v_accvgpr_read_b32 v204, a53 + v_accvgpr_read_b32 v203, a54 + v_accvgpr_read_b32 v202, a55 + v_accvgpr_read_b32 v201, a56 + v_accvgpr_read_b32 v200, a57 + v_accvgpr_read_b32 v199, a58 + v_accvgpr_read_b32 v198, a59 + v_accvgpr_read_b32 v197, a60 + v_accvgpr_read_b32 v196, a61 + v_accvgpr_read_b32 v195, a62 + v_accvgpr_read_b32 v194, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v193, a0 + v_accvgpr_read_b32 v192, a1 + v_accvgpr_read_b32 v191, a2 + v_accvgpr_read_b32 v190, a3 + v_accvgpr_read_b32 v189, a4 + v_accvgpr_read_b32 v188, a5 + v_accvgpr_read_b32 v187, a6 + v_accvgpr_read_b32 v186, a7 + v_accvgpr_read_b32 v185, a8 + v_accvgpr_read_b32 v184, a9 + v_accvgpr_read_b32 v183, a10 + v_accvgpr_read_b32 v182, a11 + v_accvgpr_read_b32 v181, a12 + v_accvgpr_read_b32 v180, a13 + v_accvgpr_read_b32 v179, a14 + v_accvgpr_read_b32 v178, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v226 + v_lshrrev_b32_e32 v0, 3, v226 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v130, v130 + v_cvt_f16_f32_e32 v132, v225 + v_cvt_f16_f32_e32 v229, v224 + v_cvt_f16_f32_e32 v230, v223 + v_cvt_f16_f32_e32 v231, v222 + v_cvt_f16_f32_e32 v232, v221 + v_cvt_f16_f32_e32 v233, v220 + v_cvt_f16_f32_e32 v234, v219 + v_cvt_f16_f32_e32 v235, v218 + v_cvt_f16_f32_e32 v236, v217 + v_cvt_f16_f32_e32 v237, v216 + v_cvt_f16_f32_e32 v238, v215 + v_cvt_f16_f32_e32 v239, v214 + v_cvt_f16_f32_e32 v240, v213 + v_cvt_f16_f32_e32 v241, v212 + v_cvt_f16_f32_e32 v242, v211 + v_cvt_f16_f32_e32 v243, v210 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v92, v92 + v_cvt_f16_f32_e32 v210, v177 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v225, v162 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v177, v76 + v_cvt_f16_f32_e32 v76, v161 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v133, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v19 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v129 + v_cvt_f16_f32_e32 v149, v128 + v_cvt_f16_f32_e32 v150, v127 + v_cvt_f16_f32_e32 v151, v126 + v_cvt_f16_f32_e32 v152, v125 + v_cvt_f16_f32_e32 v153, v124 + v_cvt_f16_f32_e32 v154, v123 + v_cvt_f16_f32_e32 v155, v122 + v_cvt_f16_f32_e32 v156, v121 + v_cvt_f16_f32_e32 v157, v120 + v_cvt_f16_f32_e32 v158, v119 + v_cvt_f16_f32_e32 v159, v118 + v_cvt_f16_f32_e32 v160, v117 + v_cvt_f16_f32_e32 v161, v116 + v_cvt_f16_f32_e32 v209, v209 + v_cvt_f16_f32_e32 v19, v208 + v_accvgpr_write_b32 a0, v19 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v72, v205 + v_cvt_f16_f32_e32 v71, v204 + v_cvt_f16_f32_e32 v70, v203 + v_cvt_f16_f32_e32 v69, v202 + v_cvt_f16_f32_e32 v68, v201 + v_cvt_f16_f32_e32 v66, v200 + v_cvt_f16_f32_e32 v60, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v3, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v19, 1, v67 + v_cvt_f16_f32_e32 v194, v115 + v_cvt_f16_f32_e32 v67, v114 + v_cvt_f16_f32_e32 v195, v113 + v_cvt_f16_f32_e32 v196, v112 + v_cvt_f16_f32_e32 v197, v111 + v_cvt_f16_f32_e32 v198, v110 + v_cvt_f16_f32_e32 v199, v109 + v_cvt_f16_f32_e32 v200, v108 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v48, v43 + v_cvt_f16_f32_e32 v49, v42 + v_cvt_f16_f32_e32 v108, v193 + v_cvt_f16_f32_e32 v109, v192 + v_cvt_f16_f32_e32 v110, v191 + v_cvt_f16_f32_e32 v111, v190 + v_cvt_f16_f32_e32 v112, v189 + v_cvt_f16_f32_e32 v113, v188 + v_cvt_f16_f32_e32 v114, v187 + v_cvt_f16_f32_e32 v115, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v43, v58 + v_cvt_f16_f32_e32 v4, v57 + v_cvt_f16_f32_e32 v5, v56 + v_cvt_f16_f32_e32 v6, v55 + v_cvt_f16_f32_e32 v7, v54 + v_cvt_f16_f32_e32 v8, v53 + v_cvt_f16_f32_e32 v9, v52 + v_cvt_f16_f32_e32 v10, v51 + v_cvt_f16_f32_e32 v11, v50 + v_cvt_f16_f32_e32 v12, v25 + v_cvt_f16_f32_e32 v13, v24 + v_cvt_f16_f32_e32 v14, v23 + v_cvt_f16_f32_e32 v15, v22 + v_cvt_f16_f32_e32 v16, v21 + v_cvt_f16_f32_e32 v17, v20 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v31, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v226 + v_lshrrev_b32_e32 v20, 1, v226 + s_cbranch_scc1 .LBB7_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB7_14 +.LBB7_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESE_SE_Li1EEEDF16_NS_12element_wise11PassThroughESH_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SO_SE_SH_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB7_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v23, s5, v0 + v_lshl_add_u32 v23, v23, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v1 offset:1152 + ds_write_b16 v23, v18 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v130 offset:3456 + ds_write_b16 v23, v132 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 60, v20 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v32, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v32, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v32 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v41, v40, s16 + v_add_u32_e32 v203, v41, v25 + v_lshlrev_b32_e32 v204, 1, v203 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v203 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v92 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v203, 64, v25 + v_add_u32_e32 v204, v41, v203 + v_lshlrev_b32_e32 v205, 1, v204 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v204 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v177 offset:3456 + ds_write_b16 v23, v76 offset:8192 + ds_write_b16 v23, v77 offset:8320 + ds_write_b16 v23, v78 offset:8448 + ds_write_b16 v23, v79 offset:8576 + ds_write_b16 v23, v80 offset:9216 + ds_write_b16 v23, v81 offset:9344 + ds_write_b16 v23, v82 offset:9472 + ds_write_b16 v23, v83 offset:9600 + ds_write_b16 v23, v84 offset:10240 + ds_write_b16 v23, v85 offset:10368 + ds_write_b16 v23, v86 offset:10496 + ds_write_b16 v23, v87 offset:10624 + ds_write_b16 v23, v88 offset:11264 + ds_write_b16 v23, v89 offset:11392 + ds_write_b16 v23, v90 offset:11520 + ds_write_b16 v23, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v204, 0x80, v25 + v_add_u32_e32 v205, v41, v204 + v_mov_b32_e32 v226, v206 + v_lshlrev_b32_e32 v206, 1, v205 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v205 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v133 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v205, 0xc0, v25 + v_add_u32_e32 v41, v41, v205 + v_lshlrev_b32_e32 v206, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_mov_b32_e32 v206, v226 + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v209 + ds_write_b16 v23, a0 offset:128 + ds_write_b16 v23, v207 offset:256 + ds_write_b16 v23, v226 offset:384 + ds_write_b16 v23, v72 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v66 offset:2176 + ds_write_b16 v23, v60 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v3 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, 0x80, v40 + v_mul_lo_u32 v40, v32, s16 + v_add_u32_e32 v41, v40, v205 + v_lshlrev_b32_e32 v205, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v194 + ds_write_b16 v23, v67 offset:128 + ds_write_b16 v23, v195 offset:256 + ds_write_b16 v23, v196 offset:384 + ds_write_b16 v23, v197 offset:1024 + ds_write_b16 v23, v198 offset:1152 + ds_write_b16 v23, v199 offset:1280 + ds_write_b16 v23, v200 offset:1408 + ds_write_b16 v23, v201 offset:2048 + ds_write_b16 v23, v202 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v48 offset:3328 + ds_write_b16 v23, v49 offset:3456 + ds_write_b16 v23, v108 offset:8192 + ds_write_b16 v23, v109 offset:8320 + ds_write_b16 v23, v110 offset:8448 + ds_write_b16 v23, v111 offset:8576 + ds_write_b16 v23, v112 offset:9216 + ds_write_b16 v23, v113 offset:9344 + ds_write_b16 v23, v114 offset:9472 + ds_write_b16 v23, v115 offset:9600 + ds_write_b16 v23, v185 offset:10240 + ds_write_b16 v23, v184 offset:10368 + ds_write_b16 v23, v183 offset:10496 + ds_write_b16 v23, v182 offset:10624 + ds_write_b16 v23, v181 offset:11264 + ds_write_b16 v23, v180 offset:11392 + ds_write_b16 v23, v179 offset:11520 + ds_write_b16 v23, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v204 + v_lshlrev_b32_e32 v204, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v43 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v31 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v41, v40, v203 + v_lshlrev_b32_e32 v203, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v203, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v203, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v203, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v203, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a111 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a110 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a109 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a108 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a107 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a106 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a105 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a104 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v40, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB7_12 +.LBB7_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_add_u32 v0, v0, 7, v19 + s_and_b32 s2, s2, 64 + v_add3_u32 v40, v0, v22, s2 + ds_write_b16 v40, v251 + ds_write_b16 v40, v252 offset:128 + ds_write_b16 v40, v253 offset:256 + ds_write_b16 v40, v254 offset:384 + ds_write_b16 v40, v255 offset:1024 + ds_write_b16 v40, v1 offset:1152 + ds_write_b16 v40, v18 offset:1280 + ds_write_b16 v40, v244 offset:1408 + ds_write_b16 v40, v245 offset:2048 + ds_write_b16 v40, v246 offset:2176 + ds_write_b16 v40, v247 offset:2304 + ds_write_b16 v40, v248 offset:2432 + ds_write_b16 v40, v249 offset:3072 + ds_write_b16 v40, v250 offset:3200 + ds_write_b16 v40, v131 offset:3328 + ds_write_b16 v40, v130 offset:3456 + ds_write_b16 v40, v132 offset:8192 + ds_write_b16 v40, v229 offset:8320 + ds_write_b16 v40, v230 offset:8448 + ds_write_b16 v40, v231 offset:8576 + ds_write_b16 v40, v232 offset:9216 + ds_write_b16 v40, v233 offset:9344 + ds_write_b16 v40, v234 offset:9472 + ds_write_b16 v40, v235 offset:9600 + ds_write_b16 v40, v236 offset:10240 + ds_write_b16 v40, v237 offset:10368 + ds_write_b16 v40, v238 offset:10496 + ds_write_b16 v40, v239 offset:10624 + ds_write_b16 v40, v240 offset:11264 + ds_write_b16 v40, v241 offset:11392 + ds_write_b16 v40, v242 offset:11520 + ds_write_b16 v40, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v20 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v41, v0, 1, v18 + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_add_u32_e32 v131, s18, v1 + v_or_b32_e32 v186, s19, v0 + v_mul_lo_u32 v0, v131, s16 + v_add_u32_e32 v1, v0, v186 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v187, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v187, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v107 + ds_write_b16 v40, v106 offset:128 + ds_write_b16 v40, v105 offset:256 + ds_write_b16 v40, v104 offset:384 + ds_write_b16 v40, v103 offset:1024 + ds_write_b16 v40, v102 offset:1152 + ds_write_b16 v40, v101 offset:1280 + ds_write_b16 v40, v100 offset:1408 + ds_write_b16 v40, v99 offset:2048 + ds_write_b16 v40, v98 offset:2176 + ds_write_b16 v40, v97 offset:2304 + ds_write_b16 v40, v96 offset:2432 + ds_write_b16 v40, v95 offset:3072 + ds_write_b16 v40, v94 offset:3200 + ds_write_b16 v40, v93 offset:3328 + ds_write_b16 v40, v92 offset:3456 + ds_write_b16 v40, v210 offset:8192 + ds_write_b16 v40, v211 offset:8320 + ds_write_b16 v40, v212 offset:8448 + ds_write_b16 v40, v213 offset:8576 + ds_write_b16 v40, v214 offset:9216 + ds_write_b16 v40, v215 offset:9344 + ds_write_b16 v40, v216 offset:9472 + ds_write_b16 v40, v217 offset:9600 + ds_write_b16 v40, v218 offset:10240 + ds_write_b16 v40, v219 offset:10368 + ds_write_b16 v40, v220 offset:10496 + ds_write_b16 v40, v221 offset:10624 + ds_write_b16 v40, v222 offset:11264 + ds_write_b16 v40, v223 offset:11392 + ds_write_b16 v40, v224 offset:11520 + ds_write_b16 v40, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v92, 64, v186 + v_add_u32_e32 v1, v0, v92 + v_lshlrev_b32_e32 v93, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v93, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v162 + ds_write_b16 v40, v163 offset:128 + ds_write_b16 v40, v164 offset:256 + ds_write_b16 v40, v165 offset:384 + ds_write_b16 v40, v166 offset:1024 + ds_write_b16 v40, v167 offset:1152 + ds_write_b16 v40, v168 offset:1280 + ds_write_b16 v40, v169 offset:1408 + ds_write_b16 v40, v170 offset:2048 + ds_write_b16 v40, v171 offset:2176 + ds_write_b16 v40, v172 offset:2304 + ds_write_b16 v40, v173 offset:2432 + ds_write_b16 v40, v174 offset:3072 + ds_write_b16 v40, v175 offset:3200 + ds_write_b16 v40, v176 offset:3328 + ds_write_b16 v40, v177 offset:3456 + ds_write_b16 v40, v76 offset:8192 + ds_write_b16 v40, v77 offset:8320 + ds_write_b16 v40, v78 offset:8448 + ds_write_b16 v40, v79 offset:8576 + ds_write_b16 v40, v80 offset:9216 + ds_write_b16 v40, v81 offset:9344 + ds_write_b16 v40, v82 offset:9472 + ds_write_b16 v40, v83 offset:9600 + ds_write_b16 v40, v84 offset:10240 + ds_write_b16 v40, v85 offset:10368 + ds_write_b16 v40, v86 offset:10496 + ds_write_b16 v40, v87 offset:10624 + ds_write_b16 v40, v88 offset:11264 + ds_write_b16 v40, v89 offset:11392 + ds_write_b16 v40, v90 offset:11520 + ds_write_b16 v40, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v76, 0x80, v186 + v_add_u32_e32 v1, v0, v76 + v_lshlrev_b32_e32 v77, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v75 + ds_write_b16 v40, v74 offset:128 + ds_write_b16 v40, v73 offset:256 + ds_write_b16 v40, v133 offset:384 + ds_write_b16 v40, v134 offset:1024 + ds_write_b16 v40, v135 offset:1152 + ds_write_b16 v40, v136 offset:1280 + ds_write_b16 v40, v137 offset:1408 + ds_write_b16 v40, v138 offset:2048 + ds_write_b16 v40, v139 offset:2176 + ds_write_b16 v40, v140 offset:2304 + ds_write_b16 v40, v141 offset:2432 + ds_write_b16 v40, v142 offset:3072 + ds_write_b16 v40, v143 offset:3200 + ds_write_b16 v40, v144 offset:3328 + ds_write_b16 v40, v145 offset:3456 + ds_write_b16 v40, v146 offset:8192 + ds_write_b16 v40, v147 offset:8320 + ds_write_b16 v40, v148 offset:8448 + ds_write_b16 v40, v149 offset:8576 + ds_write_b16 v40, v150 offset:9216 + ds_write_b16 v40, v151 offset:9344 + ds_write_b16 v40, v152 offset:9472 + ds_write_b16 v40, v153 offset:9600 + ds_write_b16 v40, v154 offset:10240 + ds_write_b16 v40, v155 offset:10368 + ds_write_b16 v40, v156 offset:10496 + ds_write_b16 v40, v157 offset:10624 + ds_write_b16 v40, v158 offset:11264 + ds_write_b16 v40, v159 offset:11392 + ds_write_b16 v40, v160 offset:11520 + ds_write_b16 v40, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v41 + ds_read_b128 v[22:25], v41 offset:128 + ds_read_b128 v[32:35], v41 offset:256 + ds_read_b128 v[36:39], v41 offset:384 + v_or_b32_e32 v74, 0xc0, v186 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v209 + ds_write_b16 v40, a0 offset:128 + ds_write_b16 v40, v207 offset:256 + ds_write_b16 v40, v206 offset:384 + ds_write_b16 v40, v72 offset:1024 + ds_write_b16 v40, v71 offset:1152 + ds_write_b16 v40, v70 offset:1280 + ds_write_b16 v40, v69 offset:1408 + ds_write_b16 v40, v68 offset:2048 + ds_write_b16 v40, v66 offset:2176 + ds_write_b16 v40, v60 offset:2304 + ds_write_b16 v40, v61 offset:2432 + ds_write_b16 v40, v62 offset:3072 + ds_write_b16 v40, v63 offset:3200 + ds_write_b16 v40, v64 offset:3328 + ds_write_b16 v40, v65 offset:3456 + ds_write_b16 v40, v2 offset:8192 + ds_write_b16 v40, v3 offset:8320 + ds_write_b16 v40, v116 offset:8448 + ds_write_b16 v40, v117 offset:8576 + ds_write_b16 v40, v118 offset:9216 + ds_write_b16 v40, v119 offset:9344 + ds_write_b16 v40, v120 offset:9472 + ds_write_b16 v40, v121 offset:9600 + ds_write_b16 v40, v122 offset:10240 + ds_write_b16 v40, v123 offset:10368 + ds_write_b16 v40, v124 offset:10496 + ds_write_b16 v40, v125 offset:10624 + ds_write_b16 v40, v126 offset:11264 + ds_write_b16 v40, v127 offset:11392 + ds_write_b16 v40, v128 offset:11520 + ds_write_b16 v40, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[18:21], v41 offset:128 + ds_read_b128 v[22:25], v41 offset:256 + ds_read_b128 v[32:35], v41 offset:384 + v_add_u32_e32 v36, 0x80, v131 + v_mul_lo_u32 v36, v36, s16 + v_add_u32_e32 v37, v36, v74 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v194 + ds_write_b16 v40, v67 offset:128 + ds_write_b16 v40, v195 offset:256 + ds_write_b16 v40, v196 offset:384 + ds_write_b16 v40, v197 offset:1024 + ds_write_b16 v40, v198 offset:1152 + ds_write_b16 v40, v199 offset:1280 + ds_write_b16 v40, v200 offset:1408 + ds_write_b16 v40, v201 offset:2048 + ds_write_b16 v40, v202 offset:2176 + ds_write_b16 v40, v47 offset:2304 + ds_write_b16 v40, v46 offset:2432 + ds_write_b16 v40, v45 offset:3072 + ds_write_b16 v40, v44 offset:3200 + ds_write_b16 v40, v48 offset:3328 + ds_write_b16 v40, v49 offset:3456 + ds_write_b16 v40, v108 offset:8192 + ds_write_b16 v40, v109 offset:8320 + ds_write_b16 v40, v110 offset:8448 + ds_write_b16 v40, v111 offset:8576 + ds_write_b16 v40, v112 offset:9216 + ds_write_b16 v40, v113 offset:9344 + ds_write_b16 v40, v114 offset:9472 + ds_write_b16 v40, v115 offset:9600 + ds_write_b16 v40, v185 offset:10240 + ds_write_b16 v40, v184 offset:10368 + ds_write_b16 v40, v183 offset:10496 + ds_write_b16 v40, v182 offset:10624 + ds_write_b16 v40, v181 offset:11264 + ds_write_b16 v40, v180 offset:11392 + ds_write_b16 v40, v179 offset:11520 + ds_write_b16 v40, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[18:21], v41 offset:128 + ds_read_b128 v[22:25], v41 offset:256 + ds_read_b128 v[32:35], v41 offset:384 + v_add_u32_e32 v37, v36, v76 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v40, v42 + ds_write_b16 v40, v43 offset:128 + ds_write_b16 v40, v4 offset:256 + ds_write_b16 v40, v5 offset:384 + ds_write_b16 v40, v6 offset:1024 + ds_write_b16 v40, v7 offset:1152 + ds_write_b16 v40, v8 offset:1280 + ds_write_b16 v40, v9 offset:1408 + ds_write_b16 v40, v10 offset:2048 + ds_write_b16 v40, v11 offset:2176 + ds_write_b16 v40, v12 offset:2304 + ds_write_b16 v40, v13 offset:2432 + ds_write_b16 v40, v14 offset:3072 + ds_write_b16 v40, v15 offset:3200 + ds_write_b16 v40, v16 offset:3328 + ds_write_b16 v40, v17 offset:3456 + ds_write_b16 v40, v50 offset:8192 + ds_write_b16 v40, v51 offset:8320 + ds_write_b16 v40, v52 offset:8448 + ds_write_b16 v40, v53 offset:8576 + ds_write_b16 v40, v54 offset:9216 + ds_write_b16 v40, v55 offset:9344 + ds_write_b16 v40, v56 offset:9472 + ds_write_b16 v40, v57 offset:9600 + ds_write_b16 v40, v58 offset:10240 + ds_write_b16 v40, v59 offset:10368 + ds_write_b16 v40, v31 offset:10496 + ds_write_b16 v40, v30 offset:10624 + ds_write_b16 v40, v29 offset:11264 + ds_write_b16 v40, v28 offset:11392 + ds_write_b16 v40, v27 offset:11520 + ds_write_b16 v40, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v36, v92 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a111 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a110 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a109 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a108 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a107 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a106 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a105 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a104 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a32 + v_cvt_f16_f32_e32 v31, v31 + ds_write_b16 v40, v0 + ds_write_b16 v40, v1 offset:128 + ds_write_b16 v40, v2 offset:256 + ds_write_b16 v40, v3 offset:384 + ds_write_b16 v40, v4 offset:1024 + ds_write_b16 v40, v5 offset:1152 + ds_write_b16 v40, v6 offset:1280 + ds_write_b16 v40, v7 offset:1408 + ds_write_b16 v40, v8 offset:2048 + ds_write_b16 v40, v9 offset:2176 + ds_write_b16 v40, v10 offset:2304 + ds_write_b16 v40, v11 offset:2432 + ds_write_b16 v40, v12 offset:3072 + ds_write_b16 v40, v13 offset:3200 + ds_write_b16 v40, v14 offset:3328 + ds_write_b16 v40, v15 offset:3456 + ds_write_b16 v40, v16 offset:8192 + ds_write_b16 v40, v17 offset:8320 + ds_write_b16 v40, v18 offset:8448 + ds_write_b16 v40, v19 offset:8576 + ds_write_b16 v40, v20 offset:9216 + ds_write_b16 v40, v21 offset:9344 + ds_write_b16 v40, v22 offset:9472 + ds_write_b16 v40, v23 offset:9600 + ds_write_b16 v40, v24 offset:10240 + ds_write_b16 v40, v25 offset:10368 + ds_write_b16 v40, v26 offset:10496 + ds_write_b16 v40, v27 offset:10624 + ds_write_b16 v40, v28 offset:11264 + ds_write_b16 v40, v29 offset:11392 + ds_write_b16 v40, v30 offset:11520 + ds_write_b16 v40, v31 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v41 + ds_read_b128 v[4:7], v41 offset:128 + ds_read_b128 v[8:11], v41 offset:256 + ds_read_b128 v[12:15], v41 offset:384 + v_add_u32_e32 v16, v36, v186 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end7: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end7-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 28692 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB8_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB8_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s8 + v_mov_b32_e32 v3, s9 + v_mul_lo_u32 v4, v6, s7 + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v0 +.LBB8_3: ; =>This Inner Loop Header: Depth=1 + global_load_ushort v7, v[2:3], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], v[4:5], 1, s[10:11] + global_load_ushort v5, v[8:9], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v1, v7, v5, v1 op_sel_hi:[1,1,0] + s_cbranch_scc0 .LBB8_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB8_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB8_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end8: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end8-_ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_DF16_fDF16_NS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 432 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v1, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v1 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s2, s12, s2 + s_mul_i32 s12, s2, s7 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[12:13], s[12:13], 1 + s_add_u32 s8, s8, s12 + s_addc_u32 s9, s9, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s10, s4, -1 + s_add_u32 s3, s10, s3 + s_add_u32 s22, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s20, s3 + s_add_u32 s2, s2, s3 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v1 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v1, -1, v1 + v_and_b32_e32 v72, 31, v1 + v_lshrrev_b32_e32 v2, 5, v1 + v_and_b32_e32 v69, 7, v1 + v_lshrrev_b32_e32 v3, 2, v1 + s_cbranch_scc0 .LBB9_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + s_lshr_b32 s24, s15, 2 + v_lshlrev_b32_e32 v5, 3, v2 + s_and_b32 s23, s24, 0x3ffffff0 + v_lshl_or_b32 v4, v72, 3, s18 + v_add_u32_e32 v6, s23, v5 + v_mad_u64_u32 v[6:7], s[10:11], v6, s7, v[4:5] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v4, 1, v6 + v_add_u32_e32 v6, s7, v6 + v_lshlrev_b32_e32 v7, 1, v6 + buffer_load_dwordx4 v[10:13], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v6 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v7, 1, v4 + buffer_load_dwordx4 v[18:21], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[22:25], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v7, 1, v4 + buffer_load_dwordx4 v[26:29], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[30:33], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_lshl_u32 v4, v4, s7, 1 + buffer_load_dwordx4 v[34:37], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v6, 12, v2 + v_lshlrev_b32_e32 v66, 3, v69 + v_and_b32_e32 v7, 0x78, v1 + v_xor_b32_e32 v4, v2, v69 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s25, 0x1000504 + s_mov_b32 s26, 0x3020706 + v_lshl_or_b32 v9, v69, 8, v6 + s_and_b32 s10, s15, 0xffffffc0 + s_lshr_b32 s27, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s24, 0x3fffffe0 + v_add_u32_e32 v7, s10, v7 + v_and_or_b32 v67, s27, 32, v72 + v_or_b32_e32 v6, s11, v72 + v_add_u32_e32 v42, s19, v7 + v_lshrrev_b32_e32 v8, 3, v6 + v_mad_u64_u32 v[42:43], s[10:11], v42, s20, v[66:67] + v_xor_b32_e32 v68, v8, v69 + v_lshlrev_b32_e32 v50, 1, v42 + v_add_u32_e32 v42, s20, v42 + v_lshl_add_u32 v9, v68, 3, v9 + v_lshlrev_b32_e32 v51, 1, v42 + v_add_u32_e32 v52, s20, v42 + buffer_load_dwordx4 v[42:45], v50, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v51, s[12:15], 0 offen + v_lshlrev_b32_e32 v58, 1, v52 + v_add_u32_e32 v50, s20, v52 + v_lshlrev_b32_e32 v59, 1, v50 + v_add_u32_e32 v60, s20, v50 + buffer_load_dwordx4 v[50:53], v58, s[12:15], 0 offen + buffer_load_dwordx4 v[54:57], v59, s[12:15], 0 offen + v_lshlrev_b32_e32 v70, 1, v60 + v_add_u32_e32 v58, s20, v60 + v_lshlrev_b32_e32 v71, 1, v58 + v_add_u32_e32 v73, s20, v58 + buffer_load_dwordx4 v[58:61], v70, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v71, s[12:15], 0 offen + v_lshlrev_b32_e32 v70, 1, v73 + v_add_lshl_u32 v71, v73, s20, 1 + buffer_load_dwordx4 v[74:77], v70, s[12:15], 0 offen + buffer_load_dwordx4 v[78:81], v71, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v82, v10, v14, s25 + v_perm_b32 v86, v10, v14, s26 + v_perm_b32 v90, v11, v15, s25 + v_perm_b32 v94, v11, v15, s26 + v_perm_b32 v98, v12, v16, s25 + v_perm_b32 v102, v12, v16, s26 + s_waitcnt vmcnt(12) + v_perm_b32 v83, v18, v22, s25 + v_perm_b32 v87, v18, v22, s26 + v_perm_b32 v91, v19, v23, s25 + v_perm_b32 v95, v19, v23, s26 + s_waitcnt vmcnt(10) + v_perm_b32 v84, v26, v30, s25 + v_perm_b32 v88, v26, v30, s26 + v_perm_b32 v92, v27, v31, s25 + v_perm_b32 v96, v27, v31, s26 + s_waitcnt vmcnt(8) + v_perm_b32 v85, v34, v38, s25 + v_perm_b32 v89, v34, v38, s26 + v_perm_b32 v93, v35, v39, s25 + v_perm_b32 v97, v35, v39, s26 + v_perm_b32 v99, v20, v24, s25 + v_perm_b32 v103, v20, v24, s26 + v_perm_b32 v100, v28, v32, s25 + v_perm_b32 v104, v28, v32, s26 + v_perm_b32 v101, v36, v40, s25 + v_perm_b32 v105, v36, v40, s26 + v_perm_b32 v10, v13, v17, s25 + v_perm_b32 v14, v13, v17, s26 + v_perm_b32 v11, v21, v25, s25 + v_perm_b32 v15, v21, v25, s26 + v_perm_b32 v12, v29, v33, s25 + v_perm_b32 v16, v29, v33, s26 + v_perm_b32 v13, v37, v41, s25 + v_perm_b32 v17, v37, v41, s26 + v_and_b32_e32 v18, 24, v3 + v_add_u32_e32 v18, s23, v18 + v_lshrrev_b32_e32 v19, 2, v18 + v_and_b32_e32 v19, 24, v19 + v_xor_b32_e32 v20, v19, v72 + v_lshlrev_b32_e32 v21, 9, v18 + v_and_b32_e32 v21, 0x3000, v21 + v_lshlrev_b32_e32 v18, 6, v18 + v_and_b32_e32 v18, 0xfffff800, v18 + v_add_u32_e32 v18, v18, v21 + v_lshl_or_b32 v18, v20, 3, v18 + v_lshlrev_b32_e32 v21, 1, v18 + ds_write_b128 v21, v[82:85] + v_or_b32_e32 v22, 1, v19 + v_xor_b32_e32 v22, v22, v72 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v23, 3, v20 + v_or_b32_e32 v24, 2, v19 + v_xor_b32_e32 v24, v24, v72 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v25, 3, v22 + v_add3_u32 v18, v23, v18, v25 + v_lshl_add_u32 v20, v20, 4, v21 + ds_write_b128 v20, v[86:89] offset:512 + v_or_b32_e32 v21, 3, v19 + v_xor_b32_e32 v21, v21, v72 + v_sub_u32_e32 v23, v21, v24 + v_lshlrev_b32_e32 v24, 3, v23 + v_or_b32_e32 v25, 4, v19 + v_xor_b32_e32 v25, v25, v72 + v_sub_u32_e32 v21, v25, v21 + v_lshlrev_b32_e32 v26, 3, v21 + v_add3_u32 v18, v18, v24, v26 + v_lshlrev_b32_e32 v22, 4, v22 + s_movk_i32 s10, 0x200 + v_add3_u32 v20, v20, s10, v22 + ds_write_b128 v20, v[90:93] offset:512 + v_or_b32_e32 v22, 5, v19 + v_xor_b32_e32 v22, v22, v72 + v_sub_u32_e32 v24, v22, v25 + v_lshlrev_b32_e32 v25, 3, v24 + v_or_b32_e32 v26, 6, v19 + v_xor_b32_e32 v26, v26, v72 + v_sub_u32_e32 v22, v26, v22 + v_lshlrev_b32_e32 v27, 3, v22 + v_add3_u32 v18, v18, v25, v27 + v_lshlrev_b32_e32 v23, 4, v23 + v_add3_u32 v20, v20, s10, v23 + ds_write_b128 v20, v[94:97] offset:512 + v_or_b32_e32 v19, 7, v19 + v_xor_b32_e32 v19, v19, v72 + v_sub_u32_e32 v19, v19, v26 + v_lshlrev_b32_e32 v19, 4, v19 + v_lshl_add_u32 v18, v18, 1, v19 + v_lshlrev_b32_e32 v19, 4, v21 + v_add3_u32 v19, v20, s10, v19 + ds_write_b128 v19, v[98:101] offset:512 + v_lshlrev_b32_e32 v20, 4, v24 + v_add3_u32 v19, v19, s10, v20 + ds_write_b128 v19, v[102:105] offset:512 + v_lshlrev_b32_e32 v20, 4, v22 + v_add3_u32 v19, v19, s10, v20 + ds_write_b128 v19, v[10:13] offset:512 + ds_write_b128 v18, v[14:17] offset:3584 + v_lshl_or_b32 v10, v7, 6, v66 + v_lshlrev_b32_e32 v11, 1, v10 + s_waitcnt vmcnt(7) + ds_write_b128 v11, v[42:45] offset:32768 + v_or_b32_e32 v12, 1, v7 + v_ashrrev_i32_e32 v13, 31, v7 + v_lshrrev_b32_e32 v13, 29, v13 + v_add_u32_e32 v14, v12, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v12, v12, v14 + v_xor_b32_e32 v12, v12, v69 + v_sub_u32_e32 v14, v12, v69 + v_lshl_add_u32 v10, v14, 3, v10 + v_lshl_add_u32 v11, v14, 4, v11 + s_waitcnt vmcnt(6) + ds_write_b128 v11, v[46:49] offset:32896 + v_or_b32_e32 v11, 2, v7 + v_add_u32_e32 v14, v11, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v11, v11, v14 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v12, v11, v12 + v_lshlrev_b32_e32 v12, 3, v12 + v_add3_u32 v10, v10, v12, 64 + v_lshlrev_b32_e32 v12, 1, v10 + s_waitcnt vmcnt(5) + ds_write_b128 v12, v[50:53] offset:32896 + v_or_b32_e32 v12, 3, v7 + v_add_u32_e32 v14, v12, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v12, v12, v14 + v_xor_b32_e32 v12, v12, v69 + v_sub_u32_e32 v11, v12, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v10, v10, v11, 64 + v_lshlrev_b32_e32 v11, 1, v10 + s_waitcnt vmcnt(4) + ds_write_b128 v11, v[54:57] offset:32896 + v_or_b32_e32 v11, 4, v7 + v_add_u32_e32 v14, v11, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v11, v11, v14 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v12, v11, v12 + v_lshlrev_b32_e32 v12, 3, v12 + v_add3_u32 v10, v10, v12, 64 + v_lshlrev_b32_e32 v12, 1, v10 + s_waitcnt vmcnt(3) + ds_write_b128 v12, v[58:61] offset:32896 + v_or_b32_e32 v12, 5, v7 + v_add_u32_e32 v14, v12, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v12, v12, v14 + v_xor_b32_e32 v12, v12, v69 + v_sub_u32_e32 v11, v12, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v10, v10, v11, 64 + v_lshlrev_b32_e32 v11, 1, v10 + s_waitcnt vmcnt(2) + ds_write_b128 v11, v[62:65] offset:32896 + v_or_b32_e32 v11, 6, v7 + v_add_u32_e32 v14, v11, v13 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v11, v11, v14 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v12, v11, v12 + v_lshlrev_b32_e32 v12, 3, v12 + v_add_lshl_u32 v10, v10, v12, 1 + v_or_b32_e32 v7, 7, v7 + v_add_u32_e32 v12, v7, v13 + v_and_b32_e32 v12, 0xffffff8, v12 + v_sub_u32_e32 v7, v7, v12 + v_xor_b32_e32 v7, v7, v69 + v_sub_u32_e32 v7, v7, v11 + v_lshl_add_u32 v7, v7, 4, v10 + s_waitcnt vmcnt(1) + ds_write_b128 v10, v[74:77] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v7, v[78:81] offset:33152 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v7, 1, v9 + ds_read_b128 v[28:31], v7 + v_add_u32_e32 v7, 16, v5 + v_lshrrev_b32_e32 v10, 5, v7 + v_bfe_u32 v11, v7, 3, 2 + v_lshl_or_b32 v12, v10, 3, v69 + v_and_b32_e32 v13, 31, v12 + v_xor_b32_e32 v14, v8, v13 + v_sub_u32_e32 v7, v14, v68 + v_lshlrev_b32_e32 v15, 11, v10 + v_lshlrev_b32_e32 v7, 3, v7 + v_sub_u32_e32 v16, v11, v2 + v_lshl_or_b32 v15, v16, 12, v15 + v_add3_u32 v7, v9, v15, v7 + v_lshlrev_b32_e32 v9, 1, v7 + v_lshlrev_b32_e32 v16, 7, v67 + v_lshl_or_b32 v17, v4, 4, v16 + ds_read_b128 v[36:39], v17 offset:32768 + ds_read_b128 v[40:43], v9 + v_xor_b32_e32 v10, 1, v10 + v_sub_u32_e32 v11, v2, v11 + v_lshl_add_u32 v12, v10, 3, v12 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[28:29], v[36:37], 0 + v_and_b32_e32 v17, 31, v12 + v_xor_b32_e32 v18, v8, v17 + v_sub_u32_e32 v14, v18, v14 + v_lshlrev_b32_e32 v10, 11, v10 + v_add_u32_e32 v19, 6, v2 + v_xor_b32_e32 v19, v19, v69 + v_lshl_add_u32 v20, v19, 4, v16 + v_mfma_f32_32x32x8_bf16 a[0:15], v[30:31], v[38:39], a[0:15] + v_sub_u32_e32 v21, v4, v19 + v_lshl_add_u32 v21, v21, 4, v20 + ds_read_b128 v[44:47], v21 offset:40960 + v_lshl_add_u32 v10, v11, 12, v10 + v_lshl_add_u32 v11, v14, 3, v10 + v_lshl_add_u32 v9, v11, 1, v9 + v_add_u32_e32 v5, 48, v5 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[28:29], v[44:45], 0 + v_lshrrev_b32_e32 v14, 5, v5 + v_add_u32_e32 v22, -1, v14 + v_bfe_u32 v5, v5, 3, 2 + v_sub_u32_e32 v23, v5, v2 + v_lshl_add_u32 v12, v22, 3, v12 + v_ashrrev_i32_e32 v24, 31, v12 + v_lshrrev_b32_e32 v24, 27, v24 + v_mfma_f32_32x32x8_bf16 a[32:47], v[30:31], v[46:47], a[32:47] + v_add_u32_e32 v24, v12, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + ds_read_b128 v[48:51], v21 offset:49152 + v_sub_u32_e32 v24, v12, v24 + v_xor_b32_e32 v8, v8, v24 + v_sub_u32_e32 v18, v8, v18 + ds_read_b128 v[52:55], v21 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[28:29], v[48:49], 0 + v_lshlrev_b32_e32 v22, 11, v22 + v_lshl_add_u32 v22, v23, 12, v22 + v_lshl_add_u32 v18, v18, 3, v22 + v_lshl_add_u32 v23, v18, 1, v9 + v_add_u32_e32 v25, 64, v6 + v_lshrrev_b32_e32 v25, 3, v25 + v_sub_u32_e32 v5, v2, v5 + v_mfma_f32_32x32x8_bf16 a[112:127], v[30:31], v[50:51], a[112:127] + v_lshlrev_b32_e32 v26, 3, v14 + v_sub_u32_e32 v12, v12, v26 + v_ashrrev_i32_e32 v26, 31, v12 + v_lshrrev_b32_e32 v26, 27, v26 + v_add_u32_e32 v26, v12, v26 + v_and_b32_e32 v26, 0xffffffe0, v26 + v_sub_u32_e32 v12, v12, v26 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[28:29], v[52:53], 0 + v_xor_b32_e32 v26, v25, v12 + v_sub_u32_e32 v8, v26, v8 + v_lshlrev_b32_e32 v5, 12, v5 + v_lshlrev_b32_e32 v14, 11, v14 + v_sub_u32_e32 v5, v5, v14 + v_lshl_add_u32 v8, v8, 3, v5 + v_lshl_add_u32 v14, v8, 1, v23 + v_mfma_f32_32x32x8_bf16 a[208:223], v[30:31], v[54:55], a[208:223] + ds_read_b128 v[32:35], v14 + v_xor_b32_e32 v27, v25, v13 + v_sub_u32_e32 v26, v27, v26 + v_lshl_add_u32 v26, v26, 3, v15 + v_lshl_add_u32 v14, v26, 1, v14 + ds_read_b128 v[56:59], v14 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[32:33], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[34:35], v[38:39], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[32:33], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[192:207], v[34:35], v[46:47], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[32:33], v[48:49], 0 + v_mfma_f32_32x32x8_bf16 a[160:175], v[34:35], v[50:51], a[160:175] + v_xor_b32_e32 v28, v25, v17 + v_sub_u32_e32 v27, v28, v27 + v_lshl_add_u32 v27, v27, 3, v10 + v_lshl_add_u32 v14, v27, 1, v14 + v_xor_b32_e32 v25, v25, v24 + v_sub_u32_e32 v28, v25, v28 + v_lshl_add_u32 v28, v28, 3, v22 + v_mfma_f32_32x32x8_bf16 a[144:159], v[32:33], v[52:53], 0 + v_lshl_add_u32 v29, v28, 1, v14 + v_add_u32_e32 v30, 0x80, v6 + v_lshrrev_b32_e32 v30, 3, v30 + v_xor_b32_e32 v31, v30, v12 + v_sub_u32_e32 v25, v31, v25 + v_lshl_add_u32 v25, v25, 3, v5 + v_lshl_add_u32 v32, v25, 1, v29 + v_mfma_f32_32x32x8_bf16 a[144:159], v[34:35], v[54:55], a[144:159] + ds_read_b128 v[60:63], v32 + v_xor_b32_e32 v33, v30, v13 + v_sub_u32_e32 v31, v33, v31 + v_lshl_add_u32 v31, v31, 3, v15 + v_lshl_add_u32 v32, v31, 1, v32 + ds_read_b128 v[64:67], v32 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[60:61], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[176:191], v[62:63], v[38:39], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[60:61], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[128:143], v[62:63], v[46:47], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[60:61], v[48:49], 0 + v_mfma_f32_32x32x8_bf16 a[80:95], v[62:63], v[50:51], a[80:95] + v_xor_b32_e32 v34, v30, v17 + v_sub_u32_e32 v33, v34, v33 + v_lshl_add_u32 v33, v33, 3, v10 + v_lshl_add_u32 v32, v33, 1, v32 + v_xor_b32_e32 v30, v30, v24 + v_sub_u32_e32 v34, v30, v34 + v_lshl_add_u32 v34, v34, 3, v22 + v_mfma_f32_32x32x8_bf16 a[64:79], v[60:61], v[52:53], 0 + v_lshl_add_u32 v35, v34, 1, v32 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 3, v6 + v_xor_b32_e32 v12, v6, v12 + v_sub_u32_e32 v30, v12, v30 + v_lshl_add_u32 v5, v30, 3, v5 + v_lshl_add_u32 v30, v5, 1, v35 + v_mfma_f32_32x32x8_bf16 a[64:79], v[62:63], v[54:55], a[64:79] + ds_read_b128 v[60:63], v30 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[60:61], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[62:63], v[38:39], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[60:61], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[48:63], v[62:63], v[46:47], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[60:61], v[48:49], 0 + v_mfma_f32_32x32x8_bf16 a[16:31], v[62:63], v[50:51], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[60:61], v[52:53], 0 + v_add_u32_e32 v36, 2, v2 + v_mfma_f32_32x32x8_bf16 a[240:255], v[62:63], v[54:55], a[240:255] + v_xor_b32_e32 v36, v36, v69 + v_lshl_or_b32 v37, v36, 4, v16 + ds_read_b128 v[44:47], v37 offset:32768 + v_or_b32_e32 v37, 4, v2 + v_xor_b32_e32 v37, v37, v69 + v_lshl_or_b32 v16, v37, 4, v16 + ds_read_b128 v[48:51], v16 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[40:41], v[44:45], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[42:43], v[46:47], a[0:15] + v_sub_u32_e32 v16, v36, v4 + v_lshl_add_u32 v16, v16, 4, v21 + ds_read_b128 v[52:55], v16 offset:40960 + ds_read_b128 v[60:63], v16 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[40:41], v[52:53], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[42:43], v[54:55], a[32:47] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[40:41], v[60:61], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[42:43], v[62:63], a[112:127] + ds_read_b128 v[74:77], v16 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[40:41], v[74:75], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[42:43], v[76:77], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[56:57], v[44:45], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[58:59], v[46:47], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[56:57], v[52:53], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[58:59], v[54:55], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[56:57], v[60:61], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[58:59], v[62:63], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[56:57], v[74:75], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[58:59], v[76:77], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[64:65], v[44:45], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[66:67], v[46:47], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[64:65], v[52:53], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[66:67], v[54:55], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[64:65], v[60:61], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[66:67], v[62:63], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[64:65], v[74:75], a[64:79] + v_xor_b32_e32 v13, v6, v13 + v_sub_u32_e32 v12, v13, v12 + v_lshl_add_u32 v12, v12, 3, v15 + v_lshl_add_u32 v15, v12, 1, v30 + v_mfma_f32_32x32x8_bf16 a[64:79], v[66:67], v[76:77], a[64:79] + ds_read_b128 v[38:41], v15 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[38:39], v[44:45], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[40:41], v[46:47], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[38:39], v[52:53], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[40:41], v[54:55], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[38:39], v[60:61], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[40:41], v[62:63], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[38:39], v[74:75], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[40:41], v[76:77], a[240:255] + ds_read_b128 v[38:41], v9 + ds_read_b128 v[42:45], v23 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[38:39], v[48:49], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[40:41], v[50:51], a[0:15] + v_sub_u32_e32 v9, v37, v4 + v_lshl_add_u32 v9, v9, 4, v21 + ds_read_b128 v[52:55], v9 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[38:39], v[52:53], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[40:41], v[54:55], a[32:47] + ds_read_b128 v[56:59], v9 offset:49152 + ds_read_b128 v[60:63], v9 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[38:39], v[56:57], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[40:41], v[58:59], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[38:39], v[60:61], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[40:41], v[62:63], a[208:223] + ds_read_b128 v[36:39], v14 + ds_read_b128 v[64:67], v29 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[36:37], v[48:49], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[38:39], v[50:51], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[36:37], v[52:53], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[38:39], v[54:55], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[36:37], v[56:57], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[38:39], v[58:59], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[36:37], v[60:61], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[38:39], v[62:63], a[144:159] + ds_read_b128 v[36:39], v32 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[36:37], v[48:49], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[38:39], v[50:51], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[36:37], v[52:53], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[38:39], v[54:55], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[36:37], v[56:57], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[38:39], v[58:59], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[36:37], v[60:61], a[64:79] + v_xor_b32_e32 v9, v6, v17 + v_sub_u32_e32 v13, v9, v13 + v_lshl_add_u32 v10, v13, 3, v10 + v_lshl_add_u32 v13, v10, 1, v15 + v_mfma_f32_32x32x8_bf16 a[64:79], v[38:39], v[62:63], a[64:79] + ds_read_b128 v[14:17], v13 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[14:15], v[48:49], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[16:17], v[50:51], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[14:15], v[52:53], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[16:17], v[54:55], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[14:15], v[56:57], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[16:17], v[58:59], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[14:15], v[60:61], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[16:17], v[62:63], a[240:255] + ds_read_b128 v[14:17], v20 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[42:43], v[14:15], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[44:45], v[16:17], a[0:15] + v_sub_u32_e32 v4, v19, v4 + v_lshl_add_u32 v4, v4, 4, v21 + ds_read_b128 v[36:39], v4 offset:40960 + ds_read_b128 v[46:49], v4 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[42:43], v[36:37], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[44:45], v[38:39], a[32:47] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[42:43], v[46:47], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[44:45], v[48:49], a[112:127] + ds_read_b128 v[50:53], v4 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[42:43], v[50:51], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[44:45], v[52:53], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[64:65], v[14:15], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[66:67], v[16:17], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[64:65], v[36:37], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[66:67], v[38:39], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[64:65], v[46:47], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[66:67], v[48:49], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[64:65], v[50:51], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[66:67], v[52:53], a[144:159] + ds_read_b128 v[40:43], v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[40:41], v[14:15], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[42:43], v[16:17], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[40:41], v[36:37], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[42:43], v[38:39], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[40:41], v[46:47], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[42:43], v[48:49], a[80:95] + v_add3_u32 v4, v11, v7, v18 + v_add3_u32 v4, v8, v4, v26 + v_add3_u32 v4, v27, v4, v28 + v_add3_u32 v4, v25, v4, v31 + v_add3_u32 v4, v33, v4, v34 + v_mfma_f32_32x32x8_bf16 a[64:79], v[40:41], v[50:51], a[64:79] + v_add3_u32 v4, v5, v4, v12 + v_xor_b32_e32 v5, v6, v24 + v_sub_u32_e32 v5, v5, v9 + v_lshlrev_b32_e32 v5, 4, v5 + v_lshlrev_b32_e32 v6, 1, v22 + v_add_lshl_u32 v4, v10, v4, 1 + v_add3_u32 v4, v5, v6, v4 + v_mfma_f32_32x32x8_bf16 a[64:79], v[42:43], v[52:53], a[64:79] + ds_read_b128 v[4:7], v4 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[14:15], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[6:7], v[16:17], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[36:37], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[6:7], v[38:39], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[46:47], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[48:49], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[50:51], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[52:53], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB9_3 + s_branch .LBB9_10 +.LBB9_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr63 + ; implicit-def: $agpr111 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr143 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr127 + ; implicit-def: $agpr47 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB9_3: + v_readfirstlane_b32 s15, v0 + s_lshr_b32 s24, s15, 2 + s_and_b32 s23, s24, 0x3ffffff0 + v_lshl_or_b32 v4, v72, 3, s18 + v_lshlrev_b32_e32 v73, 3, v2 + v_add_u32_e32 v5, s23, v73 + v_mad_u64_u32 v[66:67], s[10:11], v5, s7, v[4:5] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v4, 1, v66 + v_add_u32_e32 v5, s7, v66 + v_lshlrev_b32_e32 v6, 1, v5 + buffer_load_dwordx4 v[10:13], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v6, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v5 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + buffer_load_dwordx4 v[18:21], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[22:25], v6, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + buffer_load_dwordx4 v[26:29], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[30:33], v6, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_lshl_u32 v4, v4, s7, 1 + buffer_load_dwordx4 v[34:37], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v5, 12, v2 + v_lshlrev_b32_e32 v68, 3, v69 + v_and_b32_e32 v103, 0x78, v1 + v_xor_b32_e32 v4, v2, v69 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + v_lshl_or_b32 v8, v69, 8, v5 + s_and_b32 s25, s15, 0xffffffc0 + s_lshr_b32 s26, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s24, s24, 0x3fffffe0 + v_add_u32_e32 v67, s25, v103 + v_and_or_b32 v5, s26, 32, v72 + v_or_b32_e32 v6, s24, v72 + v_add_u32_e32 v9, s19, v67 + v_lshlrev_b32_e32 v5, 6, v5 + v_lshrrev_b32_e32 v7, 3, v6 + v_mad_u64_u32 v[70:71], s[24:25], v9, s20, v[68:69] + v_xor_b32_e32 v9, v7, v69 + v_lshlrev_b32_e32 v50, 1, v70 + v_add_u32_e32 v42, s20, v70 + v_lshl_add_u32 v8, v9, 3, v8 + v_lshlrev_b32_e32 v51, 1, v42 + v_add_u32_e32 v52, s20, v42 + buffer_load_dwordx4 v[42:45], v50, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v51, s[12:15], 0 offen + v_lshlrev_b32_e32 v58, 1, v52 + v_add_u32_e32 v50, s20, v52 + v_lshlrev_b32_e32 v59, 1, v50 + v_add_u32_e32 v60, s20, v50 + buffer_load_dwordx4 v[50:53], v58, s[12:15], 0 offen + buffer_load_dwordx4 v[54:57], v59, s[12:15], 0 offen + v_lshlrev_b32_e32 v71, 1, v60 + v_add_u32_e32 v58, s20, v60 + v_lshlrev_b32_e32 v74, 1, v58 + v_add_u32_e32 v75, s20, v58 + buffer_load_dwordx4 v[58:61], v71, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v74, s[12:15], 0 offen + v_lshlrev_b32_e32 v71, 1, v75 + v_add_lshl_u32 v82, v75, s20, 1 + buffer_load_dwordx4 v[74:77], v71, s[12:15], 0 offen + buffer_load_dwordx4 v[78:81], v82, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v82, v10, v14, s21 + v_perm_b32 v86, v10, v14, s22 + v_perm_b32 v90, v11, v15, s21 + v_perm_b32 v94, v11, v15, s22 + v_perm_b32 v98, v12, v16, s21 + s_waitcnt vmcnt(12) + v_perm_b32 v83, v18, v22, s21 + v_perm_b32 v87, v18, v22, s22 + v_perm_b32 v91, v19, v23, s21 + v_perm_b32 v95, v19, v23, s22 + s_waitcnt vmcnt(10) + v_perm_b32 v84, v26, v30, s21 + v_perm_b32 v88, v26, v30, s22 + v_perm_b32 v92, v27, v31, s21 + v_perm_b32 v96, v27, v31, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v85, v34, v38, s21 + v_perm_b32 v89, v34, v38, s22 + v_perm_b32 v93, v35, v39, s21 + v_perm_b32 v97, v35, v39, s22 + v_perm_b32 v106, v12, v16, s22 + v_perm_b32 v99, v20, v24, s21 + v_perm_b32 v107, v20, v24, s22 + v_perm_b32 v100, v28, v32, s21 + v_perm_b32 v108, v28, v32, s22 + v_perm_b32 v101, v36, v40, s21 + v_perm_b32 v109, v36, v40, s22 + v_perm_b32 v10, v13, v17, s21 + v_perm_b32 v14, v13, v17, s22 + v_perm_b32 v11, v21, v25, s21 + v_perm_b32 v15, v21, v25, s22 + v_perm_b32 v12, v29, v33, s21 + v_perm_b32 v16, v29, v33, s22 + v_perm_b32 v13, v37, v41, s21 + v_perm_b32 v17, v37, v41, s22 + v_and_b32_e32 v104, 24, v3 + v_add_u32_e32 v3, s23, v104 + v_lshrrev_b32_e32 v18, 2, v3 + v_and_b32_e32 v18, 24, v18 + v_xor_b32_e32 v19, v18, v72 + v_lshlrev_b32_e32 v20, 9, v3 + v_and_b32_e32 v20, 0x3000, v20 + v_lshlrev_b32_e32 v3, 6, v3 + v_and_b32_e32 v3, 0xfffff800, v3 + v_add_u32_e32 v3, v3, v20 + v_lshl_or_b32 v3, v19, 3, v3 + v_lshlrev_b32_e32 v20, 1, v3 + ds_write_b128 v20, v[82:85] + v_or_b32_e32 v21, 1, v18 + v_xor_b32_e32 v21, v21, v72 + v_sub_u32_e32 v19, v21, v19 + v_lshlrev_b32_e32 v22, 3, v19 + v_or_b32_e32 v23, 2, v18 + v_xor_b32_e32 v23, v23, v72 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v24, 3, v21 + v_add3_u32 v3, v22, v3, v24 + v_lshl_add_u32 v19, v19, 4, v20 + ds_write_b128 v19, v[86:89] offset:512 + v_or_b32_e32 v20, 3, v18 + v_xor_b32_e32 v20, v20, v72 + v_sub_u32_e32 v22, v20, v23 + v_lshlrev_b32_e32 v23, 3, v22 + v_or_b32_e32 v24, 4, v18 + v_xor_b32_e32 v24, v24, v72 + v_sub_u32_e32 v20, v24, v20 + v_lshlrev_b32_e32 v25, 3, v20 + v_add3_u32 v3, v3, v23, v25 + v_lshlrev_b32_e32 v21, 4, v21 + s_movk_i32 s21, 0x200 + v_add3_u32 v19, v19, s21, v21 + ds_write_b128 v19, v[90:93] offset:512 + v_or_b32_e32 v21, 5, v18 + v_xor_b32_e32 v21, v21, v72 + v_sub_u32_e32 v23, v21, v24 + v_lshlrev_b32_e32 v24, 3, v23 + v_or_b32_e32 v25, 6, v18 + v_xor_b32_e32 v25, v25, v72 + v_sub_u32_e32 v21, v25, v21 + v_lshlrev_b32_e32 v26, 3, v21 + v_add3_u32 v3, v3, v24, v26 + v_lshlrev_b32_e32 v22, 4, v22 + v_add3_u32 v19, v19, s21, v22 + ds_write_b128 v19, v[94:97] offset:512 + v_or_b32_e32 v18, 7, v18 + v_xor_b32_e32 v18, v18, v72 + v_sub_u32_e32 v18, v18, v25 + v_lshlrev_b32_e32 v18, 4, v18 + v_lshl_add_u32 v3, v3, 1, v18 + v_lshlrev_b32_e32 v18, 4, v20 + v_add3_u32 v18, v19, s21, v18 + ds_write_b128 v18, v[98:101] offset:512 + v_lshlrev_b32_e32 v19, 4, v23 + v_add3_u32 v18, v18, s21, v19 + ds_write_b128 v18, v[106:109] offset:512 + v_lshlrev_b32_e32 v19, 4, v21 + v_add3_u32 v18, v18, s21, v19 + ds_write_b128 v18, v[10:13] offset:512 + ds_write_b128 v3, v[14:17] offset:3584 + v_lshl_or_b32 v3, v67, 6, v68 + v_lshlrev_b32_e32 v10, 1, v3 + s_waitcnt vmcnt(7) + ds_write_b128 v10, v[42:45] offset:32768 + v_or_b32_e32 v11, 1, v67 + v_ashrrev_i32_e32 v12, 31, v67 + v_lshrrev_b32_e32 v12, 29, v12 + v_add_u32_e32 v13, v11, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v11, v11, v13 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v13, v11, v69 + v_lshl_add_u32 v3, v13, 3, v3 + v_lshl_add_u32 v10, v13, 4, v10 + s_waitcnt vmcnt(6) + ds_write_b128 v10, v[46:49] offset:32896 + v_or_b32_e32 v10, 2, v67 + v_add_u32_e32 v13, v10, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v10, v10, v13 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v11, v10, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v3, v3, v11, 64 + v_lshlrev_b32_e32 v11, 1, v3 + s_waitcnt vmcnt(5) + ds_write_b128 v11, v[50:53] offset:32896 + v_or_b32_e32 v11, 3, v67 + v_add_u32_e32 v13, v11, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v11, v11, v13 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v3, v3, v10, 64 + v_lshlrev_b32_e32 v10, 1, v3 + s_waitcnt vmcnt(4) + ds_write_b128 v10, v[54:57] offset:32896 + v_or_b32_e32 v10, 4, v67 + v_add_u32_e32 v13, v10, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v10, v10, v13 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v11, v10, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v3, v3, v11, 64 + v_lshlrev_b32_e32 v11, 1, v3 + s_waitcnt vmcnt(3) + ds_write_b128 v11, v[58:61] offset:32896 + v_or_b32_e32 v11, 5, v67 + v_add_u32_e32 v13, v11, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v11, v11, v13 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v3, v3, v10, 64 + v_lshlrev_b32_e32 v10, 1, v3 + s_waitcnt vmcnt(2) + ds_write_b128 v10, v[62:65] offset:32896 + v_or_b32_e32 v10, 6, v67 + v_add_u32_e32 v13, v10, v12 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v10, v10, v13 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v11, v10, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add_lshl_u32 v3, v3, v11, 1 + v_or_b32_e32 v11, 7, v67 + v_add_u32_e32 v12, v11, v12 + v_and_b32_e32 v12, 0xffffff8, v12 + v_sub_u32_e32 v11, v11, v12 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v10, v11, v10 + v_lshl_add_u32 v10, v10, 4, v3 + s_waitcnt vmcnt(1) + ds_write_b128 v3, v[74:77] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v10, v[78:81] offset:33152 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v14, 16, v73 + v_add_u32_e32 v13, 48, v73 + v_add_u32_e32 v12, 64, v6 + v_add_u32_e32 v11, 2, v2 + v_or_b32_e32 v10, 4, v2 + v_add_u32_e32 v3, 6, v2 + s_cbranch_vccnz .LBB9_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit194.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_lshrrev_b32_e32 v15, 5, v14 + v_bfe_u32 v16, v14, 3, 2 + v_lshl_or_b32 v17, v15, 3, v69 + v_xor_b32_e32 v18, v7, v17 + v_sub_u32_e32 v19, v18, v9 + v_lshlrev_b32_e32 v20, 11, v15 + v_lshlrev_b32_e32 v19, 3, v19 + v_sub_u32_e32 v21, v16, v2 + v_lshl_or_b32 v20, v21, 12, v20 + v_add3_u32 v75, v8, v20, v19 + v_xor_b32_e32 v15, 1, v15 + v_sub_u32_e32 v16, v2, v16 + v_lshl_add_u32 v19, v15, 3, v17 + v_xor_b32_e32 v21, v7, v19 + v_sub_u32_e32 v18, v21, v18 + v_lshlrev_b32_e32 v15, 11, v15 + v_lshlrev_b32_e32 v18, 3, v18 + v_lshl_or_b32 v15, v16, 12, v15 + v_add3_u32 v76, v18, v15, v75 + v_lshrrev_b32_e32 v16, 5, v13 + v_add_u32_e32 v18, -1, v16 + v_bfe_u32 v22, v13, 3, 2 + v_sub_u32_e32 v23, v22, v2 + v_lshl_add_u32 v24, v18, 3, v19 + v_ashrrev_i32_e32 v25, 31, v24 + v_lshrrev_b32_e32 v25, 27, v25 + v_add_u32_e32 v25, v24, v25 + v_and_b32_e32 v25, 0xffffffe0, v25 + v_sub_u32_e32 v25, v24, v25 + v_xor_b32_e32 v26, v7, v25 + v_sub_u32_e32 v21, v26, v21 + v_lshlrev_b32_e32 v18, 11, v18 + v_lshlrev_b32_e32 v21, 3, v21 + v_lshl_add_u32 v18, v23, 12, v18 + v_add3_u32 v67, v21, v18, v76 + v_lshrrev_b32_e32 v21, 3, v12 + v_sub_u32_e32 v22, v2, v22 + v_lshlrev_b32_e32 v23, 3, v16 + v_sub_u32_e32 v23, v24, v23 + v_ashrrev_i32_e32 v24, 31, v23 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v23, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v23, v23, v24 + v_xor_b32_e32 v24, v21, v23 + v_sub_u32_e32 v26, v24, v26 + v_lshlrev_b32_e32 v26, 3, v26 + v_lshlrev_b32_e32 v22, 12, v22 + v_lshlrev_b32_e32 v16, 11, v16 + v_sub_u32_e32 v16, v22, v16 + v_add3_u32 v94, v26, v16, v67 + v_xor_b32_e32 v22, v21, v17 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v77, v24, v20, v94 + v_xor_b32_e32 v24, v21, v19 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v78, v22, v15, v77 + v_xor_b32_e32 v21, v21, v25 + v_sub_u32_e32 v22, v21, v24 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v71, v22, v18, v78 + v_add_u32_e32 v22, 0x80, v6 + v_lshrrev_b32_e32 v22, 3, v22 + v_xor_b32_e32 v24, v22, v23 + v_sub_u32_e32 v21, v24, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v93, v21, v16, v71 + v_xor_b32_e32 v21, v22, v17 + v_sub_u32_e32 v24, v21, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v79, v24, v20, v93 + v_xor_b32_e32 v24, v22, v19 + v_sub_u32_e32 v21, v24, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v80, v21, v15, v79 + v_xor_b32_e32 v21, v22, v25 + v_sub_u32_e32 v22, v21, v24 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v73, v22, v18, v80 + v_add_u32_e32 v22, 0xc0, v6 + v_lshrrev_b32_e32 v22, 3, v22 + v_xor_b32_e32 v23, v22, v23 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v92, v21, v16, v73 + v_xor_b32_e32 v16, v22, v17 + v_sub_u32_e32 v17, v16, v23 + v_lshlrev_b32_e32 v17, 3, v17 + v_add3_u32 v81, v17, v20, v92 + v_xor_b32_e32 v17, v22, v19 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v82, v16, v15, v81 + v_xor_b32_e32 v15, v22, v25 + v_sub_u32_e32 v15, v15, v17 + v_lshlrev_b32_e32 v15, 3, v15 + v_add3_u32 v74, v15, v18, v82 + v_xor_b32_e32 v15, v11, v69 + v_lshl_add_u32 v91, v15, 3, v5 + v_xor_b32_e32 v16, v10, v69 + v_lshl_add_u32 v83, v16, 3, v5 + v_xor_b32_e32 v17, v3, v69 + v_lshl_add_u32 v84, v17, 3, v5 + v_sub_u32_e32 v18, v4, v17 + v_mov_b32_e32 v19, 0x1000 + v_lshl_add_u32 v18, v18, 3, v19 + v_add_u32_e32 v97, v84, v18 + v_sub_u32_e32 v15, v15, v4 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v100, v97, v15 + v_sub_u32_e32 v16, v16, v4 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v85, v97, v16 + v_sub_u32_e32 v17, v17, v4 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v86, v97, v17 + v_add_u32_e32 v98, v86, v18 + v_add_u32_e32 v99, v98, v15 + v_add_u32_e32 v87, v98, v16 + v_add_u32_e32 v88, v98, v17 + v_add_u32_e32 v95, v88, v18 + v_add_u32_e32 v96, v95, v15 + v_add_u32_e32 v89, v95, v16 + v_add_u32_e32 v90, v95, v17 + s_mov_b64 s[2:3], 0 + s_branch .LBB9_6 +.LBB9_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr90 +.LBB9_6: ; %Flow1284 + v_lshl_or_b32 v15, v4, 3, v5 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a96, 0 + v_lshlrev_b32_e32 v102, 1, v8 + v_lshlrev_b32_e32 v101, 1, v15 + s_cbranch_vccnz .LBB9_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i531.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_lshrrev_b32_e32 v15, 5, v14 + v_bfe_u32 v14, v14, 3, 2 + v_lshl_or_b32 v16, v15, 3, v69 + v_xor_b32_e32 v17, v7, v16 + v_sub_u32_e32 v9, v17, v9 + v_lshlrev_b32_e32 v18, 11, v15 + v_lshlrev_b32_e32 v9, 3, v9 + v_sub_u32_e32 v19, v14, v2 + v_lshl_or_b32 v18, v19, 12, v18 + v_add3_u32 v75, v8, v18, v9 + v_xor_b32_e32 v8, 1, v15 + v_sub_u32_e32 v9, v2, v14 + v_lshl_add_u32 v14, v8, 3, v16 + v_xor_b32_e32 v15, v7, v14 + v_sub_u32_e32 v17, v15, v17 + v_lshlrev_b32_e32 v8, 11, v8 + v_lshlrev_b32_e32 v17, 3, v17 + v_lshl_or_b32 v8, v9, 12, v8 + v_add3_u32 v76, v17, v8, v75 + v_lshrrev_b32_e32 v9, 5, v13 + v_add_u32_e32 v17, -1, v9 + v_bfe_u32 v13, v13, 3, 2 + v_sub_u32_e32 v19, v13, v2 + v_lshl_add_u32 v20, v17, 3, v14 + v_ashrrev_i32_e32 v21, 31, v20 + v_lshrrev_b32_e32 v21, 27, v21 + v_add_u32_e32 v21, v20, v21 + v_and_b32_e32 v21, 0xffffffe0, v21 + v_sub_u32_e32 v21, v20, v21 + v_xor_b32_e32 v7, v7, v21 + v_sub_u32_e32 v15, v7, v15 + v_lshlrev_b32_e32 v17, 11, v17 + v_lshlrev_b32_e32 v15, 3, v15 + v_lshl_add_u32 v17, v19, 12, v17 + v_add3_u32 v67, v15, v17, v76 + v_lshrrev_b32_e32 v12, 3, v12 + v_sub_u32_e32 v2, v2, v13 + v_lshlrev_b32_e32 v13, 3, v9 + v_sub_u32_e32 v13, v20, v13 + v_ashrrev_i32_e32 v15, 31, v13 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v13, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v13, v13, v15 + v_xor_b32_e32 v15, v12, v13 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v2, 12, v2 + v_lshlrev_b32_e32 v9, 11, v9 + v_sub_u32_e32 v2, v2, v9 + v_add3_u32 v94, v7, v2, v67 + v_xor_b32_e32 v7, v12, v16 + v_sub_u32_e32 v9, v7, v15 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v77, v9, v18, v94 + v_xor_b32_e32 v9, v12, v14 + v_sub_u32_e32 v7, v9, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v78, v7, v8, v77 + v_xor_b32_e32 v7, v12, v21 + v_sub_u32_e32 v9, v7, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v71, v9, v17, v78 + v_add_u32_e32 v9, 0x80, v6 + v_lshrrev_b32_e32 v9, 3, v9 + v_xor_b32_e32 v12, v9, v13 + v_sub_u32_e32 v7, v12, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v93, v7, v2, v71 + v_xor_b32_e32 v7, v9, v16 + v_sub_u32_e32 v12, v7, v12 + v_lshlrev_b32_e32 v12, 3, v12 + v_add3_u32 v79, v12, v18, v93 + v_xor_b32_e32 v12, v9, v14 + v_sub_u32_e32 v7, v12, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v80, v7, v8, v79 + v_xor_b32_e32 v7, v9, v21 + v_sub_u32_e32 v9, v7, v12 + v_lshlrev_b32_e32 v9, 3, v9 + v_add3_u32 v73, v9, v17, v80 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 3, v6 + v_xor_b32_e32 v9, v6, v13 + v_sub_u32_e32 v7, v9, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v92, v7, v2, v73 + v_xor_b32_e32 v2, v6, v16 + v_sub_u32_e32 v7, v2, v9 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v81, v7, v18, v92 + v_xor_b32_e32 v7, v6, v14 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v82, v2, v8, v81 + v_xor_b32_e32 v2, v6, v21 + v_sub_u32_e32 v2, v2, v7 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v74, v2, v17, v82 + v_xor_b32_e32 v2, v11, v69 + v_lshl_add_u32 v91, v2, 3, v5 + v_xor_b32_e32 v6, v10, v69 + v_lshl_add_u32 v83, v6, 3, v5 + v_xor_b32_e32 v3, v3, v69 + v_lshl_add_u32 v84, v3, 3, v5 + v_sub_u32_e32 v5, v4, v3 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v7, 0x1000, v5 + v_add_u32_e32 v97, v84, v7 + v_add_u32_e32 v5, v84, v5 + v_lshlrev_b32_e32 v105, 1, v5 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v100, v97, v2 + v_add_lshl_u32 v106, v5, v2, 1 + v_sub_u32_e32 v6, v6, v4 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_u32_e32 v85, v97, v6 + v_add_lshl_u32 v107, v5, v6, 1 + v_sub_u32_e32 v3, v3, v4 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v86, v97, v3 + v_add_u32_e32 v4, v5, v3 + v_lshlrev_b32_e32 v108, 1, v4 + v_add_u32_e32 v98, v86, v7 + v_add_lshl_u32 v109, v4, v7, 1 + v_add_u32_e32 v99, v98, v2 + v_add_u32_e32 v87, v98, v6 + v_add_u32_e32 v88, v98, v3 + v_add_u32_e32 v95, v88, v7 + v_add_u32_e32 v96, v95, v2 + v_add_u32_e32 v89, v95, v6 + v_add_u32_e32 v90, v95, v3 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + s_mov_b32 s6, 0x1000504 + s_mov_b32 s21, 0x3020706 + s_movk_i32 s22, 0x200 +.LBB9_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i531.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v70, 64, v70 + v_add_u32_e32 v66, s2, v66 + v_lshlrev_b32_e32 v6, 1, v66 + v_add_u32_e32 v2, s7, v66 + v_lshlrev_b32_e32 v3, 1, v70 + v_add_u32_e32 v7, s20, v70 + v_lshlrev_b32_e32 v8, 1, v2 + v_add_u32_e32 v9, s7, v2 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 1, v7 + v_add_u32_e32 v11, s20, v7 + buffer_load_dwordx4 v[34:37], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v8, s[8:11], 0 offen + v_lshlrev_b32_e32 v14, 1, v9 + v_add_u32_e32 v12, s7, v9 + buffer_load_dwordx4 v[6:9], v10, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 1, v11 + v_add_u32_e32 v15, s20, v11 + v_lshlrev_b32_e32 v16, 1, v12 + v_add_u32_e32 v17, s7, v12 + buffer_load_dwordx4 v[10:13], v10, s[12:15], 0 offen + v_lshlrev_b32_e32 v18, 1, v15 + v_add_u32_e32 v19, s20, v15 + buffer_load_dwordx4 v[42:45], v14, s[8:11], 0 offen + buffer_load_dwordx4 v[46:49], v16, s[8:11], 0 offen + v_lshlrev_b32_e32 v22, 1, v17 + v_add_u32_e32 v20, s7, v17 + buffer_load_dwordx4 v[14:17], v18, s[12:15], 0 offen + v_lshlrev_b32_e32 v18, 1, v19 + v_add_u32_e32 v23, s20, v19 + v_lshlrev_b32_e32 v24, 1, v20 + v_add_u32_e32 v25, s7, v20 + buffer_load_dwordx4 v[18:21], v18, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v23 + v_add_u32_e32 v27, s20, v23 + buffer_load_dwordx4 v[54:57], v22, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v24, s[8:11], 0 offen + v_lshlrev_b32_e32 v28, 1, v25 + v_add_lshl_u32 v29, v25, s7, 1 + buffer_load_dwordx4 v[22:25], v26, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v27 + v_add_lshl_u32 v30, v27, s20, 1 + buffer_load_dwordx4 v[50:53], v28, s[8:11], 0 offen + buffer_load_dwordx4 v[58:61], v29, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[26:29], v26, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[30:33], v30, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[114:117], v102 + ds_read_b128 v[110:113], v101 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[114:115], v[110:111], a[96:111] + ds_read_b128 v[120:123], v105 offset:40960 + ds_read_b128 v[124:127], v106 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[114:115], v[120:121], a[80:95] + ds_read_b128 v[128:131], v109 offset:40960 + v_lshlrev_b32_e32 v118, 1, v100 + ds_read_b128 v[132:135], v118 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[114:115], v[128:129], a[64:79] + v_lshlrev_b32_e32 v118, 1, v98 + ds_read_b128 v[136:139], v118 offset:40960 + v_lshlrev_b32_e32 v118, 1, v99 + ds_read_b128 v[140:143], v118 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[114:115], v[136:137], a[128:143] + v_lshlrev_b32_e32 v114, 1, v94 + ds_read_b128 v[144:147], v114 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[144:145], v[110:111], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[144:145], v[120:121], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[144:145], v[128:129], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[144:145], v[136:137], a[176:191] + v_lshlrev_b32_e32 v114, 1, v93 + ds_read_b128 v[148:151], v114 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[148:149], v[110:111], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[148:149], v[120:121], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[148:149], v[128:129], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[136:137], a[240:255] + v_lshlrev_b32_e32 v114, 1, v92 + ds_read_b128 v[152:155], v114 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[110:111], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[120:121], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[128:129], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[136:137], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[116:117], v[112:113], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[116:117], v[122:123], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[116:117], v[130:131], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[116:117], v[138:139], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[146:147], v[112:113], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[146:147], v[122:123], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[146:147], v[130:131], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[146:147], v[138:139], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[112:113], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[122:123], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[130:131], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[138:139], a[240:255] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[112:113], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[122:123], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[130:131], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[154:155], v[138:139], a[48:63] + v_lshlrev_b32_e32 v110, 1, v75 + ds_read_b128 v[112:115], v110 + v_lshlrev_b32_e32 v110, 1, v91 + ds_read_b128 v[116:119], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v76 + ds_read_b128 v[128:131], v110 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[112:113], v[116:117], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[112:113], v[124:125], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[112:113], v[132:133], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[112:113], v[140:141], a[128:143] + v_lshlrev_b32_e32 v110, 1, v77 + ds_read_b128 v[120:123], v110 + v_lshlrev_b32_e32 v110, 1, v78 + ds_read_b128 v[136:139], v110 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[120:121], v[116:117], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[120:121], v[124:125], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[120:121], v[132:133], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[120:121], v[140:141], a[176:191] + v_lshlrev_b32_e32 v110, 1, v79 + ds_read_b128 v[144:147], v110 + v_lshlrev_b32_e32 v110, 1, v80 + ds_read_b128 v[148:151], v110 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[144:145], v[116:117], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[144:145], v[124:125], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[144:145], v[132:133], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[140:141], a[240:255] + v_lshlrev_b32_e32 v110, 1, v81 + ds_read_b128 v[152:155], v110 + v_lshlrev_b32_e32 v110, 1, v82 + ds_read_b128 v[156:159], v110 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[116:117], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[124:125], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[132:133], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[140:141], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[114:115], v[118:119], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[114:115], v[126:127], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[114:115], v[134:135], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[114:115], v[142:143], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[122:123], v[118:119], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[122:123], v[126:127], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[122:123], v[134:135], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[122:123], v[142:143], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[146:147], v[118:119], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[146:147], v[126:127], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[146:147], v[134:135], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[142:143], a[240:255] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[118:119], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[126:127], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[134:135], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[154:155], v[142:143], a[48:63] + v_lshlrev_b32_e32 v110, 1, v83 + ds_read_b128 v[132:135], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v84 + ds_read_b128 v[122:125], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[128:129], v[132:133], a[96:111] + ds_read_b128 v[140:143], v107 offset:40960 + ds_read_b128 v[118:121], v108 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[128:129], v[140:141], a[80:95] + v_lshlrev_b32_e32 v110, 1, v85 + ds_read_b128 v[144:147], v110 offset:40960 + v_lshlrev_b32_e32 v110, 1, v86 + ds_read_b128 v[114:117], v110 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[128:129], v[144:145], a[64:79] + v_lshlrev_b32_e32 v110, 1, v87 + ds_read_b128 v[152:155], v110 offset:40960 + v_lshlrev_b32_e32 v110, 1, v88 + ds_read_b128 v[110:113], v110 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[152:153], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[136:137], v[132:133], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[136:137], v[140:141], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[136:137], v[144:145], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[136:137], v[152:153], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[148:149], v[132:133], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[148:149], v[140:141], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[148:149], v[144:145], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[152:153], a[240:255] + v_mfma_f32_32x32x8_bf16 a[16:31], v[156:157], v[132:133], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[156:157], v[140:141], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[156:157], v[144:145], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[156:157], v[152:153], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[130:131], v[134:135], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[130:131], v[142:143], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[130:131], v[146:147], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[130:131], v[154:155], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[138:139], v[134:135], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[138:139], v[142:143], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[138:139], v[146:147], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[138:139], v[154:155], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[134:135], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[142:143], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[146:147], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[154:155], a[240:255] + v_mfma_f32_32x32x8_bf16 a[16:31], v[158:159], v[134:135], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[158:159], v[142:143], a[32:47] + v_mfma_f32_32x32x8_bf16 a[0:15], v[158:159], v[146:147], a[0:15] + v_mfma_f32_32x32x8_bf16 a[48:63], v[158:159], v[154:155], a[48:63] + v_lshlrev_b32_e32 v126, 1, v67 + ds_read_b128 v[126:129], v126 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[126:127], v[122:123], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[126:127], v[118:119], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[126:127], v[110:111], a[128:143] + v_lshlrev_b32_e32 v126, 1, v71 + ds_read_b128 v[144:147], v126 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[144:145], v[122:123], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[144:145], v[118:119], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[144:145], v[114:115], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[144:145], v[110:111], a[176:191] + v_lshlrev_b32_e32 v126, 1, v73 + ds_read_b128 v[148:151], v126 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[148:149], v[122:123], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[148:149], v[118:119], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[148:149], v[114:115], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[110:111], a[240:255] + v_lshlrev_b32_e32 v126, 1, v74 + ds_read_b128 v[152:155], v126 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[122:123], a[16:31] + s_add_i32 s23, s3, -1 + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[118:119], a[32:47] + v_readfirstlane_b32 s24, v0 + s_lshr_b32 s25, s24, 2 + s_andn2_b32 s24, s24, 63 + s_and_b32 s25, s25, 0x3ffffff0 + v_add_u32_e32 v118, s24, v103 + v_add_u32_e32 v119, s25, v104 + v_lshl_or_b32 v122, v118, 6, v68 + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[114:115], a[0:15] + v_or_b32_e32 v114, 1, v118 + v_ashrrev_i32_e32 v115, 31, v118 + v_or_b32_e32 v123, 2, v118 + v_or_b32_e32 v126, 3, v118 + v_or_b32_e32 v127, 4, v118 + v_or_b32_e32 v130, 5, v118 + v_or_b32_e32 v131, 6, v118 + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[110:111], a[48:63] + v_or_b32_e32 v110, 7, v118 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s23 + v_lshrrev_b32_e32 v111, 2, v119 + v_lshlrev_b32_e32 v118, 9, v119 + v_lshlrev_b32_e32 v119, 6, v119 + v_lshlrev_b32_e32 v134, 1, v122 + v_mfma_f32_32x32x8_bf16 a[96:111], v[128:129], v[124:125], a[96:111] + v_lshrrev_b32_e32 v115, 29, v115 + v_and_b32_e32 v111, 24, v111 + v_and_b32_e32 v118, 0x3000, v118 + v_and_b32_e32 v119, 0xfffff800, v119 + v_add_u32_e32 v132, v114, v115 + v_add_u32_e32 v133, v123, v115 + v_add_u32_e32 v135, v126, v115 + v_mfma_f32_32x32x8_bf16 a[80:95], v[128:129], v[120:121], a[80:95] + v_add_u32_e32 v136, v127, v115 + v_add_u32_e32 v137, v130, v115 + v_add_u32_e32 v138, v131, v115 + v_add_u32_e32 v115, v110, v115 + v_xor_b32_e32 v139, v111, v72 + v_add_u32_e32 v118, v119, v118 + v_or_b32_e32 v119, 1, v111 + v_mfma_f32_32x32x8_bf16 a[64:79], v[128:129], v[116:117], a[64:79] + v_or_b32_e32 v140, 2, v111 + v_or_b32_e32 v141, 3, v111 + v_or_b32_e32 v142, 4, v111 + v_or_b32_e32 v143, 5, v111 + v_or_b32_e32 v144, 6, v111 + v_or_b32_e32 v111, 7, v111 + v_and_b32_e32 v132, -8, v132 + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[112:113], a[128:143] + v_and_b32_e32 v128, -8, v133 + v_and_b32_e32 v129, -8, v135 + v_and_b32_e32 v133, -8, v136 + v_and_b32_e32 v135, -8, v137 + v_and_b32_e32 v136, -8, v138 + v_and_b32_e32 v115, 0xffffff8, v115 + v_lshl_or_b32 v118, v139, 3, v118 + v_mfma_f32_32x32x8_bf16 a[112:127], v[146:147], v[124:125], a[112:127] + v_xor_b32_e32 v119, v119, v72 + v_xor_b32_e32 v137, v140, v72 + v_xor_b32_e32 v138, v141, v72 + v_xor_b32_e32 v140, v142, v72 + v_xor_b32_e32 v141, v143, v72 + v_xor_b32_e32 v142, v144, v72 + v_xor_b32_e32 v111, v111, v72 + v_mfma_f32_32x32x8_bf16 a[144:159], v[146:147], v[120:121], a[144:159] + v_sub_u32_e32 v114, v114, v132 + v_sub_u32_e32 v123, v123, v128 + v_sub_u32_e32 v126, v126, v129 + v_sub_u32_e32 v127, v127, v133 + v_sub_u32_e32 v128, v130, v135 + v_sub_u32_e32 v129, v131, v136 + v_sub_u32_e32 v110, v110, v115 + v_mfma_f32_32x32x8_bf16 a[160:175], v[146:147], v[116:117], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v135, 1, v118 + v_sub_u32_e32 v115, v119, v139 + v_sub_u32_e32 v119, v137, v119 + v_sub_u32_e32 v130, v138, v137 + v_sub_u32_e32 v131, v140, v138 + v_mfma_f32_32x32x8_bf16 a[176:191], v[146:147], v[112:113], a[176:191] + v_sub_u32_e32 v132, v141, v140 + v_sub_u32_e32 v133, v142, v141 + v_sub_u32_e32 v111, v111, v142 + v_xor_b32_e32 v114, v114, v69 + v_xor_b32_e32 v123, v123, v69 + v_xor_b32_e32 v126, v126, v69 + v_xor_b32_e32 v127, v127, v69 + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[124:125], a[192:207] + v_xor_b32_e32 v128, v128, v69 + v_xor_b32_e32 v129, v129, v69 + v_xor_b32_e32 v110, v110, v69 + v_lshlrev_b32_e32 v136, 3, v115 + v_lshlrev_b32_e32 v137, 3, v119 + v_lshl_add_u32 v138, v115, 4, v135 + v_lshlrev_b32_e32 v115, 3, v130 + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[120:121], a[208:223] + v_lshlrev_b32_e32 v139, 3, v131 + v_lshlrev_b32_e32 v119, 4, v119 + v_lshlrev_b32_e32 v140, 3, v132 + v_lshlrev_b32_e32 v141, 3, v133 + v_lshlrev_b32_e32 v130, 4, v130 + v_lshlrev_b32_e32 v111, 4, v111 + v_lshlrev_b32_e32 v131, 4, v131 + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[116:117], a[224:239] + v_lshlrev_b32_e32 v132, 4, v132 + v_lshlrev_b32_e32 v133, 4, v133 + v_sub_u32_e32 v142, v114, v69 + v_sub_u32_e32 v114, v123, v114 + v_sub_u32_e32 v123, v126, v123 + v_sub_u32_e32 v126, v127, v126 + v_sub_u32_e32 v127, v128, v127 + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[112:113], a[240:255] + v_sub_u32_e32 v128, v129, v128 + v_sub_u32_e32 v110, v110, v129 + v_add3_u32 v118, v136, v118, v137 + v_add3_u32 v136, v138, s22, v119 + v_lshl_add_u32 v119, v142, 3, v122 + v_lshl_add_u32 v137, v142, 4, v134 + v_lshlrev_b32_e32 v114, 3, v114 + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[124:125], a[16:31] + v_lshlrev_b32_e32 v122, 3, v123 + v_lshlrev_b32_e32 v123, 3, v126 + v_lshlrev_b32_e32 v124, 3, v127 + v_lshlrev_b32_e32 v125, 3, v128 + v_add3_u32 v115, v118, v115, v139 + v_add3_u32 v139, v136, s22, v130 + v_add3_u32 v114, v119, v114, 64 + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[120:121], a[32:47] + v_add3_u32 v115, v115, v140, v141 + v_add3_u32 v140, v139, s22, v131 + v_lshlrev_b32_e32 v141, 1, v114 + v_add3_u32 v114, v114, v122, 64 + v_lshl_add_u32 v142, v115, 1, v111 + v_add3_u32 v143, v140, s22, v132 + v_lshlrev_b32_e32 v144, 1, v114 + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[116:117], a[0:15] + v_add3_u32 v111, v114, v123, 64 + v_add3_u32 v145, v143, s22, v133 + v_lshlrev_b32_e32 v146, 1, v111 + v_add3_u32 v111, v111, v124, 64 + v_lshlrev_b32_e32 v147, 1, v111 + v_add_lshl_u32 v148, v111, v125, 1 + v_lshl_add_u32 v149, v110, 4, v148 + v_mfma_f32_32x32x8_bf16 a[48:63], v[154:155], v[112:113], a[48:63] + s_waitcnt vmcnt(13) + v_perm_b32 v110, v34, v38, s6 + v_perm_b32 v34, v34, v38, s21 + v_perm_b32 v38, v35, v39, s6 + v_perm_b32 v114, v35, v39, s21 + v_perm_b32 v118, v36, v40, s6 + v_perm_b32 v122, v36, v40, s21 + v_perm_b32 v126, v37, v41, s6 + v_perm_b32 v130, v37, v41, s21 + s_waitcnt vmcnt(9) + v_perm_b32 v111, v42, v46, s6 + v_perm_b32 v35, v42, v46, s21 + v_perm_b32 v39, v43, v47, s6 + v_perm_b32 v115, v43, v47, s21 + v_perm_b32 v119, v44, v48, s6 + v_perm_b32 v123, v44, v48, s21 + v_perm_b32 v127, v45, v49, s6 + v_perm_b32 v131, v45, v49, s21 + s_waitcnt vmcnt(5) + v_perm_b32 v112, v54, v62, s6 + v_perm_b32 v36, v54, v62, s21 + v_perm_b32 v40, v55, v63, s6 + v_perm_b32 v116, v55, v63, s21 + v_perm_b32 v120, v56, v64, s6 + v_perm_b32 v124, v56, v64, s21 + v_perm_b32 v128, v57, v65, s6 + v_perm_b32 v132, v57, v65, s21 + s_waitcnt vmcnt(2) + v_perm_b32 v113, v50, v58, s6 + v_perm_b32 v37, v50, v58, s21 + v_perm_b32 v41, v51, v59, s6 + v_perm_b32 v117, v51, v59, s21 + v_perm_b32 v121, v52, v60, s6 + v_perm_b32 v125, v52, v60, s21 + v_perm_b32 v129, v53, v61, s6 + v_perm_b32 v133, v53, v61, s21 + ds_write_b128 v135, v[110:113] + ds_write_b128 v138, v[34:37] offset:512 + ds_write_b128 v136, v[38:41] offset:512 + ds_write_b128 v139, v[114:117] offset:512 + ds_write_b128 v140, v[118:121] offset:512 + ds_write_b128 v143, v[122:125] offset:512 + ds_write_b128 v145, v[126:129] offset:512 + ds_write_b128 v142, v[130:133] offset:3584 + ds_write_b128 v134, v[2:5] offset:32768 + ds_write_b128 v137, v[6:9] offset:32896 + ds_write_b128 v141, v[10:13] offset:32896 + ds_write_b128 v144, v[14:17] offset:32896 + ds_write_b128 v146, v[18:21] offset:32896 + ds_write_b128 v147, v[22:25] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v148, v[26:29] offset:33024 + s_waitcnt vmcnt(0) + ds_write_b128 v149, v[30:33] offset:33152 + s_cbranch_scc1 .LBB9_8 +.LBB9_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE + v_accvgpr_read_b32 v140, a116 + v_accvgpr_read_b32 v141, a117 + v_accvgpr_read_b32 v142, a118 + v_accvgpr_read_b32 v143, a119 + v_accvgpr_read_b32 v144, a120 + v_accvgpr_read_b32 v145, a121 + v_accvgpr_read_b32 v146, a122 + v_accvgpr_read_b32 v147, a123 + v_accvgpr_read_b32 v148, a124 + v_accvgpr_read_b32 v149, a125 + v_accvgpr_read_b32 v150, a126 + v_accvgpr_read_b32 v151, a127 + v_accvgpr_read_b32 v120, a144 + v_accvgpr_read_b32 v121, a145 + v_accvgpr_read_b32 v122, a146 + v_accvgpr_read_b32 v123, a147 + v_accvgpr_read_b32 v124, a148 + v_accvgpr_read_b32 v125, a149 + v_accvgpr_read_b32 v126, a150 + v_accvgpr_read_b32 v127, a151 + v_accvgpr_read_b32 v128, a152 + v_accvgpr_read_b32 v129, a153 + v_accvgpr_read_b32 v130, a154 + v_accvgpr_read_b32 v131, a155 + v_accvgpr_read_b32 v132, a156 + v_accvgpr_read_b32 v133, a157 + v_accvgpr_read_b32 v134, a158 + v_accvgpr_read_b32 v135, a159 + v_accvgpr_mov_b32 a144, a176 + v_accvgpr_mov_b32 a145, a177 + v_accvgpr_mov_b32 a146, a178 + v_accvgpr_mov_b32 a147, a179 + v_accvgpr_mov_b32 a148, a180 + v_accvgpr_mov_b32 a149, a181 + v_accvgpr_mov_b32 a150, a182 + v_accvgpr_mov_b32 a151, a183 + v_accvgpr_mov_b32 a152, a184 + v_accvgpr_mov_b32 a153, a185 + v_accvgpr_mov_b32 a154, a186 + v_accvgpr_mov_b32 a155, a187 + v_accvgpr_mov_b32 a156, a188 + v_accvgpr_mov_b32 a157, a189 + v_accvgpr_mov_b32 a158, a190 + v_accvgpr_mov_b32 a159, a191 + v_accvgpr_mov_b32 a176, a192 + v_accvgpr_mov_b32 a177, a193 + v_accvgpr_mov_b32 a178, a194 + v_accvgpr_mov_b32 a179, a195 + v_accvgpr_mov_b32 a180, a196 + v_accvgpr_mov_b32 a181, a197 + v_accvgpr_mov_b32 a182, a198 + v_accvgpr_mov_b32 a183, a199 + v_accvgpr_mov_b32 a184, a200 + v_accvgpr_mov_b32 a185, a201 + v_accvgpr_mov_b32 a186, a202 + v_accvgpr_mov_b32 a187, a203 + v_accvgpr_mov_b32 a188, a204 + v_accvgpr_mov_b32 a189, a205 + v_accvgpr_mov_b32 a190, a206 + v_accvgpr_mov_b32 a191, a207 + v_accvgpr_read_b32 v104, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v106, a210 + v_accvgpr_read_b32 v107, a211 + v_accvgpr_read_b32 v108, a212 + v_accvgpr_read_b32 v109, a213 + v_accvgpr_read_b32 v110, a214 + v_accvgpr_read_b32 v111, a215 + v_accvgpr_read_b32 v112, a216 + v_accvgpr_read_b32 v113, a217 + v_accvgpr_read_b32 v114, a218 + v_accvgpr_read_b32 v115, a219 + v_accvgpr_read_b32 v116, a220 + v_accvgpr_read_b32 v117, a221 + v_accvgpr_read_b32 v118, a222 + v_accvgpr_read_b32 v119, a223 + v_accvgpr_read_b32 v50, a224 + v_accvgpr_read_b32 v51, a225 + v_accvgpr_read_b32 v52, a226 + v_accvgpr_read_b32 v53, a227 + v_accvgpr_read_b32 v54, a228 + v_accvgpr_read_b32 v55, a229 + v_accvgpr_read_b32 v56, a230 + v_accvgpr_read_b32 v57, a231 + v_accvgpr_read_b32 v58, a232 + v_accvgpr_read_b32 v59, a233 + v_accvgpr_read_b32 v60, a234 + v_accvgpr_read_b32 v61, a235 + v_accvgpr_read_b32 v62, a236 + v_accvgpr_read_b32 v63, a237 + v_accvgpr_read_b32 v64, a238 + v_accvgpr_read_b32 v65, a239 + v_accvgpr_read_b32 v34, a240 + v_accvgpr_read_b32 v35, a241 + v_accvgpr_read_b32 v36, a242 + v_accvgpr_read_b32 v37, a243 + v_accvgpr_read_b32 v38, a244 + v_accvgpr_read_b32 v39, a245 + v_accvgpr_read_b32 v40, a246 + v_accvgpr_read_b32 v41, a247 + v_accvgpr_read_b32 v42, a248 + v_accvgpr_read_b32 v43, a249 + v_accvgpr_read_b32 v44, a250 + v_accvgpr_read_b32 v45, a251 + v_accvgpr_read_b32 v46, a252 + v_accvgpr_read_b32 v47, a253 + v_accvgpr_read_b32 v48, a254 + v_accvgpr_read_b32 v49, a255 + v_accvgpr_read_b32 v18, a16 + v_accvgpr_read_b32 v19, a17 + v_accvgpr_read_b32 v20, a18 + v_accvgpr_read_b32 v21, a19 + v_accvgpr_read_b32 v22, a20 + v_accvgpr_read_b32 v23, a21 + v_accvgpr_read_b32 v24, a22 + v_accvgpr_read_b32 v25, a23 + v_accvgpr_read_b32 v26, a24 + v_accvgpr_read_b32 v27, a25 + v_accvgpr_read_b32 v28, a26 + v_accvgpr_read_b32 v29, a27 + v_accvgpr_read_b32 v30, a28 + v_accvgpr_read_b32 v31, a29 + v_accvgpr_read_b32 v32, a30 + v_accvgpr_read_b32 v33, a31 + v_accvgpr_read_b32 v2, a32 + v_accvgpr_read_b32 v3, a33 + v_accvgpr_read_b32 v4, a34 + v_accvgpr_read_b32 v5, a35 + v_accvgpr_read_b32 v6, a36 + v_accvgpr_read_b32 v7, a37 + v_accvgpr_read_b32 v8, a38 + v_accvgpr_read_b32 v9, a39 + v_accvgpr_read_b32 v10, a40 + v_accvgpr_read_b32 v11, a41 + v_accvgpr_read_b32 v12, a42 + v_accvgpr_read_b32 v13, a43 + v_accvgpr_read_b32 v14, a44 + v_accvgpr_read_b32 v15, a45 + v_accvgpr_read_b32 v16, a46 + v_accvgpr_read_b32 v17, a47 + v_accvgpr_mov_b32 a16, a0 + v_accvgpr_mov_b32 a17, a1 + v_accvgpr_mov_b32 a18, a2 + v_accvgpr_mov_b32 a19, a3 + v_accvgpr_mov_b32 a20, a4 + v_accvgpr_mov_b32 a21, a5 + v_accvgpr_mov_b32 a22, a6 + v_accvgpr_mov_b32 a23, a7 + v_accvgpr_mov_b32 a24, a8 + v_accvgpr_mov_b32 a25, a9 + v_accvgpr_mov_b32 a26, a10 + v_accvgpr_mov_b32 a27, a11 + v_accvgpr_mov_b32 a28, a12 + v_accvgpr_mov_b32 a29, a13 + v_accvgpr_mov_b32 a30, a14 + v_accvgpr_mov_b32 a31, a15 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + v_accvgpr_read_b32 v139, a115 + v_accvgpr_read_b32 v138, a114 + v_accvgpr_read_b32 v137, a113 + v_accvgpr_read_b32 v136, a112 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[152:155], v102 + ds_read_b128 v[156:159], v101 offset:32768 + v_accvgpr_mov_b32 a0, a96 + v_accvgpr_mov_b32 a1, a97 + v_accvgpr_mov_b32 a2, a98 + v_accvgpr_mov_b32 a3, a99 + v_accvgpr_mov_b32 a4, a100 + v_accvgpr_mov_b32 a5, a101 + v_accvgpr_mov_b32 a6, a102 + v_accvgpr_mov_b32 a7, a103 + v_accvgpr_mov_b32 a8, a104 + v_accvgpr_mov_b32 a9, a105 + v_accvgpr_mov_b32 a10, a106 + v_accvgpr_mov_b32 a11, a107 + v_accvgpr_mov_b32 a12, a108 + v_accvgpr_mov_b32 a13, a109 + v_accvgpr_mov_b32 a14, a110 + v_accvgpr_mov_b32 a15, a111 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[156:157], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[158:159], a[0:15] + v_lshlrev_b32_e32 v66, 1, v97 + ds_read_b128 v[160:163], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v100 + v_accvgpr_mov_b32 a32, a80 + v_accvgpr_mov_b32 a33, a81 + v_accvgpr_mov_b32 a34, a82 + v_accvgpr_mov_b32 a35, a83 + v_accvgpr_mov_b32 a36, a84 + v_accvgpr_mov_b32 a37, a85 + v_accvgpr_mov_b32 a38, a86 + v_accvgpr_mov_b32 a39, a87 + v_accvgpr_mov_b32 a40, a88 + v_accvgpr_mov_b32 a41, a89 + v_accvgpr_mov_b32 a42, a90 + v_accvgpr_mov_b32 a43, a91 + v_accvgpr_mov_b32 a44, a92 + v_accvgpr_mov_b32 a45, a93 + v_accvgpr_mov_b32 a46, a94 + v_accvgpr_mov_b32 a47, a95 + ds_read_b128 v[100:103], v66 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[160:161], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[162:163], a[32:47] + v_lshlrev_b32_e32 v66, 1, v98 + ds_read_b128 v[164:167], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v99 + ds_read_b128 v[168:171], v66 offset:32768 + v_accvgpr_mov_b32 a127, a79 + v_accvgpr_mov_b32 a126, a78 + v_accvgpr_mov_b32 a125, a77 + v_accvgpr_mov_b32 a124, a76 + v_accvgpr_mov_b32 a123, a75 + v_accvgpr_mov_b32 a122, a74 + v_accvgpr_mov_b32 a121, a73 + v_accvgpr_mov_b32 a120, a72 + v_accvgpr_mov_b32 a119, a71 + v_accvgpr_mov_b32 a118, a70 + v_accvgpr_mov_b32 a117, a69 + v_accvgpr_mov_b32 a116, a68 + v_accvgpr_mov_b32 a115, a67 + v_accvgpr_mov_b32 a114, a66 + v_accvgpr_mov_b32 a113, a65 + v_accvgpr_mov_b32 a112, a64 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[112:127], v[152:153], v[164:165], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[154:155], v[166:167], a[112:127] + v_lshlrev_b32_e32 v66, 1, v95 + ds_read_b128 v[172:175], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v96 + ds_read_b128 v[96:99], v66 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[208:223], v[152:153], v[172:173], a[208:223] + v_lshlrev_b32_e32 v66, 1, v94 + v_mfma_f32_32x32x8_bf16 a[208:223], v[154:155], v[174:175], a[208:223] + ds_read_b128 v[152:155], v66 + v_accvgpr_write_b32 a239, v151 + v_accvgpr_write_b32 a238, v150 + v_accvgpr_write_b32 a237, v149 + v_accvgpr_write_b32 a236, v148 + v_accvgpr_write_b32 a235, v147 + v_accvgpr_write_b32 a234, v146 + v_accvgpr_write_b32 a233, v145 + v_accvgpr_write_b32 a232, v144 + v_accvgpr_write_b32 a231, v143 + v_accvgpr_write_b32 a230, v142 + v_accvgpr_write_b32 a229, v141 + v_accvgpr_write_b32 a228, v140 + v_accvgpr_write_b32 a227, v139 + v_accvgpr_write_b32 a226, v138 + v_accvgpr_write_b32 a225, v137 + v_accvgpr_write_b32 a224, v136 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[152:153], v[156:157], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[154:155], v[158:159], a[224:239] + v_accvgpr_write_b32 a207, v135 + v_accvgpr_write_b32 a206, v134 + v_accvgpr_write_b32 a205, v133 + v_accvgpr_write_b32 a204, v132 + v_accvgpr_write_b32 a203, v131 + v_accvgpr_write_b32 a202, v130 + v_accvgpr_write_b32 a201, v129 + v_accvgpr_write_b32 a200, v128 + v_accvgpr_write_b32 a199, v127 + v_accvgpr_write_b32 a198, v126 + v_accvgpr_write_b32 a197, v125 + v_accvgpr_write_b32 a196, v124 + v_accvgpr_write_b32 a195, v123 + v_accvgpr_write_b32 a194, v122 + v_accvgpr_write_b32 a193, v121 + v_accvgpr_write_b32 a192, v120 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[192:207], v[152:153], v[160:161], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[154:155], v[162:163], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[152:153], v[164:165], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[154:155], v[166:167], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[152:153], v[172:173], a[144:159] + v_lshlrev_b32_e32 v66, 1, v93 + v_mfma_f32_32x32x8_bf16 a[144:159], v[154:155], v[174:175], a[144:159] + ds_read_b128 v[120:123], v66 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[120:121], v[156:157], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[122:123], v[158:159], a[176:191] + v_accvgpr_write_b32 a143, v119 + v_accvgpr_write_b32 a142, v118 + v_accvgpr_write_b32 a141, v117 + v_accvgpr_write_b32 a140, v116 + v_accvgpr_write_b32 a139, v115 + v_accvgpr_write_b32 a138, v114 + v_accvgpr_write_b32 a137, v113 + v_accvgpr_write_b32 a136, v112 + v_accvgpr_write_b32 a135, v111 + v_accvgpr_write_b32 a134, v110 + v_accvgpr_write_b32 a133, v109 + v_accvgpr_write_b32 a132, v108 + v_accvgpr_write_b32 a131, v107 + v_accvgpr_write_b32 a130, v106 + v_accvgpr_write_b32 a129, v105 + v_accvgpr_write_b32 a128, v104 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[128:143], v[120:121], v[160:161], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[122:123], v[162:163], a[128:143] + v_accvgpr_write_b32 a95, v65 + v_accvgpr_write_b32 a94, v64 + v_accvgpr_write_b32 a93, v63 + v_accvgpr_write_b32 a92, v62 + v_accvgpr_write_b32 a91, v61 + v_accvgpr_write_b32 a90, v60 + v_accvgpr_write_b32 a89, v59 + v_accvgpr_write_b32 a88, v58 + v_accvgpr_write_b32 a87, v57 + v_accvgpr_write_b32 a86, v56 + v_accvgpr_write_b32 a85, v55 + v_accvgpr_write_b32 a84, v54 + v_accvgpr_write_b32 a83, v53 + v_accvgpr_write_b32 a82, v52 + v_accvgpr_write_b32 a81, v51 + v_accvgpr_write_b32 a80, v50 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[80:95], v[120:121], v[164:165], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[122:123], v[166:167], a[80:95] + v_accvgpr_write_b32 a79, v49 + v_accvgpr_write_b32 a78, v48 + v_accvgpr_write_b32 a77, v47 + v_accvgpr_write_b32 a76, v46 + v_accvgpr_write_b32 a75, v45 + v_accvgpr_write_b32 a74, v44 + v_accvgpr_write_b32 a73, v43 + v_accvgpr_write_b32 a72, v42 + v_accvgpr_write_b32 a71, v41 + v_accvgpr_write_b32 a70, v40 + v_accvgpr_write_b32 a69, v39 + v_accvgpr_write_b32 a68, v38 + v_accvgpr_write_b32 a67, v37 + v_accvgpr_write_b32 a66, v36 + v_accvgpr_write_b32 a65, v35 + v_accvgpr_write_b32 a64, v34 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[64:79], v[120:121], v[172:173], a[64:79] + v_lshlrev_b32_e32 v34, 1, v92 + v_mfma_f32_32x32x8_bf16 a[64:79], v[122:123], v[174:175], a[64:79] + ds_read_b128 v[34:37], v34 + v_accvgpr_write_b32 a111, v33 + v_accvgpr_write_b32 a110, v32 + v_accvgpr_write_b32 a109, v31 + v_accvgpr_write_b32 a108, v30 + v_accvgpr_write_b32 a107, v29 + v_accvgpr_write_b32 a106, v28 + v_accvgpr_write_b32 a105, v27 + v_accvgpr_write_b32 a104, v26 + v_accvgpr_write_b32 a103, v25 + v_accvgpr_write_b32 a102, v24 + v_accvgpr_write_b32 a101, v23 + v_accvgpr_write_b32 a100, v22 + v_accvgpr_write_b32 a99, v21 + v_accvgpr_write_b32 a98, v20 + v_accvgpr_write_b32 a97, v19 + v_accvgpr_write_b32 a96, v18 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[34:35], v[156:157], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[36:37], v[158:159], a[96:111] + v_accvgpr_write_b32 a63, v17 + v_accvgpr_write_b32 a62, v16 + v_accvgpr_write_b32 a61, v15 + v_accvgpr_write_b32 a60, v14 + v_accvgpr_write_b32 a59, v13 + v_accvgpr_write_b32 a58, v12 + v_accvgpr_write_b32 a57, v11 + v_accvgpr_write_b32 a56, v10 + v_accvgpr_write_b32 a55, v9 + v_accvgpr_write_b32 a54, v8 + v_accvgpr_write_b32 a53, v7 + v_accvgpr_write_b32 a52, v6 + v_accvgpr_write_b32 a51, v5 + v_accvgpr_write_b32 a50, v4 + v_accvgpr_write_b32 a49, v3 + v_accvgpr_write_b32 a48, v2 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[48:63], v[34:35], v[160:161], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[36:37], v[162:163], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[34:35], v[164:165], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[36:37], v[166:167], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[34:35], v[172:173], a[240:255] + v_lshlrev_b32_e32 v2, 1, v75 + v_mfma_f32_32x32x8_bf16 a[240:255], v[36:37], v[174:175], a[240:255] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v91 + ds_read_b128 v[8:11], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v76 + ds_read_b128 v[12:15], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[8:9], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[6:7], v[10:11], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[100:101], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[6:7], v[102:103], a[32:47] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[168:169], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[6:7], v[170:171], a[112:127] + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[96:97], a[208:223] + v_lshlrev_b32_e32 v2, 1, v77 + v_mfma_f32_32x32x8_bf16 a[208:223], v[6:7], v[98:99], a[208:223] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v78 + ds_read_b128 v[16:19], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[6:7], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[100:101], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[6:7], v[102:103], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[168:169], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[6:7], v[170:171], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[96:97], a[144:159] + v_lshlrev_b32_e32 v2, 1, v79 + v_mfma_f32_32x32x8_bf16 a[144:159], v[6:7], v[98:99], a[144:159] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v80 + ds_read_b128 v[20:23], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[6:7], v[10:11], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[100:101], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[6:7], v[102:103], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[168:169], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[6:7], v[170:171], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[96:97], a[64:79] + v_lshlrev_b32_e32 v2, 1, v81 + v_mfma_f32_32x32x8_bf16 a[64:79], v[6:7], v[98:99], a[64:79] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v82 + ds_read_b128 v[24:27], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[6:7], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[100:101], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[6:7], v[102:103], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[168:169], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[170:171], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[96:97], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[98:99], a[240:255] + v_lshlrev_b32_e32 v2, 1, v83 + ds_read_b128 v[4:7], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v84 + ds_read_b128 v[8:11], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[12:13], v[4:5], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[14:15], v[6:7], a[0:15] + v_lshlrev_b32_e32 v2, 1, v85 + ds_read_b128 v[28:31], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v86 + ds_read_b128 v[32:35], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[12:13], v[28:29], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[14:15], v[30:31], a[32:47] + v_lshlrev_b32_e32 v2, 1, v87 + ds_read_b128 v[36:39], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v88 + ds_read_b128 v[40:43], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[12:13], v[36:37], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[14:15], v[38:39], a[112:127] + v_lshlrev_b32_e32 v2, 1, v89 + ds_read_b128 v[44:47], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v90 + ds_read_b128 v[48:51], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[14:15], v[46:47], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[18:19], v[6:7], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[18:19], v[30:31], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[18:19], v[38:39], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[16:17], v[44:45], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[18:19], v[46:47], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[20:21], v[4:5], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[22:23], v[6:7], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[20:21], v[28:29], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[22:23], v[30:31], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[20:21], v[36:37], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[22:23], v[38:39], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[20:21], v[44:45], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[22:23], v[46:47], a[64:79] + v_mfma_f32_32x32x8_bf16 a[96:111], v[24:25], v[4:5], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[26:27], v[6:7], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[24:25], v[28:29], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[26:27], v[30:31], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[24:25], v[36:37], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[26:27], v[38:39], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[24:25], v[44:45], a[240:255] + v_lshlrev_b32_e32 v2, 1, v67 + v_mfma_f32_32x32x8_bf16 a[240:255], v[26:27], v[46:47], a[240:255] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[2:3], v[8:9], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[10:11], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[2:3], v[32:33], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[34:35], a[32:47] + v_mfma_f32_32x32x8_bf16 a[112:127], v[2:3], v[40:41], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[42:43], a[112:127] + v_mfma_f32_32x32x8_bf16 a[208:223], v[2:3], v[48:49], a[208:223] + v_lshlrev_b32_e32 v2, 1, v71 + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[50:51], a[208:223] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[34:35], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[42:43], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[2:3], v[48:49], a[144:159] + v_lshlrev_b32_e32 v2, 1, v73 + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[50:51], a[144:159] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[2:3], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[10:11], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[2:3], v[32:33], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[34:35], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[2:3], v[40:41], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[42:43], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[2:3], v[48:49], a[64:79] + v_lshlrev_b32_e32 v2, 1, v74 + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[50:51], a[64:79] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[2:3], v[32:33], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[34:35], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[2:3], v[40:41], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[42:43], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[2:3], v[48:49], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[50:51], a[240:255] +.LBB9_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4 + v_accvgpr_read_b32 v73, a0 + v_accvgpr_read_b32 v72, a1 + v_accvgpr_read_b32 v71, a2 + v_accvgpr_read_b32 v70, a3 + v_accvgpr_read_b32 v68, a4 + v_accvgpr_read_b32 v67, a5 + v_accvgpr_read_b32 v66, a6 + v_accvgpr_read_b32 v65, a7 + v_accvgpr_read_b32 v64, a8 + v_accvgpr_read_b32 v63, a9 + v_accvgpr_read_b32 v62, a10 + v_accvgpr_read_b32 v61, a11 + v_accvgpr_read_b32 v60, a12 + v_accvgpr_read_b32 v59, a13 + v_accvgpr_read_b32 v58, a14 + v_accvgpr_read_b32 v56, a15 + v_accvgpr_read_b32 v252, a32 + v_accvgpr_read_b32 v251, a33 + v_accvgpr_read_b32 v250, a34 + v_accvgpr_read_b32 v249, a35 + v_accvgpr_read_b32 v248, a36 + v_accvgpr_read_b32 v247, a37 + v_accvgpr_read_b32 v246, a38 + v_accvgpr_read_b32 v245, a39 + v_accvgpr_read_b32 v244, a40 + v_accvgpr_read_b32 v243, a41 + v_accvgpr_read_b32 v242, a42 + v_accvgpr_read_b32 v241, a43 + v_accvgpr_read_b32 v240, a44 + v_accvgpr_read_b32 v239, a45 + v_accvgpr_read_b32 v238, a46 + v_accvgpr_read_b32 v236, a47 + v_accvgpr_read_b32 v220, a112 + v_accvgpr_read_b32 v219, a113 + v_accvgpr_read_b32 v218, a114 + v_accvgpr_read_b32 v217, a115 + v_accvgpr_read_b32 v216, a116 + v_accvgpr_read_b32 v215, a117 + v_accvgpr_read_b32 v214, a118 + v_accvgpr_read_b32 v213, a119 + v_accvgpr_read_b32 v212, a120 + v_accvgpr_read_b32 v211, a121 + v_accvgpr_read_b32 v210, a122 + v_accvgpr_read_b32 v209, a123 + v_accvgpr_read_b32 v208, a124 + v_accvgpr_read_b32 v207, a125 + v_accvgpr_read_b32 v206, a126 + v_accvgpr_read_b32 v204, a127 + v_accvgpr_read_b32 v188, a208 + v_accvgpr_read_b32 v187, a209 + v_accvgpr_read_b32 v186, a210 + v_accvgpr_read_b32 v185, a211 + v_accvgpr_read_b32 v184, a212 + v_accvgpr_read_b32 v183, a213 + v_accvgpr_read_b32 v182, a214 + v_accvgpr_read_b32 v181, a215 + v_accvgpr_read_b32 v180, a216 + v_accvgpr_read_b32 v179, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v177, a219 + v_accvgpr_read_b32 v176, a220 + v_accvgpr_read_b32 v175, a221 + v_accvgpr_read_b32 v174, a222 + v_accvgpr_read_b32 v172, a223 + v_accvgpr_read_b32 v57, a224 + v_accvgpr_read_b32 v55, a225 + v_accvgpr_read_b32 v54, a226 + v_accvgpr_read_b32 v53, a227 + v_accvgpr_read_b32 v52, a228 + v_accvgpr_read_b32 v51, a229 + v_accvgpr_read_b32 v50, a230 + v_accvgpr_read_b32 v49, a231 + v_accvgpr_read_b32 v48, a232 + v_accvgpr_read_b32 v47, a233 + v_accvgpr_read_b32 v46, a234 + v_accvgpr_read_b32 v45, a235 + v_accvgpr_read_b32 v44, a236 + v_accvgpr_read_b32 v255, a237 + v_accvgpr_read_b32 v254, a238 + v_accvgpr_read_b32 v253, a239 + v_accvgpr_read_b32 v237, a192 + v_accvgpr_read_b32 v235, a193 + v_accvgpr_read_b32 v234, a194 + v_accvgpr_read_b32 v233, a195 + v_accvgpr_read_b32 v232, a196 + v_accvgpr_read_b32 v231, a197 + v_accvgpr_read_b32 v230, a198 + v_accvgpr_read_b32 v229, a199 + v_accvgpr_read_b32 v228, a200 + v_accvgpr_read_b32 v227, a201 + v_accvgpr_read_b32 v226, a202 + v_accvgpr_read_b32 v225, a203 + v_accvgpr_read_b32 v224, a204 + v_accvgpr_read_b32 v223, a205 + v_accvgpr_read_b32 v222, a206 + v_accvgpr_read_b32 v221, a207 + v_accvgpr_read_b32 v205, a160 + v_accvgpr_read_b32 v203, a161 + v_accvgpr_read_b32 v202, a162 + v_accvgpr_read_b32 v201, a163 + v_accvgpr_read_b32 v200, a164 + v_accvgpr_read_b32 v199, a165 + v_accvgpr_read_b32 v198, a166 + v_accvgpr_read_b32 v197, a167 + v_accvgpr_read_b32 v196, a168 + v_accvgpr_read_b32 v195, a169 + v_accvgpr_read_b32 v194, a170 + v_accvgpr_read_b32 v193, a171 + v_accvgpr_read_b32 v192, a172 + v_accvgpr_read_b32 v191, a173 + v_accvgpr_read_b32 v190, a174 + v_accvgpr_read_b32 v189, a175 + v_accvgpr_read_b32 v173, a144 + v_accvgpr_read_b32 v171, a145 + v_accvgpr_read_b32 v170, a146 + v_accvgpr_read_b32 v169, a147 + v_accvgpr_read_b32 v168, a148 + v_accvgpr_read_b32 v167, a149 + v_accvgpr_read_b32 v166, a150 + v_accvgpr_read_b32 v165, a151 + v_accvgpr_read_b32 v164, a152 + v_accvgpr_read_b32 v163, a153 + v_accvgpr_read_b32 v162, a154 + v_accvgpr_read_b32 v161, a155 + v_accvgpr_read_b32 v160, a156 + v_accvgpr_read_b32 v159, a157 + v_accvgpr_read_b32 v158, a158 + v_accvgpr_read_b32 v157, a159 + v_accvgpr_mov_b32 a47, a176 + v_accvgpr_mov_b32 a46, a177 + v_accvgpr_mov_b32 a45, a178 + v_accvgpr_mov_b32 a44, a179 + v_accvgpr_mov_b32 a43, a180 + v_accvgpr_mov_b32 a42, a181 + v_accvgpr_mov_b32 a41, a182 + v_accvgpr_mov_b32 a40, a183 + v_accvgpr_mov_b32 a39, a184 + v_accvgpr_mov_b32 a38, a185 + v_accvgpr_mov_b32 a37, a186 + v_accvgpr_mov_b32 a36, a187 + v_accvgpr_mov_b32 a35, a188 + v_accvgpr_mov_b32 a34, a189 + v_accvgpr_mov_b32 a33, a190 + v_accvgpr_mov_b32 a15, a191 + v_accvgpr_read_b32 v108, a128 + v_accvgpr_read_b32 v107, a129 + v_accvgpr_read_b32 v106, a130 + v_accvgpr_read_b32 v105, a131 + v_accvgpr_read_b32 v104, a132 + v_accvgpr_read_b32 v103, a133 + v_accvgpr_read_b32 v102, a134 + v_accvgpr_read_b32 v101, a135 + v_accvgpr_read_b32 v100, a136 + v_accvgpr_read_b32 v99, a137 + v_accvgpr_read_b32 v98, a138 + v_accvgpr_read_b32 v97, a139 + v_accvgpr_read_b32 v96, a140 + v_accvgpr_read_b32 v95, a141 + v_accvgpr_read_b32 v94, a142 + v_accvgpr_read_b32 v92, a143 + v_accvgpr_read_b32 v140, a80 + v_accvgpr_read_b32 v139, a81 + v_accvgpr_read_b32 v138, a82 + v_accvgpr_read_b32 v137, a83 + v_accvgpr_read_b32 v136, a84 + v_accvgpr_read_b32 v135, a85 + v_accvgpr_read_b32 v134, a86 + v_accvgpr_read_b32 v133, a87 + v_accvgpr_read_b32 v132, a88 + v_accvgpr_read_b32 v131, a89 + v_accvgpr_read_b32 v130, a90 + v_accvgpr_read_b32 v129, a91 + v_accvgpr_read_b32 v128, a92 + v_accvgpr_read_b32 v127, a93 + v_accvgpr_read_b32 v126, a94 + v_accvgpr_read_b32 v124, a95 + v_accvgpr_read_b32 v156, a64 + v_accvgpr_read_b32 v155, a65 + v_accvgpr_read_b32 v154, a66 + v_accvgpr_read_b32 v153, a67 + v_accvgpr_read_b32 v152, a68 + v_accvgpr_read_b32 v151, a69 + v_accvgpr_read_b32 v150, a70 + v_accvgpr_read_b32 v149, a71 + v_accvgpr_read_b32 v148, a72 + v_accvgpr_read_b32 v147, a73 + v_accvgpr_read_b32 v146, a74 + v_accvgpr_read_b32 v145, a75 + v_accvgpr_read_b32 v144, a76 + v_accvgpr_read_b32 v143, a77 + v_accvgpr_read_b32 v142, a78 + v_accvgpr_read_b32 v141, a79 + v_accvgpr_mov_b32 a32, a96 + v_accvgpr_mov_b32 a14, a97 + v_accvgpr_mov_b32 a13, a98 + v_accvgpr_mov_b32 a12, a99 + v_accvgpr_mov_b32 a11, a100 + v_accvgpr_mov_b32 a10, a101 + v_accvgpr_mov_b32 a9, a102 + v_accvgpr_mov_b32 a8, a103 + v_accvgpr_mov_b32 a7, a104 + v_accvgpr_mov_b32 a6, a105 + v_accvgpr_mov_b32 a5, a106 + v_accvgpr_mov_b32 a4, a107 + v_accvgpr_mov_b32 a3, a108 + v_accvgpr_mov_b32 a2, a109 + v_accvgpr_mov_b32 a1, a110 + v_accvgpr_read_b32 v86, a111 + v_accvgpr_read_b32 v93, a48 + v_accvgpr_read_b32 v91, a49 + v_accvgpr_read_b32 v90, a50 + v_accvgpr_read_b32 v89, a51 + v_accvgpr_read_b32 v88, a52 + v_accvgpr_mov_b32 a65, a53 + v_accvgpr_mov_b32 a64, a54 + v_accvgpr_mov_b32 a54, a56 + v_accvgpr_mov_b32 a53, a57 + v_accvgpr_mov_b32 a52, a58 + v_accvgpr_mov_b32 a51, a59 + v_accvgpr_mov_b32 a50, a60 + v_accvgpr_mov_b32 a49, a61 + v_accvgpr_read_b32 v87, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v125, a16 + v_accvgpr_read_b32 v123, a17 + v_accvgpr_read_b32 v122, a18 + v_accvgpr_read_b32 v121, a19 + v_accvgpr_read_b32 v120, a20 + v_accvgpr_read_b32 v119, a21 + v_accvgpr_read_b32 v118, a22 + v_accvgpr_read_b32 v117, a23 + v_accvgpr_read_b32 v116, a24 + v_accvgpr_read_b32 v115, a25 + v_accvgpr_read_b32 v114, a26 + v_accvgpr_read_b32 v113, a27 + v_accvgpr_read_b32 v112, a28 + v_accvgpr_read_b32 v111, a29 + v_accvgpr_read_b32 v110, a30 + v_accvgpr_read_b32 v109, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mov_b64 s[2:3], -1 + s_cmp_lg_u32 s17, 1 + s_cbranch_scc1 .LBB9_13 +; %bb.11: ; %Flow1281 + s_and_b64 vcc, exec, s[2:3] + s_cbranch_vccnz .LBB9_2190 +.LBB9_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESE_NSD_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB9_13: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.14: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 +; %bb.15: ; %Flow1024 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.16: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.17: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i304.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.18: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v19, v72, v19, s7 +; %bb.19: ; %Flow1023 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.20: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v72, vcc +; %bb.21: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i307.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.22: + v_bfe_u32 v20, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v71, v20, s7 +; %bb.23: ; %Flow1022 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.24: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v71, vcc +; %bb.25: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i310.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.26: + v_bfe_u32 v21, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v70, v21, s7 +; %bb.27: ; %Flow1021 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.28: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v70, vcc +; %bb.29: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i313.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.30: + v_bfe_u32 v22, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v68, v22, s7 +; %bb.31: ; %Flow1020 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.32: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v68, vcc +; %bb.33: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i316.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.34: + v_bfe_u32 v23, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v67, v23, s7 +; %bb.35: ; %Flow1019 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.36: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v67, vcc +; %bb.37: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i319.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.38: + v_bfe_u32 v24, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v66, v24, s7 +; %bb.39: ; %Flow1018 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.40: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v66, vcc +; %bb.41: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i322.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.42: + v_bfe_u32 v25, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v65, v25, s7 +; %bb.43: ; %Flow1017 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.44: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v65, vcc +; %bb.45: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i325.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.46: + v_bfe_u32 v26, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v64, v26, s7 +; %bb.47: ; %Flow1016 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.48: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v64, vcc +; %bb.49: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i328.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.50: + v_bfe_u32 v27, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v63, v27, s7 +; %bb.51: ; %Flow1015 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.52: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v63, vcc +; %bb.53: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i331.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.54: + v_bfe_u32 v28, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v62, v28, s7 +; %bb.55: ; %Flow1014 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.56: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v62, vcc +; %bb.57: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i334.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.58: + v_bfe_u32 v29, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v61, v29, s7 +; %bb.59: ; %Flow1013 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.60: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v61, vcc +; %bb.61: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i337.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.62: + v_bfe_u32 v30, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v60, v30, s7 +; %bb.63: ; %Flow1012 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.64: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v60, vcc +; %bb.65: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i340.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.66: + v_bfe_u32 v31, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v59, v31, s7 +; %bb.67: ; %Flow1011 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.68: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v59, vcc +; %bb.69: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i343.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.70: + v_bfe_u32 v32, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v58, v32, s7 +; %bb.71: ; %Flow1010 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.72: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v58, vcc +; %bb.73: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i346.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.74: + v_bfe_u32 v33, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v56, v33, s7 +; %bb.75: ; %Flow1009 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.76: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v56, vcc +; %bb.77: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i349.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.78: + v_bfe_u32 v34, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v57, v34, s7 +; %bb.79: ; %Flow1008 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.80: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v57, vcc +; %bb.81: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i352.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.82: + v_bfe_u32 v35, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v55, v35, s7 +; %bb.83: ; %Flow1007 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.84: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v55, vcc +; %bb.85: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i355.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.86: + v_bfe_u32 v36, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v54, v36, s7 +; %bb.87: ; %Flow1006 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.88: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v54, vcc +; %bb.89: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i358.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.90: + v_bfe_u32 v37, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v53, v37, s7 +; %bb.91: ; %Flow1005 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.92: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v53, vcc +; %bb.93: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i361.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.94: + v_bfe_u32 v38, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v52, v38, s7 +; %bb.95: ; %Flow1004 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.96: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v52, vcc +; %bb.97: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i364.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.98: + v_bfe_u32 v39, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v51, v39, s7 +; %bb.99: ; %Flow1003 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.100: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v51, vcc +; %bb.101: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i367.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.102: + v_bfe_u32 v40, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v50, v40, s7 +; %bb.103: ; %Flow1002 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.104: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v50, vcc +; %bb.105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i370.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.106: + v_bfe_u32 v41, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v49, v41, s7 +; %bb.107: ; %Flow1001 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.108: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v49, vcc +; %bb.109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i373.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.110: + v_bfe_u32 v42, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v48, v42, s7 +; %bb.111: ; %Flow1000 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.112: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v48, vcc +; %bb.113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i376.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.114: + v_bfe_u32 v43, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v47, v43, s7 +; %bb.115: ; %Flow999 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.116: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v74, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v74, v47, vcc +; %bb.117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i379.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr75 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.118: + v_bfe_u32 v74, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v75, v46, v74, s7 +; %bb.119: ; %Flow998 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.120: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v75, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v75, v75, v46, vcc +; %bb.121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i382.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.122: + v_bfe_u32 v74, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v76, v45, v74, s7 +; %bb.123: ; %Flow997 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.124: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v76, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v45, vcc +; %bb.125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i385.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.126: + v_bfe_u32 v74, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v77, v44, v74, s7 +; %bb.127: ; %Flow996 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.128: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v77, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v44, vcc +; %bb.129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i388.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.130: + v_bfe_u32 v74, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v78, v255, v74, s7 +; %bb.131: ; %Flow995 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.132: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v78, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v255, vcc +; %bb.133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i391.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.134: + v_bfe_u32 v74, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v79, v254, v74, s7 +; %bb.135: ; %Flow994 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.136: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v79, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v254, vcc +; %bb.137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i394.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.138: + v_bfe_u32 v74, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v80, v253, v74, s7 +; %bb.139: ; %Flow993 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.140: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v80, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v253, vcc +; %bb.141: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1ELi2E + s_or_b64 exec, exec, s[2:3] + v_and_b32_e32 v74, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v81, 3, v1 + v_and_or_b32 v81, v81, 12, s2 + v_lshlrev_b32_e32 v81, 7, v81 + v_lshl_or_b32 v81, v69, 1, v81 + v_lshlrev_b32_e32 v74, 1, v74 + s_and_b32 s2, s6, 64 + v_or3_b32 v74, v81, v74, s2 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v38 offset:9216 + ds_write_b16_d16_hi v74, v39 offset:9344 + ds_write_b16_d16_hi v74, v40 offset:9472 + ds_write_b16_d16_hi v74, v41 offset:9600 + ds_write_b16_d16_hi v74, v42 offset:10240 + ds_write_b16_d16_hi v74, v43 offset:10368 + ds_write_b16_d16_hi v74, v75 offset:10496 + ds_write_b16_d16_hi v74, v76 offset:10624 + ds_write_b16_d16_hi v74, v77 offset:11264 + ds_write_b16_d16_hi v74, v78 offset:11392 + ds_write_b16_d16_hi v74, v79 offset:11520 + ds_write_b16_d16_hi v74, v80 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v76, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v18, 1, v1 + v_and_b32_e32 v75, 60, v18 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s18, v18 + v_or_b32_e32 v38, s19, v76 + v_mad_u64_u32 v[40:41], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[42:43], v[40:41], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off + v_lshlrev_b32_e32 v18, 7, v18 + v_lshl_or_b32 v18, v76, 1, v18 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB9_143 +.LBB9_142: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_159 +.LBB9_143: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.144: ; in Loop: Header=BB9_143 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.145: ; %Flow992 + ; in Loop: Header=BB9_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.146: ; in Loop: Header=BB9_143 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.147: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.148: ; in Loop: Header=BB9_143 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.149: ; %Flow991 + ; in Loop: Header=BB9_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.150: ; in Loop: Header=BB9_143 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.151: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.152: ; in Loop: Header=BB9_143 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.153: ; %Flow990 + ; in Loop: Header=BB9_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.154: ; in Loop: Header=BB9_143 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.155: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.156: ; in Loop: Header=BB9_143 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.157: ; %Flow989 + ; in Loop: Header=BB9_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_142 +; %bb.158: ; in Loop: Header=BB9_143 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB9_142 +.LBB9_159: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB9_161 +.LBB9_160: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v41, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_177 +.LBB9_161: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.162: ; in Loop: Header=BB9_161 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.163: ; %Flow988 + ; in Loop: Header=BB9_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.164: ; in Loop: Header=BB9_161 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.165: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.166: ; in Loop: Header=BB9_161 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s9 + ; implicit-def: $vgpr33 +; %bb.167: ; %Flow987 + ; in Loop: Header=BB9_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.168: ; in Loop: Header=BB9_161 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.169: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.170: ; in Loop: Header=BB9_161 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.171: ; %Flow986 + ; in Loop: Header=BB9_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.172: ; in Loop: Header=BB9_161 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.173: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.174: ; in Loop: Header=BB9_161 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.175: ; %Flow985 + ; in Loop: Header=BB9_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_160 +; %bb.176: ; in Loop: Header=BB9_161 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB9_160 +.LBB9_177: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_di + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v40 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB9_179 +.LBB9_178: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s10 + v_perm_b32 v30, v41, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_195 +.LBB9_179: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.180: ; in Loop: Header=BB9_179 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.181: ; %Flow984 + ; in Loop: Header=BB9_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.182: ; in Loop: Header=BB9_179 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.183: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.184: ; in Loop: Header=BB9_179 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s9 + ; implicit-def: $vgpr31 +; %bb.185: ; %Flow983 + ; in Loop: Header=BB9_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.186: ; in Loop: Header=BB9_179 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.187: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.188: ; in Loop: Header=BB9_179 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s9 + ; implicit-def: $vgpr42 +; %bb.189: ; %Flow982 + ; in Loop: Header=BB9_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.190: ; in Loop: Header=BB9_179 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.191: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.192: ; in Loop: Header=BB9_179 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s9 + ; implicit-def: $vgpr42 +; %bb.193: ; %Flow981 + ; in Loop: Header=BB9_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_178 +; %bb.194: ; in Loop: Header=BB9_179 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB9_178 +.LBB9_195: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_197 +.LBB9_196: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s10 + v_perm_b32 v28, v39, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_213 +.LBB9_197: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.198: ; in Loop: Header=BB9_197 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.199: ; %Flow980 + ; in Loop: Header=BB9_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.200: ; in Loop: Header=BB9_197 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.201: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.202: ; in Loop: Header=BB9_197 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s9 + ; implicit-def: $vgpr29 +; %bb.203: ; %Flow979 + ; in Loop: Header=BB9_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.204: ; in Loop: Header=BB9_197 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.205: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.206: ; in Loop: Header=BB9_197 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s9 + ; implicit-def: $vgpr40 +; %bb.207: ; %Flow978 + ; in Loop: Header=BB9_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.208: ; in Loop: Header=BB9_197 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.209: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.210: ; in Loop: Header=BB9_197 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s9 + ; implicit-def: $vgpr40 +; %bb.211: ; %Flow977 + ; in Loop: Header=BB9_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_196 +; %bb.212: ; in Loop: Header=BB9_197 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB9_196 +.LBB9_213: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_65 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_215 +.LBB9_214: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_231 +.LBB9_215: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.216: ; in Loop: Header=BB9_215 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.217: ; %Flow976 + ; in Loop: Header=BB9_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.218: ; in Loop: Header=BB9_215 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.219: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.220: ; in Loop: Header=BB9_215 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.221: ; %Flow975 + ; in Loop: Header=BB9_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.222: ; in Loop: Header=BB9_215 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.223: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.224: ; in Loop: Header=BB9_215 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.225: ; %Flow974 + ; in Loop: Header=BB9_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.226: ; in Loop: Header=BB9_215 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.227: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.228: ; in Loop: Header=BB9_215 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s9 + ; implicit-def: $vgpr37 +; %bb.229: ; %Flow973 + ; in Loop: Header=BB9_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_214 +; %bb.230: ; in Loop: Header=BB9_215 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB9_214 +.LBB9_231: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_233 +.LBB9_232: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_249 +.LBB9_233: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.234: ; in Loop: Header=BB9_233 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.235: ; %Flow972 + ; in Loop: Header=BB9_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.236: ; in Loop: Header=BB9_233 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.237: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.238: ; in Loop: Header=BB9_233 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.239: ; %Flow971 + ; in Loop: Header=BB9_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.240: ; in Loop: Header=BB9_233 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.241: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.242: ; in Loop: Header=BB9_233 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.243: ; %Flow970 + ; in Loop: Header=BB9_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.244: ; in Loop: Header=BB9_233 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.245: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.246: ; in Loop: Header=BB9_233 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.247: ; %Flow969 + ; in Loop: Header=BB9_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_232 +; %bb.248: ; in Loop: Header=BB9_233 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_232 +.LBB9_249: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile130 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_251 +.LBB9_250: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_267 +.LBB9_251: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.252: ; in Loop: Header=BB9_251 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.253: ; %Flow968 + ; in Loop: Header=BB9_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.254: ; in Loop: Header=BB9_251 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.255: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.256: ; in Loop: Header=BB9_251 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.257: ; %Flow967 + ; in Loop: Header=BB9_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.258: ; in Loop: Header=BB9_251 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.259: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.260: ; in Loop: Header=BB9_251 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.261: ; %Flow966 + ; in Loop: Header=BB9_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.262: ; in Loop: Header=BB9_251 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.263: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.264: ; in Loop: Header=BB9_251 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.265: ; %Flow965 + ; in Loop: Header=BB9_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_250 +; %bb.266: ; in Loop: Header=BB9_251 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_250 +.LBB9_267: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_269 +.LBB9_268: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_285 +.LBB9_269: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.270: ; in Loop: Header=BB9_269 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.271: ; %Flow964 + ; in Loop: Header=BB9_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.272: ; in Loop: Header=BB9_269 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.273: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.274: ; in Loop: Header=BB9_269 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.275: ; %Flow963 + ; in Loop: Header=BB9_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.276: ; in Loop: Header=BB9_269 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.277: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.278: ; in Loop: Header=BB9_269 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.279: ; %Flow962 + ; in Loop: Header=BB9_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.280: ; in Loop: Header=BB9_269 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.281: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB9_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.282: ; in Loop: Header=BB9_269 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.283: ; %Flow961 + ; in Loop: Header=BB9_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_268 +; %bb.284: ; in Loop: Header=BB9_269 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_268 +.LBB9_285: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.286: + v_bfe_u32 v18, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v252, v18, s6 +; %bb.287: ; %Flow960 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.288: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v252, vcc +; %bb.289: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i437.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.290: + v_bfe_u32 v19, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v251, v19, s6 +; %bb.291: ; %Flow959 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.292: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v251, vcc +; %bb.293: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i440.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.294: + v_bfe_u32 v20, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v250, v20, s6 +; %bb.295: ; %Flow958 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.296: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v250, vcc +; %bb.297: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i443.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.298: + v_bfe_u32 v21, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v249, v21, s6 +; %bb.299: ; %Flow957 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.300: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v249, vcc +; %bb.301: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i446.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.302: + v_bfe_u32 v22, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v248, v22, s6 +; %bb.303: ; %Flow956 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.304: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v248, vcc +; %bb.305: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i449.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.306: + v_bfe_u32 v23, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v247, v23, s6 +; %bb.307: ; %Flow955 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.308: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v247, vcc +; %bb.309: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i452.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.310: + v_bfe_u32 v24, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v246, v24, s6 +; %bb.311: ; %Flow954 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.312: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v246, vcc +; %bb.313: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i455.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.314: + v_bfe_u32 v25, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v245, v25, s6 +; %bb.315: ; %Flow953 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.316: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v245, vcc +; %bb.317: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i458.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.318: + v_bfe_u32 v26, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v244, v26, s6 +; %bb.319: ; %Flow952 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.320: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v244, vcc +; %bb.321: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i461.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.322: + v_bfe_u32 v27, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v243, v27, s6 +; %bb.323: ; %Flow951 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.324: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v243, vcc +; %bb.325: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i464.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.326: + v_bfe_u32 v28, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v242, v28, s6 +; %bb.327: ; %Flow950 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.328: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v242, vcc +; %bb.329: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i467.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.330: + v_bfe_u32 v29, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v241, v29, s6 +; %bb.331: ; %Flow949 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.332: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v241, vcc +; %bb.333: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i470.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.334: + v_bfe_u32 v30, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v240, v30, s6 +; %bb.335: ; %Flow948 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.336: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v240, vcc +; %bb.337: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i473.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.338: + v_bfe_u32 v31, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v239, v31, s6 +; %bb.339: ; %Flow947 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.340: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v239, vcc +; %bb.341: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i476.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.342: + v_bfe_u32 v32, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v238, v32, s6 +; %bb.343: ; %Flow946 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.344: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v238, vcc +; %bb.345: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i479.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.346: + v_bfe_u32 v33, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v236, v33, s6 +; %bb.347: ; %Flow945 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.348: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v236, vcc +; %bb.349: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i482.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.350: + v_bfe_u32 v34, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v237, v34, s6 +; %bb.351: ; %Flow944 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.352: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v237, vcc +; %bb.353: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i485.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.354: + v_bfe_u32 v35, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v235, v35, s6 +; %bb.355: ; %Flow943 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.356: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v235, vcc +; %bb.357: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i488.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.358: + v_bfe_u32 v36, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v234, v36, s6 +; %bb.359: ; %Flow942 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.360: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v234, vcc +; %bb.361: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i491.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.362: + v_bfe_u32 v37, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v233, v37, s6 +; %bb.363: ; %Flow941 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.364: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v39, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v233, vcc +; %bb.365: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i494.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.366: + v_bfe_u32 v39, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v232, v39, s6 +; %bb.367: ; %Flow940 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.368: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v232, vcc +; %bb.369: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i497.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.370: + v_bfe_u32 v40, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v231, v40, s6 +; %bb.371: ; %Flow939 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.372: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v231, vcc +; %bb.373: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i500.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.374: + v_bfe_u32 v41, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v230, v41, s6 +; %bb.375: ; %Flow938 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.376: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v230, vcc +; %bb.377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i503.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.378: + v_bfe_u32 v42, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v229, v42, s6 +; %bb.379: ; %Flow937 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.380: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v229, vcc +; %bb.381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i506.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.382: + v_bfe_u32 v43, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v228, v43, s6 +; %bb.383: ; %Flow936 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.384: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v228, vcc +; %bb.385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i509.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.386: + v_bfe_u32 v77, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v227, v77, s6 +; %bb.387: ; %Flow935 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.388: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v227, vcc +; %bb.389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i512.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.390: + v_bfe_u32 v78, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v226, v78, s6 +; %bb.391: ; %Flow934 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.392: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v226, vcc +; %bb.393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i515.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.394: + v_bfe_u32 v79, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v225, v79, s6 +; %bb.395: ; %Flow933 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.396: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v225, vcc +; %bb.397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i518.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.398: + v_bfe_u32 v80, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v224, v80, s6 +; %bb.399: ; %Flow932 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.400: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v224, vcc +; %bb.401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i521.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.402: + v_bfe_u32 v81, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v223, v81, s6 +; %bb.403: ; %Flow931 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.404: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v223, vcc +; %bb.405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i524.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.406: + v_bfe_u32 v82, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v222, v82, s6 +; %bb.407: ; %Flow930 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.408: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v222, vcc +; %bb.409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i527.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.410: + v_bfe_u32 v83, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v221, v83, s6 +; %bb.411: ; %Flow929 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.412: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v221, vcc +; %bb.413: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL159 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshlrev_b32_e32 v76, 1, v76 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB9_415 +.LBB9_414: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i222.i.i.i.i.i + ; in Loop: Header=BB9_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_431 +.LBB9_415: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.416: ; in Loop: Header=BB9_415 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.417: ; %Flow928 + ; in Loop: Header=BB9_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.418: ; in Loop: Header=BB9_415 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.419: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i213.i.i.i.i.i + ; in Loop: Header=BB9_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.420: ; in Loop: Header=BB9_415 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.421: ; %Flow927 + ; in Loop: Header=BB9_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.422: ; in Loop: Header=BB9_415 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.423: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i216.i.i.i.i.i + ; in Loop: Header=BB9_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.424: ; in Loop: Header=BB9_415 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.425: ; %Flow926 + ; in Loop: Header=BB9_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.426: ; in Loop: Header=BB9_415 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.427: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i219.i.i.i.i.i + ; in Loop: Header=BB9_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.428: ; in Loop: Header=BB9_415 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.429: ; %Flow925 + ; in Loop: Header=BB9_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_414 +; %bb.430: ; in Loop: Header=BB9_415 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB9_414 +.LBB9_431: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i225.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_433 +.LBB9_432: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i238.i.i.i.i.i + ; in Loop: Header=BB9_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_449 +.LBB9_433: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.434: ; in Loop: Header=BB9_433 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.435: ; %Flow924 + ; in Loop: Header=BB9_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.436: ; in Loop: Header=BB9_433 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.437: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i229.i.i.i.i.i + ; in Loop: Header=BB9_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.438: ; in Loop: Header=BB9_433 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.439: ; %Flow923 + ; in Loop: Header=BB9_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.440: ; in Loop: Header=BB9_433 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.441: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i232.i.i.i.i.i + ; in Loop: Header=BB9_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.442: ; in Loop: Header=BB9_433 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.443: ; %Flow922 + ; in Loop: Header=BB9_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.444: ; in Loop: Header=BB9_433 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.445: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i235.i.i.i.i.i + ; in Loop: Header=BB9_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.446: ; in Loop: Header=BB9_433 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.447: ; %Flow921 + ; in Loop: Header=BB9_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_432 +; %bb.448: ; in Loop: Header=BB9_433 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB9_432 +.LBB9_449: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile242 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 64, v38 + v_accvgpr_write_b32 a16, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_451 +.LBB9_450: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i255.i.i.i.i.i + ; in Loop: Header=BB9_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_467 +.LBB9_451: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.452: ; in Loop: Header=BB9_451 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.453: ; %Flow920 + ; in Loop: Header=BB9_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.454: ; in Loop: Header=BB9_451 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.455: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i246.i.i.i.i.i + ; in Loop: Header=BB9_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.456: ; in Loop: Header=BB9_451 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.457: ; %Flow919 + ; in Loop: Header=BB9_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.458: ; in Loop: Header=BB9_451 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.459: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i249.i.i.i.i.i + ; in Loop: Header=BB9_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.460: ; in Loop: Header=BB9_451 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.461: ; %Flow918 + ; in Loop: Header=BB9_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.462: ; in Loop: Header=BB9_451 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.463: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i252.i.i.i.i.i + ; in Loop: Header=BB9_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.464: ; in Loop: Header=BB9_451 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.465: ; %Flow917 + ; in Loop: Header=BB9_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_450 +; %bb.466: ; in Loop: Header=BB9_451 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB9_450 +.LBB9_467: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i258.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_469 +.LBB9_468: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i271.i.i.i.i.i + ; in Loop: Header=BB9_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_485 +.LBB9_469: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.470: ; in Loop: Header=BB9_469 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.471: ; %Flow916 + ; in Loop: Header=BB9_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.472: ; in Loop: Header=BB9_469 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.473: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i262.i.i.i.i.i + ; in Loop: Header=BB9_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.474: ; in Loop: Header=BB9_469 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.475: ; %Flow915 + ; in Loop: Header=BB9_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.476: ; in Loop: Header=BB9_469 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.477: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i265.i.i.i.i.i + ; in Loop: Header=BB9_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.478: ; in Loop: Header=BB9_469 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.479: ; %Flow914 + ; in Loop: Header=BB9_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.480: ; in Loop: Header=BB9_469 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.481: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i268.i.i.i.i.i + ; in Loop: Header=BB9_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.482: ; in Loop: Header=BB9_469 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.483: ; %Flow913 + ; in Loop: Header=BB9_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_468 +; %bb.484: ; in Loop: Header=BB9_469 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_468 +.LBB9_485: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile275 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_487 +.LBB9_486: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i288.i.i.i.i.i + ; in Loop: Header=BB9_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_503 +.LBB9_487: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.488: ; in Loop: Header=BB9_487 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.489: ; %Flow912 + ; in Loop: Header=BB9_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.490: ; in Loop: Header=BB9_487 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.491: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i279.i.i.i.i.i + ; in Loop: Header=BB9_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.492: ; in Loop: Header=BB9_487 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.493: ; %Flow911 + ; in Loop: Header=BB9_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.494: ; in Loop: Header=BB9_487 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.495: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i282.i.i.i.i.i + ; in Loop: Header=BB9_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.496: ; in Loop: Header=BB9_487 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.497: ; %Flow910 + ; in Loop: Header=BB9_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.498: ; in Loop: Header=BB9_487 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.499: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i285.i.i.i.i.i + ; in Loop: Header=BB9_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.500: ; in Loop: Header=BB9_487 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.501: ; %Flow909 + ; in Loop: Header=BB9_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_486 +; %bb.502: ; in Loop: Header=BB9_487 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB9_486 +.LBB9_503: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i291.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_505 +.LBB9_504: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i304.i.i.i.i.i + ; in Loop: Header=BB9_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_521 +.LBB9_505: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.506: ; in Loop: Header=BB9_505 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.507: ; %Flow908 + ; in Loop: Header=BB9_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.508: ; in Loop: Header=BB9_505 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.509: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i295.i.i.i.i.i + ; in Loop: Header=BB9_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.510: ; in Loop: Header=BB9_505 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.511: ; %Flow907 + ; in Loop: Header=BB9_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.512: ; in Loop: Header=BB9_505 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.513: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i298.i.i.i.i.i + ; in Loop: Header=BB9_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.514: ; in Loop: Header=BB9_505 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.515: ; %Flow906 + ; in Loop: Header=BB9_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.516: ; in Loop: Header=BB9_505 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.517: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i301.i.i.i.i.i + ; in Loop: Header=BB9_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.518: ; in Loop: Header=BB9_505 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.519: ; %Flow905 + ; in Loop: Header=BB9_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_504 +; %bb.520: ; in Loop: Header=BB9_505 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_504 +.LBB9_521: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile308 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_523 +.LBB9_522: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i321.i.i.i.i.i + ; in Loop: Header=BB9_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_539 +.LBB9_523: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.524: ; in Loop: Header=BB9_523 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.525: ; %Flow904 + ; in Loop: Header=BB9_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.526: ; in Loop: Header=BB9_523 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.527: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i312.i.i.i.i.i + ; in Loop: Header=BB9_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.528: ; in Loop: Header=BB9_523 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.529: ; %Flow903 + ; in Loop: Header=BB9_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.530: ; in Loop: Header=BB9_523 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.531: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i315.i.i.i.i.i + ; in Loop: Header=BB9_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.532: ; in Loop: Header=BB9_523 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.533: ; %Flow902 + ; in Loop: Header=BB9_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.534: ; in Loop: Header=BB9_523 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.535: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i318.i.i.i.i.i + ; in Loop: Header=BB9_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.536: ; in Loop: Header=BB9_523 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.537: ; %Flow901 + ; in Loop: Header=BB9_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_522 +; %bb.538: ; in Loop: Header=BB9_523 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_522 +.LBB9_539: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i324.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_541 +.LBB9_540: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i337.i.i.i.i.i + ; in Loop: Header=BB9_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_557 +.LBB9_541: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.542: ; in Loop: Header=BB9_541 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.543: ; %Flow900 + ; in Loop: Header=BB9_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.544: ; in Loop: Header=BB9_541 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.545: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i328.i.i.i.i.i + ; in Loop: Header=BB9_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.546: ; in Loop: Header=BB9_541 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.547: ; %Flow899 + ; in Loop: Header=BB9_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.548: ; in Loop: Header=BB9_541 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.549: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i331.i.i.i.i.i + ; in Loop: Header=BB9_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.550: ; in Loop: Header=BB9_541 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.551: ; %Flow898 + ; in Loop: Header=BB9_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.552: ; in Loop: Header=BB9_541 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.553: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i334.i.i.i.i.i + ; in Loop: Header=BB9_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.554: ; in Loop: Header=BB9_541 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.555: ; %Flow897 + ; in Loop: Header=BB9_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_540 +; %bb.556: ; in Loop: Header=BB9_541 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_540 +.LBB9_557: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_469 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.558: + v_bfe_u32 v18, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v220, v18, s6 +; %bb.559: ; %Flow896 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.560: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v220, vcc +; %bb.561: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i534.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.562: + v_bfe_u32 v19, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v219, v19, s6 +; %bb.563: ; %Flow895 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.564: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v219, vcc +; %bb.565: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i537.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.566: + v_bfe_u32 v20, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v218, v20, s6 +; %bb.567: ; %Flow894 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.568: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v218, vcc +; %bb.569: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i540.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.570: + v_bfe_u32 v21, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v217, v21, s6 +; %bb.571: ; %Flow893 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.572: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v217, vcc +; %bb.573: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i543.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.574: + v_bfe_u32 v22, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v216, v22, s6 +; %bb.575: ; %Flow892 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.576: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v216, vcc +; %bb.577: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i546.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.578: + v_bfe_u32 v23, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v215, v23, s6 +; %bb.579: ; %Flow891 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.580: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v215, vcc +; %bb.581: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i549.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.582: + v_bfe_u32 v24, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v214, v24, s6 +; %bb.583: ; %Flow890 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.584: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v214, vcc +; %bb.585: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i552.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.586: + v_bfe_u32 v25, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v213, v25, s6 +; %bb.587: ; %Flow889 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.588: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v213, vcc +; %bb.589: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i555.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.590: + v_bfe_u32 v26, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v212, v26, s6 +; %bb.591: ; %Flow888 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.592: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v212, vcc +; %bb.593: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i558.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.594: + v_bfe_u32 v27, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v211, v27, s6 +; %bb.595: ; %Flow887 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.596: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v211, vcc +; %bb.597: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i561.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.598: + v_bfe_u32 v28, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v210, v28, s6 +; %bb.599: ; %Flow886 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.600: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v210, vcc +; %bb.601: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i564.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.602: + v_bfe_u32 v29, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v209, v29, s6 +; %bb.603: ; %Flow885 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.604: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v209, vcc +; %bb.605: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i567.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.606: + v_bfe_u32 v30, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v208, v30, s6 +; %bb.607: ; %Flow884 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.608: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v208, vcc +; %bb.609: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.610: + v_bfe_u32 v31, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v207, v31, s6 +; %bb.611: ; %Flow883 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.612: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v207, vcc +; %bb.613: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i573.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.614: + v_bfe_u32 v32, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v206, v32, s6 +; %bb.615: ; %Flow882 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.616: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v206, vcc +; %bb.617: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i576.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.618: + v_bfe_u32 v33, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v204, v33, s6 +; %bb.619: ; %Flow881 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.620: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v204, vcc +; %bb.621: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i579.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.622: + v_bfe_u32 v34, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v205, v34, s6 +; %bb.623: ; %Flow880 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.624: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v205, vcc +; %bb.625: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i582.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.626: + v_bfe_u32 v35, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v203, v35, s6 +; %bb.627: ; %Flow879 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.628: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v203, vcc +; %bb.629: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i585.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.630: + v_bfe_u32 v36, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v202, v36, s6 +; %bb.631: ; %Flow878 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.632: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v202, vcc +; %bb.633: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i588.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.634: + v_bfe_u32 v37, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v201, v37, s6 +; %bb.635: ; %Flow877 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.636: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v201, vcc +; %bb.637: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i591.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.638: + v_bfe_u32 v40, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v200, v40, s6 +; %bb.639: ; %Flow876 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.640: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v200, vcc +; %bb.641: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i594.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.642: + v_bfe_u32 v41, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v199, v41, s6 +; %bb.643: ; %Flow875 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.644: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v199, vcc +; %bb.645: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i597.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.646: + v_bfe_u32 v42, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v198, v42, s6 +; %bb.647: ; %Flow874 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.648: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v198, vcc +; %bb.649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i600.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.650: + v_bfe_u32 v43, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v197, v43, s6 +; %bb.651: ; %Flow873 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.652: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v197, vcc +; %bb.653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.654: + v_bfe_u32 v77, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v196, v77, s6 +; %bb.655: ; %Flow872 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.656: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v196, vcc +; %bb.657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i606.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.658: + v_bfe_u32 v78, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v195, v78, s6 +; %bb.659: ; %Flow871 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.660: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v195, vcc +; %bb.661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i609.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.662: + v_bfe_u32 v79, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v194, v79, s6 +; %bb.663: ; %Flow870 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.664: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v194, vcc +; %bb.665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i612.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.666: + v_bfe_u32 v80, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v193, v80, s6 +; %bb.667: ; %Flow869 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.668: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v193, vcc +; %bb.669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i615.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.670: + v_bfe_u32 v81, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v192, v81, s6 +; %bb.671: ; %Flow868 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.672: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v192, vcc +; %bb.673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i618.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.674: + v_bfe_u32 v82, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v191, v82, s6 +; %bb.675: ; %Flow867 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.676: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v191, vcc +; %bb.677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i621.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.678: + v_bfe_u32 v83, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v190, v83, s6 +; %bb.679: ; %Flow866 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.680: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v190, vcc +; %bb.681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i624.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.682: + v_bfe_u32 v84, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v189, v84, s6 +; %bb.683: ; %Flow865 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.684: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v189, vcc +; %bb.685: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL628 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB9_687 +.LBB9_686: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i691.i.i.i.i.i + ; in Loop: Header=BB9_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_703 +.LBB9_687: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.688: ; in Loop: Header=BB9_687 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.689: ; %Flow864 + ; in Loop: Header=BB9_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.690: ; in Loop: Header=BB9_687 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.691: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i682.i.i.i.i.i + ; in Loop: Header=BB9_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.692: ; in Loop: Header=BB9_687 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.693: ; %Flow863 + ; in Loop: Header=BB9_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.694: ; in Loop: Header=BB9_687 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.695: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i685.i.i.i.i.i + ; in Loop: Header=BB9_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.696: ; in Loop: Header=BB9_687 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.697: ; %Flow862 + ; in Loop: Header=BB9_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.698: ; in Loop: Header=BB9_687 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.699: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i688.i.i.i.i.i + ; in Loop: Header=BB9_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.700: ; in Loop: Header=BB9_687 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.701: ; %Flow861 + ; in Loop: Header=BB9_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_686 +; %bb.702: ; in Loop: Header=BB9_687 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB9_686 +.LBB9_703: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i694.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_705 +.LBB9_704: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i707.i.i.i.i.i + ; in Loop: Header=BB9_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_721 +.LBB9_705: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.706: ; in Loop: Header=BB9_705 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.707: ; %Flow860 + ; in Loop: Header=BB9_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.708: ; in Loop: Header=BB9_705 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.709: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i698.i.i.i.i.i + ; in Loop: Header=BB9_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.710: ; in Loop: Header=BB9_705 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.711: ; %Flow859 + ; in Loop: Header=BB9_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.712: ; in Loop: Header=BB9_705 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.713: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i701.i.i.i.i.i + ; in Loop: Header=BB9_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.714: ; in Loop: Header=BB9_705 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.715: ; %Flow858 + ; in Loop: Header=BB9_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.716: ; in Loop: Header=BB9_705 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.717: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i704.i.i.i.i.i + ; in Loop: Header=BB9_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.718: ; in Loop: Header=BB9_705 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.719: ; %Flow857 + ; in Loop: Header=BB9_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_704 +; %bb.720: ; in Loop: Header=BB9_705 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB9_704 +.LBB9_721: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile711 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 0x80, v38 + v_accvgpr_write_b32 a17, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_723 +.LBB9_722: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i724.i.i.i.i.i + ; in Loop: Header=BB9_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_739 +.LBB9_723: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.724: ; in Loop: Header=BB9_723 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.725: ; %Flow856 + ; in Loop: Header=BB9_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.726: ; in Loop: Header=BB9_723 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.727: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i715.i.i.i.i.i + ; in Loop: Header=BB9_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.728: ; in Loop: Header=BB9_723 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.729: ; %Flow855 + ; in Loop: Header=BB9_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.730: ; in Loop: Header=BB9_723 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.731: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i718.i.i.i.i.i + ; in Loop: Header=BB9_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.732: ; in Loop: Header=BB9_723 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.733: ; %Flow854 + ; in Loop: Header=BB9_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.734: ; in Loop: Header=BB9_723 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.735: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i721.i.i.i.i.i + ; in Loop: Header=BB9_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.736: ; in Loop: Header=BB9_723 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.737: ; %Flow853 + ; in Loop: Header=BB9_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_722 +; %bb.738: ; in Loop: Header=BB9_723 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB9_722 +.LBB9_739: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i727.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_741 +.LBB9_740: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i740.i.i.i.i.i + ; in Loop: Header=BB9_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_757 +.LBB9_741: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.742: ; in Loop: Header=BB9_741 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.743: ; %Flow852 + ; in Loop: Header=BB9_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.744: ; in Loop: Header=BB9_741 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.745: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i731.i.i.i.i.i + ; in Loop: Header=BB9_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.746: ; in Loop: Header=BB9_741 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.747: ; %Flow851 + ; in Loop: Header=BB9_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.748: ; in Loop: Header=BB9_741 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.749: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i734.i.i.i.i.i + ; in Loop: Header=BB9_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.750: ; in Loop: Header=BB9_741 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.751: ; %Flow850 + ; in Loop: Header=BB9_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.752: ; in Loop: Header=BB9_741 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.753: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i737.i.i.i.i.i + ; in Loop: Header=BB9_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.754: ; in Loop: Header=BB9_741 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.755: ; %Flow849 + ; in Loop: Header=BB9_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_740 +; %bb.756: ; in Loop: Header=BB9_741 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_740 +.LBB9_757: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile744 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_759 +.LBB9_758: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i757.i.i.i.i.i + ; in Loop: Header=BB9_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_775 +.LBB9_759: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.760: ; in Loop: Header=BB9_759 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.761: ; %Flow848 + ; in Loop: Header=BB9_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.762: ; in Loop: Header=BB9_759 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.763: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i748.i.i.i.i.i + ; in Loop: Header=BB9_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.764: ; in Loop: Header=BB9_759 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.765: ; %Flow847 + ; in Loop: Header=BB9_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.766: ; in Loop: Header=BB9_759 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.767: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i751.i.i.i.i.i + ; in Loop: Header=BB9_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.768: ; in Loop: Header=BB9_759 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.769: ; %Flow846 + ; in Loop: Header=BB9_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.770: ; in Loop: Header=BB9_759 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.771: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i754.i.i.i.i.i + ; in Loop: Header=BB9_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.772: ; in Loop: Header=BB9_759 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.773: ; %Flow845 + ; in Loop: Header=BB9_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_758 +; %bb.774: ; in Loop: Header=BB9_759 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB9_758 +.LBB9_775: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i760.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_777 +.LBB9_776: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i773.i.i.i.i.i + ; in Loop: Header=BB9_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_793 +.LBB9_777: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.778: ; in Loop: Header=BB9_777 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.779: ; %Flow844 + ; in Loop: Header=BB9_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.780: ; in Loop: Header=BB9_777 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.781: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i764.i.i.i.i.i + ; in Loop: Header=BB9_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.782: ; in Loop: Header=BB9_777 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.783: ; %Flow843 + ; in Loop: Header=BB9_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.784: ; in Loop: Header=BB9_777 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.785: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i767.i.i.i.i.i + ; in Loop: Header=BB9_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.786: ; in Loop: Header=BB9_777 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.787: ; %Flow842 + ; in Loop: Header=BB9_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.788: ; in Loop: Header=BB9_777 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.789: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i770.i.i.i.i.i + ; in Loop: Header=BB9_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.790: ; in Loop: Header=BB9_777 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.791: ; %Flow841 + ; in Loop: Header=BB9_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_776 +; %bb.792: ; in Loop: Header=BB9_777 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_776 +.LBB9_793: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile777 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_795 +.LBB9_794: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i790.i.i.i.i.i + ; in Loop: Header=BB9_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_811 +.LBB9_795: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.796: ; in Loop: Header=BB9_795 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.797: ; %Flow840 + ; in Loop: Header=BB9_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.798: ; in Loop: Header=BB9_795 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.799: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i781.i.i.i.i.i + ; in Loop: Header=BB9_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.800: ; in Loop: Header=BB9_795 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.801: ; %Flow839 + ; in Loop: Header=BB9_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.802: ; in Loop: Header=BB9_795 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.803: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i784.i.i.i.i.i + ; in Loop: Header=BB9_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.804: ; in Loop: Header=BB9_795 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.805: ; %Flow838 + ; in Loop: Header=BB9_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.806: ; in Loop: Header=BB9_795 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.807: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i787.i.i.i.i.i + ; in Loop: Header=BB9_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.808: ; in Loop: Header=BB9_795 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.809: ; %Flow837 + ; in Loop: Header=BB9_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_794 +; %bb.810: ; in Loop: Header=BB9_795 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_794 +.LBB9_811: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i793.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_813 +.LBB9_812: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i806.i.i.i.i.i + ; in Loop: Header=BB9_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_829 +.LBB9_813: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.814: ; in Loop: Header=BB9_813 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.815: ; %Flow836 + ; in Loop: Header=BB9_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.816: ; in Loop: Header=BB9_813 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.817: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i797.i.i.i.i.i + ; in Loop: Header=BB9_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.818: ; in Loop: Header=BB9_813 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.819: ; %Flow835 + ; in Loop: Header=BB9_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.820: ; in Loop: Header=BB9_813 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.821: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i800.i.i.i.i.i + ; in Loop: Header=BB9_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.822: ; in Loop: Header=BB9_813 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.823: ; %Flow834 + ; in Loop: Header=BB9_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.824: ; in Loop: Header=BB9_813 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.825: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i803.i.i.i.i.i + ; in Loop: Header=BB9_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.826: ; in Loop: Header=BB9_813 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.827: ; %Flow833 + ; in Loop: Header=BB9_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_812 +; %bb.828: ; in Loop: Header=BB9_813 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_812 +.LBB9_829: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_938 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.830: + v_bfe_u32 v18, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v188, v18, s6 +; %bb.831: ; %Flow832 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.832: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v188, vcc +; %bb.833: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1003.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.834: + v_bfe_u32 v19, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v187, v19, s6 +; %bb.835: ; %Flow831 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.836: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v187, vcc +; %bb.837: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1006.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.838: + v_bfe_u32 v20, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v186, v20, s6 +; %bb.839: ; %Flow830 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.840: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v186, vcc +; %bb.841: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1009.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.842: + v_bfe_u32 v21, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v185, v21, s6 +; %bb.843: ; %Flow829 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.844: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v185, vcc +; %bb.845: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1012.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.846: + v_bfe_u32 v22, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v184, v22, s6 +; %bb.847: ; %Flow828 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.848: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v184, vcc +; %bb.849: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1015.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.850: + v_bfe_u32 v23, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v183, v23, s6 +; %bb.851: ; %Flow827 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.852: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v183, vcc +; %bb.853: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1018.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.854: + v_bfe_u32 v24, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v182, v24, s6 +; %bb.855: ; %Flow826 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.856: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v182, vcc +; %bb.857: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1021.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.858: + v_bfe_u32 v25, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v181, v25, s6 +; %bb.859: ; %Flow825 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.860: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v181, vcc +; %bb.861: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1024.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.862: + v_bfe_u32 v26, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v180, v26, s6 +; %bb.863: ; %Flow824 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.864: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v180, vcc +; %bb.865: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1027.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.866: + v_bfe_u32 v27, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v179, v27, s6 +; %bb.867: ; %Flow823 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.868: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v179, vcc +; %bb.869: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1030.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.870: + v_bfe_u32 v28, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v178, v28, s6 +; %bb.871: ; %Flow822 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.872: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v178, vcc +; %bb.873: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1033.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.874: + v_bfe_u32 v29, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v177, v29, s6 +; %bb.875: ; %Flow821 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.876: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v177, vcc +; %bb.877: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1036.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.878: + v_bfe_u32 v30, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v176, v30, s6 +; %bb.879: ; %Flow820 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.880: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v176, vcc +; %bb.881: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.882: + v_bfe_u32 v31, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v175, v31, s6 +; %bb.883: ; %Flow819 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.884: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v175, vcc +; %bb.885: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1042.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.886: + v_bfe_u32 v32, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v174, v32, s6 +; %bb.887: ; %Flow818 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.888: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v174, vcc +; %bb.889: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1045.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.890: + v_bfe_u32 v33, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v172, v33, s6 +; %bb.891: ; %Flow817 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.892: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v172, vcc +; %bb.893: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1048.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.894: + v_bfe_u32 v34, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v173, v34, s6 +; %bb.895: ; %Flow816 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.896: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v173, vcc +; %bb.897: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1051.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.898: + v_bfe_u32 v35, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v171, v35, s6 +; %bb.899: ; %Flow815 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.900: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v171, vcc +; %bb.901: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1054.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.902: + v_bfe_u32 v36, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v170, v36, s6 +; %bb.903: ; %Flow814 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.904: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v170, vcc +; %bb.905: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1057.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.906: + v_bfe_u32 v37, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v169, v37, s6 +; %bb.907: ; %Flow813 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.908: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v169, vcc +; %bb.909: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1060.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.910: + v_bfe_u32 v40, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v168, v40, s6 +; %bb.911: ; %Flow812 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.912: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v168, vcc +; %bb.913: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1063.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.914: + v_bfe_u32 v41, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v167, v41, s6 +; %bb.915: ; %Flow811 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.916: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v167, vcc +; %bb.917: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1066.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.918: + v_bfe_u32 v42, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v166, v42, s6 +; %bb.919: ; %Flow810 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.920: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v166, vcc +; %bb.921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1069.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.922: + v_bfe_u32 v43, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v165, v43, s6 +; %bb.923: ; %Flow809 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.924: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v165, vcc +; %bb.925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.926: + v_bfe_u32 v77, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v164, v77, s6 +; %bb.927: ; %Flow808 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.928: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v164, vcc +; %bb.929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1075.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.930: + v_bfe_u32 v78, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v163, v78, s6 +; %bb.931: ; %Flow807 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.932: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v163, vcc +; %bb.933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1078.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.934: + v_bfe_u32 v79, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v162, v79, s6 +; %bb.935: ; %Flow806 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.936: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v162, vcc +; %bb.937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1081.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.938: + v_bfe_u32 v80, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v161, v80, s6 +; %bb.939: ; %Flow805 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.940: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v161, vcc +; %bb.941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1084.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.942: + v_bfe_u32 v81, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v160, v81, s6 +; %bb.943: ; %Flow804 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.944: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v160, vcc +; %bb.945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1087.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.946: + v_bfe_u32 v82, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v159, v82, s6 +; %bb.947: ; %Flow803 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.948: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v159, vcc +; %bb.949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1090.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.950: + v_bfe_u32 v83, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v158, v83, s6 +; %bb.951: ; %Flow802 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.952: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v158, vcc +; %bb.953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1093.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.954: + v_bfe_u32 v84, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v157, v84, s6 +; %bb.955: ; %Flow801 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.956: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v157, vcc +; %bb.957: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1097 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB9_959 +.LBB9_958: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1160.i.i.i.i.i + ; in Loop: Header=BB9_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_975 +.LBB9_959: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.960: ; in Loop: Header=BB9_959 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.961: ; %Flow800 + ; in Loop: Header=BB9_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.962: ; in Loop: Header=BB9_959 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.963: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1151.i.i.i.i.i + ; in Loop: Header=BB9_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.964: ; in Loop: Header=BB9_959 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.965: ; %Flow799 + ; in Loop: Header=BB9_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.966: ; in Loop: Header=BB9_959 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.967: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1154.i.i.i.i.i + ; in Loop: Header=BB9_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.968: ; in Loop: Header=BB9_959 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.969: ; %Flow798 + ; in Loop: Header=BB9_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.970: ; in Loop: Header=BB9_959 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.971: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1157.i.i.i.i.i + ; in Loop: Header=BB9_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.972: ; in Loop: Header=BB9_959 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.973: ; %Flow797 + ; in Loop: Header=BB9_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_958 +; %bb.974: ; in Loop: Header=BB9_959 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB9_958 +.LBB9_975: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1163.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_977 +.LBB9_976: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1176.i.i.i.i.i + ; in Loop: Header=BB9_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_993 +.LBB9_977: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.978: ; in Loop: Header=BB9_977 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.979: ; %Flow796 + ; in Loop: Header=BB9_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.980: ; in Loop: Header=BB9_977 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.981: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1167.i.i.i.i.i + ; in Loop: Header=BB9_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.982: ; in Loop: Header=BB9_977 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.983: ; %Flow795 + ; in Loop: Header=BB9_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.984: ; in Loop: Header=BB9_977 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.985: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1170.i.i.i.i.i + ; in Loop: Header=BB9_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.986: ; in Loop: Header=BB9_977 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.987: ; %Flow794 + ; in Loop: Header=BB9_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.988: ; in Loop: Header=BB9_977 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.989: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1173.i.i.i.i.i + ; in Loop: Header=BB9_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.990: ; in Loop: Header=BB9_977 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.991: ; %Flow793 + ; in Loop: Header=BB9_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_976 +; %bb.992: ; in Loop: Header=BB9_977 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB9_976 +.LBB9_993: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1180 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v77, 0xc0, v38 + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_995 +.LBB9_994: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1193.i.i.i.i.i + ; in Loop: Header=BB9_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v78, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1011 +.LBB9_995: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.996: ; in Loop: Header=BB9_995 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.997: ; %Flow792 + ; in Loop: Header=BB9_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.998: ; in Loop: Header=BB9_995 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.999: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1184.i.i.i.i.i + ; in Loop: Header=BB9_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1000: ; in Loop: Header=BB9_995 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.1001: ; %Flow791 + ; in Loop: Header=BB9_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1002: ; in Loop: Header=BB9_995 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1003: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1187.i.i.i.i.i + ; in Loop: Header=BB9_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1004: ; in Loop: Header=BB9_995 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.1005: ; %Flow790 + ; in Loop: Header=BB9_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1006: ; in Loop: Header=BB9_995 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1007: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1190.i.i.i.i.i + ; in Loop: Header=BB9_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v78, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1008: ; in Loop: Header=BB9_995 Depth=1 + v_bfe_u32 v78, v43, 16, 1 + v_add3_u32 v78, v43, v78, s9 + ; implicit-def: $vgpr43 +; %bb.1009: ; %Flow789 + ; in Loop: Header=BB9_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_994 +; %bb.1010: ; in Loop: Header=BB9_995 Depth=1 + v_or_b32_e32 v78, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v43, vcc + s_branch .LBB9_994 +.LBB9_1011: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1196.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1013 +.LBB9_1012: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1209.i.i.i.i.i + ; in Loop: Header=BB9_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1029 +.LBB9_1013: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1014: ; in Loop: Header=BB9_1013 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.1015: ; %Flow788 + ; in Loop: Header=BB9_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1016: ; in Loop: Header=BB9_1013 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1017: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1200.i.i.i.i.i + ; in Loop: Header=BB9_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1018: ; in Loop: Header=BB9_1013 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.1019: ; %Flow787 + ; in Loop: Header=BB9_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1020: ; in Loop: Header=BB9_1013 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1021: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1203.i.i.i.i.i + ; in Loop: Header=BB9_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1022: ; in Loop: Header=BB9_1013 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.1023: ; %Flow786 + ; in Loop: Header=BB9_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1024: ; in Loop: Header=BB9_1013 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1025: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1206.i.i.i.i.i + ; in Loop: Header=BB9_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1026: ; in Loop: Header=BB9_1013 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.1027: ; %Flow785 + ; in Loop: Header=BB9_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1012 +; %bb.1028: ; in Loop: Header=BB9_1013 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_1012 +.LBB9_1029: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1213 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1031 +.LBB9_1030: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1226.i.i.i.i.i + ; in Loop: Header=BB9_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1047 +.LBB9_1031: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1032: ; in Loop: Header=BB9_1031 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.1033: ; %Flow784 + ; in Loop: Header=BB9_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1034: ; in Loop: Header=BB9_1031 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1035: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1217.i.i.i.i.i + ; in Loop: Header=BB9_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1036: ; in Loop: Header=BB9_1031 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.1037: ; %Flow783 + ; in Loop: Header=BB9_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1038: ; in Loop: Header=BB9_1031 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1039: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1220.i.i.i.i.i + ; in Loop: Header=BB9_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1040: ; in Loop: Header=BB9_1031 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.1041: ; %Flow782 + ; in Loop: Header=BB9_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1042: ; in Loop: Header=BB9_1031 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1043: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1223.i.i.i.i.i + ; in Loop: Header=BB9_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1044: ; in Loop: Header=BB9_1031 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.1045: ; %Flow781 + ; in Loop: Header=BB9_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1030 +; %bb.1046: ; in Loop: Header=BB9_1031 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB9_1030 +.LBB9_1047: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1229.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_1049 +.LBB9_1048: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1242.i.i.i.i.i + ; in Loop: Header=BB9_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1065 +.LBB9_1049: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1050: ; in Loop: Header=BB9_1049 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.1051: ; %Flow780 + ; in Loop: Header=BB9_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1052: ; in Loop: Header=BB9_1049 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1053: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1233.i.i.i.i.i + ; in Loop: Header=BB9_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1054: ; in Loop: Header=BB9_1049 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.1055: ; %Flow779 + ; in Loop: Header=BB9_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1056: ; in Loop: Header=BB9_1049 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1057: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1236.i.i.i.i.i + ; in Loop: Header=BB9_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1058: ; in Loop: Header=BB9_1049 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.1059: ; %Flow778 + ; in Loop: Header=BB9_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1060: ; in Loop: Header=BB9_1049 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1061: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1239.i.i.i.i.i + ; in Loop: Header=BB9_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1062: ; in Loop: Header=BB9_1049 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.1063: ; %Flow777 + ; in Loop: Header=BB9_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1048 +; %bb.1064: ; in Loop: Header=BB9_1049 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_1048 +.LBB9_1065: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1246 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_1067 +.LBB9_1066: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1259.i.i.i.i.i + ; in Loop: Header=BB9_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1083 +.LBB9_1067: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1068: ; in Loop: Header=BB9_1067 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.1069: ; %Flow776 + ; in Loop: Header=BB9_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1070: ; in Loop: Header=BB9_1067 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1071: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1250.i.i.i.i.i + ; in Loop: Header=BB9_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1072: ; in Loop: Header=BB9_1067 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.1073: ; %Flow775 + ; in Loop: Header=BB9_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1074: ; in Loop: Header=BB9_1067 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1075: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1253.i.i.i.i.i + ; in Loop: Header=BB9_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1076: ; in Loop: Header=BB9_1067 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.1077: ; %Flow774 + ; in Loop: Header=BB9_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1078: ; in Loop: Header=BB9_1067 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1079: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1256.i.i.i.i.i + ; in Loop: Header=BB9_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1080: ; in Loop: Header=BB9_1067 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.1081: ; %Flow773 + ; in Loop: Header=BB9_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1066 +; %bb.1082: ; in Loop: Header=BB9_1067 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_1066 +.LBB9_1083: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1262.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_1085 +.LBB9_1084: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1275.i.i.i.i.i + ; in Loop: Header=BB9_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1101 +.LBB9_1085: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1086: ; in Loop: Header=BB9_1085 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.1087: ; %Flow772 + ; in Loop: Header=BB9_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1088: ; in Loop: Header=BB9_1085 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1089: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1266.i.i.i.i.i + ; in Loop: Header=BB9_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1090: ; in Loop: Header=BB9_1085 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.1091: ; %Flow771 + ; in Loop: Header=BB9_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1092: ; in Loop: Header=BB9_1085 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1093: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1269.i.i.i.i.i + ; in Loop: Header=BB9_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1094: ; in Loop: Header=BB9_1085 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.1095: ; %Flow770 + ; in Loop: Header=BB9_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1096: ; in Loop: Header=BB9_1085 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1097: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1272.i.i.i.i.i + ; in Loop: Header=BB9_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1098: ; in Loop: Header=BB9_1085 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.1099: ; %Flow769 + ; in Loop: Header=BB9_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1084 +; %bb.1100: ; in Loop: Header=BB9_1085 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_1084 +.LBB9_1101: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1407 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1102: + v_bfe_u32 v18, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v156, v18, s6 +; %bb.1103: ; %Flow768 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1104: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v156, vcc +; %bb.1105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1472.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1106: + v_bfe_u32 v19, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v155, v19, s6 +; %bb.1107: ; %Flow767 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1108: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v155, vcc +; %bb.1109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1475.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1110: + v_bfe_u32 v20, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v154, v20, s6 +; %bb.1111: ; %Flow766 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1112: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v154, vcc +; %bb.1113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1478.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1114: + v_bfe_u32 v21, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v153, v21, s6 +; %bb.1115: ; %Flow765 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1116: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v153, vcc +; %bb.1117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1481.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1118: + v_bfe_u32 v22, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v152, v22, s6 +; %bb.1119: ; %Flow764 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1120: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v152, vcc +; %bb.1121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1484.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1122: + v_bfe_u32 v23, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v151, v23, s6 +; %bb.1123: ; %Flow763 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1124: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v151, vcc +; %bb.1125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1487.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1126: + v_bfe_u32 v24, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v150, v24, s6 +; %bb.1127: ; %Flow762 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1128: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v150, vcc +; %bb.1129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1490.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1130: + v_bfe_u32 v25, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v149, v25, s6 +; %bb.1131: ; %Flow761 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1132: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v149, vcc +; %bb.1133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1493.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1134: + v_bfe_u32 v26, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v148, v26, s6 +; %bb.1135: ; %Flow760 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1136: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v148, vcc +; %bb.1137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1496.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1138: + v_bfe_u32 v27, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v147, v27, s6 +; %bb.1139: ; %Flow759 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1140: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v147, vcc +; %bb.1141: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1499.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1142: + v_bfe_u32 v28, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v146, v28, s6 +; %bb.1143: ; %Flow758 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1144: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v146, vcc +; %bb.1145: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1502.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1146: + v_bfe_u32 v29, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v145, v29, s6 +; %bb.1147: ; %Flow757 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1148: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v145, vcc +; %bb.1149: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1505.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1150: + v_bfe_u32 v30, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v144, v30, s6 +; %bb.1151: ; %Flow756 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1152: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v144, vcc +; %bb.1153: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1508.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1154: + v_bfe_u32 v31, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v143, v31, s6 +; %bb.1155: ; %Flow755 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1156: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v143, vcc +; %bb.1157: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1511.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1158: + v_bfe_u32 v32, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v142, v32, s6 +; %bb.1159: ; %Flow754 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1160: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v142, vcc +; %bb.1161: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1514.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1162: + v_bfe_u32 v33, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v141, v33, s6 +; %bb.1163: ; %Flow753 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1164: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v141, vcc +; %bb.1165: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1517.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1166: + v_bfe_u32 v34, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v2, v34, s6 +; %bb.1167: ; %Flow752 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1168: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v2, vcc +; %bb.1169: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1520.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1170: + v_bfe_u32 v35, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v3, v35, s6 +; %bb.1171: ; %Flow751 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1172: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v3, vcc +; %bb.1173: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1523.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1174: + v_bfe_u32 v36, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v4, v36, s6 +; %bb.1175: ; %Flow750 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1176: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v4, vcc +; %bb.1177: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1526.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1178: + v_bfe_u32 v37, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v5, v37, s6 +; %bb.1179: ; %Flow749 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1180: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v5, vcc +; %bb.1181: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1529.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1182: + v_bfe_u32 v40, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v6, v40, s6 +; %bb.1183: ; %Flow748 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1184: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v6, vcc +; %bb.1185: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1532.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1186: + v_bfe_u32 v41, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v7, v41, s6 +; %bb.1187: ; %Flow747 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1188: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v7, vcc +; %bb.1189: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1535.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1190: + v_bfe_u32 v42, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v8, v42, s6 +; %bb.1191: ; %Flow746 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1192: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v8, vcc +; %bb.1193: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1538.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1194: + v_bfe_u32 v43, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v9, v43, s6 +; %bb.1195: ; %Flow745 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1196: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v78, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v78, v9, vcc +; %bb.1197: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1541.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1198: + v_bfe_u32 v78, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v10, v78, s6 +; %bb.1199: ; %Flow744 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1200: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v10, vcc +; %bb.1201: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1544.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1202: + v_bfe_u32 v79, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v11, v79, s6 +; %bb.1203: ; %Flow743 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1204: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v11, vcc +; %bb.1205: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1547.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1206: + v_bfe_u32 v80, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v12, v80, s6 +; %bb.1207: ; %Flow742 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1208: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v12, vcc +; %bb.1209: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1550.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1210: + v_bfe_u32 v81, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v13, v81, s6 +; %bb.1211: ; %Flow741 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1212: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v13, vcc +; %bb.1213: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1553.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1214: + v_bfe_u32 v82, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v14, v82, s6 +; %bb.1215: ; %Flow740 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1216: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v14, vcc +; %bb.1217: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1556.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1218: + v_bfe_u32 v83, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v15, v83, s6 +; %bb.1219: ; %Flow739 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1220: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v15, vcc +; %bb.1221: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1559.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1222: + v_bfe_u32 v84, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v16, v84, s6 +; %bb.1223: ; %Flow738 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1224: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v16, vcc +; %bb.1225: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1562.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v85, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s2, v85 + ; implicit-def: $vgpr85 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1226: + v_bfe_u32 v85, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v85, v17, v85, s6 +; %bb.1227: ; %Flow737 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1228: + v_mov_b32_e32 v85, 0 + v_accvgpr_write_b32 a0, v86 + v_or_b32_e32 v86, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v85 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v85, v86, v17, vcc + v_accvgpr_read_b32 v86, a0 +; %bb.1229: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1566 + s_or_b64 exec, exec, s[2:3] + s_or_b32 s8, s18, 0x80 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v78 offset:10240 + ds_write_b16_d16_hi v74, v79 offset:10368 + ds_write_b16_d16_hi v74, v80 offset:10496 + ds_write_b16_d16_hi v74, v81 offset:10624 + ds_write_b16_d16_hi v74, v82 offset:11264 + ds_write_b16_d16_hi v74, v83 offset:11392 + ds_write_b16_d16_hi v74, v84 offset:11520 + ds_write_b16_d16_hi v74, v85 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v78, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v79, 0 + s_branch .LBB9_1231 +.LBB9_1230: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1629.i.i.i.i.i + ; in Loop: Header=BB9_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v82, v35, s11 + v_perm_b32 v34, v80, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1247 +.LBB9_1231: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1232: ; in Loop: Header=BB9_1231 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1233: ; %Flow736 + ; in Loop: Header=BB9_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1234: ; in Loop: Header=BB9_1231 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1235: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1620.i.i.i.i.i + ; in Loop: Header=BB9_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v80, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1236: ; in Loop: Header=BB9_1231 Depth=1 + v_bfe_u32 v80, v35, 16, 1 + v_add3_u32 v80, v35, v80, s10 + ; implicit-def: $vgpr35 +; %bb.1237: ; %Flow735 + ; in Loop: Header=BB9_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1238: ; in Loop: Header=BB9_1231 Depth=1 + v_or_b32_e32 v80, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v35, vcc +; %bb.1239: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1623.i.i.i.i.i + ; in Loop: Header=BB9_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v81, v78, v35 + v_and_b32_e32 v35, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1240: ; in Loop: Header=BB9_1231 Depth=1 + v_bfe_u32 v35, v81, 16, 1 + v_add3_u32 v35, v81, v35, s10 + ; implicit-def: $vgpr81 +; %bb.1241: ; %Flow734 + ; in Loop: Header=BB9_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1242: ; in Loop: Header=BB9_1231 Depth=1 + v_or_b32_e32 v35, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v81, vcc +; %bb.1243: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1626.i.i.i.i.i + ; in Loop: Header=BB9_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v81, 0xffff0000, v37 + v_add_f32_e32 v81, v31, v81 + v_and_b32_e32 v82, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1244: ; in Loop: Header=BB9_1231 Depth=1 + v_bfe_u32 v82, v81, 16, 1 + v_add3_u32 v82, v81, v82, s10 + ; implicit-def: $vgpr81 +; %bb.1245: ; %Flow733 + ; in Loop: Header=BB9_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1230 +; %bb.1246: ; in Loop: Header=BB9_1231 Depth=1 + v_or_b32_e32 v82, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v82, v81, vcc + s_branch .LBB9_1230 +.LBB9_1247: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1632.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_1249 +.LBB9_1248: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1645.i.i.i.i.i + ; in Loop: Header=BB9_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v80, v33, s11 + v_perm_b32 v32, v78, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1265 +.LBB9_1249: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1250: ; in Loop: Header=BB9_1249 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1251: ; %Flow732 + ; in Loop: Header=BB9_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1252: ; in Loop: Header=BB9_1249 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1253: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1636.i.i.i.i.i + ; in Loop: Header=BB9_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v78, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1254: ; in Loop: Header=BB9_1249 Depth=1 + v_bfe_u32 v78, v33, 16, 1 + v_add3_u32 v78, v33, v78, s10 + ; implicit-def: $vgpr33 +; %bb.1255: ; %Flow731 + ; in Loop: Header=BB9_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1256: ; in Loop: Header=BB9_1249 Depth=1 + v_or_b32_e32 v78, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v33, vcc +; %bb.1257: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1639.i.i.i.i.i + ; in Loop: Header=BB9_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v79, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1258: ; in Loop: Header=BB9_1249 Depth=1 + v_bfe_u32 v33, v79, 16, 1 + v_add3_u32 v33, v79, v33, s10 + ; implicit-def: $vgpr79 +; %bb.1259: ; %Flow730 + ; in Loop: Header=BB9_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1260: ; in Loop: Header=BB9_1249 Depth=1 + v_or_b32_e32 v33, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v79, vcc +; %bb.1261: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1642.i.i.i.i.i + ; in Loop: Header=BB9_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v35 + v_add_f32_e32 v79, v37, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1262: ; in Loop: Header=BB9_1249 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1263: ; %Flow729 + ; in Loop: Header=BB9_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1248 +; %bb.1264: ; in Loop: Header=BB9_1249 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB9_1248 +.LBB9_1265: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1649 + s_or_b64 exec, exec, s[2:3] + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_1267 +.LBB9_1266: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1662.i.i.i.i.i + ; in Loop: Header=BB9_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1283 +.LBB9_1267: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1268: ; in Loop: Header=BB9_1267 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1269: ; %Flow728 + ; in Loop: Header=BB9_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1270: ; in Loop: Header=BB9_1267 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1271: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1653.i.i.i.i.i + ; in Loop: Header=BB9_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1272: ; in Loop: Header=BB9_1267 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1273: ; %Flow727 + ; in Loop: Header=BB9_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1274: ; in Loop: Header=BB9_1267 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1275: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1656.i.i.i.i.i + ; in Loop: Header=BB9_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1276: ; in Loop: Header=BB9_1267 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1277: ; %Flow726 + ; in Loop: Header=BB9_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1278: ; in Loop: Header=BB9_1267 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1279: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1659.i.i.i.i.i + ; in Loop: Header=BB9_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1280: ; in Loop: Header=BB9_1267 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1281: ; %Flow725 + ; in Loop: Header=BB9_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1266 +; %bb.1282: ; in Loop: Header=BB9_1267 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB9_1266 +.LBB9_1283: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1665.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1285 +.LBB9_1284: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1678.i.i.i.i.i + ; in Loop: Header=BB9_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1301 +.LBB9_1285: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1286: ; in Loop: Header=BB9_1285 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1287: ; %Flow724 + ; in Loop: Header=BB9_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1288: ; in Loop: Header=BB9_1285 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1289: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1669.i.i.i.i.i + ; in Loop: Header=BB9_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1290: ; in Loop: Header=BB9_1285 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1291: ; %Flow723 + ; in Loop: Header=BB9_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1292: ; in Loop: Header=BB9_1285 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1293: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1672.i.i.i.i.i + ; in Loop: Header=BB9_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1294: ; in Loop: Header=BB9_1285 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1295: ; %Flow722 + ; in Loop: Header=BB9_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1296: ; in Loop: Header=BB9_1285 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1297: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1675.i.i.i.i.i + ; in Loop: Header=BB9_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1298: ; in Loop: Header=BB9_1285 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1299: ; %Flow721 + ; in Loop: Header=BB9_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1284 +; %bb.1300: ; in Loop: Header=BB9_1285 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_1284 +.LBB9_1301: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1682 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1303 +.LBB9_1302: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1695.i.i.i.i.i + ; in Loop: Header=BB9_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1319 +.LBB9_1303: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1304: ; in Loop: Header=BB9_1303 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1305: ; %Flow720 + ; in Loop: Header=BB9_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1306: ; in Loop: Header=BB9_1303 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1307: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1686.i.i.i.i.i + ; in Loop: Header=BB9_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1308: ; in Loop: Header=BB9_1303 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1309: ; %Flow719 + ; in Loop: Header=BB9_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1310: ; in Loop: Header=BB9_1303 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1311: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1689.i.i.i.i.i + ; in Loop: Header=BB9_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1312: ; in Loop: Header=BB9_1303 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1313: ; %Flow718 + ; in Loop: Header=BB9_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1314: ; in Loop: Header=BB9_1303 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1315: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1692.i.i.i.i.i + ; in Loop: Header=BB9_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1316: ; in Loop: Header=BB9_1303 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1317: ; %Flow717 + ; in Loop: Header=BB9_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1302 +; %bb.1318: ; in Loop: Header=BB9_1303 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB9_1302 +.LBB9_1319: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1698.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_1321 +.LBB9_1320: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1711.i.i.i.i.i + ; in Loop: Header=BB9_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1337 +.LBB9_1321: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1322: ; in Loop: Header=BB9_1321 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1323: ; %Flow716 + ; in Loop: Header=BB9_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1324: ; in Loop: Header=BB9_1321 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1325: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1702.i.i.i.i.i + ; in Loop: Header=BB9_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1326: ; in Loop: Header=BB9_1321 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1327: ; %Flow715 + ; in Loop: Header=BB9_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1328: ; in Loop: Header=BB9_1321 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1329: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1705.i.i.i.i.i + ; in Loop: Header=BB9_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1330: ; in Loop: Header=BB9_1321 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1331: ; %Flow714 + ; in Loop: Header=BB9_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1332: ; in Loop: Header=BB9_1321 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1333: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1708.i.i.i.i.i + ; in Loop: Header=BB9_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1334: ; in Loop: Header=BB9_1321 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1335: ; %Flow713 + ; in Loop: Header=BB9_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1320 +; %bb.1336: ; in Loop: Header=BB9_1321 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_1320 +.LBB9_1337: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1715 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_1339 +.LBB9_1338: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1728.i.i.i.i.i + ; in Loop: Header=BB9_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1355 +.LBB9_1339: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1340: ; in Loop: Header=BB9_1339 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1341: ; %Flow712 + ; in Loop: Header=BB9_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1342: ; in Loop: Header=BB9_1339 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1343: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1719.i.i.i.i.i + ; in Loop: Header=BB9_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1344: ; in Loop: Header=BB9_1339 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1345: ; %Flow711 + ; in Loop: Header=BB9_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1346: ; in Loop: Header=BB9_1339 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1347: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1722.i.i.i.i.i + ; in Loop: Header=BB9_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1348: ; in Loop: Header=BB9_1339 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1349: ; %Flow710 + ; in Loop: Header=BB9_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1350: ; in Loop: Header=BB9_1339 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1351: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1725.i.i.i.i.i + ; in Loop: Header=BB9_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1352: ; in Loop: Header=BB9_1339 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1353: ; %Flow709 + ; in Loop: Header=BB9_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1338 +; %bb.1354: ; in Loop: Header=BB9_1339 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_1338 +.LBB9_1355: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1731.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_1357 +.LBB9_1356: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1744.i.i.i.i.i + ; in Loop: Header=BB9_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1373 +.LBB9_1357: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1358: ; in Loop: Header=BB9_1357 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1359: ; %Flow708 + ; in Loop: Header=BB9_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1360: ; in Loop: Header=BB9_1357 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1361: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1735.i.i.i.i.i + ; in Loop: Header=BB9_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1362: ; in Loop: Header=BB9_1357 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1363: ; %Flow707 + ; in Loop: Header=BB9_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1364: ; in Loop: Header=BB9_1357 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1365: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1738.i.i.i.i.i + ; in Loop: Header=BB9_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1366: ; in Loop: Header=BB9_1357 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1367: ; %Flow706 + ; in Loop: Header=BB9_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1368: ; in Loop: Header=BB9_1357 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1369: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1741.i.i.i.i.i + ; in Loop: Header=BB9_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1370: ; in Loop: Header=BB9_1357 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1371: ; %Flow705 + ; in Loop: Header=BB9_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1356 +; %bb.1372: ; in Loop: Header=BB9_1357 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_1356 +.LBB9_1373: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1876 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1374: + v_bfe_u32 v18, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v140, v18, s6 +; %bb.1375: ; %Flow704 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1376: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v140, vcc +; %bb.1377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1941.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1378: + v_bfe_u32 v19, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v139, v19, s6 +; %bb.1379: ; %Flow703 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1380: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v139, vcc +; %bb.1381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1944.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1382: + v_bfe_u32 v20, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v138, v20, s6 +; %bb.1383: ; %Flow702 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1384: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v138, vcc +; %bb.1385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1947.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1386: + v_bfe_u32 v21, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v137, v21, s6 +; %bb.1387: ; %Flow701 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1388: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v137, vcc +; %bb.1389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1950.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1390: + v_bfe_u32 v22, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v136, v22, s6 +; %bb.1391: ; %Flow700 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1392: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v136, vcc +; %bb.1393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1953.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1394: + v_bfe_u32 v23, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v135, v23, s6 +; %bb.1395: ; %Flow699 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1396: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v135, vcc +; %bb.1397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1956.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1398: + v_bfe_u32 v24, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v134, v24, s6 +; %bb.1399: ; %Flow698 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1400: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v134, vcc +; %bb.1401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1959.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1402: + v_bfe_u32 v25, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v133, v25, s6 +; %bb.1403: ; %Flow697 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1404: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v133, vcc +; %bb.1405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1962.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1406: + v_bfe_u32 v26, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v132, v26, s6 +; %bb.1407: ; %Flow696 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1408: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v132, vcc +; %bb.1409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1965.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1410: + v_bfe_u32 v27, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v131, v27, s6 +; %bb.1411: ; %Flow695 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1412: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v131, vcc +; %bb.1413: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1968.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1414: + v_bfe_u32 v28, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v130, v28, s6 +; %bb.1415: ; %Flow694 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1416: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v130, vcc +; %bb.1417: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1971.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1418: + v_bfe_u32 v29, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v129, v29, s6 +; %bb.1419: ; %Flow693 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1420: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v129, vcc +; %bb.1421: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1974.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1422: + v_bfe_u32 v30, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v128, v30, s6 +; %bb.1423: ; %Flow692 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1424: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v128, vcc +; %bb.1425: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1977.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1426: + v_bfe_u32 v31, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v127, v31, s6 +; %bb.1427: ; %Flow691 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1428: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v127, vcc +; %bb.1429: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1980.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1430: + v_bfe_u32 v32, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v126, v32, s6 +; %bb.1431: ; %Flow690 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1432: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v126, vcc +; %bb.1433: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1983.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1434: + v_bfe_u32 v33, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v124, v33, s6 +; %bb.1435: ; %Flow689 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1436: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v124, vcc +; %bb.1437: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1986.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1438: + v_bfe_u32 v34, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v125, v34, s6 +; %bb.1439: ; %Flow688 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1440: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v125, vcc +; %bb.1441: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1989.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1442: + v_bfe_u32 v35, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v123, v35, s6 +; %bb.1443: ; %Flow687 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1444: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v123, vcc +; %bb.1445: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1992.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1446: + v_bfe_u32 v36, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v122, v36, s6 +; %bb.1447: ; %Flow686 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1448: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v122, vcc +; %bb.1449: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1995.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1450: + v_bfe_u32 v37, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v121, v37, s6 +; %bb.1451: ; %Flow685 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1452: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v121, vcc +; %bb.1453: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1998.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1454: + v_bfe_u32 v40, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v120, v40, s6 +; %bb.1455: ; %Flow684 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1456: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v120, vcc +; %bb.1457: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2001.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1458: + v_bfe_u32 v41, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v119, v41, s6 +; %bb.1459: ; %Flow683 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1460: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v119, vcc +; %bb.1461: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2004.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1462: + v_bfe_u32 v42, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v118, v42, s6 +; %bb.1463: ; %Flow682 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1464: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v118, vcc +; %bb.1465: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2007.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1466: + v_bfe_u32 v43, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v117, v43, s6 +; %bb.1467: ; %Flow681 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1468: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v117, vcc +; %bb.1469: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2010.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1470: + v_bfe_u32 v77, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v116, v77, s6 +; %bb.1471: ; %Flow680 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1472: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v116, vcc +; %bb.1473: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2013.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1474: + v_bfe_u32 v78, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v115, v78, s6 +; %bb.1475: ; %Flow679 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1476: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v115, vcc +; %bb.1477: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2016.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1478: + v_bfe_u32 v79, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v114, v79, s6 +; %bb.1479: ; %Flow678 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1480: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v114, vcc +; %bb.1481: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2019.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1482: + v_bfe_u32 v80, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v113, v80, s6 +; %bb.1483: ; %Flow677 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1484: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v113, vcc +; %bb.1485: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2022.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1486: + v_bfe_u32 v81, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v112, v81, s6 +; %bb.1487: ; %Flow676 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1488: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v112, vcc +; %bb.1489: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2025.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1490: + v_bfe_u32 v82, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v111, v82, s6 +; %bb.1491: ; %Flow675 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1492: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v111, vcc +; %bb.1493: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2028.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1494: + v_bfe_u32 v83, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v110, v83, s6 +; %bb.1495: ; %Flow674 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1496: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v110, vcc +; %bb.1497: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2031.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1498: + v_bfe_u32 v84, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v109, v84, s6 +; %bb.1499: ; %Flow673 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1500: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v109, vcc +; %bb.1501: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2035 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB9_1503 +.LBB9_1502: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2098.i.i.i.i.i + ; in Loop: Header=BB9_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s11 + v_perm_b32 v34, v79, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1519 +.LBB9_1503: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1504: ; in Loop: Header=BB9_1503 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1505: ; %Flow672 + ; in Loop: Header=BB9_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1506: ; in Loop: Header=BB9_1503 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1507: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2089.i.i.i.i.i + ; in Loop: Header=BB9_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1508: ; in Loop: Header=BB9_1503 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s10 + ; implicit-def: $vgpr35 +; %bb.1509: ; %Flow671 + ; in Loop: Header=BB9_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1510: ; in Loop: Header=BB9_1503 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.1511: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2092.i.i.i.i.i + ; in Loop: Header=BB9_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1512: ; in Loop: Header=BB9_1503 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s10 + ; implicit-def: $vgpr80 +; %bb.1513: ; %Flow670 + ; in Loop: Header=BB9_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1514: ; in Loop: Header=BB9_1503 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.1515: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2095.i.i.i.i.i + ; in Loop: Header=BB9_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1516: ; in Loop: Header=BB9_1503 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s10 + ; implicit-def: $vgpr80 +; %bb.1517: ; %Flow669 + ; in Loop: Header=BB9_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1502 +; %bb.1518: ; in Loop: Header=BB9_1503 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB9_1502 +.LBB9_1519: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2101.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_1521 +.LBB9_1520: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2114.i.i.i.i.i + ; in Loop: Header=BB9_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s11 + v_perm_b32 v32, v77, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1537 +.LBB9_1521: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1522: ; in Loop: Header=BB9_1521 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1523: ; %Flow668 + ; in Loop: Header=BB9_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1524: ; in Loop: Header=BB9_1521 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1525: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2105.i.i.i.i.i + ; in Loop: Header=BB9_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1526: ; in Loop: Header=BB9_1521 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s10 + ; implicit-def: $vgpr33 +; %bb.1527: ; %Flow667 + ; in Loop: Header=BB9_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1528: ; in Loop: Header=BB9_1521 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.1529: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2108.i.i.i.i.i + ; in Loop: Header=BB9_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1530: ; in Loop: Header=BB9_1521 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s10 + ; implicit-def: $vgpr78 +; %bb.1531: ; %Flow666 + ; in Loop: Header=BB9_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1532: ; in Loop: Header=BB9_1521 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.1533: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2111.i.i.i.i.i + ; in Loop: Header=BB9_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1534: ; in Loop: Header=BB9_1521 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s10 + ; implicit-def: $vgpr78 +; %bb.1535: ; %Flow665 + ; in Loop: Header=BB9_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1520 +; %bb.1536: ; in Loop: Header=BB9_1521 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB9_1520 +.LBB9_1537: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2118 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a17 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB9_1539 +.LBB9_1538: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2131.i.i.i.i.i + ; in Loop: Header=BB9_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1555 +.LBB9_1539: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1540: ; in Loop: Header=BB9_1539 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1541: ; %Flow664 + ; in Loop: Header=BB9_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1542: ; in Loop: Header=BB9_1539 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1543: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2122.i.i.i.i.i + ; in Loop: Header=BB9_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1544: ; in Loop: Header=BB9_1539 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1545: ; %Flow663 + ; in Loop: Header=BB9_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1546: ; in Loop: Header=BB9_1539 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1547: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2125.i.i.i.i.i + ; in Loop: Header=BB9_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1548: ; in Loop: Header=BB9_1539 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1549: ; %Flow662 + ; in Loop: Header=BB9_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1550: ; in Loop: Header=BB9_1539 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1551: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2128.i.i.i.i.i + ; in Loop: Header=BB9_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1552: ; in Loop: Header=BB9_1539 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1553: ; %Flow661 + ; in Loop: Header=BB9_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1538 +; %bb.1554: ; in Loop: Header=BB9_1539 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB9_1538 +.LBB9_1555: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2134.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1557 +.LBB9_1556: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2147.i.i.i.i.i + ; in Loop: Header=BB9_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1573 +.LBB9_1557: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1558: ; in Loop: Header=BB9_1557 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1559: ; %Flow660 + ; in Loop: Header=BB9_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1560: ; in Loop: Header=BB9_1557 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1561: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2138.i.i.i.i.i + ; in Loop: Header=BB9_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1562: ; in Loop: Header=BB9_1557 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1563: ; %Flow659 + ; in Loop: Header=BB9_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1564: ; in Loop: Header=BB9_1557 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1565: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2141.i.i.i.i.i + ; in Loop: Header=BB9_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1566: ; in Loop: Header=BB9_1557 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1567: ; %Flow658 + ; in Loop: Header=BB9_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1568: ; in Loop: Header=BB9_1557 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1569: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2144.i.i.i.i.i + ; in Loop: Header=BB9_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1570: ; in Loop: Header=BB9_1557 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1571: ; %Flow657 + ; in Loop: Header=BB9_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1556 +; %bb.1572: ; in Loop: Header=BB9_1557 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_1556 +.LBB9_1573: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2151 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1575 +.LBB9_1574: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2164.i.i.i.i.i + ; in Loop: Header=BB9_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1591 +.LBB9_1575: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1576: ; in Loop: Header=BB9_1575 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1577: ; %Flow656 + ; in Loop: Header=BB9_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1578: ; in Loop: Header=BB9_1575 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1579: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2155.i.i.i.i.i + ; in Loop: Header=BB9_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1580: ; in Loop: Header=BB9_1575 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1581: ; %Flow655 + ; in Loop: Header=BB9_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1582: ; in Loop: Header=BB9_1575 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1583: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2158.i.i.i.i.i + ; in Loop: Header=BB9_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1584: ; in Loop: Header=BB9_1575 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1585: ; %Flow654 + ; in Loop: Header=BB9_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1586: ; in Loop: Header=BB9_1575 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1587: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2161.i.i.i.i.i + ; in Loop: Header=BB9_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1588: ; in Loop: Header=BB9_1575 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1589: ; %Flow653 + ; in Loop: Header=BB9_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1574 +; %bb.1590: ; in Loop: Header=BB9_1575 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB9_1574 +.LBB9_1591: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2167.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_1593 +.LBB9_1592: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2180.i.i.i.i.i + ; in Loop: Header=BB9_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1609 +.LBB9_1593: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1594: ; in Loop: Header=BB9_1593 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1595: ; %Flow652 + ; in Loop: Header=BB9_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1596: ; in Loop: Header=BB9_1593 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1597: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2171.i.i.i.i.i + ; in Loop: Header=BB9_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1598: ; in Loop: Header=BB9_1593 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1599: ; %Flow651 + ; in Loop: Header=BB9_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1600: ; in Loop: Header=BB9_1593 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1601: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2174.i.i.i.i.i + ; in Loop: Header=BB9_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1602: ; in Loop: Header=BB9_1593 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1603: ; %Flow650 + ; in Loop: Header=BB9_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1604: ; in Loop: Header=BB9_1593 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1605: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2177.i.i.i.i.i + ; in Loop: Header=BB9_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1606: ; in Loop: Header=BB9_1593 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1607: ; %Flow649 + ; in Loop: Header=BB9_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1592 +; %bb.1608: ; in Loop: Header=BB9_1593 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_1592 +.LBB9_1609: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2184 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_1611 +.LBB9_1610: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2197.i.i.i.i.i + ; in Loop: Header=BB9_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1627 +.LBB9_1611: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1612: ; in Loop: Header=BB9_1611 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1613: ; %Flow648 + ; in Loop: Header=BB9_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1614: ; in Loop: Header=BB9_1611 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1615: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2188.i.i.i.i.i + ; in Loop: Header=BB9_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1616: ; in Loop: Header=BB9_1611 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1617: ; %Flow647 + ; in Loop: Header=BB9_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1618: ; in Loop: Header=BB9_1611 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1619: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2191.i.i.i.i.i + ; in Loop: Header=BB9_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1620: ; in Loop: Header=BB9_1611 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1621: ; %Flow646 + ; in Loop: Header=BB9_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1622: ; in Loop: Header=BB9_1611 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1623: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2194.i.i.i.i.i + ; in Loop: Header=BB9_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1624: ; in Loop: Header=BB9_1611 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1625: ; %Flow645 + ; in Loop: Header=BB9_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1610 +; %bb.1626: ; in Loop: Header=BB9_1611 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_1610 +.LBB9_1627: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2200.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_1629 +.LBB9_1628: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2213.i.i.i.i.i + ; in Loop: Header=BB9_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1645 +.LBB9_1629: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1630: ; in Loop: Header=BB9_1629 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1631: ; %Flow644 + ; in Loop: Header=BB9_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1632: ; in Loop: Header=BB9_1629 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1633: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2204.i.i.i.i.i + ; in Loop: Header=BB9_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1634: ; in Loop: Header=BB9_1629 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1635: ; %Flow643 + ; in Loop: Header=BB9_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1636: ; in Loop: Header=BB9_1629 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1637: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2207.i.i.i.i.i + ; in Loop: Header=BB9_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1638: ; in Loop: Header=BB9_1629 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1639: ; %Flow642 + ; in Loop: Header=BB9_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1640: ; in Loop: Header=BB9_1629 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1641: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2210.i.i.i.i.i + ; in Loop: Header=BB9_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1642: ; in Loop: Header=BB9_1629 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1643: ; %Flow641 + ; in Loop: Header=BB9_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1628 +; %bb.1644: ; in Loop: Header=BB9_1629 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_1628 +.LBB9_1645: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2345 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1646: + v_bfe_u32 v18, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v108, v18, s6 +; %bb.1647: ; %Flow640 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1648: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v108, vcc +; %bb.1649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2410.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1650: + v_bfe_u32 v19, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v107, v19, s6 +; %bb.1651: ; %Flow639 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1652: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v107, vcc +; %bb.1653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2413.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1654: + v_bfe_u32 v20, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v106, v20, s6 +; %bb.1655: ; %Flow638 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1656: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v106, vcc +; %bb.1657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2416.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1658: + v_bfe_u32 v21, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v105, v21, s6 +; %bb.1659: ; %Flow637 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1660: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v105, vcc +; %bb.1661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2419.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1662: + v_bfe_u32 v22, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v104, v22, s6 +; %bb.1663: ; %Flow636 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1664: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v104, vcc +; %bb.1665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2422.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1666: + v_bfe_u32 v23, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v103, v23, s6 +; %bb.1667: ; %Flow635 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1668: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v103, vcc +; %bb.1669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2425.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1670: + v_bfe_u32 v24, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v102, v24, s6 +; %bb.1671: ; %Flow634 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1672: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v102, vcc +; %bb.1673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2428.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1674: + v_bfe_u32 v25, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v101, v25, s6 +; %bb.1675: ; %Flow633 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1676: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v101, vcc +; %bb.1677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2431.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1678: + v_bfe_u32 v26, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v100, v26, s6 +; %bb.1679: ; %Flow632 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1680: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v100, vcc +; %bb.1681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2434.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1682: + v_bfe_u32 v27, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v99, v27, s6 +; %bb.1683: ; %Flow631 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1684: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v99, vcc +; %bb.1685: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2437.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1686: + v_bfe_u32 v28, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v98, v28, s6 +; %bb.1687: ; %Flow630 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1688: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v98, vcc +; %bb.1689: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2440.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1690: + v_bfe_u32 v29, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v97, v29, s6 +; %bb.1691: ; %Flow629 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1692: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v97, vcc +; %bb.1693: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2443.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1694: + v_bfe_u32 v30, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v96, v30, s6 +; %bb.1695: ; %Flow628 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1696: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v96, vcc +; %bb.1697: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2446.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1698: + v_bfe_u32 v31, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v95, v31, s6 +; %bb.1699: ; %Flow627 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1700: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v95, vcc +; %bb.1701: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2449.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1702: + v_bfe_u32 v32, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v94, v32, s6 +; %bb.1703: ; %Flow626 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1704: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v94, vcc +; %bb.1705: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2452.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1706: + v_bfe_u32 v33, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v92, v33, s6 +; %bb.1707: ; %Flow625 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1708: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v92, vcc +; %bb.1709: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2455.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1710: + v_bfe_u32 v34, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v93, v34, s6 +; %bb.1711: ; %Flow624 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1712: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v93, vcc +; %bb.1713: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2458.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1714: + v_bfe_u32 v35, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v91, v35, s6 +; %bb.1715: ; %Flow623 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1716: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v91, vcc +; %bb.1717: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2461.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1718: + v_bfe_u32 v36, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v90, v36, s6 +; %bb.1719: ; %Flow622 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1720: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v90, vcc +; %bb.1721: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2464.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1722: + v_bfe_u32 v37, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v89, v37, s6 +; %bb.1723: ; %Flow621 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1724: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v89, vcc +; %bb.1725: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2467.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1726: + v_bfe_u32 v40, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v88, v40, s6 +; %bb.1727: ; %Flow620 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1728: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v88, vcc +; %bb.1729: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2470.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a65 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1730: + v_accvgpr_read_b32 v42, a65 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.1731: ; %Flow619 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1732: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a65 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.1733: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2473.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a64 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1734: + v_accvgpr_read_b32 v43, a64 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.1735: ; %Flow618 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1736: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a64 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.1737: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2476.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a55 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1738: + v_accvgpr_read_b32 v77, a55 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.1739: ; %Flow617 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1740: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a55 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.1741: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2479.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a54 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1742: + v_accvgpr_read_b32 v78, a54 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.1743: ; %Flow616 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1744: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a54 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.1745: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2482.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a53 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1746: + v_accvgpr_read_b32 v79, a53 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.1747: ; %Flow615 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1748: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a53 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.1749: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2485.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a52 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1750: + v_accvgpr_read_b32 v80, a52 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.1751: ; %Flow614 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1752: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a52 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.1753: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2488.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a51 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1754: + v_accvgpr_read_b32 v81, a51 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.1755: ; %Flow613 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1756: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a51 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.1757: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2491.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a50 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1758: + v_accvgpr_read_b32 v82, a50 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.1759: ; %Flow612 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1760: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a50 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.1761: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2494.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a49 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1762: + v_accvgpr_read_b32 v83, a49 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.1763: ; %Flow611 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1764: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a49 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.1765: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2497.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1766: + v_bfe_u32 v83, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v87, v83, s6 +; %bb.1767: ; %Flow610 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1768: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v87, vcc +; %bb.1769: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2500.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v84, a48 + v_and_b32_e32 v84, 0x7f800000, v84 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1770: + v_accvgpr_read_b32 v85, a48 + v_bfe_u32 v84, v85, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v85, v84, s6 +; %bb.1771: ; %Flow609 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1772: + v_mov_b32_e32 v84, 0 + v_accvgpr_write_b32 a0, v87 + v_accvgpr_read_b32 v87, a48 + v_or_b32_e32 v85, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v87, vcc + v_accvgpr_read_b32 v87, a0 +; %bb.1773: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2504 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB9_1775 +.LBB9_1774: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2567.i.i.i.i.i + ; in Loop: Header=BB9_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s11 + v_perm_b32 v34, v78, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1791 +.LBB9_1775: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1776: ; in Loop: Header=BB9_1775 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1777: ; %Flow608 + ; in Loop: Header=BB9_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1778: ; in Loop: Header=BB9_1775 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1779: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2558.i.i.i.i.i + ; in Loop: Header=BB9_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1780: ; in Loop: Header=BB9_1775 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s10 + ; implicit-def: $vgpr35 +; %bb.1781: ; %Flow607 + ; in Loop: Header=BB9_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1782: ; in Loop: Header=BB9_1775 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.1783: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2561.i.i.i.i.i + ; in Loop: Header=BB9_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1784: ; in Loop: Header=BB9_1775 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s10 + ; implicit-def: $vgpr79 +; %bb.1785: ; %Flow606 + ; in Loop: Header=BB9_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1786: ; in Loop: Header=BB9_1775 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.1787: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2564.i.i.i.i.i + ; in Loop: Header=BB9_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1788: ; in Loop: Header=BB9_1775 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1789: ; %Flow605 + ; in Loop: Header=BB9_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1774 +; %bb.1790: ; in Loop: Header=BB9_1775 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB9_1774 +.LBB9_1791: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB9_1793 +.LBB9_1792: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2583.i.i.i.i.i + ; in Loop: Header=BB9_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s11 + v_perm_b32 v32, v41, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1809 +.LBB9_1793: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1794: ; in Loop: Header=BB9_1793 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1795: ; %Flow604 + ; in Loop: Header=BB9_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1796: ; in Loop: Header=BB9_1793 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1797: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2574.i.i.i.i.i + ; in Loop: Header=BB9_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1798: ; in Loop: Header=BB9_1793 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s10 + ; implicit-def: $vgpr33 +; %bb.1799: ; %Flow603 + ; in Loop: Header=BB9_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1800: ; in Loop: Header=BB9_1793 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.1801: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2577.i.i.i.i.i + ; in Loop: Header=BB9_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1802: ; in Loop: Header=BB9_1793 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s10 + ; implicit-def: $vgpr77 +; %bb.1803: ; %Flow602 + ; in Loop: Header=BB9_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1804: ; in Loop: Header=BB9_1793 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.1805: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2580.i.i.i.i.i + ; in Loop: Header=BB9_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1806: ; in Loop: Header=BB9_1793 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s10 + ; implicit-def: $vgpr77 +; %bb.1807: ; %Flow601 + ; in Loop: Header=BB9_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1792 +; %bb.1808: ; in Loop: Header=BB9_1793 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB9_1792 +.LBB9_1809: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2587 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a16 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB9_1811 +.LBB9_1810: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2600.i.i.i.i.i + ; in Loop: Header=BB9_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s11 + v_perm_b32 v30, v41, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1827 +.LBB9_1811: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1812: ; in Loop: Header=BB9_1811 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1813: ; %Flow600 + ; in Loop: Header=BB9_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1814: ; in Loop: Header=BB9_1811 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1815: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2591.i.i.i.i.i + ; in Loop: Header=BB9_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1816: ; in Loop: Header=BB9_1811 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s10 + ; implicit-def: $vgpr31 +; %bb.1817: ; %Flow599 + ; in Loop: Header=BB9_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1818: ; in Loop: Header=BB9_1811 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.1819: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2594.i.i.i.i.i + ; in Loop: Header=BB9_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1820: ; in Loop: Header=BB9_1811 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s10 + ; implicit-def: $vgpr42 +; %bb.1821: ; %Flow598 + ; in Loop: Header=BB9_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1822: ; in Loop: Header=BB9_1811 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.1823: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2597.i.i.i.i.i + ; in Loop: Header=BB9_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1824: ; in Loop: Header=BB9_1811 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s10 + ; implicit-def: $vgpr42 +; %bb.1825: ; %Flow597 + ; in Loop: Header=BB9_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1810 +; %bb.1826: ; in Loop: Header=BB9_1811 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB9_1810 +.LBB9_1827: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1829 +.LBB9_1828: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2616.i.i.i.i.i + ; in Loop: Header=BB9_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s11 + v_perm_b32 v28, v39, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1845 +.LBB9_1829: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1830: ; in Loop: Header=BB9_1829 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1831: ; %Flow596 + ; in Loop: Header=BB9_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1832: ; in Loop: Header=BB9_1829 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1833: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2607.i.i.i.i.i + ; in Loop: Header=BB9_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1834: ; in Loop: Header=BB9_1829 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s10 + ; implicit-def: $vgpr29 +; %bb.1835: ; %Flow595 + ; in Loop: Header=BB9_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1836: ; in Loop: Header=BB9_1829 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.1837: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2610.i.i.i.i.i + ; in Loop: Header=BB9_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1838: ; in Loop: Header=BB9_1829 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s10 + ; implicit-def: $vgpr40 +; %bb.1839: ; %Flow594 + ; in Loop: Header=BB9_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1840: ; in Loop: Header=BB9_1829 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.1841: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2613.i.i.i.i.i + ; in Loop: Header=BB9_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1842: ; in Loop: Header=BB9_1829 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s10 + ; implicit-def: $vgpr40 +; %bb.1843: ; %Flow593 + ; in Loop: Header=BB9_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1828 +; %bb.1844: ; in Loop: Header=BB9_1829 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB9_1828 +.LBB9_1845: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2620 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_1847 +.LBB9_1846: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2633.i.i.i.i.i + ; in Loop: Header=BB9_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1863 +.LBB9_1847: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1848: ; in Loop: Header=BB9_1847 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1849: ; %Flow592 + ; in Loop: Header=BB9_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1850: ; in Loop: Header=BB9_1847 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1851: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2624.i.i.i.i.i + ; in Loop: Header=BB9_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1852: ; in Loop: Header=BB9_1847 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1853: ; %Flow591 + ; in Loop: Header=BB9_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1854: ; in Loop: Header=BB9_1847 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1855: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2627.i.i.i.i.i + ; in Loop: Header=BB9_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1856: ; in Loop: Header=BB9_1847 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1857: ; %Flow590 + ; in Loop: Header=BB9_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1858: ; in Loop: Header=BB9_1847 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1859: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2630.i.i.i.i.i + ; in Loop: Header=BB9_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1860: ; in Loop: Header=BB9_1847 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s10 + ; implicit-def: $vgpr37 +; %bb.1861: ; %Flow589 + ; in Loop: Header=BB9_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1846 +; %bb.1862: ; in Loop: Header=BB9_1847 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB9_1846 +.LBB9_1863: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2636.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_1865 +.LBB9_1864: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2649.i.i.i.i.i + ; in Loop: Header=BB9_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1881 +.LBB9_1865: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1866: ; in Loop: Header=BB9_1865 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1867: ; %Flow588 + ; in Loop: Header=BB9_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1868: ; in Loop: Header=BB9_1865 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1869: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2640.i.i.i.i.i + ; in Loop: Header=BB9_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1870: ; in Loop: Header=BB9_1865 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1871: ; %Flow587 + ; in Loop: Header=BB9_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1872: ; in Loop: Header=BB9_1865 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1873: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2643.i.i.i.i.i + ; in Loop: Header=BB9_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1874: ; in Loop: Header=BB9_1865 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1875: ; %Flow586 + ; in Loop: Header=BB9_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1876: ; in Loop: Header=BB9_1865 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1877: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2646.i.i.i.i.i + ; in Loop: Header=BB9_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1878: ; in Loop: Header=BB9_1865 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1879: ; %Flow585 + ; in Loop: Header=BB9_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1864 +; %bb.1880: ; in Loop: Header=BB9_1865 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_1864 +.LBB9_1881: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2653 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_1883 +.LBB9_1882: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2666.i.i.i.i.i + ; in Loop: Header=BB9_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1899 +.LBB9_1883: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1884: ; in Loop: Header=BB9_1883 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1885: ; %Flow584 + ; in Loop: Header=BB9_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1886: ; in Loop: Header=BB9_1883 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1887: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2657.i.i.i.i.i + ; in Loop: Header=BB9_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1888: ; in Loop: Header=BB9_1883 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1889: ; %Flow583 + ; in Loop: Header=BB9_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1890: ; in Loop: Header=BB9_1883 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1891: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2660.i.i.i.i.i + ; in Loop: Header=BB9_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1892: ; in Loop: Header=BB9_1883 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1893: ; %Flow582 + ; in Loop: Header=BB9_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1894: ; in Loop: Header=BB9_1883 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1895: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2663.i.i.i.i.i + ; in Loop: Header=BB9_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1896: ; in Loop: Header=BB9_1883 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1897: ; %Flow581 + ; in Loop: Header=BB9_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1882 +; %bb.1898: ; in Loop: Header=BB9_1883 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_1882 +.LBB9_1899: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2669.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_1901 +.LBB9_1900: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2682.i.i.i.i.i + ; in Loop: Header=BB9_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_1917 +.LBB9_1901: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1902: ; in Loop: Header=BB9_1901 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1903: ; %Flow580 + ; in Loop: Header=BB9_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1904: ; in Loop: Header=BB9_1901 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1905: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2673.i.i.i.i.i + ; in Loop: Header=BB9_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1906: ; in Loop: Header=BB9_1901 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1907: ; %Flow579 + ; in Loop: Header=BB9_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1908: ; in Loop: Header=BB9_1901 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1909: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2676.i.i.i.i.i + ; in Loop: Header=BB9_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1910: ; in Loop: Header=BB9_1901 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1911: ; %Flow578 + ; in Loop: Header=BB9_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1912: ; in Loop: Header=BB9_1901 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1913: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2679.i.i.i.i.i + ; in Loop: Header=BB9_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1914: ; in Loop: Header=BB9_1901 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1915: ; %Flow577 + ; in Loop: Header=BB9_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_1900 +; %bb.1916: ; in Loop: Header=BB9_1901 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_1900 +.LBB9_1917: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2814 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v18, a47 + v_and_b32_e32 v18, 0x7f800000, v18 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1918: + v_accvgpr_read_b32 v19, a47 + v_bfe_u32 v18, v19, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v19, v18, s6 +; %bb.1919: ; %Flow576 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1920: + v_mov_b32_e32 v18, 0 + v_accvgpr_read_b32 v20, a47 + v_or_b32_e32 v19, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v20, vcc +; %bb.1921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2879.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v19, a46 + v_and_b32_e32 v19, 0x7f800000, v19 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1922: + v_accvgpr_read_b32 v20, a46 + v_bfe_u32 v19, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v20, v19, s6 +; %bb.1923: ; %Flow575 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1924: + v_mov_b32_e32 v19, 0 + v_accvgpr_read_b32 v21, a46 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v21, vcc +; %bb.1925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2882.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v20, a45 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1926: + v_accvgpr_read_b32 v21, a45 + v_bfe_u32 v20, v21, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v21, v20, s6 +; %bb.1927: ; %Flow574 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1928: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v22, a45 + v_or_b32_e32 v21, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v22, vcc +; %bb.1929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2885.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v21, a44 + v_and_b32_e32 v21, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1930: + v_accvgpr_read_b32 v22, a44 + v_bfe_u32 v21, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v22, v21, s6 +; %bb.1931: ; %Flow573 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1932: + v_mov_b32_e32 v21, 0 + v_accvgpr_read_b32 v23, a44 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v23, vcc +; %bb.1933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2888.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v22, a43 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1934: + v_accvgpr_read_b32 v23, a43 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 +; %bb.1935: ; %Flow572 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1936: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a43 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.1937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2891.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v23, a42 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1938: + v_accvgpr_read_b32 v24, a42 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 +; %bb.1939: ; %Flow571 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1940: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a42 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.1941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2894.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v24, a41 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1942: + v_accvgpr_read_b32 v25, a41 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 +; %bb.1943: ; %Flow570 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1944: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a41 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.1945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2897.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v25, a40 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1946: + v_accvgpr_read_b32 v26, a40 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 +; %bb.1947: ; %Flow569 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1948: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a40 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.1949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2900.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v26, a39 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1950: + v_accvgpr_read_b32 v27, a39 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 +; %bb.1951: ; %Flow568 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1952: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a39 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.1953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2903.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v27, a38 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1954: + v_accvgpr_read_b32 v28, a38 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 +; %bb.1955: ; %Flow567 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1956: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a38 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.1957: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2906.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v28, a37 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1958: + v_accvgpr_read_b32 v29, a37 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 +; %bb.1959: ; %Flow566 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1960: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a37 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.1961: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2909.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v29, a36 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1962: + v_accvgpr_read_b32 v30, a36 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 +; %bb.1963: ; %Flow565 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1964: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a36 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.1965: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2912.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v30, a35 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1966: + v_accvgpr_read_b32 v31, a35 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 +; %bb.1967: ; %Flow564 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1968: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a35 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.1969: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2915.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v31, a34 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1970: + v_accvgpr_read_b32 v32, a34 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 +; %bb.1971: ; %Flow563 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1972: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a34 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.1973: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2918.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v32, a33 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1974: + v_accvgpr_read_b32 v33, a33 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 +; %bb.1975: ; %Flow562 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1976: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a33 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.1977: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2921.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v33, a15 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1978: + v_accvgpr_read_b32 v34, a15 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 +; %bb.1979: ; %Flow561 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1980: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a15 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.1981: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2924.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v34, a32 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1982: + v_accvgpr_read_b32 v35, a32 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 +; %bb.1983: ; %Flow560 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1984: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a32 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.1985: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2927.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v35, a14 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1986: + v_accvgpr_read_b32 v36, a14 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 +; %bb.1987: ; %Flow559 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1988: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a14 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.1989: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2930.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v36, a13 + v_and_b32_e32 v36, 0x7f800000, v36 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1990: + v_accvgpr_read_b32 v37, a13 + v_bfe_u32 v36, v37, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v37, v36, s6 +; %bb.1991: ; %Flow558 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1992: + v_mov_b32_e32 v36, 0 + v_accvgpr_read_b32 v39, a13 + v_or_b32_e32 v37, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v39, vcc +; %bb.1993: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2933.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v37, a12 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1994: + v_accvgpr_read_b32 v39, a12 + v_bfe_u32 v37, v39, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v39, v37, s6 +; %bb.1995: ; %Flow557 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1996: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v40, a12 + v_or_b32_e32 v39, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v40, vcc +; %bb.1997: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2936.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v39, a11 + v_and_b32_e32 v39, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1998: + v_accvgpr_read_b32 v40, a11 + v_bfe_u32 v39, v40, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v40, v39, s6 +; %bb.1999: ; %Flow556 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2000: + v_mov_b32_e32 v39, 0 + v_accvgpr_read_b32 v41, a11 + v_or_b32_e32 v40, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v41, vcc +; %bb.2001: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2939.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v40, a10 + v_and_b32_e32 v40, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2002: + v_accvgpr_read_b32 v41, a10 + v_bfe_u32 v40, v41, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v41, v40, s6 +; %bb.2003: ; %Flow555 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2004: + v_mov_b32_e32 v40, 0 + v_accvgpr_read_b32 v42, a10 + v_or_b32_e32 v41, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v42, vcc +; %bb.2005: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2942.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a9 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2006: + v_accvgpr_read_b32 v42, a9 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.2007: ; %Flow554 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2008: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a9 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.2009: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2945.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a8 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2010: + v_accvgpr_read_b32 v43, a8 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.2011: ; %Flow553 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2012: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a8 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.2013: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2948.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a7 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2014: + v_accvgpr_read_b32 v77, a7 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.2015: ; %Flow552 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2016: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a7 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.2017: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2951.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a6 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2018: + v_accvgpr_read_b32 v78, a6 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.2019: ; %Flow551 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2020: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a6 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.2021: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2954.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a5 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2022: + v_accvgpr_read_b32 v79, a5 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.2023: ; %Flow550 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2024: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a5 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.2025: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2957.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a4 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2026: + v_accvgpr_read_b32 v80, a4 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.2027: ; %Flow549 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2028: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a4 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.2029: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2960.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a3 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2030: + v_accvgpr_read_b32 v81, a3 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.2031: ; %Flow548 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2032: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a3 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.2033: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2963.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a2 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2034: + v_accvgpr_read_b32 v82, a2 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.2035: ; %Flow547 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2036: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a2 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.2037: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2966.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a1 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2038: + v_accvgpr_read_b32 v83, a1 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.2039: ; %Flow546 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2040: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a1 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.2041: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2969.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2042: + v_bfe_u32 v83, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v86, v83, s6 +; %bb.2043: ; %Flow545 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2044: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v86, vcc +; %bb.2045: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2973 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s8, v18 + v_mad_u64_u32 v[38:39], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[40:41], v[38:39], 1, s[0:1] + global_load_dwordx2 v[36:37], v[40:41], off + v_lshl_or_b32 v18, v18, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v42, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v43, 0 + s_branch .LBB9_2047 +.LBB9_2046: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i3036.i.i.i.i.i + ; in Loop: Header=BB9_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v76, v35, s10 + v_perm_b32 v34, v74, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[40:41], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2063 +.LBB9_2047: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2048: ; in Loop: Header=BB9_2047 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.2049: ; %Flow544 + ; in Loop: Header=BB9_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2050: ; in Loop: Header=BB9_2047 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.2051: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i3027.i.i.i.i.i + ; in Loop: Header=BB9_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v74, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2052: ; in Loop: Header=BB9_2047 Depth=1 + v_bfe_u32 v74, v35, 16, 1 + v_add3_u32 v74, v35, v74, s9 + ; implicit-def: $vgpr35 +; %bb.2053: ; %Flow543 + ; in Loop: Header=BB9_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2054: ; in Loop: Header=BB9_2047 Depth=1 + v_or_b32_e32 v74, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v35, vcc +; %bb.2055: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i3030.i.i.i.i.i + ; in Loop: Header=BB9_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v75, v42, v35 + v_and_b32_e32 v35, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2056: ; in Loop: Header=BB9_2047 Depth=1 + v_bfe_u32 v35, v75, 16, 1 + v_add3_u32 v35, v75, v35, s9 + ; implicit-def: $vgpr75 +; %bb.2057: ; %Flow542 + ; in Loop: Header=BB9_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2058: ; in Loop: Header=BB9_2047 Depth=1 + v_or_b32_e32 v35, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v75, vcc +; %bb.2059: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i3033.i.i.i.i.i + ; in Loop: Header=BB9_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v75, 0xffff0000, v37 + v_add_f32_e32 v75, v31, v75 + v_and_b32_e32 v76, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2060: ; in Loop: Header=BB9_2047 Depth=1 + v_bfe_u32 v76, v75, 16, 1 + v_add3_u32 v76, v75, v76, s9 + ; implicit-def: $vgpr75 +; %bb.2061: ; %Flow541 + ; in Loop: Header=BB9_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2046 +; %bb.2062: ; in Loop: Header=BB9_2047 Depth=1 + v_or_b32_e32 v76, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v75, vcc + s_branch .LBB9_2046 +.LBB9_2063: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i3039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[40:41], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB9_2065 +.LBB9_2064: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i3052.i.i.i.i.i + ; in Loop: Header=BB9_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v74, v33, s10 + v_perm_b32 v32, v42, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[40:41], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2081 +.LBB9_2065: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2066: ; in Loop: Header=BB9_2065 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.2067: ; %Flow540 + ; in Loop: Header=BB9_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2068: ; in Loop: Header=BB9_2065 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.2069: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i3043.i.i.i.i.i + ; in Loop: Header=BB9_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v42, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2070: ; in Loop: Header=BB9_2065 Depth=1 + v_bfe_u32 v42, v33, 16, 1 + v_add3_u32 v42, v33, v42, s9 + ; implicit-def: $vgpr33 +; %bb.2071: ; %Flow539 + ; in Loop: Header=BB9_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2072: ; in Loop: Header=BB9_2065 Depth=1 + v_or_b32_e32 v42, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v33, vcc +; %bb.2073: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i3046.i.i.i.i.i + ; in Loop: Header=BB9_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v43, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2074: ; in Loop: Header=BB9_2065 Depth=1 + v_bfe_u32 v33, v43, 16, 1 + v_add3_u32 v33, v43, v33, s9 + ; implicit-def: $vgpr43 +; %bb.2075: ; %Flow538 + ; in Loop: Header=BB9_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2076: ; in Loop: Header=BB9_2065 Depth=1 + v_or_b32_e32 v33, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v43, vcc +; %bb.2077: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i3049.i.i.i.i.i + ; in Loop: Header=BB9_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v35 + v_add_f32_e32 v43, v37, v43 + v_and_b32_e32 v74, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2078: ; in Loop: Header=BB9_2065 Depth=1 + v_bfe_u32 v74, v43, 16, 1 + v_add3_u32 v74, v43, v74, s9 + ; implicit-def: $vgpr43 +; %bb.2079: ; %Flow537 + ; in Loop: Header=BB9_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2064 +; %bb.2080: ; in Loop: Header=BB9_2065 Depth=1 + v_or_b32_e32 v74, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v43, vcc + s_branch .LBB9_2064 +.LBB9_2081: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3056 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v38 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v38, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB9_2083 +.LBB9_2082: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i3069.i.i.i.i.i + ; in Loop: Header=BB9_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v42, v31, s10 + v_perm_b32 v30, v40, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2099 +.LBB9_2083: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2084: ; in Loop: Header=BB9_2083 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.2085: ; %Flow536 + ; in Loop: Header=BB9_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2086: ; in Loop: Header=BB9_2083 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.2087: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i3060.i.i.i.i.i + ; in Loop: Header=BB9_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v40, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2088: ; in Loop: Header=BB9_2083 Depth=1 + v_bfe_u32 v40, v31, 16, 1 + v_add3_u32 v40, v31, v40, s9 + ; implicit-def: $vgpr31 +; %bb.2089: ; %Flow535 + ; in Loop: Header=BB9_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2090: ; in Loop: Header=BB9_2083 Depth=1 + v_or_b32_e32 v40, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v31, vcc +; %bb.2091: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i3063.i.i.i.i.i + ; in Loop: Header=BB9_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v41, v38, v31 + v_and_b32_e32 v31, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2092: ; in Loop: Header=BB9_2083 Depth=1 + v_bfe_u32 v31, v41, 16, 1 + v_add3_u32 v31, v41, v31, s9 + ; implicit-def: $vgpr41 +; %bb.2093: ; %Flow534 + ; in Loop: Header=BB9_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2094: ; in Loop: Header=BB9_2083 Depth=1 + v_or_b32_e32 v31, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v41, vcc +; %bb.2095: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i3066.i.i.i.i.i + ; in Loop: Header=BB9_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v33 + v_add_f32_e32 v41, v27, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2096: ; in Loop: Header=BB9_2083 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.2097: ; %Flow533 + ; in Loop: Header=BB9_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2082 +; %bb.2098: ; in Loop: Header=BB9_2083 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB9_2082 +.LBB9_2099: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i3072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_2101 +.LBB9_2100: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i3085.i.i.i.i.i + ; in Loop: Header=BB9_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v40, v29, s10 + v_perm_b32 v28, v38, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2117 +.LBB9_2101: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2102: ; in Loop: Header=BB9_2101 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.2103: ; %Flow532 + ; in Loop: Header=BB9_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2104: ; in Loop: Header=BB9_2101 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.2105: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i3076.i.i.i.i.i + ; in Loop: Header=BB9_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v38, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2106: ; in Loop: Header=BB9_2101 Depth=1 + v_bfe_u32 v38, v29, 16, 1 + v_add3_u32 v38, v29, v38, s9 + ; implicit-def: $vgpr29 +; %bb.2107: ; %Flow531 + ; in Loop: Header=BB9_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2108: ; in Loop: Header=BB9_2101 Depth=1 + v_or_b32_e32 v38, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v29, vcc +; %bb.2109: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i3079.i.i.i.i.i + ; in Loop: Header=BB9_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v39, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2110: ; in Loop: Header=BB9_2101 Depth=1 + v_bfe_u32 v29, v39, 16, 1 + v_add3_u32 v29, v39, v29, s9 + ; implicit-def: $vgpr39 +; %bb.2111: ; %Flow530 + ; in Loop: Header=BB9_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2112: ; in Loop: Header=BB9_2101 Depth=1 + v_or_b32_e32 v29, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v39, vcc +; %bb.2113: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i3082.i.i.i.i.i + ; in Loop: Header=BB9_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v39, 0xffff0000, v31 + v_add_f32_e32 v39, v33, v39 + v_and_b32_e32 v40, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2114: ; in Loop: Header=BB9_2101 Depth=1 + v_bfe_u32 v40, v39, 16, 1 + v_add3_u32 v40, v39, v40, s9 + ; implicit-def: $vgpr39 +; %bb.2115: ; %Flow529 + ; in Loop: Header=BB9_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2100 +; %bb.2116: ; in Loop: Header=BB9_2101 Depth=1 + v_or_b32_e32 v40, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v39, vcc + s_branch .LBB9_2100 +.LBB9_2117: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3089 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB9_2119 +.LBB9_2118: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i3102.i.i.i.i.i + ; in Loop: Header=BB9_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v38, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2135 +.LBB9_2119: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2120: ; in Loop: Header=BB9_2119 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.2121: ; %Flow528 + ; in Loop: Header=BB9_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2122: ; in Loop: Header=BB9_2119 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.2123: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i3093.i.i.i.i.i + ; in Loop: Header=BB9_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2124: ; in Loop: Header=BB9_2119 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.2125: ; %Flow527 + ; in Loop: Header=BB9_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2126: ; in Loop: Header=BB9_2119 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.2127: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i3096.i.i.i.i.i + ; in Loop: Header=BB9_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2128: ; in Loop: Header=BB9_2119 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.2129: ; %Flow526 + ; in Loop: Header=BB9_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2130: ; in Loop: Header=BB9_2119 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.2131: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i3099.i.i.i.i.i + ; in Loop: Header=BB9_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v38, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2132: ; in Loop: Header=BB9_2119 Depth=1 + v_bfe_u32 v38, v37, 16, 1 + v_add3_u32 v38, v37, v38, s9 + ; implicit-def: $vgpr37 +; %bb.2133: ; %Flow525 + ; in Loop: Header=BB9_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2118 +; %bb.2134: ; in Loop: Header=BB9_2119 Depth=1 + v_or_b32_e32 v38, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v37, vcc + s_branch .LBB9_2118 +.LBB9_2135: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i3105.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB9_2137 +.LBB9_2136: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i3118.i.i.i.i.i + ; in Loop: Header=BB9_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2153 +.LBB9_2137: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2138: ; in Loop: Header=BB9_2137 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.2139: ; %Flow524 + ; in Loop: Header=BB9_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2140: ; in Loop: Header=BB9_2137 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.2141: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i3109.i.i.i.i.i + ; in Loop: Header=BB9_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2142: ; in Loop: Header=BB9_2137 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.2143: ; %Flow523 + ; in Loop: Header=BB9_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2144: ; in Loop: Header=BB9_2137 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.2145: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i3112.i.i.i.i.i + ; in Loop: Header=BB9_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2146: ; in Loop: Header=BB9_2137 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.2147: ; %Flow522 + ; in Loop: Header=BB9_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2148: ; in Loop: Header=BB9_2137 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.2149: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i3115.i.i.i.i.i + ; in Loop: Header=BB9_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2150: ; in Loop: Header=BB9_2137 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.2151: ; %Flow521 + ; in Loop: Header=BB9_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2136 +; %bb.2152: ; in Loop: Header=BB9_2137 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB9_2136 +.LBB9_2153: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3122 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB9_2155 +.LBB9_2154: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i3135.i.i.i.i.i + ; in Loop: Header=BB9_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2171 +.LBB9_2155: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2156: ; in Loop: Header=BB9_2155 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.2157: ; %Flow520 + ; in Loop: Header=BB9_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2158: ; in Loop: Header=BB9_2155 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.2159: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i3126.i.i.i.i.i + ; in Loop: Header=BB9_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2160: ; in Loop: Header=BB9_2155 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.2161: ; %Flow519 + ; in Loop: Header=BB9_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2162: ; in Loop: Header=BB9_2155 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.2163: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i3129.i.i.i.i.i + ; in Loop: Header=BB9_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2164: ; in Loop: Header=BB9_2155 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.2165: ; %Flow518 + ; in Loop: Header=BB9_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2166: ; in Loop: Header=BB9_2155 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.2167: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i3132.i.i.i.i.i + ; in Loop: Header=BB9_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2168: ; in Loop: Header=BB9_2155 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.2169: ; %Flow517 + ; in Loop: Header=BB9_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2154 +; %bb.2170: ; in Loop: Header=BB9_2155 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB9_2154 +.LBB9_2171: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i3138.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB9_2173 +.LBB9_2172: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i3151.i.i.i.i.i + ; in Loop: Header=BB9_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB9_2189 +.LBB9_2173: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2174: ; in Loop: Header=BB9_2173 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.2175: ; %Flow515 + ; in Loop: Header=BB9_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2176: ; in Loop: Header=BB9_2173 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.2177: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i3142.i.i.i.i.i + ; in Loop: Header=BB9_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2178: ; in Loop: Header=BB9_2173 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.2179: ; %Flow514 + ; in Loop: Header=BB9_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2180: ; in Loop: Header=BB9_2173 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.2181: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i3145.i.i.i.i.i + ; in Loop: Header=BB9_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2182: ; in Loop: Header=BB9_2173 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.2183: ; %Flow513 + ; in Loop: Header=BB9_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2184: ; in Loop: Header=BB9_2173 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.2185: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i3148.i.i.i.i.i + ; in Loop: Header=BB9_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2186: ; in Loop: Header=BB9_2173 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.2187: ; %Flow + ; in Loop: Header=BB9_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB9_2172 +; %bb.2188: ; in Loop: Header=BB9_2173 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB9_2172 +.LBB9_2189: ; %Flow516 + s_or_b64 exec, exec, s[2:3] + s_mov_b64 vcc, 0 + s_branch .LBB9_12 +.LBB9_2190: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2191: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 + ; implicit-def: $vgpr73 +; %bb.2192: ; %Flow1280 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2193: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.2194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2195: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v72, v19, s7 + ; implicit-def: $vgpr72 +; %bb.2196: ; %Flow1279 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2197: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v72, vcc +; %bb.2198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2199: + v_bfe_u32 v19, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v71, v19, s7 + ; implicit-def: $vgpr71 +; %bb.2200: ; %Flow1278 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2201: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v71, vcc +; %bb.2202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2203: + v_bfe_u32 v19, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v70, v19, s7 + ; implicit-def: $vgpr70 +; %bb.2204: ; %Flow1277 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2205: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v70, vcc +; %bb.2206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2207: + v_bfe_u32 v19, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v68, v19, s7 + ; implicit-def: $vgpr68 +; %bb.2208: ; %Flow1276 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2209: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v23, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v68, vcc +; %bb.2210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2211: + v_bfe_u32 v19, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v67, v19, s7 + ; implicit-def: $vgpr67 +; %bb.2212: ; %Flow1275 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2213: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v24, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v67, vcc +; %bb.2214: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2215: + v_bfe_u32 v19, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v66, v19, s7 + ; implicit-def: $vgpr66 +; %bb.2216: ; %Flow1274 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2217: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v25, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v66, vcc +; %bb.2218: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2219: + v_bfe_u32 v19, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v65, v19, s7 + ; implicit-def: $vgpr65 +; %bb.2220: ; %Flow1273 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2221: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v26, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v65, vcc +; %bb.2222: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2223: + v_bfe_u32 v19, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v64, v19, s7 + ; implicit-def: $vgpr64 +; %bb.2224: ; %Flow1272 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2225: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v27, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v64, vcc +; %bb.2226: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2227: + v_bfe_u32 v19, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v63, v19, s7 + ; implicit-def: $vgpr63 +; %bb.2228: ; %Flow1271 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2229: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v28, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v63, vcc +; %bb.2230: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2231: + v_bfe_u32 v19, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v62, v19, s7 + ; implicit-def: $vgpr62 +; %bb.2232: ; %Flow1270 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2233: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v29, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v62, vcc +; %bb.2234: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2235: + v_bfe_u32 v19, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v61, v19, s7 + ; implicit-def: $vgpr61 +; %bb.2236: ; %Flow1269 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2237: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v30, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v61, vcc +; %bb.2238: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2239: + v_bfe_u32 v19, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v60, v19, s7 + ; implicit-def: $vgpr60 +; %bb.2240: ; %Flow1268 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2241: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v31, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v60, vcc +; %bb.2242: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2243: + v_bfe_u32 v19, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v59, v19, s7 + ; implicit-def: $vgpr59 +; %bb.2244: ; %Flow1267 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2245: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v32, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v59, vcc +; %bb.2246: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2247: + v_bfe_u32 v19, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v58, v19, s7 + ; implicit-def: $vgpr58 +; %bb.2248: ; %Flow1266 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2249: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v33, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v58, vcc +; %bb.2250: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2251: + v_bfe_u32 v19, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v56, v19, s7 + ; implicit-def: $vgpr56 +; %bb.2252: ; %Flow1265 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2253: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v34, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v56, vcc +; %bb.2254: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2255: + v_bfe_u32 v19, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v57, v19, s7 + ; implicit-def: $vgpr57 +; %bb.2256: ; %Flow1264 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2257: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v35, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v57, vcc +; %bb.2258: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2259: + v_bfe_u32 v19, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v55, v19, s7 + ; implicit-def: $vgpr55 +; %bb.2260: ; %Flow1263 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2261: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v36, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v55, vcc +; %bb.2262: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2263: + v_bfe_u32 v19, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v54, v19, s7 + ; implicit-def: $vgpr54 +; %bb.2264: ; %Flow1262 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2265: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v37, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v37, v54, vcc +; %bb.2266: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2267: + v_bfe_u32 v19, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v53, v19, s7 + ; implicit-def: $vgpr53 +; %bb.2268: ; %Flow1261 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2269: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v38, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v53, vcc +; %bb.2270: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2271: + v_bfe_u32 v19, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v52, v19, s7 + ; implicit-def: $vgpr52 +; %bb.2272: ; %Flow1260 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2273: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v39, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v52, vcc +; %bb.2274: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2275: + v_bfe_u32 v19, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v51, v19, s7 + ; implicit-def: $vgpr51 +; %bb.2276: ; %Flow1259 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2277: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v40, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v51, vcc +; %bb.2278: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2279: + v_bfe_u32 v19, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v50, v19, s7 + ; implicit-def: $vgpr50 +; %bb.2280: ; %Flow1258 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2281: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v41, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v50, vcc +; %bb.2282: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2283: + v_bfe_u32 v19, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v49, v19, s7 + ; implicit-def: $vgpr49 +; %bb.2284: ; %Flow1257 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2285: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v42, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v49, vcc +; %bb.2286: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2287: + v_bfe_u32 v19, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v48, v19, s7 + ; implicit-def: $vgpr48 +; %bb.2288: ; %Flow1256 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2289: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v43, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v48, vcc +; %bb.2290: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2291: + v_bfe_u32 v19, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v48, v47, v19, s7 + ; implicit-def: $vgpr47 +; %bb.2292: ; %Flow1255 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2293: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v48, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v48, v47, vcc +; %bb.2294: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2295: + v_bfe_u32 v19, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v47, v46, v19, s7 + ; implicit-def: $vgpr46 +; %bb.2296: ; %Flow1254 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2297: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v47, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v47, v46, vcc +; %bb.2298: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2299: + v_bfe_u32 v19, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v46, v45, v19, s7 + ; implicit-def: $vgpr45 +; %bb.2300: ; %Flow1253 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2301: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v46, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v46, v45, vcc +; %bb.2302: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2303: + v_bfe_u32 v19, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v45, v44, v19, s7 + ; implicit-def: $vgpr44 +; %bb.2304: ; %Flow1252 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2305: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v45, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v45, v44, vcc +; %bb.2306: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2307: + v_bfe_u32 v19, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v44, v255, v19, s7 + ; implicit-def: $vgpr255 +; %bb.2308: ; %Flow1251 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2309: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v44, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v44, v255, vcc +; %bb.2310: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2311: + v_bfe_u32 v19, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v49, v254, v19, s7 + ; implicit-def: $vgpr254 +; %bb.2312: ; %Flow1250 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2313: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v49, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v49, v254, vcc +; %bb.2314: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2315: + v_bfe_u32 v19, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v50, v253, v19, s7 + ; implicit-def: $vgpr253 +; %bb.2316: ; %Flow1249 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2317: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v50, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v50, v253, vcc +; %bb.2318: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_add_i32 s2, s4, 0x7fffffff + s_mul_i32 s2, s2, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s4, s3, s2 + v_and_b32_e32 v19, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v51, 3, v1 + v_and_or_b32 v51, v51, 12, s2 + v_lshlrev_b32_e32 v51, 7, v51 + v_lshl_or_b32 v51, v69, 1, v51 + v_lshlrev_b32_e32 v19, 1, v19 + s_and_b32 s2, s6, 64 + v_or3_b32 v19, v51, v19, s2 + ds_write_b16_d16_hi v19, v18 + ds_write_b16_d16_hi v19, v20 offset:128 + ds_write_b16_d16_hi v19, v21 offset:256 + ds_write_b16_d16_hi v19, v22 offset:384 + ds_write_b16_d16_hi v19, v23 offset:1024 + ds_write_b16_d16_hi v19, v24 offset:1152 + ds_write_b16_d16_hi v19, v25 offset:1280 + ds_write_b16_d16_hi v19, v26 offset:1408 + ds_write_b16_d16_hi v19, v27 offset:2048 + ds_write_b16_d16_hi v19, v28 offset:2176 + ds_write_b16_d16_hi v19, v29 offset:2304 + ds_write_b16_d16_hi v19, v30 offset:2432 + ds_write_b16_d16_hi v19, v31 offset:3072 + ds_write_b16_d16_hi v19, v32 offset:3200 + ds_write_b16_d16_hi v19, v33 offset:3328 + ds_write_b16_d16_hi v19, v34 offset:3456 + ds_write_b16_d16_hi v19, v35 offset:8192 + ds_write_b16_d16_hi v19, v36 offset:8320 + ds_write_b16_d16_hi v19, v37 offset:8448 + ds_write_b16_d16_hi v19, v38 offset:8576 + ds_write_b16_d16_hi v19, v39 offset:9216 + ds_write_b16_d16_hi v19, v40 offset:9344 + ds_write_b16_d16_hi v19, v41 offset:9472 + ds_write_b16_d16_hi v19, v42 offset:9600 + ds_write_b16_d16_hi v19, v43 offset:10240 + ds_write_b16_d16_hi v19, v48 offset:10368 + ds_write_b16_d16_hi v19, v47 offset:10496 + ds_write_b16_d16_hi v19, v46 offset:10624 + ds_write_b16_d16_hi v19, v45 offset:11264 + ds_write_b16_d16_hi v19, v44 offset:11392 + ds_write_b16_d16_hi v19, v49 offset:11520 + ds_write_b16_d16_hi v19, v50 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v20, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v1, 1, v1 + v_and_b32_e32 v1, 60, v1 + v_add_u32_e32 v18, s2, v1 + v_lshlrev_b32_e32 v21, 7, v18 + v_lshl_or_b32 v21, v20, 1, v21 + ds_read_b128 v[24:27], v21 + ds_read_b128 v[28:31], v21 offset:128 + ds_read_b128 v[32:35], v21 offset:256 + ds_read_b128 v[36:39], v21 offset:384 + v_add_u32_e32 v21, s18, v18 + v_or_b32_e32 v18, s19, v20 + v_mad_u64_u32 v[22:23], s[2:3], v21, s16, v[18:19] + s_add_i32 s2, s5, s4 + s_lshl_b32 s2, s2, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v21, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v21, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v22 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v22, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v21 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v22, s[0:3], 8 offen + v_add_lshl_u32 v21, v21, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v21, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s4, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2319: + v_bfe_u32 v21, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v252, v21, s6 + ; implicit-def: $vgpr252 +; %bb.2320: ; %Flow1248 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2321: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v252, vcc +; %bb.2322: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2323: + v_bfe_u32 v22, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v251, v22, s6 + ; implicit-def: $vgpr251 +; %bb.2324: ; %Flow1247 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2325: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v251, vcc +; %bb.2326: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2327: + v_bfe_u32 v23, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v250, v23, s6 + ; implicit-def: $vgpr250 +; %bb.2328: ; %Flow1246 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2329: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v250, vcc +; %bb.2330: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2331: + v_bfe_u32 v24, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v249, v24, s6 + ; implicit-def: $vgpr249 +; %bb.2332: ; %Flow1245 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2333: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v249, vcc +; %bb.2334: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2335: + v_bfe_u32 v25, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v248, v25, s6 + ; implicit-def: $vgpr248 +; %bb.2336: ; %Flow1244 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2337: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v248, vcc +; %bb.2338: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2339: + v_bfe_u32 v26, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v247, v26, s6 + ; implicit-def: $vgpr247 +; %bb.2340: ; %Flow1243 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2341: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v247, vcc +; %bb.2342: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2343: + v_bfe_u32 v27, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v246, v27, s6 + ; implicit-def: $vgpr246 +; %bb.2344: ; %Flow1242 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2345: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v246, vcc +; %bb.2346: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2347: + v_bfe_u32 v28, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v245, v28, s6 + ; implicit-def: $vgpr245 +; %bb.2348: ; %Flow1241 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2349: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v245, vcc +; %bb.2350: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2351: + v_bfe_u32 v29, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v244, v29, s6 + ; implicit-def: $vgpr244 +; %bb.2352: ; %Flow1240 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2353: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v244, vcc +; %bb.2354: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2355: + v_bfe_u32 v30, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v243, v30, s6 + ; implicit-def: $vgpr243 +; %bb.2356: ; %Flow1239 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2357: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v243, vcc +; %bb.2358: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2359: + v_bfe_u32 v31, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v242, v31, s6 + ; implicit-def: $vgpr242 +; %bb.2360: ; %Flow1238 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2361: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v242, vcc +; %bb.2362: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2363: + v_bfe_u32 v32, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v241, v32, s6 + ; implicit-def: $vgpr241 +; %bb.2364: ; %Flow1237 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2365: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v241, vcc +; %bb.2366: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2367: + v_bfe_u32 v33, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v240, v33, s6 + ; implicit-def: $vgpr240 +; %bb.2368: ; %Flow1236 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2369: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v240, vcc +; %bb.2370: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2371: + v_bfe_u32 v34, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v239, v34, s6 + ; implicit-def: $vgpr239 +; %bb.2372: ; %Flow1235 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2373: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v239, vcc +; %bb.2374: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2375: + v_bfe_u32 v35, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v238, v35, s6 + ; implicit-def: $vgpr238 +; %bb.2376: ; %Flow1234 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2377: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v238, vcc +; %bb.2378: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2379: + v_bfe_u32 v36, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v236, v36, s6 + ; implicit-def: $vgpr236 +; %bb.2380: ; %Flow1233 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2381: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v236, vcc +; %bb.2382: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2383: + v_bfe_u32 v37, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v237, v37, s6 + ; implicit-def: $vgpr237 +; %bb.2384: ; %Flow1232 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2385: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v237, vcc +; %bb.2386: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2387: + v_bfe_u32 v38, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v235, v38, s6 + ; implicit-def: $vgpr235 +; %bb.2388: ; %Flow1231 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2389: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v235, vcc +; %bb.2390: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2391: + v_bfe_u32 v39, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v234, v39, s6 + ; implicit-def: $vgpr234 +; %bb.2392: ; %Flow1230 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2393: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v234, vcc +; %bb.2394: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2395: + v_bfe_u32 v40, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v233, v40, s6 + ; implicit-def: $vgpr233 +; %bb.2396: ; %Flow1229 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2397: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v233, vcc +; %bb.2398: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2399: + v_bfe_u32 v41, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v232, v41, s6 + ; implicit-def: $vgpr232 +; %bb.2400: ; %Flow1228 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2401: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v232, vcc +; %bb.2402: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2403: + v_bfe_u32 v42, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v231, v42, s6 + ; implicit-def: $vgpr231 +; %bb.2404: ; %Flow1227 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2405: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v231, vcc +; %bb.2406: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2407: + v_bfe_u32 v43, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v230, v43, s6 + ; implicit-def: $vgpr230 +; %bb.2408: ; %Flow1226 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2409: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v230, vcc +; %bb.2410: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2411: + v_bfe_u32 v44, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v229, v44, s6 + ; implicit-def: $vgpr229 +; %bb.2412: ; %Flow1225 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2413: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v229, vcc +; %bb.2414: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2415: + v_bfe_u32 v45, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v228, v45, s6 + ; implicit-def: $vgpr228 +; %bb.2416: ; %Flow1224 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2417: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v228, vcc +; %bb.2418: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2419: + v_bfe_u32 v46, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v227, v46, s6 + ; implicit-def: $vgpr227 +; %bb.2420: ; %Flow1223 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2421: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v227, vcc +; %bb.2422: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2423: + v_bfe_u32 v47, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v226, v47, s6 + ; implicit-def: $vgpr226 +; %bb.2424: ; %Flow1222 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2425: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v226, vcc +; %bb.2426: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2427: + v_bfe_u32 v48, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v225, v48, s6 + ; implicit-def: $vgpr225 +; %bb.2428: ; %Flow1221 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2429: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v225, vcc +; %bb.2430: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2431: + v_bfe_u32 v49, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v224, v49, s6 + ; implicit-def: $vgpr224 +; %bb.2432: ; %Flow1220 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2433: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v224, vcc +; %bb.2434: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2435: + v_bfe_u32 v50, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v223, v50, s6 + ; implicit-def: $vgpr223 +; %bb.2436: ; %Flow1219 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2437: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v223, vcc +; %bb.2438: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2439: + v_bfe_u32 v51, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v222, v51, s6 + ; implicit-def: $vgpr222 +; %bb.2440: ; %Flow1218 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2441: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v222, vcc +; %bb.2442: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2443: + v_bfe_u32 v52, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v221, v52, s6 + ; implicit-def: $vgpr221 +; %bb.2444: ; %Flow1217 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2445: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v221, vcc +; %bb.2446: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_287 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v21 + ds_write_b16_d16_hi v19, v22 offset:128 + ds_write_b16_d16_hi v19, v23 offset:256 + ds_write_b16_d16_hi v19, v24 offset:384 + ds_write_b16_d16_hi v19, v25 offset:1024 + ds_write_b16_d16_hi v19, v26 offset:1152 + ds_write_b16_d16_hi v19, v27 offset:1280 + ds_write_b16_d16_hi v19, v28 offset:1408 + ds_write_b16_d16_hi v19, v29 offset:2048 + ds_write_b16_d16_hi v19, v30 offset:2176 + ds_write_b16_d16_hi v19, v31 offset:2304 + ds_write_b16_d16_hi v19, v32 offset:2432 + ds_write_b16_d16_hi v19, v33 offset:3072 + ds_write_b16_d16_hi v19, v34 offset:3200 + ds_write_b16_d16_hi v19, v35 offset:3328 + ds_write_b16_d16_hi v19, v36 offset:3456 + ds_write_b16_d16_hi v19, v37 offset:8192 + ds_write_b16_d16_hi v19, v38 offset:8320 + ds_write_b16_d16_hi v19, v39 offset:8448 + ds_write_b16_d16_hi v19, v40 offset:8576 + ds_write_b16_d16_hi v19, v41 offset:9216 + ds_write_b16_d16_hi v19, v42 offset:9344 + ds_write_b16_d16_hi v19, v43 offset:9472 + ds_write_b16_d16_hi v19, v44 offset:9600 + ds_write_b16_d16_hi v19, v45 offset:10240 + ds_write_b16_d16_hi v19, v46 offset:10368 + ds_write_b16_d16_hi v19, v47 offset:10496 + ds_write_b16_d16_hi v19, v48 offset:10624 + ds_write_b16_d16_hi v19, v49 offset:11264 + ds_write_b16_d16_hi v19, v50 offset:11392 + ds_write_b16_d16_hi v19, v51 offset:11520 + ds_write_b16_d16_hi v19, v52 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshlrev_b32_e32 v21, 1, v20 + v_lshl_or_b32 v20, v22, 7, v21 + ds_read_b128 v[24:27], v20 + ds_read_b128 v[28:31], v20 offset:128 + ds_read_b128 v[32:35], v20 offset:256 + ds_read_b128 v[36:39], v20 offset:384 + v_add_u32_e32 v22, s18, v22 + v_or_b32_e32 v20, 64, v18 + v_mad_u64_u32 v[22:23], s[4:5], v22, s16, v[20:21] + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v23, s[0:3], 8 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v22, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2447: + v_bfe_u32 v22, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v220, v22, s6 + ; implicit-def: $vgpr220 +; %bb.2448: ; %Flow1216 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2449: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v220, vcc +; %bb.2450: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i352.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2451: + v_bfe_u32 v23, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v219, v23, s6 + ; implicit-def: $vgpr219 +; %bb.2452: ; %Flow1215 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2453: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v219, vcc +; %bb.2454: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i355.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2455: + v_bfe_u32 v24, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v218, v24, s6 + ; implicit-def: $vgpr218 +; %bb.2456: ; %Flow1214 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2457: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v218, vcc +; %bb.2458: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i358.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2459: + v_bfe_u32 v25, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v217, v25, s6 + ; implicit-def: $vgpr217 +; %bb.2460: ; %Flow1213 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2461: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v217, vcc +; %bb.2462: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i361.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2463: + v_bfe_u32 v26, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v216, v26, s6 + ; implicit-def: $vgpr216 +; %bb.2464: ; %Flow1212 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2465: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v216, vcc +; %bb.2466: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i364.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2467: + v_bfe_u32 v27, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v215, v27, s6 + ; implicit-def: $vgpr215 +; %bb.2468: ; %Flow1211 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2469: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v215, vcc +; %bb.2470: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i367.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2471: + v_bfe_u32 v28, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v214, v28, s6 + ; implicit-def: $vgpr214 +; %bb.2472: ; %Flow1210 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2473: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v214, vcc +; %bb.2474: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i370.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2475: + v_bfe_u32 v29, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v213, v29, s6 + ; implicit-def: $vgpr213 +; %bb.2476: ; %Flow1209 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2477: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v213, vcc +; %bb.2478: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i373.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2479: + v_bfe_u32 v30, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v212, v30, s6 + ; implicit-def: $vgpr212 +; %bb.2480: ; %Flow1208 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2481: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v212, vcc +; %bb.2482: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i376.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2483: + v_bfe_u32 v31, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v211, v31, s6 + ; implicit-def: $vgpr211 +; %bb.2484: ; %Flow1207 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2485: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v211, vcc +; %bb.2486: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i379.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2487: + v_bfe_u32 v32, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v210, v32, s6 + ; implicit-def: $vgpr210 +; %bb.2488: ; %Flow1206 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2489: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v210, vcc +; %bb.2490: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i382.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2491: + v_bfe_u32 v33, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v209, v33, s6 + ; implicit-def: $vgpr209 +; %bb.2492: ; %Flow1205 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2493: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v209, vcc +; %bb.2494: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i385.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2495: + v_bfe_u32 v34, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v208, v34, s6 + ; implicit-def: $vgpr208 +; %bb.2496: ; %Flow1204 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2497: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v208, vcc +; %bb.2498: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i388.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2499: + v_bfe_u32 v35, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v207, v35, s6 + ; implicit-def: $vgpr207 +; %bb.2500: ; %Flow1203 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2501: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v207, vcc +; %bb.2502: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i391.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2503: + v_bfe_u32 v36, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v206, v36, s6 + ; implicit-def: $vgpr206 +; %bb.2504: ; %Flow1202 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2505: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v206, vcc +; %bb.2506: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i394.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2507: + v_bfe_u32 v37, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v204, v37, s6 + ; implicit-def: $vgpr204 +; %bb.2508: ; %Flow1201 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2509: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v204, vcc +; %bb.2510: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i397.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2511: + v_bfe_u32 v38, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v205, v38, s6 + ; implicit-def: $vgpr205 +; %bb.2512: ; %Flow1200 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2513: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v205, vcc +; %bb.2514: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i400.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2515: + v_bfe_u32 v39, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v203, v39, s6 + ; implicit-def: $vgpr203 +; %bb.2516: ; %Flow1199 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2517: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v203, vcc +; %bb.2518: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i403.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2519: + v_bfe_u32 v40, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v202, v40, s6 + ; implicit-def: $vgpr202 +; %bb.2520: ; %Flow1198 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2521: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v202, vcc +; %bb.2522: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i406.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2523: + v_bfe_u32 v41, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v201, v41, s6 + ; implicit-def: $vgpr201 +; %bb.2524: ; %Flow1197 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2525: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v201, vcc +; %bb.2526: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i409.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2527: + v_bfe_u32 v42, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v200, v42, s6 + ; implicit-def: $vgpr200 +; %bb.2528: ; %Flow1196 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2529: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v200, vcc +; %bb.2530: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i412.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2531: + v_bfe_u32 v43, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v199, v43, s6 + ; implicit-def: $vgpr199 +; %bb.2532: ; %Flow1195 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2533: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v199, vcc +; %bb.2534: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i415.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2535: + v_bfe_u32 v44, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v198, v44, s6 + ; implicit-def: $vgpr198 +; %bb.2536: ; %Flow1194 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2537: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v198, vcc +; %bb.2538: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i418.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2539: + v_bfe_u32 v45, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v197, v45, s6 + ; implicit-def: $vgpr197 +; %bb.2540: ; %Flow1193 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2541: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v197, vcc +; %bb.2542: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i421.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2543: + v_bfe_u32 v46, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v196, v46, s6 + ; implicit-def: $vgpr196 +; %bb.2544: ; %Flow1192 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2545: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v196, vcc +; %bb.2546: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i424.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2547: + v_bfe_u32 v47, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v195, v47, s6 + ; implicit-def: $vgpr195 +; %bb.2548: ; %Flow1191 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2549: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v195, vcc +; %bb.2550: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i427.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2551: + v_bfe_u32 v48, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v194, v48, s6 + ; implicit-def: $vgpr194 +; %bb.2552: ; %Flow1190 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2553: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v194, vcc +; %bb.2554: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i430.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2555: + v_bfe_u32 v49, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v193, v49, s6 + ; implicit-def: $vgpr193 +; %bb.2556: ; %Flow1189 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2557: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v193, vcc +; %bb.2558: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i433.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2559: + v_bfe_u32 v50, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v192, v50, s6 + ; implicit-def: $vgpr192 +; %bb.2560: ; %Flow1188 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2561: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v192, vcc +; %bb.2562: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i436.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2563: + v_bfe_u32 v51, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v191, v51, s6 + ; implicit-def: $vgpr191 +; %bb.2564: ; %Flow1187 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2565: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v191, vcc +; %bb.2566: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i439.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2567: + v_bfe_u32 v52, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v190, v52, s6 + ; implicit-def: $vgpr190 +; %bb.2568: ; %Flow1186 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2569: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v190, vcc +; %bb.2570: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i442.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2571: + v_bfe_u32 v53, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v189, v53, s6 + ; implicit-def: $vgpr189 +; %bb.2572: ; %Flow1185 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2573: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v189, vcc +; %bb.2574: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_574 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v22 + ds_write_b16_d16_hi v19, v23 offset:128 + ds_write_b16_d16_hi v19, v24 offset:256 + ds_write_b16_d16_hi v19, v25 offset:384 + ds_write_b16_d16_hi v19, v26 offset:1024 + ds_write_b16_d16_hi v19, v27 offset:1152 + ds_write_b16_d16_hi v19, v28 offset:1280 + ds_write_b16_d16_hi v19, v29 offset:1408 + ds_write_b16_d16_hi v19, v30 offset:2048 + ds_write_b16_d16_hi v19, v31 offset:2176 + ds_write_b16_d16_hi v19, v32 offset:2304 + ds_write_b16_d16_hi v19, v33 offset:2432 + ds_write_b16_d16_hi v19, v34 offset:3072 + ds_write_b16_d16_hi v19, v35 offset:3200 + ds_write_b16_d16_hi v19, v36 offset:3328 + ds_write_b16_d16_hi v19, v37 offset:3456 + ds_write_b16_d16_hi v19, v38 offset:8192 + ds_write_b16_d16_hi v19, v39 offset:8320 + ds_write_b16_d16_hi v19, v40 offset:8448 + ds_write_b16_d16_hi v19, v41 offset:8576 + ds_write_b16_d16_hi v19, v42 offset:9216 + ds_write_b16_d16_hi v19, v43 offset:9344 + ds_write_b16_d16_hi v19, v44 offset:9472 + ds_write_b16_d16_hi v19, v45 offset:9600 + ds_write_b16_d16_hi v19, v46 offset:10240 + ds_write_b16_d16_hi v19, v47 offset:10368 + ds_write_b16_d16_hi v19, v48 offset:10496 + ds_write_b16_d16_hi v19, v49 offset:10624 + ds_write_b16_d16_hi v19, v50 offset:11264 + ds_write_b16_d16_hi v19, v51 offset:11392 + ds_write_b16_d16_hi v19, v52 offset:11520 + ds_write_b16_d16_hi v19, v53 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshl_or_b32 v23, v22, 7, v21 + ds_read_b128 v[26:29], v23 + ds_read_b128 v[30:33], v23 offset:128 + ds_read_b128 v[34:37], v23 offset:256 + ds_read_b128 v[38:41], v23 offset:384 + v_add_u32_e32 v23, s18, v22 + v_or_b32_e32 v22, 0x80, v18 + v_mad_u64_u32 v[24:25], s[4:5], v23, s16, v[22:23] + v_lshlrev_b32_e32 v23, 1, v24 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[26:27], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v24 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[30:31], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[32:33], v24, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[34:35], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[36:37], v24, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[38:39], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[40:41], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2575: + v_bfe_u32 v23, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v188, v23, s6 + ; implicit-def: $vgpr188 +; %bb.2576: ; %Flow1184 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2577: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v188, vcc +; %bb.2578: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i639.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2579: + v_bfe_u32 v24, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v187, v24, s6 + ; implicit-def: $vgpr187 +; %bb.2580: ; %Flow1183 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2581: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v187, vcc +; %bb.2582: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i642.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2583: + v_bfe_u32 v25, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v186, v25, s6 + ; implicit-def: $vgpr186 +; %bb.2584: ; %Flow1182 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2585: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v186, vcc +; %bb.2586: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i645.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2587: + v_bfe_u32 v26, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v185, v26, s6 + ; implicit-def: $vgpr185 +; %bb.2588: ; %Flow1181 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2589: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v185, vcc +; %bb.2590: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i648.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2591: + v_bfe_u32 v27, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v184, v27, s6 + ; implicit-def: $vgpr184 +; %bb.2592: ; %Flow1180 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2593: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v184, vcc +; %bb.2594: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i651.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2595: + v_bfe_u32 v28, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v183, v28, s6 + ; implicit-def: $vgpr183 +; %bb.2596: ; %Flow1179 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2597: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v183, vcc +; %bb.2598: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i654.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2599: + v_bfe_u32 v29, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v182, v29, s6 + ; implicit-def: $vgpr182 +; %bb.2600: ; %Flow1178 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2601: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v182, vcc +; %bb.2602: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i657.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2603: + v_bfe_u32 v30, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v181, v30, s6 + ; implicit-def: $vgpr181 +; %bb.2604: ; %Flow1177 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2605: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v181, vcc +; %bb.2606: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i660.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2607: + v_bfe_u32 v31, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v180, v31, s6 + ; implicit-def: $vgpr180 +; %bb.2608: ; %Flow1176 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2609: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v180, vcc +; %bb.2610: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i663.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2611: + v_bfe_u32 v32, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v179, v32, s6 + ; implicit-def: $vgpr179 +; %bb.2612: ; %Flow1175 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2613: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v179, vcc +; %bb.2614: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i666.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2615: + v_bfe_u32 v33, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v178, v33, s6 + ; implicit-def: $vgpr178 +; %bb.2616: ; %Flow1174 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2617: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v178, vcc +; %bb.2618: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i669.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2619: + v_bfe_u32 v34, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v177, v34, s6 + ; implicit-def: $vgpr177 +; %bb.2620: ; %Flow1173 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2621: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v177, vcc +; %bb.2622: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i672.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2623: + v_bfe_u32 v35, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v176, v35, s6 + ; implicit-def: $vgpr176 +; %bb.2624: ; %Flow1172 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2625: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v176, vcc +; %bb.2626: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i675.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2627: + v_bfe_u32 v36, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v175, v36, s6 + ; implicit-def: $vgpr175 +; %bb.2628: ; %Flow1171 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2629: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v175, vcc +; %bb.2630: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i678.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2631: + v_bfe_u32 v37, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v174, v37, s6 + ; implicit-def: $vgpr174 +; %bb.2632: ; %Flow1170 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2633: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v174, vcc +; %bb.2634: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i681.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2635: + v_bfe_u32 v38, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v172, v38, s6 + ; implicit-def: $vgpr172 +; %bb.2636: ; %Flow1169 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2637: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v172, vcc +; %bb.2638: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i684.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2639: + v_bfe_u32 v39, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v173, v39, s6 + ; implicit-def: $vgpr173 +; %bb.2640: ; %Flow1168 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2641: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v173, vcc +; %bb.2642: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i687.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2643: + v_bfe_u32 v40, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v171, v40, s6 + ; implicit-def: $vgpr171 +; %bb.2644: ; %Flow1167 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2645: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v171, vcc +; %bb.2646: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i690.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2647: + v_bfe_u32 v41, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v170, v41, s6 + ; implicit-def: $vgpr170 +; %bb.2648: ; %Flow1166 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2649: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v170, vcc +; %bb.2650: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i693.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2651: + v_bfe_u32 v42, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v169, v42, s6 + ; implicit-def: $vgpr169 +; %bb.2652: ; %Flow1165 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2653: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v169, vcc +; %bb.2654: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i696.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2655: + v_bfe_u32 v43, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v168, v43, s6 + ; implicit-def: $vgpr168 +; %bb.2656: ; %Flow1164 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2657: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v168, vcc +; %bb.2658: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i699.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2659: + v_bfe_u32 v44, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v167, v44, s6 + ; implicit-def: $vgpr167 +; %bb.2660: ; %Flow1163 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2661: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v167, vcc +; %bb.2662: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i702.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2663: + v_bfe_u32 v45, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v166, v45, s6 + ; implicit-def: $vgpr166 +; %bb.2664: ; %Flow1162 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2665: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v166, vcc +; %bb.2666: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i705.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2667: + v_bfe_u32 v46, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v165, v46, s6 + ; implicit-def: $vgpr165 +; %bb.2668: ; %Flow1161 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2669: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v165, vcc +; %bb.2670: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i708.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2671: + v_bfe_u32 v47, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v164, v47, s6 + ; implicit-def: $vgpr164 +; %bb.2672: ; %Flow1160 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2673: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v164, vcc +; %bb.2674: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i711.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2675: + v_bfe_u32 v48, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v163, v48, s6 + ; implicit-def: $vgpr163 +; %bb.2676: ; %Flow1159 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2677: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v163, vcc +; %bb.2678: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i714.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2679: + v_bfe_u32 v49, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v162, v49, s6 + ; implicit-def: $vgpr162 +; %bb.2680: ; %Flow1158 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2681: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v162, vcc +; %bb.2682: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i717.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2683: + v_bfe_u32 v50, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v161, v50, s6 + ; implicit-def: $vgpr161 +; %bb.2684: ; %Flow1157 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2685: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v161, vcc +; %bb.2686: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i720.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2687: + v_bfe_u32 v51, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v160, v51, s6 + ; implicit-def: $vgpr160 +; %bb.2688: ; %Flow1156 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2689: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v160, vcc +; %bb.2690: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i723.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2691: + v_bfe_u32 v52, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v159, v52, s6 + ; implicit-def: $vgpr159 +; %bb.2692: ; %Flow1155 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2693: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v159, vcc +; %bb.2694: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i726.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2695: + v_bfe_u32 v53, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v158, v53, s6 + ; implicit-def: $vgpr158 +; %bb.2696: ; %Flow1154 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2697: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v158, vcc +; %bb.2698: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i729.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v54, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s4, v54 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2699: + v_bfe_u32 v54, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v157, v54, s6 + ; implicit-def: $vgpr157 +; %bb.2700: ; %Flow1153 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2701: + v_mov_b32_e32 v54, 0 + v_or_b32_e32 v55, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v54 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v55, v157, vcc +; %bb.2702: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_861 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v24 offset:128 + ds_write_b16_d16_hi v19, v25 offset:256 + ds_write_b16_d16_hi v19, v26 offset:384 + ds_write_b16_d16_hi v19, v27 offset:1024 + ds_write_b16_d16_hi v19, v28 offset:1152 + ds_write_b16_d16_hi v19, v29 offset:1280 + ds_write_b16_d16_hi v19, v30 offset:1408 + ds_write_b16_d16_hi v19, v31 offset:2048 + ds_write_b16_d16_hi v19, v32 offset:2176 + ds_write_b16_d16_hi v19, v33 offset:2304 + ds_write_b16_d16_hi v19, v34 offset:2432 + ds_write_b16_d16_hi v19, v35 offset:3072 + ds_write_b16_d16_hi v19, v36 offset:3200 + ds_write_b16_d16_hi v19, v37 offset:3328 + ds_write_b16_d16_hi v19, v38 offset:3456 + ds_write_b16_d16_hi v19, v39 offset:8192 + ds_write_b16_d16_hi v19, v40 offset:8320 + ds_write_b16_d16_hi v19, v41 offset:8448 + ds_write_b16_d16_hi v19, v42 offset:8576 + ds_write_b16_d16_hi v19, v43 offset:9216 + ds_write_b16_d16_hi v19, v44 offset:9344 + ds_write_b16_d16_hi v19, v45 offset:9472 + ds_write_b16_d16_hi v19, v46 offset:9600 + ds_write_b16_d16_hi v19, v47 offset:10240 + ds_write_b16_d16_hi v19, v48 offset:10368 + ds_write_b16_d16_hi v19, v49 offset:10496 + ds_write_b16_d16_hi v19, v50 offset:10624 + ds_write_b16_d16_hi v19, v51 offset:11264 + ds_write_b16_d16_hi v19, v52 offset:11392 + ds_write_b16_d16_hi v19, v53 offset:11520 + ds_write_b16_d16_hi v19, v54 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v23, s4, v1 + v_lshl_or_b32 v24, v23, 7, v21 + ds_read_b128 v[28:31], v24 + ds_read_b128 v[32:35], v24 offset:128 + ds_read_b128 v[36:39], v24 offset:256 + ds_read_b128 v[40:43], v24 offset:384 + v_add_u32_e32 v23, s18, v23 + v_or_b32_e32 v24, 0xc0, v18 + v_mad_u64_u32 v[26:27], s[4:5], v23, s16, v[24:25] + v_lshlrev_b32_e32 v23, 1, v26 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v26 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[32:33], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v25, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[36:37], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v25, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[40:41], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[42:43], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2703: + v_bfe_u32 v23, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v156, v23, s6 + ; implicit-def: $vgpr156 +; %bb.2704: ; %Flow1152 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2705: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v25, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v25, v156, vcc +; %bb.2706: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i926.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2707: + v_bfe_u32 v25, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v155, v25, s6 + ; implicit-def: $vgpr155 +; %bb.2708: ; %Flow1151 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2709: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v155, vcc +; %bb.2710: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i929.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2711: + v_bfe_u32 v26, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v154, v26, s6 + ; implicit-def: $vgpr154 +; %bb.2712: ; %Flow1150 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2713: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v154, vcc +; %bb.2714: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i932.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2715: + v_bfe_u32 v27, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v153, v27, s6 + ; implicit-def: $vgpr153 +; %bb.2716: ; %Flow1149 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2717: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v153, vcc +; %bb.2718: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i935.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2719: + v_bfe_u32 v28, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v152, v28, s6 + ; implicit-def: $vgpr152 +; %bb.2720: ; %Flow1148 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2721: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v152, vcc +; %bb.2722: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i938.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2723: + v_bfe_u32 v29, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v151, v29, s6 + ; implicit-def: $vgpr151 +; %bb.2724: ; %Flow1147 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2725: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v151, vcc +; %bb.2726: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i941.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2727: + v_bfe_u32 v30, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v150, v30, s6 + ; implicit-def: $vgpr150 +; %bb.2728: ; %Flow1146 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2729: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v150, vcc +; %bb.2730: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i944.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2731: + v_bfe_u32 v31, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v149, v31, s6 + ; implicit-def: $vgpr149 +; %bb.2732: ; %Flow1145 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2733: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v149, vcc +; %bb.2734: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i947.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2735: + v_bfe_u32 v32, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v148, v32, s6 + ; implicit-def: $vgpr148 +; %bb.2736: ; %Flow1144 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2737: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v148, vcc +; %bb.2738: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i950.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2739: + v_bfe_u32 v33, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v147, v33, s6 + ; implicit-def: $vgpr147 +; %bb.2740: ; %Flow1143 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2741: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v147, vcc +; %bb.2742: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i953.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2743: + v_bfe_u32 v34, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v146, v34, s6 + ; implicit-def: $vgpr146 +; %bb.2744: ; %Flow1142 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2745: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v146, vcc +; %bb.2746: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i956.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2747: + v_bfe_u32 v35, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v145, v35, s6 + ; implicit-def: $vgpr145 +; %bb.2748: ; %Flow1141 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2749: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v145, vcc +; %bb.2750: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i959.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2751: + v_bfe_u32 v36, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v144, v36, s6 + ; implicit-def: $vgpr144 +; %bb.2752: ; %Flow1140 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2753: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v144, vcc +; %bb.2754: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i962.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2755: + v_bfe_u32 v37, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v143, v37, s6 + ; implicit-def: $vgpr143 +; %bb.2756: ; %Flow1139 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2757: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v143, vcc +; %bb.2758: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i965.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2759: + v_bfe_u32 v38, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v142, v38, s6 + ; implicit-def: $vgpr142 +; %bb.2760: ; %Flow1138 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2761: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v142, vcc +; %bb.2762: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i968.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2763: + v_bfe_u32 v39, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v141, v39, s6 + ; implicit-def: $vgpr141 +; %bb.2764: ; %Flow1137 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2765: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v141, vcc +; %bb.2766: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i971.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2767: + v_bfe_u32 v40, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v2, v40, s6 +; %bb.2768: ; %Flow1136 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2769: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v2, vcc +; %bb.2770: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i974.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2771: + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v3, v2, s6 +; %bb.2772: ; %Flow1135 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2773: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v41, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v3, vcc +; %bb.2774: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i977.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2775: + v_bfe_u32 v2, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v4, v2, s6 +; %bb.2776: ; %Flow1134 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2777: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v3, v4, vcc +; %bb.2778: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i980.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2779: + v_bfe_u32 v2, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v5, v2, s6 +; %bb.2780: ; %Flow1133 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2781: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v3, v5, vcc +; %bb.2782: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i983.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2783: + v_bfe_u32 v2, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v6, v2, s6 +; %bb.2784: ; %Flow1132 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2785: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v3, v6, vcc +; %bb.2786: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i986.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2787: + v_bfe_u32 v2, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v7, v2, s6 +; %bb.2788: ; %Flow1131 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2789: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v3, v7, vcc +; %bb.2790: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i989.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2791: + v_bfe_u32 v2, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v8, v2, s6 +; %bb.2792: ; %Flow1130 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2793: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v3, v8, vcc +; %bb.2794: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i992.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2795: + v_bfe_u32 v2, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v9, v2, s6 +; %bb.2796: ; %Flow1129 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2797: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v3, v9, vcc +; %bb.2798: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i995.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2799: + v_bfe_u32 v2, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v10, v2, s6 +; %bb.2800: ; %Flow1128 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2801: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v3, v10, vcc +; %bb.2802: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i998.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2803: + v_bfe_u32 v2, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v11, v2, s6 +; %bb.2804: ; %Flow1127 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2805: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v3, v11, vcc +; %bb.2806: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1001.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2807: + v_bfe_u32 v2, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v12, v2, s6 +; %bb.2808: ; %Flow1126 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2809: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v3, v12, vcc +; %bb.2810: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1004.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2811: + v_bfe_u32 v2, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v13, v2, s6 +; %bb.2812: ; %Flow1125 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2813: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v3, v13, vcc +; %bb.2814: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1007.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2815: + v_bfe_u32 v2, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v14, v2, s6 +; %bb.2816: ; %Flow1124 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2817: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v3, v14, vcc +; %bb.2818: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1010.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2819: + v_bfe_u32 v2, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v15, v2, s6 +; %bb.2820: ; %Flow1123 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2821: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v3, v15, vcc +; %bb.2822: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1013.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2823: + v_bfe_u32 v2, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v16, v2, s6 +; %bb.2824: ; %Flow1122 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2825: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v3, v16, vcc +; %bb.2826: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1016.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr55 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2827: + v_bfe_u32 v2, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v55, v17, v2, s6 + ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 +; %bb.2828: ; %Flow1121 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2829: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v55, v3, v17, vcc +; %bb.2830: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1148 + s_or_b64 exec, exec, s[4:5] + s_bitset1_b32 s18, 7 + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v25 offset:128 + ds_write_b16_d16_hi v19, v26 offset:256 + ds_write_b16_d16_hi v19, v27 offset:384 + ds_write_b16_d16_hi v19, v28 offset:1024 + ds_write_b16_d16_hi v19, v29 offset:1152 + ds_write_b16_d16_hi v19, v30 offset:1280 + ds_write_b16_d16_hi v19, v31 offset:1408 + ds_write_b16_d16_hi v19, v32 offset:2048 + ds_write_b16_d16_hi v19, v33 offset:2176 + ds_write_b16_d16_hi v19, v34 offset:2304 + ds_write_b16_d16_hi v19, v35 offset:2432 + ds_write_b16_d16_hi v19, v36 offset:3072 + ds_write_b16_d16_hi v19, v37 offset:3200 + ds_write_b16_d16_hi v19, v38 offset:3328 + ds_write_b16_d16_hi v19, v39 offset:3456 + ds_write_b16_d16_hi v19, v40 offset:8192 + ds_write_b16_d16_hi v19, v41 offset:8320 + ds_write_b16_d16_hi v19, v42 offset:8448 + ds_write_b16_d16_hi v19, v43 offset:8576 + ds_write_b16_d16_hi v19, v44 offset:9216 + ds_write_b16_d16_hi v19, v45 offset:9344 + ds_write_b16_d16_hi v19, v46 offset:9472 + ds_write_b16_d16_hi v19, v47 offset:9600 + ds_write_b16_d16_hi v19, v48 offset:10240 + ds_write_b16_d16_hi v19, v49 offset:10368 + ds_write_b16_d16_hi v19, v50 offset:10496 + ds_write_b16_d16_hi v19, v51 offset:10624 + ds_write_b16_d16_hi v19, v52 offset:11264 + ds_write_b16_d16_hi v19, v53 offset:11392 + ds_write_b16_d16_hi v19, v54 offset:11520 + ds_write_b16_d16_hi v19, v55 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[26:29], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[24:25] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[26:27], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2831: + v_bfe_u32 v2, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v140, v2, s6 + ; implicit-def: $vgpr140 +; %bb.2832: ; %Flow1120 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2833: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v140, vcc +; %bb.2834: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1213.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2835: + v_bfe_u32 v3, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v139, v3, s6 + ; implicit-def: $vgpr139 +; %bb.2836: ; %Flow1119 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2837: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v139, vcc +; %bb.2838: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1216.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2839: + v_bfe_u32 v4, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v138, v4, s6 + ; implicit-def: $vgpr138 +; %bb.2840: ; %Flow1118 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2841: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v138, vcc +; %bb.2842: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1219.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2843: + v_bfe_u32 v5, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v137, v5, s6 + ; implicit-def: $vgpr137 +; %bb.2844: ; %Flow1117 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2845: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v137, vcc +; %bb.2846: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1222.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2847: + v_bfe_u32 v6, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v136, v6, s6 + ; implicit-def: $vgpr136 +; %bb.2848: ; %Flow1116 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2849: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v136, vcc +; %bb.2850: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1225.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2851: + v_bfe_u32 v7, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v135, v7, s6 + ; implicit-def: $vgpr135 +; %bb.2852: ; %Flow1115 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2853: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v135, vcc +; %bb.2854: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1228.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2855: + v_bfe_u32 v8, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v134, v8, s6 + ; implicit-def: $vgpr134 +; %bb.2856: ; %Flow1114 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2857: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v134, vcc +; %bb.2858: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1231.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2859: + v_bfe_u32 v9, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v133, v9, s6 + ; implicit-def: $vgpr133 +; %bb.2860: ; %Flow1113 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2861: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v133, vcc +; %bb.2862: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1234.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2863: + v_bfe_u32 v10, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v132, v10, s6 + ; implicit-def: $vgpr132 +; %bb.2864: ; %Flow1112 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2865: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v132, vcc +; %bb.2866: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1237.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2867: + v_bfe_u32 v11, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v131, v11, s6 + ; implicit-def: $vgpr131 +; %bb.2868: ; %Flow1111 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2869: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v131, vcc +; %bb.2870: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1240.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2871: + v_bfe_u32 v12, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v130, v12, s6 + ; implicit-def: $vgpr130 +; %bb.2872: ; %Flow1110 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2873: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v130, vcc +; %bb.2874: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1243.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2875: + v_bfe_u32 v13, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v129, v13, s6 + ; implicit-def: $vgpr129 +; %bb.2876: ; %Flow1109 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2877: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v129, vcc +; %bb.2878: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1246.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2879: + v_bfe_u32 v14, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v128, v14, s6 + ; implicit-def: $vgpr128 +; %bb.2880: ; %Flow1108 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2881: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v128, vcc +; %bb.2882: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1249.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2883: + v_bfe_u32 v15, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v127, v15, s6 + ; implicit-def: $vgpr127 +; %bb.2884: ; %Flow1107 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2885: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v127, vcc +; %bb.2886: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1252.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2887: + v_bfe_u32 v16, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v126, v16, s6 + ; implicit-def: $vgpr126 +; %bb.2888: ; %Flow1106 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2889: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v126, vcc +; %bb.2890: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1255.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2891: + v_bfe_u32 v17, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v124, v17, s6 + ; implicit-def: $vgpr124 +; %bb.2892: ; %Flow1105 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2893: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v23, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v23, v124, vcc +; %bb.2894: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1258.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2895: + v_bfe_u32 v23, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v125, v23, s6 + ; implicit-def: $vgpr125 +; %bb.2896: ; %Flow1104 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2897: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v125, vcc +; %bb.2898: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1261.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2899: + v_bfe_u32 v24, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v123, v24, s6 + ; implicit-def: $vgpr123 +; %bb.2900: ; %Flow1103 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2901: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v123, vcc +; %bb.2902: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1264.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2903: + v_bfe_u32 v25, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v122, v25, s6 + ; implicit-def: $vgpr122 +; %bb.2904: ; %Flow1102 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2905: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v122, vcc +; %bb.2906: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1267.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2907: + v_bfe_u32 v26, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v121, v26, s6 + ; implicit-def: $vgpr121 +; %bb.2908: ; %Flow1101 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2909: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v121, vcc +; %bb.2910: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1270.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2911: + v_bfe_u32 v27, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v120, v27, s6 + ; implicit-def: $vgpr120 +; %bb.2912: ; %Flow1100 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2913: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v120, vcc +; %bb.2914: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1273.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2915: + v_bfe_u32 v28, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v119, v28, s6 + ; implicit-def: $vgpr119 +; %bb.2916: ; %Flow1099 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2917: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v119, vcc +; %bb.2918: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1276.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2919: + v_bfe_u32 v29, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v118, v29, s6 + ; implicit-def: $vgpr118 +; %bb.2920: ; %Flow1098 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2921: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v118, vcc +; %bb.2922: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1279.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2923: + v_bfe_u32 v30, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v117, v30, s6 + ; implicit-def: $vgpr117 +; %bb.2924: ; %Flow1097 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2925: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v117, vcc +; %bb.2926: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1282.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2927: + v_bfe_u32 v31, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v116, v31, s6 + ; implicit-def: $vgpr116 +; %bb.2928: ; %Flow1096 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2929: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v116, vcc +; %bb.2930: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1285.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2931: + v_bfe_u32 v32, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v115, v32, s6 + ; implicit-def: $vgpr115 +; %bb.2932: ; %Flow1095 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2933: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v115, vcc +; %bb.2934: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1288.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2935: + v_bfe_u32 v33, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v114, v33, s6 + ; implicit-def: $vgpr114 +; %bb.2936: ; %Flow1094 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2937: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v114, vcc +; %bb.2938: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1291.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2939: + v_bfe_u32 v34, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v113, v34, s6 + ; implicit-def: $vgpr113 +; %bb.2940: ; %Flow1093 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2941: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v113, vcc +; %bb.2942: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1294.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2943: + v_bfe_u32 v35, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v112, v35, s6 + ; implicit-def: $vgpr112 +; %bb.2944: ; %Flow1092 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2945: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v112, vcc +; %bb.2946: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1297.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2947: + v_bfe_u32 v36, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v111, v36, s6 + ; implicit-def: $vgpr111 +; %bb.2948: ; %Flow1091 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2949: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v111, vcc +; %bb.2950: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1300.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2951: + v_bfe_u32 v37, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v110, v37, s6 + ; implicit-def: $vgpr110 +; %bb.2952: ; %Flow1090 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2953: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v110, vcc +; %bb.2954: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1303.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2955: + v_bfe_u32 v38, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v109, v38, s6 + ; implicit-def: $vgpr109 +; %bb.2956: ; %Flow1089 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2957: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v109, vcc +; %bb.2958: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1435 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v23 offset:8192 + ds_write_b16_d16_hi v19, v24 offset:8320 + ds_write_b16_d16_hi v19, v25 offset:8448 + ds_write_b16_d16_hi v19, v26 offset:8576 + ds_write_b16_d16_hi v19, v27 offset:9216 + ds_write_b16_d16_hi v19, v28 offset:9344 + ds_write_b16_d16_hi v19, v29 offset:9472 + ds_write_b16_d16_hi v19, v30 offset:9600 + ds_write_b16_d16_hi v19, v31 offset:10240 + ds_write_b16_d16_hi v19, v32 offset:10368 + ds_write_b16_d16_hi v19, v33 offset:10496 + ds_write_b16_d16_hi v19, v34 offset:10624 + ds_write_b16_d16_hi v19, v35 offset:11264 + ds_write_b16_d16_hi v19, v36 offset:11392 + ds_write_b16_d16_hi v19, v37 offset:11520 + ds_write_b16_d16_hi v19, v38 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[24:27], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[22:23] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[24:25], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2959: + v_bfe_u32 v2, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v108, v2, s6 + ; implicit-def: $vgpr108 +; %bb.2960: ; %Flow1088 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2961: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v108, vcc +; %bb.2962: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1500.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2963: + v_bfe_u32 v3, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v107, v3, s6 + ; implicit-def: $vgpr107 +; %bb.2964: ; %Flow1087 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2965: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v107, vcc +; %bb.2966: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1503.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2967: + v_bfe_u32 v4, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v106, v4, s6 + ; implicit-def: $vgpr106 +; %bb.2968: ; %Flow1086 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2969: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v106, vcc +; %bb.2970: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1506.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2971: + v_bfe_u32 v5, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v105, v5, s6 + ; implicit-def: $vgpr105 +; %bb.2972: ; %Flow1085 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2973: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v105, vcc +; %bb.2974: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1509.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2975: + v_bfe_u32 v6, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v104, v6, s6 + ; implicit-def: $vgpr104 +; %bb.2976: ; %Flow1084 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2977: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v104, vcc +; %bb.2978: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1512.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2979: + v_bfe_u32 v7, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v103, v7, s6 + ; implicit-def: $vgpr103 +; %bb.2980: ; %Flow1083 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2981: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v103, vcc +; %bb.2982: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1515.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2983: + v_bfe_u32 v8, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v102, v8, s6 + ; implicit-def: $vgpr102 +; %bb.2984: ; %Flow1082 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2985: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v102, vcc +; %bb.2986: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1518.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2987: + v_bfe_u32 v9, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v101, v9, s6 + ; implicit-def: $vgpr101 +; %bb.2988: ; %Flow1081 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2989: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v101, vcc +; %bb.2990: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1521.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2991: + v_bfe_u32 v10, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v100, v10, s6 + ; implicit-def: $vgpr100 +; %bb.2992: ; %Flow1080 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2993: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v100, vcc +; %bb.2994: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1524.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2995: + v_bfe_u32 v11, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v99, v11, s6 + ; implicit-def: $vgpr99 +; %bb.2996: ; %Flow1079 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2997: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v99, vcc +; %bb.2998: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1527.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2999: + v_bfe_u32 v12, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v98, v12, s6 + ; implicit-def: $vgpr98 +; %bb.3000: ; %Flow1078 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3001: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v98, vcc +; %bb.3002: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1530.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3003: + v_bfe_u32 v13, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v97, v13, s6 + ; implicit-def: $vgpr97 +; %bb.3004: ; %Flow1077 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3005: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v97, vcc +; %bb.3006: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1533.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3007: + v_bfe_u32 v14, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v96, v14, s6 + ; implicit-def: $vgpr96 +; %bb.3008: ; %Flow1076 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3009: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v96, vcc +; %bb.3010: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1536.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3011: + v_bfe_u32 v15, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v95, v15, s6 + ; implicit-def: $vgpr95 +; %bb.3012: ; %Flow1075 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3013: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v95, vcc +; %bb.3014: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1539.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3015: + v_bfe_u32 v16, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v94, v16, s6 + ; implicit-def: $vgpr94 +; %bb.3016: ; %Flow1074 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3017: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v94, vcc +; %bb.3018: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1542.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3019: + v_bfe_u32 v17, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v92, v17, s6 + ; implicit-def: $vgpr92 +; %bb.3020: ; %Flow1073 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3021: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v22, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v22, v92, vcc +; %bb.3022: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1545.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3023: + v_bfe_u32 v22, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v93, v22, s6 + ; implicit-def: $vgpr93 +; %bb.3024: ; %Flow1072 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3025: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v93, vcc +; %bb.3026: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1548.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3027: + v_bfe_u32 v23, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v91, v23, s6 + ; implicit-def: $vgpr91 +; %bb.3028: ; %Flow1071 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3029: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v91, vcc +; %bb.3030: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1551.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3031: + v_bfe_u32 v24, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v90, v24, s6 + ; implicit-def: $vgpr90 +; %bb.3032: ; %Flow1070 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3033: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v90, vcc +; %bb.3034: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1554.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3035: + v_bfe_u32 v25, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v89, v25, s6 + ; implicit-def: $vgpr89 +; %bb.3036: ; %Flow1069 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3037: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v89, vcc +; %bb.3038: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1557.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3039: + v_bfe_u32 v26, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v88, v26, s6 + ; implicit-def: $vgpr88 +; %bb.3040: ; %Flow1068 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3041: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v88, vcc +; %bb.3042: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1560.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a65 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3043: + v_accvgpr_read_b32 v28, a65 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr65 +; %bb.3044: ; %Flow1067 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3045: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a65 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3046: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1563.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a64 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3047: + v_accvgpr_read_b32 v29, a64 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr64 +; %bb.3048: ; %Flow1066 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3049: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a64 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3050: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1566.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a55 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3051: + v_accvgpr_read_b32 v30, a55 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr55 +; %bb.3052: ; %Flow1065 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3053: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a55 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3054: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1569.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a54 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3055: + v_accvgpr_read_b32 v31, a54 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr54 +; %bb.3056: ; %Flow1064 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3057: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a54 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3058: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1572.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a53 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3059: + v_accvgpr_read_b32 v32, a53 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr53 +; %bb.3060: ; %Flow1063 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3061: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a53 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3062: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1575.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a52 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3063: + v_accvgpr_read_b32 v33, a52 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr52 +; %bb.3064: ; %Flow1062 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3065: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a52 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3066: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1578.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a51 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3067: + v_accvgpr_read_b32 v34, a51 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr51 +; %bb.3068: ; %Flow1061 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3069: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a51 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3070: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1581.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a50 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3071: + v_accvgpr_read_b32 v35, a50 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr50 +; %bb.3072: ; %Flow1060 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3073: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a50 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3074: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1584.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a49 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3075: + v_accvgpr_read_b32 v36, a49 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr49 +; %bb.3076: ; %Flow1059 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3077: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a49 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3078: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1587.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3079: + v_bfe_u32 v36, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v87, v36, s6 + ; implicit-def: $vgpr87 +; %bb.3080: ; %Flow1058 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3081: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v87, vcc +; %bb.3082: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1590.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v37, a48 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3083: + v_accvgpr_read_b32 v38, a48 + v_bfe_u32 v37, v38, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v38, v37, s6 + ; implicit-def: $agpr48 +; %bb.3084: ; %Flow1057 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3085: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v39, a48 + v_or_b32_e32 v38, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v39, vcc +; %bb.3086: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1722 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v22 offset:8192 + ds_write_b16_d16_hi v19, v23 offset:8320 + ds_write_b16_d16_hi v19, v24 offset:8448 + ds_write_b16_d16_hi v19, v25 offset:8576 + ds_write_b16_d16_hi v19, v26 offset:9216 + ds_write_b16_d16_hi v19, v27 offset:9344 + ds_write_b16_d16_hi v19, v28 offset:9472 + ds_write_b16_d16_hi v19, v29 offset:9600 + ds_write_b16_d16_hi v19, v30 offset:10240 + ds_write_b16_d16_hi v19, v31 offset:10368 + ds_write_b16_d16_hi v19, v32 offset:10496 + ds_write_b16_d16_hi v19, v33 offset:10624 + ds_write_b16_d16_hi v19, v34 offset:11264 + ds_write_b16_d16_hi v19, v35 offset:11392 + ds_write_b16_d16_hi v19, v36 offset:11520 + ds_write_b16_d16_hi v19, v37 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[22:25], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[20:21] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[22:23], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[24:25], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v2, a47 + v_and_b32_e32 v2, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3087: + v_accvgpr_read_b32 v3, a47 + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v3, v2, s6 + ; implicit-def: $agpr47 +; %bb.3088: ; %Flow1056 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3089: + v_mov_b32_e32 v2, 0 + v_accvgpr_read_b32 v4, a47 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v4, vcc +; %bb.3090: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1787.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v3, a46 + v_and_b32_e32 v3, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3091: + v_accvgpr_read_b32 v4, a46 + v_bfe_u32 v3, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v4, v3, s6 + ; implicit-def: $agpr46 +; %bb.3092: ; %Flow1055 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3093: + v_mov_b32_e32 v3, 0 + v_accvgpr_read_b32 v5, a46 + v_or_b32_e32 v4, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v5, vcc +; %bb.3094: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1790.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v4, a45 + v_and_b32_e32 v4, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3095: + v_accvgpr_read_b32 v5, a45 + v_bfe_u32 v4, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v5, v4, s6 + ; implicit-def: $agpr45 +; %bb.3096: ; %Flow1054 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3097: + v_mov_b32_e32 v4, 0 + v_accvgpr_read_b32 v6, a45 + v_or_b32_e32 v5, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v6, vcc +; %bb.3098: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1793.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v5, a44 + v_and_b32_e32 v5, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3099: + v_accvgpr_read_b32 v6, a44 + v_bfe_u32 v5, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v6, v5, s6 + ; implicit-def: $agpr44 +; %bb.3100: ; %Flow1053 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3101: + v_mov_b32_e32 v5, 0 + v_accvgpr_read_b32 v7, a44 + v_or_b32_e32 v6, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v7, vcc +; %bb.3102: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1796.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v6, a43 + v_and_b32_e32 v6, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3103: + v_accvgpr_read_b32 v7, a43 + v_bfe_u32 v6, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v7, v6, s6 + ; implicit-def: $agpr43 +; %bb.3104: ; %Flow1052 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3105: + v_mov_b32_e32 v6, 0 + v_accvgpr_read_b32 v8, a43 + v_or_b32_e32 v7, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v8, vcc +; %bb.3106: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1799.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v7, a42 + v_and_b32_e32 v7, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3107: + v_accvgpr_read_b32 v8, a42 + v_bfe_u32 v7, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v8, v7, s6 + ; implicit-def: $agpr42 +; %bb.3108: ; %Flow1051 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3109: + v_mov_b32_e32 v7, 0 + v_accvgpr_read_b32 v9, a42 + v_or_b32_e32 v8, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v9, vcc +; %bb.3110: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1802.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v8, a41 + v_and_b32_e32 v8, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3111: + v_accvgpr_read_b32 v9, a41 + v_bfe_u32 v8, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v9, v8, s6 + ; implicit-def: $agpr41 +; %bb.3112: ; %Flow1050 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3113: + v_mov_b32_e32 v8, 0 + v_accvgpr_read_b32 v10, a41 + v_or_b32_e32 v9, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v10, vcc +; %bb.3114: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1805.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v9, a40 + v_and_b32_e32 v9, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3115: + v_accvgpr_read_b32 v10, a40 + v_bfe_u32 v9, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v10, v9, s6 + ; implicit-def: $agpr40 +; %bb.3116: ; %Flow1049 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3117: + v_mov_b32_e32 v9, 0 + v_accvgpr_read_b32 v11, a40 + v_or_b32_e32 v10, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v11, vcc +; %bb.3118: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1808.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v10, a39 + v_and_b32_e32 v10, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3119: + v_accvgpr_read_b32 v11, a39 + v_bfe_u32 v10, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v11, v10, s6 + ; implicit-def: $agpr39 +; %bb.3120: ; %Flow1048 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3121: + v_mov_b32_e32 v10, 0 + v_accvgpr_read_b32 v12, a39 + v_or_b32_e32 v11, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v12, vcc +; %bb.3122: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1811.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v11, a38 + v_and_b32_e32 v11, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3123: + v_accvgpr_read_b32 v12, a38 + v_bfe_u32 v11, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v12, v11, s6 + ; implicit-def: $agpr38 +; %bb.3124: ; %Flow1047 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3125: + v_mov_b32_e32 v11, 0 + v_accvgpr_read_b32 v13, a38 + v_or_b32_e32 v12, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v13, vcc +; %bb.3126: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1814.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v12, a37 + v_and_b32_e32 v12, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3127: + v_accvgpr_read_b32 v13, a37 + v_bfe_u32 v12, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v13, v12, s6 + ; implicit-def: $agpr37 +; %bb.3128: ; %Flow1046 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3129: + v_mov_b32_e32 v12, 0 + v_accvgpr_read_b32 v14, a37 + v_or_b32_e32 v13, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v14, vcc +; %bb.3130: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1817.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v13, a36 + v_and_b32_e32 v13, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3131: + v_accvgpr_read_b32 v14, a36 + v_bfe_u32 v13, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v14, v13, s6 + ; implicit-def: $agpr36 +; %bb.3132: ; %Flow1045 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3133: + v_mov_b32_e32 v13, 0 + v_accvgpr_read_b32 v15, a36 + v_or_b32_e32 v14, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v15, vcc +; %bb.3134: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1820.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v14, a35 + v_and_b32_e32 v14, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3135: + v_accvgpr_read_b32 v15, a35 + v_bfe_u32 v14, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v15, v14, s6 + ; implicit-def: $agpr35 +; %bb.3136: ; %Flow1044 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3137: + v_mov_b32_e32 v14, 0 + v_accvgpr_read_b32 v16, a35 + v_or_b32_e32 v15, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v16, vcc +; %bb.3138: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1823.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v15, a34 + v_and_b32_e32 v15, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3139: + v_accvgpr_read_b32 v16, a34 + v_bfe_u32 v15, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v16, v15, s6 + ; implicit-def: $agpr34 +; %bb.3140: ; %Flow1043 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3141: + v_mov_b32_e32 v15, 0 + v_accvgpr_read_b32 v17, a34 + v_or_b32_e32 v16, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v17, vcc +; %bb.3142: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1826.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v16, a33 + v_and_b32_e32 v16, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3143: + v_accvgpr_read_b32 v17, a33 + v_bfe_u32 v16, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v17, v16, s6 + ; implicit-def: $agpr33 +; %bb.3144: ; %Flow1042 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3145: + v_mov_b32_e32 v16, 0 + v_accvgpr_read_b32 v20, a33 + v_or_b32_e32 v17, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v20, vcc +; %bb.3146: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1829.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v17, a15 + v_and_b32_e32 v17, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3147: + v_accvgpr_read_b32 v20, a15 + v_bfe_u32 v17, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v20, v17, s6 + ; implicit-def: $agpr15 +; %bb.3148: ; %Flow1041 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3149: + v_mov_b32_e32 v17, 0 + v_accvgpr_read_b32 v22, a15 + v_or_b32_e32 v20, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v20, v22, vcc +; %bb.3150: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1832.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v20, a32 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s4, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3151: + v_accvgpr_read_b32 v22, a32 + v_bfe_u32 v20, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v22, v20, s6 + ; implicit-def: $agpr32 +; %bb.3152: ; %Flow1040 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3153: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v23, a32 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v22, v23, vcc +; %bb.3154: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1835.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v22, a14 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3155: + v_accvgpr_read_b32 v23, a14 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 + ; implicit-def: $agpr14 +; %bb.3156: ; %Flow1039 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3157: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a14 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.3158: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1838.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v23, a13 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3159: + v_accvgpr_read_b32 v24, a13 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 + ; implicit-def: $agpr13 +; %bb.3160: ; %Flow1038 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3161: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a13 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.3162: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1841.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v24, a12 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3163: + v_accvgpr_read_b32 v25, a12 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 + ; implicit-def: $agpr12 +; %bb.3164: ; %Flow1037 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3165: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a12 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.3166: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1844.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v25, a11 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3167: + v_accvgpr_read_b32 v26, a11 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 + ; implicit-def: $agpr11 +; %bb.3168: ; %Flow1036 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3169: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a11 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.3170: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1847.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v26, a10 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3171: + v_accvgpr_read_b32 v27, a10 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 + ; implicit-def: $agpr10 +; %bb.3172: ; %Flow1035 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3173: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a10 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.3174: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1850.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a9 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3175: + v_accvgpr_read_b32 v28, a9 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr9 +; %bb.3176: ; %Flow1034 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3177: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a9 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3178: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1853.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a8 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3179: + v_accvgpr_read_b32 v29, a8 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr8 +; %bb.3180: ; %Flow1033 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3181: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a8 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3182: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1856.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a7 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3183: + v_accvgpr_read_b32 v30, a7 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr7 +; %bb.3184: ; %Flow1032 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3185: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a7 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3186: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1859.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a6 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3187: + v_accvgpr_read_b32 v31, a6 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr6 +; %bb.3188: ; %Flow1031 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3189: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a6 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3190: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1862.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a5 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3191: + v_accvgpr_read_b32 v32, a5 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr5 +; %bb.3192: ; %Flow1030 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3193: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a5 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1865.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a4 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3195: + v_accvgpr_read_b32 v33, a4 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr4 +; %bb.3196: ; %Flow1029 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3197: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a4 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1868.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a3 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3199: + v_accvgpr_read_b32 v34, a3 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr3 +; %bb.3200: ; %Flow1028 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3201: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a3 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1871.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a2 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3203: + v_accvgpr_read_b32 v35, a2 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr2 +; %bb.3204: ; %Flow1027 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3205: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a2 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1874.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a1 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3207: + v_accvgpr_read_b32 v36, a1 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr1 +; %bb.3208: ; %Flow1026 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3209: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a1 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1877.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3211: + v_bfe_u32 v36, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v86, v36, s6 + ; implicit-def: $vgpr86 +; %bb.3212: ; %Flow1025 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3213: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v86, vcc +; %bb.3214: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP_ + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v20 offset:8192 + ds_write_b16_d16_hi v19, v22 offset:8320 + ds_write_b16_d16_hi v19, v23 offset:8448 + ds_write_b16_d16_hi v19, v24 offset:8576 + ds_write_b16_d16_hi v19, v25 offset:9216 + ds_write_b16_d16_hi v19, v26 offset:9344 + ds_write_b16_d16_hi v19, v27 offset:9472 + ds_write_b16_d16_hi v19, v28 offset:9600 + ds_write_b16_d16_hi v19, v29 offset:10240 + ds_write_b16_d16_hi v19, v30 offset:10368 + ds_write_b16_d16_hi v19, v31 offset:10496 + ds_write_b16_d16_hi v19, v32 offset:10624 + ds_write_b16_d16_hi v19, v33 offset:11264 + ds_write_b16_d16_hi v19, v34 offset:11392 + ds_write_b16_d16_hi v19, v35 offset:11520 + ds_write_b16_d16_hi v19, v36 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v0, s4, v1 + v_lshl_or_b32 v1, v0, 7, v21 + ds_read_b128 v[2:5], v1 + ds_read_b128 v[6:9], v1 offset:128 + ds_read_b128 v[10:13], v1 offset:256 + ds_read_b128 v[14:17], v1 offset:384 + v_add_u32_e32 v0, s18, v0 + v_mad_u64_u32 v[0:1], s[4:5], v0, s16, v[18:19] + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[2:3], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[4:5], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[6:7], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[8:9], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[10:11], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[12:13], v1, s[0:3], 8 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[14:15], v0, s[0:3], 0 offen + buffer_store_dwordx2 v[16:17], v0, s[0:3], 8 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end9: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end9-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 100136 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB10_9 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB10_4 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s10 + v_mov_b32_e32 v3, s11 + v_mul_lo_u32 v4, v0, s2 + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v6 +.LBB10_3: ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_ushort v7, v[2:3], off + v_lshl_add_u64 v[8:9], v[4:5], 1, s[8:9] + global_load_ushort v5, v[8:9], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_add_u32_e32 v4, s7, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(1) + v_lshlrev_b32_e32 v7, 16, v7 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v5, 16, v5 + v_fmac_f32_e32 v1, v7, v5 + s_cbranch_scc0 .LBB10_3 +.LBB10_4: ; %._crit_edge + s_mov_b32 s0, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s0, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[0:1], vcc + s_xor_b64 s[0:1], exec, s[0:1] + s_cbranch_execz .LBB10_6 +; %bb.5: + v_bfe_u32 v2, v1, 16, 1 + s_waitcnt lgkmcnt(0) + s_movk_i32 s2, 0x7fff + v_add3_u32 v2, v1, v2, s2 + ; implicit-def: $vgpr1 +.LBB10_6: ; %Flow + s_andn2_saveexec_b64 s[0:1], s[0:1] +; %bb.7: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v1, vcc +; %bb.8: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit + s_or_b64 exec, exec, s[0:1] + s_waitcnt lgkmcnt(0) + v_mad_u64_u32 v[0:1], s[0:1], v6, s3, v[0:1] + v_mov_b32_e32 v4, s12 + v_mov_b32_e32 v5, s13 + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[4:5] + global_store_short_d16_hi v[0:1], v2, off +.LBB10_9: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end10: + .size _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end10-_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 528 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v1, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v1 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s22, s12, s2 + s_mul_i32 s2, s22, s7 + s_mul_i32 s12, s22, s20 + s_sub_i32 s6, s6, s22 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[2:3], s[12:13], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s10, s4, -1 + s_add_u32 s3, s10, s3 + s_add_u32 s22, s3, 1 + s_mul_i32 s2, s20, s2 + s_add_i32 s5, s5, -1 + s_add_u32 s2, s5, s2 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v1 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v1, -1, v1 + v_and_b32_e32 v70, 31, v1 + v_lshrrev_b32_e32 v2, 5, v1 + v_and_b32_e32 v110, 7, v1 + v_lshrrev_b32_e32 v3, 2, v1 + s_cbranch_scc0 .LBB11_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + s_lshr_b32 s25, s15, 2 + v_lshlrev_b32_e32 v71, 3, v2 + s_and_b32 s23, s25, 0x3ffffff0 + v_lshlrev_b32_e32 v6, 3, v70 + v_or_b32_e32 v4, s18, v6 + v_add_u32_e32 v7, s23, v71 + v_mad_u64_u32 v[4:5], s[10:11], v7, s7, v[4:5] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v8, 1, v4 + buffer_load_dwordx4 v[10:13], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v8, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v8, 1, v4 + buffer_load_dwordx4 v[18:21], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[22:25], v8, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v8, 1, v4 + buffer_load_dwordx4 v[26:29], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[30:33], v8, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + v_add_lshl_u32 v4, v4, s7, 1 + buffer_load_dwordx4 v[34:37], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v4, 12, v2 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s10, 0x1000504 + s_mov_b32 s24, 0x3020706 + v_lshl_or_b32 v5, v110, 8, v4 + v_or_b32_e32 v6, s19, v6 + s_lshr_b32 s26, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s25, 0x3fffffe0 + v_and_or_b32 v8, s26, 32, v70 + v_or_b32_e32 v4, s11, v70 + v_lshrrev_b32_e32 v9, 3, v8 + v_lshrrev_b32_e32 v8, 3, v4 + v_mad_u64_u32 v[6:7], s[26:27], v7, s20, v[6:7] + v_xor_b32_e32 v100, v9, v110 + v_xor_b32_e32 v7, v8, v110 + v_lshl_or_b32 v101, v100, 3, v5 + v_lshlrev_b32_e32 v50, 1, v6 + v_add_u32_e32 v6, s20, v6 + v_lshl_add_u32 v5, v7, 3, v5 + v_lshlrev_b32_e32 v51, 1, v6 + v_add_u32_e32 v6, s20, v6 + buffer_load_dwordx4 v[42:45], v50, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v51, s[12:15], 0 offen + v_lshlrev_b32_e32 v58, 1, v6 + v_add_u32_e32 v6, s20, v6 + v_lshlrev_b32_e32 v59, 1, v6 + v_add_u32_e32 v6, s20, v6 + buffer_load_dwordx4 v[50:53], v58, s[12:15], 0 offen + buffer_load_dwordx4 v[54:57], v59, s[12:15], 0 offen + v_lshlrev_b32_e32 v66, 1, v6 + v_add_u32_e32 v6, s20, v6 + v_lshlrev_b32_e32 v67, 1, v6 + v_add_u32_e32 v6, s20, v6 + buffer_load_dwordx4 v[58:61], v66, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v67, s[12:15], 0 offen + v_lshlrev_b32_e32 v76, 1, v6 + v_add_lshl_u32 v6, v6, s20, 1 + buffer_load_dwordx4 v[66:69], v76, s[12:15], 0 offen + buffer_load_dwordx4 v[72:75], v6, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v76, v10, v14, s10 + v_perm_b32 v80, v10, v14, s24 + v_perm_b32 v84, v11, v15, s10 + v_perm_b32 v88, v11, v15, s24 + v_perm_b32 v92, v12, v16, s10 + v_perm_b32 v96, v12, v16, s24 + s_waitcnt vmcnt(12) + v_perm_b32 v77, v18, v22, s10 + v_perm_b32 v81, v18, v22, s24 + v_perm_b32 v85, v19, v23, s10 + v_perm_b32 v89, v19, v23, s24 + v_perm_b32 v93, v20, v24, s10 + s_waitcnt vmcnt(10) + v_perm_b32 v78, v26, v30, s10 + v_perm_b32 v82, v26, v30, s24 + v_perm_b32 v86, v27, v31, s10 + v_perm_b32 v90, v27, v31, s24 + s_waitcnt vmcnt(8) + v_perm_b32 v79, v34, v38, s10 + v_perm_b32 v83, v34, v38, s24 + v_perm_b32 v87, v35, v39, s10 + v_perm_b32 v91, v35, v39, s24 + v_perm_b32 v97, v20, v24, s24 + v_perm_b32 v94, v28, v32, s10 + v_perm_b32 v98, v28, v32, s24 + v_perm_b32 v95, v36, v40, s10 + v_perm_b32 v99, v36, v40, s24 + v_perm_b32 v10, v13, v17, s10 + v_perm_b32 v14, v13, v17, s24 + v_perm_b32 v11, v21, v25, s10 + v_perm_b32 v15, v21, v25, s24 + v_perm_b32 v12, v29, v33, s10 + v_perm_b32 v16, v29, v33, s24 + v_perm_b32 v13, v37, v41, s10 + v_perm_b32 v17, v37, v41, s24 + v_and_b32_e32 v6, 24, v3 + v_add_u32_e32 v6, s23, v6 + v_lshrrev_b32_e32 v18, 2, v6 + v_and_b32_e32 v18, 24, v18 + v_xor_b32_e32 v19, v18, v70 + v_lshlrev_b32_e32 v20, 9, v6 + v_and_b32_e32 v20, 0x3000, v20 + v_lshlrev_b32_e32 v6, 6, v6 + v_and_b32_e32 v6, 0x7ffff800, v6 + v_add_lshl_u32 v6, v6, v20, 1 + v_lshl_or_b32 v6, v19, 4, v6 + ds_write_b128 v6, v[76:79] + v_or_b32_e32 v20, 1, v18 + v_xor_b32_e32 v20, v20, v70 + v_sub_u32_e32 v19, v20, v19 + v_lshl_add_u32 v76, v19, 4, v6 + ds_write_b128 v76, v[80:83] offset:512 + v_or_b32_e32 v19, 2, v18 + v_xor_b32_e32 v19, v19, v70 + v_sub_u32_e32 v20, v19, v20 + v_lshlrev_b32_e32 v20, 4, v20 + s_movk_i32 s11, 0x200 + v_add3_u32 v77, v76, s11, v20 + ds_write_b128 v77, v[84:87] offset:512 + v_or_b32_e32 v20, 3, v18 + v_xor_b32_e32 v20, v20, v70 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 4, v19 + v_add3_u32 v78, v77, s11, v19 + ds_write_b128 v78, v[88:91] offset:512 + v_or_b32_e32 v19, 4, v18 + v_xor_b32_e32 v19, v19, v70 + v_sub_u32_e32 v20, v19, v20 + v_lshlrev_b32_e32 v20, 4, v20 + v_add3_u32 v79, v78, s11, v20 + ds_write_b128 v79, v[92:95] offset:512 + v_or_b32_e32 v20, 5, v18 + v_xor_b32_e32 v20, v20, v70 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 4, v19 + v_add3_u32 v80, v79, s11, v19 + ds_write_b128 v80, v[96:99] offset:512 + v_or_b32_e32 v19, 6, v18 + v_xor_b32_e32 v19, v19, v70 + v_sub_u32_e32 v20, v19, v20 + v_lshlrev_b32_e32 v20, 4, v20 + v_add3_u32 v81, v80, s11, v20 + ds_write_b128 v81, v[10:13] offset:512 + v_or_b32_e32 v10, 7, v18 + v_xor_b32_e32 v10, v10, v70 + v_sub_u32_e32 v10, v10, v19 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v82, v81, s11, v10 + ds_write_b128 v82, v[14:17] offset:512 + s_waitcnt vmcnt(6) + v_perm_b32 v10, v42, v46, s10 + v_perm_b32 v14, v42, v46, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v11, v50, v54, s10 + v_perm_b32 v15, v50, v54, s24 + s_waitcnt vmcnt(2) + v_perm_b32 v12, v58, v62, s10 + v_perm_b32 v16, v58, v62, s24 + s_waitcnt vmcnt(0) + v_perm_b32 v13, v66, v72, s10 + v_perm_b32 v17, v66, v72, s24 + v_perm_b32 v18, v43, v47, s10 + v_perm_b32 v22, v43, v47, s24 + v_perm_b32 v19, v51, v55, s10 + v_perm_b32 v23, v51, v55, s24 + v_perm_b32 v20, v59, v63, s10 + v_perm_b32 v24, v59, v63, s24 + v_perm_b32 v21, v67, v73, s10 + v_perm_b32 v25, v67, v73, s24 + v_perm_b32 v26, v44, v48, s10 + v_perm_b32 v30, v44, v48, s24 + v_perm_b32 v27, v52, v56, s10 + v_perm_b32 v31, v52, v56, s24 + v_perm_b32 v28, v60, v64, s10 + v_perm_b32 v32, v60, v64, s24 + v_perm_b32 v29, v68, v74, s10 + v_perm_b32 v33, v68, v74, s24 + v_perm_b32 v34, v45, v49, s10 + v_perm_b32 v38, v45, v49, s24 + v_perm_b32 v35, v53, v57, s10 + v_perm_b32 v39, v53, v57, s24 + v_perm_b32 v36, v61, v65, s10 + v_perm_b32 v40, v61, v65, s24 + v_perm_b32 v37, v69, v75, s10 + v_perm_b32 v41, v69, v75, s24 + ds_write_b128 v6, v[10:13] offset:32768 + ds_write_b128 v76, v[14:17] offset:33280 + ds_write_b128 v77, v[18:21] offset:33280 + ds_write_b128 v78, v[22:25] offset:33280 + ds_write_b128 v79, v[26:29] offset:33280 + ds_write_b128 v80, v[30:33] offset:33280 + ds_write_b128 v81, v[34:37] offset:33280 + ds_write_b128 v82, v[38:41] offset:33280 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v6, 1, v5 + v_add_u32_e32 v10, 16, v71 + v_lshrrev_b32_e32 v11, 5, v10 + v_bfe_u32 v10, v10, 3, 2 + v_lshl_or_b32 v12, v11, 3, v110 + v_and_b32_e32 v13, 31, v12 + v_xor_b32_e32 v15, v8, v13 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v14, 11, v11 + v_lshlrev_b32_e32 v7, 3, v7 + v_sub_u32_e32 v16, v10, v2 + v_lshl_or_b32 v14, v16, 12, v14 + v_add3_u32 v5, v5, v14, v7 + v_lshlrev_b32_e32 v16, 1, v5 + ds_read_b128 v[44:47], v6 + ds_read_b128 v[56:59], v16 + v_xor_b32_e32 v6, 1, v11 + v_sub_u32_e32 v7, v2, v10 + v_lshl_add_u32 v10, v6, 3, v12 + v_and_b32_e32 v11, 31, v10 + v_xor_b32_e32 v17, v8, v11 + v_sub_u32_e32 v15, v17, v15 + v_lshlrev_b32_e32 v6, 11, v6 + v_lshl_add_u32 v12, v7, 12, v6 + v_lshl_add_u32 v6, v15, 3, v12 + v_add_u32_e32 v7, 48, v71 + v_lshrrev_b32_e32 v15, 5, v7 + v_add_u32_e32 v18, -1, v15 + v_bfe_u32 v19, v7, 3, 2 + v_sub_u32_e32 v20, v19, v2 + v_lshl_add_u32 v21, v18, 3, v10 + v_ashrrev_i32_e32 v7, 31, v21 + v_lshrrev_b32_e32 v7, 27, v7 + v_add_u32_e32 v7, v21, v7 + v_and_b32_e32 v7, 0xffffffe0, v7 + v_sub_u32_e32 v7, v21, v7 + v_lshlrev_b32_e32 v10, 11, v18 + v_lshl_add_u32 v10, v20, 12, v10 + v_sub_u32_e32 v18, v2, v19 + v_lshlrev_b32_e32 v19, 3, v15 + v_sub_u32_e32 v19, v21, v19 + v_ashrrev_i32_e32 v20, 31, v19 + v_lshrrev_b32_e32 v20, 27, v20 + v_add_u32_e32 v20, v19, v20 + v_and_b32_e32 v20, 0xffffffe0, v20 + v_sub_u32_e32 v19, v19, v20 + v_lshlrev_b32_e32 v18, 12, v18 + v_lshlrev_b32_e32 v15, 11, v15 + v_sub_u32_e32 v15, v18, v15 + v_lshlrev_b32_e32 v18, 1, v101 + ds_read_b128 v[60:63], v18 offset:32768 + v_xor_b32_e32 v18, v9, v13 + v_sub_u32_e32 v20, v18, v100 + v_lshlrev_b32_e32 v20, 3, v20 + v_add3_u32 v20, v101, v14, v20 + v_lshlrev_b32_e32 v21, 1, v20 + v_xor_b32_e32 v22, v9, v11 + v_sub_u32_e32 v18, v22, v18 + v_lshl_add_u32 v18, v18, 3, v12 + v_lshl_add_u32 v23, v18, 1, v21 + v_xor_b32_e32 v24, v9, v7 + v_sub_u32_e32 v22, v24, v22 + v_lshl_add_u32 v22, v22, 3, v10 + v_lshl_add_u32 v25, v22, 1, v23 + v_or_b32_e32 v26, 8, v9 + v_xor_b32_e32 v27, v26, v19 + v_sub_u32_e32 v24, v27, v24 + v_lshl_add_u32 v24, v24, 3, v15 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[44:45], v[60:61], 0 + v_lshl_add_u32 v28, v24, 1, v25 + ds_read_b128 v[64:67], v28 offset:32768 + v_xor_b32_e32 v29, v26, v13 + v_sub_u32_e32 v27, v29, v27 + v_lshl_add_u32 v27, v27, 3, v14 + v_lshl_add_u32 v28, v27, 1, v28 + v_xor_b32_e32 v30, v26, v11 + v_mfma_f32_32x32x8_bf16 a[0:15], v[46:47], v[62:63], a[0:15] + v_sub_u32_e32 v29, v30, v29 + v_lshl_add_u32 v29, v29, 3, v12 + v_lshl_add_u32 v31, v29, 1, v28 + v_xor_b32_e32 v26, v26, v7 + v_sub_u32_e32 v30, v26, v30 + v_lshl_add_u32 v30, v30, 3, v10 + v_lshl_add_u32 v32, v30, 1, v31 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[44:45], v[64:65], 0 + v_or_b32_e32 v33, 16, v9 + v_xor_b32_e32 v34, v33, v19 + v_sub_u32_e32 v26, v34, v26 + v_lshl_add_u32 v26, v26, 3, v15 + v_lshl_add_u32 v35, v26, 1, v32 + ds_read_b128 v[72:75], v35 offset:32768 + v_xor_b32_e32 v36, v33, v13 + v_mfma_f32_32x32x8_bf16 a[32:47], v[46:47], v[66:67], a[32:47] + v_sub_u32_e32 v34, v36, v34 + v_lshl_add_u32 v34, v34, 3, v14 + v_lshl_add_u32 v35, v34, 1, v35 + v_xor_b32_e32 v37, v33, v11 + v_sub_u32_e32 v36, v37, v36 + v_lshl_add_u32 v36, v36, 3, v12 + v_lshl_add_u32 v38, v36, 1, v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[44:45], v[72:73], 0 + v_xor_b32_e32 v33, v33, v7 + v_sub_u32_e32 v37, v33, v37 + v_lshl_add_u32 v37, v37, 3, v10 + v_lshl_add_u32 v39, v37, 1, v38 + v_or_b32_e32 v9, 24, v9 + v_xor_b32_e32 v40, v9, v19 + v_sub_u32_e32 v33, v40, v33 + v_mfma_f32_32x32x8_bf16 a[112:127], v[46:47], v[74:75], a[112:127] + v_lshl_add_u32 v33, v33, 3, v15 + v_lshl_add_u32 v41, v33, 1, v39 + ds_read_b128 v[76:79], v41 offset:32768 + v_lshl_add_u32 v16, v6, 1, v16 + v_xor_b32_e32 v8, v8, v7 + v_sub_u32_e32 v17, v8, v17 + v_lshl_add_u32 v17, v17, 3, v10 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[44:45], v[76:77], 0 + v_lshl_add_u32 v42, v17, 1, v16 + v_add_u32_e32 v43, 64, v4 + v_lshrrev_b32_e32 v43, 3, v43 + v_xor_b32_e32 v44, v43, v19 + v_sub_u32_e32 v8, v44, v8 + v_lshl_add_u32 v8, v8, 3, v15 + v_lshl_add_u32 v45, v8, 1, v42 + v_mfma_f32_32x32x8_bf16 a[208:223], v[46:47], v[78:79], a[208:223] + ds_read_b128 v[50:53], v45 + v_xor_b32_e32 v46, v43, v13 + v_sub_u32_e32 v44, v46, v44 + v_lshl_add_u32 v44, v44, 3, v14 + v_lshl_add_u32 v45, v44, 1, v45 + ds_read_b128 v[80:83], v45 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[50:51], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[52:53], v[62:63], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[50:51], v[64:65], 0 + v_mfma_f32_32x32x8_bf16 a[192:207], v[52:53], v[66:67], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[50:51], v[72:73], 0 + v_mfma_f32_32x32x8_bf16 a[160:175], v[52:53], v[74:75], a[160:175] + v_xor_b32_e32 v47, v43, v11 + v_sub_u32_e32 v46, v47, v46 + v_lshl_add_u32 v46, v46, 3, v12 + v_lshl_add_u32 v45, v46, 1, v45 + v_xor_b32_e32 v43, v43, v7 + v_sub_u32_e32 v47, v43, v47 + v_lshl_add_u32 v47, v47, 3, v10 + v_mfma_f32_32x32x8_bf16 a[144:159], v[50:51], v[76:77], 0 + v_lshl_add_u32 v48, v47, 1, v45 + v_add_u32_e32 v49, 0x80, v4 + v_lshrrev_b32_e32 v49, 3, v49 + v_xor_b32_e32 v50, v49, v19 + v_sub_u32_e32 v43, v50, v43 + v_lshl_add_u32 v43, v43, 3, v15 + v_lshl_add_u32 v51, v43, 1, v48 + v_mfma_f32_32x32x8_bf16 a[144:159], v[52:53], v[78:79], a[144:159] + ds_read_b128 v[84:87], v51 + v_xor_b32_e32 v52, v49, v13 + v_sub_u32_e32 v50, v52, v50 + v_lshl_add_u32 v50, v50, 3, v14 + v_lshl_add_u32 v51, v50, 1, v51 + ds_read_b128 v[88:91], v51 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[84:85], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[176:191], v[86:87], v[62:63], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[84:85], v[64:65], 0 + v_mfma_f32_32x32x8_bf16 a[128:143], v[86:87], v[66:67], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[84:85], v[72:73], 0 + v_mfma_f32_32x32x8_bf16 a[80:95], v[86:87], v[74:75], a[80:95] + v_xor_b32_e32 v53, v49, v11 + v_sub_u32_e32 v52, v53, v52 + v_lshl_add_u32 v52, v52, 3, v12 + v_lshl_add_u32 v51, v52, 1, v51 + v_xor_b32_e32 v49, v49, v7 + v_sub_u32_e32 v53, v49, v53 + v_lshl_add_u32 v53, v53, 3, v10 + v_mfma_f32_32x32x8_bf16 a[64:79], v[84:85], v[76:77], 0 + v_lshl_add_u32 v54, v53, 1, v51 + v_add_u32_e32 v4, 0xc0, v4 + v_lshrrev_b32_e32 v4, 3, v4 + v_xor_b32_e32 v19, v4, v19 + v_sub_u32_e32 v49, v19, v49 + v_lshl_add_u32 v15, v49, 3, v15 + v_lshl_add_u32 v49, v15, 1, v54 + v_mfma_f32_32x32x8_bf16 a[64:79], v[86:87], v[78:79], a[64:79] + ds_read_b128 v[84:87], v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[84:85], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[86:87], v[62:63], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[84:85], v[64:65], 0 + v_mfma_f32_32x32x8_bf16 a[48:63], v[86:87], v[66:67], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[84:85], v[72:73], 0 + v_mfma_f32_32x32x8_bf16 a[16:31], v[86:87], v[74:75], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[84:85], v[76:77], 0 + v_mfma_f32_32x32x8_bf16 a[240:255], v[86:87], v[78:79], a[240:255] + ds_read_b128 v[60:63], v21 offset:32768 + ds_read_b128 v[64:67], v23 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[56:57], v[60:61], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[58:59], v[62:63], a[0:15] + ds_read_b128 v[72:75], v28 offset:32768 + ds_read_b128 v[76:79], v31 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[56:57], v[72:73], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[58:59], v[74:75], a[32:47] + ds_read_b128 v[84:87], v35 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[56:57], v[84:85], a[112:127] + v_xor_b32_e32 v21, v9, v13 + v_sub_u32_e32 v23, v21, v40 + v_mfma_f32_32x32x8_bf16 a[112:127], v[58:59], v[86:87], a[112:127] + v_lshl_add_u32 v23, v23, 3, v14 + v_lshl_add_u32 v28, v23, 1, v41 + ds_read_b128 v[92:95], v28 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[56:57], v[92:93], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[58:59], v[94:95], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[80:81], v[60:61], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[82:83], v[62:63], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[80:81], v[72:73], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[82:83], v[74:75], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[80:81], v[84:85], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[82:83], v[86:87], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[80:81], v[92:93], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[82:83], v[94:95], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[88:89], v[60:61], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[90:91], v[62:63], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[88:89], v[72:73], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[90:91], v[74:75], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[88:89], v[84:85], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[90:91], v[86:87], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[88:89], v[92:93], a[64:79] + v_xor_b32_e32 v13, v4, v13 + v_sub_u32_e32 v19, v13, v19 + v_lshl_add_u32 v14, v19, 3, v14 + v_lshl_add_u32 v19, v14, 1, v49 + v_mfma_f32_32x32x8_bf16 a[64:79], v[90:91], v[94:95], a[64:79] + ds_read_b128 v[56:59], v19 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[56:57], v[60:61], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[58:59], v[62:63], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[56:57], v[72:73], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[58:59], v[74:75], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[56:57], v[84:85], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[58:59], v[86:87], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[56:57], v[92:93], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[58:59], v[94:95], a[240:255] + ds_read_b128 v[56:59], v16 + ds_read_b128 v[60:63], v42 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[56:57], v[64:65], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[58:59], v[66:67], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[56:57], v[76:77], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[58:59], v[78:79], a[32:47] + ds_read_b128 v[72:75], v38 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[56:57], v[72:73], a[112:127] + v_xor_b32_e32 v16, v9, v11 + v_sub_u32_e32 v21, v16, v21 + v_mfma_f32_32x32x8_bf16 a[112:127], v[58:59], v[74:75], a[112:127] + v_lshl_add_u32 v21, v21, 3, v12 + v_lshl_add_u32 v28, v21, 1, v28 + ds_read_b128 v[80:83], v28 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[56:57], v[80:81], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[58:59], v[82:83], a[208:223] + ds_read_b128 v[56:59], v45 + ds_read_b128 v[84:87], v48 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[56:57], v[64:65], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[58:59], v[66:67], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[56:57], v[76:77], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[58:59], v[78:79], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[56:57], v[72:73], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[58:59], v[74:75], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[56:57], v[80:81], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[58:59], v[82:83], a[144:159] + ds_read_b128 v[56:59], v51 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[56:57], v[64:65], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[58:59], v[66:67], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[56:57], v[76:77], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[58:59], v[78:79], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[56:57], v[72:73], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[58:59], v[74:75], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[56:57], v[80:81], a[64:79] + v_xor_b32_e32 v11, v4, v11 + v_sub_u32_e32 v13, v11, v13 + v_lshl_add_u32 v12, v13, 3, v12 + v_lshl_add_u32 v13, v12, 1, v19 + v_mfma_f32_32x32x8_bf16 a[64:79], v[58:59], v[82:83], a[64:79] + ds_read_b128 v[56:59], v13 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[56:57], v[64:65], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[58:59], v[66:67], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[56:57], v[76:77], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[58:59], v[78:79], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[56:57], v[72:73], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[58:59], v[74:75], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[56:57], v[80:81], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[58:59], v[82:83], a[240:255] + ds_read_b128 v[56:59], v25 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[60:61], v[56:57], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[62:63], v[58:59], a[0:15] + ds_read_b128 v[64:67], v32 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[60:61], v[64:65], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[62:63], v[66:67], a[32:47] + ds_read_b128 v[38:41], v39 offset:32768 + v_lshlrev_b32_e32 v10, 1, v10 + v_add3_u32 v13, v18, v20, v22 + v_add3_u32 v13, v24, v13, v27 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[60:61], v[38:39], a[112:127] + v_add3_u32 v13, v29, v13, v30 + v_add3_u32 v13, v26, v13, v34 + v_add3_u32 v13, v36, v13, v37 + v_add3_u32 v13, v33, v13, v23 + v_xor_b32_e32 v9, v9, v7 + v_sub_u32_e32 v9, v9, v16 + v_lshlrev_b32_e32 v9, 4, v9 + v_mfma_f32_32x32x8_bf16 a[112:127], v[62:63], v[40:41], a[112:127] + v_add_lshl_u32 v13, v21, v13, 1 + v_add3_u32 v9, v9, v10, v13 + ds_read_b128 v[18:21], v9 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[60:61], v[18:19], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[62:63], v[20:21], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[84:85], v[56:57], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[86:87], v[58:59], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[84:85], v[64:65], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[86:87], v[66:67], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[84:85], v[38:39], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[86:87], v[40:41], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[84:85], v[18:19], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[86:87], v[20:21], a[144:159] + ds_read_b128 v[22:25], v54 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[22:23], v[56:57], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[24:25], v[58:59], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[22:23], v[64:65], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[24:25], v[66:67], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[22:23], v[38:39], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[24:25], v[40:41], a[80:95] + v_add3_u32 v5, v6, v5, v17 + v_add3_u32 v5, v8, v5, v44 + v_add3_u32 v5, v46, v5, v47 + v_add3_u32 v5, v43, v5, v50 + v_mfma_f32_32x32x8_bf16 a[64:79], v[22:23], v[18:19], a[64:79] + v_add3_u32 v5, v52, v5, v53 + v_add3_u32 v5, v15, v5, v14 + v_xor_b32_e32 v4, v4, v7 + v_sub_u32_e32 v4, v4, v11 + v_lshlrev_b32_e32 v4, 4, v4 + v_add_lshl_u32 v5, v12, v5, 1 + v_add3_u32 v4, v4, v10, v5 + v_mfma_f32_32x32x8_bf16 a[64:79], v[24:25], v[20:21], a[64:79] + ds_read_b128 v[4:7], v4 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[56:57], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[6:7], v[58:59], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[64:65], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[6:7], v[66:67], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[38:39], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[40:41], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[18:19], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[20:21], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB11_3 + s_branch .LBB11_10 +.LBB11_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr63 + ; implicit-def: $agpr111 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr143 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr127 + ; implicit-def: $agpr47 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB11_3: + v_readfirstlane_b32 s15, v0 + v_lshlrev_b32_e32 v5, 3, v70 + s_lshr_b32 s24, s15, 2 + s_and_b32 s23, s24, 0x3ffffff0 + v_or_b32_e32 v4, s18, v5 + v_lshlrev_b32_e32 v11, 3, v2 + v_add_u32_e32 v9, s23, v11 + v_mad_u64_u32 v[66:67], s[10:11], v9, s7, v[4:5] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v4, 1, v66 + v_add_u32_e32 v6, s7, v66 + v_lshlrev_b32_e32 v7, 1, v6 + buffer_load_dwordx4 v[12:15], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[16:19], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v6 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v7, 1, v4 + buffer_load_dwordx4 v[20:23], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[24:27], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v7, 1, v4 + buffer_load_dwordx4 v[28:31], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[32:35], v7, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v6, 1, v4 + v_add_lshl_u32 v4, v4, s7, 1 + buffer_load_dwordx4 v[36:39], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[40:43], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v4, 12, v2 + s_lshl_b32 s14, s21, 1 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + v_lshl_or_b32 v44, v110, 8, v4 + v_or_b32_e32 v6, s19, v5 + s_lshr_b32 s25, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s24, s24, 0x3fffffe0 + v_and_or_b32 v4, s25, 32, v70 + v_or_b32_e32 v7, s24, v70 + v_lshrrev_b32_e32 v4, 3, v4 + v_lshrrev_b32_e32 v8, 3, v7 + v_mad_u64_u32 v[68:69], s[24:25], v9, s20, v[6:7] + v_xor_b32_e32 v5, v4, v110 + v_xor_b32_e32 v10, v8, v110 + v_lshl_or_b32 v6, v5, 3, v44 + v_lshlrev_b32_e32 v52, 1, v68 + v_add_u32_e32 v45, s20, v68 + v_lshl_add_u32 v9, v10, 3, v44 + v_lshlrev_b32_e32 v53, 1, v45 + v_add_u32_e32 v54, s20, v45 + buffer_load_dwordx4 v[44:47], v52, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v53, s[12:15], 0 offen + v_lshlrev_b32_e32 v60, 1, v54 + v_add_u32_e32 v52, s20, v54 + v_lshlrev_b32_e32 v61, 1, v52 + v_add_u32_e32 v62, s20, v52 + buffer_load_dwordx4 v[52:55], v60, s[12:15], 0 offen + buffer_load_dwordx4 v[56:59], v61, s[12:15], 0 offen + v_lshlrev_b32_e32 v64, 1, v62 + v_add_u32_e32 v60, s20, v62 + v_lshlrev_b32_e32 v65, 1, v60 + v_add_u32_e32 v67, s20, v60 + buffer_load_dwordx4 v[60:63], v64, s[12:15], 0 offen + buffer_load_dwordx4 v[72:75], v65, s[12:15], 0 offen + v_lshlrev_b32_e32 v64, 1, v67 + v_add_lshl_u32 v65, v67, s20, 1 + buffer_load_dwordx4 v[76:79], v64, s[12:15], 0 offen + buffer_load_dwordx4 v[80:83], v65, s[12:15], 0 offen + s_waitcnt vmcnt(14) + v_perm_b32 v84, v12, v16, s21 + v_perm_b32 v88, v12, v16, s22 + v_perm_b32 v92, v13, v17, s21 + v_perm_b32 v96, v13, v17, s22 + v_perm_b32 v102, v14, v18, s21 + v_perm_b32 v106, v14, v18, s22 + s_waitcnt vmcnt(12) + v_perm_b32 v85, v20, v24, s21 + v_perm_b32 v89, v20, v24, s22 + v_perm_b32 v93, v21, v25, s21 + v_perm_b32 v97, v21, v25, s22 + v_perm_b32 v103, v22, v26, s21 + s_waitcnt vmcnt(10) + v_perm_b32 v86, v28, v32, s21 + v_perm_b32 v90, v28, v32, s22 + v_perm_b32 v94, v29, v33, s21 + v_perm_b32 v98, v29, v33, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v87, v36, v40, s21 + v_perm_b32 v91, v36, v40, s22 + v_perm_b32 v95, v37, v41, s21 + v_perm_b32 v99, v37, v41, s22 + v_perm_b32 v107, v22, v26, s22 + v_perm_b32 v104, v30, v34, s21 + v_perm_b32 v108, v30, v34, s22 + v_perm_b32 v105, v38, v42, s21 + v_perm_b32 v109, v38, v42, s22 + v_perm_b32 v12, v15, v19, s21 + v_perm_b32 v16, v15, v19, s22 + v_perm_b32 v13, v23, v27, s21 + v_perm_b32 v17, v23, v27, s22 + v_perm_b32 v14, v31, v35, s21 + v_perm_b32 v18, v31, v35, s22 + v_perm_b32 v15, v39, v43, s21 + v_perm_b32 v19, v39, v43, s22 + v_and_b32_e32 v101, 24, v3 + v_add_u32_e32 v3, s23, v101 + v_lshrrev_b32_e32 v20, 2, v3 + v_and_b32_e32 v20, 24, v20 + v_xor_b32_e32 v21, v20, v70 + v_lshlrev_b32_e32 v22, 9, v3 + v_and_b32_e32 v22, 0x3000, v22 + v_lshlrev_b32_e32 v3, 6, v3 + v_and_b32_e32 v3, 0x7ffff800, v3 + v_add_lshl_u32 v3, v3, v22, 1 + v_lshl_or_b32 v3, v21, 4, v3 + ds_write_b128 v3, v[84:87] + v_or_b32_e32 v22, 1, v20 + v_xor_b32_e32 v22, v22, v70 + v_sub_u32_e32 v21, v22, v21 + v_lshl_add_u32 v64, v21, 4, v3 + ds_write_b128 v64, v[88:91] offset:512 + v_or_b32_e32 v21, 2, v20 + v_xor_b32_e32 v21, v21, v70 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 4, v22 + s_movk_i32 s23, 0x200 + v_add3_u32 v65, v64, s23, v22 + ds_write_b128 v65, v[92:95] offset:512 + v_or_b32_e32 v22, 3, v20 + v_xor_b32_e32 v22, v22, v70 + v_sub_u32_e32 v21, v22, v21 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v67, v65, s23, v21 + ds_write_b128 v67, v[96:99] offset:512 + v_or_b32_e32 v21, 4, v20 + v_xor_b32_e32 v21, v21, v70 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 4, v22 + v_add3_u32 v69, v67, s23, v22 + ds_write_b128 v69, v[102:105] offset:512 + v_or_b32_e32 v22, 5, v20 + v_xor_b32_e32 v22, v22, v70 + v_sub_u32_e32 v21, v22, v21 + v_lshlrev_b32_e32 v21, 4, v21 + v_add3_u32 v71, v69, s23, v21 + ds_write_b128 v71, v[106:109] offset:512 + v_or_b32_e32 v21, 6, v20 + v_xor_b32_e32 v21, v21, v70 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 4, v22 + v_add3_u32 v84, v71, s23, v22 + ds_write_b128 v84, v[12:15] offset:512 + v_or_b32_e32 v12, 7, v20 + v_xor_b32_e32 v12, v12, v70 + v_sub_u32_e32 v12, v12, v21 + v_lshlrev_b32_e32 v12, 4, v12 + v_add3_u32 v85, v84, s23, v12 + ds_write_b128 v85, v[16:19] offset:512 + s_waitcnt vmcnt(6) + v_perm_b32 v12, v44, v48, s21 + v_perm_b32 v16, v44, v48, s22 + s_waitcnt vmcnt(4) + v_perm_b32 v13, v52, v56, s21 + v_perm_b32 v17, v52, v56, s22 + s_waitcnt vmcnt(2) + v_perm_b32 v14, v60, v72, s21 + v_perm_b32 v18, v60, v72, s22 + s_waitcnt vmcnt(0) + v_perm_b32 v15, v76, v80, s21 + v_perm_b32 v19, v76, v80, s22 + v_perm_b32 v20, v45, v49, s21 + v_perm_b32 v24, v45, v49, s22 + v_perm_b32 v21, v53, v57, s21 + v_perm_b32 v25, v53, v57, s22 + v_perm_b32 v22, v61, v73, s21 + v_perm_b32 v26, v61, v73, s22 + v_perm_b32 v23, v77, v81, s21 + v_perm_b32 v27, v77, v81, s22 + v_perm_b32 v28, v46, v50, s21 + v_perm_b32 v32, v46, v50, s22 + v_perm_b32 v29, v54, v58, s21 + v_perm_b32 v33, v54, v58, s22 + v_perm_b32 v30, v62, v74, s21 + v_perm_b32 v34, v62, v74, s22 + v_perm_b32 v31, v78, v82, s21 + v_perm_b32 v35, v78, v82, s22 + v_perm_b32 v36, v47, v51, s21 + v_perm_b32 v40, v47, v51, s22 + v_perm_b32 v37, v55, v59, s21 + v_perm_b32 v41, v55, v59, s22 + v_perm_b32 v38, v63, v75, s21 + v_perm_b32 v42, v63, v75, s22 + v_perm_b32 v39, v79, v83, s21 + v_perm_b32 v43, v79, v83, s22 + ds_write_b128 v3, v[12:15] offset:32768 + ds_write_b128 v64, v[16:19] offset:33280 + ds_write_b128 v65, v[20:23] offset:33280 + ds_write_b128 v67, v[24:27] offset:33280 + ds_write_b128 v69, v[28:31] offset:33280 + ds_write_b128 v71, v[32:35] offset:33280 + ds_write_b128 v84, v[36:39] offset:33280 + ds_write_b128 v85, v[40:43] offset:33280 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v15, 16, v11 + v_add_u32_e32 v14, 48, v11 + v_add_u32_e32 v13, 64, v7 + v_or_b32_e32 v12, 8, v4 + v_or_b32_e32 v11, 16, v4 + v_or_b32_e32 v3, 24, v4 + s_cbranch_vccnz .LBB11_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit768.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_lshrrev_b32_e32 v16, 5, v15 + v_bfe_u32 v17, v15, 3, 2 + v_lshl_or_b32 v18, v16, 3, v110 + v_xor_b32_e32 v19, v8, v18 + v_sub_u32_e32 v20, v19, v10 + v_lshlrev_b32_e32 v21, 11, v16 + v_lshlrev_b32_e32 v20, 3, v20 + v_sub_u32_e32 v22, v17, v2 + v_lshl_or_b32 v21, v22, 12, v21 + v_add3_u32 v73, v9, v21, v20 + v_xor_b32_e32 v16, 1, v16 + v_sub_u32_e32 v17, v2, v17 + v_lshl_add_u32 v20, v16, 3, v18 + v_xor_b32_e32 v22, v8, v20 + v_sub_u32_e32 v19, v22, v19 + v_lshlrev_b32_e32 v16, 11, v16 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshl_or_b32 v16, v17, 12, v16 + v_add3_u32 v74, v19, v16, v73 + v_lshrrev_b32_e32 v17, 5, v14 + v_add_u32_e32 v19, -1, v17 + v_bfe_u32 v23, v14, 3, 2 + v_sub_u32_e32 v24, v23, v2 + v_lshl_add_u32 v25, v19, 3, v20 + v_ashrrev_i32_e32 v26, 31, v25 + v_lshrrev_b32_e32 v26, 27, v26 + v_add_u32_e32 v26, v25, v26 + v_and_b32_e32 v26, 0xffffffe0, v26 + v_sub_u32_e32 v26, v25, v26 + v_xor_b32_e32 v27, v8, v26 + v_sub_u32_e32 v22, v27, v22 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshl_add_u32 v19, v24, 12, v19 + v_add3_u32 v67, v22, v19, v74 + v_lshrrev_b32_e32 v22, 3, v13 + v_sub_u32_e32 v23, v2, v23 + v_lshlrev_b32_e32 v24, 3, v17 + v_sub_u32_e32 v24, v25, v24 + v_ashrrev_i32_e32 v25, 31, v24 + v_lshrrev_b32_e32 v25, 27, v25 + v_add_u32_e32 v25, v24, v25 + v_and_b32_e32 v25, 0xffffffe0, v25 + v_sub_u32_e32 v24, v24, v25 + v_xor_b32_e32 v25, v22, v24 + v_sub_u32_e32 v27, v25, v27 + v_lshlrev_b32_e32 v27, 3, v27 + v_lshlrev_b32_e32 v23, 12, v23 + v_lshlrev_b32_e32 v17, 11, v17 + v_sub_u32_e32 v17, v23, v17 + v_add3_u32 v92, v27, v17, v67 + v_xor_b32_e32 v23, v22, v18 + v_sub_u32_e32 v25, v23, v25 + v_lshlrev_b32_e32 v25, 3, v25 + v_add3_u32 v75, v25, v21, v92 + v_xor_b32_e32 v25, v22, v20 + v_sub_u32_e32 v23, v25, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v76, v23, v16, v75 + v_xor_b32_e32 v22, v22, v26 + v_sub_u32_e32 v23, v22, v25 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v69, v23, v19, v76 + v_add_u32_e32 v23, 0x80, v7 + v_lshrrev_b32_e32 v23, 3, v23 + v_xor_b32_e32 v25, v23, v24 + v_sub_u32_e32 v22, v25, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v91, v22, v17, v69 + v_xor_b32_e32 v22, v23, v18 + v_sub_u32_e32 v25, v22, v25 + v_lshlrev_b32_e32 v25, 3, v25 + v_add3_u32 v77, v25, v21, v91 + v_xor_b32_e32 v25, v23, v20 + v_sub_u32_e32 v22, v25, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v78, v22, v16, v77 + v_xor_b32_e32 v22, v23, v26 + v_sub_u32_e32 v23, v22, v25 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v71, v23, v19, v78 + v_add_u32_e32 v23, 0xc0, v7 + v_lshrrev_b32_e32 v23, 3, v23 + v_xor_b32_e32 v25, v23, v24 + v_sub_u32_e32 v22, v25, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v90, v22, v17, v71 + v_xor_b32_e32 v22, v23, v18 + v_sub_u32_e32 v25, v22, v25 + v_lshlrev_b32_e32 v25, 3, v25 + v_add3_u32 v79, v25, v21, v90 + v_xor_b32_e32 v25, v23, v20 + v_sub_u32_e32 v22, v25, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v80, v22, v16, v79 + v_xor_b32_e32 v22, v23, v26 + v_sub_u32_e32 v22, v22, v25 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v72, v22, v19, v80 + v_xor_b32_e32 v22, v4, v18 + v_sub_u32_e32 v23, v22, v5 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v87, v6, v21, v23 + v_xor_b32_e32 v23, v4, v20 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v81, v22, v16, v87 + v_xor_b32_e32 v22, v4, v26 + v_sub_u32_e32 v23, v22, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v82, v23, v19, v81 + v_xor_b32_e32 v23, v12, v24 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v93, v22, v17, v82 + v_xor_b32_e32 v22, v12, v18 + v_sub_u32_e32 v23, v22, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v94, v23, v21, v93 + v_xor_b32_e32 v23, v12, v20 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v83, v22, v16, v94 + v_xor_b32_e32 v22, v12, v26 + v_sub_u32_e32 v23, v22, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v84, v23, v19, v83 + v_xor_b32_e32 v23, v11, v24 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v95, v22, v17, v84 + v_xor_b32_e32 v22, v11, v18 + v_sub_u32_e32 v23, v22, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v96, v23, v21, v95 + v_xor_b32_e32 v23, v11, v20 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v85, v22, v16, v96 + v_xor_b32_e32 v22, v11, v26 + v_sub_u32_e32 v23, v22, v23 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v86, v23, v19, v85 + v_xor_b32_e32 v23, v3, v24 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v97, v22, v17, v86 + v_xor_b32_e32 v17, v3, v18 + v_sub_u32_e32 v18, v17, v23 + v_lshlrev_b32_e32 v18, 3, v18 + v_add3_u32 v98, v18, v21, v97 + v_xor_b32_e32 v18, v3, v20 + v_sub_u32_e32 v17, v18, v17 + v_lshlrev_b32_e32 v17, 3, v17 + v_add3_u32 v88, v17, v16, v98 + v_xor_b32_e32 v16, v3, v26 + v_sub_u32_e32 v16, v16, v18 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v89, v16, v19, v88 + s_mov_b64 s[2:3], 0 + s_branch .LBB11_6 +.LBB11_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr89 +.LBB11_6: ; %Flow1284 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_lshlrev_b32_e32 v100, 1, v9 + v_lshlrev_b32_e32 v99, 1, v6 + s_cbranch_vccnz .LBB11_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1666.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s20, 6 + s_lshl_b32 s6, s7, 6 + v_lshrrev_b32_e32 v16, 5, v15 + v_bfe_u32 v15, v15, 3, 2 + v_lshl_or_b32 v17, v16, 3, v110 + v_xor_b32_e32 v18, v8, v17 + v_sub_u32_e32 v10, v18, v10 + v_lshlrev_b32_e32 v19, 11, v16 + v_lshlrev_b32_e32 v10, 3, v10 + v_sub_u32_e32 v20, v15, v2 + v_lshl_or_b32 v19, v20, 12, v19 + v_add3_u32 v73, v9, v19, v10 + v_xor_b32_e32 v9, 1, v16 + v_sub_u32_e32 v10, v2, v15 + v_lshl_add_u32 v15, v9, 3, v17 + v_xor_b32_e32 v16, v8, v15 + v_sub_u32_e32 v18, v16, v18 + v_lshlrev_b32_e32 v9, 11, v9 + v_lshlrev_b32_e32 v18, 3, v18 + v_lshl_or_b32 v9, v10, 12, v9 + v_add3_u32 v74, v18, v9, v73 + v_lshrrev_b32_e32 v10, 5, v14 + v_add_u32_e32 v18, -1, v10 + v_bfe_u32 v14, v14, 3, 2 + v_sub_u32_e32 v20, v14, v2 + v_lshl_add_u32 v21, v18, 3, v15 + v_ashrrev_i32_e32 v22, 31, v21 + v_lshrrev_b32_e32 v22, 27, v22 + v_add_u32_e32 v22, v21, v22 + v_and_b32_e32 v22, 0xffffffe0, v22 + v_sub_u32_e32 v22, v21, v22 + v_xor_b32_e32 v8, v8, v22 + v_sub_u32_e32 v16, v8, v16 + v_lshlrev_b32_e32 v18, 11, v18 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshl_add_u32 v18, v20, 12, v18 + v_add3_u32 v67, v16, v18, v74 + v_lshrrev_b32_e32 v13, 3, v13 + v_sub_u32_e32 v2, v2, v14 + v_lshlrev_b32_e32 v14, 3, v10 + v_sub_u32_e32 v14, v21, v14 + v_ashrrev_i32_e32 v16, 31, v14 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v14, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v14, v14, v16 + v_xor_b32_e32 v16, v13, v14 + v_sub_u32_e32 v8, v16, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_lshlrev_b32_e32 v2, 12, v2 + v_lshlrev_b32_e32 v10, 11, v10 + v_sub_u32_e32 v2, v2, v10 + v_add3_u32 v92, v8, v2, v67 + v_xor_b32_e32 v8, v13, v17 + v_sub_u32_e32 v10, v8, v16 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v75, v10, v19, v92 + v_xor_b32_e32 v10, v13, v15 + v_sub_u32_e32 v8, v10, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v76, v8, v9, v75 + v_xor_b32_e32 v8, v13, v22 + v_sub_u32_e32 v10, v8, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v69, v10, v18, v76 + v_add_u32_e32 v10, 0x80, v7 + v_lshrrev_b32_e32 v10, 3, v10 + v_xor_b32_e32 v13, v10, v14 + v_sub_u32_e32 v8, v13, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v91, v8, v2, v69 + v_xor_b32_e32 v8, v10, v17 + v_sub_u32_e32 v13, v8, v13 + v_lshlrev_b32_e32 v13, 3, v13 + v_add3_u32 v77, v13, v19, v91 + v_xor_b32_e32 v13, v10, v15 + v_sub_u32_e32 v8, v13, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v78, v8, v9, v77 + v_xor_b32_e32 v8, v10, v22 + v_sub_u32_e32 v10, v8, v13 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v71, v10, v18, v78 + v_add_u32_e32 v7, 0xc0, v7 + v_lshrrev_b32_e32 v7, 3, v7 + v_xor_b32_e32 v10, v7, v14 + v_sub_u32_e32 v8, v10, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v90, v8, v2, v71 + v_xor_b32_e32 v8, v7, v17 + v_sub_u32_e32 v10, v8, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v79, v10, v19, v90 + v_xor_b32_e32 v10, v7, v15 + v_sub_u32_e32 v8, v10, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v80, v8, v9, v79 + v_xor_b32_e32 v7, v7, v22 + v_sub_u32_e32 v7, v7, v10 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v72, v7, v18, v80 + v_xor_b32_e32 v7, v4, v17 + v_sub_u32_e32 v5, v7, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v87, v6, v19, v5 + v_xor_b32_e32 v5, v4, v15 + v_sub_u32_e32 v6, v5, v7 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v81, v6, v9, v87 + v_xor_b32_e32 v4, v4, v22 + v_sub_u32_e32 v5, v4, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v82, v5, v18, v81 + v_xor_b32_e32 v5, v12, v14 + v_sub_u32_e32 v4, v5, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v93, v4, v2, v82 + v_xor_b32_e32 v4, v12, v17 + v_sub_u32_e32 v5, v4, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v94, v5, v19, v93 + v_xor_b32_e32 v5, v12, v15 + v_sub_u32_e32 v4, v5, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v83, v4, v9, v94 + v_xor_b32_e32 v4, v12, v22 + v_sub_u32_e32 v5, v4, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v84, v5, v18, v83 + v_xor_b32_e32 v5, v11, v14 + v_sub_u32_e32 v4, v5, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v95, v4, v2, v84 + v_xor_b32_e32 v4, v11, v17 + v_sub_u32_e32 v5, v4, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v96, v5, v19, v95 + v_xor_b32_e32 v5, v11, v15 + v_sub_u32_e32 v4, v5, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v85, v4, v9, v96 + v_xor_b32_e32 v4, v11, v22 + v_sub_u32_e32 v5, v4, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add3_u32 v86, v5, v18, v85 + v_xor_b32_e32 v5, v3, v14 + v_sub_u32_e32 v4, v5, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v97, v4, v2, v86 + v_xor_b32_e32 v2, v3, v17 + v_sub_u32_e32 v4, v2, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v98, v4, v19, v97 + v_xor_b32_e32 v4, v3, v15 + v_sub_u32_e32 v2, v4, v2 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v88, v2, v9, v98 + v_xor_b32_e32 v2, v3, v22 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v89, v2, v18, v88 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 +.LBB11_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1666.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v68, s2, v68 + v_add_u32_e32 v66, s6, v66 + v_lshlrev_b32_e32 v2, 1, v66 + v_add_u32_e32 v3, s7, v66 + v_lshlrev_b32_e32 v4, 1, v68 + v_add_u32_e32 v5, s20, v68 + v_lshlrev_b32_e32 v6, 1, v3 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[30:33], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_u32_e32 v5, s20, v5 + buffer_load_dwordx4 v[58:61], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v6, s[8:11], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[50:53], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_u32_e32 v5, s20, v5 + v_lshlrev_b32_e32 v6, 1, v3 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[22:25], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_u32_e32 v5, s20, v5 + buffer_load_dwordx4 v[46:49], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v6, s[8:11], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[38:41], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_u32_e32 v5, s20, v5 + v_lshlrev_b32_e32 v6, 1, v3 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[10:13], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_u32_e32 v5, s20, v5 + buffer_load_dwordx4 v[34:37], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[42:45], v6, s[8:11], 0 offen + v_lshlrev_b32_e32 v2, 1, v3 + v_add_lshl_u32 v3, v3, s7, 1 + buffer_load_dwordx4 v[26:29], v4, s[12:15], 0 offen + v_lshlrev_b32_e32 v4, 1, v5 + v_add_lshl_u32 v6, v5, s20, 1 + buffer_load_dwordx4 v[14:17], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[18:21], v3, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v4, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[6:9], v6, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[106:109], v100 + ds_read_b128 v[102:105], v99 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[106:107], v[102:103], a[112:127] + v_lshlrev_b32_e32 v110, 1, v93 + ds_read_b128 v[112:115], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v94 + ds_read_b128 v[116:119], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[106:107], v[112:113], a[96:111] + v_lshlrev_b32_e32 v110, 1, v95 + ds_read_b128 v[120:123], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v96 + ds_read_b128 v[124:127], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[106:107], v[120:121], a[80:95] + v_lshlrev_b32_e32 v110, 1, v97 + ds_read_b128 v[128:131], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v98 + ds_read_b128 v[132:135], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[106:107], v[128:129], a[128:143] + v_lshlrev_b32_e32 v106, 1, v92 + ds_read_b128 v[136:139], v106 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[144:159], v[136:137], v[102:103], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[136:137], v[112:113], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[136:137], v[120:121], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[136:137], v[128:129], a[160:175] + v_lshlrev_b32_e32 v106, 1, v91 + ds_read_b128 v[140:143], v106 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[140:141], v[102:103], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[140:141], v[112:113], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[140:141], v[120:121], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[140:141], v[128:129], a[224:239] + v_lshlrev_b32_e32 v106, 1, v90 + ds_read_b128 v[144:147], v106 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[102:103], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[144:145], v[112:113], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[144:145], v[120:121], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[144:145], v[128:129], a[48:63] + v_mfma_f32_32x32x8_bf16 a[112:127], v[108:109], v[104:105], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[108:109], v[114:115], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[108:109], v[122:123], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[108:109], v[130:131], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[138:139], v[104:105], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[138:139], v[114:115], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[138:139], v[122:123], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[138:139], v[130:131], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[142:143], v[104:105], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[142:143], v[114:115], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[142:143], v[122:123], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[142:143], v[130:131], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[104:105], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[146:147], v[114:115], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[146:147], v[122:123], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[146:147], v[130:131], a[48:63] + v_lshlrev_b32_e32 v102, 1, v73 + ds_read_b128 v[104:107], v102 + v_lshlrev_b32_e32 v102, 1, v87 + ds_read_b128 v[108:111], v102 offset:32768 + v_lshlrev_b32_e32 v102, 1, v74 + ds_read_b128 v[120:123], v102 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[104:105], v[108:109], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[104:105], v[116:117], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[104:105], v[124:125], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[104:105], v[132:133], a[128:143] + v_lshlrev_b32_e32 v102, 1, v75 + ds_read_b128 v[112:115], v102 + v_lshlrev_b32_e32 v102, 1, v76 + ds_read_b128 v[128:131], v102 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[144:159], v[112:113], v[108:109], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[112:113], v[116:117], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[112:113], v[124:125], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[112:113], v[132:133], a[160:175] + v_lshlrev_b32_e32 v102, 1, v77 + ds_read_b128 v[136:139], v102 + v_lshlrev_b32_e32 v102, 1, v78 + ds_read_b128 v[140:143], v102 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[136:137], v[108:109], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[136:137], v[116:117], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[136:137], v[124:125], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[136:137], v[132:133], a[224:239] + v_lshlrev_b32_e32 v102, 1, v79 + ds_read_b128 v[144:147], v102 + v_lshlrev_b32_e32 v102, 1, v80 + ds_read_b128 v[148:151], v102 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[108:109], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[144:145], v[116:117], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[144:145], v[124:125], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[144:145], v[132:133], a[48:63] + v_mfma_f32_32x32x8_bf16 a[112:127], v[106:107], v[110:111], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[106:107], v[118:119], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[106:107], v[126:127], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[106:107], v[134:135], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[114:115], v[110:111], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[114:115], v[118:119], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[114:115], v[126:127], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[114:115], v[134:135], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[138:139], v[110:111], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[138:139], v[118:119], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[138:139], v[126:127], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[138:139], v[134:135], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[110:111], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[146:147], v[118:119], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[146:147], v[126:127], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[146:147], v[134:135], a[48:63] + v_lshlrev_b32_e32 v102, 1, v81 + ds_read_b128 v[124:127], v102 offset:32768 + v_lshlrev_b32_e32 v102, 1, v82 + ds_read_b128 v[114:117], v102 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[120:121], v[124:125], a[112:127] + v_lshlrev_b32_e32 v102, 1, v83 + ds_read_b128 v[132:135], v102 offset:32768 + v_lshlrev_b32_e32 v102, 1, v84 + ds_read_b128 v[110:113], v102 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[120:121], v[132:133], a[96:111] + v_lshlrev_b32_e32 v102, 1, v85 + ds_read_b128 v[136:139], v102 offset:32768 + v_lshlrev_b32_e32 v102, 1, v86 + ds_read_b128 v[106:109], v102 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[120:121], v[136:137], a[80:95] + v_lshlrev_b32_e32 v102, 1, v88 + ds_read_b128 v[144:147], v102 offset:32768 + v_lshlrev_b32_e32 v102, 1, v89 + ds_read_b128 v[102:105], v102 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[120:121], v[144:145], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[128:129], v[124:125], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[128:129], v[132:133], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[128:129], v[136:137], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[128:129], v[144:145], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[140:141], v[124:125], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[140:141], v[132:133], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[140:141], v[136:137], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[140:141], v[144:145], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[124:125], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[148:149], v[132:133], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[148:149], v[136:137], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[148:149], v[144:145], a[48:63] + v_mfma_f32_32x32x8_bf16 a[112:127], v[122:123], v[126:127], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[122:123], v[134:135], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[122:123], v[138:139], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[122:123], v[146:147], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[130:131], v[126:127], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[130:131], v[134:135], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[130:131], v[138:139], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[130:131], v[146:147], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[142:143], v[126:127], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[142:143], v[134:135], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[142:143], v[138:139], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[142:143], v[146:147], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[126:127], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[150:151], v[134:135], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[150:151], v[138:139], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[150:151], v[146:147], a[48:63] + v_lshlrev_b32_e32 v118, 1, v67 + ds_read_b128 v[118:121], v118 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[118:119], v[114:115], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[118:119], v[110:111], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[118:119], v[106:107], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[118:119], v[102:103], a[128:143] + v_lshlrev_b32_e32 v118, 1, v69 + ds_read_b128 v[122:125], v118 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[144:159], v[122:123], v[114:115], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[122:123], v[110:111], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[122:123], v[106:107], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[122:123], v[102:103], a[160:175] + v_lshlrev_b32_e32 v118, 1, v71 + ds_read_b128 v[126:129], v118 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[126:127], v[114:115], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[126:127], v[110:111], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[126:127], v[106:107], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[126:127], v[102:103], a[224:239] + v_lshlrev_b32_e32 v118, 1, v72 + ds_read_b128 v[130:133], v118 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[240:255], v[130:131], v[114:115], a[240:255] + v_mfma_f32_32x32x8_bf16 a[32:47], v[130:131], v[110:111], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[130:131], v[106:107], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[130:131], v[102:103], a[48:63] + v_mfma_f32_32x32x8_bf16 a[112:127], v[120:121], v[116:117], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[120:121], v[112:113], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[120:121], v[108:109], a[80:95] + v_mfma_f32_32x32x8_bf16 a[128:143], v[120:121], v[104:105], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[124:125], v[116:117], a[144:159] + v_mfma_f32_32x32x8_bf16 a[64:79], v[124:125], v[112:113], a[64:79] + v_mfma_f32_32x32x8_bf16 a[0:15], v[124:125], v[108:109], a[0:15] + v_mfma_f32_32x32x8_bf16 a[160:175], v[124:125], v[104:105], a[160:175] + s_add_i32 s24, s3, -1 + v_readfirstlane_b32 s25, v0 + s_lshr_b32 s25, s25, 2 + v_mfma_f32_32x32x8_bf16 a[176:191], v[128:129], v[116:117], a[176:191] + s_and_b32 s25, s25, 0x3ffffff0 + v_add_u32_e32 v102, s25, v101 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s24 + v_lshrrev_b32_e32 v103, 2, v102 + v_lshlrev_b32_e32 v106, 9, v102 + v_lshlrev_b32_e32 v102, 6, v102 + v_mfma_f32_32x32x8_bf16 a[192:207], v[128:129], v[112:113], a[192:207] + v_and_b32_e32 v103, 24, v103 + v_and_b32_e32 v106, 0x3000, v106 + v_and_b32_e32 v102, 0x7ffff800, v102 + v_xor_b32_e32 v107, v103, v70 + v_add_lshl_u32 v102, v102, v106, 1 + v_or_b32_e32 v106, 1, v103 + v_or_b32_e32 v110, 2, v103 + v_mfma_f32_32x32x8_bf16 a[208:223], v[128:129], v[108:109], a[208:223] + v_or_b32_e32 v111, 3, v103 + v_or_b32_e32 v114, 4, v103 + v_or_b32_e32 v115, 5, v103 + v_or_b32_e32 v118, 6, v103 + v_or_b32_e32 v103, 7, v103 + v_lshl_or_b32 v150, v107, 4, v102 + v_xor_b32_e32 v102, v106, v70 + v_mfma_f32_32x32x8_bf16 a[224:239], v[128:129], v[104:105], a[224:239] + v_xor_b32_e32 v106, v110, v70 + v_xor_b32_e32 v110, v111, v70 + v_xor_b32_e32 v111, v114, v70 + v_xor_b32_e32 v114, v115, v70 + v_xor_b32_e32 v115, v118, v70 + v_xor_b32_e32 v103, v103, v70 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[240:255], v[132:133], v[116:117], a[240:255] + s_barrier + v_sub_u32_e32 v107, v102, v107 + v_sub_u32_e32 v102, v106, v102 + v_sub_u32_e32 v106, v110, v106 + v_sub_u32_e32 v110, v111, v110 + v_sub_u32_e32 v111, v114, v111 + v_sub_u32_e32 v114, v115, v114 + v_mfma_f32_32x32x8_bf16 a[32:47], v[132:133], v[112:113], a[32:47] + v_sub_u32_e32 v103, v103, v115 + v_lshl_add_u32 v151, v107, 4, v150 + v_lshlrev_b32_e32 v102, 4, v102 + v_lshlrev_b32_e32 v106, 4, v106 + v_lshlrev_b32_e32 v107, 4, v110 + v_lshlrev_b32_e32 v110, 4, v111 + v_lshlrev_b32_e32 v111, 4, v114 + v_mfma_f32_32x32x8_bf16 a[16:31], v[132:133], v[108:109], a[16:31] + v_lshlrev_b32_e32 v103, 4, v103 + v_add3_u32 v152, v151, s23, v102 + v_add3_u32 v153, v152, s23, v106 + v_add3_u32 v154, v153, s23, v107 + v_add3_u32 v155, v154, s23, v110 + v_add3_u32 v156, v155, s23, v111 + v_add3_u32 v157, v156, s23, v103 + v_mfma_f32_32x32x8_bf16 a[48:63], v[132:133], v[104:105], a[48:63] + s_waitcnt vmcnt(13) + v_perm_b32 v102, v58, v62, s21 + v_perm_b32 v58, v58, v62, s22 + v_perm_b32 v62, v59, v63, s21 + v_perm_b32 v106, v59, v63, s22 + v_perm_b32 v110, v60, v64, s21 + v_perm_b32 v114, v60, v64, s22 + v_perm_b32 v118, v61, v65, s21 + v_perm_b32 v122, v61, v65, s22 + s_waitcnt vmcnt(12) + v_perm_b32 v126, v30, v50, s21 + v_perm_b32 v30, v30, v50, s22 + v_perm_b32 v50, v31, v51, s21 + v_perm_b32 v130, v31, v51, s22 + v_perm_b32 v134, v32, v52, s21 + v_perm_b32 v138, v32, v52, s22 + v_perm_b32 v142, v33, v53, s21 + v_perm_b32 v146, v33, v53, s22 + s_waitcnt vmcnt(9) + v_perm_b32 v103, v46, v54, s21 + v_perm_b32 v59, v46, v54, s22 + v_perm_b32 v63, v47, v55, s21 + v_perm_b32 v107, v47, v55, s22 + v_perm_b32 v111, v48, v56, s21 + v_perm_b32 v115, v48, v56, s22 + v_perm_b32 v119, v49, v57, s21 + v_perm_b32 v123, v49, v57, s22 + s_waitcnt vmcnt(8) + v_perm_b32 v127, v22, v38, s21 + v_perm_b32 v31, v22, v38, s22 + v_perm_b32 v51, v23, v39, s21 + v_perm_b32 v131, v23, v39, s22 + v_perm_b32 v135, v24, v40, s21 + v_perm_b32 v139, v24, v40, s22 + v_perm_b32 v143, v25, v41, s21 + v_perm_b32 v147, v25, v41, s22 + s_waitcnt vmcnt(5) + v_perm_b32 v104, v34, v42, s21 + v_perm_b32 v60, v34, v42, s22 + v_perm_b32 v64, v35, v43, s21 + v_perm_b32 v108, v35, v43, s22 + v_perm_b32 v112, v36, v44, s21 + v_perm_b32 v116, v36, v44, s22 + v_perm_b32 v120, v37, v45, s21 + v_perm_b32 v124, v37, v45, s22 + s_waitcnt vmcnt(4) + v_perm_b32 v128, v10, v26, s21 + v_perm_b32 v32, v10, v26, s22 + v_perm_b32 v52, v11, v27, s21 + v_perm_b32 v132, v11, v27, s22 + v_perm_b32 v136, v12, v28, s21 + v_perm_b32 v140, v12, v28, s22 + v_perm_b32 v144, v13, v29, s21 + v_perm_b32 v148, v13, v29, s22 + s_waitcnt vmcnt(2) + v_perm_b32 v105, v14, v18, s21 + v_perm_b32 v61, v14, v18, s22 + v_perm_b32 v65, v15, v19, s21 + v_perm_b32 v109, v15, v19, s22 + v_perm_b32 v113, v16, v20, s21 + v_perm_b32 v117, v16, v20, s22 + v_perm_b32 v121, v17, v21, s21 + v_perm_b32 v125, v17, v21, s22 + s_waitcnt vmcnt(0) + v_perm_b32 v129, v2, v6, s21 + v_perm_b32 v33, v2, v6, s22 + v_perm_b32 v53, v3, v7, s21 + v_perm_b32 v133, v3, v7, s22 + v_perm_b32 v137, v4, v8, s21 + v_perm_b32 v141, v4, v8, s22 + v_perm_b32 v145, v5, v9, s21 + v_perm_b32 v149, v5, v9, s22 + ds_write_b128 v150, v[102:105] + ds_write_b128 v151, v[58:61] offset:512 + ds_write_b128 v152, v[62:65] offset:512 + ds_write_b128 v153, v[106:109] offset:512 + ds_write_b128 v154, v[110:113] offset:512 + ds_write_b128 v155, v[114:117] offset:512 + ds_write_b128 v156, v[118:121] offset:512 + ds_write_b128 v157, v[122:125] offset:512 + ds_write_b128 v150, v[126:129] offset:32768 + ds_write_b128 v151, v[30:33] offset:33280 + ds_write_b128 v152, v[50:53] offset:33280 + ds_write_b128 v153, v[130:133] offset:33280 + ds_write_b128 v154, v[134:137] offset:33280 + ds_write_b128 v155, v[138:141] offset:33280 + ds_write_b128 v156, v[142:145] offset:33280 + ds_write_b128 v157, v[146:149] offset:33280 + s_cbranch_scc1 .LBB11_8 +.LBB11_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_R + v_accvgpr_read_b32 v137, a3 + v_accvgpr_read_b32 v138, a4 + v_accvgpr_read_b32 v139, a5 + v_accvgpr_read_b32 v140, a6 + v_accvgpr_read_b32 v141, a7 + v_accvgpr_read_b32 v142, a8 + v_accvgpr_read_b32 v143, a9 + v_accvgpr_read_b32 v144, a10 + v_accvgpr_read_b32 v145, a11 + v_accvgpr_read_b32 v146, a12 + v_accvgpr_read_b32 v147, a13 + v_accvgpr_read_b32 v148, a14 + v_accvgpr_read_b32 v149, a15 + v_accvgpr_read_b32 v118, a160 + v_accvgpr_read_b32 v119, a161 + v_accvgpr_read_b32 v120, a162 + v_accvgpr_read_b32 v121, a163 + v_accvgpr_read_b32 v122, a164 + v_accvgpr_read_b32 v123, a165 + v_accvgpr_read_b32 v124, a166 + v_accvgpr_read_b32 v125, a167 + v_accvgpr_read_b32 v126, a168 + v_accvgpr_read_b32 v127, a169 + v_accvgpr_read_b32 v128, a170 + v_accvgpr_read_b32 v129, a171 + v_accvgpr_read_b32 v130, a172 + v_accvgpr_read_b32 v131, a173 + v_accvgpr_read_b32 v132, a174 + v_accvgpr_read_b32 v133, a175 + v_accvgpr_read_b32 v102, a192 + v_accvgpr_read_b32 v103, a193 + v_accvgpr_read_b32 v104, a194 + v_accvgpr_read_b32 v105, a195 + v_accvgpr_read_b32 v106, a196 + v_accvgpr_read_b32 v107, a197 + v_accvgpr_read_b32 v108, a198 + v_accvgpr_read_b32 v109, a199 + v_accvgpr_read_b32 v110, a200 + v_accvgpr_read_b32 v111, a201 + v_accvgpr_read_b32 v112, a202 + v_accvgpr_read_b32 v113, a203 + v_accvgpr_read_b32 v114, a204 + v_accvgpr_read_b32 v115, a205 + v_accvgpr_read_b32 v116, a206 + v_accvgpr_read_b32 v117, a207 + v_accvgpr_read_b32 v50, a208 + v_accvgpr_read_b32 v51, a209 + v_accvgpr_read_b32 v52, a210 + v_accvgpr_read_b32 v53, a211 + v_accvgpr_read_b32 v54, a212 + v_accvgpr_read_b32 v55, a213 + v_accvgpr_read_b32 v56, a214 + v_accvgpr_read_b32 v57, a215 + v_accvgpr_read_b32 v58, a216 + v_accvgpr_read_b32 v59, a217 + v_accvgpr_read_b32 v60, a218 + v_accvgpr_read_b32 v61, a219 + v_accvgpr_read_b32 v62, a220 + v_accvgpr_read_b32 v63, a221 + v_accvgpr_read_b32 v64, a222 + v_accvgpr_read_b32 v65, a223 + v_accvgpr_read_b32 v34, a224 + v_accvgpr_read_b32 v35, a225 + v_accvgpr_read_b32 v36, a226 + v_accvgpr_read_b32 v37, a227 + v_accvgpr_read_b32 v38, a228 + v_accvgpr_read_b32 v39, a229 + v_accvgpr_read_b32 v40, a230 + v_accvgpr_read_b32 v41, a231 + v_accvgpr_read_b32 v42, a232 + v_accvgpr_read_b32 v43, a233 + v_accvgpr_read_b32 v44, a234 + v_accvgpr_read_b32 v45, a235 + v_accvgpr_read_b32 v46, a236 + v_accvgpr_read_b32 v47, a237 + v_accvgpr_read_b32 v48, a238 + v_accvgpr_read_b32 v49, a239 + v_accvgpr_read_b32 v18, a240 + v_accvgpr_read_b32 v19, a241 + v_accvgpr_read_b32 v20, a242 + v_accvgpr_read_b32 v21, a243 + v_accvgpr_read_b32 v22, a244 + v_accvgpr_read_b32 v23, a245 + v_accvgpr_read_b32 v24, a246 + v_accvgpr_read_b32 v25, a247 + v_accvgpr_read_b32 v26, a248 + v_accvgpr_read_b32 v27, a249 + v_accvgpr_read_b32 v28, a250 + v_accvgpr_read_b32 v29, a251 + v_accvgpr_read_b32 v30, a252 + v_accvgpr_read_b32 v31, a253 + v_accvgpr_read_b32 v32, a254 + v_accvgpr_read_b32 v33, a255 + v_accvgpr_read_b32 v2, a32 + v_accvgpr_read_b32 v3, a33 + v_accvgpr_read_b32 v4, a34 + v_accvgpr_read_b32 v5, a35 + v_accvgpr_read_b32 v6, a36 + v_accvgpr_read_b32 v7, a37 + v_accvgpr_read_b32 v8, a38 + v_accvgpr_read_b32 v9, a39 + v_accvgpr_read_b32 v10, a40 + v_accvgpr_read_b32 v11, a41 + v_accvgpr_read_b32 v12, a42 + v_accvgpr_read_b32 v13, a43 + v_accvgpr_read_b32 v14, a44 + v_accvgpr_read_b32 v15, a45 + v_accvgpr_read_b32 v16, a46 + v_accvgpr_read_b32 v17, a47 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + v_accvgpr_read_b32 v136, a2 + v_accvgpr_read_b32 v135, a1 + v_accvgpr_read_b32 v134, a0 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[150:153], v100 + ds_read_b128 v[154:157], v99 offset:32768 + v_accvgpr_mov_b32 a0, a112 + v_accvgpr_mov_b32 a1, a113 + v_accvgpr_mov_b32 a2, a114 + v_accvgpr_mov_b32 a3, a115 + v_accvgpr_mov_b32 a4, a116 + v_accvgpr_mov_b32 a5, a117 + v_accvgpr_mov_b32 a6, a118 + v_accvgpr_mov_b32 a7, a119 + v_accvgpr_mov_b32 a8, a120 + v_accvgpr_mov_b32 a9, a121 + v_accvgpr_mov_b32 a10, a122 + v_accvgpr_mov_b32 a11, a123 + v_accvgpr_mov_b32 a12, a124 + v_accvgpr_mov_b32 a13, a125 + v_accvgpr_mov_b32 a14, a126 + v_accvgpr_mov_b32 a15, a127 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[0:15], v[150:151], v[154:155], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[156:157], a[0:15] + v_lshlrev_b32_e32 v66, 1, v93 + ds_read_b128 v[158:161], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v94 + v_accvgpr_mov_b32 a32, a96 + v_accvgpr_mov_b32 a33, a97 + v_accvgpr_mov_b32 a34, a98 + v_accvgpr_mov_b32 a35, a99 + v_accvgpr_mov_b32 a36, a100 + v_accvgpr_mov_b32 a37, a101 + v_accvgpr_mov_b32 a38, a102 + v_accvgpr_mov_b32 a39, a103 + v_accvgpr_mov_b32 a40, a104 + v_accvgpr_mov_b32 a41, a105 + v_accvgpr_mov_b32 a42, a106 + v_accvgpr_mov_b32 a43, a107 + v_accvgpr_mov_b32 a44, a108 + v_accvgpr_mov_b32 a45, a109 + v_accvgpr_mov_b32 a46, a110 + v_accvgpr_mov_b32 a47, a111 + ds_read_b128 v[162:165], v66 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[150:151], v[158:159], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[160:161], a[32:47] + v_lshlrev_b32_e32 v66, 1, v95 + ds_read_b128 v[166:169], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v96 + ds_read_b128 v[170:173], v66 offset:32768 + v_accvgpr_mov_b32 a127, a95 + v_accvgpr_mov_b32 a126, a94 + v_accvgpr_mov_b32 a125, a93 + v_accvgpr_mov_b32 a124, a92 + v_accvgpr_mov_b32 a123, a91 + v_accvgpr_mov_b32 a122, a90 + v_accvgpr_mov_b32 a121, a89 + v_accvgpr_mov_b32 a120, a88 + v_accvgpr_mov_b32 a119, a87 + v_accvgpr_mov_b32 a118, a86 + v_accvgpr_mov_b32 a117, a85 + v_accvgpr_mov_b32 a116, a84 + v_accvgpr_mov_b32 a115, a83 + v_accvgpr_mov_b32 a114, a82 + v_accvgpr_mov_b32 a113, a81 + v_accvgpr_mov_b32 a112, a80 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[112:127], v[150:151], v[166:167], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[152:153], v[168:169], a[112:127] + v_lshlrev_b32_e32 v66, 1, v97 + ds_read_b128 v[94:97], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v98 + ds_read_b128 v[98:101], v66 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[94:95], a[208:223] + v_lshlrev_b32_e32 v66, 1, v92 + v_mfma_f32_32x32x8_bf16 a[208:223], v[152:153], v[96:97], a[208:223] + ds_read_b128 v[150:153], v66 + v_accvgpr_mov_b32 a239, a159 + v_accvgpr_mov_b32 a238, a158 + v_accvgpr_mov_b32 a237, a157 + v_accvgpr_mov_b32 a236, a156 + v_accvgpr_mov_b32 a235, a155 + v_accvgpr_mov_b32 a234, a154 + v_accvgpr_mov_b32 a233, a153 + v_accvgpr_mov_b32 a232, a152 + v_accvgpr_mov_b32 a231, a151 + v_accvgpr_mov_b32 a230, a150 + v_accvgpr_mov_b32 a229, a149 + v_accvgpr_mov_b32 a228, a148 + v_accvgpr_mov_b32 a227, a147 + v_accvgpr_mov_b32 a226, a146 + v_accvgpr_mov_b32 a225, a145 + v_accvgpr_mov_b32 a224, a144 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[154:155], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[152:153], v[156:157], a[224:239] + v_accvgpr_mov_b32 a207, a79 + v_accvgpr_mov_b32 a206, a78 + v_accvgpr_mov_b32 a205, a77 + v_accvgpr_mov_b32 a204, a76 + v_accvgpr_mov_b32 a203, a75 + v_accvgpr_mov_b32 a202, a74 + v_accvgpr_mov_b32 a201, a73 + v_accvgpr_mov_b32 a200, a72 + v_accvgpr_mov_b32 a199, a71 + v_accvgpr_mov_b32 a198, a70 + v_accvgpr_mov_b32 a197, a69 + v_accvgpr_mov_b32 a196, a68 + v_accvgpr_mov_b32 a195, a67 + v_accvgpr_mov_b32 a194, a66 + v_accvgpr_mov_b32 a193, a65 + v_accvgpr_mov_b32 a192, a64 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[158:159], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[152:153], v[160:161], a[192:207] + v_accvgpr_write_b32 a175, v149 + v_accvgpr_write_b32 a174, v148 + v_accvgpr_write_b32 a173, v147 + v_accvgpr_write_b32 a172, v146 + v_accvgpr_write_b32 a171, v145 + v_accvgpr_write_b32 a170, v144 + v_accvgpr_write_b32 a169, v143 + v_accvgpr_write_b32 a168, v142 + v_accvgpr_write_b32 a167, v141 + v_accvgpr_write_b32 a166, v140 + v_accvgpr_write_b32 a165, v139 + v_accvgpr_write_b32 a164, v138 + v_accvgpr_write_b32 a163, v137 + v_accvgpr_write_b32 a162, v136 + v_accvgpr_write_b32 a161, v135 + v_accvgpr_write_b32 a160, v134 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[160:175], v[150:151], v[166:167], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[152:153], v[168:169], a[160:175] + v_accvgpr_write_b32 a159, v133 + v_accvgpr_write_b32 a158, v132 + v_accvgpr_write_b32 a157, v131 + v_accvgpr_write_b32 a156, v130 + v_accvgpr_write_b32 a155, v129 + v_accvgpr_write_b32 a154, v128 + v_accvgpr_write_b32 a153, v127 + v_accvgpr_write_b32 a152, v126 + v_accvgpr_write_b32 a151, v125 + v_accvgpr_write_b32 a150, v124 + v_accvgpr_write_b32 a149, v123 + v_accvgpr_write_b32 a148, v122 + v_accvgpr_write_b32 a147, v121 + v_accvgpr_write_b32 a146, v120 + v_accvgpr_write_b32 a145, v119 + v_accvgpr_write_b32 a144, v118 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[144:159], v[150:151], v[94:95], a[144:159] + v_lshlrev_b32_e32 v66, 1, v91 + v_mfma_f32_32x32x8_bf16 a[144:159], v[152:153], v[96:97], a[144:159] + ds_read_b128 v[118:121], v66 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[118:119], v[154:155], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[120:121], v[156:157], a[176:191] + v_accvgpr_write_b32 a143, v117 + v_accvgpr_write_b32 a142, v116 + v_accvgpr_write_b32 a141, v115 + v_accvgpr_write_b32 a140, v114 + v_accvgpr_write_b32 a139, v113 + v_accvgpr_write_b32 a138, v112 + v_accvgpr_write_b32 a137, v111 + v_accvgpr_write_b32 a136, v110 + v_accvgpr_write_b32 a135, v109 + v_accvgpr_write_b32 a134, v108 + v_accvgpr_write_b32 a133, v107 + v_accvgpr_write_b32 a132, v106 + v_accvgpr_write_b32 a131, v105 + v_accvgpr_write_b32 a130, v104 + v_accvgpr_write_b32 a129, v103 + v_accvgpr_write_b32 a128, v102 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[128:143], v[118:119], v[158:159], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[120:121], v[160:161], a[128:143] + v_accvgpr_write_b32 a95, v65 + v_accvgpr_write_b32 a94, v64 + v_accvgpr_write_b32 a93, v63 + v_accvgpr_write_b32 a92, v62 + v_accvgpr_write_b32 a91, v61 + v_accvgpr_write_b32 a90, v60 + v_accvgpr_write_b32 a89, v59 + v_accvgpr_write_b32 a88, v58 + v_accvgpr_write_b32 a87, v57 + v_accvgpr_write_b32 a86, v56 + v_accvgpr_write_b32 a85, v55 + v_accvgpr_write_b32 a84, v54 + v_accvgpr_write_b32 a83, v53 + v_accvgpr_write_b32 a82, v52 + v_accvgpr_write_b32 a81, v51 + v_accvgpr_write_b32 a80, v50 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[80:95], v[118:119], v[166:167], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[120:121], v[168:169], a[80:95] + v_accvgpr_write_b32 a79, v49 + v_accvgpr_write_b32 a78, v48 + v_accvgpr_write_b32 a77, v47 + v_accvgpr_write_b32 a76, v46 + v_accvgpr_write_b32 a75, v45 + v_accvgpr_write_b32 a74, v44 + v_accvgpr_write_b32 a73, v43 + v_accvgpr_write_b32 a72, v42 + v_accvgpr_write_b32 a71, v41 + v_accvgpr_write_b32 a70, v40 + v_accvgpr_write_b32 a69, v39 + v_accvgpr_write_b32 a68, v38 + v_accvgpr_write_b32 a67, v37 + v_accvgpr_write_b32 a66, v36 + v_accvgpr_write_b32 a65, v35 + v_accvgpr_write_b32 a64, v34 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[64:79], v[118:119], v[94:95], a[64:79] + v_lshlrev_b32_e32 v34, 1, v90 + v_mfma_f32_32x32x8_bf16 a[64:79], v[120:121], v[96:97], a[64:79] + ds_read_b128 v[34:37], v34 + v_accvgpr_write_b32 a111, v33 + v_accvgpr_write_b32 a110, v32 + v_accvgpr_write_b32 a109, v31 + v_accvgpr_write_b32 a108, v30 + v_accvgpr_write_b32 a107, v29 + v_accvgpr_write_b32 a106, v28 + v_accvgpr_write_b32 a105, v27 + v_accvgpr_write_b32 a104, v26 + v_accvgpr_write_b32 a103, v25 + v_accvgpr_write_b32 a102, v24 + v_accvgpr_write_b32 a101, v23 + v_accvgpr_write_b32 a100, v22 + v_accvgpr_write_b32 a99, v21 + v_accvgpr_write_b32 a98, v20 + v_accvgpr_write_b32 a97, v19 + v_accvgpr_write_b32 a96, v18 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[34:35], v[154:155], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[36:37], v[156:157], a[96:111] + v_accvgpr_write_b32 a63, v17 + v_accvgpr_write_b32 a62, v16 + v_accvgpr_write_b32 a61, v15 + v_accvgpr_write_b32 a60, v14 + v_accvgpr_write_b32 a59, v13 + v_accvgpr_write_b32 a58, v12 + v_accvgpr_write_b32 a57, v11 + v_accvgpr_write_b32 a56, v10 + v_accvgpr_write_b32 a55, v9 + v_accvgpr_write_b32 a54, v8 + v_accvgpr_write_b32 a53, v7 + v_accvgpr_write_b32 a52, v6 + v_accvgpr_write_b32 a51, v5 + v_accvgpr_write_b32 a50, v4 + v_accvgpr_write_b32 a49, v3 + v_accvgpr_write_b32 a48, v2 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[48:63], v[34:35], v[158:159], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[36:37], v[160:161], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[34:35], v[166:167], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[36:37], v[168:169], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[34:35], v[94:95], a[240:255] + v_lshlrev_b32_e32 v2, 1, v73 + v_mfma_f32_32x32x8_bf16 a[240:255], v[36:37], v[96:97], a[240:255] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v87 + ds_read_b128 v[8:11], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v74 + ds_read_b128 v[12:15], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[8:9], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[6:7], v[10:11], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[162:163], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[6:7], v[164:165], a[32:47] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[170:171], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[6:7], v[172:173], a[112:127] + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[98:99], a[208:223] + v_lshlrev_b32_e32 v2, 1, v75 + v_mfma_f32_32x32x8_bf16 a[208:223], v[6:7], v[100:101], a[208:223] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v76 + ds_read_b128 v[16:19], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[6:7], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[162:163], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[6:7], v[164:165], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[170:171], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[6:7], v[172:173], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[98:99], a[144:159] + v_lshlrev_b32_e32 v2, 1, v77 + v_mfma_f32_32x32x8_bf16 a[144:159], v[6:7], v[100:101], a[144:159] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v78 + ds_read_b128 v[20:23], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[6:7], v[10:11], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[162:163], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[6:7], v[164:165], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[170:171], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[6:7], v[172:173], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[98:99], a[64:79] + v_lshlrev_b32_e32 v2, 1, v79 + v_mfma_f32_32x32x8_bf16 a[64:79], v[6:7], v[100:101], a[64:79] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v80 + ds_read_b128 v[24:27], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[6:7], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[162:163], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[6:7], v[164:165], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[170:171], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[172:173], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[98:99], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[100:101], a[240:255] + v_lshlrev_b32_e32 v2, 1, v81 + ds_read_b128 v[4:7], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v82 + ds_read_b128 v[8:11], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[12:13], v[4:5], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[14:15], v[6:7], a[0:15] + v_lshlrev_b32_e32 v2, 1, v83 + ds_read_b128 v[28:31], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v84 + ds_read_b128 v[32:35], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[12:13], v[28:29], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[14:15], v[30:31], a[32:47] + v_lshlrev_b32_e32 v2, 1, v85 + ds_read_b128 v[36:39], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v86 + ds_read_b128 v[40:43], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[12:13], v[36:37], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[14:15], v[38:39], a[112:127] + v_lshlrev_b32_e32 v2, 1, v88 + ds_read_b128 v[44:47], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v89 + ds_read_b128 v[48:51], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[14:15], v[46:47], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[18:19], v[6:7], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[18:19], v[30:31], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[18:19], v[38:39], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[16:17], v[44:45], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[18:19], v[46:47], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[20:21], v[4:5], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[22:23], v[6:7], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[20:21], v[28:29], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[22:23], v[30:31], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[20:21], v[36:37], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[22:23], v[38:39], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[20:21], v[44:45], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[22:23], v[46:47], a[64:79] + v_mfma_f32_32x32x8_bf16 a[96:111], v[24:25], v[4:5], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[26:27], v[6:7], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[24:25], v[28:29], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[26:27], v[30:31], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[24:25], v[36:37], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[26:27], v[38:39], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[24:25], v[44:45], a[240:255] + v_lshlrev_b32_e32 v2, 1, v67 + v_mfma_f32_32x32x8_bf16 a[240:255], v[26:27], v[46:47], a[240:255] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[2:3], v[8:9], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[10:11], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[2:3], v[32:33], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[34:35], a[32:47] + v_mfma_f32_32x32x8_bf16 a[112:127], v[2:3], v[40:41], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[42:43], a[112:127] + v_mfma_f32_32x32x8_bf16 a[208:223], v[2:3], v[48:49], a[208:223] + v_lshlrev_b32_e32 v2, 1, v69 + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[50:51], a[208:223] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[34:35], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[42:43], a[160:175] + v_mfma_f32_32x32x8_bf16 a[144:159], v[2:3], v[48:49], a[144:159] + v_lshlrev_b32_e32 v2, 1, v71 + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[50:51], a[144:159] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[2:3], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[10:11], a[176:191] + v_mfma_f32_32x32x8_bf16 a[128:143], v[2:3], v[32:33], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[34:35], a[128:143] + v_mfma_f32_32x32x8_bf16 a[80:95], v[2:3], v[40:41], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[42:43], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[2:3], v[48:49], a[64:79] + v_lshlrev_b32_e32 v2, 1, v72 + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[50:51], a[64:79] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[48:63], v[2:3], v[32:33], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[34:35], a[48:63] + v_mfma_f32_32x32x8_bf16 a[16:31], v[2:3], v[40:41], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[42:43], a[16:31] + v_mfma_f32_32x32x8_bf16 a[240:255], v[2:3], v[48:49], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[50:51], a[240:255] +.LBB11_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RK + v_accvgpr_read_b32 v72, a0 + v_accvgpr_read_b32 v71, a1 + v_accvgpr_read_b32 v69, a2 + v_accvgpr_read_b32 v68, a3 + v_accvgpr_read_b32 v67, a4 + v_accvgpr_read_b32 v66, a5 + v_accvgpr_read_b32 v65, a6 + v_accvgpr_read_b32 v64, a7 + v_accvgpr_read_b32 v63, a8 + v_accvgpr_read_b32 v62, a9 + v_accvgpr_read_b32 v61, a10 + v_accvgpr_read_b32 v60, a11 + v_accvgpr_read_b32 v59, a12 + v_accvgpr_read_b32 v58, a13 + v_accvgpr_read_b32 v57, a14 + v_accvgpr_read_b32 v55, a15 + v_accvgpr_read_b32 v252, a32 + v_accvgpr_read_b32 v251, a33 + v_accvgpr_read_b32 v250, a34 + v_accvgpr_read_b32 v249, a35 + v_accvgpr_read_b32 v248, a36 + v_accvgpr_read_b32 v247, a37 + v_accvgpr_read_b32 v246, a38 + v_accvgpr_read_b32 v245, a39 + v_accvgpr_read_b32 v244, a40 + v_accvgpr_read_b32 v243, a41 + v_accvgpr_read_b32 v242, a42 + v_accvgpr_read_b32 v241, a43 + v_accvgpr_read_b32 v240, a44 + v_accvgpr_read_b32 v239, a45 + v_accvgpr_read_b32 v238, a46 + v_accvgpr_read_b32 v236, a47 + v_accvgpr_read_b32 v220, a112 + v_accvgpr_read_b32 v219, a113 + v_accvgpr_read_b32 v218, a114 + v_accvgpr_read_b32 v217, a115 + v_accvgpr_read_b32 v216, a116 + v_accvgpr_read_b32 v215, a117 + v_accvgpr_read_b32 v214, a118 + v_accvgpr_read_b32 v213, a119 + v_accvgpr_read_b32 v212, a120 + v_accvgpr_read_b32 v211, a121 + v_accvgpr_read_b32 v210, a122 + v_accvgpr_read_b32 v209, a123 + v_accvgpr_read_b32 v208, a124 + v_accvgpr_read_b32 v207, a125 + v_accvgpr_read_b32 v206, a126 + v_accvgpr_read_b32 v204, a127 + v_accvgpr_read_b32 v188, a208 + v_accvgpr_read_b32 v187, a209 + v_accvgpr_read_b32 v186, a210 + v_accvgpr_read_b32 v185, a211 + v_accvgpr_read_b32 v184, a212 + v_accvgpr_read_b32 v183, a213 + v_accvgpr_read_b32 v182, a214 + v_accvgpr_read_b32 v181, a215 + v_accvgpr_read_b32 v180, a216 + v_accvgpr_read_b32 v179, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v177, a219 + v_accvgpr_read_b32 v176, a220 + v_accvgpr_read_b32 v175, a221 + v_accvgpr_read_b32 v174, a222 + v_accvgpr_read_b32 v172, a223 + v_accvgpr_read_b32 v56, a224 + v_accvgpr_read_b32 v54, a225 + v_accvgpr_read_b32 v53, a226 + v_accvgpr_read_b32 v52, a227 + v_accvgpr_read_b32 v51, a228 + v_accvgpr_read_b32 v50, a229 + v_accvgpr_read_b32 v49, a230 + v_accvgpr_read_b32 v48, a231 + v_accvgpr_read_b32 v47, a232 + v_accvgpr_read_b32 v46, a233 + v_accvgpr_read_b32 v45, a234 + v_accvgpr_read_b32 v44, a235 + v_accvgpr_read_b32 v70, a236 + v_accvgpr_read_b32 v255, a237 + v_accvgpr_read_b32 v254, a238 + v_accvgpr_read_b32 v253, a239 + v_accvgpr_read_b32 v237, a192 + v_accvgpr_read_b32 v235, a193 + v_accvgpr_read_b32 v234, a194 + v_accvgpr_read_b32 v233, a195 + v_accvgpr_read_b32 v232, a196 + v_accvgpr_read_b32 v231, a197 + v_accvgpr_read_b32 v230, a198 + v_accvgpr_read_b32 v229, a199 + v_accvgpr_read_b32 v228, a200 + v_accvgpr_read_b32 v227, a201 + v_accvgpr_read_b32 v226, a202 + v_accvgpr_read_b32 v225, a203 + v_accvgpr_read_b32 v224, a204 + v_accvgpr_read_b32 v223, a205 + v_accvgpr_read_b32 v222, a206 + v_accvgpr_read_b32 v221, a207 + v_accvgpr_read_b32 v205, a160 + v_accvgpr_read_b32 v203, a161 + v_accvgpr_read_b32 v202, a162 + v_accvgpr_read_b32 v201, a163 + v_accvgpr_read_b32 v200, a164 + v_accvgpr_read_b32 v199, a165 + v_accvgpr_read_b32 v198, a166 + v_accvgpr_read_b32 v197, a167 + v_accvgpr_read_b32 v196, a168 + v_accvgpr_read_b32 v195, a169 + v_accvgpr_read_b32 v194, a170 + v_accvgpr_read_b32 v193, a171 + v_accvgpr_read_b32 v192, a172 + v_accvgpr_read_b32 v191, a173 + v_accvgpr_read_b32 v190, a174 + v_accvgpr_read_b32 v189, a175 + v_accvgpr_read_b32 v173, a144 + v_accvgpr_read_b32 v171, a145 + v_accvgpr_read_b32 v170, a146 + v_accvgpr_read_b32 v169, a147 + v_accvgpr_read_b32 v168, a148 + v_accvgpr_read_b32 v167, a149 + v_accvgpr_read_b32 v166, a150 + v_accvgpr_read_b32 v165, a151 + v_accvgpr_read_b32 v164, a152 + v_accvgpr_read_b32 v163, a153 + v_accvgpr_read_b32 v162, a154 + v_accvgpr_read_b32 v161, a155 + v_accvgpr_read_b32 v160, a156 + v_accvgpr_read_b32 v159, a157 + v_accvgpr_read_b32 v158, a158 + v_accvgpr_read_b32 v157, a159 + v_accvgpr_mov_b32 a47, a176 + v_accvgpr_mov_b32 a46, a177 + v_accvgpr_mov_b32 a45, a178 + v_accvgpr_mov_b32 a44, a179 + v_accvgpr_mov_b32 a43, a180 + v_accvgpr_mov_b32 a42, a181 + v_accvgpr_mov_b32 a41, a182 + v_accvgpr_mov_b32 a40, a183 + v_accvgpr_mov_b32 a39, a184 + v_accvgpr_mov_b32 a38, a185 + v_accvgpr_mov_b32 a37, a186 + v_accvgpr_mov_b32 a36, a187 + v_accvgpr_mov_b32 a35, a188 + v_accvgpr_mov_b32 a34, a189 + v_accvgpr_mov_b32 a33, a190 + v_accvgpr_mov_b32 a15, a191 + v_accvgpr_read_b32 v108, a128 + v_accvgpr_read_b32 v107, a129 + v_accvgpr_read_b32 v106, a130 + v_accvgpr_read_b32 v105, a131 + v_accvgpr_read_b32 v104, a132 + v_accvgpr_read_b32 v103, a133 + v_accvgpr_read_b32 v102, a134 + v_accvgpr_read_b32 v101, a135 + v_accvgpr_read_b32 v100, a136 + v_accvgpr_read_b32 v99, a137 + v_accvgpr_read_b32 v98, a138 + v_accvgpr_read_b32 v97, a139 + v_accvgpr_read_b32 v96, a140 + v_accvgpr_read_b32 v95, a141 + v_accvgpr_read_b32 v94, a142 + v_accvgpr_read_b32 v92, a143 + v_accvgpr_read_b32 v140, a80 + v_accvgpr_read_b32 v139, a81 + v_accvgpr_read_b32 v138, a82 + v_accvgpr_read_b32 v137, a83 + v_accvgpr_read_b32 v136, a84 + v_accvgpr_read_b32 v135, a85 + v_accvgpr_read_b32 v134, a86 + v_accvgpr_read_b32 v133, a87 + v_accvgpr_read_b32 v132, a88 + v_accvgpr_read_b32 v131, a89 + v_accvgpr_read_b32 v130, a90 + v_accvgpr_read_b32 v129, a91 + v_accvgpr_read_b32 v128, a92 + v_accvgpr_read_b32 v127, a93 + v_accvgpr_read_b32 v126, a94 + v_accvgpr_read_b32 v124, a95 + v_accvgpr_read_b32 v156, a64 + v_accvgpr_read_b32 v155, a65 + v_accvgpr_read_b32 v154, a66 + v_accvgpr_read_b32 v153, a67 + v_accvgpr_read_b32 v152, a68 + v_accvgpr_read_b32 v151, a69 + v_accvgpr_read_b32 v150, a70 + v_accvgpr_read_b32 v149, a71 + v_accvgpr_read_b32 v148, a72 + v_accvgpr_read_b32 v147, a73 + v_accvgpr_read_b32 v146, a74 + v_accvgpr_read_b32 v145, a75 + v_accvgpr_read_b32 v144, a76 + v_accvgpr_read_b32 v143, a77 + v_accvgpr_read_b32 v142, a78 + v_accvgpr_read_b32 v141, a79 + v_accvgpr_mov_b32 a32, a96 + v_accvgpr_mov_b32 a14, a97 + v_accvgpr_mov_b32 a13, a98 + v_accvgpr_mov_b32 a12, a99 + v_accvgpr_mov_b32 a11, a100 + v_accvgpr_mov_b32 a10, a101 + v_accvgpr_mov_b32 a9, a102 + v_accvgpr_mov_b32 a8, a103 + v_accvgpr_mov_b32 a7, a104 + v_accvgpr_mov_b32 a6, a105 + v_accvgpr_mov_b32 a5, a106 + v_accvgpr_mov_b32 a4, a107 + v_accvgpr_mov_b32 a3, a108 + v_accvgpr_mov_b32 a2, a109 + v_accvgpr_mov_b32 a1, a110 + v_accvgpr_read_b32 v85, a111 + v_accvgpr_read_b32 v93, a48 + v_accvgpr_read_b32 v91, a49 + v_accvgpr_read_b32 v90, a50 + v_accvgpr_read_b32 v89, a51 + v_accvgpr_read_b32 v88, a52 + v_accvgpr_read_b32 v87, a53 + v_accvgpr_mov_b32 a64, a54 + v_accvgpr_mov_b32 a54, a56 + v_accvgpr_mov_b32 a53, a57 + v_accvgpr_mov_b32 a52, a58 + v_accvgpr_mov_b32 a51, a59 + v_accvgpr_mov_b32 a50, a60 + v_accvgpr_mov_b32 a49, a61 + v_accvgpr_read_b32 v86, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v125, a16 + v_accvgpr_read_b32 v123, a17 + v_accvgpr_read_b32 v122, a18 + v_accvgpr_read_b32 v121, a19 + v_accvgpr_read_b32 v120, a20 + v_accvgpr_read_b32 v119, a21 + v_accvgpr_read_b32 v118, a22 + v_accvgpr_read_b32 v117, a23 + v_accvgpr_read_b32 v116, a24 + v_accvgpr_read_b32 v115, a25 + v_accvgpr_read_b32 v114, a26 + v_accvgpr_read_b32 v113, a27 + v_accvgpr_read_b32 v112, a28 + v_accvgpr_read_b32 v111, a29 + v_accvgpr_read_b32 v110, a30 + v_accvgpr_read_b32 v109, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mov_b64 s[2:3], -1 + s_cmp_lg_u32 s17, 1 + s_cbranch_scc1 .LBB11_13 +; %bb.11: ; %Flow1281 + s_and_b64 vcc, exec, s[2:3] + s_cbranch_vccnz .LBB11_2190 +.LBB11_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSD_8RowMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB11_13: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.14: + v_bfe_u32 v18, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v72, v18, s7 +; %bb.15: ; %Flow1024 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.16: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v72, vcc +; %bb.17: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i305.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.18: + v_bfe_u32 v19, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v19, v71, v19, s7 +; %bb.19: ; %Flow1023 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.20: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v71, vcc +; %bb.21: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i308.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v69 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.22: + v_bfe_u32 v20, v69, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v69, v20, s7 +; %bb.23: ; %Flow1022 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.24: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v69 + v_cmp_eq_u32_sdwa vcc, v69, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v69, vcc +; %bb.25: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i311.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.26: + v_bfe_u32 v21, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v68, v21, s7 +; %bb.27: ; %Flow1021 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.28: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v68, vcc +; %bb.29: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i314.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.30: + v_bfe_u32 v22, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v67, v22, s7 +; %bb.31: ; %Flow1020 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.32: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v67, vcc +; %bb.33: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i317.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.34: + v_bfe_u32 v23, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v66, v23, s7 +; %bb.35: ; %Flow1019 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.36: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v66, vcc +; %bb.37: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i320.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.38: + v_bfe_u32 v24, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v65, v24, s7 +; %bb.39: ; %Flow1018 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.40: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v65, vcc +; %bb.41: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i323.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.42: + v_bfe_u32 v25, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v64, v25, s7 +; %bb.43: ; %Flow1017 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.44: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v64, vcc +; %bb.45: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i326.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.46: + v_bfe_u32 v26, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v63, v26, s7 +; %bb.47: ; %Flow1016 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.48: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v63, vcc +; %bb.49: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i329.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.50: + v_bfe_u32 v27, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v62, v27, s7 +; %bb.51: ; %Flow1015 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.52: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v62, vcc +; %bb.53: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i332.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.54: + v_bfe_u32 v28, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v61, v28, s7 +; %bb.55: ; %Flow1014 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.56: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v61, vcc +; %bb.57: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i335.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.58: + v_bfe_u32 v29, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v60, v29, s7 +; %bb.59: ; %Flow1013 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.60: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v60, vcc +; %bb.61: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i338.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.62: + v_bfe_u32 v30, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v59, v30, s7 +; %bb.63: ; %Flow1012 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.64: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v59, vcc +; %bb.65: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i341.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.66: + v_bfe_u32 v31, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v58, v31, s7 +; %bb.67: ; %Flow1011 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.68: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v58, vcc +; %bb.69: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i344.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.70: + v_bfe_u32 v32, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v57, v32, s7 +; %bb.71: ; %Flow1010 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.72: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v57, vcc +; %bb.73: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i347.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.74: + v_bfe_u32 v33, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v55, v33, s7 +; %bb.75: ; %Flow1009 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.76: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v55, vcc +; %bb.77: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i350.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.78: + v_bfe_u32 v34, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v56, v34, s7 +; %bb.79: ; %Flow1008 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.80: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v56, vcc +; %bb.81: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i353.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.82: + v_bfe_u32 v35, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v54, v35, s7 +; %bb.83: ; %Flow1007 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.84: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v54, vcc +; %bb.85: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i356.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.86: + v_bfe_u32 v36, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v53, v36, s7 +; %bb.87: ; %Flow1006 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.88: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v53, vcc +; %bb.89: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i359.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.90: + v_bfe_u32 v37, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v52, v37, s7 +; %bb.91: ; %Flow1005 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.92: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v52, vcc +; %bb.93: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i362.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.94: + v_bfe_u32 v38, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v51, v38, s7 +; %bb.95: ; %Flow1004 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.96: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v51, vcc +; %bb.97: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i365.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.98: + v_bfe_u32 v39, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v50, v39, s7 +; %bb.99: ; %Flow1003 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.100: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v50, vcc +; %bb.101: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i368.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.102: + v_bfe_u32 v40, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v49, v40, s7 +; %bb.103: ; %Flow1002 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.104: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v49, vcc +; %bb.105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i371.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.106: + v_bfe_u32 v41, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v48, v41, s7 +; %bb.107: ; %Flow1001 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.108: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v48, vcc +; %bb.109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i374.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.110: + v_bfe_u32 v42, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v47, v42, s7 +; %bb.111: ; %Flow1000 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.112: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v47, vcc +; %bb.113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i377.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.114: + v_bfe_u32 v43, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v46, v43, s7 +; %bb.115: ; %Flow999 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.116: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v73, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v73, v46, vcc +; %bb.117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i380.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.118: + v_bfe_u32 v73, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v74, v45, v73, s7 +; %bb.119: ; %Flow998 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.120: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v74, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v45, vcc +; %bb.121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i383.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr75 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.122: + v_bfe_u32 v73, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v75, v44, v73, s7 +; %bb.123: ; %Flow997 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.124: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v75, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v75, v75, v44, vcc +; %bb.125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i386.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.126: + v_bfe_u32 v73, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v76, v70, v73, s7 +; %bb.127: ; %Flow996 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.128: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v76, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v70, vcc +; %bb.129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i389.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.130: + v_bfe_u32 v73, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v77, v255, v73, s7 +; %bb.131: ; %Flow995 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.132: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v77, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v255, vcc +; %bb.133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i392.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.134: + v_bfe_u32 v73, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v78, v254, v73, s7 +; %bb.135: ; %Flow994 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.136: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v78, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v254, vcc +; %bb.137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i395.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v73, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v73 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.138: + v_bfe_u32 v73, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v79, v253, v73, s7 +; %bb.139: ; %Flow993 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.140: + v_mov_b32_e32 v73, 0 + v_or_b32_e32 v79, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v73 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v253, vcc +; %bb.141: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1ELi2E + s_or_b64 exec, exec, s[2:3] + v_and_b32_e32 v73, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v80, 3, v1 + v_and_or_b32 v80, v80, 12, s2 + v_lshlrev_b32_e32 v80, 7, v80 + v_and_b32_e32 v81, 7, v1 + v_lshl_or_b32 v80, v81, 1, v80 + v_lshlrev_b32_e32 v73, 1, v73 + s_and_b32 s2, s6, 64 + v_or3_b32 v73, v80, v73, s2 + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v38 offset:9216 + ds_write_b16_d16_hi v73, v39 offset:9344 + ds_write_b16_d16_hi v73, v40 offset:9472 + ds_write_b16_d16_hi v73, v41 offset:9600 + ds_write_b16_d16_hi v73, v42 offset:10240 + ds_write_b16_d16_hi v73, v43 offset:10368 + ds_write_b16_d16_hi v73, v74 offset:10496 + ds_write_b16_d16_hi v73, v75 offset:10624 + ds_write_b16_d16_hi v73, v76 offset:11264 + ds_write_b16_d16_hi v73, v77 offset:11392 + ds_write_b16_d16_hi v73, v78 offset:11520 + ds_write_b16_d16_hi v73, v79 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v75, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v18, 1, v1 + v_and_b32_e32 v74, 60, v18 + v_add_u32_e32 v18, s2, v74 + v_add_u32_e32 v19, s18, v18 + v_or_b32_e32 v38, s19, v75 + v_mad_u64_u32 v[40:41], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[42:43], v[40:41], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off + v_lshlrev_b32_e32 v18, 7, v18 + v_lshl_or_b32 v18, v75, 1, v18 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v76, 0 + s_branch .LBB11_143 +.LBB11_142: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v79, v35, s10 + v_perm_b32 v34, v77, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_159 +.LBB11_143: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.144: ; in Loop: Header=BB11_143 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.145: ; %Flow992 + ; in Loop: Header=BB11_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.146: ; in Loop: Header=BB11_143 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.147: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v77, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.148: ; in Loop: Header=BB11_143 Depth=1 + v_bfe_u32 v77, v35, 16, 1 + v_add3_u32 v77, v35, v77, s9 + ; implicit-def: $vgpr35 +; %bb.149: ; %Flow991 + ; in Loop: Header=BB11_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.150: ; in Loop: Header=BB11_143 Depth=1 + v_or_b32_e32 v77, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v35, vcc +; %bb.151: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v78, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.152: ; in Loop: Header=BB11_143 Depth=1 + v_bfe_u32 v35, v78, 16, 1 + v_add3_u32 v35, v78, v35, s9 + ; implicit-def: $vgpr78 +; %bb.153: ; %Flow990 + ; in Loop: Header=BB11_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.154: ; in Loop: Header=BB11_143 Depth=1 + v_or_b32_e32 v35, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v78, vcc +; %bb.155: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v37 + v_add_f32_e32 v78, v31, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.156: ; in Loop: Header=BB11_143 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.157: ; %Flow989 + ; in Loop: Header=BB11_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_142 +; %bb.158: ; in Loop: Header=BB11_143 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB11_142 +.LBB11_159: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB11_161 +.LBB11_160: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v77, v33, s10 + v_perm_b32 v32, v41, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_177 +.LBB11_161: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.162: ; in Loop: Header=BB11_161 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.163: ; %Flow988 + ; in Loop: Header=BB11_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.164: ; in Loop: Header=BB11_161 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.165: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.166: ; in Loop: Header=BB11_161 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s9 + ; implicit-def: $vgpr33 +; %bb.167: ; %Flow987 + ; in Loop: Header=BB11_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.168: ; in Loop: Header=BB11_161 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.169: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v76, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.170: ; in Loop: Header=BB11_161 Depth=1 + v_bfe_u32 v33, v76, 16, 1 + v_add3_u32 v33, v76, v33, s9 + ; implicit-def: $vgpr76 +; %bb.171: ; %Flow986 + ; in Loop: Header=BB11_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.172: ; in Loop: Header=BB11_161 Depth=1 + v_or_b32_e32 v33, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v76, vcc +; %bb.173: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v76, 0xffff0000, v35 + v_add_f32_e32 v76, v37, v76 + v_and_b32_e32 v77, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.174: ; in Loop: Header=BB11_161 Depth=1 + v_bfe_u32 v77, v76, 16, 1 + v_add3_u32 v77, v76, v77, s9 + ; implicit-def: $vgpr76 +; %bb.175: ; %Flow985 + ; in Loop: Header=BB11_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_160 +; %bb.176: ; in Loop: Header=BB11_161 Depth=1 + v_or_b32_e32 v77, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v76, vcc + s_branch .LBB11_160 +.LBB11_177: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_di + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v40 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB11_179 +.LBB11_178: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s10 + v_perm_b32 v30, v41, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_195 +.LBB11_179: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.180: ; in Loop: Header=BB11_179 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.181: ; %Flow984 + ; in Loop: Header=BB11_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.182: ; in Loop: Header=BB11_179 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.183: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.184: ; in Loop: Header=BB11_179 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s9 + ; implicit-def: $vgpr31 +; %bb.185: ; %Flow983 + ; in Loop: Header=BB11_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.186: ; in Loop: Header=BB11_179 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.187: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.188: ; in Loop: Header=BB11_179 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s9 + ; implicit-def: $vgpr42 +; %bb.189: ; %Flow982 + ; in Loop: Header=BB11_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.190: ; in Loop: Header=BB11_179 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.191: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.192: ; in Loop: Header=BB11_179 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s9 + ; implicit-def: $vgpr42 +; %bb.193: ; %Flow981 + ; in Loop: Header=BB11_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_178 +; %bb.194: ; in Loop: Header=BB11_179 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB11_178 +.LBB11_195: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_197 +.LBB11_196: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s10 + v_perm_b32 v28, v39, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_213 +.LBB11_197: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.198: ; in Loop: Header=BB11_197 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.199: ; %Flow980 + ; in Loop: Header=BB11_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.200: ; in Loop: Header=BB11_197 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.201: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.202: ; in Loop: Header=BB11_197 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s9 + ; implicit-def: $vgpr29 +; %bb.203: ; %Flow979 + ; in Loop: Header=BB11_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.204: ; in Loop: Header=BB11_197 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.205: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.206: ; in Loop: Header=BB11_197 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s9 + ; implicit-def: $vgpr40 +; %bb.207: ; %Flow978 + ; in Loop: Header=BB11_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.208: ; in Loop: Header=BB11_197 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.209: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.210: ; in Loop: Header=BB11_197 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s9 + ; implicit-def: $vgpr40 +; %bb.211: ; %Flow977 + ; in Loop: Header=BB11_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_196 +; %bb.212: ; in Loop: Header=BB11_197 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB11_196 +.LBB11_213: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_65 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_215 +.LBB11_214: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_231 +.LBB11_215: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.216: ; in Loop: Header=BB11_215 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.217: ; %Flow976 + ; in Loop: Header=BB11_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.218: ; in Loop: Header=BB11_215 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.219: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.220: ; in Loop: Header=BB11_215 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.221: ; %Flow975 + ; in Loop: Header=BB11_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.222: ; in Loop: Header=BB11_215 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.223: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.224: ; in Loop: Header=BB11_215 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.225: ; %Flow974 + ; in Loop: Header=BB11_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.226: ; in Loop: Header=BB11_215 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.227: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.228: ; in Loop: Header=BB11_215 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s9 + ; implicit-def: $vgpr37 +; %bb.229: ; %Flow973 + ; in Loop: Header=BB11_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_214 +; %bb.230: ; in Loop: Header=BB11_215 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB11_214 +.LBB11_231: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_233 +.LBB11_232: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_249 +.LBB11_233: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.234: ; in Loop: Header=BB11_233 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.235: ; %Flow972 + ; in Loop: Header=BB11_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.236: ; in Loop: Header=BB11_233 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.237: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.238: ; in Loop: Header=BB11_233 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.239: ; %Flow971 + ; in Loop: Header=BB11_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.240: ; in Loop: Header=BB11_233 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.241: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.242: ; in Loop: Header=BB11_233 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.243: ; %Flow970 + ; in Loop: Header=BB11_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.244: ; in Loop: Header=BB11_233 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.245: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.246: ; in Loop: Header=BB11_233 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.247: ; %Flow969 + ; in Loop: Header=BB11_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_232 +; %bb.248: ; in Loop: Header=BB11_233 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_232 +.LBB11_249: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile130 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_251 +.LBB11_250: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_267 +.LBB11_251: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.252: ; in Loop: Header=BB11_251 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.253: ; %Flow968 + ; in Loop: Header=BB11_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.254: ; in Loop: Header=BB11_251 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.255: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.256: ; in Loop: Header=BB11_251 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.257: ; %Flow967 + ; in Loop: Header=BB11_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.258: ; in Loop: Header=BB11_251 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.259: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.260: ; in Loop: Header=BB11_251 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.261: ; %Flow966 + ; in Loop: Header=BB11_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.262: ; in Loop: Header=BB11_251 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.263: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.264: ; in Loop: Header=BB11_251 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.265: ; %Flow965 + ; in Loop: Header=BB11_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_250 +; %bb.266: ; in Loop: Header=BB11_251 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_250 +.LBB11_267: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_269 +.LBB11_268: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_285 +.LBB11_269: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.270: ; in Loop: Header=BB11_269 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.271: ; %Flow964 + ; in Loop: Header=BB11_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.272: ; in Loop: Header=BB11_269 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.273: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.274: ; in Loop: Header=BB11_269 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.275: ; %Flow963 + ; in Loop: Header=BB11_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.276: ; in Loop: Header=BB11_269 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.277: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.278: ; in Loop: Header=BB11_269 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.279: ; %Flow962 + ; in Loop: Header=BB11_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.280: ; in Loop: Header=BB11_269 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.281: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB11_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.282: ; in Loop: Header=BB11_269 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.283: ; %Flow961 + ; in Loop: Header=BB11_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_268 +; %bb.284: ; in Loop: Header=BB11_269 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_268 +.LBB11_285: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.286: + v_bfe_u32 v18, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v252, v18, s6 +; %bb.287: ; %Flow960 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.288: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v252, vcc +; %bb.289: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i438.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.290: + v_bfe_u32 v19, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v251, v19, s6 +; %bb.291: ; %Flow959 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.292: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v251, vcc +; %bb.293: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i441.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.294: + v_bfe_u32 v20, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v250, v20, s6 +; %bb.295: ; %Flow958 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.296: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v250, vcc +; %bb.297: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i444.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.298: + v_bfe_u32 v21, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v249, v21, s6 +; %bb.299: ; %Flow957 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.300: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v249, vcc +; %bb.301: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i447.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.302: + v_bfe_u32 v22, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v248, v22, s6 +; %bb.303: ; %Flow956 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.304: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v248, vcc +; %bb.305: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i450.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.306: + v_bfe_u32 v23, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v247, v23, s6 +; %bb.307: ; %Flow955 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.308: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v247, vcc +; %bb.309: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i453.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.310: + v_bfe_u32 v24, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v246, v24, s6 +; %bb.311: ; %Flow954 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.312: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v246, vcc +; %bb.313: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i456.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.314: + v_bfe_u32 v25, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v245, v25, s6 +; %bb.315: ; %Flow953 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.316: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v245, vcc +; %bb.317: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i459.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.318: + v_bfe_u32 v26, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v244, v26, s6 +; %bb.319: ; %Flow952 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.320: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v244, vcc +; %bb.321: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i462.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.322: + v_bfe_u32 v27, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v243, v27, s6 +; %bb.323: ; %Flow951 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.324: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v243, vcc +; %bb.325: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i465.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.326: + v_bfe_u32 v28, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v242, v28, s6 +; %bb.327: ; %Flow950 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.328: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v242, vcc +; %bb.329: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i468.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.330: + v_bfe_u32 v29, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v241, v29, s6 +; %bb.331: ; %Flow949 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.332: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v241, vcc +; %bb.333: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i471.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.334: + v_bfe_u32 v30, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v240, v30, s6 +; %bb.335: ; %Flow948 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.336: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v240, vcc +; %bb.337: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i474.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.338: + v_bfe_u32 v31, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v239, v31, s6 +; %bb.339: ; %Flow947 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.340: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v239, vcc +; %bb.341: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i477.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.342: + v_bfe_u32 v32, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v238, v32, s6 +; %bb.343: ; %Flow946 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.344: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v238, vcc +; %bb.345: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i480.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.346: + v_bfe_u32 v33, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v236, v33, s6 +; %bb.347: ; %Flow945 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.348: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v236, vcc +; %bb.349: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i483.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.350: + v_bfe_u32 v34, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v237, v34, s6 +; %bb.351: ; %Flow944 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.352: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v237, vcc +; %bb.353: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i486.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.354: + v_bfe_u32 v35, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v235, v35, s6 +; %bb.355: ; %Flow943 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.356: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v235, vcc +; %bb.357: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i489.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.358: + v_bfe_u32 v36, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v234, v36, s6 +; %bb.359: ; %Flow942 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.360: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v234, vcc +; %bb.361: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i492.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.362: + v_bfe_u32 v37, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v233, v37, s6 +; %bb.363: ; %Flow941 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.364: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v39, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v233, vcc +; %bb.365: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i495.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.366: + v_bfe_u32 v39, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v232, v39, s6 +; %bb.367: ; %Flow940 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.368: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v232, vcc +; %bb.369: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i498.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.370: + v_bfe_u32 v40, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v231, v40, s6 +; %bb.371: ; %Flow939 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.372: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v231, vcc +; %bb.373: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i501.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.374: + v_bfe_u32 v41, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v230, v41, s6 +; %bb.375: ; %Flow938 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.376: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v230, vcc +; %bb.377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i504.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.378: + v_bfe_u32 v42, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v229, v42, s6 +; %bb.379: ; %Flow937 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.380: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v229, vcc +; %bb.381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i507.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.382: + v_bfe_u32 v43, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v228, v43, s6 +; %bb.383: ; %Flow936 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.384: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v76, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v228, vcc +; %bb.385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i510.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v76, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.386: + v_bfe_u32 v76, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v227, v76, s6 +; %bb.387: ; %Flow935 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.388: + v_mov_b32_e32 v76, 0 + v_or_b32_e32 v77, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v227, vcc +; %bb.389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i513.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.390: + v_bfe_u32 v77, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v226, v77, s6 +; %bb.391: ; %Flow934 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.392: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v226, vcc +; %bb.393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i516.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.394: + v_bfe_u32 v78, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v225, v78, s6 +; %bb.395: ; %Flow933 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.396: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v225, vcc +; %bb.397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i519.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.398: + v_bfe_u32 v79, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v224, v79, s6 +; %bb.399: ; %Flow932 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.400: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v224, vcc +; %bb.401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i522.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.402: + v_bfe_u32 v80, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v223, v80, s6 +; %bb.403: ; %Flow931 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.404: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v223, vcc +; %bb.405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i525.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.406: + v_bfe_u32 v81, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v222, v81, s6 +; %bb.407: ; %Flow930 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.408: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v222, vcc +; %bb.409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i528.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.410: + v_bfe_u32 v82, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v221, v82, s6 +; %bb.411: ; %Flow929 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.412: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v221, vcc +; %bb.413: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL159 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v39 offset:9216 + ds_write_b16_d16_hi v73, v40 offset:9344 + ds_write_b16_d16_hi v73, v41 offset:9472 + ds_write_b16_d16_hi v73, v42 offset:9600 + ds_write_b16_d16_hi v73, v43 offset:10240 + ds_write_b16_d16_hi v73, v76 offset:10368 + ds_write_b16_d16_hi v73, v77 offset:10496 + ds_write_b16_d16_hi v73, v78 offset:10624 + ds_write_b16_d16_hi v73, v79 offset:11264 + ds_write_b16_d16_hi v73, v80 offset:11392 + ds_write_b16_d16_hi v73, v81 offset:11520 + ds_write_b16_d16_hi v73, v82 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshlrev_b32_e32 v75, 1, v75 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v76, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB11_415 +.LBB11_414: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i222.i.i.i.i.i + ; in Loop: Header=BB11_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_431 +.LBB11_415: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.416: ; in Loop: Header=BB11_415 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.417: ; %Flow928 + ; in Loop: Header=BB11_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.418: ; in Loop: Header=BB11_415 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.419: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i213.i.i.i.i.i + ; in Loop: Header=BB11_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.420: ; in Loop: Header=BB11_415 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.421: ; %Flow927 + ; in Loop: Header=BB11_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.422: ; in Loop: Header=BB11_415 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.423: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i216.i.i.i.i.i + ; in Loop: Header=BB11_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v76, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.424: ; in Loop: Header=BB11_415 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.425: ; %Flow926 + ; in Loop: Header=BB11_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.426: ; in Loop: Header=BB11_415 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.427: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i219.i.i.i.i.i + ; in Loop: Header=BB11_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.428: ; in Loop: Header=BB11_415 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.429: ; %Flow925 + ; in Loop: Header=BB11_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_414 +; %bb.430: ; in Loop: Header=BB11_415 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB11_414 +.LBB11_431: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i225.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_433 +.LBB11_432: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i238.i.i.i.i.i + ; in Loop: Header=BB11_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v76, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_449 +.LBB11_433: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.434: ; in Loop: Header=BB11_433 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.435: ; %Flow924 + ; in Loop: Header=BB11_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.436: ; in Loop: Header=BB11_433 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.437: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i229.i.i.i.i.i + ; in Loop: Header=BB11_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v76, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.438: ; in Loop: Header=BB11_433 Depth=1 + v_bfe_u32 v76, v33, 16, 1 + v_add3_u32 v76, v33, v76, s9 + ; implicit-def: $vgpr33 +; %bb.439: ; %Flow923 + ; in Loop: Header=BB11_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.440: ; in Loop: Header=BB11_433 Depth=1 + v_or_b32_e32 v76, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v33, vcc +; %bb.441: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i232.i.i.i.i.i + ; in Loop: Header=BB11_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.442: ; in Loop: Header=BB11_433 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.443: ; %Flow922 + ; in Loop: Header=BB11_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.444: ; in Loop: Header=BB11_433 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.445: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i235.i.i.i.i.i + ; in Loop: Header=BB11_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.446: ; in Loop: Header=BB11_433 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.447: ; %Flow921 + ; in Loop: Header=BB11_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_432 +; %bb.448: ; in Loop: Header=BB11_433 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB11_432 +.LBB11_449: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile242 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 64, v38 + v_accvgpr_write_b32 a16, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_451 +.LBB11_450: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i255.i.i.i.i.i + ; in Loop: Header=BB11_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v76, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_467 +.LBB11_451: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.452: ; in Loop: Header=BB11_451 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.453: ; %Flow920 + ; in Loop: Header=BB11_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.454: ; in Loop: Header=BB11_451 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.455: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i246.i.i.i.i.i + ; in Loop: Header=BB11_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.456: ; in Loop: Header=BB11_451 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.457: ; %Flow919 + ; in Loop: Header=BB11_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.458: ; in Loop: Header=BB11_451 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.459: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i249.i.i.i.i.i + ; in Loop: Header=BB11_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.460: ; in Loop: Header=BB11_451 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.461: ; %Flow918 + ; in Loop: Header=BB11_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.462: ; in Loop: Header=BB11_451 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.463: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i252.i.i.i.i.i + ; in Loop: Header=BB11_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v76, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.464: ; in Loop: Header=BB11_451 Depth=1 + v_bfe_u32 v76, v43, 16, 1 + v_add3_u32 v76, v43, v76, s9 + ; implicit-def: $vgpr43 +; %bb.465: ; %Flow917 + ; in Loop: Header=BB11_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_450 +; %bb.466: ; in Loop: Header=BB11_451 Depth=1 + v_or_b32_e32 v76, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v43, vcc + s_branch .LBB11_450 +.LBB11_467: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i258.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_469 +.LBB11_468: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i271.i.i.i.i.i + ; in Loop: Header=BB11_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_485 +.LBB11_469: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.470: ; in Loop: Header=BB11_469 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.471: ; %Flow916 + ; in Loop: Header=BB11_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.472: ; in Loop: Header=BB11_469 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.473: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i262.i.i.i.i.i + ; in Loop: Header=BB11_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.474: ; in Loop: Header=BB11_469 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.475: ; %Flow915 + ; in Loop: Header=BB11_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.476: ; in Loop: Header=BB11_469 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.477: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i265.i.i.i.i.i + ; in Loop: Header=BB11_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.478: ; in Loop: Header=BB11_469 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.479: ; %Flow914 + ; in Loop: Header=BB11_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.480: ; in Loop: Header=BB11_469 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.481: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i268.i.i.i.i.i + ; in Loop: Header=BB11_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.482: ; in Loop: Header=BB11_469 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.483: ; %Flow913 + ; in Loop: Header=BB11_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_468 +; %bb.484: ; in Loop: Header=BB11_469 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_468 +.LBB11_485: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile275 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_487 +.LBB11_486: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i288.i.i.i.i.i + ; in Loop: Header=BB11_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_503 +.LBB11_487: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.488: ; in Loop: Header=BB11_487 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.489: ; %Flow912 + ; in Loop: Header=BB11_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.490: ; in Loop: Header=BB11_487 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.491: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i279.i.i.i.i.i + ; in Loop: Header=BB11_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.492: ; in Loop: Header=BB11_487 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.493: ; %Flow911 + ; in Loop: Header=BB11_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.494: ; in Loop: Header=BB11_487 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.495: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i282.i.i.i.i.i + ; in Loop: Header=BB11_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.496: ; in Loop: Header=BB11_487 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.497: ; %Flow910 + ; in Loop: Header=BB11_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.498: ; in Loop: Header=BB11_487 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.499: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i285.i.i.i.i.i + ; in Loop: Header=BB11_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.500: ; in Loop: Header=BB11_487 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.501: ; %Flow909 + ; in Loop: Header=BB11_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_486 +; %bb.502: ; in Loop: Header=BB11_487 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB11_486 +.LBB11_503: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i291.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_505 +.LBB11_504: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i304.i.i.i.i.i + ; in Loop: Header=BB11_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_521 +.LBB11_505: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.506: ; in Loop: Header=BB11_505 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.507: ; %Flow908 + ; in Loop: Header=BB11_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.508: ; in Loop: Header=BB11_505 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.509: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i295.i.i.i.i.i + ; in Loop: Header=BB11_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.510: ; in Loop: Header=BB11_505 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.511: ; %Flow907 + ; in Loop: Header=BB11_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.512: ; in Loop: Header=BB11_505 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.513: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i298.i.i.i.i.i + ; in Loop: Header=BB11_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.514: ; in Loop: Header=BB11_505 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.515: ; %Flow906 + ; in Loop: Header=BB11_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.516: ; in Loop: Header=BB11_505 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.517: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i301.i.i.i.i.i + ; in Loop: Header=BB11_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.518: ; in Loop: Header=BB11_505 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.519: ; %Flow905 + ; in Loop: Header=BB11_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_504 +; %bb.520: ; in Loop: Header=BB11_505 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_504 +.LBB11_521: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile308 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_523 +.LBB11_522: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i321.i.i.i.i.i + ; in Loop: Header=BB11_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_539 +.LBB11_523: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.524: ; in Loop: Header=BB11_523 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.525: ; %Flow904 + ; in Loop: Header=BB11_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.526: ; in Loop: Header=BB11_523 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.527: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i312.i.i.i.i.i + ; in Loop: Header=BB11_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.528: ; in Loop: Header=BB11_523 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.529: ; %Flow903 + ; in Loop: Header=BB11_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.530: ; in Loop: Header=BB11_523 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.531: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i315.i.i.i.i.i + ; in Loop: Header=BB11_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.532: ; in Loop: Header=BB11_523 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.533: ; %Flow902 + ; in Loop: Header=BB11_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.534: ; in Loop: Header=BB11_523 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.535: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i318.i.i.i.i.i + ; in Loop: Header=BB11_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.536: ; in Loop: Header=BB11_523 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.537: ; %Flow901 + ; in Loop: Header=BB11_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_522 +; %bb.538: ; in Loop: Header=BB11_523 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_522 +.LBB11_539: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i324.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_541 +.LBB11_540: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i337.i.i.i.i.i + ; in Loop: Header=BB11_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_557 +.LBB11_541: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.542: ; in Loop: Header=BB11_541 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.543: ; %Flow900 + ; in Loop: Header=BB11_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.544: ; in Loop: Header=BB11_541 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.545: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i328.i.i.i.i.i + ; in Loop: Header=BB11_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.546: ; in Loop: Header=BB11_541 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.547: ; %Flow899 + ; in Loop: Header=BB11_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.548: ; in Loop: Header=BB11_541 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.549: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i331.i.i.i.i.i + ; in Loop: Header=BB11_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.550: ; in Loop: Header=BB11_541 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.551: ; %Flow898 + ; in Loop: Header=BB11_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.552: ; in Loop: Header=BB11_541 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.553: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i334.i.i.i.i.i + ; in Loop: Header=BB11_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.554: ; in Loop: Header=BB11_541 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.555: ; %Flow897 + ; in Loop: Header=BB11_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_540 +; %bb.556: ; in Loop: Header=BB11_541 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_540 +.LBB11_557: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_469 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.558: + v_bfe_u32 v18, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v220, v18, s6 +; %bb.559: ; %Flow896 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.560: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v220, vcc +; %bb.561: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i534.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.562: + v_bfe_u32 v19, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v219, v19, s6 +; %bb.563: ; %Flow895 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.564: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v219, vcc +; %bb.565: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i537.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.566: + v_bfe_u32 v20, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v218, v20, s6 +; %bb.567: ; %Flow894 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.568: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v218, vcc +; %bb.569: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i540.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.570: + v_bfe_u32 v21, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v217, v21, s6 +; %bb.571: ; %Flow893 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.572: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v217, vcc +; %bb.573: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i543.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.574: + v_bfe_u32 v22, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v216, v22, s6 +; %bb.575: ; %Flow892 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.576: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v216, vcc +; %bb.577: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i546.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.578: + v_bfe_u32 v23, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v215, v23, s6 +; %bb.579: ; %Flow891 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.580: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v215, vcc +; %bb.581: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i549.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.582: + v_bfe_u32 v24, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v214, v24, s6 +; %bb.583: ; %Flow890 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.584: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v214, vcc +; %bb.585: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i552.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.586: + v_bfe_u32 v25, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v213, v25, s6 +; %bb.587: ; %Flow889 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.588: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v213, vcc +; %bb.589: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i555.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.590: + v_bfe_u32 v26, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v212, v26, s6 +; %bb.591: ; %Flow888 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.592: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v212, vcc +; %bb.593: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i558.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.594: + v_bfe_u32 v27, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v211, v27, s6 +; %bb.595: ; %Flow887 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.596: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v211, vcc +; %bb.597: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i561.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.598: + v_bfe_u32 v28, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v210, v28, s6 +; %bb.599: ; %Flow886 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.600: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v210, vcc +; %bb.601: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i564.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.602: + v_bfe_u32 v29, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v209, v29, s6 +; %bb.603: ; %Flow885 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.604: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v209, vcc +; %bb.605: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i567.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.606: + v_bfe_u32 v30, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v208, v30, s6 +; %bb.607: ; %Flow884 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.608: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v208, vcc +; %bb.609: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.610: + v_bfe_u32 v31, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v207, v31, s6 +; %bb.611: ; %Flow883 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.612: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v207, vcc +; %bb.613: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i573.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.614: + v_bfe_u32 v32, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v206, v32, s6 +; %bb.615: ; %Flow882 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.616: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v206, vcc +; %bb.617: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i576.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.618: + v_bfe_u32 v33, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v204, v33, s6 +; %bb.619: ; %Flow881 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.620: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v204, vcc +; %bb.621: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i579.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.622: + v_bfe_u32 v34, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v205, v34, s6 +; %bb.623: ; %Flow880 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.624: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v205, vcc +; %bb.625: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i582.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.626: + v_bfe_u32 v35, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v203, v35, s6 +; %bb.627: ; %Flow879 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.628: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v203, vcc +; %bb.629: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i585.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.630: + v_bfe_u32 v36, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v202, v36, s6 +; %bb.631: ; %Flow878 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.632: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v202, vcc +; %bb.633: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i588.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.634: + v_bfe_u32 v37, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v201, v37, s6 +; %bb.635: ; %Flow877 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.636: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v201, vcc +; %bb.637: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i591.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.638: + v_bfe_u32 v40, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v200, v40, s6 +; %bb.639: ; %Flow876 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.640: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v200, vcc +; %bb.641: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i594.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.642: + v_bfe_u32 v41, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v199, v41, s6 +; %bb.643: ; %Flow875 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.644: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v199, vcc +; %bb.645: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i597.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.646: + v_bfe_u32 v42, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v198, v42, s6 +; %bb.647: ; %Flow874 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.648: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v198, vcc +; %bb.649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i600.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.650: + v_bfe_u32 v43, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v197, v43, s6 +; %bb.651: ; %Flow873 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.652: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v76, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v197, vcc +; %bb.653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v76, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.654: + v_bfe_u32 v76, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v196, v76, s6 +; %bb.655: ; %Flow872 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.656: + v_mov_b32_e32 v76, 0 + v_or_b32_e32 v77, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v196, vcc +; %bb.657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i606.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.658: + v_bfe_u32 v77, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v195, v77, s6 +; %bb.659: ; %Flow871 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.660: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v195, vcc +; %bb.661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i609.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.662: + v_bfe_u32 v78, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v194, v78, s6 +; %bb.663: ; %Flow870 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.664: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v194, vcc +; %bb.665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i612.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.666: + v_bfe_u32 v79, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v193, v79, s6 +; %bb.667: ; %Flow869 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.668: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v193, vcc +; %bb.669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i615.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.670: + v_bfe_u32 v80, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v192, v80, s6 +; %bb.671: ; %Flow868 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.672: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v192, vcc +; %bb.673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i618.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.674: + v_bfe_u32 v81, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v191, v81, s6 +; %bb.675: ; %Flow867 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.676: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v191, vcc +; %bb.677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i621.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.678: + v_bfe_u32 v82, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v190, v82, s6 +; %bb.679: ; %Flow866 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.680: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v190, vcc +; %bb.681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i624.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.682: + v_bfe_u32 v83, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v189, v83, s6 +; %bb.683: ; %Flow865 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.684: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v189, vcc +; %bb.685: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL628 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v40 offset:9216 + ds_write_b16_d16_hi v73, v41 offset:9344 + ds_write_b16_d16_hi v73, v42 offset:9472 + ds_write_b16_d16_hi v73, v43 offset:9600 + ds_write_b16_d16_hi v73, v76 offset:10240 + ds_write_b16_d16_hi v73, v77 offset:10368 + ds_write_b16_d16_hi v73, v78 offset:10496 + ds_write_b16_d16_hi v73, v79 offset:10624 + ds_write_b16_d16_hi v73, v80 offset:11264 + ds_write_b16_d16_hi v73, v81 offset:11392 + ds_write_b16_d16_hi v73, v82 offset:11520 + ds_write_b16_d16_hi v73, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v76, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB11_687 +.LBB11_686: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i691.i.i.i.i.i + ; in Loop: Header=BB11_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_703 +.LBB11_687: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.688: ; in Loop: Header=BB11_687 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.689: ; %Flow864 + ; in Loop: Header=BB11_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.690: ; in Loop: Header=BB11_687 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.691: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i682.i.i.i.i.i + ; in Loop: Header=BB11_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.692: ; in Loop: Header=BB11_687 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.693: ; %Flow863 + ; in Loop: Header=BB11_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.694: ; in Loop: Header=BB11_687 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.695: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i685.i.i.i.i.i + ; in Loop: Header=BB11_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v76, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.696: ; in Loop: Header=BB11_687 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.697: ; %Flow862 + ; in Loop: Header=BB11_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.698: ; in Loop: Header=BB11_687 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.699: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i688.i.i.i.i.i + ; in Loop: Header=BB11_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.700: ; in Loop: Header=BB11_687 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.701: ; %Flow861 + ; in Loop: Header=BB11_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_686 +; %bb.702: ; in Loop: Header=BB11_687 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB11_686 +.LBB11_703: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i694.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_705 +.LBB11_704: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i707.i.i.i.i.i + ; in Loop: Header=BB11_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v76, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_721 +.LBB11_705: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.706: ; in Loop: Header=BB11_705 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.707: ; %Flow860 + ; in Loop: Header=BB11_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.708: ; in Loop: Header=BB11_705 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.709: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i698.i.i.i.i.i + ; in Loop: Header=BB11_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v76, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.710: ; in Loop: Header=BB11_705 Depth=1 + v_bfe_u32 v76, v33, 16, 1 + v_add3_u32 v76, v33, v76, s9 + ; implicit-def: $vgpr33 +; %bb.711: ; %Flow859 + ; in Loop: Header=BB11_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.712: ; in Loop: Header=BB11_705 Depth=1 + v_or_b32_e32 v76, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v33, vcc +; %bb.713: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i701.i.i.i.i.i + ; in Loop: Header=BB11_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.714: ; in Loop: Header=BB11_705 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.715: ; %Flow858 + ; in Loop: Header=BB11_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.716: ; in Loop: Header=BB11_705 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.717: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i704.i.i.i.i.i + ; in Loop: Header=BB11_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.718: ; in Loop: Header=BB11_705 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.719: ; %Flow857 + ; in Loop: Header=BB11_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_704 +; %bb.720: ; in Loop: Header=BB11_705 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB11_704 +.LBB11_721: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile711 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 0x80, v38 + v_accvgpr_write_b32 a17, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_723 +.LBB11_722: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i724.i.i.i.i.i + ; in Loop: Header=BB11_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v76, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_739 +.LBB11_723: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.724: ; in Loop: Header=BB11_723 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.725: ; %Flow856 + ; in Loop: Header=BB11_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.726: ; in Loop: Header=BB11_723 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.727: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i715.i.i.i.i.i + ; in Loop: Header=BB11_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.728: ; in Loop: Header=BB11_723 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.729: ; %Flow855 + ; in Loop: Header=BB11_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.730: ; in Loop: Header=BB11_723 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.731: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i718.i.i.i.i.i + ; in Loop: Header=BB11_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.732: ; in Loop: Header=BB11_723 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.733: ; %Flow854 + ; in Loop: Header=BB11_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.734: ; in Loop: Header=BB11_723 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.735: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i721.i.i.i.i.i + ; in Loop: Header=BB11_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v76, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.736: ; in Loop: Header=BB11_723 Depth=1 + v_bfe_u32 v76, v43, 16, 1 + v_add3_u32 v76, v43, v76, s9 + ; implicit-def: $vgpr43 +; %bb.737: ; %Flow853 + ; in Loop: Header=BB11_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_722 +; %bb.738: ; in Loop: Header=BB11_723 Depth=1 + v_or_b32_e32 v76, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v43, vcc + s_branch .LBB11_722 +.LBB11_739: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i727.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_741 +.LBB11_740: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i740.i.i.i.i.i + ; in Loop: Header=BB11_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_757 +.LBB11_741: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.742: ; in Loop: Header=BB11_741 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.743: ; %Flow852 + ; in Loop: Header=BB11_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.744: ; in Loop: Header=BB11_741 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.745: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i731.i.i.i.i.i + ; in Loop: Header=BB11_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.746: ; in Loop: Header=BB11_741 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.747: ; %Flow851 + ; in Loop: Header=BB11_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.748: ; in Loop: Header=BB11_741 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.749: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i734.i.i.i.i.i + ; in Loop: Header=BB11_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.750: ; in Loop: Header=BB11_741 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.751: ; %Flow850 + ; in Loop: Header=BB11_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.752: ; in Loop: Header=BB11_741 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.753: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i737.i.i.i.i.i + ; in Loop: Header=BB11_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.754: ; in Loop: Header=BB11_741 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.755: ; %Flow849 + ; in Loop: Header=BB11_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_740 +; %bb.756: ; in Loop: Header=BB11_741 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_740 +.LBB11_757: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile744 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_759 +.LBB11_758: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i757.i.i.i.i.i + ; in Loop: Header=BB11_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_775 +.LBB11_759: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.760: ; in Loop: Header=BB11_759 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.761: ; %Flow848 + ; in Loop: Header=BB11_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.762: ; in Loop: Header=BB11_759 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.763: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i748.i.i.i.i.i + ; in Loop: Header=BB11_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.764: ; in Loop: Header=BB11_759 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.765: ; %Flow847 + ; in Loop: Header=BB11_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.766: ; in Loop: Header=BB11_759 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.767: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i751.i.i.i.i.i + ; in Loop: Header=BB11_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.768: ; in Loop: Header=BB11_759 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.769: ; %Flow846 + ; in Loop: Header=BB11_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.770: ; in Loop: Header=BB11_759 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.771: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i754.i.i.i.i.i + ; in Loop: Header=BB11_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.772: ; in Loop: Header=BB11_759 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.773: ; %Flow845 + ; in Loop: Header=BB11_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_758 +; %bb.774: ; in Loop: Header=BB11_759 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB11_758 +.LBB11_775: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i760.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_777 +.LBB11_776: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i773.i.i.i.i.i + ; in Loop: Header=BB11_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_793 +.LBB11_777: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.778: ; in Loop: Header=BB11_777 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.779: ; %Flow844 + ; in Loop: Header=BB11_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.780: ; in Loop: Header=BB11_777 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.781: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i764.i.i.i.i.i + ; in Loop: Header=BB11_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.782: ; in Loop: Header=BB11_777 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.783: ; %Flow843 + ; in Loop: Header=BB11_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.784: ; in Loop: Header=BB11_777 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.785: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i767.i.i.i.i.i + ; in Loop: Header=BB11_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.786: ; in Loop: Header=BB11_777 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.787: ; %Flow842 + ; in Loop: Header=BB11_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.788: ; in Loop: Header=BB11_777 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.789: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i770.i.i.i.i.i + ; in Loop: Header=BB11_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.790: ; in Loop: Header=BB11_777 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.791: ; %Flow841 + ; in Loop: Header=BB11_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_776 +; %bb.792: ; in Loop: Header=BB11_777 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_776 +.LBB11_793: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile777 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_795 +.LBB11_794: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i790.i.i.i.i.i + ; in Loop: Header=BB11_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_811 +.LBB11_795: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.796: ; in Loop: Header=BB11_795 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.797: ; %Flow840 + ; in Loop: Header=BB11_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.798: ; in Loop: Header=BB11_795 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.799: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i781.i.i.i.i.i + ; in Loop: Header=BB11_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.800: ; in Loop: Header=BB11_795 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.801: ; %Flow839 + ; in Loop: Header=BB11_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.802: ; in Loop: Header=BB11_795 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.803: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i784.i.i.i.i.i + ; in Loop: Header=BB11_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.804: ; in Loop: Header=BB11_795 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.805: ; %Flow838 + ; in Loop: Header=BB11_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.806: ; in Loop: Header=BB11_795 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.807: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i787.i.i.i.i.i + ; in Loop: Header=BB11_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.808: ; in Loop: Header=BB11_795 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.809: ; %Flow837 + ; in Loop: Header=BB11_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_794 +; %bb.810: ; in Loop: Header=BB11_795 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_794 +.LBB11_811: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i793.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_813 +.LBB11_812: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i806.i.i.i.i.i + ; in Loop: Header=BB11_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_829 +.LBB11_813: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.814: ; in Loop: Header=BB11_813 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.815: ; %Flow836 + ; in Loop: Header=BB11_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.816: ; in Loop: Header=BB11_813 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.817: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i797.i.i.i.i.i + ; in Loop: Header=BB11_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.818: ; in Loop: Header=BB11_813 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.819: ; %Flow835 + ; in Loop: Header=BB11_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.820: ; in Loop: Header=BB11_813 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.821: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i800.i.i.i.i.i + ; in Loop: Header=BB11_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.822: ; in Loop: Header=BB11_813 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.823: ; %Flow834 + ; in Loop: Header=BB11_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.824: ; in Loop: Header=BB11_813 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.825: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i803.i.i.i.i.i + ; in Loop: Header=BB11_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.826: ; in Loop: Header=BB11_813 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.827: ; %Flow833 + ; in Loop: Header=BB11_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_812 +; %bb.828: ; in Loop: Header=BB11_813 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_812 +.LBB11_829: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_938 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.830: + v_bfe_u32 v18, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v188, v18, s6 +; %bb.831: ; %Flow832 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.832: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v188, vcc +; %bb.833: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1003.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.834: + v_bfe_u32 v19, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v187, v19, s6 +; %bb.835: ; %Flow831 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.836: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v187, vcc +; %bb.837: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1006.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.838: + v_bfe_u32 v20, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v186, v20, s6 +; %bb.839: ; %Flow830 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.840: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v186, vcc +; %bb.841: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1009.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.842: + v_bfe_u32 v21, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v185, v21, s6 +; %bb.843: ; %Flow829 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.844: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v185, vcc +; %bb.845: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1012.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.846: + v_bfe_u32 v22, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v184, v22, s6 +; %bb.847: ; %Flow828 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.848: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v184, vcc +; %bb.849: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1015.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.850: + v_bfe_u32 v23, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v183, v23, s6 +; %bb.851: ; %Flow827 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.852: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v183, vcc +; %bb.853: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1018.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.854: + v_bfe_u32 v24, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v182, v24, s6 +; %bb.855: ; %Flow826 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.856: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v182, vcc +; %bb.857: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1021.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.858: + v_bfe_u32 v25, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v181, v25, s6 +; %bb.859: ; %Flow825 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.860: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v181, vcc +; %bb.861: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1024.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.862: + v_bfe_u32 v26, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v180, v26, s6 +; %bb.863: ; %Flow824 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.864: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v180, vcc +; %bb.865: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1027.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.866: + v_bfe_u32 v27, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v179, v27, s6 +; %bb.867: ; %Flow823 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.868: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v179, vcc +; %bb.869: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1030.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.870: + v_bfe_u32 v28, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v178, v28, s6 +; %bb.871: ; %Flow822 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.872: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v178, vcc +; %bb.873: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1033.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.874: + v_bfe_u32 v29, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v177, v29, s6 +; %bb.875: ; %Flow821 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.876: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v177, vcc +; %bb.877: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1036.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.878: + v_bfe_u32 v30, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v176, v30, s6 +; %bb.879: ; %Flow820 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.880: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v176, vcc +; %bb.881: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.882: + v_bfe_u32 v31, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v175, v31, s6 +; %bb.883: ; %Flow819 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.884: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v175, vcc +; %bb.885: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1042.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.886: + v_bfe_u32 v32, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v174, v32, s6 +; %bb.887: ; %Flow818 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.888: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v174, vcc +; %bb.889: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1045.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.890: + v_bfe_u32 v33, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v172, v33, s6 +; %bb.891: ; %Flow817 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.892: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v172, vcc +; %bb.893: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1048.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.894: + v_bfe_u32 v34, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v173, v34, s6 +; %bb.895: ; %Flow816 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.896: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v173, vcc +; %bb.897: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1051.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.898: + v_bfe_u32 v35, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v171, v35, s6 +; %bb.899: ; %Flow815 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.900: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v171, vcc +; %bb.901: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1054.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.902: + v_bfe_u32 v36, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v170, v36, s6 +; %bb.903: ; %Flow814 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.904: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v170, vcc +; %bb.905: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1057.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.906: + v_bfe_u32 v37, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v169, v37, s6 +; %bb.907: ; %Flow813 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.908: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v169, vcc +; %bb.909: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1060.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.910: + v_bfe_u32 v40, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v168, v40, s6 +; %bb.911: ; %Flow812 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.912: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v168, vcc +; %bb.913: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1063.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.914: + v_bfe_u32 v41, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v167, v41, s6 +; %bb.915: ; %Flow811 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.916: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v167, vcc +; %bb.917: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1066.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.918: + v_bfe_u32 v42, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v166, v42, s6 +; %bb.919: ; %Flow810 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.920: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v166, vcc +; %bb.921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1069.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.922: + v_bfe_u32 v43, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v165, v43, s6 +; %bb.923: ; %Flow809 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.924: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v76, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v165, vcc +; %bb.925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v76, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.926: + v_bfe_u32 v76, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v164, v76, s6 +; %bb.927: ; %Flow808 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.928: + v_mov_b32_e32 v76, 0 + v_or_b32_e32 v77, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v164, vcc +; %bb.929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1075.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.930: + v_bfe_u32 v77, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v163, v77, s6 +; %bb.931: ; %Flow807 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.932: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v163, vcc +; %bb.933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1078.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.934: + v_bfe_u32 v78, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v162, v78, s6 +; %bb.935: ; %Flow806 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.936: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v162, vcc +; %bb.937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1081.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.938: + v_bfe_u32 v79, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v161, v79, s6 +; %bb.939: ; %Flow805 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.940: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v161, vcc +; %bb.941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1084.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.942: + v_bfe_u32 v80, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v160, v80, s6 +; %bb.943: ; %Flow804 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.944: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v160, vcc +; %bb.945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1087.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.946: + v_bfe_u32 v81, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v159, v81, s6 +; %bb.947: ; %Flow803 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.948: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v159, vcc +; %bb.949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1090.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.950: + v_bfe_u32 v82, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v158, v82, s6 +; %bb.951: ; %Flow802 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.952: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v158, vcc +; %bb.953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1093.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.954: + v_bfe_u32 v83, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v157, v83, s6 +; %bb.955: ; %Flow801 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.956: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v157, vcc +; %bb.957: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1097 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v40 offset:9216 + ds_write_b16_d16_hi v73, v41 offset:9344 + ds_write_b16_d16_hi v73, v42 offset:9472 + ds_write_b16_d16_hi v73, v43 offset:9600 + ds_write_b16_d16_hi v73, v76 offset:10240 + ds_write_b16_d16_hi v73, v77 offset:10368 + ds_write_b16_d16_hi v73, v78 offset:10496 + ds_write_b16_d16_hi v73, v79 offset:10624 + ds_write_b16_d16_hi v73, v80 offset:11264 + ds_write_b16_d16_hi v73, v81 offset:11392 + ds_write_b16_d16_hi v73, v82 offset:11520 + ds_write_b16_d16_hi v73, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v76, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB11_959 +.LBB11_958: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1160.i.i.i.i.i + ; in Loop: Header=BB11_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_975 +.LBB11_959: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.960: ; in Loop: Header=BB11_959 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.961: ; %Flow800 + ; in Loop: Header=BB11_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.962: ; in Loop: Header=BB11_959 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.963: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1151.i.i.i.i.i + ; in Loop: Header=BB11_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.964: ; in Loop: Header=BB11_959 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.965: ; %Flow799 + ; in Loop: Header=BB11_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.966: ; in Loop: Header=BB11_959 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.967: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1154.i.i.i.i.i + ; in Loop: Header=BB11_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v76, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.968: ; in Loop: Header=BB11_959 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.969: ; %Flow798 + ; in Loop: Header=BB11_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.970: ; in Loop: Header=BB11_959 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.971: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1157.i.i.i.i.i + ; in Loop: Header=BB11_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.972: ; in Loop: Header=BB11_959 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.973: ; %Flow797 + ; in Loop: Header=BB11_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_958 +; %bb.974: ; in Loop: Header=BB11_959 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB11_958 +.LBB11_975: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1163.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_977 +.LBB11_976: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1176.i.i.i.i.i + ; in Loop: Header=BB11_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v76, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_993 +.LBB11_977: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.978: ; in Loop: Header=BB11_977 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.979: ; %Flow796 + ; in Loop: Header=BB11_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.980: ; in Loop: Header=BB11_977 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.981: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1167.i.i.i.i.i + ; in Loop: Header=BB11_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v76, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.982: ; in Loop: Header=BB11_977 Depth=1 + v_bfe_u32 v76, v33, 16, 1 + v_add3_u32 v76, v33, v76, s9 + ; implicit-def: $vgpr33 +; %bb.983: ; %Flow795 + ; in Loop: Header=BB11_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.984: ; in Loop: Header=BB11_977 Depth=1 + v_or_b32_e32 v76, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v33, vcc +; %bb.985: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1170.i.i.i.i.i + ; in Loop: Header=BB11_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.986: ; in Loop: Header=BB11_977 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.987: ; %Flow794 + ; in Loop: Header=BB11_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.988: ; in Loop: Header=BB11_977 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.989: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1173.i.i.i.i.i + ; in Loop: Header=BB11_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.990: ; in Loop: Header=BB11_977 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.991: ; %Flow793 + ; in Loop: Header=BB11_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_976 +; %bb.992: ; in Loop: Header=BB11_977 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB11_976 +.LBB11_993: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1180 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v76, 0xc0, v38 + v_add3_u32 v34, v40, v76, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_995 +.LBB11_994: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1193.i.i.i.i.i + ; in Loop: Header=BB11_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1011 +.LBB11_995: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.996: ; in Loop: Header=BB11_995 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.997: ; %Flow792 + ; in Loop: Header=BB11_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.998: ; in Loop: Header=BB11_995 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.999: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1184.i.i.i.i.i + ; in Loop: Header=BB11_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1000: ; in Loop: Header=BB11_995 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.1001: ; %Flow791 + ; in Loop: Header=BB11_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1002: ; in Loop: Header=BB11_995 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1003: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1187.i.i.i.i.i + ; in Loop: Header=BB11_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1004: ; in Loop: Header=BB11_995 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.1005: ; %Flow790 + ; in Loop: Header=BB11_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1006: ; in Loop: Header=BB11_995 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1007: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1190.i.i.i.i.i + ; in Loop: Header=BB11_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1008: ; in Loop: Header=BB11_995 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.1009: ; %Flow789 + ; in Loop: Header=BB11_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_994 +; %bb.1010: ; in Loop: Header=BB11_995 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB11_994 +.LBB11_1011: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1196.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1013 +.LBB11_1012: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1209.i.i.i.i.i + ; in Loop: Header=BB11_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1029 +.LBB11_1013: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1014: ; in Loop: Header=BB11_1013 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.1015: ; %Flow788 + ; in Loop: Header=BB11_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1016: ; in Loop: Header=BB11_1013 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1017: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1200.i.i.i.i.i + ; in Loop: Header=BB11_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1018: ; in Loop: Header=BB11_1013 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.1019: ; %Flow787 + ; in Loop: Header=BB11_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1020: ; in Loop: Header=BB11_1013 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1021: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1203.i.i.i.i.i + ; in Loop: Header=BB11_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1022: ; in Loop: Header=BB11_1013 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.1023: ; %Flow786 + ; in Loop: Header=BB11_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1024: ; in Loop: Header=BB11_1013 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1025: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1206.i.i.i.i.i + ; in Loop: Header=BB11_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1026: ; in Loop: Header=BB11_1013 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.1027: ; %Flow785 + ; in Loop: Header=BB11_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1012 +; %bb.1028: ; in Loop: Header=BB11_1013 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_1012 +.LBB11_1029: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1213 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1031 +.LBB11_1030: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1226.i.i.i.i.i + ; in Loop: Header=BB11_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1047 +.LBB11_1031: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1032: ; in Loop: Header=BB11_1031 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.1033: ; %Flow784 + ; in Loop: Header=BB11_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1034: ; in Loop: Header=BB11_1031 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1035: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1217.i.i.i.i.i + ; in Loop: Header=BB11_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1036: ; in Loop: Header=BB11_1031 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.1037: ; %Flow783 + ; in Loop: Header=BB11_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1038: ; in Loop: Header=BB11_1031 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1039: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1220.i.i.i.i.i + ; in Loop: Header=BB11_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1040: ; in Loop: Header=BB11_1031 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.1041: ; %Flow782 + ; in Loop: Header=BB11_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1042: ; in Loop: Header=BB11_1031 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1043: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1223.i.i.i.i.i + ; in Loop: Header=BB11_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1044: ; in Loop: Header=BB11_1031 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.1045: ; %Flow781 + ; in Loop: Header=BB11_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1030 +; %bb.1046: ; in Loop: Header=BB11_1031 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB11_1030 +.LBB11_1047: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1229.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_1049 +.LBB11_1048: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1242.i.i.i.i.i + ; in Loop: Header=BB11_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1065 +.LBB11_1049: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1050: ; in Loop: Header=BB11_1049 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.1051: ; %Flow780 + ; in Loop: Header=BB11_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1052: ; in Loop: Header=BB11_1049 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1053: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1233.i.i.i.i.i + ; in Loop: Header=BB11_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1054: ; in Loop: Header=BB11_1049 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.1055: ; %Flow779 + ; in Loop: Header=BB11_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1056: ; in Loop: Header=BB11_1049 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1057: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1236.i.i.i.i.i + ; in Loop: Header=BB11_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1058: ; in Loop: Header=BB11_1049 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.1059: ; %Flow778 + ; in Loop: Header=BB11_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1060: ; in Loop: Header=BB11_1049 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1061: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1239.i.i.i.i.i + ; in Loop: Header=BB11_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1062: ; in Loop: Header=BB11_1049 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.1063: ; %Flow777 + ; in Loop: Header=BB11_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1048 +; %bb.1064: ; in Loop: Header=BB11_1049 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_1048 +.LBB11_1065: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1246 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_1067 +.LBB11_1066: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1259.i.i.i.i.i + ; in Loop: Header=BB11_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1083 +.LBB11_1067: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1068: ; in Loop: Header=BB11_1067 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.1069: ; %Flow776 + ; in Loop: Header=BB11_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1070: ; in Loop: Header=BB11_1067 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1071: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1250.i.i.i.i.i + ; in Loop: Header=BB11_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1072: ; in Loop: Header=BB11_1067 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.1073: ; %Flow775 + ; in Loop: Header=BB11_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1074: ; in Loop: Header=BB11_1067 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1075: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1253.i.i.i.i.i + ; in Loop: Header=BB11_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1076: ; in Loop: Header=BB11_1067 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.1077: ; %Flow774 + ; in Loop: Header=BB11_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1078: ; in Loop: Header=BB11_1067 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1079: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1256.i.i.i.i.i + ; in Loop: Header=BB11_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1080: ; in Loop: Header=BB11_1067 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.1081: ; %Flow773 + ; in Loop: Header=BB11_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1066 +; %bb.1082: ; in Loop: Header=BB11_1067 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_1066 +.LBB11_1083: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1262.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_1085 +.LBB11_1084: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1275.i.i.i.i.i + ; in Loop: Header=BB11_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1101 +.LBB11_1085: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1086: ; in Loop: Header=BB11_1085 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.1087: ; %Flow772 + ; in Loop: Header=BB11_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1088: ; in Loop: Header=BB11_1085 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1089: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1266.i.i.i.i.i + ; in Loop: Header=BB11_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1090: ; in Loop: Header=BB11_1085 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.1091: ; %Flow771 + ; in Loop: Header=BB11_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1092: ; in Loop: Header=BB11_1085 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1093: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1269.i.i.i.i.i + ; in Loop: Header=BB11_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1094: ; in Loop: Header=BB11_1085 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.1095: ; %Flow770 + ; in Loop: Header=BB11_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1096: ; in Loop: Header=BB11_1085 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1097: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1272.i.i.i.i.i + ; in Loop: Header=BB11_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1098: ; in Loop: Header=BB11_1085 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.1099: ; %Flow769 + ; in Loop: Header=BB11_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1084 +; %bb.1100: ; in Loop: Header=BB11_1085 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_1084 +.LBB11_1101: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1407 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1102: + v_bfe_u32 v18, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v156, v18, s6 +; %bb.1103: ; %Flow768 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1104: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v156, vcc +; %bb.1105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1472.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1106: + v_bfe_u32 v19, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v155, v19, s6 +; %bb.1107: ; %Flow767 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1108: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v155, vcc +; %bb.1109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1475.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1110: + v_bfe_u32 v20, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v154, v20, s6 +; %bb.1111: ; %Flow766 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1112: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v154, vcc +; %bb.1113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1478.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1114: + v_bfe_u32 v21, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v153, v21, s6 +; %bb.1115: ; %Flow765 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1116: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v153, vcc +; %bb.1117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1481.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1118: + v_bfe_u32 v22, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v152, v22, s6 +; %bb.1119: ; %Flow764 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1120: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v152, vcc +; %bb.1121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1484.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1122: + v_bfe_u32 v23, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v151, v23, s6 +; %bb.1123: ; %Flow763 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1124: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v151, vcc +; %bb.1125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1487.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1126: + v_bfe_u32 v24, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v150, v24, s6 +; %bb.1127: ; %Flow762 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1128: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v150, vcc +; %bb.1129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1490.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1130: + v_bfe_u32 v25, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v149, v25, s6 +; %bb.1131: ; %Flow761 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1132: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v149, vcc +; %bb.1133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1493.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1134: + v_bfe_u32 v26, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v148, v26, s6 +; %bb.1135: ; %Flow760 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1136: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v148, vcc +; %bb.1137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1496.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1138: + v_bfe_u32 v27, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v147, v27, s6 +; %bb.1139: ; %Flow759 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1140: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v147, vcc +; %bb.1141: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1499.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1142: + v_bfe_u32 v28, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v146, v28, s6 +; %bb.1143: ; %Flow758 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1144: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v146, vcc +; %bb.1145: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1502.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1146: + v_bfe_u32 v29, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v145, v29, s6 +; %bb.1147: ; %Flow757 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1148: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v145, vcc +; %bb.1149: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1505.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1150: + v_bfe_u32 v30, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v144, v30, s6 +; %bb.1151: ; %Flow756 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1152: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v144, vcc +; %bb.1153: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1508.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1154: + v_bfe_u32 v31, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v143, v31, s6 +; %bb.1155: ; %Flow755 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1156: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v143, vcc +; %bb.1157: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1511.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1158: + v_bfe_u32 v32, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v142, v32, s6 +; %bb.1159: ; %Flow754 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1160: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v142, vcc +; %bb.1161: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1514.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1162: + v_bfe_u32 v33, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v141, v33, s6 +; %bb.1163: ; %Flow753 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1164: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v141, vcc +; %bb.1165: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1517.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1166: + v_bfe_u32 v34, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v2, v34, s6 +; %bb.1167: ; %Flow752 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1168: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v2, vcc +; %bb.1169: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1520.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1170: + v_bfe_u32 v35, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v3, v35, s6 +; %bb.1171: ; %Flow751 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1172: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v3, vcc +; %bb.1173: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1523.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1174: + v_bfe_u32 v36, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v4, v36, s6 +; %bb.1175: ; %Flow750 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1176: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v4, vcc +; %bb.1177: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1526.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1178: + v_bfe_u32 v37, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v5, v37, s6 +; %bb.1179: ; %Flow749 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1180: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v5, vcc +; %bb.1181: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1529.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1182: + v_bfe_u32 v40, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v6, v40, s6 +; %bb.1183: ; %Flow748 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1184: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v6, vcc +; %bb.1185: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1532.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1186: + v_bfe_u32 v41, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v7, v41, s6 +; %bb.1187: ; %Flow747 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1188: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v7, vcc +; %bb.1189: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1535.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1190: + v_bfe_u32 v42, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v8, v42, s6 +; %bb.1191: ; %Flow746 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1192: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v8, vcc +; %bb.1193: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1538.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1194: + v_bfe_u32 v43, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v9, v43, s6 +; %bb.1195: ; %Flow745 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1196: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v9, vcc +; %bb.1197: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1541.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1198: + v_bfe_u32 v77, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v10, v77, s6 +; %bb.1199: ; %Flow744 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1200: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v10, vcc +; %bb.1201: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1544.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1202: + v_bfe_u32 v78, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v11, v78, s6 +; %bb.1203: ; %Flow743 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1204: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v11, vcc +; %bb.1205: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1547.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1206: + v_bfe_u32 v79, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v12, v79, s6 +; %bb.1207: ; %Flow742 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1208: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v12, vcc +; %bb.1209: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1550.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1210: + v_bfe_u32 v80, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v13, v80, s6 +; %bb.1211: ; %Flow741 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1212: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v13, vcc +; %bb.1213: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1553.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1214: + v_bfe_u32 v81, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v14, v81, s6 +; %bb.1215: ; %Flow740 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1216: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v14, vcc +; %bb.1217: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1556.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1218: + v_bfe_u32 v82, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v15, v82, s6 +; %bb.1219: ; %Flow739 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1220: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v15, vcc +; %bb.1221: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1559.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1222: + v_bfe_u32 v83, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v16, v83, s6 +; %bb.1223: ; %Flow738 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1224: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v16, vcc +; %bb.1225: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1562.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1226: + v_bfe_u32 v84, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v17, v84, s6 +; %bb.1227: ; %Flow737 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1228: + v_mov_b32_e32 v84, 0 + v_accvgpr_write_b32 a0, v85 + v_or_b32_e32 v85, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v17, vcc + v_accvgpr_read_b32 v85, a0 +; %bb.1229: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1566 + s_or_b64 exec, exec, s[2:3] + s_or_b32 s8, s18, 0x80 + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v40 offset:9216 + ds_write_b16_d16_hi v73, v41 offset:9344 + ds_write_b16_d16_hi v73, v42 offset:9472 + ds_write_b16_d16_hi v73, v43 offset:9600 + ds_write_b16_d16_hi v73, v77 offset:10240 + ds_write_b16_d16_hi v73, v78 offset:10368 + ds_write_b16_d16_hi v73, v79 offset:10496 + ds_write_b16_d16_hi v73, v80 offset:10624 + ds_write_b16_d16_hi v73, v81 offset:11264 + ds_write_b16_d16_hi v73, v82 offset:11392 + ds_write_b16_d16_hi v73, v83 offset:11520 + ds_write_b16_d16_hi v73, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB11_1231 +.LBB11_1230: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1629.i.i.i.i.i + ; in Loop: Header=BB11_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s11 + v_perm_b32 v34, v79, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1247 +.LBB11_1231: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1232: ; in Loop: Header=BB11_1231 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1233: ; %Flow736 + ; in Loop: Header=BB11_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1234: ; in Loop: Header=BB11_1231 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1235: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1620.i.i.i.i.i + ; in Loop: Header=BB11_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1236: ; in Loop: Header=BB11_1231 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s10 + ; implicit-def: $vgpr35 +; %bb.1237: ; %Flow735 + ; in Loop: Header=BB11_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1238: ; in Loop: Header=BB11_1231 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.1239: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1623.i.i.i.i.i + ; in Loop: Header=BB11_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1240: ; in Loop: Header=BB11_1231 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s10 + ; implicit-def: $vgpr80 +; %bb.1241: ; %Flow734 + ; in Loop: Header=BB11_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1242: ; in Loop: Header=BB11_1231 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.1243: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1626.i.i.i.i.i + ; in Loop: Header=BB11_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1244: ; in Loop: Header=BB11_1231 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s10 + ; implicit-def: $vgpr80 +; %bb.1245: ; %Flow733 + ; in Loop: Header=BB11_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1230 +; %bb.1246: ; in Loop: Header=BB11_1231 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB11_1230 +.LBB11_1247: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1632.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_1249 +.LBB11_1248: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1645.i.i.i.i.i + ; in Loop: Header=BB11_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s11 + v_perm_b32 v32, v77, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1265 +.LBB11_1249: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1250: ; in Loop: Header=BB11_1249 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1251: ; %Flow732 + ; in Loop: Header=BB11_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1252: ; in Loop: Header=BB11_1249 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1253: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1636.i.i.i.i.i + ; in Loop: Header=BB11_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1254: ; in Loop: Header=BB11_1249 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s10 + ; implicit-def: $vgpr33 +; %bb.1255: ; %Flow731 + ; in Loop: Header=BB11_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1256: ; in Loop: Header=BB11_1249 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.1257: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1639.i.i.i.i.i + ; in Loop: Header=BB11_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1258: ; in Loop: Header=BB11_1249 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s10 + ; implicit-def: $vgpr78 +; %bb.1259: ; %Flow730 + ; in Loop: Header=BB11_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1260: ; in Loop: Header=BB11_1249 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.1261: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1642.i.i.i.i.i + ; in Loop: Header=BB11_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1262: ; in Loop: Header=BB11_1249 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s10 + ; implicit-def: $vgpr78 +; %bb.1263: ; %Flow729 + ; in Loop: Header=BB11_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1248 +; %bb.1264: ; in Loop: Header=BB11_1249 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB11_1248 +.LBB11_1265: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1649 + s_or_b64 exec, exec, s[2:3] + v_add3_u32 v34, v40, v76, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_1267 +.LBB11_1266: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1662.i.i.i.i.i + ; in Loop: Header=BB11_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v76, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1283 +.LBB11_1267: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1268: ; in Loop: Header=BB11_1267 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1269: ; %Flow728 + ; in Loop: Header=BB11_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1270: ; in Loop: Header=BB11_1267 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1271: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1653.i.i.i.i.i + ; in Loop: Header=BB11_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1272: ; in Loop: Header=BB11_1267 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1273: ; %Flow727 + ; in Loop: Header=BB11_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1274: ; in Loop: Header=BB11_1267 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1275: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1656.i.i.i.i.i + ; in Loop: Header=BB11_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1276: ; in Loop: Header=BB11_1267 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1277: ; %Flow726 + ; in Loop: Header=BB11_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1278: ; in Loop: Header=BB11_1267 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1279: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1659.i.i.i.i.i + ; in Loop: Header=BB11_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v76, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1280: ; in Loop: Header=BB11_1267 Depth=1 + v_bfe_u32 v76, v43, 16, 1 + v_add3_u32 v76, v43, v76, s10 + ; implicit-def: $vgpr43 +; %bb.1281: ; %Flow725 + ; in Loop: Header=BB11_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1266 +; %bb.1282: ; in Loop: Header=BB11_1267 Depth=1 + v_or_b32_e32 v76, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v43, vcc + s_branch .LBB11_1266 +.LBB11_1283: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1665.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1285 +.LBB11_1284: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1678.i.i.i.i.i + ; in Loop: Header=BB11_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1301 +.LBB11_1285: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1286: ; in Loop: Header=BB11_1285 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1287: ; %Flow724 + ; in Loop: Header=BB11_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1288: ; in Loop: Header=BB11_1285 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1289: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1669.i.i.i.i.i + ; in Loop: Header=BB11_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1290: ; in Loop: Header=BB11_1285 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1291: ; %Flow723 + ; in Loop: Header=BB11_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1292: ; in Loop: Header=BB11_1285 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1293: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1672.i.i.i.i.i + ; in Loop: Header=BB11_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1294: ; in Loop: Header=BB11_1285 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1295: ; %Flow722 + ; in Loop: Header=BB11_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1296: ; in Loop: Header=BB11_1285 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1297: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1675.i.i.i.i.i + ; in Loop: Header=BB11_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1298: ; in Loop: Header=BB11_1285 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1299: ; %Flow721 + ; in Loop: Header=BB11_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1284 +; %bb.1300: ; in Loop: Header=BB11_1285 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_1284 +.LBB11_1301: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1682 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1303 +.LBB11_1302: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1695.i.i.i.i.i + ; in Loop: Header=BB11_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1319 +.LBB11_1303: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1304: ; in Loop: Header=BB11_1303 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1305: ; %Flow720 + ; in Loop: Header=BB11_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1306: ; in Loop: Header=BB11_1303 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1307: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1686.i.i.i.i.i + ; in Loop: Header=BB11_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1308: ; in Loop: Header=BB11_1303 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1309: ; %Flow719 + ; in Loop: Header=BB11_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1310: ; in Loop: Header=BB11_1303 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1311: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1689.i.i.i.i.i + ; in Loop: Header=BB11_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1312: ; in Loop: Header=BB11_1303 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1313: ; %Flow718 + ; in Loop: Header=BB11_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1314: ; in Loop: Header=BB11_1303 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1315: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1692.i.i.i.i.i + ; in Loop: Header=BB11_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1316: ; in Loop: Header=BB11_1303 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1317: ; %Flow717 + ; in Loop: Header=BB11_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1302 +; %bb.1318: ; in Loop: Header=BB11_1303 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB11_1302 +.LBB11_1319: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1698.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_1321 +.LBB11_1320: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1711.i.i.i.i.i + ; in Loop: Header=BB11_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1337 +.LBB11_1321: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1322: ; in Loop: Header=BB11_1321 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1323: ; %Flow716 + ; in Loop: Header=BB11_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1324: ; in Loop: Header=BB11_1321 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1325: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1702.i.i.i.i.i + ; in Loop: Header=BB11_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1326: ; in Loop: Header=BB11_1321 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1327: ; %Flow715 + ; in Loop: Header=BB11_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1328: ; in Loop: Header=BB11_1321 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1329: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1705.i.i.i.i.i + ; in Loop: Header=BB11_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1330: ; in Loop: Header=BB11_1321 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1331: ; %Flow714 + ; in Loop: Header=BB11_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1332: ; in Loop: Header=BB11_1321 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1333: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1708.i.i.i.i.i + ; in Loop: Header=BB11_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1334: ; in Loop: Header=BB11_1321 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1335: ; %Flow713 + ; in Loop: Header=BB11_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1320 +; %bb.1336: ; in Loop: Header=BB11_1321 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_1320 +.LBB11_1337: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1715 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_1339 +.LBB11_1338: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1728.i.i.i.i.i + ; in Loop: Header=BB11_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1355 +.LBB11_1339: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1340: ; in Loop: Header=BB11_1339 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1341: ; %Flow712 + ; in Loop: Header=BB11_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1342: ; in Loop: Header=BB11_1339 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1343: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1719.i.i.i.i.i + ; in Loop: Header=BB11_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1344: ; in Loop: Header=BB11_1339 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1345: ; %Flow711 + ; in Loop: Header=BB11_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1346: ; in Loop: Header=BB11_1339 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1347: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1722.i.i.i.i.i + ; in Loop: Header=BB11_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1348: ; in Loop: Header=BB11_1339 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1349: ; %Flow710 + ; in Loop: Header=BB11_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1350: ; in Loop: Header=BB11_1339 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1351: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1725.i.i.i.i.i + ; in Loop: Header=BB11_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1352: ; in Loop: Header=BB11_1339 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1353: ; %Flow709 + ; in Loop: Header=BB11_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1338 +; %bb.1354: ; in Loop: Header=BB11_1339 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_1338 +.LBB11_1355: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1731.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_1357 +.LBB11_1356: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1744.i.i.i.i.i + ; in Loop: Header=BB11_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1373 +.LBB11_1357: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1358: ; in Loop: Header=BB11_1357 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1359: ; %Flow708 + ; in Loop: Header=BB11_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1360: ; in Loop: Header=BB11_1357 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1361: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1735.i.i.i.i.i + ; in Loop: Header=BB11_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1362: ; in Loop: Header=BB11_1357 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1363: ; %Flow707 + ; in Loop: Header=BB11_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1364: ; in Loop: Header=BB11_1357 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1365: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1738.i.i.i.i.i + ; in Loop: Header=BB11_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1366: ; in Loop: Header=BB11_1357 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1367: ; %Flow706 + ; in Loop: Header=BB11_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1368: ; in Loop: Header=BB11_1357 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1369: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1741.i.i.i.i.i + ; in Loop: Header=BB11_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1370: ; in Loop: Header=BB11_1357 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1371: ; %Flow705 + ; in Loop: Header=BB11_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1356 +; %bb.1372: ; in Loop: Header=BB11_1357 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_1356 +.LBB11_1373: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1876 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1374: + v_bfe_u32 v18, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v140, v18, s6 +; %bb.1375: ; %Flow704 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1376: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v140, vcc +; %bb.1377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1941.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1378: + v_bfe_u32 v19, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v139, v19, s6 +; %bb.1379: ; %Flow703 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1380: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v139, vcc +; %bb.1381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1944.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1382: + v_bfe_u32 v20, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v138, v20, s6 +; %bb.1383: ; %Flow702 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1384: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v138, vcc +; %bb.1385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1947.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1386: + v_bfe_u32 v21, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v137, v21, s6 +; %bb.1387: ; %Flow701 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1388: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v137, vcc +; %bb.1389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1950.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1390: + v_bfe_u32 v22, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v136, v22, s6 +; %bb.1391: ; %Flow700 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1392: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v136, vcc +; %bb.1393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1953.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1394: + v_bfe_u32 v23, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v135, v23, s6 +; %bb.1395: ; %Flow699 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1396: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v135, vcc +; %bb.1397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1956.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1398: + v_bfe_u32 v24, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v134, v24, s6 +; %bb.1399: ; %Flow698 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1400: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v134, vcc +; %bb.1401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1959.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1402: + v_bfe_u32 v25, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v133, v25, s6 +; %bb.1403: ; %Flow697 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1404: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v133, vcc +; %bb.1405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1962.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1406: + v_bfe_u32 v26, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v132, v26, s6 +; %bb.1407: ; %Flow696 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1408: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v132, vcc +; %bb.1409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1965.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1410: + v_bfe_u32 v27, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v131, v27, s6 +; %bb.1411: ; %Flow695 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1412: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v131, vcc +; %bb.1413: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1968.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1414: + v_bfe_u32 v28, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v130, v28, s6 +; %bb.1415: ; %Flow694 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1416: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v130, vcc +; %bb.1417: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1971.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1418: + v_bfe_u32 v29, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v129, v29, s6 +; %bb.1419: ; %Flow693 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1420: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v129, vcc +; %bb.1421: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1974.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1422: + v_bfe_u32 v30, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v128, v30, s6 +; %bb.1423: ; %Flow692 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1424: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v128, vcc +; %bb.1425: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1977.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1426: + v_bfe_u32 v31, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v127, v31, s6 +; %bb.1427: ; %Flow691 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1428: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v127, vcc +; %bb.1429: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1980.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1430: + v_bfe_u32 v32, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v126, v32, s6 +; %bb.1431: ; %Flow690 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1432: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v126, vcc +; %bb.1433: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1983.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1434: + v_bfe_u32 v33, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v124, v33, s6 +; %bb.1435: ; %Flow689 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1436: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v124, vcc +; %bb.1437: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1986.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1438: + v_bfe_u32 v34, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v125, v34, s6 +; %bb.1439: ; %Flow688 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1440: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v125, vcc +; %bb.1441: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1989.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1442: + v_bfe_u32 v35, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v123, v35, s6 +; %bb.1443: ; %Flow687 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1444: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v123, vcc +; %bb.1445: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1992.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1446: + v_bfe_u32 v36, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v122, v36, s6 +; %bb.1447: ; %Flow686 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1448: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v122, vcc +; %bb.1449: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1995.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1450: + v_bfe_u32 v37, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v121, v37, s6 +; %bb.1451: ; %Flow685 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1452: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v121, vcc +; %bb.1453: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1998.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1454: + v_bfe_u32 v40, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v120, v40, s6 +; %bb.1455: ; %Flow684 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1456: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v120, vcc +; %bb.1457: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2001.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1458: + v_bfe_u32 v41, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v119, v41, s6 +; %bb.1459: ; %Flow683 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1460: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v119, vcc +; %bb.1461: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2004.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1462: + v_bfe_u32 v42, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v118, v42, s6 +; %bb.1463: ; %Flow682 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1464: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v118, vcc +; %bb.1465: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2007.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1466: + v_bfe_u32 v43, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v117, v43, s6 +; %bb.1467: ; %Flow681 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1468: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v76, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v117, vcc +; %bb.1469: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2010.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v76, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1470: + v_bfe_u32 v76, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v116, v76, s6 +; %bb.1471: ; %Flow680 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1472: + v_mov_b32_e32 v76, 0 + v_or_b32_e32 v77, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v116, vcc +; %bb.1473: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2013.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1474: + v_bfe_u32 v77, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v115, v77, s6 +; %bb.1475: ; %Flow679 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1476: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v115, vcc +; %bb.1477: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2016.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1478: + v_bfe_u32 v78, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v114, v78, s6 +; %bb.1479: ; %Flow678 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1480: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v114, vcc +; %bb.1481: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2019.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1482: + v_bfe_u32 v79, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v113, v79, s6 +; %bb.1483: ; %Flow677 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1484: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v113, vcc +; %bb.1485: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2022.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1486: + v_bfe_u32 v80, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v112, v80, s6 +; %bb.1487: ; %Flow676 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1488: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v112, vcc +; %bb.1489: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2025.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1490: + v_bfe_u32 v81, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v111, v81, s6 +; %bb.1491: ; %Flow675 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1492: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v111, vcc +; %bb.1493: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2028.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1494: + v_bfe_u32 v82, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v110, v82, s6 +; %bb.1495: ; %Flow674 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1496: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v110, vcc +; %bb.1497: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2031.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1498: + v_bfe_u32 v83, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v109, v83, s6 +; %bb.1499: ; %Flow673 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1500: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v109, vcc +; %bb.1501: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2035 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v40 offset:9216 + ds_write_b16_d16_hi v73, v41 offset:9344 + ds_write_b16_d16_hi v73, v42 offset:9472 + ds_write_b16_d16_hi v73, v43 offset:9600 + ds_write_b16_d16_hi v73, v76 offset:10240 + ds_write_b16_d16_hi v73, v77 offset:10368 + ds_write_b16_d16_hi v73, v78 offset:10496 + ds_write_b16_d16_hi v73, v79 offset:10624 + ds_write_b16_d16_hi v73, v80 offset:11264 + ds_write_b16_d16_hi v73, v81 offset:11392 + ds_write_b16_d16_hi v73, v82 offset:11520 + ds_write_b16_d16_hi v73, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v76, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB11_1503 +.LBB11_1502: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2098.i.i.i.i.i + ; in Loop: Header=BB11_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s11 + v_perm_b32 v34, v78, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1519 +.LBB11_1503: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1504: ; in Loop: Header=BB11_1503 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1505: ; %Flow672 + ; in Loop: Header=BB11_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1506: ; in Loop: Header=BB11_1503 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1507: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2089.i.i.i.i.i + ; in Loop: Header=BB11_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1508: ; in Loop: Header=BB11_1503 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s10 + ; implicit-def: $vgpr35 +; %bb.1509: ; %Flow671 + ; in Loop: Header=BB11_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1510: ; in Loop: Header=BB11_1503 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.1511: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2092.i.i.i.i.i + ; in Loop: Header=BB11_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v76, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1512: ; in Loop: Header=BB11_1503 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s10 + ; implicit-def: $vgpr79 +; %bb.1513: ; %Flow670 + ; in Loop: Header=BB11_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1514: ; in Loop: Header=BB11_1503 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.1515: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2095.i.i.i.i.i + ; in Loop: Header=BB11_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1516: ; in Loop: Header=BB11_1503 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1517: ; %Flow669 + ; in Loop: Header=BB11_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1502 +; %bb.1518: ; in Loop: Header=BB11_1503 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB11_1502 +.LBB11_1519: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2101.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_1521 +.LBB11_1520: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2114.i.i.i.i.i + ; in Loop: Header=BB11_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s11 + v_perm_b32 v32, v76, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1537 +.LBB11_1521: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1522: ; in Loop: Header=BB11_1521 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1523: ; %Flow668 + ; in Loop: Header=BB11_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1524: ; in Loop: Header=BB11_1521 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1525: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2105.i.i.i.i.i + ; in Loop: Header=BB11_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v76, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1526: ; in Loop: Header=BB11_1521 Depth=1 + v_bfe_u32 v76, v33, 16, 1 + v_add3_u32 v76, v33, v76, s10 + ; implicit-def: $vgpr33 +; %bb.1527: ; %Flow667 + ; in Loop: Header=BB11_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1528: ; in Loop: Header=BB11_1521 Depth=1 + v_or_b32_e32 v76, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v33, vcc +; %bb.1529: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2108.i.i.i.i.i + ; in Loop: Header=BB11_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1530: ; in Loop: Header=BB11_1521 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s10 + ; implicit-def: $vgpr77 +; %bb.1531: ; %Flow666 + ; in Loop: Header=BB11_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1532: ; in Loop: Header=BB11_1521 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.1533: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2111.i.i.i.i.i + ; in Loop: Header=BB11_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1534: ; in Loop: Header=BB11_1521 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s10 + ; implicit-def: $vgpr77 +; %bb.1535: ; %Flow665 + ; in Loop: Header=BB11_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1520 +; %bb.1536: ; in Loop: Header=BB11_1521 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB11_1520 +.LBB11_1537: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2118 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a17 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB11_1539 +.LBB11_1538: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2131.i.i.i.i.i + ; in Loop: Header=BB11_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v76, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1555 +.LBB11_1539: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1540: ; in Loop: Header=BB11_1539 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1541: ; %Flow664 + ; in Loop: Header=BB11_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1542: ; in Loop: Header=BB11_1539 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1543: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2122.i.i.i.i.i + ; in Loop: Header=BB11_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1544: ; in Loop: Header=BB11_1539 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1545: ; %Flow663 + ; in Loop: Header=BB11_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1546: ; in Loop: Header=BB11_1539 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1547: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2125.i.i.i.i.i + ; in Loop: Header=BB11_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1548: ; in Loop: Header=BB11_1539 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1549: ; %Flow662 + ; in Loop: Header=BB11_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1550: ; in Loop: Header=BB11_1539 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1551: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2128.i.i.i.i.i + ; in Loop: Header=BB11_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v76, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1552: ; in Loop: Header=BB11_1539 Depth=1 + v_bfe_u32 v76, v43, 16, 1 + v_add3_u32 v76, v43, v76, s10 + ; implicit-def: $vgpr43 +; %bb.1553: ; %Flow661 + ; in Loop: Header=BB11_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1538 +; %bb.1554: ; in Loop: Header=BB11_1539 Depth=1 + v_or_b32_e32 v76, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v43, vcc + s_branch .LBB11_1538 +.LBB11_1555: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2134.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1557 +.LBB11_1556: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2147.i.i.i.i.i + ; in Loop: Header=BB11_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1573 +.LBB11_1557: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1558: ; in Loop: Header=BB11_1557 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1559: ; %Flow660 + ; in Loop: Header=BB11_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1560: ; in Loop: Header=BB11_1557 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1561: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2138.i.i.i.i.i + ; in Loop: Header=BB11_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1562: ; in Loop: Header=BB11_1557 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1563: ; %Flow659 + ; in Loop: Header=BB11_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1564: ; in Loop: Header=BB11_1557 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1565: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2141.i.i.i.i.i + ; in Loop: Header=BB11_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1566: ; in Loop: Header=BB11_1557 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1567: ; %Flow658 + ; in Loop: Header=BB11_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1568: ; in Loop: Header=BB11_1557 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1569: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2144.i.i.i.i.i + ; in Loop: Header=BB11_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1570: ; in Loop: Header=BB11_1557 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1571: ; %Flow657 + ; in Loop: Header=BB11_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1556 +; %bb.1572: ; in Loop: Header=BB11_1557 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_1556 +.LBB11_1573: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2151 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1575 +.LBB11_1574: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2164.i.i.i.i.i + ; in Loop: Header=BB11_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1591 +.LBB11_1575: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1576: ; in Loop: Header=BB11_1575 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1577: ; %Flow656 + ; in Loop: Header=BB11_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1578: ; in Loop: Header=BB11_1575 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1579: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2155.i.i.i.i.i + ; in Loop: Header=BB11_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1580: ; in Loop: Header=BB11_1575 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1581: ; %Flow655 + ; in Loop: Header=BB11_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1582: ; in Loop: Header=BB11_1575 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1583: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2158.i.i.i.i.i + ; in Loop: Header=BB11_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1584: ; in Loop: Header=BB11_1575 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1585: ; %Flow654 + ; in Loop: Header=BB11_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1586: ; in Loop: Header=BB11_1575 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1587: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2161.i.i.i.i.i + ; in Loop: Header=BB11_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1588: ; in Loop: Header=BB11_1575 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1589: ; %Flow653 + ; in Loop: Header=BB11_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1574 +; %bb.1590: ; in Loop: Header=BB11_1575 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB11_1574 +.LBB11_1591: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2167.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_1593 +.LBB11_1592: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2180.i.i.i.i.i + ; in Loop: Header=BB11_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1609 +.LBB11_1593: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1594: ; in Loop: Header=BB11_1593 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1595: ; %Flow652 + ; in Loop: Header=BB11_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1596: ; in Loop: Header=BB11_1593 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1597: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2171.i.i.i.i.i + ; in Loop: Header=BB11_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1598: ; in Loop: Header=BB11_1593 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1599: ; %Flow651 + ; in Loop: Header=BB11_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1600: ; in Loop: Header=BB11_1593 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1601: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2174.i.i.i.i.i + ; in Loop: Header=BB11_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1602: ; in Loop: Header=BB11_1593 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1603: ; %Flow650 + ; in Loop: Header=BB11_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1604: ; in Loop: Header=BB11_1593 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1605: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2177.i.i.i.i.i + ; in Loop: Header=BB11_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1606: ; in Loop: Header=BB11_1593 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1607: ; %Flow649 + ; in Loop: Header=BB11_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1592 +; %bb.1608: ; in Loop: Header=BB11_1593 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_1592 +.LBB11_1609: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2184 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_1611 +.LBB11_1610: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2197.i.i.i.i.i + ; in Loop: Header=BB11_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1627 +.LBB11_1611: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1612: ; in Loop: Header=BB11_1611 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1613: ; %Flow648 + ; in Loop: Header=BB11_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1614: ; in Loop: Header=BB11_1611 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1615: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2188.i.i.i.i.i + ; in Loop: Header=BB11_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1616: ; in Loop: Header=BB11_1611 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1617: ; %Flow647 + ; in Loop: Header=BB11_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1618: ; in Loop: Header=BB11_1611 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1619: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2191.i.i.i.i.i + ; in Loop: Header=BB11_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1620: ; in Loop: Header=BB11_1611 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1621: ; %Flow646 + ; in Loop: Header=BB11_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1622: ; in Loop: Header=BB11_1611 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1623: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2194.i.i.i.i.i + ; in Loop: Header=BB11_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1624: ; in Loop: Header=BB11_1611 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1625: ; %Flow645 + ; in Loop: Header=BB11_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1610 +; %bb.1626: ; in Loop: Header=BB11_1611 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_1610 +.LBB11_1627: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2200.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_1629 +.LBB11_1628: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2213.i.i.i.i.i + ; in Loop: Header=BB11_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1645 +.LBB11_1629: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1630: ; in Loop: Header=BB11_1629 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1631: ; %Flow644 + ; in Loop: Header=BB11_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1632: ; in Loop: Header=BB11_1629 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1633: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2204.i.i.i.i.i + ; in Loop: Header=BB11_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1634: ; in Loop: Header=BB11_1629 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1635: ; %Flow643 + ; in Loop: Header=BB11_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1636: ; in Loop: Header=BB11_1629 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1637: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2207.i.i.i.i.i + ; in Loop: Header=BB11_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1638: ; in Loop: Header=BB11_1629 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1639: ; %Flow642 + ; in Loop: Header=BB11_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1640: ; in Loop: Header=BB11_1629 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1641: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2210.i.i.i.i.i + ; in Loop: Header=BB11_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1642: ; in Loop: Header=BB11_1629 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1643: ; %Flow641 + ; in Loop: Header=BB11_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1628 +; %bb.1644: ; in Loop: Header=BB11_1629 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_1628 +.LBB11_1645: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2345 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1646: + v_bfe_u32 v18, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v108, v18, s6 +; %bb.1647: ; %Flow640 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1648: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v108, vcc +; %bb.1649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2410.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1650: + v_bfe_u32 v19, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v107, v19, s6 +; %bb.1651: ; %Flow639 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1652: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v107, vcc +; %bb.1653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2413.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1654: + v_bfe_u32 v20, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v106, v20, s6 +; %bb.1655: ; %Flow638 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1656: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v106, vcc +; %bb.1657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2416.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1658: + v_bfe_u32 v21, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v105, v21, s6 +; %bb.1659: ; %Flow637 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1660: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v105, vcc +; %bb.1661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2419.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1662: + v_bfe_u32 v22, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v104, v22, s6 +; %bb.1663: ; %Flow636 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1664: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v104, vcc +; %bb.1665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2422.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1666: + v_bfe_u32 v23, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v103, v23, s6 +; %bb.1667: ; %Flow635 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1668: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v103, vcc +; %bb.1669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2425.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1670: + v_bfe_u32 v24, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v102, v24, s6 +; %bb.1671: ; %Flow634 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1672: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v102, vcc +; %bb.1673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2428.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1674: + v_bfe_u32 v25, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v101, v25, s6 +; %bb.1675: ; %Flow633 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1676: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v101, vcc +; %bb.1677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2431.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1678: + v_bfe_u32 v26, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v100, v26, s6 +; %bb.1679: ; %Flow632 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1680: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v100, vcc +; %bb.1681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2434.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1682: + v_bfe_u32 v27, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v99, v27, s6 +; %bb.1683: ; %Flow631 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1684: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v99, vcc +; %bb.1685: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2437.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1686: + v_bfe_u32 v28, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v98, v28, s6 +; %bb.1687: ; %Flow630 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1688: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v98, vcc +; %bb.1689: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2440.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1690: + v_bfe_u32 v29, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v97, v29, s6 +; %bb.1691: ; %Flow629 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1692: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v97, vcc +; %bb.1693: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2443.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1694: + v_bfe_u32 v30, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v96, v30, s6 +; %bb.1695: ; %Flow628 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1696: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v96, vcc +; %bb.1697: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2446.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1698: + v_bfe_u32 v31, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v95, v31, s6 +; %bb.1699: ; %Flow627 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1700: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v95, vcc +; %bb.1701: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2449.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1702: + v_bfe_u32 v32, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v94, v32, s6 +; %bb.1703: ; %Flow626 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1704: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v94, vcc +; %bb.1705: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2452.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1706: + v_bfe_u32 v33, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v92, v33, s6 +; %bb.1707: ; %Flow625 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1708: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v92, vcc +; %bb.1709: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2455.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1710: + v_bfe_u32 v34, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v93, v34, s6 +; %bb.1711: ; %Flow624 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1712: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v93, vcc +; %bb.1713: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2458.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1714: + v_bfe_u32 v35, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v91, v35, s6 +; %bb.1715: ; %Flow623 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1716: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v91, vcc +; %bb.1717: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2461.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1718: + v_bfe_u32 v36, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v90, v36, s6 +; %bb.1719: ; %Flow622 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1720: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v90, vcc +; %bb.1721: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2464.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1722: + v_bfe_u32 v37, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v89, v37, s6 +; %bb.1723: ; %Flow621 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1724: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v89, vcc +; %bb.1725: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2467.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1726: + v_bfe_u32 v40, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v88, v40, s6 +; %bb.1727: ; %Flow620 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1728: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v88, vcc +; %bb.1729: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2470.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1730: + v_bfe_u32 v41, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v87, v41, s6 +; %bb.1731: ; %Flow619 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1732: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v87, vcc +; %bb.1733: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2473.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a64 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1734: + v_accvgpr_read_b32 v43, a64 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.1735: ; %Flow618 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1736: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v76, a64 + v_or_b32_e32 v43, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v76, vcc +; %bb.1737: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2476.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a55 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1738: + v_accvgpr_read_b32 v76, a55 + v_bfe_u32 v43, v76, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v76, v43, s6 +; %bb.1739: ; %Flow617 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1740: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v77, a55 + v_or_b32_e32 v76, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v77, vcc +; %bb.1741: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2479.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v76, a54 + v_and_b32_e32 v76, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1742: + v_accvgpr_read_b32 v77, a54 + v_bfe_u32 v76, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v77, v76, s6 +; %bb.1743: ; %Flow616 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1744: + v_mov_b32_e32 v76, 0 + v_accvgpr_read_b32 v78, a54 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v78, vcc +; %bb.1745: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2482.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a53 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1746: + v_accvgpr_read_b32 v78, a53 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.1747: ; %Flow615 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1748: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a53 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.1749: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2485.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a52 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1750: + v_accvgpr_read_b32 v79, a52 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.1751: ; %Flow614 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1752: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a52 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.1753: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2488.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a51 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1754: + v_accvgpr_read_b32 v80, a51 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.1755: ; %Flow613 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1756: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a51 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.1757: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2491.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a50 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1758: + v_accvgpr_read_b32 v81, a50 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.1759: ; %Flow612 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1760: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a50 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.1761: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2494.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a49 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1762: + v_accvgpr_read_b32 v82, a49 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.1763: ; %Flow611 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1764: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a49 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.1765: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2497.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1766: + v_bfe_u32 v82, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v86, v82, s6 +; %bb.1767: ; %Flow610 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1768: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v86, vcc +; %bb.1769: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2500.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v83, a48 + v_and_b32_e32 v83, 0x7f800000, v83 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1770: + v_accvgpr_read_b32 v84, a48 + v_bfe_u32 v83, v84, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v84, v83, s6 +; %bb.1771: ; %Flow609 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1772: + v_mov_b32_e32 v83, 0 + v_accvgpr_write_b32 a0, v86 + v_accvgpr_read_b32 v86, a48 + v_or_b32_e32 v84, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v86, vcc + v_accvgpr_read_b32 v86, a0 +; %bb.1773: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2504 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v40 offset:9216 + ds_write_b16_d16_hi v73, v41 offset:9344 + ds_write_b16_d16_hi v73, v42 offset:9472 + ds_write_b16_d16_hi v73, v43 offset:9600 + ds_write_b16_d16_hi v73, v76 offset:10240 + ds_write_b16_d16_hi v73, v77 offset:10368 + ds_write_b16_d16_hi v73, v78 offset:10496 + ds_write_b16_d16_hi v73, v79 offset:10624 + ds_write_b16_d16_hi v73, v80 offset:11264 + ds_write_b16_d16_hi v73, v81 offset:11392 + ds_write_b16_d16_hi v73, v82 offset:11520 + ds_write_b16_d16_hi v73, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v74 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshl_or_b32 v18, v20, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v76, 0 + s_branch .LBB11_1775 +.LBB11_1774: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2567.i.i.i.i.i + ; in Loop: Header=BB11_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v79, v35, s11 + v_perm_b32 v34, v77, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1791 +.LBB11_1775: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1776: ; in Loop: Header=BB11_1775 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1777: ; %Flow608 + ; in Loop: Header=BB11_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1778: ; in Loop: Header=BB11_1775 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1779: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2558.i.i.i.i.i + ; in Loop: Header=BB11_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v77, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1780: ; in Loop: Header=BB11_1775 Depth=1 + v_bfe_u32 v77, v35, 16, 1 + v_add3_u32 v77, v35, v77, s10 + ; implicit-def: $vgpr35 +; %bb.1781: ; %Flow607 + ; in Loop: Header=BB11_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1782: ; in Loop: Header=BB11_1775 Depth=1 + v_or_b32_e32 v77, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v35, vcc +; %bb.1783: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2561.i.i.i.i.i + ; in Loop: Header=BB11_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v78, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1784: ; in Loop: Header=BB11_1775 Depth=1 + v_bfe_u32 v35, v78, 16, 1 + v_add3_u32 v35, v78, v35, s10 + ; implicit-def: $vgpr78 +; %bb.1785: ; %Flow606 + ; in Loop: Header=BB11_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1786: ; in Loop: Header=BB11_1775 Depth=1 + v_or_b32_e32 v35, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v78, vcc +; %bb.1787: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2564.i.i.i.i.i + ; in Loop: Header=BB11_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v37 + v_add_f32_e32 v78, v31, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1788: ; in Loop: Header=BB11_1775 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s10 + ; implicit-def: $vgpr78 +; %bb.1789: ; %Flow605 + ; in Loop: Header=BB11_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1774 +; %bb.1790: ; in Loop: Header=BB11_1775 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB11_1774 +.LBB11_1791: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB11_1793 +.LBB11_1792: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2583.i.i.i.i.i + ; in Loop: Header=BB11_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v77, v33, s11 + v_perm_b32 v32, v41, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1809 +.LBB11_1793: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1794: ; in Loop: Header=BB11_1793 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1795: ; %Flow604 + ; in Loop: Header=BB11_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1796: ; in Loop: Header=BB11_1793 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1797: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2574.i.i.i.i.i + ; in Loop: Header=BB11_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1798: ; in Loop: Header=BB11_1793 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s10 + ; implicit-def: $vgpr33 +; %bb.1799: ; %Flow603 + ; in Loop: Header=BB11_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1800: ; in Loop: Header=BB11_1793 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.1801: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2577.i.i.i.i.i + ; in Loop: Header=BB11_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v76, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1802: ; in Loop: Header=BB11_1793 Depth=1 + v_bfe_u32 v33, v76, 16, 1 + v_add3_u32 v33, v76, v33, s10 + ; implicit-def: $vgpr76 +; %bb.1803: ; %Flow602 + ; in Loop: Header=BB11_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1804: ; in Loop: Header=BB11_1793 Depth=1 + v_or_b32_e32 v33, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v76, vcc +; %bb.1805: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2580.i.i.i.i.i + ; in Loop: Header=BB11_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v76, 0xffff0000, v35 + v_add_f32_e32 v76, v37, v76 + v_and_b32_e32 v77, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1806: ; in Loop: Header=BB11_1793 Depth=1 + v_bfe_u32 v77, v76, 16, 1 + v_add3_u32 v77, v76, v77, s10 + ; implicit-def: $vgpr76 +; %bb.1807: ; %Flow601 + ; in Loop: Header=BB11_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1792 +; %bb.1808: ; in Loop: Header=BB11_1793 Depth=1 + v_or_b32_e32 v77, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v76, vcc + s_branch .LBB11_1792 +.LBB11_1809: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2587 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a16 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB11_1811 +.LBB11_1810: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2600.i.i.i.i.i + ; in Loop: Header=BB11_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s11 + v_perm_b32 v30, v41, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1827 +.LBB11_1811: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1812: ; in Loop: Header=BB11_1811 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1813: ; %Flow600 + ; in Loop: Header=BB11_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1814: ; in Loop: Header=BB11_1811 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1815: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2591.i.i.i.i.i + ; in Loop: Header=BB11_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1816: ; in Loop: Header=BB11_1811 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s10 + ; implicit-def: $vgpr31 +; %bb.1817: ; %Flow599 + ; in Loop: Header=BB11_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1818: ; in Loop: Header=BB11_1811 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.1819: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2594.i.i.i.i.i + ; in Loop: Header=BB11_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1820: ; in Loop: Header=BB11_1811 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s10 + ; implicit-def: $vgpr42 +; %bb.1821: ; %Flow598 + ; in Loop: Header=BB11_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1822: ; in Loop: Header=BB11_1811 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.1823: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2597.i.i.i.i.i + ; in Loop: Header=BB11_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1824: ; in Loop: Header=BB11_1811 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s10 + ; implicit-def: $vgpr42 +; %bb.1825: ; %Flow597 + ; in Loop: Header=BB11_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1810 +; %bb.1826: ; in Loop: Header=BB11_1811 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB11_1810 +.LBB11_1827: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1829 +.LBB11_1828: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2616.i.i.i.i.i + ; in Loop: Header=BB11_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s11 + v_perm_b32 v28, v39, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1845 +.LBB11_1829: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1830: ; in Loop: Header=BB11_1829 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1831: ; %Flow596 + ; in Loop: Header=BB11_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1832: ; in Loop: Header=BB11_1829 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1833: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2607.i.i.i.i.i + ; in Loop: Header=BB11_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1834: ; in Loop: Header=BB11_1829 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s10 + ; implicit-def: $vgpr29 +; %bb.1835: ; %Flow595 + ; in Loop: Header=BB11_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1836: ; in Loop: Header=BB11_1829 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.1837: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2610.i.i.i.i.i + ; in Loop: Header=BB11_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1838: ; in Loop: Header=BB11_1829 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s10 + ; implicit-def: $vgpr40 +; %bb.1839: ; %Flow594 + ; in Loop: Header=BB11_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1840: ; in Loop: Header=BB11_1829 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.1841: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2613.i.i.i.i.i + ; in Loop: Header=BB11_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1842: ; in Loop: Header=BB11_1829 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s10 + ; implicit-def: $vgpr40 +; %bb.1843: ; %Flow593 + ; in Loop: Header=BB11_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1828 +; %bb.1844: ; in Loop: Header=BB11_1829 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB11_1828 +.LBB11_1845: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2620 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_1847 +.LBB11_1846: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2633.i.i.i.i.i + ; in Loop: Header=BB11_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1863 +.LBB11_1847: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1848: ; in Loop: Header=BB11_1847 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1849: ; %Flow592 + ; in Loop: Header=BB11_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1850: ; in Loop: Header=BB11_1847 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1851: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2624.i.i.i.i.i + ; in Loop: Header=BB11_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1852: ; in Loop: Header=BB11_1847 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1853: ; %Flow591 + ; in Loop: Header=BB11_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1854: ; in Loop: Header=BB11_1847 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1855: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2627.i.i.i.i.i + ; in Loop: Header=BB11_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1856: ; in Loop: Header=BB11_1847 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1857: ; %Flow590 + ; in Loop: Header=BB11_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1858: ; in Loop: Header=BB11_1847 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1859: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2630.i.i.i.i.i + ; in Loop: Header=BB11_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1860: ; in Loop: Header=BB11_1847 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s10 + ; implicit-def: $vgpr37 +; %bb.1861: ; %Flow589 + ; in Loop: Header=BB11_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1846 +; %bb.1862: ; in Loop: Header=BB11_1847 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB11_1846 +.LBB11_1863: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2636.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_1865 +.LBB11_1864: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2649.i.i.i.i.i + ; in Loop: Header=BB11_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1881 +.LBB11_1865: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1866: ; in Loop: Header=BB11_1865 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1867: ; %Flow588 + ; in Loop: Header=BB11_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1868: ; in Loop: Header=BB11_1865 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1869: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2640.i.i.i.i.i + ; in Loop: Header=BB11_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1870: ; in Loop: Header=BB11_1865 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1871: ; %Flow587 + ; in Loop: Header=BB11_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1872: ; in Loop: Header=BB11_1865 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1873: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2643.i.i.i.i.i + ; in Loop: Header=BB11_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1874: ; in Loop: Header=BB11_1865 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1875: ; %Flow586 + ; in Loop: Header=BB11_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1876: ; in Loop: Header=BB11_1865 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1877: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2646.i.i.i.i.i + ; in Loop: Header=BB11_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1878: ; in Loop: Header=BB11_1865 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1879: ; %Flow585 + ; in Loop: Header=BB11_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1864 +; %bb.1880: ; in Loop: Header=BB11_1865 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_1864 +.LBB11_1881: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2653 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_1883 +.LBB11_1882: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2666.i.i.i.i.i + ; in Loop: Header=BB11_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1899 +.LBB11_1883: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1884: ; in Loop: Header=BB11_1883 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1885: ; %Flow584 + ; in Loop: Header=BB11_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1886: ; in Loop: Header=BB11_1883 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1887: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2657.i.i.i.i.i + ; in Loop: Header=BB11_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1888: ; in Loop: Header=BB11_1883 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1889: ; %Flow583 + ; in Loop: Header=BB11_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1890: ; in Loop: Header=BB11_1883 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1891: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2660.i.i.i.i.i + ; in Loop: Header=BB11_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1892: ; in Loop: Header=BB11_1883 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1893: ; %Flow582 + ; in Loop: Header=BB11_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1894: ; in Loop: Header=BB11_1883 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1895: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2663.i.i.i.i.i + ; in Loop: Header=BB11_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1896: ; in Loop: Header=BB11_1883 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1897: ; %Flow581 + ; in Loop: Header=BB11_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1882 +; %bb.1898: ; in Loop: Header=BB11_1883 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_1882 +.LBB11_1899: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2669.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_1901 +.LBB11_1900: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2682.i.i.i.i.i + ; in Loop: Header=BB11_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_1917 +.LBB11_1901: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1902: ; in Loop: Header=BB11_1901 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1903: ; %Flow580 + ; in Loop: Header=BB11_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1904: ; in Loop: Header=BB11_1901 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1905: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2673.i.i.i.i.i + ; in Loop: Header=BB11_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1906: ; in Loop: Header=BB11_1901 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1907: ; %Flow579 + ; in Loop: Header=BB11_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1908: ; in Loop: Header=BB11_1901 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1909: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2676.i.i.i.i.i + ; in Loop: Header=BB11_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1910: ; in Loop: Header=BB11_1901 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1911: ; %Flow578 + ; in Loop: Header=BB11_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1912: ; in Loop: Header=BB11_1901 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1913: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2679.i.i.i.i.i + ; in Loop: Header=BB11_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1914: ; in Loop: Header=BB11_1901 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1915: ; %Flow577 + ; in Loop: Header=BB11_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_1900 +; %bb.1916: ; in Loop: Header=BB11_1901 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_1900 +.LBB11_1917: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2814 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v18, a47 + v_and_b32_e32 v18, 0x7f800000, v18 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1918: + v_accvgpr_read_b32 v19, a47 + v_bfe_u32 v18, v19, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v19, v18, s6 +; %bb.1919: ; %Flow576 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1920: + v_mov_b32_e32 v18, 0 + v_accvgpr_read_b32 v20, a47 + v_or_b32_e32 v19, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v20, vcc +; %bb.1921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2879.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v19, a46 + v_and_b32_e32 v19, 0x7f800000, v19 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1922: + v_accvgpr_read_b32 v20, a46 + v_bfe_u32 v19, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v20, v19, s6 +; %bb.1923: ; %Flow575 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1924: + v_mov_b32_e32 v19, 0 + v_accvgpr_read_b32 v21, a46 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v21, vcc +; %bb.1925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2882.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v20, a45 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1926: + v_accvgpr_read_b32 v21, a45 + v_bfe_u32 v20, v21, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v21, v20, s6 +; %bb.1927: ; %Flow574 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1928: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v22, a45 + v_or_b32_e32 v21, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v22, vcc +; %bb.1929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2885.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v21, a44 + v_and_b32_e32 v21, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1930: + v_accvgpr_read_b32 v22, a44 + v_bfe_u32 v21, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v22, v21, s6 +; %bb.1931: ; %Flow573 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1932: + v_mov_b32_e32 v21, 0 + v_accvgpr_read_b32 v23, a44 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v23, vcc +; %bb.1933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2888.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v22, a43 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1934: + v_accvgpr_read_b32 v23, a43 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 +; %bb.1935: ; %Flow572 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1936: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a43 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.1937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2891.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v23, a42 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1938: + v_accvgpr_read_b32 v24, a42 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 +; %bb.1939: ; %Flow571 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1940: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a42 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.1941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2894.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v24, a41 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1942: + v_accvgpr_read_b32 v25, a41 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 +; %bb.1943: ; %Flow570 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1944: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a41 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.1945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2897.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v25, a40 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1946: + v_accvgpr_read_b32 v26, a40 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 +; %bb.1947: ; %Flow569 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1948: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a40 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.1949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2900.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v26, a39 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1950: + v_accvgpr_read_b32 v27, a39 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 +; %bb.1951: ; %Flow568 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1952: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a39 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.1953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2903.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v27, a38 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1954: + v_accvgpr_read_b32 v28, a38 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 +; %bb.1955: ; %Flow567 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1956: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a38 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.1957: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2906.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v28, a37 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1958: + v_accvgpr_read_b32 v29, a37 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 +; %bb.1959: ; %Flow566 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1960: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a37 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.1961: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2909.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v29, a36 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1962: + v_accvgpr_read_b32 v30, a36 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 +; %bb.1963: ; %Flow565 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1964: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a36 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.1965: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2912.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v30, a35 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1966: + v_accvgpr_read_b32 v31, a35 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 +; %bb.1967: ; %Flow564 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1968: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a35 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.1969: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2915.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v31, a34 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1970: + v_accvgpr_read_b32 v32, a34 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 +; %bb.1971: ; %Flow563 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1972: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a34 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.1973: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2918.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v32, a33 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1974: + v_accvgpr_read_b32 v33, a33 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 +; %bb.1975: ; %Flow562 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1976: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a33 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.1977: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2921.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v33, a15 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1978: + v_accvgpr_read_b32 v34, a15 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 +; %bb.1979: ; %Flow561 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1980: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a15 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.1981: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2924.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v34, a32 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1982: + v_accvgpr_read_b32 v35, a32 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 +; %bb.1983: ; %Flow560 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1984: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a32 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.1985: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2927.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v35, a14 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1986: + v_accvgpr_read_b32 v36, a14 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 +; %bb.1987: ; %Flow559 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1988: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a14 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.1989: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2930.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v36, a13 + v_and_b32_e32 v36, 0x7f800000, v36 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1990: + v_accvgpr_read_b32 v37, a13 + v_bfe_u32 v36, v37, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v37, v36, s6 +; %bb.1991: ; %Flow558 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1992: + v_mov_b32_e32 v36, 0 + v_accvgpr_read_b32 v39, a13 + v_or_b32_e32 v37, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v39, vcc +; %bb.1993: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2933.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v37, a12 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1994: + v_accvgpr_read_b32 v39, a12 + v_bfe_u32 v37, v39, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v39, v37, s6 +; %bb.1995: ; %Flow557 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1996: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v40, a12 + v_or_b32_e32 v39, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v40, vcc +; %bb.1997: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2936.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v39, a11 + v_and_b32_e32 v39, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1998: + v_accvgpr_read_b32 v40, a11 + v_bfe_u32 v39, v40, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v40, v39, s6 +; %bb.1999: ; %Flow556 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2000: + v_mov_b32_e32 v39, 0 + v_accvgpr_read_b32 v41, a11 + v_or_b32_e32 v40, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v41, vcc +; %bb.2001: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2939.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v40, a10 + v_and_b32_e32 v40, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2002: + v_accvgpr_read_b32 v41, a10 + v_bfe_u32 v40, v41, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v41, v40, s6 +; %bb.2003: ; %Flow555 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2004: + v_mov_b32_e32 v40, 0 + v_accvgpr_read_b32 v42, a10 + v_or_b32_e32 v41, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v42, vcc +; %bb.2005: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2942.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a9 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2006: + v_accvgpr_read_b32 v42, a9 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.2007: ; %Flow554 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2008: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a9 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.2009: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2945.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a8 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2010: + v_accvgpr_read_b32 v43, a8 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.2011: ; %Flow553 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2012: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v76, a8 + v_or_b32_e32 v43, 0x10000, v76 + v_cmp_eq_u32_sdwa vcc, v76, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v76, vcc +; %bb.2013: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2948.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a7 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2014: + v_accvgpr_read_b32 v76, a7 + v_bfe_u32 v43, v76, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v76, v43, s6 +; %bb.2015: ; %Flow552 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2016: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v77, a7 + v_or_b32_e32 v76, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v76, v77, vcc +; %bb.2017: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2951.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v76, a6 + v_and_b32_e32 v76, 0x7f800000, v76 + v_cmp_ne_u32_e32 vcc, s2, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2018: + v_accvgpr_read_b32 v77, a6 + v_bfe_u32 v76, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v76, v77, v76, s6 +; %bb.2019: ; %Flow551 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2020: + v_mov_b32_e32 v76, 0 + v_accvgpr_read_b32 v78, a6 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v76 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v77, v78, vcc +; %bb.2021: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2954.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a5 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2022: + v_accvgpr_read_b32 v78, a5 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.2023: ; %Flow550 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2024: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a5 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.2025: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2957.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a4 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2026: + v_accvgpr_read_b32 v79, a4 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.2027: ; %Flow549 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2028: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a4 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.2029: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2960.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a3 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2030: + v_accvgpr_read_b32 v80, a3 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.2031: ; %Flow548 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2032: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a3 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.2033: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2963.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a2 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2034: + v_accvgpr_read_b32 v81, a2 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.2035: ; %Flow547 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2036: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a2 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.2037: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2966.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a1 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2038: + v_accvgpr_read_b32 v82, a1 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.2039: ; %Flow546 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2040: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a1 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.2041: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2969.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v85 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2042: + v_bfe_u32 v82, v85, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v85, v82, s6 +; %bb.2043: ; %Flow545 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2044: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v85 + v_cmp_eq_u32_sdwa vcc, v85, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v85, vcc +; %bb.2045: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2973 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v73, v18 + ds_write_b16_d16_hi v73, v19 offset:128 + ds_write_b16_d16_hi v73, v20 offset:256 + ds_write_b16_d16_hi v73, v21 offset:384 + ds_write_b16_d16_hi v73, v22 offset:1024 + ds_write_b16_d16_hi v73, v23 offset:1152 + ds_write_b16_d16_hi v73, v24 offset:1280 + ds_write_b16_d16_hi v73, v25 offset:1408 + ds_write_b16_d16_hi v73, v26 offset:2048 + ds_write_b16_d16_hi v73, v27 offset:2176 + ds_write_b16_d16_hi v73, v28 offset:2304 + ds_write_b16_d16_hi v73, v29 offset:2432 + ds_write_b16_d16_hi v73, v30 offset:3072 + ds_write_b16_d16_hi v73, v31 offset:3200 + ds_write_b16_d16_hi v73, v32 offset:3328 + ds_write_b16_d16_hi v73, v33 offset:3456 + ds_write_b16_d16_hi v73, v34 offset:8192 + ds_write_b16_d16_hi v73, v35 offset:8320 + ds_write_b16_d16_hi v73, v36 offset:8448 + ds_write_b16_d16_hi v73, v37 offset:8576 + ds_write_b16_d16_hi v73, v39 offset:9216 + ds_write_b16_d16_hi v73, v40 offset:9344 + ds_write_b16_d16_hi v73, v41 offset:9472 + ds_write_b16_d16_hi v73, v42 offset:9600 + ds_write_b16_d16_hi v73, v43 offset:10240 + ds_write_b16_d16_hi v73, v76 offset:10368 + ds_write_b16_d16_hi v73, v77 offset:10496 + ds_write_b16_d16_hi v73, v78 offset:10624 + ds_write_b16_d16_hi v73, v79 offset:11264 + ds_write_b16_d16_hi v73, v80 offset:11392 + ds_write_b16_d16_hi v73, v81 offset:11520 + ds_write_b16_d16_hi v73, v82 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v18, s2, v74 + v_add_u32_e32 v19, s8, v18 + v_mad_u64_u32 v[38:39], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[40:41], v[38:39], 1, s[0:1] + global_load_dwordx2 v[36:37], v[40:41], off + v_lshl_or_b32 v18, v18, 7, v75 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v42, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v43, 0 + s_branch .LBB11_2047 +.LBB11_2046: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i3036.i.i.i.i.i + ; in Loop: Header=BB11_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v75, v35, s10 + v_perm_b32 v34, v73, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[40:41], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2063 +.LBB11_2047: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2048: ; in Loop: Header=BB11_2047 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.2049: ; %Flow544 + ; in Loop: Header=BB11_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2050: ; in Loop: Header=BB11_2047 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.2051: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i3027.i.i.i.i.i + ; in Loop: Header=BB11_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v73, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v73 + ; implicit-def: $vgpr73 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2052: ; in Loop: Header=BB11_2047 Depth=1 + v_bfe_u32 v73, v35, 16, 1 + v_add3_u32 v73, v35, v73, s9 + ; implicit-def: $vgpr35 +; %bb.2053: ; %Flow543 + ; in Loop: Header=BB11_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2054: ; in Loop: Header=BB11_2047 Depth=1 + v_or_b32_e32 v73, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v73, v73, v35, vcc +; %bb.2055: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i3030.i.i.i.i.i + ; in Loop: Header=BB11_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v74, v42, v35 + v_and_b32_e32 v35, 0x7f800000, v74 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2056: ; in Loop: Header=BB11_2047 Depth=1 + v_bfe_u32 v35, v74, 16, 1 + v_add3_u32 v35, v74, v35, s9 + ; implicit-def: $vgpr74 +; %bb.2057: ; %Flow542 + ; in Loop: Header=BB11_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2058: ; in Loop: Header=BB11_2047 Depth=1 + v_or_b32_e32 v35, 0x10000, v74 + v_cmp_eq_u32_sdwa vcc, v74, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v74, vcc +; %bb.2059: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i3033.i.i.i.i.i + ; in Loop: Header=BB11_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v74, 0xffff0000, v37 + v_add_f32_e32 v74, v31, v74 + v_and_b32_e32 v75, 0x7f800000, v74 + v_cmp_ne_u32_e32 vcc, s8, v75 + ; implicit-def: $vgpr75 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2060: ; in Loop: Header=BB11_2047 Depth=1 + v_bfe_u32 v75, v74, 16, 1 + v_add3_u32 v75, v74, v75, s9 + ; implicit-def: $vgpr74 +; %bb.2061: ; %Flow541 + ; in Loop: Header=BB11_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2046 +; %bb.2062: ; in Loop: Header=BB11_2047 Depth=1 + v_or_b32_e32 v75, 0x10000, v74 + v_cmp_eq_u32_sdwa vcc, v74, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v75, v75, v74, vcc + s_branch .LBB11_2046 +.LBB11_2063: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i3039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[40:41], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB11_2065 +.LBB11_2064: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i3052.i.i.i.i.i + ; in Loop: Header=BB11_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v73, v33, s10 + v_perm_b32 v32, v42, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[40:41], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2081 +.LBB11_2065: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2066: ; in Loop: Header=BB11_2065 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.2067: ; %Flow540 + ; in Loop: Header=BB11_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2068: ; in Loop: Header=BB11_2065 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.2069: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i3043.i.i.i.i.i + ; in Loop: Header=BB11_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v42, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2070: ; in Loop: Header=BB11_2065 Depth=1 + v_bfe_u32 v42, v33, 16, 1 + v_add3_u32 v42, v33, v42, s9 + ; implicit-def: $vgpr33 +; %bb.2071: ; %Flow539 + ; in Loop: Header=BB11_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2072: ; in Loop: Header=BB11_2065 Depth=1 + v_or_b32_e32 v42, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v33, vcc +; %bb.2073: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i3046.i.i.i.i.i + ; in Loop: Header=BB11_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v43, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2074: ; in Loop: Header=BB11_2065 Depth=1 + v_bfe_u32 v33, v43, 16, 1 + v_add3_u32 v33, v43, v33, s9 + ; implicit-def: $vgpr43 +; %bb.2075: ; %Flow538 + ; in Loop: Header=BB11_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2076: ; in Loop: Header=BB11_2065 Depth=1 + v_or_b32_e32 v33, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v43, vcc +; %bb.2077: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i3049.i.i.i.i.i + ; in Loop: Header=BB11_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v35 + v_add_f32_e32 v43, v37, v43 + v_and_b32_e32 v73, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v73 + ; implicit-def: $vgpr73 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2078: ; in Loop: Header=BB11_2065 Depth=1 + v_bfe_u32 v73, v43, 16, 1 + v_add3_u32 v73, v43, v73, s9 + ; implicit-def: $vgpr43 +; %bb.2079: ; %Flow537 + ; in Loop: Header=BB11_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2064 +; %bb.2080: ; in Loop: Header=BB11_2065 Depth=1 + v_or_b32_e32 v73, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v73, v73, v43, vcc + s_branch .LBB11_2064 +.LBB11_2081: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3056 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v38 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v38, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB11_2083 +.LBB11_2082: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i3069.i.i.i.i.i + ; in Loop: Header=BB11_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v42, v31, s10 + v_perm_b32 v30, v40, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2099 +.LBB11_2083: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2084: ; in Loop: Header=BB11_2083 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.2085: ; %Flow536 + ; in Loop: Header=BB11_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2086: ; in Loop: Header=BB11_2083 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.2087: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i3060.i.i.i.i.i + ; in Loop: Header=BB11_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v40, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2088: ; in Loop: Header=BB11_2083 Depth=1 + v_bfe_u32 v40, v31, 16, 1 + v_add3_u32 v40, v31, v40, s9 + ; implicit-def: $vgpr31 +; %bb.2089: ; %Flow535 + ; in Loop: Header=BB11_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2090: ; in Loop: Header=BB11_2083 Depth=1 + v_or_b32_e32 v40, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v31, vcc +; %bb.2091: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i3063.i.i.i.i.i + ; in Loop: Header=BB11_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v41, v38, v31 + v_and_b32_e32 v31, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2092: ; in Loop: Header=BB11_2083 Depth=1 + v_bfe_u32 v31, v41, 16, 1 + v_add3_u32 v31, v41, v31, s9 + ; implicit-def: $vgpr41 +; %bb.2093: ; %Flow534 + ; in Loop: Header=BB11_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2094: ; in Loop: Header=BB11_2083 Depth=1 + v_or_b32_e32 v31, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v41, vcc +; %bb.2095: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i3066.i.i.i.i.i + ; in Loop: Header=BB11_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v33 + v_add_f32_e32 v41, v27, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2096: ; in Loop: Header=BB11_2083 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.2097: ; %Flow533 + ; in Loop: Header=BB11_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2082 +; %bb.2098: ; in Loop: Header=BB11_2083 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB11_2082 +.LBB11_2099: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i3072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_2101 +.LBB11_2100: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i3085.i.i.i.i.i + ; in Loop: Header=BB11_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v40, v29, s10 + v_perm_b32 v28, v38, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2117 +.LBB11_2101: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2102: ; in Loop: Header=BB11_2101 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.2103: ; %Flow532 + ; in Loop: Header=BB11_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2104: ; in Loop: Header=BB11_2101 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.2105: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i3076.i.i.i.i.i + ; in Loop: Header=BB11_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v38, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2106: ; in Loop: Header=BB11_2101 Depth=1 + v_bfe_u32 v38, v29, 16, 1 + v_add3_u32 v38, v29, v38, s9 + ; implicit-def: $vgpr29 +; %bb.2107: ; %Flow531 + ; in Loop: Header=BB11_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2108: ; in Loop: Header=BB11_2101 Depth=1 + v_or_b32_e32 v38, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v29, vcc +; %bb.2109: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i3079.i.i.i.i.i + ; in Loop: Header=BB11_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v39, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2110: ; in Loop: Header=BB11_2101 Depth=1 + v_bfe_u32 v29, v39, 16, 1 + v_add3_u32 v29, v39, v29, s9 + ; implicit-def: $vgpr39 +; %bb.2111: ; %Flow530 + ; in Loop: Header=BB11_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2112: ; in Loop: Header=BB11_2101 Depth=1 + v_or_b32_e32 v29, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v39, vcc +; %bb.2113: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i3082.i.i.i.i.i + ; in Loop: Header=BB11_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v39, 0xffff0000, v31 + v_add_f32_e32 v39, v33, v39 + v_and_b32_e32 v40, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2114: ; in Loop: Header=BB11_2101 Depth=1 + v_bfe_u32 v40, v39, 16, 1 + v_add3_u32 v40, v39, v40, s9 + ; implicit-def: $vgpr39 +; %bb.2115: ; %Flow529 + ; in Loop: Header=BB11_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2100 +; %bb.2116: ; in Loop: Header=BB11_2101 Depth=1 + v_or_b32_e32 v40, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v39, vcc + s_branch .LBB11_2100 +.LBB11_2117: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3089 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB11_2119 +.LBB11_2118: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i3102.i.i.i.i.i + ; in Loop: Header=BB11_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v38, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2135 +.LBB11_2119: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2120: ; in Loop: Header=BB11_2119 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.2121: ; %Flow528 + ; in Loop: Header=BB11_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2122: ; in Loop: Header=BB11_2119 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.2123: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i3093.i.i.i.i.i + ; in Loop: Header=BB11_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2124: ; in Loop: Header=BB11_2119 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.2125: ; %Flow527 + ; in Loop: Header=BB11_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2126: ; in Loop: Header=BB11_2119 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.2127: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i3096.i.i.i.i.i + ; in Loop: Header=BB11_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2128: ; in Loop: Header=BB11_2119 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.2129: ; %Flow526 + ; in Loop: Header=BB11_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2130: ; in Loop: Header=BB11_2119 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.2131: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i3099.i.i.i.i.i + ; in Loop: Header=BB11_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v38, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2132: ; in Loop: Header=BB11_2119 Depth=1 + v_bfe_u32 v38, v37, 16, 1 + v_add3_u32 v38, v37, v38, s9 + ; implicit-def: $vgpr37 +; %bb.2133: ; %Flow525 + ; in Loop: Header=BB11_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2118 +; %bb.2134: ; in Loop: Header=BB11_2119 Depth=1 + v_or_b32_e32 v38, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v37, vcc + s_branch .LBB11_2118 +.LBB11_2135: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i3105.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB11_2137 +.LBB11_2136: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i3118.i.i.i.i.i + ; in Loop: Header=BB11_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2153 +.LBB11_2137: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2138: ; in Loop: Header=BB11_2137 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.2139: ; %Flow524 + ; in Loop: Header=BB11_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2140: ; in Loop: Header=BB11_2137 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.2141: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i3109.i.i.i.i.i + ; in Loop: Header=BB11_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2142: ; in Loop: Header=BB11_2137 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.2143: ; %Flow523 + ; in Loop: Header=BB11_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2144: ; in Loop: Header=BB11_2137 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.2145: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i3112.i.i.i.i.i + ; in Loop: Header=BB11_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2146: ; in Loop: Header=BB11_2137 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.2147: ; %Flow522 + ; in Loop: Header=BB11_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2148: ; in Loop: Header=BB11_2137 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.2149: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i3115.i.i.i.i.i + ; in Loop: Header=BB11_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2150: ; in Loop: Header=BB11_2137 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.2151: ; %Flow521 + ; in Loop: Header=BB11_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2136 +; %bb.2152: ; in Loop: Header=BB11_2137 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB11_2136 +.LBB11_2153: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3122 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB11_2155 +.LBB11_2154: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i3135.i.i.i.i.i + ; in Loop: Header=BB11_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2171 +.LBB11_2155: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2156: ; in Loop: Header=BB11_2155 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.2157: ; %Flow520 + ; in Loop: Header=BB11_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2158: ; in Loop: Header=BB11_2155 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.2159: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i3126.i.i.i.i.i + ; in Loop: Header=BB11_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2160: ; in Loop: Header=BB11_2155 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.2161: ; %Flow519 + ; in Loop: Header=BB11_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2162: ; in Loop: Header=BB11_2155 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.2163: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i3129.i.i.i.i.i + ; in Loop: Header=BB11_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2164: ; in Loop: Header=BB11_2155 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.2165: ; %Flow518 + ; in Loop: Header=BB11_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2166: ; in Loop: Header=BB11_2155 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.2167: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i3132.i.i.i.i.i + ; in Loop: Header=BB11_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2168: ; in Loop: Header=BB11_2155 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.2169: ; %Flow517 + ; in Loop: Header=BB11_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2154 +; %bb.2170: ; in Loop: Header=BB11_2155 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB11_2154 +.LBB11_2171: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i3138.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB11_2173 +.LBB11_2172: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i3151.i.i.i.i.i + ; in Loop: Header=BB11_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB11_2189 +.LBB11_2173: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2174: ; in Loop: Header=BB11_2173 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.2175: ; %Flow515 + ; in Loop: Header=BB11_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2176: ; in Loop: Header=BB11_2173 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.2177: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i3142.i.i.i.i.i + ; in Loop: Header=BB11_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2178: ; in Loop: Header=BB11_2173 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.2179: ; %Flow514 + ; in Loop: Header=BB11_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2180: ; in Loop: Header=BB11_2173 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.2181: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i3145.i.i.i.i.i + ; in Loop: Header=BB11_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2182: ; in Loop: Header=BB11_2173 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.2183: ; %Flow513 + ; in Loop: Header=BB11_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2184: ; in Loop: Header=BB11_2173 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.2185: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i3148.i.i.i.i.i + ; in Loop: Header=BB11_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2186: ; in Loop: Header=BB11_2173 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.2187: ; %Flow + ; in Loop: Header=BB11_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB11_2172 +; %bb.2188: ; in Loop: Header=BB11_2173 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB11_2172 +.LBB11_2189: ; %Flow516 + s_or_b64 exec, exec, s[2:3] + s_mov_b64 vcc, 0 + s_branch .LBB11_12 +.LBB11_2190: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2191: + v_bfe_u32 v18, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v72, v18, s7 + ; implicit-def: $vgpr72 +; %bb.2192: ; %Flow1280 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2193: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v72, vcc +; %bb.2194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2195: + v_bfe_u32 v19, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v71, v19, s7 + ; implicit-def: $vgpr71 +; %bb.2196: ; %Flow1279 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2197: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v71, vcc +; %bb.2198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v69 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2199: + v_bfe_u32 v19, v69, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v69, v19, s7 + ; implicit-def: $vgpr69 +; %bb.2200: ; %Flow1278 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2201: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v21, 0x10000, v69 + v_cmp_eq_u32_sdwa vcc, v69, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v69, vcc +; %bb.2202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2203: + v_bfe_u32 v19, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v68, v19, s7 + ; implicit-def: $vgpr68 +; %bb.2204: ; %Flow1277 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2205: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v22, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v68, vcc +; %bb.2206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2207: + v_bfe_u32 v19, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v67, v19, s7 + ; implicit-def: $vgpr67 +; %bb.2208: ; %Flow1276 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2209: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v23, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v67, vcc +; %bb.2210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2211: + v_bfe_u32 v19, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v66, v19, s7 + ; implicit-def: $vgpr66 +; %bb.2212: ; %Flow1275 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2213: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v24, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v66, vcc +; %bb.2214: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2215: + v_bfe_u32 v19, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v65, v19, s7 + ; implicit-def: $vgpr65 +; %bb.2216: ; %Flow1274 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2217: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v25, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v65, vcc +; %bb.2218: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2219: + v_bfe_u32 v19, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v64, v19, s7 + ; implicit-def: $vgpr64 +; %bb.2220: ; %Flow1273 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2221: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v26, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v64, vcc +; %bb.2222: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2223: + v_bfe_u32 v19, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v63, v19, s7 + ; implicit-def: $vgpr63 +; %bb.2224: ; %Flow1272 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2225: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v27, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v63, vcc +; %bb.2226: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2227: + v_bfe_u32 v19, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v62, v19, s7 + ; implicit-def: $vgpr62 +; %bb.2228: ; %Flow1271 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2229: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v28, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v62, vcc +; %bb.2230: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2231: + v_bfe_u32 v19, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v61, v19, s7 + ; implicit-def: $vgpr61 +; %bb.2232: ; %Flow1270 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2233: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v29, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v61, vcc +; %bb.2234: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2235: + v_bfe_u32 v19, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v60, v19, s7 + ; implicit-def: $vgpr60 +; %bb.2236: ; %Flow1269 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2237: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v30, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v60, vcc +; %bb.2238: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2239: + v_bfe_u32 v19, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v59, v19, s7 + ; implicit-def: $vgpr59 +; %bb.2240: ; %Flow1268 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2241: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v31, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v59, vcc +; %bb.2242: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2243: + v_bfe_u32 v19, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v58, v19, s7 + ; implicit-def: $vgpr58 +; %bb.2244: ; %Flow1267 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2245: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v32, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v58, vcc +; %bb.2246: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2247: + v_bfe_u32 v19, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v57, v19, s7 + ; implicit-def: $vgpr57 +; %bb.2248: ; %Flow1266 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2249: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v33, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v57, vcc +; %bb.2250: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2251: + v_bfe_u32 v19, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v55, v19, s7 + ; implicit-def: $vgpr55 +; %bb.2252: ; %Flow1265 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2253: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v34, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v55, vcc +; %bb.2254: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2255: + v_bfe_u32 v19, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v56, v19, s7 + ; implicit-def: $vgpr56 +; %bb.2256: ; %Flow1264 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2257: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v35, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v56, vcc +; %bb.2258: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2259: + v_bfe_u32 v19, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v54, v19, s7 + ; implicit-def: $vgpr54 +; %bb.2260: ; %Flow1263 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2261: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v36, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v54, vcc +; %bb.2262: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2263: + v_bfe_u32 v19, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v53, v19, s7 + ; implicit-def: $vgpr53 +; %bb.2264: ; %Flow1262 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2265: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v37, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v37, v53, vcc +; %bb.2266: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2267: + v_bfe_u32 v19, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v52, v19, s7 + ; implicit-def: $vgpr52 +; %bb.2268: ; %Flow1261 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2269: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v38, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v52, vcc +; %bb.2270: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2271: + v_bfe_u32 v19, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v51, v19, s7 + ; implicit-def: $vgpr51 +; %bb.2272: ; %Flow1260 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2273: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v39, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v51, vcc +; %bb.2274: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2275: + v_bfe_u32 v19, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v50, v19, s7 + ; implicit-def: $vgpr50 +; %bb.2276: ; %Flow1259 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2277: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v40, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v50, vcc +; %bb.2278: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2279: + v_bfe_u32 v19, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v49, v19, s7 + ; implicit-def: $vgpr49 +; %bb.2280: ; %Flow1258 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2281: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v41, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v49, vcc +; %bb.2282: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2283: + v_bfe_u32 v19, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v48, v19, s7 + ; implicit-def: $vgpr48 +; %bb.2284: ; %Flow1257 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2285: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v42, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v48, vcc +; %bb.2286: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2287: + v_bfe_u32 v19, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v47, v19, s7 + ; implicit-def: $vgpr47 +; %bb.2288: ; %Flow1256 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2289: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v43, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v47, vcc +; %bb.2290: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2291: + v_bfe_u32 v19, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v47, v46, v19, s7 + ; implicit-def: $vgpr46 +; %bb.2292: ; %Flow1255 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2293: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v47, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v47, v46, vcc +; %bb.2294: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2295: + v_bfe_u32 v19, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v46, v45, v19, s7 + ; implicit-def: $vgpr45 +; %bb.2296: ; %Flow1254 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2297: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v46, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v46, v45, vcc +; %bb.2298: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2299: + v_bfe_u32 v19, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v45, v44, v19, s7 + ; implicit-def: $vgpr44 +; %bb.2300: ; %Flow1253 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2301: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v45, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v45, v44, vcc +; %bb.2302: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2303: + v_bfe_u32 v19, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v44, v70, v19, s7 + ; implicit-def: $vgpr70 +; %bb.2304: ; %Flow1252 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2305: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v44, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v44, v70, vcc +; %bb.2306: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2307: + v_bfe_u32 v19, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v48, v255, v19, s7 + ; implicit-def: $vgpr255 +; %bb.2308: ; %Flow1251 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2309: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v48, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v48, v255, vcc +; %bb.2310: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2311: + v_bfe_u32 v19, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v49, v254, v19, s7 + ; implicit-def: $vgpr254 +; %bb.2312: ; %Flow1250 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2313: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v49, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v49, v254, vcc +; %bb.2314: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2315: + v_bfe_u32 v19, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v50, v253, v19, s7 + ; implicit-def: $vgpr253 +; %bb.2316: ; %Flow1249 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2317: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v50, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v50, v253, vcc +; %bb.2318: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_add_i32 s2, s4, 0x7fffffff + s_mul_i32 s2, s2, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_i32 s5, s5, s3 + s_lshl_b32 s4, s5, 1 + v_and_b32_e32 v19, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v51, 3, v1 + v_and_or_b32 v51, v51, 12, s2 + v_lshlrev_b32_e32 v51, 7, v51 + v_and_b32_e32 v52, 7, v1 + v_lshl_or_b32 v51, v52, 1, v51 + v_lshlrev_b32_e32 v19, 1, v19 + s_and_b32 s2, s6, 64 + v_or3_b32 v19, v51, v19, s2 + ds_write_b16_d16_hi v19, v18 + ds_write_b16_d16_hi v19, v20 offset:128 + ds_write_b16_d16_hi v19, v21 offset:256 + ds_write_b16_d16_hi v19, v22 offset:384 + ds_write_b16_d16_hi v19, v23 offset:1024 + ds_write_b16_d16_hi v19, v24 offset:1152 + ds_write_b16_d16_hi v19, v25 offset:1280 + ds_write_b16_d16_hi v19, v26 offset:1408 + ds_write_b16_d16_hi v19, v27 offset:2048 + ds_write_b16_d16_hi v19, v28 offset:2176 + ds_write_b16_d16_hi v19, v29 offset:2304 + ds_write_b16_d16_hi v19, v30 offset:2432 + ds_write_b16_d16_hi v19, v31 offset:3072 + ds_write_b16_d16_hi v19, v32 offset:3200 + ds_write_b16_d16_hi v19, v33 offset:3328 + ds_write_b16_d16_hi v19, v34 offset:3456 + ds_write_b16_d16_hi v19, v35 offset:8192 + ds_write_b16_d16_hi v19, v36 offset:8320 + ds_write_b16_d16_hi v19, v37 offset:8448 + ds_write_b16_d16_hi v19, v38 offset:8576 + ds_write_b16_d16_hi v19, v39 offset:9216 + ds_write_b16_d16_hi v19, v40 offset:9344 + ds_write_b16_d16_hi v19, v41 offset:9472 + ds_write_b16_d16_hi v19, v42 offset:9600 + ds_write_b16_d16_hi v19, v43 offset:10240 + ds_write_b16_d16_hi v19, v47 offset:10368 + ds_write_b16_d16_hi v19, v46 offset:10496 + ds_write_b16_d16_hi v19, v45 offset:10624 + ds_write_b16_d16_hi v19, v44 offset:11264 + ds_write_b16_d16_hi v19, v48 offset:11392 + ds_write_b16_d16_hi v19, v49 offset:11520 + ds_write_b16_d16_hi v19, v50 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v20, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v1, 1, v1 + v_and_b32_e32 v1, 60, v1 + v_add_u32_e32 v18, s2, v1 + v_lshlrev_b32_e32 v21, 7, v18 + v_lshl_or_b32 v21, v20, 1, v21 + ds_read_b128 v[24:27], v21 + ds_read_b128 v[28:31], v21 offset:128 + ds_read_b128 v[32:35], v21 offset:256 + ds_read_b128 v[36:39], v21 offset:384 + v_add_u32_e32 v21, s18, v18 + v_or_b32_e32 v18, s19, v20 + v_mad_u64_u32 v[22:23], s[2:3], v21, s16, v[18:19] + s_add_i32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v21, 1, v22 + s_waitcnt lgkmcnt(3) + s_nop 0 + buffer_store_dwordx2 v[24:25], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v21, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v22 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v22, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v21 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v22, s[0:3], 8 offen + v_add_lshl_u32 v21, v21, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v21, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s4, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2319: + v_bfe_u32 v21, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v252, v21, s6 + ; implicit-def: $vgpr252 +; %bb.2320: ; %Flow1248 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2321: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v252, vcc +; %bb.2322: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2323: + v_bfe_u32 v22, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v251, v22, s6 + ; implicit-def: $vgpr251 +; %bb.2324: ; %Flow1247 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2325: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v251, vcc +; %bb.2326: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2327: + v_bfe_u32 v23, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v250, v23, s6 + ; implicit-def: $vgpr250 +; %bb.2328: ; %Flow1246 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2329: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v250, vcc +; %bb.2330: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2331: + v_bfe_u32 v24, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v249, v24, s6 + ; implicit-def: $vgpr249 +; %bb.2332: ; %Flow1245 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2333: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v249, vcc +; %bb.2334: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2335: + v_bfe_u32 v25, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v248, v25, s6 + ; implicit-def: $vgpr248 +; %bb.2336: ; %Flow1244 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2337: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v248, vcc +; %bb.2338: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2339: + v_bfe_u32 v26, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v247, v26, s6 + ; implicit-def: $vgpr247 +; %bb.2340: ; %Flow1243 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2341: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v247, vcc +; %bb.2342: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2343: + v_bfe_u32 v27, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v246, v27, s6 + ; implicit-def: $vgpr246 +; %bb.2344: ; %Flow1242 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2345: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v246, vcc +; %bb.2346: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2347: + v_bfe_u32 v28, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v245, v28, s6 + ; implicit-def: $vgpr245 +; %bb.2348: ; %Flow1241 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2349: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v245, vcc +; %bb.2350: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2351: + v_bfe_u32 v29, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v244, v29, s6 + ; implicit-def: $vgpr244 +; %bb.2352: ; %Flow1240 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2353: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v244, vcc +; %bb.2354: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2355: + v_bfe_u32 v30, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v243, v30, s6 + ; implicit-def: $vgpr243 +; %bb.2356: ; %Flow1239 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2357: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v243, vcc +; %bb.2358: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2359: + v_bfe_u32 v31, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v242, v31, s6 + ; implicit-def: $vgpr242 +; %bb.2360: ; %Flow1238 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2361: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v242, vcc +; %bb.2362: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2363: + v_bfe_u32 v32, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v241, v32, s6 + ; implicit-def: $vgpr241 +; %bb.2364: ; %Flow1237 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2365: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v241, vcc +; %bb.2366: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2367: + v_bfe_u32 v33, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v240, v33, s6 + ; implicit-def: $vgpr240 +; %bb.2368: ; %Flow1236 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2369: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v240, vcc +; %bb.2370: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2371: + v_bfe_u32 v34, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v239, v34, s6 + ; implicit-def: $vgpr239 +; %bb.2372: ; %Flow1235 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2373: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v239, vcc +; %bb.2374: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2375: + v_bfe_u32 v35, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v238, v35, s6 + ; implicit-def: $vgpr238 +; %bb.2376: ; %Flow1234 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2377: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v238, vcc +; %bb.2378: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2379: + v_bfe_u32 v36, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v236, v36, s6 + ; implicit-def: $vgpr236 +; %bb.2380: ; %Flow1233 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2381: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v236, vcc +; %bb.2382: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2383: + v_bfe_u32 v37, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v237, v37, s6 + ; implicit-def: $vgpr237 +; %bb.2384: ; %Flow1232 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2385: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v237, vcc +; %bb.2386: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2387: + v_bfe_u32 v38, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v235, v38, s6 + ; implicit-def: $vgpr235 +; %bb.2388: ; %Flow1231 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2389: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v235, vcc +; %bb.2390: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2391: + v_bfe_u32 v39, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v234, v39, s6 + ; implicit-def: $vgpr234 +; %bb.2392: ; %Flow1230 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2393: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v234, vcc +; %bb.2394: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2395: + v_bfe_u32 v40, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v233, v40, s6 + ; implicit-def: $vgpr233 +; %bb.2396: ; %Flow1229 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2397: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v233, vcc +; %bb.2398: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2399: + v_bfe_u32 v41, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v232, v41, s6 + ; implicit-def: $vgpr232 +; %bb.2400: ; %Flow1228 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2401: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v232, vcc +; %bb.2402: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2403: + v_bfe_u32 v42, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v231, v42, s6 + ; implicit-def: $vgpr231 +; %bb.2404: ; %Flow1227 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2405: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v231, vcc +; %bb.2406: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2407: + v_bfe_u32 v43, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v230, v43, s6 + ; implicit-def: $vgpr230 +; %bb.2408: ; %Flow1226 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2409: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v230, vcc +; %bb.2410: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2411: + v_bfe_u32 v44, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v229, v44, s6 + ; implicit-def: $vgpr229 +; %bb.2412: ; %Flow1225 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2413: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v229, vcc +; %bb.2414: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2415: + v_bfe_u32 v45, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v228, v45, s6 + ; implicit-def: $vgpr228 +; %bb.2416: ; %Flow1224 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2417: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v228, vcc +; %bb.2418: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2419: + v_bfe_u32 v46, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v227, v46, s6 + ; implicit-def: $vgpr227 +; %bb.2420: ; %Flow1223 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2421: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v227, vcc +; %bb.2422: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2423: + v_bfe_u32 v47, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v226, v47, s6 + ; implicit-def: $vgpr226 +; %bb.2424: ; %Flow1222 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2425: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v226, vcc +; %bb.2426: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2427: + v_bfe_u32 v48, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v225, v48, s6 + ; implicit-def: $vgpr225 +; %bb.2428: ; %Flow1221 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2429: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v225, vcc +; %bb.2430: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2431: + v_bfe_u32 v49, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v224, v49, s6 + ; implicit-def: $vgpr224 +; %bb.2432: ; %Flow1220 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2433: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v224, vcc +; %bb.2434: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2435: + v_bfe_u32 v50, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v223, v50, s6 + ; implicit-def: $vgpr223 +; %bb.2436: ; %Flow1219 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2437: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v223, vcc +; %bb.2438: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2439: + v_bfe_u32 v51, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v222, v51, s6 + ; implicit-def: $vgpr222 +; %bb.2440: ; %Flow1218 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2441: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v222, vcc +; %bb.2442: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2443: + v_bfe_u32 v52, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v221, v52, s6 + ; implicit-def: $vgpr221 +; %bb.2444: ; %Flow1217 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2445: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v221, vcc +; %bb.2446: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_287 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v21 + ds_write_b16_d16_hi v19, v22 offset:128 + ds_write_b16_d16_hi v19, v23 offset:256 + ds_write_b16_d16_hi v19, v24 offset:384 + ds_write_b16_d16_hi v19, v25 offset:1024 + ds_write_b16_d16_hi v19, v26 offset:1152 + ds_write_b16_d16_hi v19, v27 offset:1280 + ds_write_b16_d16_hi v19, v28 offset:1408 + ds_write_b16_d16_hi v19, v29 offset:2048 + ds_write_b16_d16_hi v19, v30 offset:2176 + ds_write_b16_d16_hi v19, v31 offset:2304 + ds_write_b16_d16_hi v19, v32 offset:2432 + ds_write_b16_d16_hi v19, v33 offset:3072 + ds_write_b16_d16_hi v19, v34 offset:3200 + ds_write_b16_d16_hi v19, v35 offset:3328 + ds_write_b16_d16_hi v19, v36 offset:3456 + ds_write_b16_d16_hi v19, v37 offset:8192 + ds_write_b16_d16_hi v19, v38 offset:8320 + ds_write_b16_d16_hi v19, v39 offset:8448 + ds_write_b16_d16_hi v19, v40 offset:8576 + ds_write_b16_d16_hi v19, v41 offset:9216 + ds_write_b16_d16_hi v19, v42 offset:9344 + ds_write_b16_d16_hi v19, v43 offset:9472 + ds_write_b16_d16_hi v19, v44 offset:9600 + ds_write_b16_d16_hi v19, v45 offset:10240 + ds_write_b16_d16_hi v19, v46 offset:10368 + ds_write_b16_d16_hi v19, v47 offset:10496 + ds_write_b16_d16_hi v19, v48 offset:10624 + ds_write_b16_d16_hi v19, v49 offset:11264 + ds_write_b16_d16_hi v19, v50 offset:11392 + ds_write_b16_d16_hi v19, v51 offset:11520 + ds_write_b16_d16_hi v19, v52 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshlrev_b32_e32 v21, 1, v20 + v_lshl_or_b32 v20, v22, 7, v21 + ds_read_b128 v[24:27], v20 + ds_read_b128 v[28:31], v20 offset:128 + ds_read_b128 v[32:35], v20 offset:256 + ds_read_b128 v[36:39], v20 offset:384 + v_add_u32_e32 v22, s18, v22 + v_or_b32_e32 v20, 64, v18 + v_mad_u64_u32 v[22:23], s[4:5], v22, s16, v[20:21] + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v23, s[0:3], 8 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v22, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2447: + v_bfe_u32 v22, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v220, v22, s6 + ; implicit-def: $vgpr220 +; %bb.2448: ; %Flow1216 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2449: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v220, vcc +; %bb.2450: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i352.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2451: + v_bfe_u32 v23, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v219, v23, s6 + ; implicit-def: $vgpr219 +; %bb.2452: ; %Flow1215 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2453: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v219, vcc +; %bb.2454: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i355.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2455: + v_bfe_u32 v24, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v218, v24, s6 + ; implicit-def: $vgpr218 +; %bb.2456: ; %Flow1214 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2457: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v218, vcc +; %bb.2458: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i358.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2459: + v_bfe_u32 v25, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v217, v25, s6 + ; implicit-def: $vgpr217 +; %bb.2460: ; %Flow1213 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2461: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v217, vcc +; %bb.2462: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i361.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2463: + v_bfe_u32 v26, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v216, v26, s6 + ; implicit-def: $vgpr216 +; %bb.2464: ; %Flow1212 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2465: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v216, vcc +; %bb.2466: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i364.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2467: + v_bfe_u32 v27, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v215, v27, s6 + ; implicit-def: $vgpr215 +; %bb.2468: ; %Flow1211 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2469: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v215, vcc +; %bb.2470: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i367.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2471: + v_bfe_u32 v28, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v214, v28, s6 + ; implicit-def: $vgpr214 +; %bb.2472: ; %Flow1210 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2473: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v214, vcc +; %bb.2474: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i370.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2475: + v_bfe_u32 v29, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v213, v29, s6 + ; implicit-def: $vgpr213 +; %bb.2476: ; %Flow1209 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2477: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v213, vcc +; %bb.2478: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i373.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2479: + v_bfe_u32 v30, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v212, v30, s6 + ; implicit-def: $vgpr212 +; %bb.2480: ; %Flow1208 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2481: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v212, vcc +; %bb.2482: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i376.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2483: + v_bfe_u32 v31, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v211, v31, s6 + ; implicit-def: $vgpr211 +; %bb.2484: ; %Flow1207 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2485: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v211, vcc +; %bb.2486: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i379.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2487: + v_bfe_u32 v32, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v210, v32, s6 + ; implicit-def: $vgpr210 +; %bb.2488: ; %Flow1206 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2489: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v210, vcc +; %bb.2490: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i382.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2491: + v_bfe_u32 v33, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v209, v33, s6 + ; implicit-def: $vgpr209 +; %bb.2492: ; %Flow1205 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2493: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v209, vcc +; %bb.2494: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i385.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2495: + v_bfe_u32 v34, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v208, v34, s6 + ; implicit-def: $vgpr208 +; %bb.2496: ; %Flow1204 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2497: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v208, vcc +; %bb.2498: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i388.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2499: + v_bfe_u32 v35, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v207, v35, s6 + ; implicit-def: $vgpr207 +; %bb.2500: ; %Flow1203 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2501: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v207, vcc +; %bb.2502: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i391.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2503: + v_bfe_u32 v36, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v206, v36, s6 + ; implicit-def: $vgpr206 +; %bb.2504: ; %Flow1202 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2505: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v206, vcc +; %bb.2506: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i394.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2507: + v_bfe_u32 v37, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v204, v37, s6 + ; implicit-def: $vgpr204 +; %bb.2508: ; %Flow1201 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2509: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v204, vcc +; %bb.2510: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i397.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2511: + v_bfe_u32 v38, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v205, v38, s6 + ; implicit-def: $vgpr205 +; %bb.2512: ; %Flow1200 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2513: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v205, vcc +; %bb.2514: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i400.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2515: + v_bfe_u32 v39, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v203, v39, s6 + ; implicit-def: $vgpr203 +; %bb.2516: ; %Flow1199 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2517: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v203, vcc +; %bb.2518: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i403.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2519: + v_bfe_u32 v40, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v202, v40, s6 + ; implicit-def: $vgpr202 +; %bb.2520: ; %Flow1198 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2521: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v202, vcc +; %bb.2522: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i406.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2523: + v_bfe_u32 v41, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v201, v41, s6 + ; implicit-def: $vgpr201 +; %bb.2524: ; %Flow1197 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2525: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v201, vcc +; %bb.2526: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i409.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2527: + v_bfe_u32 v42, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v200, v42, s6 + ; implicit-def: $vgpr200 +; %bb.2528: ; %Flow1196 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2529: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v200, vcc +; %bb.2530: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i412.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2531: + v_bfe_u32 v43, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v199, v43, s6 + ; implicit-def: $vgpr199 +; %bb.2532: ; %Flow1195 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2533: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v199, vcc +; %bb.2534: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i415.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2535: + v_bfe_u32 v44, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v198, v44, s6 + ; implicit-def: $vgpr198 +; %bb.2536: ; %Flow1194 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2537: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v198, vcc +; %bb.2538: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i418.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2539: + v_bfe_u32 v45, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v197, v45, s6 + ; implicit-def: $vgpr197 +; %bb.2540: ; %Flow1193 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2541: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v197, vcc +; %bb.2542: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i421.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2543: + v_bfe_u32 v46, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v196, v46, s6 + ; implicit-def: $vgpr196 +; %bb.2544: ; %Flow1192 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2545: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v196, vcc +; %bb.2546: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i424.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2547: + v_bfe_u32 v47, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v195, v47, s6 + ; implicit-def: $vgpr195 +; %bb.2548: ; %Flow1191 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2549: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v195, vcc +; %bb.2550: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i427.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2551: + v_bfe_u32 v48, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v194, v48, s6 + ; implicit-def: $vgpr194 +; %bb.2552: ; %Flow1190 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2553: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v194, vcc +; %bb.2554: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i430.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2555: + v_bfe_u32 v49, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v193, v49, s6 + ; implicit-def: $vgpr193 +; %bb.2556: ; %Flow1189 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2557: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v193, vcc +; %bb.2558: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i433.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2559: + v_bfe_u32 v50, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v192, v50, s6 + ; implicit-def: $vgpr192 +; %bb.2560: ; %Flow1188 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2561: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v192, vcc +; %bb.2562: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i436.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2563: + v_bfe_u32 v51, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v191, v51, s6 + ; implicit-def: $vgpr191 +; %bb.2564: ; %Flow1187 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2565: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v191, vcc +; %bb.2566: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i439.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2567: + v_bfe_u32 v52, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v190, v52, s6 + ; implicit-def: $vgpr190 +; %bb.2568: ; %Flow1186 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2569: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v190, vcc +; %bb.2570: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i442.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2571: + v_bfe_u32 v53, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v189, v53, s6 + ; implicit-def: $vgpr189 +; %bb.2572: ; %Flow1185 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2573: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v189, vcc +; %bb.2574: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_574 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v22 + ds_write_b16_d16_hi v19, v23 offset:128 + ds_write_b16_d16_hi v19, v24 offset:256 + ds_write_b16_d16_hi v19, v25 offset:384 + ds_write_b16_d16_hi v19, v26 offset:1024 + ds_write_b16_d16_hi v19, v27 offset:1152 + ds_write_b16_d16_hi v19, v28 offset:1280 + ds_write_b16_d16_hi v19, v29 offset:1408 + ds_write_b16_d16_hi v19, v30 offset:2048 + ds_write_b16_d16_hi v19, v31 offset:2176 + ds_write_b16_d16_hi v19, v32 offset:2304 + ds_write_b16_d16_hi v19, v33 offset:2432 + ds_write_b16_d16_hi v19, v34 offset:3072 + ds_write_b16_d16_hi v19, v35 offset:3200 + ds_write_b16_d16_hi v19, v36 offset:3328 + ds_write_b16_d16_hi v19, v37 offset:3456 + ds_write_b16_d16_hi v19, v38 offset:8192 + ds_write_b16_d16_hi v19, v39 offset:8320 + ds_write_b16_d16_hi v19, v40 offset:8448 + ds_write_b16_d16_hi v19, v41 offset:8576 + ds_write_b16_d16_hi v19, v42 offset:9216 + ds_write_b16_d16_hi v19, v43 offset:9344 + ds_write_b16_d16_hi v19, v44 offset:9472 + ds_write_b16_d16_hi v19, v45 offset:9600 + ds_write_b16_d16_hi v19, v46 offset:10240 + ds_write_b16_d16_hi v19, v47 offset:10368 + ds_write_b16_d16_hi v19, v48 offset:10496 + ds_write_b16_d16_hi v19, v49 offset:10624 + ds_write_b16_d16_hi v19, v50 offset:11264 + ds_write_b16_d16_hi v19, v51 offset:11392 + ds_write_b16_d16_hi v19, v52 offset:11520 + ds_write_b16_d16_hi v19, v53 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshl_or_b32 v23, v22, 7, v21 + ds_read_b128 v[26:29], v23 + ds_read_b128 v[30:33], v23 offset:128 + ds_read_b128 v[34:37], v23 offset:256 + ds_read_b128 v[38:41], v23 offset:384 + v_add_u32_e32 v23, s18, v22 + v_or_b32_e32 v22, 0x80, v18 + v_mad_u64_u32 v[24:25], s[4:5], v23, s16, v[22:23] + v_lshlrev_b32_e32 v23, 1, v24 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[26:27], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v24 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[30:31], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[32:33], v24, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[34:35], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[36:37], v24, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[38:39], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[40:41], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2575: + v_bfe_u32 v23, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v188, v23, s6 + ; implicit-def: $vgpr188 +; %bb.2576: ; %Flow1184 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2577: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v188, vcc +; %bb.2578: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i639.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2579: + v_bfe_u32 v24, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v187, v24, s6 + ; implicit-def: $vgpr187 +; %bb.2580: ; %Flow1183 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2581: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v187, vcc +; %bb.2582: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i642.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2583: + v_bfe_u32 v25, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v186, v25, s6 + ; implicit-def: $vgpr186 +; %bb.2584: ; %Flow1182 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2585: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v186, vcc +; %bb.2586: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i645.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2587: + v_bfe_u32 v26, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v185, v26, s6 + ; implicit-def: $vgpr185 +; %bb.2588: ; %Flow1181 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2589: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v185, vcc +; %bb.2590: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i648.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2591: + v_bfe_u32 v27, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v184, v27, s6 + ; implicit-def: $vgpr184 +; %bb.2592: ; %Flow1180 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2593: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v184, vcc +; %bb.2594: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i651.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2595: + v_bfe_u32 v28, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v183, v28, s6 + ; implicit-def: $vgpr183 +; %bb.2596: ; %Flow1179 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2597: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v183, vcc +; %bb.2598: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i654.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2599: + v_bfe_u32 v29, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v182, v29, s6 + ; implicit-def: $vgpr182 +; %bb.2600: ; %Flow1178 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2601: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v182, vcc +; %bb.2602: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i657.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2603: + v_bfe_u32 v30, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v181, v30, s6 + ; implicit-def: $vgpr181 +; %bb.2604: ; %Flow1177 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2605: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v181, vcc +; %bb.2606: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i660.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2607: + v_bfe_u32 v31, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v180, v31, s6 + ; implicit-def: $vgpr180 +; %bb.2608: ; %Flow1176 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2609: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v180, vcc +; %bb.2610: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i663.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2611: + v_bfe_u32 v32, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v179, v32, s6 + ; implicit-def: $vgpr179 +; %bb.2612: ; %Flow1175 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2613: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v179, vcc +; %bb.2614: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i666.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2615: + v_bfe_u32 v33, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v178, v33, s6 + ; implicit-def: $vgpr178 +; %bb.2616: ; %Flow1174 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2617: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v178, vcc +; %bb.2618: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i669.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2619: + v_bfe_u32 v34, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v177, v34, s6 + ; implicit-def: $vgpr177 +; %bb.2620: ; %Flow1173 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2621: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v177, vcc +; %bb.2622: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i672.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2623: + v_bfe_u32 v35, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v176, v35, s6 + ; implicit-def: $vgpr176 +; %bb.2624: ; %Flow1172 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2625: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v176, vcc +; %bb.2626: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i675.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2627: + v_bfe_u32 v36, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v175, v36, s6 + ; implicit-def: $vgpr175 +; %bb.2628: ; %Flow1171 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2629: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v175, vcc +; %bb.2630: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i678.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2631: + v_bfe_u32 v37, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v174, v37, s6 + ; implicit-def: $vgpr174 +; %bb.2632: ; %Flow1170 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2633: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v174, vcc +; %bb.2634: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i681.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2635: + v_bfe_u32 v38, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v172, v38, s6 + ; implicit-def: $vgpr172 +; %bb.2636: ; %Flow1169 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2637: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v172, vcc +; %bb.2638: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i684.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2639: + v_bfe_u32 v39, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v173, v39, s6 + ; implicit-def: $vgpr173 +; %bb.2640: ; %Flow1168 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2641: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v173, vcc +; %bb.2642: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i687.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2643: + v_bfe_u32 v40, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v171, v40, s6 + ; implicit-def: $vgpr171 +; %bb.2644: ; %Flow1167 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2645: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v171, vcc +; %bb.2646: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i690.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2647: + v_bfe_u32 v41, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v170, v41, s6 + ; implicit-def: $vgpr170 +; %bb.2648: ; %Flow1166 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2649: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v170, vcc +; %bb.2650: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i693.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2651: + v_bfe_u32 v42, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v169, v42, s6 + ; implicit-def: $vgpr169 +; %bb.2652: ; %Flow1165 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2653: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v169, vcc +; %bb.2654: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i696.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2655: + v_bfe_u32 v43, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v168, v43, s6 + ; implicit-def: $vgpr168 +; %bb.2656: ; %Flow1164 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2657: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v168, vcc +; %bb.2658: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i699.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2659: + v_bfe_u32 v44, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v167, v44, s6 + ; implicit-def: $vgpr167 +; %bb.2660: ; %Flow1163 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2661: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v167, vcc +; %bb.2662: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i702.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2663: + v_bfe_u32 v45, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v166, v45, s6 + ; implicit-def: $vgpr166 +; %bb.2664: ; %Flow1162 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2665: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v166, vcc +; %bb.2666: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i705.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2667: + v_bfe_u32 v46, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v165, v46, s6 + ; implicit-def: $vgpr165 +; %bb.2668: ; %Flow1161 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2669: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v165, vcc +; %bb.2670: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i708.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2671: + v_bfe_u32 v47, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v164, v47, s6 + ; implicit-def: $vgpr164 +; %bb.2672: ; %Flow1160 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2673: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v164, vcc +; %bb.2674: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i711.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2675: + v_bfe_u32 v48, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v163, v48, s6 + ; implicit-def: $vgpr163 +; %bb.2676: ; %Flow1159 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2677: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v163, vcc +; %bb.2678: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i714.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2679: + v_bfe_u32 v49, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v162, v49, s6 + ; implicit-def: $vgpr162 +; %bb.2680: ; %Flow1158 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2681: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v162, vcc +; %bb.2682: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i717.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2683: + v_bfe_u32 v50, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v161, v50, s6 + ; implicit-def: $vgpr161 +; %bb.2684: ; %Flow1157 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2685: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v161, vcc +; %bb.2686: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i720.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2687: + v_bfe_u32 v51, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v160, v51, s6 + ; implicit-def: $vgpr160 +; %bb.2688: ; %Flow1156 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2689: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v160, vcc +; %bb.2690: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i723.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2691: + v_bfe_u32 v52, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v159, v52, s6 + ; implicit-def: $vgpr159 +; %bb.2692: ; %Flow1155 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2693: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v159, vcc +; %bb.2694: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i726.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2695: + v_bfe_u32 v53, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v158, v53, s6 + ; implicit-def: $vgpr158 +; %bb.2696: ; %Flow1154 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2697: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v158, vcc +; %bb.2698: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i729.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v54, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s4, v54 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2699: + v_bfe_u32 v54, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v157, v54, s6 + ; implicit-def: $vgpr157 +; %bb.2700: ; %Flow1153 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2701: + v_mov_b32_e32 v54, 0 + v_or_b32_e32 v55, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v54 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v55, v157, vcc +; %bb.2702: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_861 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v24 offset:128 + ds_write_b16_d16_hi v19, v25 offset:256 + ds_write_b16_d16_hi v19, v26 offset:384 + ds_write_b16_d16_hi v19, v27 offset:1024 + ds_write_b16_d16_hi v19, v28 offset:1152 + ds_write_b16_d16_hi v19, v29 offset:1280 + ds_write_b16_d16_hi v19, v30 offset:1408 + ds_write_b16_d16_hi v19, v31 offset:2048 + ds_write_b16_d16_hi v19, v32 offset:2176 + ds_write_b16_d16_hi v19, v33 offset:2304 + ds_write_b16_d16_hi v19, v34 offset:2432 + ds_write_b16_d16_hi v19, v35 offset:3072 + ds_write_b16_d16_hi v19, v36 offset:3200 + ds_write_b16_d16_hi v19, v37 offset:3328 + ds_write_b16_d16_hi v19, v38 offset:3456 + ds_write_b16_d16_hi v19, v39 offset:8192 + ds_write_b16_d16_hi v19, v40 offset:8320 + ds_write_b16_d16_hi v19, v41 offset:8448 + ds_write_b16_d16_hi v19, v42 offset:8576 + ds_write_b16_d16_hi v19, v43 offset:9216 + ds_write_b16_d16_hi v19, v44 offset:9344 + ds_write_b16_d16_hi v19, v45 offset:9472 + ds_write_b16_d16_hi v19, v46 offset:9600 + ds_write_b16_d16_hi v19, v47 offset:10240 + ds_write_b16_d16_hi v19, v48 offset:10368 + ds_write_b16_d16_hi v19, v49 offset:10496 + ds_write_b16_d16_hi v19, v50 offset:10624 + ds_write_b16_d16_hi v19, v51 offset:11264 + ds_write_b16_d16_hi v19, v52 offset:11392 + ds_write_b16_d16_hi v19, v53 offset:11520 + ds_write_b16_d16_hi v19, v54 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v23, s4, v1 + v_lshl_or_b32 v24, v23, 7, v21 + ds_read_b128 v[28:31], v24 + ds_read_b128 v[32:35], v24 offset:128 + ds_read_b128 v[36:39], v24 offset:256 + ds_read_b128 v[40:43], v24 offset:384 + v_add_u32_e32 v23, s18, v23 + v_or_b32_e32 v24, 0xc0, v18 + v_mad_u64_u32 v[26:27], s[4:5], v23, s16, v[24:25] + v_lshlrev_b32_e32 v23, 1, v26 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v26 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[32:33], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v25, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[36:37], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v25, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[40:41], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[42:43], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2703: + v_bfe_u32 v23, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v156, v23, s6 + ; implicit-def: $vgpr156 +; %bb.2704: ; %Flow1152 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2705: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v25, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v25, v156, vcc +; %bb.2706: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i926.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2707: + v_bfe_u32 v25, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v155, v25, s6 + ; implicit-def: $vgpr155 +; %bb.2708: ; %Flow1151 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2709: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v155, vcc +; %bb.2710: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i929.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2711: + v_bfe_u32 v26, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v154, v26, s6 + ; implicit-def: $vgpr154 +; %bb.2712: ; %Flow1150 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2713: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v154, vcc +; %bb.2714: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i932.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2715: + v_bfe_u32 v27, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v153, v27, s6 + ; implicit-def: $vgpr153 +; %bb.2716: ; %Flow1149 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2717: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v153, vcc +; %bb.2718: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i935.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2719: + v_bfe_u32 v28, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v152, v28, s6 + ; implicit-def: $vgpr152 +; %bb.2720: ; %Flow1148 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2721: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v152, vcc +; %bb.2722: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i938.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2723: + v_bfe_u32 v29, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v151, v29, s6 + ; implicit-def: $vgpr151 +; %bb.2724: ; %Flow1147 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2725: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v151, vcc +; %bb.2726: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i941.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2727: + v_bfe_u32 v30, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v150, v30, s6 + ; implicit-def: $vgpr150 +; %bb.2728: ; %Flow1146 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2729: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v150, vcc +; %bb.2730: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i944.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2731: + v_bfe_u32 v31, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v149, v31, s6 + ; implicit-def: $vgpr149 +; %bb.2732: ; %Flow1145 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2733: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v149, vcc +; %bb.2734: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i947.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2735: + v_bfe_u32 v32, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v148, v32, s6 + ; implicit-def: $vgpr148 +; %bb.2736: ; %Flow1144 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2737: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v148, vcc +; %bb.2738: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i950.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2739: + v_bfe_u32 v33, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v147, v33, s6 + ; implicit-def: $vgpr147 +; %bb.2740: ; %Flow1143 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2741: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v147, vcc +; %bb.2742: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i953.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2743: + v_bfe_u32 v34, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v146, v34, s6 + ; implicit-def: $vgpr146 +; %bb.2744: ; %Flow1142 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2745: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v146, vcc +; %bb.2746: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i956.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2747: + v_bfe_u32 v35, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v145, v35, s6 + ; implicit-def: $vgpr145 +; %bb.2748: ; %Flow1141 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2749: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v145, vcc +; %bb.2750: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i959.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2751: + v_bfe_u32 v36, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v144, v36, s6 + ; implicit-def: $vgpr144 +; %bb.2752: ; %Flow1140 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2753: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v144, vcc +; %bb.2754: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i962.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2755: + v_bfe_u32 v37, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v143, v37, s6 + ; implicit-def: $vgpr143 +; %bb.2756: ; %Flow1139 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2757: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v143, vcc +; %bb.2758: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i965.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2759: + v_bfe_u32 v38, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v142, v38, s6 + ; implicit-def: $vgpr142 +; %bb.2760: ; %Flow1138 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2761: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v142, vcc +; %bb.2762: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i968.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2763: + v_bfe_u32 v39, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v141, v39, s6 + ; implicit-def: $vgpr141 +; %bb.2764: ; %Flow1137 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2765: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v141, vcc +; %bb.2766: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i971.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2767: + v_bfe_u32 v40, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v2, v40, s6 +; %bb.2768: ; %Flow1136 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2769: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v2, vcc +; %bb.2770: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i974.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2771: + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v3, v2, s6 +; %bb.2772: ; %Flow1135 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2773: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v41, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v3, vcc +; %bb.2774: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i977.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2775: + v_bfe_u32 v2, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v4, v2, s6 +; %bb.2776: ; %Flow1134 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2777: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v3, v4, vcc +; %bb.2778: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i980.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2779: + v_bfe_u32 v2, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v5, v2, s6 +; %bb.2780: ; %Flow1133 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2781: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v3, v5, vcc +; %bb.2782: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i983.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2783: + v_bfe_u32 v2, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v6, v2, s6 +; %bb.2784: ; %Flow1132 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2785: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v3, v6, vcc +; %bb.2786: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i986.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2787: + v_bfe_u32 v2, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v7, v2, s6 +; %bb.2788: ; %Flow1131 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2789: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v3, v7, vcc +; %bb.2790: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i989.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2791: + v_bfe_u32 v2, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v8, v2, s6 +; %bb.2792: ; %Flow1130 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2793: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v3, v8, vcc +; %bb.2794: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i992.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2795: + v_bfe_u32 v2, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v9, v2, s6 +; %bb.2796: ; %Flow1129 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2797: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v3, v9, vcc +; %bb.2798: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i995.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2799: + v_bfe_u32 v2, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v10, v2, s6 +; %bb.2800: ; %Flow1128 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2801: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v3, v10, vcc +; %bb.2802: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i998.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2803: + v_bfe_u32 v2, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v11, v2, s6 +; %bb.2804: ; %Flow1127 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2805: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v3, v11, vcc +; %bb.2806: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1001.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2807: + v_bfe_u32 v2, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v12, v2, s6 +; %bb.2808: ; %Flow1126 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2809: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v3, v12, vcc +; %bb.2810: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1004.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2811: + v_bfe_u32 v2, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v13, v2, s6 +; %bb.2812: ; %Flow1125 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2813: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v3, v13, vcc +; %bb.2814: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1007.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2815: + v_bfe_u32 v2, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v14, v2, s6 +; %bb.2816: ; %Flow1124 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2817: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v3, v14, vcc +; %bb.2818: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1010.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2819: + v_bfe_u32 v2, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v15, v2, s6 +; %bb.2820: ; %Flow1123 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2821: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v3, v15, vcc +; %bb.2822: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1013.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2823: + v_bfe_u32 v2, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v16, v2, s6 +; %bb.2824: ; %Flow1122 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2825: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v3, v16, vcc +; %bb.2826: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1016.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr55 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2827: + v_bfe_u32 v2, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v55, v17, v2, s6 + ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 +; %bb.2828: ; %Flow1121 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2829: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v55, v3, v17, vcc +; %bb.2830: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1148 + s_or_b64 exec, exec, s[4:5] + s_bitset1_b32 s18, 7 + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v25 offset:128 + ds_write_b16_d16_hi v19, v26 offset:256 + ds_write_b16_d16_hi v19, v27 offset:384 + ds_write_b16_d16_hi v19, v28 offset:1024 + ds_write_b16_d16_hi v19, v29 offset:1152 + ds_write_b16_d16_hi v19, v30 offset:1280 + ds_write_b16_d16_hi v19, v31 offset:1408 + ds_write_b16_d16_hi v19, v32 offset:2048 + ds_write_b16_d16_hi v19, v33 offset:2176 + ds_write_b16_d16_hi v19, v34 offset:2304 + ds_write_b16_d16_hi v19, v35 offset:2432 + ds_write_b16_d16_hi v19, v36 offset:3072 + ds_write_b16_d16_hi v19, v37 offset:3200 + ds_write_b16_d16_hi v19, v38 offset:3328 + ds_write_b16_d16_hi v19, v39 offset:3456 + ds_write_b16_d16_hi v19, v40 offset:8192 + ds_write_b16_d16_hi v19, v41 offset:8320 + ds_write_b16_d16_hi v19, v42 offset:8448 + ds_write_b16_d16_hi v19, v43 offset:8576 + ds_write_b16_d16_hi v19, v44 offset:9216 + ds_write_b16_d16_hi v19, v45 offset:9344 + ds_write_b16_d16_hi v19, v46 offset:9472 + ds_write_b16_d16_hi v19, v47 offset:9600 + ds_write_b16_d16_hi v19, v48 offset:10240 + ds_write_b16_d16_hi v19, v49 offset:10368 + ds_write_b16_d16_hi v19, v50 offset:10496 + ds_write_b16_d16_hi v19, v51 offset:10624 + ds_write_b16_d16_hi v19, v52 offset:11264 + ds_write_b16_d16_hi v19, v53 offset:11392 + ds_write_b16_d16_hi v19, v54 offset:11520 + ds_write_b16_d16_hi v19, v55 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[26:29], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[24:25] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[26:27], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2831: + v_bfe_u32 v2, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v140, v2, s6 + ; implicit-def: $vgpr140 +; %bb.2832: ; %Flow1120 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2833: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v140, vcc +; %bb.2834: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1213.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2835: + v_bfe_u32 v3, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v139, v3, s6 + ; implicit-def: $vgpr139 +; %bb.2836: ; %Flow1119 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2837: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v139, vcc +; %bb.2838: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1216.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2839: + v_bfe_u32 v4, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v138, v4, s6 + ; implicit-def: $vgpr138 +; %bb.2840: ; %Flow1118 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2841: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v138, vcc +; %bb.2842: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1219.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2843: + v_bfe_u32 v5, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v137, v5, s6 + ; implicit-def: $vgpr137 +; %bb.2844: ; %Flow1117 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2845: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v137, vcc +; %bb.2846: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1222.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2847: + v_bfe_u32 v6, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v136, v6, s6 + ; implicit-def: $vgpr136 +; %bb.2848: ; %Flow1116 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2849: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v136, vcc +; %bb.2850: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1225.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2851: + v_bfe_u32 v7, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v135, v7, s6 + ; implicit-def: $vgpr135 +; %bb.2852: ; %Flow1115 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2853: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v135, vcc +; %bb.2854: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1228.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2855: + v_bfe_u32 v8, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v134, v8, s6 + ; implicit-def: $vgpr134 +; %bb.2856: ; %Flow1114 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2857: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v134, vcc +; %bb.2858: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1231.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2859: + v_bfe_u32 v9, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v133, v9, s6 + ; implicit-def: $vgpr133 +; %bb.2860: ; %Flow1113 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2861: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v133, vcc +; %bb.2862: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1234.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2863: + v_bfe_u32 v10, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v132, v10, s6 + ; implicit-def: $vgpr132 +; %bb.2864: ; %Flow1112 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2865: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v132, vcc +; %bb.2866: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1237.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2867: + v_bfe_u32 v11, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v131, v11, s6 + ; implicit-def: $vgpr131 +; %bb.2868: ; %Flow1111 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2869: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v131, vcc +; %bb.2870: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1240.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2871: + v_bfe_u32 v12, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v130, v12, s6 + ; implicit-def: $vgpr130 +; %bb.2872: ; %Flow1110 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2873: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v130, vcc +; %bb.2874: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1243.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2875: + v_bfe_u32 v13, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v129, v13, s6 + ; implicit-def: $vgpr129 +; %bb.2876: ; %Flow1109 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2877: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v129, vcc +; %bb.2878: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1246.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2879: + v_bfe_u32 v14, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v128, v14, s6 + ; implicit-def: $vgpr128 +; %bb.2880: ; %Flow1108 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2881: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v128, vcc +; %bb.2882: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1249.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2883: + v_bfe_u32 v15, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v127, v15, s6 + ; implicit-def: $vgpr127 +; %bb.2884: ; %Flow1107 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2885: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v127, vcc +; %bb.2886: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1252.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2887: + v_bfe_u32 v16, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v126, v16, s6 + ; implicit-def: $vgpr126 +; %bb.2888: ; %Flow1106 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2889: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v126, vcc +; %bb.2890: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1255.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2891: + v_bfe_u32 v17, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v124, v17, s6 + ; implicit-def: $vgpr124 +; %bb.2892: ; %Flow1105 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2893: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v23, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v23, v124, vcc +; %bb.2894: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1258.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2895: + v_bfe_u32 v23, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v125, v23, s6 + ; implicit-def: $vgpr125 +; %bb.2896: ; %Flow1104 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2897: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v125, vcc +; %bb.2898: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1261.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2899: + v_bfe_u32 v24, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v123, v24, s6 + ; implicit-def: $vgpr123 +; %bb.2900: ; %Flow1103 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2901: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v123, vcc +; %bb.2902: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1264.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2903: + v_bfe_u32 v25, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v122, v25, s6 + ; implicit-def: $vgpr122 +; %bb.2904: ; %Flow1102 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2905: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v122, vcc +; %bb.2906: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1267.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2907: + v_bfe_u32 v26, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v121, v26, s6 + ; implicit-def: $vgpr121 +; %bb.2908: ; %Flow1101 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2909: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v121, vcc +; %bb.2910: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1270.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2911: + v_bfe_u32 v27, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v120, v27, s6 + ; implicit-def: $vgpr120 +; %bb.2912: ; %Flow1100 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2913: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v120, vcc +; %bb.2914: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1273.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2915: + v_bfe_u32 v28, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v119, v28, s6 + ; implicit-def: $vgpr119 +; %bb.2916: ; %Flow1099 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2917: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v119, vcc +; %bb.2918: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1276.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2919: + v_bfe_u32 v29, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v118, v29, s6 + ; implicit-def: $vgpr118 +; %bb.2920: ; %Flow1098 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2921: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v118, vcc +; %bb.2922: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1279.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2923: + v_bfe_u32 v30, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v117, v30, s6 + ; implicit-def: $vgpr117 +; %bb.2924: ; %Flow1097 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2925: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v117, vcc +; %bb.2926: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1282.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2927: + v_bfe_u32 v31, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v116, v31, s6 + ; implicit-def: $vgpr116 +; %bb.2928: ; %Flow1096 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2929: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v116, vcc +; %bb.2930: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1285.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2931: + v_bfe_u32 v32, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v115, v32, s6 + ; implicit-def: $vgpr115 +; %bb.2932: ; %Flow1095 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2933: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v115, vcc +; %bb.2934: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1288.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2935: + v_bfe_u32 v33, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v114, v33, s6 + ; implicit-def: $vgpr114 +; %bb.2936: ; %Flow1094 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2937: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v114, vcc +; %bb.2938: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1291.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2939: + v_bfe_u32 v34, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v113, v34, s6 + ; implicit-def: $vgpr113 +; %bb.2940: ; %Flow1093 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2941: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v113, vcc +; %bb.2942: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1294.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2943: + v_bfe_u32 v35, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v112, v35, s6 + ; implicit-def: $vgpr112 +; %bb.2944: ; %Flow1092 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2945: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v112, vcc +; %bb.2946: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1297.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2947: + v_bfe_u32 v36, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v111, v36, s6 + ; implicit-def: $vgpr111 +; %bb.2948: ; %Flow1091 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2949: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v111, vcc +; %bb.2950: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1300.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2951: + v_bfe_u32 v37, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v110, v37, s6 + ; implicit-def: $vgpr110 +; %bb.2952: ; %Flow1090 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2953: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v110, vcc +; %bb.2954: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1303.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2955: + v_bfe_u32 v38, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v109, v38, s6 + ; implicit-def: $vgpr109 +; %bb.2956: ; %Flow1089 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2957: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v109, vcc +; %bb.2958: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1435 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v23 offset:8192 + ds_write_b16_d16_hi v19, v24 offset:8320 + ds_write_b16_d16_hi v19, v25 offset:8448 + ds_write_b16_d16_hi v19, v26 offset:8576 + ds_write_b16_d16_hi v19, v27 offset:9216 + ds_write_b16_d16_hi v19, v28 offset:9344 + ds_write_b16_d16_hi v19, v29 offset:9472 + ds_write_b16_d16_hi v19, v30 offset:9600 + ds_write_b16_d16_hi v19, v31 offset:10240 + ds_write_b16_d16_hi v19, v32 offset:10368 + ds_write_b16_d16_hi v19, v33 offset:10496 + ds_write_b16_d16_hi v19, v34 offset:10624 + ds_write_b16_d16_hi v19, v35 offset:11264 + ds_write_b16_d16_hi v19, v36 offset:11392 + ds_write_b16_d16_hi v19, v37 offset:11520 + ds_write_b16_d16_hi v19, v38 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[24:27], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[22:23] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[24:25], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2959: + v_bfe_u32 v2, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v108, v2, s6 + ; implicit-def: $vgpr108 +; %bb.2960: ; %Flow1088 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2961: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v108, vcc +; %bb.2962: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1500.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2963: + v_bfe_u32 v3, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v107, v3, s6 + ; implicit-def: $vgpr107 +; %bb.2964: ; %Flow1087 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2965: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v107, vcc +; %bb.2966: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1503.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2967: + v_bfe_u32 v4, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v106, v4, s6 + ; implicit-def: $vgpr106 +; %bb.2968: ; %Flow1086 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2969: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v106, vcc +; %bb.2970: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1506.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2971: + v_bfe_u32 v5, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v105, v5, s6 + ; implicit-def: $vgpr105 +; %bb.2972: ; %Flow1085 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2973: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v105, vcc +; %bb.2974: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1509.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2975: + v_bfe_u32 v6, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v104, v6, s6 + ; implicit-def: $vgpr104 +; %bb.2976: ; %Flow1084 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2977: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v104, vcc +; %bb.2978: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1512.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2979: + v_bfe_u32 v7, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v103, v7, s6 + ; implicit-def: $vgpr103 +; %bb.2980: ; %Flow1083 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2981: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v103, vcc +; %bb.2982: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1515.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2983: + v_bfe_u32 v8, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v102, v8, s6 + ; implicit-def: $vgpr102 +; %bb.2984: ; %Flow1082 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2985: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v102, vcc +; %bb.2986: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1518.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2987: + v_bfe_u32 v9, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v101, v9, s6 + ; implicit-def: $vgpr101 +; %bb.2988: ; %Flow1081 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2989: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v101, vcc +; %bb.2990: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1521.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2991: + v_bfe_u32 v10, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v100, v10, s6 + ; implicit-def: $vgpr100 +; %bb.2992: ; %Flow1080 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2993: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v100, vcc +; %bb.2994: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1524.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2995: + v_bfe_u32 v11, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v99, v11, s6 + ; implicit-def: $vgpr99 +; %bb.2996: ; %Flow1079 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2997: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v99, vcc +; %bb.2998: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1527.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2999: + v_bfe_u32 v12, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v98, v12, s6 + ; implicit-def: $vgpr98 +; %bb.3000: ; %Flow1078 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3001: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v98, vcc +; %bb.3002: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1530.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3003: + v_bfe_u32 v13, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v97, v13, s6 + ; implicit-def: $vgpr97 +; %bb.3004: ; %Flow1077 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3005: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v97, vcc +; %bb.3006: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1533.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3007: + v_bfe_u32 v14, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v96, v14, s6 + ; implicit-def: $vgpr96 +; %bb.3008: ; %Flow1076 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3009: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v96, vcc +; %bb.3010: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1536.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3011: + v_bfe_u32 v15, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v95, v15, s6 + ; implicit-def: $vgpr95 +; %bb.3012: ; %Flow1075 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3013: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v95, vcc +; %bb.3014: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1539.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3015: + v_bfe_u32 v16, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v94, v16, s6 + ; implicit-def: $vgpr94 +; %bb.3016: ; %Flow1074 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3017: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v94, vcc +; %bb.3018: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1542.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3019: + v_bfe_u32 v17, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v92, v17, s6 + ; implicit-def: $vgpr92 +; %bb.3020: ; %Flow1073 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3021: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v22, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v22, v92, vcc +; %bb.3022: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1545.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3023: + v_bfe_u32 v22, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v93, v22, s6 + ; implicit-def: $vgpr93 +; %bb.3024: ; %Flow1072 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3025: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v93, vcc +; %bb.3026: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1548.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3027: + v_bfe_u32 v23, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v91, v23, s6 + ; implicit-def: $vgpr91 +; %bb.3028: ; %Flow1071 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3029: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v91, vcc +; %bb.3030: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1551.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3031: + v_bfe_u32 v24, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v90, v24, s6 + ; implicit-def: $vgpr90 +; %bb.3032: ; %Flow1070 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3033: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v90, vcc +; %bb.3034: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1554.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3035: + v_bfe_u32 v25, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v89, v25, s6 + ; implicit-def: $vgpr89 +; %bb.3036: ; %Flow1069 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3037: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v89, vcc +; %bb.3038: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1557.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3039: + v_bfe_u32 v26, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v88, v26, s6 + ; implicit-def: $vgpr88 +; %bb.3040: ; %Flow1068 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3041: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v88, vcc +; %bb.3042: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1560.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3043: + v_bfe_u32 v27, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v87, v27, s6 + ; implicit-def: $vgpr87 +; %bb.3044: ; %Flow1067 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3045: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v87, vcc +; %bb.3046: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1563.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a64 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3047: + v_accvgpr_read_b32 v29, a64 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr64 +; %bb.3048: ; %Flow1066 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3049: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a64 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3050: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1566.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a55 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3051: + v_accvgpr_read_b32 v30, a55 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr55 +; %bb.3052: ; %Flow1065 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3053: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a55 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3054: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1569.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a54 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3055: + v_accvgpr_read_b32 v31, a54 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr54 +; %bb.3056: ; %Flow1064 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3057: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a54 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3058: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1572.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a53 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3059: + v_accvgpr_read_b32 v32, a53 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr53 +; %bb.3060: ; %Flow1063 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3061: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a53 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3062: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1575.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a52 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3063: + v_accvgpr_read_b32 v33, a52 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr52 +; %bb.3064: ; %Flow1062 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3065: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a52 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3066: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1578.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a51 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3067: + v_accvgpr_read_b32 v34, a51 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr51 +; %bb.3068: ; %Flow1061 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3069: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a51 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3070: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1581.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a50 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3071: + v_accvgpr_read_b32 v35, a50 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr50 +; %bb.3072: ; %Flow1060 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3073: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a50 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3074: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1584.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a49 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3075: + v_accvgpr_read_b32 v36, a49 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr49 +; %bb.3076: ; %Flow1059 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3077: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a49 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3078: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1587.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3079: + v_bfe_u32 v36, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v86, v36, s6 + ; implicit-def: $vgpr86 +; %bb.3080: ; %Flow1058 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3081: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v86, vcc +; %bb.3082: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1590.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v37, a48 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3083: + v_accvgpr_read_b32 v38, a48 + v_bfe_u32 v37, v38, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v38, v37, s6 + ; implicit-def: $agpr48 +; %bb.3084: ; %Flow1057 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3085: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v39, a48 + v_or_b32_e32 v38, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v39, vcc +; %bb.3086: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1722 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v22 offset:8192 + ds_write_b16_d16_hi v19, v23 offset:8320 + ds_write_b16_d16_hi v19, v24 offset:8448 + ds_write_b16_d16_hi v19, v25 offset:8576 + ds_write_b16_d16_hi v19, v26 offset:9216 + ds_write_b16_d16_hi v19, v27 offset:9344 + ds_write_b16_d16_hi v19, v28 offset:9472 + ds_write_b16_d16_hi v19, v29 offset:9600 + ds_write_b16_d16_hi v19, v30 offset:10240 + ds_write_b16_d16_hi v19, v31 offset:10368 + ds_write_b16_d16_hi v19, v32 offset:10496 + ds_write_b16_d16_hi v19, v33 offset:10624 + ds_write_b16_d16_hi v19, v34 offset:11264 + ds_write_b16_d16_hi v19, v35 offset:11392 + ds_write_b16_d16_hi v19, v36 offset:11520 + ds_write_b16_d16_hi v19, v37 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[22:25], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[20:21] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[22:23], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[24:25], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v2, a47 + v_and_b32_e32 v2, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3087: + v_accvgpr_read_b32 v3, a47 + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v3, v2, s6 + ; implicit-def: $agpr47 +; %bb.3088: ; %Flow1056 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3089: + v_mov_b32_e32 v2, 0 + v_accvgpr_read_b32 v4, a47 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v4, vcc +; %bb.3090: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1787.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v3, a46 + v_and_b32_e32 v3, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3091: + v_accvgpr_read_b32 v4, a46 + v_bfe_u32 v3, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v4, v3, s6 + ; implicit-def: $agpr46 +; %bb.3092: ; %Flow1055 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3093: + v_mov_b32_e32 v3, 0 + v_accvgpr_read_b32 v5, a46 + v_or_b32_e32 v4, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v5, vcc +; %bb.3094: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1790.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v4, a45 + v_and_b32_e32 v4, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3095: + v_accvgpr_read_b32 v5, a45 + v_bfe_u32 v4, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v5, v4, s6 + ; implicit-def: $agpr45 +; %bb.3096: ; %Flow1054 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3097: + v_mov_b32_e32 v4, 0 + v_accvgpr_read_b32 v6, a45 + v_or_b32_e32 v5, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v6, vcc +; %bb.3098: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1793.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v5, a44 + v_and_b32_e32 v5, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3099: + v_accvgpr_read_b32 v6, a44 + v_bfe_u32 v5, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v6, v5, s6 + ; implicit-def: $agpr44 +; %bb.3100: ; %Flow1053 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3101: + v_mov_b32_e32 v5, 0 + v_accvgpr_read_b32 v7, a44 + v_or_b32_e32 v6, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v7, vcc +; %bb.3102: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1796.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v6, a43 + v_and_b32_e32 v6, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3103: + v_accvgpr_read_b32 v7, a43 + v_bfe_u32 v6, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v7, v6, s6 + ; implicit-def: $agpr43 +; %bb.3104: ; %Flow1052 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3105: + v_mov_b32_e32 v6, 0 + v_accvgpr_read_b32 v8, a43 + v_or_b32_e32 v7, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v8, vcc +; %bb.3106: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1799.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v7, a42 + v_and_b32_e32 v7, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3107: + v_accvgpr_read_b32 v8, a42 + v_bfe_u32 v7, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v8, v7, s6 + ; implicit-def: $agpr42 +; %bb.3108: ; %Flow1051 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3109: + v_mov_b32_e32 v7, 0 + v_accvgpr_read_b32 v9, a42 + v_or_b32_e32 v8, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v9, vcc +; %bb.3110: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1802.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v8, a41 + v_and_b32_e32 v8, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3111: + v_accvgpr_read_b32 v9, a41 + v_bfe_u32 v8, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v9, v8, s6 + ; implicit-def: $agpr41 +; %bb.3112: ; %Flow1050 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3113: + v_mov_b32_e32 v8, 0 + v_accvgpr_read_b32 v10, a41 + v_or_b32_e32 v9, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v10, vcc +; %bb.3114: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1805.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v9, a40 + v_and_b32_e32 v9, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3115: + v_accvgpr_read_b32 v10, a40 + v_bfe_u32 v9, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v10, v9, s6 + ; implicit-def: $agpr40 +; %bb.3116: ; %Flow1049 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3117: + v_mov_b32_e32 v9, 0 + v_accvgpr_read_b32 v11, a40 + v_or_b32_e32 v10, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v11, vcc +; %bb.3118: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1808.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v10, a39 + v_and_b32_e32 v10, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3119: + v_accvgpr_read_b32 v11, a39 + v_bfe_u32 v10, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v11, v10, s6 + ; implicit-def: $agpr39 +; %bb.3120: ; %Flow1048 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3121: + v_mov_b32_e32 v10, 0 + v_accvgpr_read_b32 v12, a39 + v_or_b32_e32 v11, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v12, vcc +; %bb.3122: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1811.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v11, a38 + v_and_b32_e32 v11, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3123: + v_accvgpr_read_b32 v12, a38 + v_bfe_u32 v11, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v12, v11, s6 + ; implicit-def: $agpr38 +; %bb.3124: ; %Flow1047 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3125: + v_mov_b32_e32 v11, 0 + v_accvgpr_read_b32 v13, a38 + v_or_b32_e32 v12, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v13, vcc +; %bb.3126: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1814.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v12, a37 + v_and_b32_e32 v12, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3127: + v_accvgpr_read_b32 v13, a37 + v_bfe_u32 v12, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v13, v12, s6 + ; implicit-def: $agpr37 +; %bb.3128: ; %Flow1046 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3129: + v_mov_b32_e32 v12, 0 + v_accvgpr_read_b32 v14, a37 + v_or_b32_e32 v13, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v14, vcc +; %bb.3130: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1817.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v13, a36 + v_and_b32_e32 v13, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3131: + v_accvgpr_read_b32 v14, a36 + v_bfe_u32 v13, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v14, v13, s6 + ; implicit-def: $agpr36 +; %bb.3132: ; %Flow1045 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3133: + v_mov_b32_e32 v13, 0 + v_accvgpr_read_b32 v15, a36 + v_or_b32_e32 v14, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v15, vcc +; %bb.3134: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1820.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v14, a35 + v_and_b32_e32 v14, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3135: + v_accvgpr_read_b32 v15, a35 + v_bfe_u32 v14, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v15, v14, s6 + ; implicit-def: $agpr35 +; %bb.3136: ; %Flow1044 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3137: + v_mov_b32_e32 v14, 0 + v_accvgpr_read_b32 v16, a35 + v_or_b32_e32 v15, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v16, vcc +; %bb.3138: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1823.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v15, a34 + v_and_b32_e32 v15, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3139: + v_accvgpr_read_b32 v16, a34 + v_bfe_u32 v15, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v16, v15, s6 + ; implicit-def: $agpr34 +; %bb.3140: ; %Flow1043 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3141: + v_mov_b32_e32 v15, 0 + v_accvgpr_read_b32 v17, a34 + v_or_b32_e32 v16, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v17, vcc +; %bb.3142: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1826.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v16, a33 + v_and_b32_e32 v16, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3143: + v_accvgpr_read_b32 v17, a33 + v_bfe_u32 v16, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v17, v16, s6 + ; implicit-def: $agpr33 +; %bb.3144: ; %Flow1042 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3145: + v_mov_b32_e32 v16, 0 + v_accvgpr_read_b32 v20, a33 + v_or_b32_e32 v17, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v20, vcc +; %bb.3146: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1829.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v17, a15 + v_and_b32_e32 v17, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3147: + v_accvgpr_read_b32 v20, a15 + v_bfe_u32 v17, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v20, v17, s6 + ; implicit-def: $agpr15 +; %bb.3148: ; %Flow1041 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3149: + v_mov_b32_e32 v17, 0 + v_accvgpr_read_b32 v22, a15 + v_or_b32_e32 v20, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v20, v22, vcc +; %bb.3150: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1832.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v20, a32 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s4, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3151: + v_accvgpr_read_b32 v22, a32 + v_bfe_u32 v20, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v22, v20, s6 + ; implicit-def: $agpr32 +; %bb.3152: ; %Flow1040 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3153: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v23, a32 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v22, v23, vcc +; %bb.3154: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1835.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v22, a14 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3155: + v_accvgpr_read_b32 v23, a14 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 + ; implicit-def: $agpr14 +; %bb.3156: ; %Flow1039 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3157: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a14 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.3158: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1838.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v23, a13 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3159: + v_accvgpr_read_b32 v24, a13 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 + ; implicit-def: $agpr13 +; %bb.3160: ; %Flow1038 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3161: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a13 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.3162: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1841.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v24, a12 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3163: + v_accvgpr_read_b32 v25, a12 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 + ; implicit-def: $agpr12 +; %bb.3164: ; %Flow1037 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3165: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a12 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.3166: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1844.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v25, a11 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3167: + v_accvgpr_read_b32 v26, a11 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 + ; implicit-def: $agpr11 +; %bb.3168: ; %Flow1036 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3169: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a11 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.3170: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1847.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v26, a10 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3171: + v_accvgpr_read_b32 v27, a10 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 + ; implicit-def: $agpr10 +; %bb.3172: ; %Flow1035 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3173: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a10 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.3174: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1850.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a9 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3175: + v_accvgpr_read_b32 v28, a9 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr9 +; %bb.3176: ; %Flow1034 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3177: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a9 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3178: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1853.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a8 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3179: + v_accvgpr_read_b32 v29, a8 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr8 +; %bb.3180: ; %Flow1033 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3181: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a8 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3182: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1856.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a7 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3183: + v_accvgpr_read_b32 v30, a7 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr7 +; %bb.3184: ; %Flow1032 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3185: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a7 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3186: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1859.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a6 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3187: + v_accvgpr_read_b32 v31, a6 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr6 +; %bb.3188: ; %Flow1031 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3189: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a6 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3190: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1862.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a5 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3191: + v_accvgpr_read_b32 v32, a5 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr5 +; %bb.3192: ; %Flow1030 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3193: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a5 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1865.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a4 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3195: + v_accvgpr_read_b32 v33, a4 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr4 +; %bb.3196: ; %Flow1029 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3197: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a4 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1868.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a3 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3199: + v_accvgpr_read_b32 v34, a3 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr3 +; %bb.3200: ; %Flow1028 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3201: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a3 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1871.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a2 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3203: + v_accvgpr_read_b32 v35, a2 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr2 +; %bb.3204: ; %Flow1027 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3205: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a2 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1874.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a1 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3207: + v_accvgpr_read_b32 v36, a1 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr1 +; %bb.3208: ; %Flow1026 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3209: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a1 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1877.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v85 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3211: + v_bfe_u32 v36, v85, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v85, v36, s6 + ; implicit-def: $vgpr85 +; %bb.3212: ; %Flow1025 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3213: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v85 + v_cmp_eq_u32_sdwa vcc, v85, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v85, vcc +; %bb.3214: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP_ + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v20 offset:8192 + ds_write_b16_d16_hi v19, v22 offset:8320 + ds_write_b16_d16_hi v19, v23 offset:8448 + ds_write_b16_d16_hi v19, v24 offset:8576 + ds_write_b16_d16_hi v19, v25 offset:9216 + ds_write_b16_d16_hi v19, v26 offset:9344 + ds_write_b16_d16_hi v19, v27 offset:9472 + ds_write_b16_d16_hi v19, v28 offset:9600 + ds_write_b16_d16_hi v19, v29 offset:10240 + ds_write_b16_d16_hi v19, v30 offset:10368 + ds_write_b16_d16_hi v19, v31 offset:10496 + ds_write_b16_d16_hi v19, v32 offset:10624 + ds_write_b16_d16_hi v19, v33 offset:11264 + ds_write_b16_d16_hi v19, v34 offset:11392 + ds_write_b16_d16_hi v19, v35 offset:11520 + ds_write_b16_d16_hi v19, v36 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v0, s4, v1 + v_lshl_or_b32 v1, v0, 7, v21 + ds_read_b128 v[2:5], v1 + ds_read_b128 v[6:9], v1 offset:128 + ds_read_b128 v[10:13], v1 offset:256 + ds_read_b128 v[14:17], v1 offset:384 + v_add_u32_e32 v0, s18, v0 + v_mad_u64_u32 v[0:1], s[4:5], v0, s16, v[18:19] + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[2:3], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[4:5], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[6:7], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[8:9], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[10:11], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[12:13], v1, s[0:3], 8 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[14:15], v0, s[0:3], 0 offen + buffer_store_dwordx2 v[16:17], v0, s[0:3], 8 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end11: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end11-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 100364 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB12_9 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB12_4 +; %bb.2: ; %.lr.ph.preheader + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v2, v6 + v_mov_b32_e32 v4, v0 +.LBB12_3: ; %.lr.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[8:9], v[2:3], 1, s[8:9] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[10:11], v[4:5], 1, s[10:11] + global_load_ushort v3, v[8:9], off + global_load_ushort v5, v[10:11], off + s_add_i32 s6, s6, -1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(1) + v_lshlrev_b32_e32 v3, 16, v3 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v5, 16, v5 + v_fmac_f32_e32 v1, v5, v3 + v_add_u32_e32 v2, s7, v2 + s_cbranch_scc0 .LBB12_3 +.LBB12_4: ; %._crit_edge + s_mov_b32 s0, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s0, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[0:1], vcc + s_xor_b64 s[0:1], exec, s[0:1] + s_cbranch_execz .LBB12_6 +; %bb.5: + v_bfe_u32 v2, v1, 16, 1 + s_waitcnt lgkmcnt(0) + s_movk_i32 s2, 0x7fff + v_add3_u32 v2, v1, v2, s2 + ; implicit-def: $vgpr1 +.LBB12_6: ; %Flow + s_andn2_saveexec_b64 s[0:1], s[0:1] +; %bb.7: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v1, vcc +; %bb.8: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit + s_or_b64 exec, exec, s[0:1] + s_waitcnt lgkmcnt(0) + v_mad_u64_u32 v[0:1], s[0:1], v6, s3, v[0:1] + v_mov_b32_e32 v4, s12 + v_mov_b32_e32 v5, s13 + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[4:5] + global_store_short_d16_hi v[0:1], v2, off +.LBB12_9: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 12 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end12: + .size _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end12-_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 12 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 512 +; TotalNumSgprs: 20 +; NumVgprs: 12 +; NumAgprs: 0 +; TotalNumVgprs: 12 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 12 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_waitcnt lgkmcnt(0) + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v1, s13 + s_lshl_b32 s18, s12, 8 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s21, v1 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s12, s12, s15 + s_xor_b32 s2, s12, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s21, s12, s21 + s_mul_i32 s22, s21, s13 + s_sub_i32 s12, s12, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s12, s23, s12 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s12, s2, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s12, s2 + s_sub_i32 s21, s3, s14 + s_max_i32 s21, s21, 0 + s_mul_i32 s21, s13, s21 + s_add_i32 s2, s21, s2 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s12, s12, s13 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s12 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s4, -1 + s_mul_i32 s2, s7, s2 + s_add_i32 s3, s6, -1 + s_add_u32 s3, s3, 1 + s_add_u32 s22, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s20, s2 + s_add_u32 s21, s2, s3 + s_add_i32 s6, s6, 63 + s_movk_i32 s23, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v1 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v68, -1, v1 + v_and_b32_e32 v3, 31, v68 + v_lshrrev_b32_e32 v1, 5, v68 + v_and_b32_e32 v69, 7, v68 + s_cbranch_scc0 .LBB13_2 +; %bb.1: + v_readfirstlane_b32 s26, v0 + v_lshlrev_b32_e32 v2, 3, v69 + v_and_b32_e32 v4, 0x78, v68 + s_and_b32 s10, s26, 0xffffffc0 + v_add_u32_e32 v70, s10, v4 + v_add_u32_e32 v4, s18, v70 + v_mad_u64_u32 v[4:5], s[10:11], v4, s7, v[2:3] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v12, 1, v4 + v_add_u32_e32 v13, s7, v4 + v_lshlrev_b32_e32 v14, 1, v13 + buffer_load_dwordx4 v[4:7], v12, s[8:11], 0 offen + buffer_load_dwordx4 v[8:11], v14, s[8:11], 0 offen + v_add_u32_e32 v16, s7, v13 + v_lshlrev_b32_e32 v12, 1, v16 + buffer_load_dwordx4 v[12:15], v12, s[8:11], 0 offen + v_add_u32_e32 v20, s7, v16 + v_lshlrev_b32_e32 v16, 1, v20 + buffer_load_dwordx4 v[16:19], v16, s[8:11], 0 offen + v_xor_b32_e32 v71, v1, v69 + v_add_u32_e32 v24, s7, v20 + v_lshlrev_b32_e32 v20, 1, v24 + buffer_load_dwordx4 v[20:23], v20, s[8:11], 0 offen + s_lshl_b32 s14, s21, 1 + s_mov_b32 s15, s11 + v_add_u32_e32 v25, s19, v70 + v_mad_u64_u32 v[28:29], s[24:25], v25, s20, v[2:3] + v_lshlrev_b32_e32 v2, 1, v28 + v_add_u32_e32 v36, s7, v24 + v_lshlrev_b32_e32 v24, 1, v36 + buffer_load_dwordx4 v[24:27], v24, s[8:11], 0 offen + v_add_u32_e32 v28, s20, v28 + v_lshlrev_b32_e32 v37, 1, v28 + v_add_u32_e32 v38, s20, v28 + buffer_load_dwordx4 v[28:31], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[32:35], v37, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v38 + v_add_u32_e32 v40, s20, v38 + v_add_u32_e32 v48, s7, v36 + v_lshlrev_b32_e32 v36, 1, v48 + buffer_load_dwordx4 v[36:39], v36, s[8:11], 0 offen + v_lshlrev_b32_e32 v49, 1, v40 + v_add_u32_e32 v50, s20, v40 + buffer_load_dwordx4 v[40:43], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[44:47], v49, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v50 + v_add_u32_e32 v52, s20, v50 + v_add_lshl_u32 v48, v48, s7, 1 + buffer_load_dwordx4 v[48:51], v48, s[8:11], 0 offen + v_lshlrev_b32_e32 v60, 1, v52 + v_add_u32_e32 v61, s20, v52 + buffer_load_dwordx4 v[52:55], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[56:59], v60, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 1, v61 + v_add_lshl_u32 v72, v61, s20, 1 + buffer_load_dwordx4 v[60:63], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[64:67], v72, s[12:15], 0 offen + v_lshlrev_b32_e32 v2, 4, v69 + s_lshr_b32 s10, s26, 2 + s_lshr_b32 s11, s26, 1 + s_and_b32 s10, s10, 0x1ffffe0 + v_and_or_b32 v72, s11, 32, v3 + v_or_b32_e32 v73, s10, v3 + v_lshl_or_b32 v2, v70, 7, v2 + v_or_b32_e32 v74, 1, v70 + v_ashrrev_i32_e32 v75, 31, v70 + v_or_b32_e32 v76, 2, v70 + v_or_b32_e32 v77, 3, v70 + v_lshrrev_b32_e32 v75, 29, v75 + v_add_u32_e32 v78, v74, v75 + v_add_u32_e32 v79, v76, v75 + v_add_u32_e32 v80, v77, v75 + v_and_b32_e32 v78, -8, v78 + v_and_b32_e32 v79, -8, v79 + v_sub_u32_e32 v74, v74, v78 + v_sub_u32_e32 v76, v76, v79 + v_xor_b32_e32 v74, v74, v69 + v_xor_b32_e32 v76, v76, v69 + v_sub_u32_e32 v78, v74, v69 + v_sub_u32_e32 v74, v76, v74 + v_lshl_add_u32 v78, v78, 4, v2 + v_lshlrev_b32_e32 v74, 4, v74 + v_add3_u32 v74, v78, s23, v74 + s_waitcnt vmcnt(15) + ds_write_b128 v2, v[4:7] + s_waitcnt vmcnt(14) + ds_write_b128 v78, v[8:11] offset:128 + s_waitcnt vmcnt(13) + ds_write_b128 v74, v[12:15] offset:128 + v_and_b32_e32 v4, -8, v80 + v_sub_u32_e32 v4, v77, v4 + v_xor_b32_e32 v4, v4, v69 + v_sub_u32_e32 v5, v4, v76 + v_lshlrev_b32_e32 v5, 4, v5 + v_add3_u32 v5, v74, s23, v5 + s_waitcnt vmcnt(12) + ds_write_b128 v5, v[16:19] offset:128 + v_or_b32_e32 v6, 4, v70 + v_add_u32_e32 v7, v6, v75 + v_and_b32_e32 v7, -8, v7 + v_sub_u32_e32 v6, v6, v7 + v_xor_b32_e32 v6, v6, v69 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 4, v4 + v_add3_u32 v4, v5, s23, v4 + s_waitcnt vmcnt(11) + ds_write_b128 v4, v[20:23] offset:128 + v_or_b32_e32 v7, 5, v70 + v_add_u32_e32 v8, v7, v75 + v_and_b32_e32 v8, -8, v8 + v_sub_u32_e32 v7, v7, v8 + v_xor_b32_e32 v7, v7, v69 + v_sub_u32_e32 v6, v7, v6 + v_lshlrev_b32_e32 v6, 4, v6 + v_add3_u32 v6, v4, s23, v6 + s_waitcnt vmcnt(10) + ds_write_b128 v6, v[24:27] offset:128 + v_or_b32_e32 v8, 6, v70 + v_add_u32_e32 v9, v8, v75 + v_and_b32_e32 v9, -8, v9 + v_sub_u32_e32 v8, v8, v9 + v_xor_b32_e32 v8, v8, v69 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 4, v7 + v_add3_u32 v7, v6, s23, v7 + v_add_u32_e32 v9, 0x80, v7 + s_waitcnt vmcnt(7) + ds_write_b128 v7, v[36:39] offset:128 + v_or_b32_e32 v10, 7, v70 + v_add_u32_e32 v11, v10, v75 + v_and_b32_e32 v11, 0xffffff8, v11 + v_sub_u32_e32 v10, v10, v11 + v_xor_b32_e32 v10, v10, v69 + v_sub_u32_e32 v8, v10, v8 + v_lshl_add_u32 v8, v8, 4, v9 + s_waitcnt vmcnt(4) + ds_write_b128 v8, v[48:51] offset:128 + ds_write_b128 v2, v[28:31] offset:32768 + ds_write_b128 v78, v[32:35] offset:32896 + ds_write_b128 v74, v[40:43] offset:32896 + ds_write_b128 v5, v[44:47] offset:32896 + s_waitcnt vmcnt(3) + ds_write_b128 v4, v[52:55] offset:32896 + s_waitcnt vmcnt(2) + ds_write_b128 v6, v[56:59] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v7, v[60:63] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v8, v[64:67] offset:32896 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v2, 4, v71 + v_lshl_or_b32 v4, v73, 7, v2 + ds_read_b128 v[12:15], v4 + v_add_u32_e32 v5, 2, v1 + v_xor_b32_e32 v5, v5, v69 + v_sub_u32_e32 v5, v5, v71 + v_lshlrev_b32_e32 v5, 4, v5 + v_lshl_or_b32 v2, v72, 7, v2 + ds_read_b128 v[16:19], v2 offset:32768 + v_add_u32_e32 v6, v4, v5 + ds_read_b128 v[20:23], v6 + v_add_u32_e32 v5, v2, v5 + ds_read_b128 v[24:27], v5 offset:32768 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x8_bf16 a[160:175], v[12:13], v[16:17], 0 + v_add_u32_e32 v7, 6, v1 + v_xor_b32_e32 v7, v7, v69 + v_sub_u32_e32 v8, v7, v71 + v_lshlrev_b32_e32 v8, 4, v8 + v_sub_u32_e32 v7, v71, v7 + v_lshlrev_b32_e32 v7, 4, v7 + v_mfma_f32_32x32x8_bf16 a[160:175], v[14:15], v[18:19], a[160:175] + v_add_u32_e32 v9, v2, v8 + v_add_u32_e32 v10, v9, v7 + ds_read_b128 v[28:31], v10 offset:40960 + ds_read_b128 v[32:35], v9 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[12:13], v[28:29], 0 + v_mfma_f32_32x32x8_bf16 a[192:207], v[14:15], v[30:31], a[192:207] + ds_read_b128 v[36:39], v10 offset:49152 + ds_read_b128 v[40:43], v10 offset:57344 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[12:13], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[14:15], v[38:39], a[224:239] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[40:41], 0 + v_add_u32_e32 v8, v4, v8 + v_add_u32_e32 v7, v8, v7 + v_mfma_f32_32x32x8_bf16 a[208:223], v[14:15], v[42:43], a[208:223] + ds_read_b128 v[10:13], v7 offset:8192 + ds_read_b128 v[44:47], v8 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[10:11], v[16:17], 0 + v_mfma_f32_32x32x8_bf16 a[176:191], v[12:13], v[18:19], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[10:11], v[28:29], 0 + v_mfma_f32_32x32x8_bf16 a[144:159], v[12:13], v[30:31], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[10:11], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[128:143], v[12:13], v[38:39], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[10:11], v[40:41], 0 + v_mfma_f32_32x32x8_bf16 a[112:127], v[12:13], v[42:43], a[112:127] + ds_read_b128 v[10:13], v7 offset:16384 + ds_read_b128 v[48:51], v7 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[10:11], v[16:17], 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[12:13], v[18:19], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[10:11], v[28:29], 0 + v_mfma_f32_32x32x8_bf16 a[80:95], v[12:13], v[30:31], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[10:11], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[64:79], v[12:13], v[38:39], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[10:11], v[40:41], 0 + v_mfma_f32_32x32x8_bf16 a[48:63], v[12:13], v[42:43], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[48:49], v[16:17], 0 + v_mfma_f32_32x32x8_bf16 a[32:47], v[50:51], v[18:19], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[48:49], v[28:29], 0 + v_mfma_f32_32x32x8_bf16 a[16:31], v[50:51], v[30:31], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[48:49], v[36:37], 0 + v_mfma_f32_32x32x8_bf16 a[0:15], v[50:51], v[38:39], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[48:49], v[40:41], 0 + v_mfma_f32_32x32x8_bf16 a[240:255], v[50:51], v[42:43], a[240:255] + v_mfma_f32_32x32x8_bf16 a[160:175], v[20:21], v[24:25], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[22:23], v[26:27], a[160:175] + ds_read_b128 v[10:13], v5 offset:40960 + ds_read_b128 v[14:17], v5 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[20:21], v[10:11], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[22:23], v[12:13], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[20:21], v[14:15], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[22:23], v[16:17], a[224:239] + ds_read_b128 v[28:31], v5 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[20:21], v[28:29], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[22:23], v[30:31], a[208:223] + ds_read_b128 v[18:21], v6 offset:8192 + ds_read_b128 v[36:39], v6 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[18:19], v[24:25], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[20:21], v[26:27], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[18:19], v[10:11], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[20:21], v[12:13], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[18:19], v[14:15], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[20:21], v[16:17], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[18:19], v[28:29], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[20:21], v[30:31], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[36:37], v[24:25], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[38:39], v[26:27], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[36:37], v[10:11], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[38:39], v[12:13], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[36:37], v[14:15], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[38:39], v[16:17], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[36:37], v[28:29], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[38:39], v[30:31], a[48:63] + ds_read_b128 v[18:21], v6 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[18:19], v[24:25], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[20:21], v[26:27], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[18:19], v[10:11], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[20:21], v[12:13], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[18:19], v[14:15], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[20:21], v[16:17], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[18:19], v[28:29], a[240:255] + v_or_b32_e32 v5, 4, v1 + v_xor_b32_e32 v5, v5, v69 + v_sub_u32_e32 v5, v5, v71 + v_lshlrev_b32_e32 v5, 4, v5 + v_add_u32_e32 v4, v4, v5 + v_mfma_f32_32x32x8_bf16 a[240:255], v[20:21], v[30:31], a[240:255] + ds_read_b128 v[10:13], v4 + v_add_u32_e32 v2, v2, v5 + ds_read_b128 v[14:17], v2 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[160:175], v[10:11], v[14:15], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[12:13], v[16:17], a[160:175] + ds_read_b128 v[18:21], v2 offset:40960 + ds_read_b128 v[22:25], v2 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[10:11], v[18:19], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[12:13], v[20:21], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[10:11], v[22:23], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[12:13], v[24:25], a[224:239] + ds_read_b128 v[26:29], v2 offset:57344 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[10:11], v[26:27], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[28:29], a[208:223] + ds_read_b128 v[10:13], v4 offset:8192 + ds_read_b128 v[36:39], v4 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[10:11], v[14:15], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[12:13], v[16:17], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[10:11], v[18:19], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[12:13], v[20:21], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[10:11], v[22:23], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[12:13], v[24:25], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[10:11], v[26:27], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[12:13], v[28:29], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[36:37], v[14:15], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[38:39], v[16:17], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[36:37], v[18:19], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[38:39], v[20:21], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[36:37], v[22:23], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[38:39], v[24:25], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[36:37], v[26:27], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[38:39], v[28:29], a[48:63] + ds_read_b128 v[4:7], v4 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[14:15], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[6:7], v[16:17], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[18:19], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[20:21], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[22:23], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[6:7], v[24:25], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[26:27], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[28:29], a[240:255] + ds_read_b128 v[4:7], v8 + ds_read_b128 v[10:13], v9 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[10:11], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[6:7], v[12:13], a[160:175] + ds_read_b128 v[14:17], v9 offset:40960 + ds_read_b128 v[18:21], v9 offset:49152 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[14:15], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[6:7], v[16:17], a[192:207] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[18:19], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[6:7], v[20:21], a[224:239] + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[32:33], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[6:7], v[34:35], a[208:223] + ds_read_b128 v[4:7], v8 offset:8192 + ds_read_b128 v[22:25], v8 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[10:11], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[6:7], v[12:13], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[14:15], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[6:7], v[16:17], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[18:19], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[6:7], v[20:21], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[32:33], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[6:7], v[34:35], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[22:23], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[24:25], v[12:13], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[22:23], v[14:15], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[24:25], v[16:17], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[22:23], v[18:19], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[24:25], v[20:21], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[22:23], v[32:33], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[24:25], v[34:35], a[48:63] + v_mfma_f32_32x32x8_bf16 a[32:47], v[44:45], v[10:11], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[46:47], v[12:13], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[44:45], v[14:15], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[46:47], v[16:17], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[44:45], v[18:19], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[46:47], v[20:21], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[44:45], v[32:33], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[46:47], v[34:35], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB13_3 + s_branch .LBB13_10 +.LBB13_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr191 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr207 + ; implicit-def: $agpr175 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB13_3: + s_mov_b32 s10, s7 + v_readfirstlane_b32 s15, v0 + v_lshlrev_b32_e32 v2, 3, v69 + s_and_b32 s11, s15, 0xffffffc0 + v_and_b32_e32 v101, 0x78, v68 + v_add_u32_e32 v7, s11, v101 + v_add_u32_e32 v4, s18, v7 + v_mad_u64_u32 v[66:67], s[10:11], v4, s10, v[2:3] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v4, 1, v66 + v_add_u32_e32 v5, s7, v66 + v_lshlrev_b32_e32 v6, 1, v5 + buffer_load_dwordx4 v[8:11], v4, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v6, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v5 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[16:19], v5, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v4 + v_lshlrev_b32_e32 v5, 1, v4 + buffer_load_dwordx4 v[20:23], v5, s[8:11], 0 offen + v_xor_b32_e32 v6, v1, v69 + s_lshl_b32 s14, s21, 1 + v_lshlrev_b32_e32 v64, 4, v69 + s_lshr_b32 s21, s15, 2 + v_lshlrev_b32_e32 v65, 3, v6 + v_add_u32_e32 v28, s7, v4 + v_lshlrev_b32_e32 v4, 1, v28 + buffer_load_dwordx4 v[24:27], v4, s[8:11], 0 offen + s_lshr_b32 s24, s15, 1 + s_mov_b32 s15, s11 + v_add_u32_e32 v4, s19, v7 + v_mad_u64_u32 v[4:5], s[22:23], v4, s20, v[2:3] + v_lshlrev_b32_e32 v5, 1, v4 + v_add_u32_e32 v32, s20, v4 + v_add_u32_e32 v40, s7, v28 + v_lshlrev_b32_e32 v28, 1, v40 + buffer_load_dwordx4 v[28:31], v28, s[8:11], 0 offen + v_lshlrev_b32_e32 v41, 1, v32 + v_add_u32_e32 v42, s20, v32 + buffer_load_dwordx4 v[32:35], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[36:39], v41, s[12:15], 0 offen + v_lshlrev_b32_e32 v5, 1, v42 + v_add_u32_e32 v44, s20, v42 + v_add_u32_e32 v52, s7, v40 + v_lshlrev_b32_e32 v40, 1, v52 + buffer_load_dwordx4 v[40:43], v40, s[8:11], 0 offen + v_lshlrev_b32_e32 v53, 1, v44 + v_add_u32_e32 v54, s20, v44 + buffer_load_dwordx4 v[44:47], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v53, s[12:15], 0 offen + v_lshlrev_b32_e32 v5, 1, v54 + v_add_u32_e32 v56, s20, v54 + v_add_lshl_u32 v52, v52, s7, 1 + buffer_load_dwordx4 v[52:55], v52, s[8:11], 0 offen + v_lshlrev_b32_e32 v67, 1, v56 + v_add_u32_e32 v70, s20, v56 + buffer_load_dwordx4 v[56:59], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[60:63], v67, s[12:15], 0 offen + v_lshlrev_b32_e32 v5, 1, v70 + v_add_lshl_u32 v67, v70, s20, 1 + buffer_load_dwordx4 v[70:73], v5, s[12:15], 0 offen + buffer_load_dwordx4 v[74:77], v67, s[12:15], 0 offen + s_and_b32 s21, s21, 0x3ffffe0 + v_and_or_b32 v5, s24, 32, v3 + v_or_b32_e32 v67, s21, v3 + v_lshl_or_b32 v3, v5, 6, v65 + v_lshl_or_b32 v64, v7, 7, v64 + v_or_b32_e32 v78, 1, v7 + v_ashrrev_i32_e32 v79, 31, v7 + v_or_b32_e32 v80, 2, v7 + v_lshl_or_b32 v5, v67, 6, v65 + v_lshrrev_b32_e32 v65, 29, v79 + v_add_u32_e32 v67, v78, v65 + v_add_u32_e32 v79, v80, v65 + v_and_b32_e32 v67, -8, v67 + v_and_b32_e32 v79, -8, v79 + v_sub_u32_e32 v67, v78, v67 + v_sub_u32_e32 v78, v80, v79 + v_xor_b32_e32 v67, v67, v69 + v_xor_b32_e32 v78, v78, v69 + v_sub_u32_e32 v79, v67, v69 + v_sub_u32_e32 v67, v78, v67 + v_lshl_add_u32 v79, v79, 4, v64 + s_waitcnt vmcnt(15) + ds_write_b128 v64, v[8:11] + s_waitcnt vmcnt(14) + ds_write_b128 v79, v[12:15] offset:128 + v_lshlrev_b32_e32 v8, 4, v67 + s_movk_i32 s21, 0x80 + v_add3_u32 v8, v79, s21, v8 + s_waitcnt vmcnt(13) + ds_write_b128 v8, v[16:19] offset:128 + v_or_b32_e32 v9, 3, v7 + v_add_u32_e32 v10, v9, v65 + v_and_b32_e32 v10, -8, v10 + v_sub_u32_e32 v9, v9, v10 + v_xor_b32_e32 v9, v9, v69 + v_sub_u32_e32 v10, v9, v78 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v10, v8, s21, v10 + s_waitcnt vmcnt(12) + ds_write_b128 v10, v[20:23] offset:128 + v_or_b32_e32 v11, 4, v7 + v_add_u32_e32 v12, v11, v65 + v_and_b32_e32 v12, -8, v12 + v_sub_u32_e32 v11, v11, v12 + v_xor_b32_e32 v11, v11, v69 + v_sub_u32_e32 v9, v11, v9 + v_lshlrev_b32_e32 v9, 4, v9 + v_add3_u32 v9, v10, s21, v9 + s_waitcnt vmcnt(11) + ds_write_b128 v9, v[24:27] offset:128 + v_or_b32_e32 v12, 5, v7 + v_add_u32_e32 v13, v12, v65 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v69 + v_sub_u32_e32 v11, v12, v11 + v_lshlrev_b32_e32 v11, 4, v11 + v_add3_u32 v11, v9, s21, v11 + v_add_u32_e32 v13, 0x80, v11 + s_waitcnt vmcnt(10) + ds_write_b128 v11, v[28:31] offset:128 + v_or_b32_e32 v14, 6, v7 + v_add_u32_e32 v15, v14, v65 + v_and_b32_e32 v15, -8, v15 + v_sub_u32_e32 v14, v14, v15 + v_xor_b32_e32 v14, v14, v69 + v_sub_u32_e32 v12, v14, v12 + v_lshl_add_u32 v12, v12, 4, v13 + v_add_u32_e32 v13, 0x80, v12 + s_waitcnt vmcnt(7) + ds_write_b128 v12, v[40:43] offset:128 + v_or_b32_e32 v7, 7, v7 + v_add_u32_e32 v15, v7, v65 + v_and_b32_e32 v15, 0xffffff8, v15 + v_sub_u32_e32 v7, v7, v15 + v_xor_b32_e32 v7, v7, v69 + v_sub_u32_e32 v7, v7, v14 + v_lshl_add_u32 v7, v7, 4, v13 + s_waitcnt vmcnt(4) + ds_write_b128 v7, v[52:55] offset:128 + ds_write_b128 v64, v[32:35] offset:32768 + ds_write_b128 v79, v[36:39] offset:32896 + ds_write_b128 v8, v[44:47] offset:32896 + ds_write_b128 v10, v[48:51] offset:32896 + s_waitcnt vmcnt(3) + ds_write_b128 v9, v[56:59] offset:32896 + s_waitcnt vmcnt(2) + ds_write_b128 v11, v[60:63] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v12, v[70:73] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v7, v[74:77] offset:32896 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v9, 2, v1 + v_or_b32_e32 v8, 4, v1 + v_add_u32_e32 v7, 6, v1 + s_cbranch_vccnz .LBB13_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit602.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v9, v69 + v_sub_u32_e32 v1, v1, v6 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v85, v5, v1 + v_xor_b32_e32 v10, v8, v69 + v_sub_u32_e32 v10, v10, v6 + v_lshlrev_b32_e32 v10, 3, v10 + v_add_u32_e32 v87, v5, v10 + v_xor_b32_e32 v11, v7, v69 + v_sub_u32_e32 v12, v11, v6 + v_lshlrev_b32_e32 v12, 3, v12 + v_add_u32_e32 v72, v5, v12 + v_sub_u32_e32 v11, v6, v11 + v_mov_b32_e32 v13, 0x1000 + v_lshl_add_u32 v11, v11, 3, v13 + v_add_u32_e32 v92, v72, v11 + v_add_u32_e32 v88, v92, v1 + v_add_u32_e32 v86, v92, v10 + v_add_u32_e32 v71, v92, v12 + v_add_u32_e32 v91, v71, v11 + v_add_u32_e32 v82, v91, v1 + v_add_u32_e32 v83, v91, v10 + v_add_u32_e32 v70, v91, v12 + v_add_u32_e32 v90, v70, v11 + v_add_u32_e32 v78, v90, v1 + v_add_u32_e32 v79, v90, v10 + v_add_u32_e32 v67, v90, v12 + v_add_u32_e32 v89, v3, v1 + v_add_u32_e32 v73, v3, v10 + v_add_u32_e32 v74, v3, v12 + v_add_u32_e32 v97, v74, v11 + v_add_u32_e32 v98, v97, v1 + v_add_u32_e32 v75, v97, v10 + v_add_u32_e32 v76, v97, v12 + v_add_u32_e32 v95, v76, v11 + v_add_u32_e32 v96, v95, v1 + v_add_u32_e32 v77, v95, v10 + v_add_u32_e32 v80, v95, v12 + v_add_u32_e32 v93, v80, v11 + v_add_u32_e32 v94, v93, v1 + v_add_u32_e32 v81, v93, v10 + v_add_u32_e32 v84, v93, v12 + s_mov_b64 s[2:3], 0 + s_branch .LBB13_6 +.LBB13_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr84 +.LBB13_6: ; %Flow1295 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_lshlrev_b32_e32 v100, 1, v5 + v_lshlrev_b32_e32 v99, 1, v3 + s_cbranch_vccnz .LBB13_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1184.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v1, v4 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v4, v9, v69 + v_sub_u32_e32 v4, v4, v6 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v85, v5, v4 + v_lshlrev_b32_e32 v102, 1, v85 + v_xor_b32_e32 v8, v8, v69 + v_sub_u32_e32 v8, v8, v6 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_u32_e32 v87, v5, v8 + v_lshlrev_b32_e32 v103, 1, v87 + v_xor_b32_e32 v7, v7, v69 + v_sub_u32_e32 v9, v7, v6 + v_lshlrev_b32_e32 v9, 3, v9 + v_add_u32_e32 v72, v5, v9 + v_lshlrev_b32_e32 v104, 1, v72 + v_sub_u32_e32 v5, v6, v7 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v6, 0x1000, v5 + v_add_u32_e32 v92, v72, v6 + v_add_lshl_u32 v105, v72, v5, 1 + v_add_u32_e32 v88, v92, v4 + v_add_u32_e32 v86, v92, v8 + v_add_u32_e32 v71, v92, v9 + v_add_u32_e32 v91, v71, v6 + v_add_u32_e32 v82, v91, v4 + v_add_u32_e32 v83, v91, v8 + v_add_u32_e32 v70, v91, v9 + v_add_u32_e32 v90, v70, v6 + v_add_u32_e32 v78, v90, v4 + v_add_u32_e32 v79, v90, v8 + v_add_u32_e32 v67, v90, v9 + v_add_u32_e32 v89, v3, v4 + v_lshlrev_b32_e32 v106, 1, v89 + v_add_u32_e32 v73, v3, v8 + v_lshlrev_b32_e32 v107, 1, v73 + v_add_u32_e32 v74, v3, v9 + v_lshlrev_b32_e32 v108, 1, v74 + v_add_u32_e32 v97, v74, v6 + v_add_lshl_u32 v109, v74, v5, 1 + v_add_u32_e32 v98, v97, v4 + v_add_u32_e32 v75, v97, v8 + v_add_u32_e32 v76, v97, v9 + v_add_u32_e32 v95, v76, v6 + v_add_u32_e32 v96, v95, v4 + v_add_u32_e32 v77, v95, v8 + v_add_u32_e32 v80, v95, v9 + v_add_u32_e32 v93, v80, v6 + v_add_u32_e32 v94, v93, v4 + v_add_u32_e32 v81, v93, v8 + v_add_u32_e32 v84, v93, v9 + s_add_i32 s2, s2, 1 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_lshlrev_b32_e32 v110, 1, v2 + s_movk_i32 s3, 0x80 +.LBB13_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1184.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v1, 64, v1 + v_add_u32_e32 v66, 64, v66 + v_lshlrev_b32_e32 v6, 1, v66 + v_add_u32_e32 v2, s7, v66 + v_lshlrev_b32_e32 v3, 1, v1 + v_add_u32_e32 v7, s20, v1 + v_lshlrev_b32_e32 v8, 1, v2 + v_add_u32_e32 v9, s7, v2 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 1, v7 + v_add_u32_e32 v11, s20, v7 + buffer_load_dwordx4 v[14:17], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[18:21], v8, s[8:11], 0 offen + v_lshlrev_b32_e32 v22, 1, v9 + v_add_u32_e32 v12, s7, v9 + buffer_load_dwordx4 v[6:9], v10, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 1, v11 + v_add_u32_e32 v23, s20, v11 + v_lshlrev_b32_e32 v24, 1, v12 + v_add_u32_e32 v25, s7, v12 + buffer_load_dwordx4 v[10:13], v10, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v23 + v_add_u32_e32 v27, s20, v23 + buffer_load_dwordx4 v[30:33], v22, s[8:11], 0 offen + buffer_load_dwordx4 v[34:37], v24, s[8:11], 0 offen + v_lshlrev_b32_e32 v38, 1, v25 + v_add_u32_e32 v28, s7, v25 + buffer_load_dwordx4 v[22:25], v26, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v27 + v_add_u32_e32 v39, s20, v27 + v_lshlrev_b32_e32 v40, 1, v28 + v_add_u32_e32 v41, s7, v28 + buffer_load_dwordx4 v[26:29], v26, s[12:15], 0 offen + v_lshlrev_b32_e32 v42, 1, v39 + v_add_u32_e32 v43, s20, v39 + buffer_load_dwordx4 v[50:53], v38, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v40, s[8:11], 0 offen + v_lshlrev_b32_e32 v44, 1, v41 + v_add_lshl_u32 v45, v41, s7, 1 + buffer_load_dwordx4 v[38:41], v42, s[12:15], 0 offen + v_lshlrev_b32_e32 v42, 1, v43 + v_add_lshl_u32 v46, v43, s20, 1 + buffer_load_dwordx4 v[58:61], v44, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v45, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[42:45], v42, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[46:49], v46, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[120:123], v100 + ds_read_b128 v[116:119], v99 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[64:79], v[120:121], v[116:117], a[64:79] + ds_read_b128 v[128:131], v109 offset:40960 + ds_read_b128 v[112:115], v108 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[48:63], v[120:121], v[128:129], a[48:63] + v_lshlrev_b32_e32 v111, 1, v97 + ds_read_b128 v[136:139], v111 offset:40960 + v_lshlrev_b32_e32 v111, 1, v98 + ds_read_b128 v[124:127], v111 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[120:121], v[136:137], a[0:15] + v_lshlrev_b32_e32 v111, 1, v95 + ds_read_b128 v[140:143], v111 offset:40960 + v_lshlrev_b32_e32 v111, 1, v96 + ds_read_b128 v[132:135], v111 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[120:121], v[140:141], a[112:127] + ds_read_b128 v[144:147], v105 offset:8192 + v_lshlrev_b32_e32 v111, 1, v92 + ds_read_b128 v[148:151], v111 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[144:145], v[116:117], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[144:145], v[128:129], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[144:145], v[136:137], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[144:145], v[140:141], a[176:191] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[148:149], v[116:117], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[148:149], v[128:129], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[148:149], v[136:137], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[140:141], a[240:255] + v_lshlrev_b32_e32 v111, 1, v91 + ds_read_b128 v[152:155], v111 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[152:153], v[116:117], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[152:153], v[128:129], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[136:137], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[140:141], a[32:47] + v_mfma_f32_32x32x8_bf16 a[64:79], v[122:123], v[118:119], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[122:123], v[130:131], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[122:123], v[138:139], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[122:123], v[142:143], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[146:147], v[118:119], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[146:147], v[130:131], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[146:147], v[138:139], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[146:147], v[142:143], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[118:119], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[130:131], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[138:139], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[142:143], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[154:155], v[118:119], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[154:155], v[130:131], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[138:139], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[142:143], a[32:47] + ds_read_b128 v[116:119], v102 + ds_read_b128 v[120:123], v106 offset:32768 + ds_read_b128 v[128:131], v102 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[116:117], v[120:121], a[64:79] + ds_read_b128 v[136:139], v106 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[48:63], v[116:117], v[136:137], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[116:117], v[124:125], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[116:117], v[132:133], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[120:121], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[128:129], v[136:137], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[128:129], v[124:125], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[128:129], v[132:133], a[176:191] + v_lshlrev_b32_e32 v111, 1, v88 + ds_read_b128 v[140:143], v111 offset:8192 + v_lshlrev_b32_e32 v111, 1, v86 + ds_read_b128 v[144:147], v111 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[140:141], v[120:121], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[140:141], v[136:137], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[140:141], v[124:125], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[140:141], v[132:133], a[240:255] + v_lshlrev_b32_e32 v111, 1, v82 + ds_read_b128 v[148:151], v111 offset:8192 + v_lshlrev_b32_e32 v111, 1, v83 + ds_read_b128 v[152:155], v111 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[148:149], v[120:121], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[148:149], v[136:137], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[148:149], v[124:125], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[148:149], v[132:133], a[32:47] + v_mfma_f32_32x32x8_bf16 a[64:79], v[118:119], v[122:123], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[118:119], v[138:139], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[118:119], v[126:127], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[118:119], v[134:135], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[130:131], v[122:123], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[130:131], v[138:139], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[130:131], v[126:127], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[130:131], v[134:135], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[142:143], v[122:123], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[142:143], v[138:139], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[142:143], v[126:127], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[142:143], v[134:135], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[150:151], v[122:123], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[150:151], v[138:139], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[150:151], v[126:127], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[150:151], v[134:135], a[32:47] + ds_read_b128 v[124:127], v103 + ds_read_b128 v[128:131], v107 offset:32768 + ds_read_b128 v[132:135], v103 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[124:125], v[128:129], a[64:79] + ds_read_b128 v[136:139], v107 offset:40960 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[48:63], v[124:125], v[136:137], a[48:63] + v_lshlrev_b32_e32 v111, 1, v75 + ds_read_b128 v[140:143], v111 offset:40960 + v_lshlrev_b32_e32 v111, 1, v76 + ds_read_b128 v[120:123], v111 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[124:125], v[140:141], a[0:15] + v_lshlrev_b32_e32 v111, 1, v77 + ds_read_b128 v[148:151], v111 offset:40960 + v_lshlrev_b32_e32 v111, 1, v80 + ds_read_b128 v[116:119], v111 offset:40960 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[124:125], v[148:149], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[132:133], v[128:129], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[132:133], v[136:137], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[132:133], v[140:141], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[132:133], v[148:149], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[144:145], v[128:129], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[144:145], v[136:137], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[144:145], v[140:141], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[148:149], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[152:153], v[128:129], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[152:153], v[136:137], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[140:141], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[148:149], a[32:47] + v_mfma_f32_32x32x8_bf16 a[64:79], v[126:127], v[130:131], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[126:127], v[138:139], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[126:127], v[142:143], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[126:127], v[150:151], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[134:135], v[130:131], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[134:135], v[138:139], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[134:135], v[142:143], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[134:135], v[150:151], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[146:147], v[130:131], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[146:147], v[138:139], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[146:147], v[142:143], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[150:151], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[154:155], v[130:131], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[154:155], v[138:139], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[142:143], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[150:151], a[32:47] + ds_read_b128 v[132:135], v104 + ds_read_b128 v[124:127], v108 offset:32768 + ds_read_b128 v[128:131], v104 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[132:133], v[124:125], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[132:133], v[112:113], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[132:133], v[120:121], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[132:133], v[116:117], a[112:127] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[124:125], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[128:129], v[112:113], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[128:129], v[120:121], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[128:129], v[116:117], a[176:191] + v_lshlrev_b32_e32 v111, 1, v71 + ds_read_b128 v[136:139], v111 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[136:137], v[124:125], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[136:137], v[112:113], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[136:137], v[120:121], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[136:137], v[116:117], a[240:255] + v_lshlrev_b32_e32 v111, 1, v70 + ds_read_b128 v[140:143], v111 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[140:141], v[124:125], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[140:141], v[112:113], a[80:95] + v_mfma_f32_32x32x8_bf16 a[16:31], v[140:141], v[120:121], a[16:31] + v_mfma_f32_32x32x8_bf16 a[32:47], v[140:141], v[116:117], a[32:47] + v_mfma_f32_32x32x8_bf16 a[64:79], v[134:135], v[126:127], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[134:135], v[114:115], a[48:63] + v_mfma_f32_32x32x8_bf16 a[0:15], v[134:135], v[122:123], a[0:15] + v_mfma_f32_32x32x8_bf16 a[112:127], v[134:135], v[118:119], a[112:127] + v_mfma_f32_32x32x8_bf16 a[128:143], v[130:131], v[126:127], a[128:143] + v_mfma_f32_32x32x8_bf16 a[144:159], v[130:131], v[114:115], a[144:159] + v_readfirstlane_b32 s6, v0 + s_add_i32 s2, s2, -1 + v_mfma_f32_32x32x8_bf16 a[160:175], v[130:131], v[122:123], a[160:175] + s_andn2_b32 s6, s6, 63 + v_add_u32_e32 v111, s6, v101 + s_cmp_gt_u32 s2, 2 + v_lshl_or_b32 v112, v111, 7, v110 + v_or_b32_e32 v113, 1, v111 + v_ashrrev_i32_e32 v116, 31, v111 + v_or_b32_e32 v117, 2, v111 + v_mfma_f32_32x32x8_bf16 a[176:191], v[130:131], v[118:119], a[176:191] + v_or_b32_e32 v120, 3, v111 + v_or_b32_e32 v121, 4, v111 + v_or_b32_e32 v124, 5, v111 + v_or_b32_e32 v125, 6, v111 + v_or_b32_e32 v111, 7, v111 + v_lshrrev_b32_e32 v116, 29, v116 + v_add_u32_e32 v128, v113, v116 + v_mfma_f32_32x32x8_bf16 a[192:207], v[138:139], v[126:127], a[192:207] + v_add_u32_e32 v129, v117, v116 + v_add_u32_e32 v130, v120, v116 + v_add_u32_e32 v131, v121, v116 + v_add_u32_e32 v132, v124, v116 + v_add_u32_e32 v133, v125, v116 + v_add_u32_e32 v116, v111, v116 + v_and_b32_e32 v128, -8, v128 + v_mfma_f32_32x32x8_bf16 a[208:223], v[138:139], v[114:115], a[208:223] + v_and_b32_e32 v129, -8, v129 + v_and_b32_e32 v130, -8, v130 + v_and_b32_e32 v131, -8, v131 + v_and_b32_e32 v132, -8, v132 + v_and_b32_e32 v133, -8, v133 + v_and_b32_e32 v116, 0xffffff8, v116 + v_sub_u32_e32 v113, v113, v128 + v_mfma_f32_32x32x8_bf16 a[224:239], v[138:139], v[122:123], a[224:239] + v_sub_u32_e32 v117, v117, v129 + v_sub_u32_e32 v120, v120, v130 + v_sub_u32_e32 v121, v121, v131 + v_sub_u32_e32 v124, v124, v132 + v_sub_u32_e32 v125, v125, v133 + v_sub_u32_e32 v111, v111, v116 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[240:255], v[138:139], v[118:119], a[240:255] + s_barrier + v_xor_b32_e32 v113, v113, v69 + v_xor_b32_e32 v116, v117, v69 + v_xor_b32_e32 v117, v120, v69 + v_xor_b32_e32 v120, v121, v69 + v_xor_b32_e32 v121, v124, v69 + v_xor_b32_e32 v124, v125, v69 + v_mfma_f32_32x32x8_bf16 a[96:111], v[142:143], v[126:127], a[96:111] + v_xor_b32_e32 v111, v111, v69 + v_sub_u32_e32 v125, v113, v69 + v_sub_u32_e32 v113, v116, v113 + v_sub_u32_e32 v116, v117, v116 + v_sub_u32_e32 v117, v120, v117 + v_sub_u32_e32 v120, v121, v120 + v_sub_u32_e32 v121, v124, v121 + v_mfma_f32_32x32x8_bf16 a[80:95], v[142:143], v[114:115], a[80:95] + v_sub_u32_e32 v111, v111, v124 + v_lshl_add_u32 v114, v125, 4, v112 + v_lshlrev_b32_e32 v113, 4, v113 + v_lshlrev_b32_e32 v115, 4, v116 + v_lshlrev_b32_e32 v116, 4, v117 + v_lshlrev_b32_e32 v117, 4, v120 + v_lshlrev_b32_e32 v120, 4, v121 + v_mfma_f32_32x32x8_bf16 a[16:31], v[142:143], v[122:123], a[16:31] + v_add3_u32 v113, v114, s3, v113 + v_add3_u32 v115, v113, s3, v115 + v_add3_u32 v116, v115, s3, v116 + v_add3_u32 v117, v116, s3, v117 + v_add3_u32 v120, v117, s3, v120 + v_add_u32_e32 v121, 0x80, v120 + v_lshl_add_u32 v111, v111, 4, v121 + v_mfma_f32_32x32x8_bf16 a[32:47], v[142:143], v[118:119], a[32:47] + s_waitcnt vmcnt(14) + ds_write_b128 v112, v[14:17] + s_waitcnt vmcnt(13) + ds_write_b128 v114, v[18:21] offset:128 + s_waitcnt vmcnt(10) + ds_write_b128 v113, v[30:33] offset:128 + s_waitcnt vmcnt(9) + ds_write_b128 v115, v[34:37] offset:128 + s_waitcnt vmcnt(6) + ds_write_b128 v116, v[50:53] offset:128 + s_waitcnt vmcnt(5) + ds_write_b128 v117, v[54:57] offset:128 + s_waitcnt vmcnt(3) + ds_write_b128 v120, v[58:61] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v111, v[62:65] offset:128 + ds_write_b128 v112, v[2:5] offset:32768 + ds_write_b128 v114, v[6:9] offset:32896 + ds_write_b128 v113, v[10:13] offset:32896 + ds_write_b128 v115, v[22:25] offset:32896 + ds_write_b128 v116, v[26:29] offset:32896 + ds_write_b128 v117, v[38:41] offset:32896 + s_waitcnt vmcnt(1) + ds_write_b128 v120, v[42:45] offset:32896 + s_waitcnt vmcnt(0) + ds_write_b128 v111, v[46:49] offset:32896 + s_cbranch_scc1 .LBB13_8 +.LBB13_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_R + v_accvgpr_read_b32 v166, a112 + v_accvgpr_read_b32 v167, a113 + v_accvgpr_read_b32 v168, a114 + v_accvgpr_read_b32 v169, a115 + v_accvgpr_read_b32 v170, a116 + v_accvgpr_read_b32 v171, a117 + v_accvgpr_read_b32 v172, a118 + v_accvgpr_read_b32 v173, a119 + v_accvgpr_read_b32 v174, a120 + v_accvgpr_read_b32 v175, a121 + v_accvgpr_read_b32 v176, a122 + v_accvgpr_read_b32 v177, a123 + v_accvgpr_read_b32 v178, a124 + v_accvgpr_read_b32 v179, a125 + v_accvgpr_read_b32 v180, a126 + v_accvgpr_read_b32 v181, a127 + v_accvgpr_read_b32 v150, a128 + v_accvgpr_read_b32 v151, a129 + v_accvgpr_read_b32 v152, a130 + v_accvgpr_read_b32 v153, a131 + v_accvgpr_read_b32 v154, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v156, a134 + v_accvgpr_read_b32 v157, a135 + v_accvgpr_read_b32 v158, a136 + v_accvgpr_read_b32 v159, a137 + v_accvgpr_read_b32 v160, a138 + v_accvgpr_read_b32 v161, a139 + v_accvgpr_read_b32 v162, a140 + v_accvgpr_read_b32 v163, a141 + v_accvgpr_read_b32 v164, a142 + v_accvgpr_read_b32 v165, a143 + v_accvgpr_mov_b32 a128, a160 + v_accvgpr_mov_b32 a129, a161 + v_accvgpr_mov_b32 a130, a162 + v_accvgpr_mov_b32 a131, a163 + v_accvgpr_mov_b32 a132, a164 + v_accvgpr_mov_b32 a133, a165 + v_accvgpr_mov_b32 a134, a166 + v_accvgpr_mov_b32 a135, a167 + v_accvgpr_mov_b32 a136, a168 + v_accvgpr_mov_b32 a137, a169 + v_accvgpr_mov_b32 a138, a170 + v_accvgpr_mov_b32 a139, a171 + v_accvgpr_mov_b32 a140, a172 + v_accvgpr_mov_b32 a141, a173 + v_accvgpr_mov_b32 a142, a174 + v_accvgpr_mov_b32 a143, a175 + v_accvgpr_mov_b32 a112, a176 + v_accvgpr_mov_b32 a113, a177 + v_accvgpr_mov_b32 a114, a178 + v_accvgpr_mov_b32 a115, a179 + v_accvgpr_mov_b32 a116, a180 + v_accvgpr_mov_b32 a117, a181 + v_accvgpr_mov_b32 a118, a182 + v_accvgpr_mov_b32 a119, a183 + v_accvgpr_mov_b32 a120, a184 + v_accvgpr_mov_b32 a121, a185 + v_accvgpr_mov_b32 a122, a186 + v_accvgpr_mov_b32 a123, a187 + v_accvgpr_mov_b32 a124, a188 + v_accvgpr_mov_b32 a125, a189 + v_accvgpr_mov_b32 a126, a190 + v_accvgpr_mov_b32 a127, a191 + v_accvgpr_read_b32 v134, a192 + v_accvgpr_read_b32 v135, a193 + v_accvgpr_read_b32 v136, a194 + v_accvgpr_read_b32 v137, a195 + v_accvgpr_read_b32 v138, a196 + v_accvgpr_read_b32 v139, a197 + v_accvgpr_read_b32 v140, a198 + v_accvgpr_read_b32 v141, a199 + v_accvgpr_read_b32 v142, a200 + v_accvgpr_read_b32 v143, a201 + v_accvgpr_read_b32 v144, a202 + v_accvgpr_read_b32 v145, a203 + v_accvgpr_read_b32 v146, a204 + v_accvgpr_read_b32 v147, a205 + v_accvgpr_read_b32 v148, a206 + v_accvgpr_read_b32 v149, a207 + v_accvgpr_read_b32 v118, a208 + v_accvgpr_read_b32 v119, a209 + v_accvgpr_read_b32 v120, a210 + v_accvgpr_read_b32 v121, a211 + v_accvgpr_read_b32 v122, a212 + v_accvgpr_read_b32 v123, a213 + v_accvgpr_read_b32 v124, a214 + v_accvgpr_read_b32 v125, a215 + v_accvgpr_read_b32 v126, a216 + v_accvgpr_read_b32 v127, a217 + v_accvgpr_read_b32 v128, a218 + v_accvgpr_read_b32 v129, a219 + v_accvgpr_read_b32 v130, a220 + v_accvgpr_read_b32 v131, a221 + v_accvgpr_read_b32 v132, a222 + v_accvgpr_read_b32 v133, a223 + v_accvgpr_read_b32 v102, a224 + v_accvgpr_read_b32 v103, a225 + v_accvgpr_read_b32 v104, a226 + v_accvgpr_read_b32 v105, a227 + v_accvgpr_read_b32 v106, a228 + v_accvgpr_read_b32 v107, a229 + v_accvgpr_read_b32 v108, a230 + v_accvgpr_read_b32 v109, a231 + v_accvgpr_read_b32 v110, a232 + v_accvgpr_read_b32 v111, a233 + v_accvgpr_read_b32 v112, a234 + v_accvgpr_read_b32 v113, a235 + v_accvgpr_read_b32 v114, a236 + v_accvgpr_read_b32 v115, a237 + v_accvgpr_read_b32 v116, a238 + v_accvgpr_read_b32 v117, a239 + v_accvgpr_read_b32 v50, a240 + v_accvgpr_read_b32 v51, a241 + v_accvgpr_read_b32 v52, a242 + v_accvgpr_read_b32 v53, a243 + v_accvgpr_read_b32 v54, a244 + v_accvgpr_read_b32 v55, a245 + v_accvgpr_read_b32 v56, a246 + v_accvgpr_read_b32 v57, a247 + v_accvgpr_read_b32 v58, a248 + v_accvgpr_read_b32 v59, a249 + v_accvgpr_read_b32 v60, a250 + v_accvgpr_read_b32 v61, a251 + v_accvgpr_read_b32 v62, a252 + v_accvgpr_read_b32 v63, a253 + v_accvgpr_read_b32 v64, a254 + v_accvgpr_read_b32 v65, a255 + v_accvgpr_read_b32 v34, a96 + v_accvgpr_read_b32 v35, a97 + v_accvgpr_read_b32 v36, a98 + v_accvgpr_read_b32 v37, a99 + v_accvgpr_read_b32 v38, a100 + v_accvgpr_read_b32 v39, a101 + v_accvgpr_read_b32 v40, a102 + v_accvgpr_read_b32 v41, a103 + v_accvgpr_read_b32 v42, a104 + v_accvgpr_read_b32 v43, a105 + v_accvgpr_read_b32 v44, a106 + v_accvgpr_read_b32 v45, a107 + v_accvgpr_read_b32 v46, a108 + v_accvgpr_read_b32 v47, a109 + v_accvgpr_read_b32 v48, a110 + v_accvgpr_read_b32 v49, a111 + v_accvgpr_read_b32 v18, a80 + v_accvgpr_read_b32 v19, a81 + v_accvgpr_read_b32 v20, a82 + v_accvgpr_read_b32 v21, a83 + v_accvgpr_read_b32 v22, a84 + v_accvgpr_read_b32 v23, a85 + v_accvgpr_read_b32 v24, a86 + v_accvgpr_read_b32 v25, a87 + v_accvgpr_read_b32 v26, a88 + v_accvgpr_read_b32 v27, a89 + v_accvgpr_read_b32 v28, a90 + v_accvgpr_read_b32 v29, a91 + v_accvgpr_read_b32 v30, a92 + v_accvgpr_read_b32 v31, a93 + v_accvgpr_read_b32 v32, a94 + v_accvgpr_read_b32 v33, a95 + v_accvgpr_read_b32 v2, a16 + v_accvgpr_read_b32 v3, a17 + v_accvgpr_read_b32 v4, a18 + v_accvgpr_read_b32 v5, a19 + v_accvgpr_read_b32 v6, a20 + v_accvgpr_read_b32 v7, a21 + v_accvgpr_read_b32 v8, a22 + v_accvgpr_read_b32 v9, a23 + v_accvgpr_read_b32 v10, a24 + v_accvgpr_read_b32 v11, a25 + v_accvgpr_read_b32 v12, a26 + v_accvgpr_read_b32 v13, a27 + v_accvgpr_read_b32 v14, a28 + v_accvgpr_read_b32 v15, a29 + v_accvgpr_read_b32 v16, a30 + v_accvgpr_read_b32 v17, a31 + v_accvgpr_mov_b32 a240, a32 + v_accvgpr_mov_b32 a241, a33 + v_accvgpr_mov_b32 a242, a34 + v_accvgpr_mov_b32 a243, a35 + v_accvgpr_mov_b32 a244, a36 + v_accvgpr_mov_b32 a245, a37 + v_accvgpr_mov_b32 a246, a38 + v_accvgpr_mov_b32 a247, a39 + v_accvgpr_mov_b32 a248, a40 + v_accvgpr_mov_b32 a249, a41 + v_accvgpr_mov_b32 a250, a42 + v_accvgpr_mov_b32 a251, a43 + v_accvgpr_mov_b32 a252, a44 + v_accvgpr_mov_b32 a253, a45 + v_accvgpr_mov_b32 a254, a46 + v_accvgpr_mov_b32 a255, a47 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[182:185], v100 + ds_read_b128 v[186:189], v99 offset:32768 + v_accvgpr_mov_b32 a175, a79 + v_accvgpr_mov_b32 a174, a78 + v_accvgpr_mov_b32 a173, a77 + v_accvgpr_mov_b32 a172, a76 + v_accvgpr_mov_b32 a171, a75 + v_accvgpr_mov_b32 a170, a74 + v_accvgpr_mov_b32 a169, a73 + v_accvgpr_mov_b32 a168, a72 + v_accvgpr_mov_b32 a167, a71 + v_accvgpr_mov_b32 a166, a70 + v_accvgpr_mov_b32 a165, a69 + v_accvgpr_mov_b32 a164, a68 + v_accvgpr_mov_b32 a163, a67 + v_accvgpr_mov_b32 a162, a66 + v_accvgpr_mov_b32 a161, a65 + v_accvgpr_mov_b32 a160, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[160:175], v[182:183], v[186:187], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[184:185], v[188:189], a[160:175] + v_lshlrev_b32_e32 v1, 1, v97 + ds_read_b128 v[190:193], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v98 + v_accvgpr_mov_b32 a207, a63 + v_accvgpr_mov_b32 a206, a62 + v_accvgpr_mov_b32 a205, a61 + v_accvgpr_mov_b32 a204, a60 + v_accvgpr_mov_b32 a203, a59 + v_accvgpr_mov_b32 a202, a58 + v_accvgpr_mov_b32 a201, a57 + v_accvgpr_mov_b32 a200, a56 + v_accvgpr_mov_b32 a199, a55 + v_accvgpr_mov_b32 a198, a54 + v_accvgpr_mov_b32 a197, a53 + v_accvgpr_mov_b32 a196, a52 + v_accvgpr_mov_b32 a195, a51 + v_accvgpr_mov_b32 a194, a50 + v_accvgpr_mov_b32 a193, a49 + v_accvgpr_mov_b32 a192, a48 + ds_read_b128 v[98:101], v1 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[182:183], v[190:191], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[184:185], v[192:193], a[192:207] + v_lshlrev_b32_e32 v1, 1, v95 + ds_read_b128 v[194:197], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v96 + ds_read_b128 v[198:201], v1 offset:32768 + v_accvgpr_mov_b32 a239, a15 + v_accvgpr_mov_b32 a238, a14 + v_accvgpr_mov_b32 a237, a13 + v_accvgpr_mov_b32 a236, a12 + v_accvgpr_mov_b32 a235, a11 + v_accvgpr_mov_b32 a234, a10 + v_accvgpr_mov_b32 a233, a9 + v_accvgpr_mov_b32 a232, a8 + v_accvgpr_mov_b32 a231, a7 + v_accvgpr_mov_b32 a230, a6 + v_accvgpr_mov_b32 a229, a5 + v_accvgpr_mov_b32 a228, a4 + v_accvgpr_mov_b32 a227, a3 + v_accvgpr_mov_b32 a226, a2 + v_accvgpr_mov_b32 a225, a1 + v_accvgpr_mov_b32 a224, a0 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[182:183], v[194:195], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[184:185], v[196:197], a[224:239] + v_lshlrev_b32_e32 v1, 1, v93 + ds_read_b128 v[202:205], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v94 + ds_read_b128 v[94:97], v1 offset:32768 + v_accvgpr_write_b32 a223, v181 + v_accvgpr_write_b32 a222, v180 + v_accvgpr_write_b32 a221, v179 + v_accvgpr_write_b32 a220, v178 + v_accvgpr_write_b32 a219, v177 + v_accvgpr_write_b32 a218, v176 + v_accvgpr_write_b32 a217, v175 + v_accvgpr_write_b32 a216, v174 + v_accvgpr_write_b32 a215, v173 + v_accvgpr_write_b32 a214, v172 + v_accvgpr_write_b32 a213, v171 + v_accvgpr_write_b32 a212, v170 + v_accvgpr_write_b32 a211, v169 + v_accvgpr_write_b32 a210, v168 + v_accvgpr_write_b32 a209, v167 + v_accvgpr_write_b32 a208, v166 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[208:223], v[182:183], v[202:203], a[208:223] + v_lshlrev_b32_e32 v1, 1, v92 + v_mfma_f32_32x32x8_bf16 a[208:223], v[184:185], v[204:205], a[208:223] + ds_read_b128 v[166:169], v1 + v_accvgpr_write_b32 a191, v165 + v_accvgpr_write_b32 a190, v164 + v_accvgpr_write_b32 a189, v163 + v_accvgpr_write_b32 a188, v162 + v_accvgpr_write_b32 a187, v161 + v_accvgpr_write_b32 a186, v160 + v_accvgpr_write_b32 a185, v159 + v_accvgpr_write_b32 a184, v158 + v_accvgpr_write_b32 a183, v157 + v_accvgpr_write_b32 a182, v156 + v_accvgpr_write_b32 a181, v155 + v_accvgpr_write_b32 a180, v154 + v_accvgpr_write_b32 a179, v153 + v_accvgpr_write_b32 a178, v152 + v_accvgpr_write_b32 a177, v151 + v_accvgpr_write_b32 a176, v150 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[176:191], v[166:167], v[186:187], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[168:169], v[188:189], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[166:167], v[190:191], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[168:169], v[192:193], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[166:167], v[194:195], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[168:169], v[196:197], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[166:167], v[202:203], a[112:127] + v_lshlrev_b32_e32 v1, 1, v91 + v_mfma_f32_32x32x8_bf16 a[112:127], v[168:169], v[204:205], a[112:127] + ds_read_b128 v[150:153], v1 + v_accvgpr_write_b32 a96, v134 + v_accvgpr_write_b32 a97, v135 + v_accvgpr_write_b32 a98, v136 + v_accvgpr_write_b32 a99, v137 + v_accvgpr_write_b32 a100, v138 + v_accvgpr_write_b32 a101, v139 + v_accvgpr_write_b32 a102, v140 + v_accvgpr_write_b32 a103, v141 + v_accvgpr_write_b32 a104, v142 + v_accvgpr_write_b32 a105, v143 + v_accvgpr_write_b32 a106, v144 + v_accvgpr_write_b32 a107, v145 + v_accvgpr_write_b32 a108, v146 + v_accvgpr_write_b32 a109, v147 + v_accvgpr_write_b32 a110, v148 + v_accvgpr_write_b32 a111, v149 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[96:111], v[150:151], v[186:187], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[152:153], v[188:189], a[96:111] + v_accvgpr_write_b32 a80, v118 + v_accvgpr_write_b32 a81, v119 + v_accvgpr_write_b32 a82, v120 + v_accvgpr_write_b32 a83, v121 + v_accvgpr_write_b32 a84, v122 + v_accvgpr_write_b32 a85, v123 + v_accvgpr_write_b32 a86, v124 + v_accvgpr_write_b32 a87, v125 + v_accvgpr_write_b32 a88, v126 + v_accvgpr_write_b32 a89, v127 + v_accvgpr_write_b32 a90, v128 + v_accvgpr_write_b32 a91, v129 + v_accvgpr_write_b32 a92, v130 + v_accvgpr_write_b32 a93, v131 + v_accvgpr_write_b32 a94, v132 + v_accvgpr_write_b32 a95, v133 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[80:95], v[150:151], v[190:191], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[152:153], v[192:193], a[80:95] + v_accvgpr_write_b32 a64, v102 + v_accvgpr_write_b32 a65, v103 + v_accvgpr_write_b32 a66, v104 + v_accvgpr_write_b32 a67, v105 + v_accvgpr_write_b32 a68, v106 + v_accvgpr_write_b32 a69, v107 + v_accvgpr_write_b32 a70, v108 + v_accvgpr_write_b32 a71, v109 + v_accvgpr_write_b32 a72, v110 + v_accvgpr_write_b32 a73, v111 + v_accvgpr_write_b32 a74, v112 + v_accvgpr_write_b32 a75, v113 + v_accvgpr_write_b32 a76, v114 + v_accvgpr_write_b32 a77, v115 + v_accvgpr_write_b32 a78, v116 + v_accvgpr_write_b32 a79, v117 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[64:79], v[150:151], v[194:195], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[152:153], v[196:197], a[64:79] + v_accvgpr_write_b32 a48, v50 + v_accvgpr_write_b32 a49, v51 + v_accvgpr_write_b32 a50, v52 + v_accvgpr_write_b32 a51, v53 + v_accvgpr_write_b32 a52, v54 + v_accvgpr_write_b32 a53, v55 + v_accvgpr_write_b32 a54, v56 + v_accvgpr_write_b32 a55, v57 + v_accvgpr_write_b32 a56, v58 + v_accvgpr_write_b32 a57, v59 + v_accvgpr_write_b32 a58, v60 + v_accvgpr_write_b32 a59, v61 + v_accvgpr_write_b32 a60, v62 + v_accvgpr_write_b32 a61, v63 + v_accvgpr_write_b32 a62, v64 + v_accvgpr_write_b32 a63, v65 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[48:63], v[150:151], v[202:203], a[48:63] + v_lshlrev_b32_e32 v1, 1, v90 + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[204:205], a[48:63] + ds_read_b128 v[50:53], v1 + v_accvgpr_write_b32 a32, v34 + v_accvgpr_write_b32 a33, v35 + v_accvgpr_write_b32 a34, v36 + v_accvgpr_write_b32 a35, v37 + v_accvgpr_write_b32 a36, v38 + v_accvgpr_write_b32 a37, v39 + v_accvgpr_write_b32 a38, v40 + v_accvgpr_write_b32 a39, v41 + v_accvgpr_write_b32 a40, v42 + v_accvgpr_write_b32 a41, v43 + v_accvgpr_write_b32 a42, v44 + v_accvgpr_write_b32 a43, v45 + v_accvgpr_write_b32 a44, v46 + v_accvgpr_write_b32 a45, v47 + v_accvgpr_write_b32 a46, v48 + v_accvgpr_write_b32 a47, v49 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[32:47], v[50:51], v[186:187], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[52:53], v[188:189], a[32:47] + v_accvgpr_write_b32 a16, v18 + v_accvgpr_write_b32 a17, v19 + v_accvgpr_write_b32 a18, v20 + v_accvgpr_write_b32 a19, v21 + v_accvgpr_write_b32 a20, v22 + v_accvgpr_write_b32 a21, v23 + v_accvgpr_write_b32 a22, v24 + v_accvgpr_write_b32 a23, v25 + v_accvgpr_write_b32 a24, v26 + v_accvgpr_write_b32 a25, v27 + v_accvgpr_write_b32 a26, v28 + v_accvgpr_write_b32 a27, v29 + v_accvgpr_write_b32 a28, v30 + v_accvgpr_write_b32 a29, v31 + v_accvgpr_write_b32 a30, v32 + v_accvgpr_write_b32 a31, v33 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[16:31], v[50:51], v[190:191], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[52:53], v[192:193], a[16:31] + v_accvgpr_write_b32 a0, v2 + v_accvgpr_write_b32 a1, v3 + v_accvgpr_write_b32 a2, v4 + v_accvgpr_write_b32 a3, v5 + v_accvgpr_write_b32 a4, v6 + v_accvgpr_write_b32 a5, v7 + v_accvgpr_write_b32 a6, v8 + v_accvgpr_write_b32 a7, v9 + v_accvgpr_write_b32 a8, v10 + v_accvgpr_write_b32 a9, v11 + v_accvgpr_write_b32 a10, v12 + v_accvgpr_write_b32 a11, v13 + v_accvgpr_write_b32 a12, v14 + v_accvgpr_write_b32 a13, v15 + v_accvgpr_write_b32 a14, v16 + v_accvgpr_write_b32 a15, v17 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[0:15], v[50:51], v[194:195], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[52:53], v[196:197], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[50:51], v[202:203], a[240:255] + v_lshlrev_b32_e32 v1, 1, v85 + v_mfma_f32_32x32x8_bf16 a[240:255], v[52:53], v[204:205], a[240:255] + ds_read_b128 v[2:5], v1 + v_lshlrev_b32_e32 v1, 1, v89 + ds_read_b128 v[6:9], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v87 + ds_read_b128 v[10:13], v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[8:9], a[160:175] + v_mfma_f32_32x32x8_bf16 a[192:207], v[2:3], v[98:99], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[100:101], a[192:207] + v_mfma_f32_32x32x8_bf16 a[224:239], v[2:3], v[198:199], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[200:201], a[224:239] + v_mfma_f32_32x32x8_bf16 a[208:223], v[2:3], v[94:95], a[208:223] + v_lshlrev_b32_e32 v1, 1, v88 + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[96:97], a[208:223] + ds_read_b128 v[2:5], v1 + v_lshlrev_b32_e32 v1, 1, v86 + ds_read_b128 v[14:17], v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[2:3], v[6:7], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[2:3], v[98:99], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[100:101], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[2:3], v[198:199], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[200:201], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[2:3], v[94:95], a[112:127] + v_lshlrev_b32_e32 v1, 1, v82 + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[96:97], a[112:127] + ds_read_b128 v[2:5], v1 + v_lshlrev_b32_e32 v1, 1, v83 + ds_read_b128 v[18:21], v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[2:3], v[98:99], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[100:101], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[2:3], v[198:199], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[200:201], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[2:3], v[94:95], a[48:63] + v_lshlrev_b32_e32 v1, 1, v78 + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[96:97], a[48:63] + ds_read_b128 v[2:5], v1 + v_lshlrev_b32_e32 v1, 1, v79 + ds_read_b128 v[22:25], v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[2:3], v[6:7], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[8:9], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[2:3], v[98:99], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[100:101], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[2:3], v[198:199], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[200:201], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[2:3], v[94:95], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[96:97], a[240:255] + v_lshlrev_b32_e32 v1, 1, v73 + ds_read_b128 v[2:5], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v74 + ds_read_b128 v[6:9], v1 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[12:13], v[4:5], a[160:175] + v_lshlrev_b32_e32 v1, 1, v75 + ds_read_b128 v[26:29], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v76 + ds_read_b128 v[30:33], v1 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[10:11], v[26:27], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[12:13], v[28:29], a[192:207] + v_lshlrev_b32_e32 v1, 1, v77 + ds_read_b128 v[34:37], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v80 + ds_read_b128 v[38:41], v1 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[10:11], v[34:35], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[12:13], v[36:37], a[224:239] + v_lshlrev_b32_e32 v1, 1, v81 + ds_read_b128 v[42:45], v1 offset:32768 + v_lshlrev_b32_e32 v1, 1, v84 + ds_read_b128 v[46:49], v1 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[208:223], v[10:11], v[42:43], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_bf16 a[176:191], v[14:15], v[2:3], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[16:17], v[4:5], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[14:15], v[26:27], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[16:17], v[28:29], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[14:15], v[34:35], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[16:17], v[36:37], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[14:15], v[42:43], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[16:17], v[44:45], a[112:127] + v_mfma_f32_32x32x8_bf16 a[96:111], v[18:19], v[2:3], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[20:21], v[4:5], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[18:19], v[26:27], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[20:21], v[28:29], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[18:19], v[34:35], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[20:21], v[36:37], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[18:19], v[42:43], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[20:21], v[44:45], a[48:63] + v_mfma_f32_32x32x8_bf16 a[32:47], v[22:23], v[2:3], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[24:25], v[4:5], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[22:23], v[26:27], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[24:25], v[28:29], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[22:23], v[34:35], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[24:25], v[36:37], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[22:23], v[42:43], a[240:255] + v_lshlrev_b32_e32 v1, 1, v72 + v_mfma_f32_32x32x8_bf16 a[240:255], v[24:25], v[44:45], a[240:255] + ds_read_b128 v[2:5], v1 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[8:9], a[160:175] + v_mfma_f32_32x32x8_bf16 a[192:207], v[2:3], v[30:31], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[32:33], a[192:207] + v_mfma_f32_32x32x8_bf16 a[224:239], v[2:3], v[38:39], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[40:41], a[224:239] + v_mfma_f32_32x32x8_bf16 a[208:223], v[2:3], v[46:47], a[208:223] + v_lshlrev_b32_e32 v1, 1, v71 + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[48:49], a[208:223] + ds_read_b128 v[2:5], v1 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[2:3], v[6:7], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[8:9], a[176:191] + v_mfma_f32_32x32x8_bf16 a[144:159], v[2:3], v[30:31], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[32:33], a[144:159] + v_mfma_f32_32x32x8_bf16 a[128:143], v[2:3], v[38:39], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[40:41], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[2:3], v[46:47], a[112:127] + v_lshlrev_b32_e32 v1, 1, v70 + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[48:49], a[112:127] + ds_read_b128 v[2:5], v1 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[2:3], v[6:7], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[2:3], v[30:31], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[32:33], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[2:3], v[38:39], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[40:41], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[2:3], v[46:47], a[48:63] + v_lshlrev_b32_e32 v1, 1, v67 + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[48:49], a[48:63] + ds_read_b128 v[2:5], v1 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[2:3], v[6:7], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[8:9], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[2:3], v[30:31], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[32:33], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[2:3], v[38:39], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[40:41], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[2:3], v[46:47], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[48:49], a[240:255] +.LBB13_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEDF16bNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RK + v_accvgpr_read_b32 v73, a160 + v_accvgpr_read_b32 v72, a161 + v_accvgpr_read_b32 v71, a162 + v_accvgpr_read_b32 v70, a163 + v_accvgpr_read_b32 v67, a164 + v_accvgpr_read_b32 v66, a165 + v_accvgpr_read_b32 v65, a166 + v_accvgpr_read_b32 v64, a167 + v_accvgpr_read_b32 v63, a168 + v_accvgpr_read_b32 v62, a169 + v_accvgpr_read_b32 v61, a170 + v_accvgpr_read_b32 v60, a171 + v_accvgpr_read_b32 v59, a172 + v_accvgpr_read_b32 v58, a173 + v_accvgpr_read_b32 v57, a174 + v_accvgpr_read_b32 v55, a175 + v_accvgpr_read_b32 v252, a192 + v_accvgpr_read_b32 v251, a193 + v_accvgpr_read_b32 v250, a194 + v_accvgpr_read_b32 v249, a195 + v_accvgpr_read_b32 v248, a196 + v_accvgpr_read_b32 v247, a197 + v_accvgpr_read_b32 v246, a198 + v_accvgpr_read_b32 v245, a199 + v_accvgpr_read_b32 v244, a200 + v_accvgpr_read_b32 v243, a201 + v_accvgpr_read_b32 v242, a202 + v_accvgpr_read_b32 v241, a203 + v_accvgpr_read_b32 v240, a204 + v_accvgpr_read_b32 v239, a205 + v_accvgpr_read_b32 v238, a206 + v_accvgpr_read_b32 v236, a207 + v_accvgpr_read_b32 v220, a224 + v_accvgpr_read_b32 v219, a225 + v_accvgpr_read_b32 v218, a226 + v_accvgpr_read_b32 v217, a227 + v_accvgpr_read_b32 v216, a228 + v_accvgpr_read_b32 v215, a229 + v_accvgpr_read_b32 v214, a230 + v_accvgpr_read_b32 v213, a231 + v_accvgpr_read_b32 v212, a232 + v_accvgpr_read_b32 v211, a233 + v_accvgpr_read_b32 v210, a234 + v_accvgpr_read_b32 v209, a235 + v_accvgpr_read_b32 v208, a236 + v_accvgpr_read_b32 v207, a237 + v_accvgpr_read_b32 v206, a238 + v_accvgpr_read_b32 v204, a239 + v_accvgpr_read_b32 v188, a208 + v_accvgpr_read_b32 v187, a209 + v_accvgpr_read_b32 v186, a210 + v_accvgpr_read_b32 v185, a211 + v_accvgpr_read_b32 v184, a212 + v_accvgpr_read_b32 v183, a213 + v_accvgpr_read_b32 v182, a214 + v_accvgpr_read_b32 v181, a215 + v_accvgpr_read_b32 v180, a216 + v_accvgpr_read_b32 v179, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v177, a219 + v_accvgpr_read_b32 v176, a220 + v_accvgpr_read_b32 v175, a221 + v_accvgpr_read_b32 v174, a222 + v_accvgpr_read_b32 v172, a223 + v_accvgpr_read_b32 v56, a176 + v_accvgpr_read_b32 v54, a177 + v_accvgpr_read_b32 v53, a178 + v_accvgpr_read_b32 v52, a179 + v_accvgpr_read_b32 v51, a180 + v_accvgpr_read_b32 v50, a181 + v_accvgpr_read_b32 v49, a182 + v_accvgpr_read_b32 v48, a183 + v_accvgpr_read_b32 v47, a184 + v_accvgpr_read_b32 v46, a185 + v_accvgpr_read_b32 v45, a186 + v_accvgpr_read_b32 v44, a187 + v_accvgpr_read_b32 v1, a188 + v_accvgpr_read_b32 v255, a189 + v_accvgpr_read_b32 v254, a190 + v_accvgpr_read_b32 v253, a191 + v_accvgpr_read_b32 v237, a144 + v_accvgpr_read_b32 v235, a145 + v_accvgpr_read_b32 v234, a146 + v_accvgpr_read_b32 v233, a147 + v_accvgpr_read_b32 v232, a148 + v_accvgpr_read_b32 v231, a149 + v_accvgpr_read_b32 v230, a150 + v_accvgpr_read_b32 v229, a151 + v_accvgpr_read_b32 v228, a152 + v_accvgpr_read_b32 v227, a153 + v_accvgpr_read_b32 v226, a154 + v_accvgpr_read_b32 v225, a155 + v_accvgpr_read_b32 v224, a156 + v_accvgpr_read_b32 v223, a157 + v_accvgpr_read_b32 v222, a158 + v_accvgpr_read_b32 v221, a159 + v_accvgpr_read_b32 v205, a128 + v_accvgpr_read_b32 v203, a129 + v_accvgpr_read_b32 v202, a130 + v_accvgpr_read_b32 v201, a131 + v_accvgpr_read_b32 v200, a132 + v_accvgpr_read_b32 v199, a133 + v_accvgpr_read_b32 v198, a134 + v_accvgpr_read_b32 v197, a135 + v_accvgpr_read_b32 v196, a136 + v_accvgpr_read_b32 v195, a137 + v_accvgpr_read_b32 v194, a138 + v_accvgpr_read_b32 v193, a139 + v_accvgpr_read_b32 v192, a140 + v_accvgpr_read_b32 v191, a141 + v_accvgpr_read_b32 v190, a142 + v_accvgpr_read_b32 v189, a143 + v_accvgpr_read_b32 v173, a112 + v_accvgpr_read_b32 v171, a113 + v_accvgpr_read_b32 v170, a114 + v_accvgpr_read_b32 v169, a115 + v_accvgpr_read_b32 v168, a116 + v_accvgpr_read_b32 v167, a117 + v_accvgpr_read_b32 v166, a118 + v_accvgpr_read_b32 v165, a119 + v_accvgpr_read_b32 v164, a120 + v_accvgpr_read_b32 v163, a121 + v_accvgpr_read_b32 v162, a122 + v_accvgpr_read_b32 v161, a123 + v_accvgpr_read_b32 v160, a124 + v_accvgpr_read_b32 v159, a125 + v_accvgpr_read_b32 v158, a126 + v_accvgpr_read_b32 v157, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v108, a80 + v_accvgpr_read_b32 v107, a81 + v_accvgpr_read_b32 v106, a82 + v_accvgpr_read_b32 v105, a83 + v_accvgpr_read_b32 v104, a84 + v_accvgpr_read_b32 v103, a85 + v_accvgpr_read_b32 v102, a86 + v_accvgpr_read_b32 v101, a87 + v_accvgpr_read_b32 v100, a88 + v_accvgpr_read_b32 v99, a89 + v_accvgpr_read_b32 v98, a90 + v_accvgpr_read_b32 v97, a91 + v_accvgpr_read_b32 v96, a92 + v_accvgpr_read_b32 v95, a93 + v_accvgpr_read_b32 v94, a94 + v_accvgpr_read_b32 v92, a95 + v_accvgpr_read_b32 v140, a64 + v_accvgpr_read_b32 v139, a65 + v_accvgpr_read_b32 v138, a66 + v_accvgpr_read_b32 v137, a67 + v_accvgpr_read_b32 v136, a68 + v_accvgpr_read_b32 v135, a69 + v_accvgpr_read_b32 v134, a70 + v_accvgpr_read_b32 v133, a71 + v_accvgpr_read_b32 v132, a72 + v_accvgpr_read_b32 v131, a73 + v_accvgpr_read_b32 v130, a74 + v_accvgpr_read_b32 v129, a75 + v_accvgpr_read_b32 v128, a76 + v_accvgpr_read_b32 v127, a77 + v_accvgpr_read_b32 v126, a78 + v_accvgpr_read_b32 v124, a79 + v_accvgpr_read_b32 v156, a48 + v_accvgpr_read_b32 v155, a49 + v_accvgpr_read_b32 v154, a50 + v_accvgpr_read_b32 v153, a51 + v_accvgpr_read_b32 v152, a52 + v_accvgpr_read_b32 v151, a53 + v_accvgpr_read_b32 v150, a54 + v_accvgpr_read_b32 v149, a55 + v_accvgpr_read_b32 v148, a56 + v_accvgpr_read_b32 v147, a57 + v_accvgpr_read_b32 v146, a58 + v_accvgpr_read_b32 v145, a59 + v_accvgpr_read_b32 v144, a60 + v_accvgpr_read_b32 v143, a61 + v_accvgpr_read_b32 v142, a62 + v_accvgpr_read_b32 v141, a63 + v_accvgpr_mov_b32 a54, a32 + v_accvgpr_mov_b32 a53, a33 + v_accvgpr_mov_b32 a52, a34 + v_accvgpr_mov_b32 a51, a35 + v_accvgpr_mov_b32 a50, a36 + v_accvgpr_mov_b32 a49, a37 + v_accvgpr_mov_b32 a48, a38 + v_accvgpr_mov_b32 a38, a40 + v_accvgpr_mov_b32 a37, a41 + v_accvgpr_mov_b32 a36, a42 + v_accvgpr_mov_b32 a35, a43 + v_accvgpr_mov_b32 a34, a44 + v_accvgpr_mov_b32 a33, a45 + v_accvgpr_mov_b32 a32, a46 + v_accvgpr_read_b32 v86, a47 + v_accvgpr_read_b32 v93, a16 + v_accvgpr_read_b32 v91, a17 + v_accvgpr_read_b32 v90, a18 + v_accvgpr_read_b32 v89, a19 + v_accvgpr_read_b32 v88, a20 + v_accvgpr_mov_b32 a41, a21 + v_accvgpr_mov_b32 a40, a22 + v_accvgpr_mov_b32 a22, a24 + v_accvgpr_mov_b32 a21, a25 + v_accvgpr_mov_b32 a20, a26 + v_accvgpr_mov_b32 a19, a27 + v_accvgpr_mov_b32 a18, a28 + v_accvgpr_mov_b32 a17, a29 + v_accvgpr_read_b32 v87, a30 + v_accvgpr_mov_b32 a16, a31 + v_accvgpr_read_b32 v125, a0 + v_accvgpr_read_b32 v123, a1 + v_accvgpr_read_b32 v122, a2 + v_accvgpr_read_b32 v121, a3 + v_accvgpr_read_b32 v120, a4 + v_accvgpr_read_b32 v119, a5 + v_accvgpr_read_b32 v118, a6 + v_accvgpr_read_b32 v117, a7 + v_accvgpr_read_b32 v116, a8 + v_accvgpr_read_b32 v115, a9 + v_accvgpr_read_b32 v114, a10 + v_accvgpr_read_b32 v113, a11 + v_accvgpr_read_b32 v112, a12 + v_accvgpr_read_b32 v111, a13 + v_accvgpr_read_b32 v110, a14 + v_accvgpr_read_b32 v109, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mov_b64 s[2:3], -1 + s_cmp_lg_u32 s17, 1 + s_cbranch_scc1 .LBB13_13 +; %bb.11: ; %Flow1292 + s_and_b64 vcc, exec, s[2:3] + s_cbranch_vccnz .LBB13_2190 +.LBB13_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSD_11ColumnMajorESE_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SE_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB13_13: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.14: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 +; %bb.15: ; %Flow1035 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.16: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.17: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i306.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.18: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v19, v72, v19, s7 +; %bb.19: ; %Flow1034 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.20: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v72, vcc +; %bb.21: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i309.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.22: + v_bfe_u32 v20, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v71, v20, s7 +; %bb.23: ; %Flow1033 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.24: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v71, vcc +; %bb.25: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i312.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.26: + v_bfe_u32 v21, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v70, v21, s7 +; %bb.27: ; %Flow1032 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.28: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v70, vcc +; %bb.29: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i315.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.30: + v_bfe_u32 v22, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v67, v22, s7 +; %bb.31: ; %Flow1031 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.32: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v67, vcc +; %bb.33: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i318.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.34: + v_bfe_u32 v23, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v66, v23, s7 +; %bb.35: ; %Flow1030 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.36: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v66, vcc +; %bb.37: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i321.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.38: + v_bfe_u32 v24, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v65, v24, s7 +; %bb.39: ; %Flow1029 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.40: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v65, vcc +; %bb.41: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i324.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.42: + v_bfe_u32 v25, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v64, v25, s7 +; %bb.43: ; %Flow1028 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.44: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v64, vcc +; %bb.45: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i327.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.46: + v_bfe_u32 v26, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v63, v26, s7 +; %bb.47: ; %Flow1027 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.48: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v63, vcc +; %bb.49: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i330.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.50: + v_bfe_u32 v27, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v62, v27, s7 +; %bb.51: ; %Flow1026 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.52: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v62, vcc +; %bb.53: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i333.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.54: + v_bfe_u32 v28, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v61, v28, s7 +; %bb.55: ; %Flow1025 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.56: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v61, vcc +; %bb.57: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i336.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.58: + v_bfe_u32 v29, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v60, v29, s7 +; %bb.59: ; %Flow1024 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.60: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v60, vcc +; %bb.61: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i339.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.62: + v_bfe_u32 v30, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v59, v30, s7 +; %bb.63: ; %Flow1023 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.64: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v59, vcc +; %bb.65: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i342.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.66: + v_bfe_u32 v31, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v58, v31, s7 +; %bb.67: ; %Flow1022 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.68: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v58, vcc +; %bb.69: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i345.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.70: + v_bfe_u32 v32, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v57, v32, s7 +; %bb.71: ; %Flow1021 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.72: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v57, vcc +; %bb.73: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i348.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.74: + v_bfe_u32 v33, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v55, v33, s7 +; %bb.75: ; %Flow1020 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.76: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v55, vcc +; %bb.77: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i351.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.78: + v_bfe_u32 v34, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v56, v34, s7 +; %bb.79: ; %Flow1019 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.80: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v56, vcc +; %bb.81: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i354.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.82: + v_bfe_u32 v35, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v54, v35, s7 +; %bb.83: ; %Flow1018 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.84: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v54, vcc +; %bb.85: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i357.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.86: + v_bfe_u32 v36, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v53, v36, s7 +; %bb.87: ; %Flow1017 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.88: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v53, vcc +; %bb.89: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i360.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.90: + v_bfe_u32 v37, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v52, v37, s7 +; %bb.91: ; %Flow1016 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.92: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v52, vcc +; %bb.93: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i363.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.94: + v_bfe_u32 v38, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v51, v38, s7 +; %bb.95: ; %Flow1015 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.96: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v51, vcc +; %bb.97: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i366.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.98: + v_bfe_u32 v39, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v50, v39, s7 +; %bb.99: ; %Flow1014 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.100: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v50, vcc +; %bb.101: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i369.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.102: + v_bfe_u32 v40, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v49, v40, s7 +; %bb.103: ; %Flow1013 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.104: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v49, vcc +; %bb.105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i372.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.106: + v_bfe_u32 v41, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v48, v41, s7 +; %bb.107: ; %Flow1012 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.108: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v48, vcc +; %bb.109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i375.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.110: + v_bfe_u32 v42, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v47, v42, s7 +; %bb.111: ; %Flow1011 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.112: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v47, vcc +; %bb.113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i378.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.114: + v_bfe_u32 v43, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v46, v43, s7 +; %bb.115: ; %Flow1010 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.116: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v74, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v74, v46, vcc +; %bb.117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i381.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr75 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.118: + v_bfe_u32 v74, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v75, v45, v74, s7 +; %bb.119: ; %Flow1009 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.120: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v75, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v75, v75, v45, vcc +; %bb.121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i384.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.122: + v_bfe_u32 v74, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v76, v44, v74, s7 +; %bb.123: ; %Flow1008 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.124: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v76, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v44, vcc +; %bb.125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i387.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.126: + v_bfe_u32 v74, v1, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v77, v1, v74, s7 +; %bb.127: ; %Flow1007 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.128: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v77, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v1, vcc +; %bb.129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i390.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.130: + v_bfe_u32 v74, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v78, v255, v74, s7 +; %bb.131: ; %Flow1006 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.132: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v78, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v255, vcc +; %bb.133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i393.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.134: + v_bfe_u32 v74, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v79, v254, v74, s7 +; %bb.135: ; %Flow1005 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.136: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v79, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v254, vcc +; %bb.137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i396.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.138: + v_bfe_u32 v74, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v80, v253, v74, s7 +; %bb.139: ; %Flow1004 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.140: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v80, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v253, vcc +; %bb.141: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1ELi2E + s_or_b64 exec, exec, s[2:3] + v_and_b32_e32 v74, 24, v68 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v81, 3, v68 + v_and_or_b32 v81, v81, 12, s2 + v_lshlrev_b32_e32 v81, 7, v81 + v_lshl_or_b32 v81, v69, 1, v81 + v_lshlrev_b32_e32 v74, 1, v74 + s_and_b32 s2, s6, 64 + v_or3_b32 v74, v81, v74, s2 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v38 offset:9216 + ds_write_b16_d16_hi v74, v39 offset:9344 + ds_write_b16_d16_hi v74, v40 offset:9472 + ds_write_b16_d16_hi v74, v41 offset:9600 + ds_write_b16_d16_hi v74, v42 offset:10240 + ds_write_b16_d16_hi v74, v43 offset:10368 + ds_write_b16_d16_hi v74, v75 offset:10496 + ds_write_b16_d16_hi v74, v76 offset:10624 + ds_write_b16_d16_hi v74, v77 offset:11264 + ds_write_b16_d16_hi v74, v78 offset:11392 + ds_write_b16_d16_hi v74, v79 offset:11520 + ds_write_b16_d16_hi v74, v80 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v68 + v_and_b32_e32 v76, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v18, 1, v68 + v_and_b32_e32 v75, 60, v18 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s18, v18 + v_or_b32_e32 v38, s19, v76 + v_mad_u64_u32 v[40:41], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[42:43], v[40:41], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off + v_lshlrev_b32_e32 v18, 7, v18 + v_lshl_or_b32 v18, v76, 1, v18 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB13_143 +.LBB13_142: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_159 +.LBB13_143: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.144: ; in Loop: Header=BB13_143 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.145: ; %Flow1003 + ; in Loop: Header=BB13_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.146: ; in Loop: Header=BB13_143 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.147: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.148: ; in Loop: Header=BB13_143 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.149: ; %Flow1002 + ; in Loop: Header=BB13_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.150: ; in Loop: Header=BB13_143 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.151: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.152: ; in Loop: Header=BB13_143 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.153: ; %Flow1001 + ; in Loop: Header=BB13_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.154: ; in Loop: Header=BB13_143 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.155: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.156: ; in Loop: Header=BB13_143 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.157: ; %Flow1000 + ; in Loop: Header=BB13_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_142 +; %bb.158: ; in Loop: Header=BB13_143 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB13_142 +.LBB13_159: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB13_161 +.LBB13_160: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v41, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_177 +.LBB13_161: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.162: ; in Loop: Header=BB13_161 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.163: ; %Flow999 + ; in Loop: Header=BB13_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.164: ; in Loop: Header=BB13_161 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.165: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.166: ; in Loop: Header=BB13_161 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s9 + ; implicit-def: $vgpr33 +; %bb.167: ; %Flow998 + ; in Loop: Header=BB13_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.168: ; in Loop: Header=BB13_161 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.169: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.170: ; in Loop: Header=BB13_161 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.171: ; %Flow997 + ; in Loop: Header=BB13_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.172: ; in Loop: Header=BB13_161 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.173: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.174: ; in Loop: Header=BB13_161 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.175: ; %Flow996 + ; in Loop: Header=BB13_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_160 +; %bb.176: ; in Loop: Header=BB13_161 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB13_160 +.LBB13_177: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_di + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v40 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB13_179 +.LBB13_178: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s10 + v_perm_b32 v30, v41, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_195 +.LBB13_179: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.180: ; in Loop: Header=BB13_179 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.181: ; %Flow995 + ; in Loop: Header=BB13_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.182: ; in Loop: Header=BB13_179 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.183: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.184: ; in Loop: Header=BB13_179 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s9 + ; implicit-def: $vgpr31 +; %bb.185: ; %Flow994 + ; in Loop: Header=BB13_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.186: ; in Loop: Header=BB13_179 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.187: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.188: ; in Loop: Header=BB13_179 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s9 + ; implicit-def: $vgpr42 +; %bb.189: ; %Flow993 + ; in Loop: Header=BB13_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.190: ; in Loop: Header=BB13_179 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.191: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.192: ; in Loop: Header=BB13_179 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s9 + ; implicit-def: $vgpr42 +; %bb.193: ; %Flow992 + ; in Loop: Header=BB13_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_178 +; %bb.194: ; in Loop: Header=BB13_179 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB13_178 +.LBB13_195: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_197 +.LBB13_196: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s10 + v_perm_b32 v28, v39, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_213 +.LBB13_197: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.198: ; in Loop: Header=BB13_197 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.199: ; %Flow991 + ; in Loop: Header=BB13_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.200: ; in Loop: Header=BB13_197 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.201: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.202: ; in Loop: Header=BB13_197 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s9 + ; implicit-def: $vgpr29 +; %bb.203: ; %Flow990 + ; in Loop: Header=BB13_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.204: ; in Loop: Header=BB13_197 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.205: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.206: ; in Loop: Header=BB13_197 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s9 + ; implicit-def: $vgpr40 +; %bb.207: ; %Flow989 + ; in Loop: Header=BB13_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.208: ; in Loop: Header=BB13_197 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.209: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.210: ; in Loop: Header=BB13_197 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s9 + ; implicit-def: $vgpr40 +; %bb.211: ; %Flow988 + ; in Loop: Header=BB13_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_196 +; %bb.212: ; in Loop: Header=BB13_197 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB13_196 +.LBB13_213: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_65 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_215 +.LBB13_214: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_231 +.LBB13_215: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.216: ; in Loop: Header=BB13_215 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.217: ; %Flow987 + ; in Loop: Header=BB13_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.218: ; in Loop: Header=BB13_215 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.219: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.220: ; in Loop: Header=BB13_215 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.221: ; %Flow986 + ; in Loop: Header=BB13_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.222: ; in Loop: Header=BB13_215 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.223: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.224: ; in Loop: Header=BB13_215 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.225: ; %Flow985 + ; in Loop: Header=BB13_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.226: ; in Loop: Header=BB13_215 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.227: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.228: ; in Loop: Header=BB13_215 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s9 + ; implicit-def: $vgpr37 +; %bb.229: ; %Flow984 + ; in Loop: Header=BB13_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_214 +; %bb.230: ; in Loop: Header=BB13_215 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB13_214 +.LBB13_231: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_233 +.LBB13_232: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_249 +.LBB13_233: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.234: ; in Loop: Header=BB13_233 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.235: ; %Flow983 + ; in Loop: Header=BB13_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.236: ; in Loop: Header=BB13_233 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.237: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.238: ; in Loop: Header=BB13_233 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.239: ; %Flow982 + ; in Loop: Header=BB13_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.240: ; in Loop: Header=BB13_233 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.241: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.242: ; in Loop: Header=BB13_233 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.243: ; %Flow981 + ; in Loop: Header=BB13_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.244: ; in Loop: Header=BB13_233 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.245: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.246: ; in Loop: Header=BB13_233 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.247: ; %Flow980 + ; in Loop: Header=BB13_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_232 +; %bb.248: ; in Loop: Header=BB13_233 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_232 +.LBB13_249: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile130 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_251 +.LBB13_250: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_267 +.LBB13_251: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.252: ; in Loop: Header=BB13_251 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.253: ; %Flow979 + ; in Loop: Header=BB13_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.254: ; in Loop: Header=BB13_251 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.255: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.256: ; in Loop: Header=BB13_251 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.257: ; %Flow978 + ; in Loop: Header=BB13_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.258: ; in Loop: Header=BB13_251 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.259: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.260: ; in Loop: Header=BB13_251 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.261: ; %Flow977 + ; in Loop: Header=BB13_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.262: ; in Loop: Header=BB13_251 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.263: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.264: ; in Loop: Header=BB13_251 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.265: ; %Flow976 + ; in Loop: Header=BB13_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_250 +; %bb.266: ; in Loop: Header=BB13_251 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_250 +.LBB13_267: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_269 +.LBB13_268: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_285 +.LBB13_269: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.270: ; in Loop: Header=BB13_269 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.271: ; %Flow975 + ; in Loop: Header=BB13_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.272: ; in Loop: Header=BB13_269 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.273: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.274: ; in Loop: Header=BB13_269 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.275: ; %Flow974 + ; in Loop: Header=BB13_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.276: ; in Loop: Header=BB13_269 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.277: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.278: ; in Loop: Header=BB13_269 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.279: ; %Flow973 + ; in Loop: Header=BB13_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.280: ; in Loop: Header=BB13_269 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.281: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB13_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.282: ; in Loop: Header=BB13_269 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.283: ; %Flow972 + ; in Loop: Header=BB13_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_268 +; %bb.284: ; in Loop: Header=BB13_269 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_268 +.LBB13_285: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.286: + v_bfe_u32 v18, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v252, v18, s6 +; %bb.287: ; %Flow971 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.288: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v252, vcc +; %bb.289: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i439.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.290: + v_bfe_u32 v19, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v251, v19, s6 +; %bb.291: ; %Flow970 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.292: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v251, vcc +; %bb.293: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i442.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.294: + v_bfe_u32 v20, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v250, v20, s6 +; %bb.295: ; %Flow969 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.296: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v250, vcc +; %bb.297: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i445.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.298: + v_bfe_u32 v21, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v249, v21, s6 +; %bb.299: ; %Flow968 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.300: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v249, vcc +; %bb.301: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i448.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.302: + v_bfe_u32 v22, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v248, v22, s6 +; %bb.303: ; %Flow967 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.304: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v248, vcc +; %bb.305: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i451.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.306: + v_bfe_u32 v23, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v247, v23, s6 +; %bb.307: ; %Flow966 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.308: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v247, vcc +; %bb.309: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i454.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.310: + v_bfe_u32 v24, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v246, v24, s6 +; %bb.311: ; %Flow965 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.312: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v246, vcc +; %bb.313: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i457.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.314: + v_bfe_u32 v25, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v245, v25, s6 +; %bb.315: ; %Flow964 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.316: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v245, vcc +; %bb.317: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i460.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.318: + v_bfe_u32 v26, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v244, v26, s6 +; %bb.319: ; %Flow963 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.320: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v244, vcc +; %bb.321: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i463.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.322: + v_bfe_u32 v27, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v243, v27, s6 +; %bb.323: ; %Flow962 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.324: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v243, vcc +; %bb.325: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i466.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.326: + v_bfe_u32 v28, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v242, v28, s6 +; %bb.327: ; %Flow961 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.328: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v242, vcc +; %bb.329: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i469.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.330: + v_bfe_u32 v29, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v241, v29, s6 +; %bb.331: ; %Flow960 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.332: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v241, vcc +; %bb.333: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i472.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.334: + v_bfe_u32 v30, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v240, v30, s6 +; %bb.335: ; %Flow959 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.336: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v240, vcc +; %bb.337: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i475.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.338: + v_bfe_u32 v31, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v239, v31, s6 +; %bb.339: ; %Flow958 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.340: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v239, vcc +; %bb.341: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i478.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.342: + v_bfe_u32 v32, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v238, v32, s6 +; %bb.343: ; %Flow957 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.344: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v238, vcc +; %bb.345: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i481.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.346: + v_bfe_u32 v33, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v236, v33, s6 +; %bb.347: ; %Flow956 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.348: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v236, vcc +; %bb.349: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i484.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.350: + v_bfe_u32 v34, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v237, v34, s6 +; %bb.351: ; %Flow955 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.352: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v237, vcc +; %bb.353: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i487.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.354: + v_bfe_u32 v35, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v235, v35, s6 +; %bb.355: ; %Flow954 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.356: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v235, vcc +; %bb.357: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i490.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.358: + v_bfe_u32 v36, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v234, v36, s6 +; %bb.359: ; %Flow953 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.360: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v234, vcc +; %bb.361: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i493.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.362: + v_bfe_u32 v37, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v233, v37, s6 +; %bb.363: ; %Flow952 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.364: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v39, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v233, vcc +; %bb.365: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i496.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.366: + v_bfe_u32 v39, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v232, v39, s6 +; %bb.367: ; %Flow951 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.368: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v232, vcc +; %bb.369: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i499.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.370: + v_bfe_u32 v40, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v231, v40, s6 +; %bb.371: ; %Flow950 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.372: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v231, vcc +; %bb.373: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i502.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.374: + v_bfe_u32 v41, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v230, v41, s6 +; %bb.375: ; %Flow949 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.376: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v230, vcc +; %bb.377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i505.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.378: + v_bfe_u32 v42, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v229, v42, s6 +; %bb.379: ; %Flow948 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.380: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v229, vcc +; %bb.381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i508.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.382: + v_bfe_u32 v43, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v228, v43, s6 +; %bb.383: ; %Flow947 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.384: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v228, vcc +; %bb.385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i511.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.386: + v_bfe_u32 v77, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v227, v77, s6 +; %bb.387: ; %Flow946 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.388: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v227, vcc +; %bb.389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i514.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.390: + v_bfe_u32 v78, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v226, v78, s6 +; %bb.391: ; %Flow945 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.392: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v226, vcc +; %bb.393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i517.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.394: + v_bfe_u32 v79, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v225, v79, s6 +; %bb.395: ; %Flow944 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.396: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v225, vcc +; %bb.397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i520.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.398: + v_bfe_u32 v80, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v224, v80, s6 +; %bb.399: ; %Flow943 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.400: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v224, vcc +; %bb.401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i523.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.402: + v_bfe_u32 v81, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v223, v81, s6 +; %bb.403: ; %Flow942 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.404: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v223, vcc +; %bb.405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i526.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.406: + v_bfe_u32 v82, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v222, v82, s6 +; %bb.407: ; %Flow941 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.408: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v222, vcc +; %bb.409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i529.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.410: + v_bfe_u32 v83, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v221, v83, s6 +; %bb.411: ; %Flow940 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.412: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v221, vcc +; %bb.413: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL159 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshlrev_b32_e32 v76, 1, v76 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB13_415 +.LBB13_414: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i222.i.i.i.i.i + ; in Loop: Header=BB13_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_431 +.LBB13_415: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.416: ; in Loop: Header=BB13_415 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.417: ; %Flow939 + ; in Loop: Header=BB13_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.418: ; in Loop: Header=BB13_415 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.419: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i213.i.i.i.i.i + ; in Loop: Header=BB13_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.420: ; in Loop: Header=BB13_415 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.421: ; %Flow938 + ; in Loop: Header=BB13_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.422: ; in Loop: Header=BB13_415 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.423: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i216.i.i.i.i.i + ; in Loop: Header=BB13_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.424: ; in Loop: Header=BB13_415 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.425: ; %Flow937 + ; in Loop: Header=BB13_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.426: ; in Loop: Header=BB13_415 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.427: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i219.i.i.i.i.i + ; in Loop: Header=BB13_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.428: ; in Loop: Header=BB13_415 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.429: ; %Flow936 + ; in Loop: Header=BB13_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_414 +; %bb.430: ; in Loop: Header=BB13_415 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB13_414 +.LBB13_431: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i225.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_433 +.LBB13_432: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i238.i.i.i.i.i + ; in Loop: Header=BB13_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_449 +.LBB13_433: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.434: ; in Loop: Header=BB13_433 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.435: ; %Flow935 + ; in Loop: Header=BB13_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.436: ; in Loop: Header=BB13_433 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.437: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i229.i.i.i.i.i + ; in Loop: Header=BB13_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.438: ; in Loop: Header=BB13_433 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.439: ; %Flow934 + ; in Loop: Header=BB13_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.440: ; in Loop: Header=BB13_433 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.441: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i232.i.i.i.i.i + ; in Loop: Header=BB13_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.442: ; in Loop: Header=BB13_433 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.443: ; %Flow933 + ; in Loop: Header=BB13_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.444: ; in Loop: Header=BB13_433 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.445: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i235.i.i.i.i.i + ; in Loop: Header=BB13_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.446: ; in Loop: Header=BB13_433 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.447: ; %Flow932 + ; in Loop: Header=BB13_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_432 +; %bb.448: ; in Loop: Header=BB13_433 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB13_432 +.LBB13_449: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile242 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 64, v38 + v_accvgpr_write_b32 a1, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_451 +.LBB13_450: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i255.i.i.i.i.i + ; in Loop: Header=BB13_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_467 +.LBB13_451: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.452: ; in Loop: Header=BB13_451 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.453: ; %Flow931 + ; in Loop: Header=BB13_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.454: ; in Loop: Header=BB13_451 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.455: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i246.i.i.i.i.i + ; in Loop: Header=BB13_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.456: ; in Loop: Header=BB13_451 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.457: ; %Flow930 + ; in Loop: Header=BB13_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.458: ; in Loop: Header=BB13_451 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.459: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i249.i.i.i.i.i + ; in Loop: Header=BB13_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.460: ; in Loop: Header=BB13_451 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.461: ; %Flow929 + ; in Loop: Header=BB13_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.462: ; in Loop: Header=BB13_451 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.463: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i252.i.i.i.i.i + ; in Loop: Header=BB13_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.464: ; in Loop: Header=BB13_451 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.465: ; %Flow928 + ; in Loop: Header=BB13_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_450 +; %bb.466: ; in Loop: Header=BB13_451 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB13_450 +.LBB13_467: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i258.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_469 +.LBB13_468: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i271.i.i.i.i.i + ; in Loop: Header=BB13_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_485 +.LBB13_469: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.470: ; in Loop: Header=BB13_469 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.471: ; %Flow927 + ; in Loop: Header=BB13_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.472: ; in Loop: Header=BB13_469 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.473: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i262.i.i.i.i.i + ; in Loop: Header=BB13_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.474: ; in Loop: Header=BB13_469 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.475: ; %Flow926 + ; in Loop: Header=BB13_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.476: ; in Loop: Header=BB13_469 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.477: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i265.i.i.i.i.i + ; in Loop: Header=BB13_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.478: ; in Loop: Header=BB13_469 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.479: ; %Flow925 + ; in Loop: Header=BB13_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.480: ; in Loop: Header=BB13_469 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.481: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i268.i.i.i.i.i + ; in Loop: Header=BB13_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.482: ; in Loop: Header=BB13_469 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.483: ; %Flow924 + ; in Loop: Header=BB13_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_468 +; %bb.484: ; in Loop: Header=BB13_469 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_468 +.LBB13_485: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile275 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_487 +.LBB13_486: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i288.i.i.i.i.i + ; in Loop: Header=BB13_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_503 +.LBB13_487: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.488: ; in Loop: Header=BB13_487 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.489: ; %Flow923 + ; in Loop: Header=BB13_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.490: ; in Loop: Header=BB13_487 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.491: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i279.i.i.i.i.i + ; in Loop: Header=BB13_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.492: ; in Loop: Header=BB13_487 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.493: ; %Flow922 + ; in Loop: Header=BB13_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.494: ; in Loop: Header=BB13_487 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.495: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i282.i.i.i.i.i + ; in Loop: Header=BB13_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.496: ; in Loop: Header=BB13_487 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.497: ; %Flow921 + ; in Loop: Header=BB13_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.498: ; in Loop: Header=BB13_487 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.499: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i285.i.i.i.i.i + ; in Loop: Header=BB13_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.500: ; in Loop: Header=BB13_487 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.501: ; %Flow920 + ; in Loop: Header=BB13_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_486 +; %bb.502: ; in Loop: Header=BB13_487 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB13_486 +.LBB13_503: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i291.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_505 +.LBB13_504: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i304.i.i.i.i.i + ; in Loop: Header=BB13_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_521 +.LBB13_505: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.506: ; in Loop: Header=BB13_505 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.507: ; %Flow919 + ; in Loop: Header=BB13_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.508: ; in Loop: Header=BB13_505 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.509: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i295.i.i.i.i.i + ; in Loop: Header=BB13_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.510: ; in Loop: Header=BB13_505 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.511: ; %Flow918 + ; in Loop: Header=BB13_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.512: ; in Loop: Header=BB13_505 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.513: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i298.i.i.i.i.i + ; in Loop: Header=BB13_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.514: ; in Loop: Header=BB13_505 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.515: ; %Flow917 + ; in Loop: Header=BB13_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.516: ; in Loop: Header=BB13_505 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.517: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i301.i.i.i.i.i + ; in Loop: Header=BB13_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.518: ; in Loop: Header=BB13_505 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.519: ; %Flow916 + ; in Loop: Header=BB13_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_504 +; %bb.520: ; in Loop: Header=BB13_505 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_504 +.LBB13_521: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile308 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_523 +.LBB13_522: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i321.i.i.i.i.i + ; in Loop: Header=BB13_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_539 +.LBB13_523: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.524: ; in Loop: Header=BB13_523 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.525: ; %Flow915 + ; in Loop: Header=BB13_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.526: ; in Loop: Header=BB13_523 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.527: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i312.i.i.i.i.i + ; in Loop: Header=BB13_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.528: ; in Loop: Header=BB13_523 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.529: ; %Flow914 + ; in Loop: Header=BB13_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.530: ; in Loop: Header=BB13_523 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.531: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i315.i.i.i.i.i + ; in Loop: Header=BB13_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.532: ; in Loop: Header=BB13_523 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.533: ; %Flow913 + ; in Loop: Header=BB13_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.534: ; in Loop: Header=BB13_523 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.535: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i318.i.i.i.i.i + ; in Loop: Header=BB13_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.536: ; in Loop: Header=BB13_523 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.537: ; %Flow912 + ; in Loop: Header=BB13_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_522 +; %bb.538: ; in Loop: Header=BB13_523 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_522 +.LBB13_539: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i324.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_541 +.LBB13_540: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i337.i.i.i.i.i + ; in Loop: Header=BB13_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_557 +.LBB13_541: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.542: ; in Loop: Header=BB13_541 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.543: ; %Flow911 + ; in Loop: Header=BB13_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.544: ; in Loop: Header=BB13_541 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.545: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i328.i.i.i.i.i + ; in Loop: Header=BB13_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.546: ; in Loop: Header=BB13_541 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.547: ; %Flow910 + ; in Loop: Header=BB13_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.548: ; in Loop: Header=BB13_541 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.549: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i331.i.i.i.i.i + ; in Loop: Header=BB13_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.550: ; in Loop: Header=BB13_541 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.551: ; %Flow909 + ; in Loop: Header=BB13_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.552: ; in Loop: Header=BB13_541 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.553: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i334.i.i.i.i.i + ; in Loop: Header=BB13_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.554: ; in Loop: Header=BB13_541 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.555: ; %Flow908 + ; in Loop: Header=BB13_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_540 +; %bb.556: ; in Loop: Header=BB13_541 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_540 +.LBB13_557: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_469 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.558: + v_bfe_u32 v18, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v220, v18, s6 +; %bb.559: ; %Flow907 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.560: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v220, vcc +; %bb.561: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i534.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.562: + v_bfe_u32 v19, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v219, v19, s6 +; %bb.563: ; %Flow906 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.564: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v219, vcc +; %bb.565: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i537.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.566: + v_bfe_u32 v20, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v218, v20, s6 +; %bb.567: ; %Flow905 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.568: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v218, vcc +; %bb.569: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i540.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.570: + v_bfe_u32 v21, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v217, v21, s6 +; %bb.571: ; %Flow904 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.572: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v217, vcc +; %bb.573: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i543.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.574: + v_bfe_u32 v22, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v216, v22, s6 +; %bb.575: ; %Flow903 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.576: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v216, vcc +; %bb.577: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i546.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.578: + v_bfe_u32 v23, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v215, v23, s6 +; %bb.579: ; %Flow902 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.580: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v215, vcc +; %bb.581: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i549.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.582: + v_bfe_u32 v24, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v214, v24, s6 +; %bb.583: ; %Flow901 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.584: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v214, vcc +; %bb.585: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i552.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.586: + v_bfe_u32 v25, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v213, v25, s6 +; %bb.587: ; %Flow900 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.588: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v213, vcc +; %bb.589: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i555.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.590: + v_bfe_u32 v26, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v212, v26, s6 +; %bb.591: ; %Flow899 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.592: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v212, vcc +; %bb.593: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i558.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.594: + v_bfe_u32 v27, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v211, v27, s6 +; %bb.595: ; %Flow898 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.596: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v211, vcc +; %bb.597: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i561.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.598: + v_bfe_u32 v28, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v210, v28, s6 +; %bb.599: ; %Flow897 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.600: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v210, vcc +; %bb.601: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i564.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.602: + v_bfe_u32 v29, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v209, v29, s6 +; %bb.603: ; %Flow896 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.604: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v209, vcc +; %bb.605: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i567.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.606: + v_bfe_u32 v30, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v208, v30, s6 +; %bb.607: ; %Flow895 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.608: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v208, vcc +; %bb.609: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.610: + v_bfe_u32 v31, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v207, v31, s6 +; %bb.611: ; %Flow894 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.612: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v207, vcc +; %bb.613: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i573.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.614: + v_bfe_u32 v32, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v206, v32, s6 +; %bb.615: ; %Flow893 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.616: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v206, vcc +; %bb.617: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i576.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.618: + v_bfe_u32 v33, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v204, v33, s6 +; %bb.619: ; %Flow892 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.620: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v204, vcc +; %bb.621: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i579.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.622: + v_bfe_u32 v34, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v205, v34, s6 +; %bb.623: ; %Flow891 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.624: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v205, vcc +; %bb.625: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i582.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.626: + v_bfe_u32 v35, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v203, v35, s6 +; %bb.627: ; %Flow890 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.628: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v203, vcc +; %bb.629: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i585.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.630: + v_bfe_u32 v36, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v202, v36, s6 +; %bb.631: ; %Flow889 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.632: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v202, vcc +; %bb.633: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i588.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.634: + v_bfe_u32 v37, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v201, v37, s6 +; %bb.635: ; %Flow888 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.636: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v201, vcc +; %bb.637: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i591.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.638: + v_bfe_u32 v40, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v200, v40, s6 +; %bb.639: ; %Flow887 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.640: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v200, vcc +; %bb.641: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i594.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.642: + v_bfe_u32 v41, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v199, v41, s6 +; %bb.643: ; %Flow886 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.644: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v199, vcc +; %bb.645: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i597.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.646: + v_bfe_u32 v42, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v198, v42, s6 +; %bb.647: ; %Flow885 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.648: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v198, vcc +; %bb.649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i600.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.650: + v_bfe_u32 v43, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v197, v43, s6 +; %bb.651: ; %Flow884 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.652: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v197, vcc +; %bb.653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.654: + v_bfe_u32 v77, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v196, v77, s6 +; %bb.655: ; %Flow883 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.656: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v196, vcc +; %bb.657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i606.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.658: + v_bfe_u32 v78, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v195, v78, s6 +; %bb.659: ; %Flow882 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.660: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v195, vcc +; %bb.661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i609.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.662: + v_bfe_u32 v79, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v194, v79, s6 +; %bb.663: ; %Flow881 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.664: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v194, vcc +; %bb.665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i612.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.666: + v_bfe_u32 v80, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v193, v80, s6 +; %bb.667: ; %Flow880 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.668: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v193, vcc +; %bb.669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i615.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.670: + v_bfe_u32 v81, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v192, v81, s6 +; %bb.671: ; %Flow879 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.672: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v192, vcc +; %bb.673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i618.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.674: + v_bfe_u32 v82, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v191, v82, s6 +; %bb.675: ; %Flow878 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.676: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v191, vcc +; %bb.677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i621.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.678: + v_bfe_u32 v83, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v190, v83, s6 +; %bb.679: ; %Flow877 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.680: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v190, vcc +; %bb.681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i624.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.682: + v_bfe_u32 v84, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v189, v84, s6 +; %bb.683: ; %Flow876 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.684: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v189, vcc +; %bb.685: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL628 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB13_687 +.LBB13_686: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i691.i.i.i.i.i + ; in Loop: Header=BB13_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_703 +.LBB13_687: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.688: ; in Loop: Header=BB13_687 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.689: ; %Flow875 + ; in Loop: Header=BB13_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.690: ; in Loop: Header=BB13_687 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.691: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i682.i.i.i.i.i + ; in Loop: Header=BB13_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.692: ; in Loop: Header=BB13_687 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.693: ; %Flow874 + ; in Loop: Header=BB13_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.694: ; in Loop: Header=BB13_687 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.695: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i685.i.i.i.i.i + ; in Loop: Header=BB13_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.696: ; in Loop: Header=BB13_687 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.697: ; %Flow873 + ; in Loop: Header=BB13_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.698: ; in Loop: Header=BB13_687 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.699: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i688.i.i.i.i.i + ; in Loop: Header=BB13_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.700: ; in Loop: Header=BB13_687 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.701: ; %Flow872 + ; in Loop: Header=BB13_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_686 +; %bb.702: ; in Loop: Header=BB13_687 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB13_686 +.LBB13_703: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i694.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_705 +.LBB13_704: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i707.i.i.i.i.i + ; in Loop: Header=BB13_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_721 +.LBB13_705: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.706: ; in Loop: Header=BB13_705 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.707: ; %Flow871 + ; in Loop: Header=BB13_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.708: ; in Loop: Header=BB13_705 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.709: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i698.i.i.i.i.i + ; in Loop: Header=BB13_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.710: ; in Loop: Header=BB13_705 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.711: ; %Flow870 + ; in Loop: Header=BB13_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.712: ; in Loop: Header=BB13_705 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.713: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i701.i.i.i.i.i + ; in Loop: Header=BB13_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.714: ; in Loop: Header=BB13_705 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.715: ; %Flow869 + ; in Loop: Header=BB13_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.716: ; in Loop: Header=BB13_705 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.717: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i704.i.i.i.i.i + ; in Loop: Header=BB13_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.718: ; in Loop: Header=BB13_705 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.719: ; %Flow868 + ; in Loop: Header=BB13_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_704 +; %bb.720: ; in Loop: Header=BB13_705 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB13_704 +.LBB13_721: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile711 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 0x80, v38 + v_accvgpr_write_b32 a2, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_723 +.LBB13_722: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i724.i.i.i.i.i + ; in Loop: Header=BB13_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_739 +.LBB13_723: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.724: ; in Loop: Header=BB13_723 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.725: ; %Flow867 + ; in Loop: Header=BB13_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.726: ; in Loop: Header=BB13_723 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.727: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i715.i.i.i.i.i + ; in Loop: Header=BB13_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.728: ; in Loop: Header=BB13_723 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.729: ; %Flow866 + ; in Loop: Header=BB13_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.730: ; in Loop: Header=BB13_723 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.731: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i718.i.i.i.i.i + ; in Loop: Header=BB13_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.732: ; in Loop: Header=BB13_723 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.733: ; %Flow865 + ; in Loop: Header=BB13_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.734: ; in Loop: Header=BB13_723 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.735: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i721.i.i.i.i.i + ; in Loop: Header=BB13_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.736: ; in Loop: Header=BB13_723 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.737: ; %Flow864 + ; in Loop: Header=BB13_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_722 +; %bb.738: ; in Loop: Header=BB13_723 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB13_722 +.LBB13_739: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i727.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_741 +.LBB13_740: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i740.i.i.i.i.i + ; in Loop: Header=BB13_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_757 +.LBB13_741: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.742: ; in Loop: Header=BB13_741 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.743: ; %Flow863 + ; in Loop: Header=BB13_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.744: ; in Loop: Header=BB13_741 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.745: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i731.i.i.i.i.i + ; in Loop: Header=BB13_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.746: ; in Loop: Header=BB13_741 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.747: ; %Flow862 + ; in Loop: Header=BB13_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.748: ; in Loop: Header=BB13_741 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.749: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i734.i.i.i.i.i + ; in Loop: Header=BB13_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.750: ; in Loop: Header=BB13_741 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.751: ; %Flow861 + ; in Loop: Header=BB13_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.752: ; in Loop: Header=BB13_741 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.753: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i737.i.i.i.i.i + ; in Loop: Header=BB13_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.754: ; in Loop: Header=BB13_741 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.755: ; %Flow860 + ; in Loop: Header=BB13_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_740 +; %bb.756: ; in Loop: Header=BB13_741 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_740 +.LBB13_757: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile744 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_759 +.LBB13_758: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i757.i.i.i.i.i + ; in Loop: Header=BB13_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_775 +.LBB13_759: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.760: ; in Loop: Header=BB13_759 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.761: ; %Flow859 + ; in Loop: Header=BB13_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.762: ; in Loop: Header=BB13_759 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.763: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i748.i.i.i.i.i + ; in Loop: Header=BB13_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.764: ; in Loop: Header=BB13_759 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.765: ; %Flow858 + ; in Loop: Header=BB13_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.766: ; in Loop: Header=BB13_759 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.767: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i751.i.i.i.i.i + ; in Loop: Header=BB13_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.768: ; in Loop: Header=BB13_759 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.769: ; %Flow857 + ; in Loop: Header=BB13_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.770: ; in Loop: Header=BB13_759 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.771: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i754.i.i.i.i.i + ; in Loop: Header=BB13_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.772: ; in Loop: Header=BB13_759 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.773: ; %Flow856 + ; in Loop: Header=BB13_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_758 +; %bb.774: ; in Loop: Header=BB13_759 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB13_758 +.LBB13_775: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i760.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_777 +.LBB13_776: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i773.i.i.i.i.i + ; in Loop: Header=BB13_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_793 +.LBB13_777: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.778: ; in Loop: Header=BB13_777 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.779: ; %Flow855 + ; in Loop: Header=BB13_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.780: ; in Loop: Header=BB13_777 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.781: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i764.i.i.i.i.i + ; in Loop: Header=BB13_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.782: ; in Loop: Header=BB13_777 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.783: ; %Flow854 + ; in Loop: Header=BB13_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.784: ; in Loop: Header=BB13_777 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.785: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i767.i.i.i.i.i + ; in Loop: Header=BB13_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.786: ; in Loop: Header=BB13_777 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.787: ; %Flow853 + ; in Loop: Header=BB13_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.788: ; in Loop: Header=BB13_777 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.789: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i770.i.i.i.i.i + ; in Loop: Header=BB13_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.790: ; in Loop: Header=BB13_777 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.791: ; %Flow852 + ; in Loop: Header=BB13_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_776 +; %bb.792: ; in Loop: Header=BB13_777 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_776 +.LBB13_793: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile777 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_795 +.LBB13_794: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i790.i.i.i.i.i + ; in Loop: Header=BB13_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_811 +.LBB13_795: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.796: ; in Loop: Header=BB13_795 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.797: ; %Flow851 + ; in Loop: Header=BB13_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.798: ; in Loop: Header=BB13_795 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.799: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i781.i.i.i.i.i + ; in Loop: Header=BB13_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.800: ; in Loop: Header=BB13_795 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.801: ; %Flow850 + ; in Loop: Header=BB13_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.802: ; in Loop: Header=BB13_795 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.803: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i784.i.i.i.i.i + ; in Loop: Header=BB13_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.804: ; in Loop: Header=BB13_795 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.805: ; %Flow849 + ; in Loop: Header=BB13_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.806: ; in Loop: Header=BB13_795 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.807: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i787.i.i.i.i.i + ; in Loop: Header=BB13_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.808: ; in Loop: Header=BB13_795 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.809: ; %Flow848 + ; in Loop: Header=BB13_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_794 +; %bb.810: ; in Loop: Header=BB13_795 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_794 +.LBB13_811: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i793.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_813 +.LBB13_812: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i806.i.i.i.i.i + ; in Loop: Header=BB13_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_829 +.LBB13_813: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.814: ; in Loop: Header=BB13_813 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.815: ; %Flow847 + ; in Loop: Header=BB13_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.816: ; in Loop: Header=BB13_813 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.817: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i797.i.i.i.i.i + ; in Loop: Header=BB13_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.818: ; in Loop: Header=BB13_813 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.819: ; %Flow846 + ; in Loop: Header=BB13_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.820: ; in Loop: Header=BB13_813 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.821: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i800.i.i.i.i.i + ; in Loop: Header=BB13_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.822: ; in Loop: Header=BB13_813 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.823: ; %Flow845 + ; in Loop: Header=BB13_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.824: ; in Loop: Header=BB13_813 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.825: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i803.i.i.i.i.i + ; in Loop: Header=BB13_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.826: ; in Loop: Header=BB13_813 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.827: ; %Flow844 + ; in Loop: Header=BB13_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_812 +; %bb.828: ; in Loop: Header=BB13_813 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_812 +.LBB13_829: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_938 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.830: + v_bfe_u32 v18, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v188, v18, s6 +; %bb.831: ; %Flow843 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.832: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v188, vcc +; %bb.833: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1003.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.834: + v_bfe_u32 v19, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v187, v19, s6 +; %bb.835: ; %Flow842 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.836: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v187, vcc +; %bb.837: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1006.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.838: + v_bfe_u32 v20, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v186, v20, s6 +; %bb.839: ; %Flow841 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.840: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v186, vcc +; %bb.841: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1009.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.842: + v_bfe_u32 v21, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v185, v21, s6 +; %bb.843: ; %Flow840 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.844: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v185, vcc +; %bb.845: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1012.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.846: + v_bfe_u32 v22, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v184, v22, s6 +; %bb.847: ; %Flow839 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.848: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v184, vcc +; %bb.849: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1015.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.850: + v_bfe_u32 v23, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v183, v23, s6 +; %bb.851: ; %Flow838 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.852: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v183, vcc +; %bb.853: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1018.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.854: + v_bfe_u32 v24, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v182, v24, s6 +; %bb.855: ; %Flow837 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.856: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v182, vcc +; %bb.857: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1021.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.858: + v_bfe_u32 v25, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v181, v25, s6 +; %bb.859: ; %Flow836 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.860: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v181, vcc +; %bb.861: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1024.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.862: + v_bfe_u32 v26, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v180, v26, s6 +; %bb.863: ; %Flow835 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.864: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v180, vcc +; %bb.865: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1027.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.866: + v_bfe_u32 v27, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v179, v27, s6 +; %bb.867: ; %Flow834 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.868: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v179, vcc +; %bb.869: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1030.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.870: + v_bfe_u32 v28, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v178, v28, s6 +; %bb.871: ; %Flow833 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.872: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v178, vcc +; %bb.873: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1033.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.874: + v_bfe_u32 v29, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v177, v29, s6 +; %bb.875: ; %Flow832 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.876: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v177, vcc +; %bb.877: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1036.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.878: + v_bfe_u32 v30, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v176, v30, s6 +; %bb.879: ; %Flow831 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.880: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v176, vcc +; %bb.881: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.882: + v_bfe_u32 v31, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v175, v31, s6 +; %bb.883: ; %Flow830 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.884: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v175, vcc +; %bb.885: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1042.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.886: + v_bfe_u32 v32, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v174, v32, s6 +; %bb.887: ; %Flow829 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.888: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v174, vcc +; %bb.889: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1045.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.890: + v_bfe_u32 v33, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v172, v33, s6 +; %bb.891: ; %Flow828 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.892: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v172, vcc +; %bb.893: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1048.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.894: + v_bfe_u32 v34, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v173, v34, s6 +; %bb.895: ; %Flow827 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.896: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v173, vcc +; %bb.897: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1051.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.898: + v_bfe_u32 v35, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v171, v35, s6 +; %bb.899: ; %Flow826 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.900: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v171, vcc +; %bb.901: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1054.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.902: + v_bfe_u32 v36, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v170, v36, s6 +; %bb.903: ; %Flow825 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.904: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v170, vcc +; %bb.905: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1057.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.906: + v_bfe_u32 v37, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v169, v37, s6 +; %bb.907: ; %Flow824 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.908: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v169, vcc +; %bb.909: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1060.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.910: + v_bfe_u32 v40, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v168, v40, s6 +; %bb.911: ; %Flow823 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.912: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v168, vcc +; %bb.913: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1063.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.914: + v_bfe_u32 v41, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v167, v41, s6 +; %bb.915: ; %Flow822 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.916: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v167, vcc +; %bb.917: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1066.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.918: + v_bfe_u32 v42, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v166, v42, s6 +; %bb.919: ; %Flow821 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.920: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v166, vcc +; %bb.921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1069.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.922: + v_bfe_u32 v43, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v165, v43, s6 +; %bb.923: ; %Flow820 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.924: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v165, vcc +; %bb.925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.926: + v_bfe_u32 v77, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v164, v77, s6 +; %bb.927: ; %Flow819 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.928: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v164, vcc +; %bb.929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1075.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.930: + v_bfe_u32 v78, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v163, v78, s6 +; %bb.931: ; %Flow818 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.932: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v163, vcc +; %bb.933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1078.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.934: + v_bfe_u32 v79, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v162, v79, s6 +; %bb.935: ; %Flow817 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.936: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v162, vcc +; %bb.937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1081.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.938: + v_bfe_u32 v80, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v161, v80, s6 +; %bb.939: ; %Flow816 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.940: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v161, vcc +; %bb.941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1084.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.942: + v_bfe_u32 v81, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v160, v81, s6 +; %bb.943: ; %Flow815 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.944: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v160, vcc +; %bb.945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1087.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.946: + v_bfe_u32 v82, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v159, v82, s6 +; %bb.947: ; %Flow814 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.948: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v159, vcc +; %bb.949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1090.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.950: + v_bfe_u32 v83, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v158, v83, s6 +; %bb.951: ; %Flow813 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.952: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v158, vcc +; %bb.953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1093.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.954: + v_bfe_u32 v84, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v157, v84, s6 +; %bb.955: ; %Flow812 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.956: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v157, vcc +; %bb.957: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1097 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB13_959 +.LBB13_958: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1160.i.i.i.i.i + ; in Loop: Header=BB13_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_975 +.LBB13_959: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.960: ; in Loop: Header=BB13_959 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.961: ; %Flow811 + ; in Loop: Header=BB13_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.962: ; in Loop: Header=BB13_959 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.963: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1151.i.i.i.i.i + ; in Loop: Header=BB13_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.964: ; in Loop: Header=BB13_959 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.965: ; %Flow810 + ; in Loop: Header=BB13_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.966: ; in Loop: Header=BB13_959 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.967: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1154.i.i.i.i.i + ; in Loop: Header=BB13_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.968: ; in Loop: Header=BB13_959 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.969: ; %Flow809 + ; in Loop: Header=BB13_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.970: ; in Loop: Header=BB13_959 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.971: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1157.i.i.i.i.i + ; in Loop: Header=BB13_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.972: ; in Loop: Header=BB13_959 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.973: ; %Flow808 + ; in Loop: Header=BB13_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_958 +; %bb.974: ; in Loop: Header=BB13_959 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB13_958 +.LBB13_975: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1163.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_977 +.LBB13_976: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1176.i.i.i.i.i + ; in Loop: Header=BB13_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_993 +.LBB13_977: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.978: ; in Loop: Header=BB13_977 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.979: ; %Flow807 + ; in Loop: Header=BB13_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.980: ; in Loop: Header=BB13_977 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.981: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1167.i.i.i.i.i + ; in Loop: Header=BB13_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.982: ; in Loop: Header=BB13_977 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.983: ; %Flow806 + ; in Loop: Header=BB13_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.984: ; in Loop: Header=BB13_977 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.985: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1170.i.i.i.i.i + ; in Loop: Header=BB13_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.986: ; in Loop: Header=BB13_977 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.987: ; %Flow805 + ; in Loop: Header=BB13_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.988: ; in Loop: Header=BB13_977 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.989: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1173.i.i.i.i.i + ; in Loop: Header=BB13_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.990: ; in Loop: Header=BB13_977 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.991: ; %Flow804 + ; in Loop: Header=BB13_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_976 +; %bb.992: ; in Loop: Header=BB13_977 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB13_976 +.LBB13_993: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1180 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v77, 0xc0, v38 + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_995 +.LBB13_994: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1193.i.i.i.i.i + ; in Loop: Header=BB13_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v78, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1011 +.LBB13_995: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.996: ; in Loop: Header=BB13_995 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.997: ; %Flow803 + ; in Loop: Header=BB13_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.998: ; in Loop: Header=BB13_995 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.999: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1184.i.i.i.i.i + ; in Loop: Header=BB13_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1000: ; in Loop: Header=BB13_995 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.1001: ; %Flow802 + ; in Loop: Header=BB13_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1002: ; in Loop: Header=BB13_995 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1003: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1187.i.i.i.i.i + ; in Loop: Header=BB13_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1004: ; in Loop: Header=BB13_995 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.1005: ; %Flow801 + ; in Loop: Header=BB13_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1006: ; in Loop: Header=BB13_995 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1007: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1190.i.i.i.i.i + ; in Loop: Header=BB13_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v78, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1008: ; in Loop: Header=BB13_995 Depth=1 + v_bfe_u32 v78, v43, 16, 1 + v_add3_u32 v78, v43, v78, s9 + ; implicit-def: $vgpr43 +; %bb.1009: ; %Flow800 + ; in Loop: Header=BB13_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_994 +; %bb.1010: ; in Loop: Header=BB13_995 Depth=1 + v_or_b32_e32 v78, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v43, vcc + s_branch .LBB13_994 +.LBB13_1011: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1196.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1013 +.LBB13_1012: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1209.i.i.i.i.i + ; in Loop: Header=BB13_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1029 +.LBB13_1013: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1014: ; in Loop: Header=BB13_1013 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.1015: ; %Flow799 + ; in Loop: Header=BB13_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1016: ; in Loop: Header=BB13_1013 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1017: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1200.i.i.i.i.i + ; in Loop: Header=BB13_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1018: ; in Loop: Header=BB13_1013 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.1019: ; %Flow798 + ; in Loop: Header=BB13_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1020: ; in Loop: Header=BB13_1013 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1021: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1203.i.i.i.i.i + ; in Loop: Header=BB13_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1022: ; in Loop: Header=BB13_1013 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.1023: ; %Flow797 + ; in Loop: Header=BB13_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1024: ; in Loop: Header=BB13_1013 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1025: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1206.i.i.i.i.i + ; in Loop: Header=BB13_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1026: ; in Loop: Header=BB13_1013 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.1027: ; %Flow796 + ; in Loop: Header=BB13_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1012 +; %bb.1028: ; in Loop: Header=BB13_1013 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_1012 +.LBB13_1029: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1213 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1031 +.LBB13_1030: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1226.i.i.i.i.i + ; in Loop: Header=BB13_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1047 +.LBB13_1031: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1032: ; in Loop: Header=BB13_1031 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.1033: ; %Flow795 + ; in Loop: Header=BB13_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1034: ; in Loop: Header=BB13_1031 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1035: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1217.i.i.i.i.i + ; in Loop: Header=BB13_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1036: ; in Loop: Header=BB13_1031 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.1037: ; %Flow794 + ; in Loop: Header=BB13_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1038: ; in Loop: Header=BB13_1031 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1039: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1220.i.i.i.i.i + ; in Loop: Header=BB13_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1040: ; in Loop: Header=BB13_1031 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.1041: ; %Flow793 + ; in Loop: Header=BB13_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1042: ; in Loop: Header=BB13_1031 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1043: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1223.i.i.i.i.i + ; in Loop: Header=BB13_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1044: ; in Loop: Header=BB13_1031 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.1045: ; %Flow792 + ; in Loop: Header=BB13_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1030 +; %bb.1046: ; in Loop: Header=BB13_1031 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB13_1030 +.LBB13_1047: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1229.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_1049 +.LBB13_1048: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1242.i.i.i.i.i + ; in Loop: Header=BB13_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1065 +.LBB13_1049: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1050: ; in Loop: Header=BB13_1049 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.1051: ; %Flow791 + ; in Loop: Header=BB13_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1052: ; in Loop: Header=BB13_1049 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1053: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1233.i.i.i.i.i + ; in Loop: Header=BB13_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1054: ; in Loop: Header=BB13_1049 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.1055: ; %Flow790 + ; in Loop: Header=BB13_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1056: ; in Loop: Header=BB13_1049 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1057: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1236.i.i.i.i.i + ; in Loop: Header=BB13_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1058: ; in Loop: Header=BB13_1049 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.1059: ; %Flow789 + ; in Loop: Header=BB13_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1060: ; in Loop: Header=BB13_1049 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1061: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1239.i.i.i.i.i + ; in Loop: Header=BB13_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1062: ; in Loop: Header=BB13_1049 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.1063: ; %Flow788 + ; in Loop: Header=BB13_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1048 +; %bb.1064: ; in Loop: Header=BB13_1049 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_1048 +.LBB13_1065: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1246 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_1067 +.LBB13_1066: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1259.i.i.i.i.i + ; in Loop: Header=BB13_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1083 +.LBB13_1067: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1068: ; in Loop: Header=BB13_1067 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.1069: ; %Flow787 + ; in Loop: Header=BB13_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1070: ; in Loop: Header=BB13_1067 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1071: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1250.i.i.i.i.i + ; in Loop: Header=BB13_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1072: ; in Loop: Header=BB13_1067 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.1073: ; %Flow786 + ; in Loop: Header=BB13_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1074: ; in Loop: Header=BB13_1067 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1075: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1253.i.i.i.i.i + ; in Loop: Header=BB13_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1076: ; in Loop: Header=BB13_1067 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.1077: ; %Flow785 + ; in Loop: Header=BB13_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1078: ; in Loop: Header=BB13_1067 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1079: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1256.i.i.i.i.i + ; in Loop: Header=BB13_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1080: ; in Loop: Header=BB13_1067 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.1081: ; %Flow784 + ; in Loop: Header=BB13_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1066 +; %bb.1082: ; in Loop: Header=BB13_1067 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_1066 +.LBB13_1083: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1262.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_1085 +.LBB13_1084: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1275.i.i.i.i.i + ; in Loop: Header=BB13_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1101 +.LBB13_1085: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1086: ; in Loop: Header=BB13_1085 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.1087: ; %Flow783 + ; in Loop: Header=BB13_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1088: ; in Loop: Header=BB13_1085 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1089: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1266.i.i.i.i.i + ; in Loop: Header=BB13_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1090: ; in Loop: Header=BB13_1085 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.1091: ; %Flow782 + ; in Loop: Header=BB13_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1092: ; in Loop: Header=BB13_1085 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1093: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1269.i.i.i.i.i + ; in Loop: Header=BB13_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1094: ; in Loop: Header=BB13_1085 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.1095: ; %Flow781 + ; in Loop: Header=BB13_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1096: ; in Loop: Header=BB13_1085 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1097: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1272.i.i.i.i.i + ; in Loop: Header=BB13_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1098: ; in Loop: Header=BB13_1085 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.1099: ; %Flow780 + ; in Loop: Header=BB13_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1084 +; %bb.1100: ; in Loop: Header=BB13_1085 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_1084 +.LBB13_1101: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1407 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1102: + v_bfe_u32 v18, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v156, v18, s6 +; %bb.1103: ; %Flow779 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1104: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v156, vcc +; %bb.1105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1472.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1106: + v_bfe_u32 v19, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v155, v19, s6 +; %bb.1107: ; %Flow778 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1108: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v155, vcc +; %bb.1109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1475.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1110: + v_bfe_u32 v20, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v154, v20, s6 +; %bb.1111: ; %Flow777 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1112: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v154, vcc +; %bb.1113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1478.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1114: + v_bfe_u32 v21, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v153, v21, s6 +; %bb.1115: ; %Flow776 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1116: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v153, vcc +; %bb.1117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1481.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1118: + v_bfe_u32 v22, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v152, v22, s6 +; %bb.1119: ; %Flow775 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1120: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v152, vcc +; %bb.1121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1484.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1122: + v_bfe_u32 v23, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v151, v23, s6 +; %bb.1123: ; %Flow774 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1124: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v151, vcc +; %bb.1125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1487.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1126: + v_bfe_u32 v24, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v150, v24, s6 +; %bb.1127: ; %Flow773 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1128: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v150, vcc +; %bb.1129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1490.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1130: + v_bfe_u32 v25, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v149, v25, s6 +; %bb.1131: ; %Flow772 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1132: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v149, vcc +; %bb.1133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1493.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1134: + v_bfe_u32 v26, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v148, v26, s6 +; %bb.1135: ; %Flow771 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1136: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v148, vcc +; %bb.1137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1496.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1138: + v_bfe_u32 v27, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v147, v27, s6 +; %bb.1139: ; %Flow770 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1140: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v147, vcc +; %bb.1141: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1499.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1142: + v_bfe_u32 v28, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v146, v28, s6 +; %bb.1143: ; %Flow769 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1144: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v146, vcc +; %bb.1145: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1502.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1146: + v_bfe_u32 v29, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v145, v29, s6 +; %bb.1147: ; %Flow768 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1148: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v145, vcc +; %bb.1149: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1505.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1150: + v_bfe_u32 v30, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v144, v30, s6 +; %bb.1151: ; %Flow767 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1152: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v144, vcc +; %bb.1153: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1508.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1154: + v_bfe_u32 v31, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v143, v31, s6 +; %bb.1155: ; %Flow766 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1156: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v143, vcc +; %bb.1157: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1511.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1158: + v_bfe_u32 v32, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v142, v32, s6 +; %bb.1159: ; %Flow765 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1160: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v142, vcc +; %bb.1161: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1514.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1162: + v_bfe_u32 v33, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v141, v33, s6 +; %bb.1163: ; %Flow764 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1164: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v141, vcc +; %bb.1165: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1517.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1166: + v_bfe_u32 v34, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v2, v34, s6 +; %bb.1167: ; %Flow763 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1168: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v2, vcc +; %bb.1169: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1520.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1170: + v_bfe_u32 v35, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v3, v35, s6 +; %bb.1171: ; %Flow762 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1172: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v3, vcc +; %bb.1173: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1523.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1174: + v_bfe_u32 v36, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v4, v36, s6 +; %bb.1175: ; %Flow761 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1176: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v4, vcc +; %bb.1177: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1526.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1178: + v_bfe_u32 v37, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v5, v37, s6 +; %bb.1179: ; %Flow760 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1180: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v5, vcc +; %bb.1181: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1529.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1182: + v_bfe_u32 v40, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v6, v40, s6 +; %bb.1183: ; %Flow759 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1184: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v6, vcc +; %bb.1185: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1532.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1186: + v_bfe_u32 v41, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v7, v41, s6 +; %bb.1187: ; %Flow758 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1188: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v7, vcc +; %bb.1189: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1535.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1190: + v_bfe_u32 v42, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v8, v42, s6 +; %bb.1191: ; %Flow757 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1192: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v8, vcc +; %bb.1193: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1538.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1194: + v_bfe_u32 v43, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v9, v43, s6 +; %bb.1195: ; %Flow756 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1196: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v78, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v78, v9, vcc +; %bb.1197: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1541.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1198: + v_bfe_u32 v78, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v10, v78, s6 +; %bb.1199: ; %Flow755 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1200: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v10, vcc +; %bb.1201: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1544.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1202: + v_bfe_u32 v79, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v11, v79, s6 +; %bb.1203: ; %Flow754 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1204: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v11, vcc +; %bb.1205: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1547.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1206: + v_bfe_u32 v80, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v12, v80, s6 +; %bb.1207: ; %Flow753 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1208: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v12, vcc +; %bb.1209: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1550.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1210: + v_bfe_u32 v81, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v13, v81, s6 +; %bb.1211: ; %Flow752 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1212: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v13, vcc +; %bb.1213: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1553.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1214: + v_bfe_u32 v82, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v14, v82, s6 +; %bb.1215: ; %Flow751 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1216: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v14, vcc +; %bb.1217: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1556.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1218: + v_bfe_u32 v83, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v15, v83, s6 +; %bb.1219: ; %Flow750 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1220: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v15, vcc +; %bb.1221: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1559.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1222: + v_bfe_u32 v84, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v16, v84, s6 +; %bb.1223: ; %Flow749 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1224: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v16, vcc +; %bb.1225: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1562.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v85, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s2, v85 + ; implicit-def: $vgpr85 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1226: + v_bfe_u32 v85, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v85, v17, v85, s6 +; %bb.1227: ; %Flow748 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1228: + v_mov_b32_e32 v85, 0 + v_accvgpr_write_b32 a0, v86 + v_or_b32_e32 v86, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v85 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v85, v86, v17, vcc + v_accvgpr_read_b32 v86, a0 +; %bb.1229: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1566 + s_or_b64 exec, exec, s[2:3] + s_or_b32 s8, s18, 0x80 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v78 offset:10240 + ds_write_b16_d16_hi v74, v79 offset:10368 + ds_write_b16_d16_hi v74, v80 offset:10496 + ds_write_b16_d16_hi v74, v81 offset:10624 + ds_write_b16_d16_hi v74, v82 offset:11264 + ds_write_b16_d16_hi v74, v83 offset:11392 + ds_write_b16_d16_hi v74, v84 offset:11520 + ds_write_b16_d16_hi v74, v85 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v78, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v79, 0 + s_branch .LBB13_1231 +.LBB13_1230: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1629.i.i.i.i.i + ; in Loop: Header=BB13_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v82, v35, s11 + v_perm_b32 v34, v80, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1247 +.LBB13_1231: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1232: ; in Loop: Header=BB13_1231 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1233: ; %Flow747 + ; in Loop: Header=BB13_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1234: ; in Loop: Header=BB13_1231 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1235: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1620.i.i.i.i.i + ; in Loop: Header=BB13_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v80, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1236: ; in Loop: Header=BB13_1231 Depth=1 + v_bfe_u32 v80, v35, 16, 1 + v_add3_u32 v80, v35, v80, s10 + ; implicit-def: $vgpr35 +; %bb.1237: ; %Flow746 + ; in Loop: Header=BB13_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1238: ; in Loop: Header=BB13_1231 Depth=1 + v_or_b32_e32 v80, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v35, vcc +; %bb.1239: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1623.i.i.i.i.i + ; in Loop: Header=BB13_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v81, v78, v35 + v_and_b32_e32 v35, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1240: ; in Loop: Header=BB13_1231 Depth=1 + v_bfe_u32 v35, v81, 16, 1 + v_add3_u32 v35, v81, v35, s10 + ; implicit-def: $vgpr81 +; %bb.1241: ; %Flow745 + ; in Loop: Header=BB13_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1242: ; in Loop: Header=BB13_1231 Depth=1 + v_or_b32_e32 v35, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v81, vcc +; %bb.1243: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1626.i.i.i.i.i + ; in Loop: Header=BB13_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v81, 0xffff0000, v37 + v_add_f32_e32 v81, v31, v81 + v_and_b32_e32 v82, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1244: ; in Loop: Header=BB13_1231 Depth=1 + v_bfe_u32 v82, v81, 16, 1 + v_add3_u32 v82, v81, v82, s10 + ; implicit-def: $vgpr81 +; %bb.1245: ; %Flow744 + ; in Loop: Header=BB13_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1230 +; %bb.1246: ; in Loop: Header=BB13_1231 Depth=1 + v_or_b32_e32 v82, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v82, v81, vcc + s_branch .LBB13_1230 +.LBB13_1247: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1632.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_1249 +.LBB13_1248: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1645.i.i.i.i.i + ; in Loop: Header=BB13_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v80, v33, s11 + v_perm_b32 v32, v78, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1265 +.LBB13_1249: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1250: ; in Loop: Header=BB13_1249 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1251: ; %Flow743 + ; in Loop: Header=BB13_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1252: ; in Loop: Header=BB13_1249 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1253: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1636.i.i.i.i.i + ; in Loop: Header=BB13_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v78, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1254: ; in Loop: Header=BB13_1249 Depth=1 + v_bfe_u32 v78, v33, 16, 1 + v_add3_u32 v78, v33, v78, s10 + ; implicit-def: $vgpr33 +; %bb.1255: ; %Flow742 + ; in Loop: Header=BB13_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1256: ; in Loop: Header=BB13_1249 Depth=1 + v_or_b32_e32 v78, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v33, vcc +; %bb.1257: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1639.i.i.i.i.i + ; in Loop: Header=BB13_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v79, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1258: ; in Loop: Header=BB13_1249 Depth=1 + v_bfe_u32 v33, v79, 16, 1 + v_add3_u32 v33, v79, v33, s10 + ; implicit-def: $vgpr79 +; %bb.1259: ; %Flow741 + ; in Loop: Header=BB13_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1260: ; in Loop: Header=BB13_1249 Depth=1 + v_or_b32_e32 v33, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v79, vcc +; %bb.1261: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1642.i.i.i.i.i + ; in Loop: Header=BB13_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v35 + v_add_f32_e32 v79, v37, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1262: ; in Loop: Header=BB13_1249 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1263: ; %Flow740 + ; in Loop: Header=BB13_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1248 +; %bb.1264: ; in Loop: Header=BB13_1249 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB13_1248 +.LBB13_1265: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1649 + s_or_b64 exec, exec, s[2:3] + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_1267 +.LBB13_1266: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1662.i.i.i.i.i + ; in Loop: Header=BB13_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1283 +.LBB13_1267: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1268: ; in Loop: Header=BB13_1267 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1269: ; %Flow739 + ; in Loop: Header=BB13_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1270: ; in Loop: Header=BB13_1267 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1271: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1653.i.i.i.i.i + ; in Loop: Header=BB13_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1272: ; in Loop: Header=BB13_1267 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1273: ; %Flow738 + ; in Loop: Header=BB13_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1274: ; in Loop: Header=BB13_1267 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1275: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1656.i.i.i.i.i + ; in Loop: Header=BB13_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1276: ; in Loop: Header=BB13_1267 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1277: ; %Flow737 + ; in Loop: Header=BB13_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1278: ; in Loop: Header=BB13_1267 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1279: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1659.i.i.i.i.i + ; in Loop: Header=BB13_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1280: ; in Loop: Header=BB13_1267 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1281: ; %Flow736 + ; in Loop: Header=BB13_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1266 +; %bb.1282: ; in Loop: Header=BB13_1267 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB13_1266 +.LBB13_1283: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1665.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1285 +.LBB13_1284: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1678.i.i.i.i.i + ; in Loop: Header=BB13_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1301 +.LBB13_1285: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1286: ; in Loop: Header=BB13_1285 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1287: ; %Flow735 + ; in Loop: Header=BB13_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1288: ; in Loop: Header=BB13_1285 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1289: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1669.i.i.i.i.i + ; in Loop: Header=BB13_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1290: ; in Loop: Header=BB13_1285 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1291: ; %Flow734 + ; in Loop: Header=BB13_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1292: ; in Loop: Header=BB13_1285 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1293: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1672.i.i.i.i.i + ; in Loop: Header=BB13_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1294: ; in Loop: Header=BB13_1285 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1295: ; %Flow733 + ; in Loop: Header=BB13_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1296: ; in Loop: Header=BB13_1285 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1297: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1675.i.i.i.i.i + ; in Loop: Header=BB13_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1298: ; in Loop: Header=BB13_1285 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1299: ; %Flow732 + ; in Loop: Header=BB13_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1284 +; %bb.1300: ; in Loop: Header=BB13_1285 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_1284 +.LBB13_1301: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1682 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1303 +.LBB13_1302: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1695.i.i.i.i.i + ; in Loop: Header=BB13_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1319 +.LBB13_1303: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1304: ; in Loop: Header=BB13_1303 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1305: ; %Flow731 + ; in Loop: Header=BB13_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1306: ; in Loop: Header=BB13_1303 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1307: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1686.i.i.i.i.i + ; in Loop: Header=BB13_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1308: ; in Loop: Header=BB13_1303 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1309: ; %Flow730 + ; in Loop: Header=BB13_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1310: ; in Loop: Header=BB13_1303 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1311: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1689.i.i.i.i.i + ; in Loop: Header=BB13_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1312: ; in Loop: Header=BB13_1303 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1313: ; %Flow729 + ; in Loop: Header=BB13_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1314: ; in Loop: Header=BB13_1303 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1315: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1692.i.i.i.i.i + ; in Loop: Header=BB13_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1316: ; in Loop: Header=BB13_1303 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1317: ; %Flow728 + ; in Loop: Header=BB13_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1302 +; %bb.1318: ; in Loop: Header=BB13_1303 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB13_1302 +.LBB13_1319: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1698.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_1321 +.LBB13_1320: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1711.i.i.i.i.i + ; in Loop: Header=BB13_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1337 +.LBB13_1321: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1322: ; in Loop: Header=BB13_1321 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1323: ; %Flow727 + ; in Loop: Header=BB13_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1324: ; in Loop: Header=BB13_1321 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1325: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1702.i.i.i.i.i + ; in Loop: Header=BB13_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1326: ; in Loop: Header=BB13_1321 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1327: ; %Flow726 + ; in Loop: Header=BB13_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1328: ; in Loop: Header=BB13_1321 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1329: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1705.i.i.i.i.i + ; in Loop: Header=BB13_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1330: ; in Loop: Header=BB13_1321 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1331: ; %Flow725 + ; in Loop: Header=BB13_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1332: ; in Loop: Header=BB13_1321 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1333: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1708.i.i.i.i.i + ; in Loop: Header=BB13_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1334: ; in Loop: Header=BB13_1321 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1335: ; %Flow724 + ; in Loop: Header=BB13_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1320 +; %bb.1336: ; in Loop: Header=BB13_1321 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_1320 +.LBB13_1337: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1715 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_1339 +.LBB13_1338: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1728.i.i.i.i.i + ; in Loop: Header=BB13_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1355 +.LBB13_1339: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1340: ; in Loop: Header=BB13_1339 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1341: ; %Flow723 + ; in Loop: Header=BB13_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1342: ; in Loop: Header=BB13_1339 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1343: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1719.i.i.i.i.i + ; in Loop: Header=BB13_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1344: ; in Loop: Header=BB13_1339 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1345: ; %Flow722 + ; in Loop: Header=BB13_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1346: ; in Loop: Header=BB13_1339 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1347: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1722.i.i.i.i.i + ; in Loop: Header=BB13_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1348: ; in Loop: Header=BB13_1339 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1349: ; %Flow721 + ; in Loop: Header=BB13_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1350: ; in Loop: Header=BB13_1339 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1351: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1725.i.i.i.i.i + ; in Loop: Header=BB13_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1352: ; in Loop: Header=BB13_1339 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1353: ; %Flow720 + ; in Loop: Header=BB13_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1338 +; %bb.1354: ; in Loop: Header=BB13_1339 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_1338 +.LBB13_1355: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1731.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_1357 +.LBB13_1356: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1744.i.i.i.i.i + ; in Loop: Header=BB13_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1373 +.LBB13_1357: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1358: ; in Loop: Header=BB13_1357 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1359: ; %Flow719 + ; in Loop: Header=BB13_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1360: ; in Loop: Header=BB13_1357 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1361: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1735.i.i.i.i.i + ; in Loop: Header=BB13_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1362: ; in Loop: Header=BB13_1357 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1363: ; %Flow718 + ; in Loop: Header=BB13_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1364: ; in Loop: Header=BB13_1357 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1365: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1738.i.i.i.i.i + ; in Loop: Header=BB13_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1366: ; in Loop: Header=BB13_1357 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1367: ; %Flow717 + ; in Loop: Header=BB13_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1368: ; in Loop: Header=BB13_1357 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1369: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1741.i.i.i.i.i + ; in Loop: Header=BB13_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1370: ; in Loop: Header=BB13_1357 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1371: ; %Flow716 + ; in Loop: Header=BB13_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1356 +; %bb.1372: ; in Loop: Header=BB13_1357 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_1356 +.LBB13_1373: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1876 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1374: + v_bfe_u32 v18, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v140, v18, s6 +; %bb.1375: ; %Flow715 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1376: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v140, vcc +; %bb.1377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1941.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1378: + v_bfe_u32 v19, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v139, v19, s6 +; %bb.1379: ; %Flow714 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1380: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v139, vcc +; %bb.1381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1944.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1382: + v_bfe_u32 v20, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v138, v20, s6 +; %bb.1383: ; %Flow713 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1384: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v138, vcc +; %bb.1385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1947.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1386: + v_bfe_u32 v21, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v137, v21, s6 +; %bb.1387: ; %Flow712 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1388: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v137, vcc +; %bb.1389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1950.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1390: + v_bfe_u32 v22, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v136, v22, s6 +; %bb.1391: ; %Flow711 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1392: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v136, vcc +; %bb.1393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1953.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1394: + v_bfe_u32 v23, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v135, v23, s6 +; %bb.1395: ; %Flow710 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1396: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v135, vcc +; %bb.1397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1956.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1398: + v_bfe_u32 v24, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v134, v24, s6 +; %bb.1399: ; %Flow709 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1400: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v134, vcc +; %bb.1401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1959.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1402: + v_bfe_u32 v25, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v133, v25, s6 +; %bb.1403: ; %Flow708 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1404: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v133, vcc +; %bb.1405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1962.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1406: + v_bfe_u32 v26, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v132, v26, s6 +; %bb.1407: ; %Flow707 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1408: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v132, vcc +; %bb.1409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1965.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1410: + v_bfe_u32 v27, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v131, v27, s6 +; %bb.1411: ; %Flow706 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1412: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v131, vcc +; %bb.1413: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1968.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1414: + v_bfe_u32 v28, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v130, v28, s6 +; %bb.1415: ; %Flow705 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1416: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v130, vcc +; %bb.1417: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1971.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1418: + v_bfe_u32 v29, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v129, v29, s6 +; %bb.1419: ; %Flow704 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1420: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v129, vcc +; %bb.1421: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1974.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1422: + v_bfe_u32 v30, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v128, v30, s6 +; %bb.1423: ; %Flow703 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1424: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v128, vcc +; %bb.1425: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1977.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1426: + v_bfe_u32 v31, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v127, v31, s6 +; %bb.1427: ; %Flow702 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1428: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v127, vcc +; %bb.1429: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1980.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1430: + v_bfe_u32 v32, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v126, v32, s6 +; %bb.1431: ; %Flow701 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1432: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v126, vcc +; %bb.1433: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1983.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1434: + v_bfe_u32 v33, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v124, v33, s6 +; %bb.1435: ; %Flow700 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1436: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v124, vcc +; %bb.1437: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1986.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1438: + v_bfe_u32 v34, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v125, v34, s6 +; %bb.1439: ; %Flow699 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1440: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v125, vcc +; %bb.1441: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1989.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1442: + v_bfe_u32 v35, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v123, v35, s6 +; %bb.1443: ; %Flow698 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1444: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v123, vcc +; %bb.1445: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1992.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1446: + v_bfe_u32 v36, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v122, v36, s6 +; %bb.1447: ; %Flow697 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1448: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v122, vcc +; %bb.1449: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1995.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1450: + v_bfe_u32 v37, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v121, v37, s6 +; %bb.1451: ; %Flow696 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1452: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v121, vcc +; %bb.1453: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1998.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1454: + v_bfe_u32 v40, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v120, v40, s6 +; %bb.1455: ; %Flow695 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1456: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v120, vcc +; %bb.1457: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2001.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1458: + v_bfe_u32 v41, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v119, v41, s6 +; %bb.1459: ; %Flow694 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1460: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v119, vcc +; %bb.1461: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2004.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1462: + v_bfe_u32 v42, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v118, v42, s6 +; %bb.1463: ; %Flow693 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1464: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v118, vcc +; %bb.1465: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2007.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1466: + v_bfe_u32 v43, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v117, v43, s6 +; %bb.1467: ; %Flow692 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1468: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v117, vcc +; %bb.1469: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2010.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1470: + v_bfe_u32 v77, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v116, v77, s6 +; %bb.1471: ; %Flow691 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1472: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v116, vcc +; %bb.1473: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2013.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1474: + v_bfe_u32 v78, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v115, v78, s6 +; %bb.1475: ; %Flow690 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1476: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v115, vcc +; %bb.1477: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2016.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1478: + v_bfe_u32 v79, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v114, v79, s6 +; %bb.1479: ; %Flow689 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1480: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v114, vcc +; %bb.1481: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2019.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1482: + v_bfe_u32 v80, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v113, v80, s6 +; %bb.1483: ; %Flow688 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1484: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v113, vcc +; %bb.1485: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2022.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1486: + v_bfe_u32 v81, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v112, v81, s6 +; %bb.1487: ; %Flow687 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1488: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v112, vcc +; %bb.1489: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2025.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1490: + v_bfe_u32 v82, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v111, v82, s6 +; %bb.1491: ; %Flow686 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1492: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v111, vcc +; %bb.1493: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2028.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1494: + v_bfe_u32 v83, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v110, v83, s6 +; %bb.1495: ; %Flow685 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1496: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v110, vcc +; %bb.1497: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2031.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1498: + v_bfe_u32 v84, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v109, v84, s6 +; %bb.1499: ; %Flow684 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1500: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v109, vcc +; %bb.1501: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2035 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB13_1503 +.LBB13_1502: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2098.i.i.i.i.i + ; in Loop: Header=BB13_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s11 + v_perm_b32 v34, v79, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1519 +.LBB13_1503: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1504: ; in Loop: Header=BB13_1503 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1505: ; %Flow683 + ; in Loop: Header=BB13_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1506: ; in Loop: Header=BB13_1503 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1507: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2089.i.i.i.i.i + ; in Loop: Header=BB13_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1508: ; in Loop: Header=BB13_1503 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s10 + ; implicit-def: $vgpr35 +; %bb.1509: ; %Flow682 + ; in Loop: Header=BB13_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1510: ; in Loop: Header=BB13_1503 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.1511: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2092.i.i.i.i.i + ; in Loop: Header=BB13_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1512: ; in Loop: Header=BB13_1503 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s10 + ; implicit-def: $vgpr80 +; %bb.1513: ; %Flow681 + ; in Loop: Header=BB13_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1514: ; in Loop: Header=BB13_1503 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.1515: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2095.i.i.i.i.i + ; in Loop: Header=BB13_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1516: ; in Loop: Header=BB13_1503 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s10 + ; implicit-def: $vgpr80 +; %bb.1517: ; %Flow680 + ; in Loop: Header=BB13_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1502 +; %bb.1518: ; in Loop: Header=BB13_1503 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB13_1502 +.LBB13_1519: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2101.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_1521 +.LBB13_1520: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2114.i.i.i.i.i + ; in Loop: Header=BB13_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s11 + v_perm_b32 v32, v77, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1537 +.LBB13_1521: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1522: ; in Loop: Header=BB13_1521 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1523: ; %Flow679 + ; in Loop: Header=BB13_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1524: ; in Loop: Header=BB13_1521 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1525: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2105.i.i.i.i.i + ; in Loop: Header=BB13_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1526: ; in Loop: Header=BB13_1521 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s10 + ; implicit-def: $vgpr33 +; %bb.1527: ; %Flow678 + ; in Loop: Header=BB13_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1528: ; in Loop: Header=BB13_1521 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.1529: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2108.i.i.i.i.i + ; in Loop: Header=BB13_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1530: ; in Loop: Header=BB13_1521 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s10 + ; implicit-def: $vgpr78 +; %bb.1531: ; %Flow677 + ; in Loop: Header=BB13_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1532: ; in Loop: Header=BB13_1521 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.1533: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2111.i.i.i.i.i + ; in Loop: Header=BB13_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1534: ; in Loop: Header=BB13_1521 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s10 + ; implicit-def: $vgpr78 +; %bb.1535: ; %Flow676 + ; in Loop: Header=BB13_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1520 +; %bb.1536: ; in Loop: Header=BB13_1521 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB13_1520 +.LBB13_1537: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2118 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a2 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB13_1539 +.LBB13_1538: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2131.i.i.i.i.i + ; in Loop: Header=BB13_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1555 +.LBB13_1539: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1540: ; in Loop: Header=BB13_1539 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1541: ; %Flow675 + ; in Loop: Header=BB13_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1542: ; in Loop: Header=BB13_1539 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1543: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2122.i.i.i.i.i + ; in Loop: Header=BB13_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1544: ; in Loop: Header=BB13_1539 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1545: ; %Flow674 + ; in Loop: Header=BB13_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1546: ; in Loop: Header=BB13_1539 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1547: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2125.i.i.i.i.i + ; in Loop: Header=BB13_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1548: ; in Loop: Header=BB13_1539 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1549: ; %Flow673 + ; in Loop: Header=BB13_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1550: ; in Loop: Header=BB13_1539 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1551: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2128.i.i.i.i.i + ; in Loop: Header=BB13_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1552: ; in Loop: Header=BB13_1539 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1553: ; %Flow672 + ; in Loop: Header=BB13_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1538 +; %bb.1554: ; in Loop: Header=BB13_1539 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB13_1538 +.LBB13_1555: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2134.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1557 +.LBB13_1556: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2147.i.i.i.i.i + ; in Loop: Header=BB13_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1573 +.LBB13_1557: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1558: ; in Loop: Header=BB13_1557 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1559: ; %Flow671 + ; in Loop: Header=BB13_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1560: ; in Loop: Header=BB13_1557 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1561: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2138.i.i.i.i.i + ; in Loop: Header=BB13_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1562: ; in Loop: Header=BB13_1557 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1563: ; %Flow670 + ; in Loop: Header=BB13_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1564: ; in Loop: Header=BB13_1557 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1565: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2141.i.i.i.i.i + ; in Loop: Header=BB13_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1566: ; in Loop: Header=BB13_1557 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1567: ; %Flow669 + ; in Loop: Header=BB13_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1568: ; in Loop: Header=BB13_1557 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1569: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2144.i.i.i.i.i + ; in Loop: Header=BB13_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1570: ; in Loop: Header=BB13_1557 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1571: ; %Flow668 + ; in Loop: Header=BB13_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1556 +; %bb.1572: ; in Loop: Header=BB13_1557 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_1556 +.LBB13_1573: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2151 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1575 +.LBB13_1574: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2164.i.i.i.i.i + ; in Loop: Header=BB13_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1591 +.LBB13_1575: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1576: ; in Loop: Header=BB13_1575 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1577: ; %Flow667 + ; in Loop: Header=BB13_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1578: ; in Loop: Header=BB13_1575 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1579: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2155.i.i.i.i.i + ; in Loop: Header=BB13_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1580: ; in Loop: Header=BB13_1575 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1581: ; %Flow666 + ; in Loop: Header=BB13_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1582: ; in Loop: Header=BB13_1575 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1583: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2158.i.i.i.i.i + ; in Loop: Header=BB13_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1584: ; in Loop: Header=BB13_1575 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1585: ; %Flow665 + ; in Loop: Header=BB13_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1586: ; in Loop: Header=BB13_1575 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1587: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2161.i.i.i.i.i + ; in Loop: Header=BB13_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1588: ; in Loop: Header=BB13_1575 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1589: ; %Flow664 + ; in Loop: Header=BB13_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1574 +; %bb.1590: ; in Loop: Header=BB13_1575 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB13_1574 +.LBB13_1591: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2167.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_1593 +.LBB13_1592: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2180.i.i.i.i.i + ; in Loop: Header=BB13_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1609 +.LBB13_1593: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1594: ; in Loop: Header=BB13_1593 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1595: ; %Flow663 + ; in Loop: Header=BB13_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1596: ; in Loop: Header=BB13_1593 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1597: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2171.i.i.i.i.i + ; in Loop: Header=BB13_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1598: ; in Loop: Header=BB13_1593 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1599: ; %Flow662 + ; in Loop: Header=BB13_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1600: ; in Loop: Header=BB13_1593 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1601: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2174.i.i.i.i.i + ; in Loop: Header=BB13_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1602: ; in Loop: Header=BB13_1593 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1603: ; %Flow661 + ; in Loop: Header=BB13_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1604: ; in Loop: Header=BB13_1593 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1605: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2177.i.i.i.i.i + ; in Loop: Header=BB13_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1606: ; in Loop: Header=BB13_1593 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1607: ; %Flow660 + ; in Loop: Header=BB13_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1592 +; %bb.1608: ; in Loop: Header=BB13_1593 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_1592 +.LBB13_1609: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2184 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_1611 +.LBB13_1610: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2197.i.i.i.i.i + ; in Loop: Header=BB13_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1627 +.LBB13_1611: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1612: ; in Loop: Header=BB13_1611 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1613: ; %Flow659 + ; in Loop: Header=BB13_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1614: ; in Loop: Header=BB13_1611 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1615: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2188.i.i.i.i.i + ; in Loop: Header=BB13_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1616: ; in Loop: Header=BB13_1611 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1617: ; %Flow658 + ; in Loop: Header=BB13_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1618: ; in Loop: Header=BB13_1611 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1619: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2191.i.i.i.i.i + ; in Loop: Header=BB13_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1620: ; in Loop: Header=BB13_1611 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1621: ; %Flow657 + ; in Loop: Header=BB13_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1622: ; in Loop: Header=BB13_1611 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1623: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2194.i.i.i.i.i + ; in Loop: Header=BB13_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1624: ; in Loop: Header=BB13_1611 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1625: ; %Flow656 + ; in Loop: Header=BB13_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1610 +; %bb.1626: ; in Loop: Header=BB13_1611 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_1610 +.LBB13_1627: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2200.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_1629 +.LBB13_1628: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2213.i.i.i.i.i + ; in Loop: Header=BB13_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1645 +.LBB13_1629: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1630: ; in Loop: Header=BB13_1629 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1631: ; %Flow655 + ; in Loop: Header=BB13_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1632: ; in Loop: Header=BB13_1629 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1633: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2204.i.i.i.i.i + ; in Loop: Header=BB13_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1634: ; in Loop: Header=BB13_1629 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1635: ; %Flow654 + ; in Loop: Header=BB13_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1636: ; in Loop: Header=BB13_1629 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1637: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2207.i.i.i.i.i + ; in Loop: Header=BB13_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1638: ; in Loop: Header=BB13_1629 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1639: ; %Flow653 + ; in Loop: Header=BB13_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1640: ; in Loop: Header=BB13_1629 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1641: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2210.i.i.i.i.i + ; in Loop: Header=BB13_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1642: ; in Loop: Header=BB13_1629 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1643: ; %Flow652 + ; in Loop: Header=BB13_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1628 +; %bb.1644: ; in Loop: Header=BB13_1629 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_1628 +.LBB13_1645: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2345 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1646: + v_bfe_u32 v18, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v108, v18, s6 +; %bb.1647: ; %Flow651 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1648: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v108, vcc +; %bb.1649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2410.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1650: + v_bfe_u32 v19, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v107, v19, s6 +; %bb.1651: ; %Flow650 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1652: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v107, vcc +; %bb.1653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2413.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1654: + v_bfe_u32 v20, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v106, v20, s6 +; %bb.1655: ; %Flow649 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1656: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v106, vcc +; %bb.1657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2416.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1658: + v_bfe_u32 v21, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v105, v21, s6 +; %bb.1659: ; %Flow648 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1660: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v105, vcc +; %bb.1661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2419.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1662: + v_bfe_u32 v22, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v104, v22, s6 +; %bb.1663: ; %Flow647 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1664: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v104, vcc +; %bb.1665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2422.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1666: + v_bfe_u32 v23, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v103, v23, s6 +; %bb.1667: ; %Flow646 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1668: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v103, vcc +; %bb.1669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2425.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1670: + v_bfe_u32 v24, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v102, v24, s6 +; %bb.1671: ; %Flow645 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1672: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v102, vcc +; %bb.1673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2428.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1674: + v_bfe_u32 v25, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v101, v25, s6 +; %bb.1675: ; %Flow644 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1676: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v101, vcc +; %bb.1677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2431.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1678: + v_bfe_u32 v26, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v100, v26, s6 +; %bb.1679: ; %Flow643 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1680: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v100, vcc +; %bb.1681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2434.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1682: + v_bfe_u32 v27, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v99, v27, s6 +; %bb.1683: ; %Flow642 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1684: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v99, vcc +; %bb.1685: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2437.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1686: + v_bfe_u32 v28, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v98, v28, s6 +; %bb.1687: ; %Flow641 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1688: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v98, vcc +; %bb.1689: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2440.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1690: + v_bfe_u32 v29, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v97, v29, s6 +; %bb.1691: ; %Flow640 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1692: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v97, vcc +; %bb.1693: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2443.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1694: + v_bfe_u32 v30, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v96, v30, s6 +; %bb.1695: ; %Flow639 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1696: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v96, vcc +; %bb.1697: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2446.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1698: + v_bfe_u32 v31, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v95, v31, s6 +; %bb.1699: ; %Flow638 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1700: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v95, vcc +; %bb.1701: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2449.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1702: + v_bfe_u32 v32, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v94, v32, s6 +; %bb.1703: ; %Flow637 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1704: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v94, vcc +; %bb.1705: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2452.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1706: + v_bfe_u32 v33, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v92, v33, s6 +; %bb.1707: ; %Flow636 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1708: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v92, vcc +; %bb.1709: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2455.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1710: + v_bfe_u32 v34, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v93, v34, s6 +; %bb.1711: ; %Flow635 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1712: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v93, vcc +; %bb.1713: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2458.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1714: + v_bfe_u32 v35, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v91, v35, s6 +; %bb.1715: ; %Flow634 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1716: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v91, vcc +; %bb.1717: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2461.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1718: + v_bfe_u32 v36, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v90, v36, s6 +; %bb.1719: ; %Flow633 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1720: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v90, vcc +; %bb.1721: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2464.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1722: + v_bfe_u32 v37, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v89, v37, s6 +; %bb.1723: ; %Flow632 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1724: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v89, vcc +; %bb.1725: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2467.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1726: + v_bfe_u32 v40, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v88, v40, s6 +; %bb.1727: ; %Flow631 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1728: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v88, vcc +; %bb.1729: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2470.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a41 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1730: + v_accvgpr_read_b32 v42, a41 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.1731: ; %Flow630 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1732: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a41 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.1733: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2473.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a40 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1734: + v_accvgpr_read_b32 v43, a40 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.1735: ; %Flow629 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1736: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a40 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.1737: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2476.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a23 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1738: + v_accvgpr_read_b32 v77, a23 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.1739: ; %Flow628 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1740: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a23 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.1741: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2479.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a22 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1742: + v_accvgpr_read_b32 v78, a22 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.1743: ; %Flow627 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1744: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a22 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.1745: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2482.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a21 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1746: + v_accvgpr_read_b32 v79, a21 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.1747: ; %Flow626 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1748: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a21 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.1749: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2485.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a20 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1750: + v_accvgpr_read_b32 v80, a20 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.1751: ; %Flow625 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1752: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a20 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.1753: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2488.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a19 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1754: + v_accvgpr_read_b32 v81, a19 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.1755: ; %Flow624 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1756: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a19 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.1757: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2491.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a18 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1758: + v_accvgpr_read_b32 v82, a18 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.1759: ; %Flow623 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1760: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a18 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.1761: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2494.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a17 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1762: + v_accvgpr_read_b32 v83, a17 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.1763: ; %Flow622 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1764: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a17 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.1765: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2497.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1766: + v_bfe_u32 v83, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v87, v83, s6 +; %bb.1767: ; %Flow621 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1768: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v87, vcc +; %bb.1769: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2500.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v84, a16 + v_and_b32_e32 v84, 0x7f800000, v84 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1770: + v_accvgpr_read_b32 v85, a16 + v_bfe_u32 v84, v85, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v85, v84, s6 +; %bb.1771: ; %Flow620 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1772: + v_mov_b32_e32 v84, 0 + v_accvgpr_write_b32 a0, v87 + v_accvgpr_read_b32 v87, a16 + v_or_b32_e32 v85, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v87, vcc + v_accvgpr_read_b32 v87, a0 +; %bb.1773: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2504 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB13_1775 +.LBB13_1774: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2567.i.i.i.i.i + ; in Loop: Header=BB13_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s11 + v_perm_b32 v34, v78, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1791 +.LBB13_1775: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1776: ; in Loop: Header=BB13_1775 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1777: ; %Flow619 + ; in Loop: Header=BB13_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1778: ; in Loop: Header=BB13_1775 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1779: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2558.i.i.i.i.i + ; in Loop: Header=BB13_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1780: ; in Loop: Header=BB13_1775 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s10 + ; implicit-def: $vgpr35 +; %bb.1781: ; %Flow618 + ; in Loop: Header=BB13_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1782: ; in Loop: Header=BB13_1775 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.1783: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2561.i.i.i.i.i + ; in Loop: Header=BB13_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1784: ; in Loop: Header=BB13_1775 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s10 + ; implicit-def: $vgpr79 +; %bb.1785: ; %Flow617 + ; in Loop: Header=BB13_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1786: ; in Loop: Header=BB13_1775 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.1787: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2564.i.i.i.i.i + ; in Loop: Header=BB13_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1788: ; in Loop: Header=BB13_1775 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1789: ; %Flow616 + ; in Loop: Header=BB13_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1774 +; %bb.1790: ; in Loop: Header=BB13_1775 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB13_1774 +.LBB13_1791: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB13_1793 +.LBB13_1792: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2583.i.i.i.i.i + ; in Loop: Header=BB13_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s11 + v_perm_b32 v32, v41, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1809 +.LBB13_1793: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1794: ; in Loop: Header=BB13_1793 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1795: ; %Flow615 + ; in Loop: Header=BB13_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1796: ; in Loop: Header=BB13_1793 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1797: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2574.i.i.i.i.i + ; in Loop: Header=BB13_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1798: ; in Loop: Header=BB13_1793 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s10 + ; implicit-def: $vgpr33 +; %bb.1799: ; %Flow614 + ; in Loop: Header=BB13_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1800: ; in Loop: Header=BB13_1793 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.1801: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2577.i.i.i.i.i + ; in Loop: Header=BB13_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1802: ; in Loop: Header=BB13_1793 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s10 + ; implicit-def: $vgpr77 +; %bb.1803: ; %Flow613 + ; in Loop: Header=BB13_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1804: ; in Loop: Header=BB13_1793 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.1805: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2580.i.i.i.i.i + ; in Loop: Header=BB13_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1806: ; in Loop: Header=BB13_1793 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s10 + ; implicit-def: $vgpr77 +; %bb.1807: ; %Flow612 + ; in Loop: Header=BB13_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1792 +; %bb.1808: ; in Loop: Header=BB13_1793 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB13_1792 +.LBB13_1809: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2587 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a1 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB13_1811 +.LBB13_1810: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2600.i.i.i.i.i + ; in Loop: Header=BB13_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s11 + v_perm_b32 v30, v41, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1827 +.LBB13_1811: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1812: ; in Loop: Header=BB13_1811 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1813: ; %Flow611 + ; in Loop: Header=BB13_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1814: ; in Loop: Header=BB13_1811 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1815: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2591.i.i.i.i.i + ; in Loop: Header=BB13_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1816: ; in Loop: Header=BB13_1811 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s10 + ; implicit-def: $vgpr31 +; %bb.1817: ; %Flow610 + ; in Loop: Header=BB13_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1818: ; in Loop: Header=BB13_1811 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.1819: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2594.i.i.i.i.i + ; in Loop: Header=BB13_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1820: ; in Loop: Header=BB13_1811 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s10 + ; implicit-def: $vgpr42 +; %bb.1821: ; %Flow609 + ; in Loop: Header=BB13_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1822: ; in Loop: Header=BB13_1811 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.1823: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2597.i.i.i.i.i + ; in Loop: Header=BB13_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1824: ; in Loop: Header=BB13_1811 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s10 + ; implicit-def: $vgpr42 +; %bb.1825: ; %Flow608 + ; in Loop: Header=BB13_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1810 +; %bb.1826: ; in Loop: Header=BB13_1811 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB13_1810 +.LBB13_1827: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1829 +.LBB13_1828: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2616.i.i.i.i.i + ; in Loop: Header=BB13_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s11 + v_perm_b32 v28, v39, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1845 +.LBB13_1829: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1830: ; in Loop: Header=BB13_1829 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1831: ; %Flow607 + ; in Loop: Header=BB13_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1832: ; in Loop: Header=BB13_1829 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1833: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2607.i.i.i.i.i + ; in Loop: Header=BB13_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1834: ; in Loop: Header=BB13_1829 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s10 + ; implicit-def: $vgpr29 +; %bb.1835: ; %Flow606 + ; in Loop: Header=BB13_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1836: ; in Loop: Header=BB13_1829 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.1837: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2610.i.i.i.i.i + ; in Loop: Header=BB13_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1838: ; in Loop: Header=BB13_1829 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s10 + ; implicit-def: $vgpr40 +; %bb.1839: ; %Flow605 + ; in Loop: Header=BB13_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1840: ; in Loop: Header=BB13_1829 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.1841: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2613.i.i.i.i.i + ; in Loop: Header=BB13_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1842: ; in Loop: Header=BB13_1829 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s10 + ; implicit-def: $vgpr40 +; %bb.1843: ; %Flow604 + ; in Loop: Header=BB13_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1828 +; %bb.1844: ; in Loop: Header=BB13_1829 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB13_1828 +.LBB13_1845: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2620 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_1847 +.LBB13_1846: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2633.i.i.i.i.i + ; in Loop: Header=BB13_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1863 +.LBB13_1847: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1848: ; in Loop: Header=BB13_1847 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1849: ; %Flow603 + ; in Loop: Header=BB13_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1850: ; in Loop: Header=BB13_1847 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1851: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2624.i.i.i.i.i + ; in Loop: Header=BB13_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1852: ; in Loop: Header=BB13_1847 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1853: ; %Flow602 + ; in Loop: Header=BB13_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1854: ; in Loop: Header=BB13_1847 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1855: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2627.i.i.i.i.i + ; in Loop: Header=BB13_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1856: ; in Loop: Header=BB13_1847 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1857: ; %Flow601 + ; in Loop: Header=BB13_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1858: ; in Loop: Header=BB13_1847 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1859: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2630.i.i.i.i.i + ; in Loop: Header=BB13_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1860: ; in Loop: Header=BB13_1847 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s10 + ; implicit-def: $vgpr37 +; %bb.1861: ; %Flow600 + ; in Loop: Header=BB13_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1846 +; %bb.1862: ; in Loop: Header=BB13_1847 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB13_1846 +.LBB13_1863: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2636.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_1865 +.LBB13_1864: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2649.i.i.i.i.i + ; in Loop: Header=BB13_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1881 +.LBB13_1865: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1866: ; in Loop: Header=BB13_1865 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1867: ; %Flow599 + ; in Loop: Header=BB13_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1868: ; in Loop: Header=BB13_1865 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1869: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2640.i.i.i.i.i + ; in Loop: Header=BB13_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1870: ; in Loop: Header=BB13_1865 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1871: ; %Flow598 + ; in Loop: Header=BB13_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1872: ; in Loop: Header=BB13_1865 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1873: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2643.i.i.i.i.i + ; in Loop: Header=BB13_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1874: ; in Loop: Header=BB13_1865 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1875: ; %Flow597 + ; in Loop: Header=BB13_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1876: ; in Loop: Header=BB13_1865 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1877: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2646.i.i.i.i.i + ; in Loop: Header=BB13_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1878: ; in Loop: Header=BB13_1865 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1879: ; %Flow596 + ; in Loop: Header=BB13_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1864 +; %bb.1880: ; in Loop: Header=BB13_1865 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_1864 +.LBB13_1881: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2653 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_1883 +.LBB13_1882: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2666.i.i.i.i.i + ; in Loop: Header=BB13_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1899 +.LBB13_1883: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1884: ; in Loop: Header=BB13_1883 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1885: ; %Flow595 + ; in Loop: Header=BB13_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1886: ; in Loop: Header=BB13_1883 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1887: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2657.i.i.i.i.i + ; in Loop: Header=BB13_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1888: ; in Loop: Header=BB13_1883 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1889: ; %Flow594 + ; in Loop: Header=BB13_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1890: ; in Loop: Header=BB13_1883 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1891: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2660.i.i.i.i.i + ; in Loop: Header=BB13_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1892: ; in Loop: Header=BB13_1883 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1893: ; %Flow593 + ; in Loop: Header=BB13_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1894: ; in Loop: Header=BB13_1883 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1895: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2663.i.i.i.i.i + ; in Loop: Header=BB13_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1896: ; in Loop: Header=BB13_1883 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1897: ; %Flow592 + ; in Loop: Header=BB13_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1882 +; %bb.1898: ; in Loop: Header=BB13_1883 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_1882 +.LBB13_1899: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2669.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_1901 +.LBB13_1900: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2682.i.i.i.i.i + ; in Loop: Header=BB13_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_1917 +.LBB13_1901: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1902: ; in Loop: Header=BB13_1901 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1903: ; %Flow591 + ; in Loop: Header=BB13_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1904: ; in Loop: Header=BB13_1901 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1905: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2673.i.i.i.i.i + ; in Loop: Header=BB13_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1906: ; in Loop: Header=BB13_1901 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1907: ; %Flow590 + ; in Loop: Header=BB13_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1908: ; in Loop: Header=BB13_1901 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1909: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2676.i.i.i.i.i + ; in Loop: Header=BB13_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1910: ; in Loop: Header=BB13_1901 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1911: ; %Flow589 + ; in Loop: Header=BB13_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1912: ; in Loop: Header=BB13_1901 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1913: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2679.i.i.i.i.i + ; in Loop: Header=BB13_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1914: ; in Loop: Header=BB13_1901 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1915: ; %Flow588 + ; in Loop: Header=BB13_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_1900 +; %bb.1916: ; in Loop: Header=BB13_1901 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_1900 +.LBB13_1917: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2814 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v18, a119 + v_and_b32_e32 v18, 0x7f800000, v18 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1918: + v_accvgpr_read_b32 v19, a119 + v_bfe_u32 v18, v19, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v19, v18, s6 +; %bb.1919: ; %Flow587 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1920: + v_mov_b32_e32 v18, 0 + v_accvgpr_read_b32 v20, a119 + v_or_b32_e32 v19, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v20, vcc +; %bb.1921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2879.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v19, a118 + v_and_b32_e32 v19, 0x7f800000, v19 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1922: + v_accvgpr_read_b32 v20, a118 + v_bfe_u32 v19, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v20, v19, s6 +; %bb.1923: ; %Flow586 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1924: + v_mov_b32_e32 v19, 0 + v_accvgpr_read_b32 v21, a118 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v21, vcc +; %bb.1925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2882.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v20, a117 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1926: + v_accvgpr_read_b32 v21, a117 + v_bfe_u32 v20, v21, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v21, v20, s6 +; %bb.1927: ; %Flow585 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1928: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v22, a117 + v_or_b32_e32 v21, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v22, vcc +; %bb.1929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2885.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v21, a116 + v_and_b32_e32 v21, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1930: + v_accvgpr_read_b32 v22, a116 + v_bfe_u32 v21, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v22, v21, s6 +; %bb.1931: ; %Flow584 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1932: + v_mov_b32_e32 v21, 0 + v_accvgpr_read_b32 v23, a116 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v23, vcc +; %bb.1933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2888.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v22, a115 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1934: + v_accvgpr_read_b32 v23, a115 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 +; %bb.1935: ; %Flow583 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1936: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a115 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.1937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2891.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v23, a114 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1938: + v_accvgpr_read_b32 v24, a114 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 +; %bb.1939: ; %Flow582 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1940: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a114 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.1941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2894.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v24, a113 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1942: + v_accvgpr_read_b32 v25, a113 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 +; %bb.1943: ; %Flow581 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1944: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a113 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.1945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2897.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v25, a112 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1946: + v_accvgpr_read_b32 v26, a112 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 +; %bb.1947: ; %Flow580 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1948: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a112 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.1949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2900.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v26, a103 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1950: + v_accvgpr_read_b32 v27, a103 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 +; %bb.1951: ; %Flow579 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1952: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a103 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.1953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2903.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v27, a102 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1954: + v_accvgpr_read_b32 v28, a102 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 +; %bb.1955: ; %Flow578 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1956: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a102 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.1957: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2906.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v28, a101 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1958: + v_accvgpr_read_b32 v29, a101 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 +; %bb.1959: ; %Flow577 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1960: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a101 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.1961: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2909.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v29, a100 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1962: + v_accvgpr_read_b32 v30, a100 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 +; %bb.1963: ; %Flow576 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1964: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a100 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.1965: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2912.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v30, a99 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1966: + v_accvgpr_read_b32 v31, a99 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 +; %bb.1967: ; %Flow575 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1968: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a99 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.1969: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2915.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v31, a98 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1970: + v_accvgpr_read_b32 v32, a98 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 +; %bb.1971: ; %Flow574 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1972: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a98 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.1973: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2918.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v32, a97 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1974: + v_accvgpr_read_b32 v33, a97 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 +; %bb.1975: ; %Flow573 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1976: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a97 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.1977: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2921.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v33, a96 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1978: + v_accvgpr_read_b32 v34, a96 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 +; %bb.1979: ; %Flow572 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1980: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a96 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.1981: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2924.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v34, a54 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1982: + v_accvgpr_read_b32 v35, a54 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 +; %bb.1983: ; %Flow571 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1984: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a54 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.1985: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2927.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v35, a53 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1986: + v_accvgpr_read_b32 v36, a53 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 +; %bb.1987: ; %Flow570 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1988: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a53 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.1989: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2930.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v36, a52 + v_and_b32_e32 v36, 0x7f800000, v36 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1990: + v_accvgpr_read_b32 v37, a52 + v_bfe_u32 v36, v37, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v37, v36, s6 +; %bb.1991: ; %Flow569 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1992: + v_mov_b32_e32 v36, 0 + v_accvgpr_read_b32 v39, a52 + v_or_b32_e32 v37, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v39, vcc +; %bb.1993: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2933.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v37, a51 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1994: + v_accvgpr_read_b32 v39, a51 + v_bfe_u32 v37, v39, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v39, v37, s6 +; %bb.1995: ; %Flow568 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1996: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v40, a51 + v_or_b32_e32 v39, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v40, vcc +; %bb.1997: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2936.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v39, a50 + v_and_b32_e32 v39, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1998: + v_accvgpr_read_b32 v40, a50 + v_bfe_u32 v39, v40, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v40, v39, s6 +; %bb.1999: ; %Flow567 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2000: + v_mov_b32_e32 v39, 0 + v_accvgpr_read_b32 v41, a50 + v_or_b32_e32 v40, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v41, vcc +; %bb.2001: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2939.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v40, a49 + v_and_b32_e32 v40, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2002: + v_accvgpr_read_b32 v41, a49 + v_bfe_u32 v40, v41, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v41, v40, s6 +; %bb.2003: ; %Flow566 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2004: + v_mov_b32_e32 v40, 0 + v_accvgpr_read_b32 v42, a49 + v_or_b32_e32 v41, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v42, vcc +; %bb.2005: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2942.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a48 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2006: + v_accvgpr_read_b32 v42, a48 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.2007: ; %Flow565 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2008: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a48 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.2009: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2945.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a39 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2010: + v_accvgpr_read_b32 v43, a39 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.2011: ; %Flow564 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2012: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a39 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.2013: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2948.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a38 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2014: + v_accvgpr_read_b32 v77, a38 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.2015: ; %Flow563 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2016: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a38 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.2017: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2951.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a37 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2018: + v_accvgpr_read_b32 v78, a37 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.2019: ; %Flow562 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2020: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a37 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.2021: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2954.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a36 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2022: + v_accvgpr_read_b32 v79, a36 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.2023: ; %Flow561 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2024: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a36 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.2025: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2957.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a35 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2026: + v_accvgpr_read_b32 v80, a35 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.2027: ; %Flow560 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2028: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a35 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.2029: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2960.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a34 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2030: + v_accvgpr_read_b32 v81, a34 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.2031: ; %Flow559 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2032: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a34 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.2033: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2963.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a33 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2034: + v_accvgpr_read_b32 v82, a33 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.2035: ; %Flow558 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2036: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a33 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.2037: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2966.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a32 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2038: + v_accvgpr_read_b32 v83, a32 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.2039: ; %Flow557 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2040: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a32 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.2041: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2969.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2042: + v_bfe_u32 v83, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v86, v83, s6 +; %bb.2043: ; %Flow556 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2044: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v86, vcc +; %bb.2045: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2973 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s8, v18 + v_mad_u64_u32 v[38:39], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[40:41], v[38:39], 1, s[0:1] + global_load_dwordx2 v[36:37], v[40:41], off + v_lshl_or_b32 v18, v18, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v42, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v43, 0 + s_branch .LBB13_2047 +.LBB13_2046: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i3036.i.i.i.i.i + ; in Loop: Header=BB13_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v76, v35, s10 + v_perm_b32 v34, v74, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[40:41], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2063 +.LBB13_2047: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2048: ; in Loop: Header=BB13_2047 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.2049: ; %Flow555 + ; in Loop: Header=BB13_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2050: ; in Loop: Header=BB13_2047 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.2051: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i3027.i.i.i.i.i + ; in Loop: Header=BB13_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v74, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2052: ; in Loop: Header=BB13_2047 Depth=1 + v_bfe_u32 v74, v35, 16, 1 + v_add3_u32 v74, v35, v74, s9 + ; implicit-def: $vgpr35 +; %bb.2053: ; %Flow554 + ; in Loop: Header=BB13_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2054: ; in Loop: Header=BB13_2047 Depth=1 + v_or_b32_e32 v74, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v35, vcc +; %bb.2055: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i3030.i.i.i.i.i + ; in Loop: Header=BB13_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v75, v42, v35 + v_and_b32_e32 v35, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2056: ; in Loop: Header=BB13_2047 Depth=1 + v_bfe_u32 v35, v75, 16, 1 + v_add3_u32 v35, v75, v35, s9 + ; implicit-def: $vgpr75 +; %bb.2057: ; %Flow553 + ; in Loop: Header=BB13_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2058: ; in Loop: Header=BB13_2047 Depth=1 + v_or_b32_e32 v35, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v75, vcc +; %bb.2059: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i3033.i.i.i.i.i + ; in Loop: Header=BB13_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v75, 0xffff0000, v37 + v_add_f32_e32 v75, v31, v75 + v_and_b32_e32 v76, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2060: ; in Loop: Header=BB13_2047 Depth=1 + v_bfe_u32 v76, v75, 16, 1 + v_add3_u32 v76, v75, v76, s9 + ; implicit-def: $vgpr75 +; %bb.2061: ; %Flow552 + ; in Loop: Header=BB13_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2046 +; %bb.2062: ; in Loop: Header=BB13_2047 Depth=1 + v_or_b32_e32 v76, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v75, vcc + s_branch .LBB13_2046 +.LBB13_2063: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i3039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[40:41], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB13_2065 +.LBB13_2064: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i3052.i.i.i.i.i + ; in Loop: Header=BB13_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v74, v33, s10 + v_perm_b32 v32, v42, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[40:41], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2081 +.LBB13_2065: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2066: ; in Loop: Header=BB13_2065 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.2067: ; %Flow551 + ; in Loop: Header=BB13_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2068: ; in Loop: Header=BB13_2065 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.2069: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i3043.i.i.i.i.i + ; in Loop: Header=BB13_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v42, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2070: ; in Loop: Header=BB13_2065 Depth=1 + v_bfe_u32 v42, v33, 16, 1 + v_add3_u32 v42, v33, v42, s9 + ; implicit-def: $vgpr33 +; %bb.2071: ; %Flow550 + ; in Loop: Header=BB13_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2072: ; in Loop: Header=BB13_2065 Depth=1 + v_or_b32_e32 v42, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v33, vcc +; %bb.2073: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i3046.i.i.i.i.i + ; in Loop: Header=BB13_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v43, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2074: ; in Loop: Header=BB13_2065 Depth=1 + v_bfe_u32 v33, v43, 16, 1 + v_add3_u32 v33, v43, v33, s9 + ; implicit-def: $vgpr43 +; %bb.2075: ; %Flow549 + ; in Loop: Header=BB13_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2076: ; in Loop: Header=BB13_2065 Depth=1 + v_or_b32_e32 v33, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v43, vcc +; %bb.2077: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i3049.i.i.i.i.i + ; in Loop: Header=BB13_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v35 + v_add_f32_e32 v43, v37, v43 + v_and_b32_e32 v74, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2078: ; in Loop: Header=BB13_2065 Depth=1 + v_bfe_u32 v74, v43, 16, 1 + v_add3_u32 v74, v43, v74, s9 + ; implicit-def: $vgpr43 +; %bb.2079: ; %Flow548 + ; in Loop: Header=BB13_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2064 +; %bb.2080: ; in Loop: Header=BB13_2065 Depth=1 + v_or_b32_e32 v74, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v43, vcc + s_branch .LBB13_2064 +.LBB13_2081: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3056 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v38 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v38, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB13_2083 +.LBB13_2082: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i3069.i.i.i.i.i + ; in Loop: Header=BB13_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v42, v31, s10 + v_perm_b32 v30, v40, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2099 +.LBB13_2083: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2084: ; in Loop: Header=BB13_2083 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.2085: ; %Flow547 + ; in Loop: Header=BB13_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2086: ; in Loop: Header=BB13_2083 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.2087: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i3060.i.i.i.i.i + ; in Loop: Header=BB13_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v40, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2088: ; in Loop: Header=BB13_2083 Depth=1 + v_bfe_u32 v40, v31, 16, 1 + v_add3_u32 v40, v31, v40, s9 + ; implicit-def: $vgpr31 +; %bb.2089: ; %Flow546 + ; in Loop: Header=BB13_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2090: ; in Loop: Header=BB13_2083 Depth=1 + v_or_b32_e32 v40, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v31, vcc +; %bb.2091: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i3063.i.i.i.i.i + ; in Loop: Header=BB13_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v41, v38, v31 + v_and_b32_e32 v31, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2092: ; in Loop: Header=BB13_2083 Depth=1 + v_bfe_u32 v31, v41, 16, 1 + v_add3_u32 v31, v41, v31, s9 + ; implicit-def: $vgpr41 +; %bb.2093: ; %Flow545 + ; in Loop: Header=BB13_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2094: ; in Loop: Header=BB13_2083 Depth=1 + v_or_b32_e32 v31, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v41, vcc +; %bb.2095: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i3066.i.i.i.i.i + ; in Loop: Header=BB13_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v33 + v_add_f32_e32 v41, v27, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2096: ; in Loop: Header=BB13_2083 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.2097: ; %Flow544 + ; in Loop: Header=BB13_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2082 +; %bb.2098: ; in Loop: Header=BB13_2083 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB13_2082 +.LBB13_2099: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i3072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_2101 +.LBB13_2100: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i3085.i.i.i.i.i + ; in Loop: Header=BB13_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v40, v29, s10 + v_perm_b32 v28, v38, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2117 +.LBB13_2101: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2102: ; in Loop: Header=BB13_2101 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.2103: ; %Flow543 + ; in Loop: Header=BB13_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2104: ; in Loop: Header=BB13_2101 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.2105: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i3076.i.i.i.i.i + ; in Loop: Header=BB13_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v38, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2106: ; in Loop: Header=BB13_2101 Depth=1 + v_bfe_u32 v38, v29, 16, 1 + v_add3_u32 v38, v29, v38, s9 + ; implicit-def: $vgpr29 +; %bb.2107: ; %Flow542 + ; in Loop: Header=BB13_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2108: ; in Loop: Header=BB13_2101 Depth=1 + v_or_b32_e32 v38, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v29, vcc +; %bb.2109: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i3079.i.i.i.i.i + ; in Loop: Header=BB13_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v39, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2110: ; in Loop: Header=BB13_2101 Depth=1 + v_bfe_u32 v29, v39, 16, 1 + v_add3_u32 v29, v39, v29, s9 + ; implicit-def: $vgpr39 +; %bb.2111: ; %Flow541 + ; in Loop: Header=BB13_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2112: ; in Loop: Header=BB13_2101 Depth=1 + v_or_b32_e32 v29, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v39, vcc +; %bb.2113: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i3082.i.i.i.i.i + ; in Loop: Header=BB13_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v39, 0xffff0000, v31 + v_add_f32_e32 v39, v33, v39 + v_and_b32_e32 v40, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2114: ; in Loop: Header=BB13_2101 Depth=1 + v_bfe_u32 v40, v39, 16, 1 + v_add3_u32 v40, v39, v40, s9 + ; implicit-def: $vgpr39 +; %bb.2115: ; %Flow540 + ; in Loop: Header=BB13_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2100 +; %bb.2116: ; in Loop: Header=BB13_2101 Depth=1 + v_or_b32_e32 v40, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v39, vcc + s_branch .LBB13_2100 +.LBB13_2117: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3089 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB13_2119 +.LBB13_2118: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i3102.i.i.i.i.i + ; in Loop: Header=BB13_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v38, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2135 +.LBB13_2119: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2120: ; in Loop: Header=BB13_2119 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.2121: ; %Flow539 + ; in Loop: Header=BB13_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2122: ; in Loop: Header=BB13_2119 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.2123: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i3093.i.i.i.i.i + ; in Loop: Header=BB13_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2124: ; in Loop: Header=BB13_2119 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.2125: ; %Flow538 + ; in Loop: Header=BB13_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2126: ; in Loop: Header=BB13_2119 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.2127: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i3096.i.i.i.i.i + ; in Loop: Header=BB13_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2128: ; in Loop: Header=BB13_2119 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.2129: ; %Flow537 + ; in Loop: Header=BB13_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2130: ; in Loop: Header=BB13_2119 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.2131: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i3099.i.i.i.i.i + ; in Loop: Header=BB13_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v38, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2132: ; in Loop: Header=BB13_2119 Depth=1 + v_bfe_u32 v38, v37, 16, 1 + v_add3_u32 v38, v37, v38, s9 + ; implicit-def: $vgpr37 +; %bb.2133: ; %Flow536 + ; in Loop: Header=BB13_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2118 +; %bb.2134: ; in Loop: Header=BB13_2119 Depth=1 + v_or_b32_e32 v38, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v37, vcc + s_branch .LBB13_2118 +.LBB13_2135: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i3105.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB13_2137 +.LBB13_2136: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i3118.i.i.i.i.i + ; in Loop: Header=BB13_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2153 +.LBB13_2137: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2138: ; in Loop: Header=BB13_2137 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.2139: ; %Flow535 + ; in Loop: Header=BB13_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2140: ; in Loop: Header=BB13_2137 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.2141: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i3109.i.i.i.i.i + ; in Loop: Header=BB13_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2142: ; in Loop: Header=BB13_2137 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.2143: ; %Flow534 + ; in Loop: Header=BB13_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2144: ; in Loop: Header=BB13_2137 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.2145: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i3112.i.i.i.i.i + ; in Loop: Header=BB13_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2146: ; in Loop: Header=BB13_2137 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.2147: ; %Flow533 + ; in Loop: Header=BB13_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2148: ; in Loop: Header=BB13_2137 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.2149: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i3115.i.i.i.i.i + ; in Loop: Header=BB13_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2150: ; in Loop: Header=BB13_2137 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.2151: ; %Flow532 + ; in Loop: Header=BB13_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2136 +; %bb.2152: ; in Loop: Header=BB13_2137 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB13_2136 +.LBB13_2153: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3122 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB13_2155 +.LBB13_2154: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i3135.i.i.i.i.i + ; in Loop: Header=BB13_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2171 +.LBB13_2155: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2156: ; in Loop: Header=BB13_2155 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.2157: ; %Flow531 + ; in Loop: Header=BB13_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2158: ; in Loop: Header=BB13_2155 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.2159: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i3126.i.i.i.i.i + ; in Loop: Header=BB13_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2160: ; in Loop: Header=BB13_2155 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.2161: ; %Flow530 + ; in Loop: Header=BB13_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2162: ; in Loop: Header=BB13_2155 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.2163: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i3129.i.i.i.i.i + ; in Loop: Header=BB13_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2164: ; in Loop: Header=BB13_2155 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.2165: ; %Flow529 + ; in Loop: Header=BB13_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2166: ; in Loop: Header=BB13_2155 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.2167: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i3132.i.i.i.i.i + ; in Loop: Header=BB13_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2168: ; in Loop: Header=BB13_2155 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.2169: ; %Flow528 + ; in Loop: Header=BB13_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2154 +; %bb.2170: ; in Loop: Header=BB13_2155 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB13_2154 +.LBB13_2171: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i3138.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB13_2173 +.LBB13_2172: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i3151.i.i.i.i.i + ; in Loop: Header=BB13_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB13_2189 +.LBB13_2173: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2174: ; in Loop: Header=BB13_2173 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.2175: ; %Flow526 + ; in Loop: Header=BB13_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2176: ; in Loop: Header=BB13_2173 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.2177: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i3142.i.i.i.i.i + ; in Loop: Header=BB13_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2178: ; in Loop: Header=BB13_2173 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.2179: ; %Flow525 + ; in Loop: Header=BB13_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2180: ; in Loop: Header=BB13_2173 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.2181: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i3145.i.i.i.i.i + ; in Loop: Header=BB13_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2182: ; in Loop: Header=BB13_2173 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.2183: ; %Flow524 + ; in Loop: Header=BB13_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2184: ; in Loop: Header=BB13_2173 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.2185: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i3148.i.i.i.i.i + ; in Loop: Header=BB13_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2186: ; in Loop: Header=BB13_2173 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.2187: ; %Flow + ; in Loop: Header=BB13_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB13_2172 +; %bb.2188: ; in Loop: Header=BB13_2173 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB13_2172 +.LBB13_2189: ; %Flow527 + s_or_b64 exec, exec, s[2:3] + s_mov_b64 vcc, 0 + s_branch .LBB13_12 +.LBB13_2190: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2191: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 + ; implicit-def: $vgpr73 +; %bb.2192: ; %Flow1291 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2193: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.2194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2195: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v19, v72, v19, s7 + ; implicit-def: $vgpr72 +; %bb.2196: ; %Flow1290 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2197: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v72, vcc +; %bb.2198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2199: + v_bfe_u32 v20, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v71, v20, s7 + ; implicit-def: $vgpr71 +; %bb.2200: ; %Flow1289 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2201: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v71, vcc +; %bb.2202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2203: + v_bfe_u32 v21, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v70, v21, s7 + ; implicit-def: $vgpr70 +; %bb.2204: ; %Flow1288 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2205: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v70, vcc +; %bb.2206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v67 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2207: + v_bfe_u32 v22, v67, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v67, v22, s7 + ; implicit-def: $vgpr67 +; %bb.2208: ; %Flow1287 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2209: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v67 + v_cmp_eq_u32_sdwa vcc, v67, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v67, vcc +; %bb.2210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2211: + v_bfe_u32 v23, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v66, v23, s7 + ; implicit-def: $vgpr66 +; %bb.2212: ; %Flow1286 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2213: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v66, vcc +; %bb.2214: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2215: + v_bfe_u32 v24, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v65, v24, s7 + ; implicit-def: $vgpr65 +; %bb.2216: ; %Flow1285 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2217: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v65, vcc +; %bb.2218: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2219: + v_bfe_u32 v25, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v64, v25, s7 + ; implicit-def: $vgpr64 +; %bb.2220: ; %Flow1284 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2221: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v64, vcc +; %bb.2222: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2223: + v_bfe_u32 v26, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v63, v26, s7 + ; implicit-def: $vgpr63 +; %bb.2224: ; %Flow1283 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2225: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v63, vcc +; %bb.2226: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2227: + v_bfe_u32 v27, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v62, v27, s7 + ; implicit-def: $vgpr62 +; %bb.2228: ; %Flow1282 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2229: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v62, vcc +; %bb.2230: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2231: + v_bfe_u32 v28, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v61, v28, s7 + ; implicit-def: $vgpr61 +; %bb.2232: ; %Flow1281 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2233: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v61, vcc +; %bb.2234: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2235: + v_bfe_u32 v29, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v60, v29, s7 + ; implicit-def: $vgpr60 +; %bb.2236: ; %Flow1280 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2237: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v60, vcc +; %bb.2238: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2239: + v_bfe_u32 v30, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v59, v30, s7 + ; implicit-def: $vgpr59 +; %bb.2240: ; %Flow1279 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2241: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v59, vcc +; %bb.2242: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2243: + v_bfe_u32 v31, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v58, v31, s7 + ; implicit-def: $vgpr58 +; %bb.2244: ; %Flow1278 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2245: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v58, vcc +; %bb.2246: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2247: + v_bfe_u32 v32, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v57, v32, s7 + ; implicit-def: $vgpr57 +; %bb.2248: ; %Flow1277 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2249: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v57, vcc +; %bb.2250: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2251: + v_bfe_u32 v33, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v55, v33, s7 + ; implicit-def: $vgpr55 +; %bb.2252: ; %Flow1276 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2253: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v55, vcc +; %bb.2254: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2255: + v_bfe_u32 v34, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v56, v34, s7 + ; implicit-def: $vgpr56 +; %bb.2256: ; %Flow1275 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2257: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v56, vcc +; %bb.2258: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2259: + v_bfe_u32 v35, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v54, v35, s7 + ; implicit-def: $vgpr54 +; %bb.2260: ; %Flow1274 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2261: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v54, vcc +; %bb.2262: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2263: + v_bfe_u32 v36, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v53, v36, s7 + ; implicit-def: $vgpr53 +; %bb.2264: ; %Flow1273 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2265: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v53, vcc +; %bb.2266: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2267: + v_bfe_u32 v37, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v52, v37, s7 + ; implicit-def: $vgpr52 +; %bb.2268: ; %Flow1272 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2269: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v52, vcc +; %bb.2270: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2271: + v_bfe_u32 v38, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v51, v38, s7 + ; implicit-def: $vgpr51 +; %bb.2272: ; %Flow1271 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2273: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v51, vcc +; %bb.2274: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2275: + v_bfe_u32 v39, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v50, v39, s7 + ; implicit-def: $vgpr50 +; %bb.2276: ; %Flow1270 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2277: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v50, vcc +; %bb.2278: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2279: + v_bfe_u32 v40, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v49, v40, s7 + ; implicit-def: $vgpr49 +; %bb.2280: ; %Flow1269 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2281: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v49, vcc +; %bb.2282: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2283: + v_bfe_u32 v41, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v48, v41, s7 + ; implicit-def: $vgpr48 +; %bb.2284: ; %Flow1268 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2285: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v48, vcc +; %bb.2286: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2287: + v_bfe_u32 v42, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v47, v42, s7 + ; implicit-def: $vgpr47 +; %bb.2288: ; %Flow1267 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2289: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v47, vcc +; %bb.2290: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2291: + v_bfe_u32 v43, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v46, v43, s7 + ; implicit-def: $vgpr46 +; %bb.2292: ; %Flow1266 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2293: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v47, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v47, v46, vcc +; %bb.2294: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2295: + v_bfe_u32 v46, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v46, v45, v46, s7 + ; implicit-def: $vgpr45 +; %bb.2296: ; %Flow1265 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2297: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v45, vcc +; %bb.2298: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2299: + v_bfe_u32 v45, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v45, v44, v45, s7 + ; implicit-def: $vgpr44 +; %bb.2300: ; %Flow1264 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2301: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v47, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v47, v44, vcc +; %bb.2302: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s2, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2303: + v_bfe_u32 v44, v1, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v44, v1, v44, s7 + ; implicit-def: $vgpr1 +; %bb.2304: ; %Flow1263 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2305: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v47, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v47, v1, vcc +; %bb.2306: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v1, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v1 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2307: + v_bfe_u32 v1, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v47, v255, v1, s7 + ; implicit-def: $vgpr255 +; %bb.2308: ; %Flow1262 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2309: + v_mov_b32_e32 v1, 0 + v_or_b32_e32 v47, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v1 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v47, v255, vcc +; %bb.2310: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v1, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v1 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2311: + v_bfe_u32 v1, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v48, v254, v1, s7 + ; implicit-def: $vgpr254 +; %bb.2312: ; %Flow1261 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2313: + v_mov_b32_e32 v1, 0 + v_or_b32_e32 v48, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v1 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v48, v254, vcc +; %bb.2314: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v1, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v1 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2315: + v_bfe_u32 v1, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v49, v253, v1, s7 + ; implicit-def: $vgpr253 +; %bb.2316: ; %Flow1260 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2317: + v_mov_b32_e32 v1, 0 + v_or_b32_e32 v49, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v1 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v49, v253, vcc +; %bb.2318: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_add_i32 s2, s4, 0x7fffffff + s_mul_i32 s4, s2, s16 + v_and_b32_e32 v1, 24, v68 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v50, 3, v68 + v_and_or_b32 v50, v50, 12, s2 + v_lshlrev_b32_e32 v50, 7, v50 + v_lshl_or_b32 v50, v69, 1, v50 + v_lshlrev_b32_e32 v1, 1, v1 + s_and_b32 s2, s6, 64 + v_or3_b32 v1, v50, v1, s2 + ds_write_b16_d16_hi v1, v18 + ds_write_b16_d16_hi v1, v19 offset:128 + ds_write_b16_d16_hi v1, v20 offset:256 + ds_write_b16_d16_hi v1, v21 offset:384 + ds_write_b16_d16_hi v1, v22 offset:1024 + ds_write_b16_d16_hi v1, v23 offset:1152 + ds_write_b16_d16_hi v1, v24 offset:1280 + ds_write_b16_d16_hi v1, v25 offset:1408 + ds_write_b16_d16_hi v1, v26 offset:2048 + ds_write_b16_d16_hi v1, v27 offset:2176 + ds_write_b16_d16_hi v1, v28 offset:2304 + ds_write_b16_d16_hi v1, v29 offset:2432 + ds_write_b16_d16_hi v1, v30 offset:3072 + ds_write_b16_d16_hi v1, v31 offset:3200 + ds_write_b16_d16_hi v1, v32 offset:3328 + ds_write_b16_d16_hi v1, v33 offset:3456 + ds_write_b16_d16_hi v1, v34 offset:8192 + ds_write_b16_d16_hi v1, v35 offset:8320 + ds_write_b16_d16_hi v1, v36 offset:8448 + ds_write_b16_d16_hi v1, v37 offset:8576 + ds_write_b16_d16_hi v1, v38 offset:9216 + ds_write_b16_d16_hi v1, v39 offset:9344 + ds_write_b16_d16_hi v1, v40 offset:9472 + ds_write_b16_d16_hi v1, v41 offset:9600 + ds_write_b16_d16_hi v1, v42 offset:10240 + ds_write_b16_d16_hi v1, v43 offset:10368 + ds_write_b16_d16_hi v1, v46 offset:10496 + ds_write_b16_d16_hi v1, v45 offset:10624 + ds_write_b16_d16_hi v1, v44 offset:11264 + ds_write_b16_d16_hi v1, v47 offset:11392 + ds_write_b16_d16_hi v1, v48 offset:11520 + ds_write_b16_d16_hi v1, v49 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v68 + v_and_b32_e32 v20, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v18, 1, v68 + v_and_b32_e32 v19, 60, v18 + v_add_u32_e32 v18, s2, v19 + v_lshlrev_b32_e32 v21, 7, v18 + v_lshl_or_b32 v21, v20, 1, v21 + ds_read_b128 v[24:27], v21 + ds_read_b128 v[28:31], v21 offset:128 + ds_read_b128 v[32:35], v21 offset:256 + ds_read_b128 v[36:39], v21 offset:384 + v_add_u32_e32 v21, s18, v18 + v_or_b32_e32 v18, s19, v20 + v_mad_u64_u32 v[22:23], s[2:3], v21, s16, v[18:19] + s_add_i32 s2, s5, s4 + s_lshl_b32 s2, s2, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v21, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v21, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v22 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v22, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v21 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v22, s[0:3], 8 offen + v_add_lshl_u32 v21, v21, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v21, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s4, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2319: + v_bfe_u32 v21, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v252, v21, s6 + ; implicit-def: $vgpr252 +; %bb.2320: ; %Flow1259 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2321: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v252, vcc +; %bb.2322: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2323: + v_bfe_u32 v22, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v251, v22, s6 + ; implicit-def: $vgpr251 +; %bb.2324: ; %Flow1258 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2325: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v251, vcc +; %bb.2326: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2327: + v_bfe_u32 v23, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v250, v23, s6 + ; implicit-def: $vgpr250 +; %bb.2328: ; %Flow1257 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2329: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v250, vcc +; %bb.2330: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2331: + v_bfe_u32 v24, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v249, v24, s6 + ; implicit-def: $vgpr249 +; %bb.2332: ; %Flow1256 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2333: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v249, vcc +; %bb.2334: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2335: + v_bfe_u32 v25, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v248, v25, s6 + ; implicit-def: $vgpr248 +; %bb.2336: ; %Flow1255 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2337: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v248, vcc +; %bb.2338: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2339: + v_bfe_u32 v26, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v247, v26, s6 + ; implicit-def: $vgpr247 +; %bb.2340: ; %Flow1254 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2341: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v247, vcc +; %bb.2342: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2343: + v_bfe_u32 v27, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v246, v27, s6 + ; implicit-def: $vgpr246 +; %bb.2344: ; %Flow1253 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2345: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v246, vcc +; %bb.2346: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2347: + v_bfe_u32 v28, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v245, v28, s6 + ; implicit-def: $vgpr245 +; %bb.2348: ; %Flow1252 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2349: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v245, vcc +; %bb.2350: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2351: + v_bfe_u32 v29, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v244, v29, s6 + ; implicit-def: $vgpr244 +; %bb.2352: ; %Flow1251 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2353: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v244, vcc +; %bb.2354: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2355: + v_bfe_u32 v30, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v243, v30, s6 + ; implicit-def: $vgpr243 +; %bb.2356: ; %Flow1250 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2357: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v243, vcc +; %bb.2358: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2359: + v_bfe_u32 v31, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v242, v31, s6 + ; implicit-def: $vgpr242 +; %bb.2360: ; %Flow1249 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2361: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v242, vcc +; %bb.2362: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2363: + v_bfe_u32 v32, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v241, v32, s6 + ; implicit-def: $vgpr241 +; %bb.2364: ; %Flow1248 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2365: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v241, vcc +; %bb.2366: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2367: + v_bfe_u32 v33, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v240, v33, s6 + ; implicit-def: $vgpr240 +; %bb.2368: ; %Flow1247 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2369: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v240, vcc +; %bb.2370: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2371: + v_bfe_u32 v34, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v239, v34, s6 + ; implicit-def: $vgpr239 +; %bb.2372: ; %Flow1246 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2373: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v239, vcc +; %bb.2374: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2375: + v_bfe_u32 v35, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v238, v35, s6 + ; implicit-def: $vgpr238 +; %bb.2376: ; %Flow1245 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2377: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v238, vcc +; %bb.2378: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2379: + v_bfe_u32 v36, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v236, v36, s6 + ; implicit-def: $vgpr236 +; %bb.2380: ; %Flow1244 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2381: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v236, vcc +; %bb.2382: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2383: + v_bfe_u32 v37, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v237, v37, s6 + ; implicit-def: $vgpr237 +; %bb.2384: ; %Flow1243 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2385: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v237, vcc +; %bb.2386: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2387: + v_bfe_u32 v38, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v235, v38, s6 + ; implicit-def: $vgpr235 +; %bb.2388: ; %Flow1242 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2389: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v235, vcc +; %bb.2390: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2391: + v_bfe_u32 v39, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v234, v39, s6 + ; implicit-def: $vgpr234 +; %bb.2392: ; %Flow1241 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2393: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v234, vcc +; %bb.2394: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2395: + v_bfe_u32 v40, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v233, v40, s6 + ; implicit-def: $vgpr233 +; %bb.2396: ; %Flow1240 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2397: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v233, vcc +; %bb.2398: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2399: + v_bfe_u32 v41, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v232, v41, s6 + ; implicit-def: $vgpr232 +; %bb.2400: ; %Flow1239 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2401: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v232, vcc +; %bb.2402: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2403: + v_bfe_u32 v42, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v231, v42, s6 + ; implicit-def: $vgpr231 +; %bb.2404: ; %Flow1238 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2405: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v231, vcc +; %bb.2406: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2407: + v_bfe_u32 v43, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v230, v43, s6 + ; implicit-def: $vgpr230 +; %bb.2408: ; %Flow1237 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2409: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v230, vcc +; %bb.2410: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2411: + v_bfe_u32 v44, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v229, v44, s6 + ; implicit-def: $vgpr229 +; %bb.2412: ; %Flow1236 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2413: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v229, vcc +; %bb.2414: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2415: + v_bfe_u32 v45, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v228, v45, s6 + ; implicit-def: $vgpr228 +; %bb.2416: ; %Flow1235 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2417: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v228, vcc +; %bb.2418: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2419: + v_bfe_u32 v46, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v227, v46, s6 + ; implicit-def: $vgpr227 +; %bb.2420: ; %Flow1234 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2421: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v227, vcc +; %bb.2422: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2423: + v_bfe_u32 v47, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v226, v47, s6 + ; implicit-def: $vgpr226 +; %bb.2424: ; %Flow1233 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2425: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v226, vcc +; %bb.2426: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2427: + v_bfe_u32 v48, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v225, v48, s6 + ; implicit-def: $vgpr225 +; %bb.2428: ; %Flow1232 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2429: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v225, vcc +; %bb.2430: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2431: + v_bfe_u32 v49, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v224, v49, s6 + ; implicit-def: $vgpr224 +; %bb.2432: ; %Flow1231 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2433: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v224, vcc +; %bb.2434: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2435: + v_bfe_u32 v50, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v223, v50, s6 + ; implicit-def: $vgpr223 +; %bb.2436: ; %Flow1230 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2437: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v223, vcc +; %bb.2438: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2439: + v_bfe_u32 v51, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v222, v51, s6 + ; implicit-def: $vgpr222 +; %bb.2440: ; %Flow1229 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2441: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v222, vcc +; %bb.2442: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2443: + v_bfe_u32 v52, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v221, v52, s6 + ; implicit-def: $vgpr221 +; %bb.2444: ; %Flow1228 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2445: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v221, vcc +; %bb.2446: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_287 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v21 + ds_write_b16_d16_hi v1, v22 offset:128 + ds_write_b16_d16_hi v1, v23 offset:256 + ds_write_b16_d16_hi v1, v24 offset:384 + ds_write_b16_d16_hi v1, v25 offset:1024 + ds_write_b16_d16_hi v1, v26 offset:1152 + ds_write_b16_d16_hi v1, v27 offset:1280 + ds_write_b16_d16_hi v1, v28 offset:1408 + ds_write_b16_d16_hi v1, v29 offset:2048 + ds_write_b16_d16_hi v1, v30 offset:2176 + ds_write_b16_d16_hi v1, v31 offset:2304 + ds_write_b16_d16_hi v1, v32 offset:2432 + ds_write_b16_d16_hi v1, v33 offset:3072 + ds_write_b16_d16_hi v1, v34 offset:3200 + ds_write_b16_d16_hi v1, v35 offset:3328 + ds_write_b16_d16_hi v1, v36 offset:3456 + ds_write_b16_d16_hi v1, v37 offset:8192 + ds_write_b16_d16_hi v1, v38 offset:8320 + ds_write_b16_d16_hi v1, v39 offset:8448 + ds_write_b16_d16_hi v1, v40 offset:8576 + ds_write_b16_d16_hi v1, v41 offset:9216 + ds_write_b16_d16_hi v1, v42 offset:9344 + ds_write_b16_d16_hi v1, v43 offset:9472 + ds_write_b16_d16_hi v1, v44 offset:9600 + ds_write_b16_d16_hi v1, v45 offset:10240 + ds_write_b16_d16_hi v1, v46 offset:10368 + ds_write_b16_d16_hi v1, v47 offset:10496 + ds_write_b16_d16_hi v1, v48 offset:10624 + ds_write_b16_d16_hi v1, v49 offset:11264 + ds_write_b16_d16_hi v1, v50 offset:11392 + ds_write_b16_d16_hi v1, v51 offset:11520 + ds_write_b16_d16_hi v1, v52 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v19 + v_lshlrev_b32_e32 v21, 1, v20 + v_lshl_or_b32 v20, v22, 7, v21 + ds_read_b128 v[24:27], v20 + ds_read_b128 v[28:31], v20 offset:128 + ds_read_b128 v[32:35], v20 offset:256 + ds_read_b128 v[36:39], v20 offset:384 + v_add_u32_e32 v22, s18, v22 + v_or_b32_e32 v20, 64, v18 + v_mad_u64_u32 v[22:23], s[4:5], v22, s16, v[20:21] + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v23, s[0:3], 8 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v22, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2447: + v_bfe_u32 v22, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v220, v22, s6 + ; implicit-def: $vgpr220 +; %bb.2448: ; %Flow1227 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2449: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v220, vcc +; %bb.2450: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i352.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2451: + v_bfe_u32 v23, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v219, v23, s6 + ; implicit-def: $vgpr219 +; %bb.2452: ; %Flow1226 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2453: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v219, vcc +; %bb.2454: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i355.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2455: + v_bfe_u32 v24, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v218, v24, s6 + ; implicit-def: $vgpr218 +; %bb.2456: ; %Flow1225 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2457: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v218, vcc +; %bb.2458: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i358.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2459: + v_bfe_u32 v25, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v217, v25, s6 + ; implicit-def: $vgpr217 +; %bb.2460: ; %Flow1224 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2461: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v217, vcc +; %bb.2462: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i361.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2463: + v_bfe_u32 v26, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v216, v26, s6 + ; implicit-def: $vgpr216 +; %bb.2464: ; %Flow1223 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2465: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v216, vcc +; %bb.2466: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i364.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2467: + v_bfe_u32 v27, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v215, v27, s6 + ; implicit-def: $vgpr215 +; %bb.2468: ; %Flow1222 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2469: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v215, vcc +; %bb.2470: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i367.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2471: + v_bfe_u32 v28, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v214, v28, s6 + ; implicit-def: $vgpr214 +; %bb.2472: ; %Flow1221 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2473: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v214, vcc +; %bb.2474: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i370.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2475: + v_bfe_u32 v29, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v213, v29, s6 + ; implicit-def: $vgpr213 +; %bb.2476: ; %Flow1220 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2477: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v213, vcc +; %bb.2478: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i373.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2479: + v_bfe_u32 v30, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v212, v30, s6 + ; implicit-def: $vgpr212 +; %bb.2480: ; %Flow1219 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2481: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v212, vcc +; %bb.2482: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i376.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2483: + v_bfe_u32 v31, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v211, v31, s6 + ; implicit-def: $vgpr211 +; %bb.2484: ; %Flow1218 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2485: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v211, vcc +; %bb.2486: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i379.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2487: + v_bfe_u32 v32, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v210, v32, s6 + ; implicit-def: $vgpr210 +; %bb.2488: ; %Flow1217 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2489: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v210, vcc +; %bb.2490: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i382.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2491: + v_bfe_u32 v33, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v209, v33, s6 + ; implicit-def: $vgpr209 +; %bb.2492: ; %Flow1216 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2493: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v209, vcc +; %bb.2494: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i385.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2495: + v_bfe_u32 v34, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v208, v34, s6 + ; implicit-def: $vgpr208 +; %bb.2496: ; %Flow1215 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2497: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v208, vcc +; %bb.2498: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i388.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2499: + v_bfe_u32 v35, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v207, v35, s6 + ; implicit-def: $vgpr207 +; %bb.2500: ; %Flow1214 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2501: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v207, vcc +; %bb.2502: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i391.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2503: + v_bfe_u32 v36, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v206, v36, s6 + ; implicit-def: $vgpr206 +; %bb.2504: ; %Flow1213 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2505: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v206, vcc +; %bb.2506: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i394.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2507: + v_bfe_u32 v37, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v204, v37, s6 + ; implicit-def: $vgpr204 +; %bb.2508: ; %Flow1212 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2509: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v204, vcc +; %bb.2510: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i397.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2511: + v_bfe_u32 v38, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v205, v38, s6 + ; implicit-def: $vgpr205 +; %bb.2512: ; %Flow1211 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2513: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v205, vcc +; %bb.2514: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i400.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2515: + v_bfe_u32 v39, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v203, v39, s6 + ; implicit-def: $vgpr203 +; %bb.2516: ; %Flow1210 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2517: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v203, vcc +; %bb.2518: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i403.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2519: + v_bfe_u32 v40, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v202, v40, s6 + ; implicit-def: $vgpr202 +; %bb.2520: ; %Flow1209 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2521: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v202, vcc +; %bb.2522: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i406.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2523: + v_bfe_u32 v41, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v201, v41, s6 + ; implicit-def: $vgpr201 +; %bb.2524: ; %Flow1208 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2525: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v201, vcc +; %bb.2526: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i409.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2527: + v_bfe_u32 v42, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v200, v42, s6 + ; implicit-def: $vgpr200 +; %bb.2528: ; %Flow1207 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2529: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v200, vcc +; %bb.2530: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i412.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2531: + v_bfe_u32 v43, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v199, v43, s6 + ; implicit-def: $vgpr199 +; %bb.2532: ; %Flow1206 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2533: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v199, vcc +; %bb.2534: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i415.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2535: + v_bfe_u32 v44, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v198, v44, s6 + ; implicit-def: $vgpr198 +; %bb.2536: ; %Flow1205 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2537: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v198, vcc +; %bb.2538: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i418.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2539: + v_bfe_u32 v45, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v197, v45, s6 + ; implicit-def: $vgpr197 +; %bb.2540: ; %Flow1204 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2541: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v197, vcc +; %bb.2542: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i421.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2543: + v_bfe_u32 v46, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v196, v46, s6 + ; implicit-def: $vgpr196 +; %bb.2544: ; %Flow1203 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2545: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v196, vcc +; %bb.2546: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i424.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2547: + v_bfe_u32 v47, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v195, v47, s6 + ; implicit-def: $vgpr195 +; %bb.2548: ; %Flow1202 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2549: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v195, vcc +; %bb.2550: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i427.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2551: + v_bfe_u32 v48, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v194, v48, s6 + ; implicit-def: $vgpr194 +; %bb.2552: ; %Flow1201 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2553: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v194, vcc +; %bb.2554: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i430.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2555: + v_bfe_u32 v49, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v193, v49, s6 + ; implicit-def: $vgpr193 +; %bb.2556: ; %Flow1200 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2557: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v193, vcc +; %bb.2558: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i433.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2559: + v_bfe_u32 v50, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v192, v50, s6 + ; implicit-def: $vgpr192 +; %bb.2560: ; %Flow1199 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2561: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v192, vcc +; %bb.2562: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i436.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2563: + v_bfe_u32 v51, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v191, v51, s6 + ; implicit-def: $vgpr191 +; %bb.2564: ; %Flow1198 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2565: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v191, vcc +; %bb.2566: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i439.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2567: + v_bfe_u32 v52, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v190, v52, s6 + ; implicit-def: $vgpr190 +; %bb.2568: ; %Flow1197 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2569: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v190, vcc +; %bb.2570: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i442.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2571: + v_bfe_u32 v53, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v189, v53, s6 + ; implicit-def: $vgpr189 +; %bb.2572: ; %Flow1196 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2573: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v189, vcc +; %bb.2574: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_574 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v22 + ds_write_b16_d16_hi v1, v23 offset:128 + ds_write_b16_d16_hi v1, v24 offset:256 + ds_write_b16_d16_hi v1, v25 offset:384 + ds_write_b16_d16_hi v1, v26 offset:1024 + ds_write_b16_d16_hi v1, v27 offset:1152 + ds_write_b16_d16_hi v1, v28 offset:1280 + ds_write_b16_d16_hi v1, v29 offset:1408 + ds_write_b16_d16_hi v1, v30 offset:2048 + ds_write_b16_d16_hi v1, v31 offset:2176 + ds_write_b16_d16_hi v1, v32 offset:2304 + ds_write_b16_d16_hi v1, v33 offset:2432 + ds_write_b16_d16_hi v1, v34 offset:3072 + ds_write_b16_d16_hi v1, v35 offset:3200 + ds_write_b16_d16_hi v1, v36 offset:3328 + ds_write_b16_d16_hi v1, v37 offset:3456 + ds_write_b16_d16_hi v1, v38 offset:8192 + ds_write_b16_d16_hi v1, v39 offset:8320 + ds_write_b16_d16_hi v1, v40 offset:8448 + ds_write_b16_d16_hi v1, v41 offset:8576 + ds_write_b16_d16_hi v1, v42 offset:9216 + ds_write_b16_d16_hi v1, v43 offset:9344 + ds_write_b16_d16_hi v1, v44 offset:9472 + ds_write_b16_d16_hi v1, v45 offset:9600 + ds_write_b16_d16_hi v1, v46 offset:10240 + ds_write_b16_d16_hi v1, v47 offset:10368 + ds_write_b16_d16_hi v1, v48 offset:10496 + ds_write_b16_d16_hi v1, v49 offset:10624 + ds_write_b16_d16_hi v1, v50 offset:11264 + ds_write_b16_d16_hi v1, v51 offset:11392 + ds_write_b16_d16_hi v1, v52 offset:11520 + ds_write_b16_d16_hi v1, v53 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v19 + v_lshl_or_b32 v23, v22, 7, v21 + ds_read_b128 v[26:29], v23 + ds_read_b128 v[30:33], v23 offset:128 + ds_read_b128 v[34:37], v23 offset:256 + ds_read_b128 v[38:41], v23 offset:384 + v_add_u32_e32 v23, s18, v22 + v_or_b32_e32 v22, 0x80, v18 + v_mad_u64_u32 v[24:25], s[4:5], v23, s16, v[22:23] + v_lshlrev_b32_e32 v23, 1, v24 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[26:27], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v24 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[30:31], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[32:33], v24, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[34:35], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[36:37], v24, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[38:39], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[40:41], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2575: + v_bfe_u32 v23, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v188, v23, s6 + ; implicit-def: $vgpr188 +; %bb.2576: ; %Flow1195 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2577: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v188, vcc +; %bb.2578: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i639.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2579: + v_bfe_u32 v24, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v187, v24, s6 + ; implicit-def: $vgpr187 +; %bb.2580: ; %Flow1194 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2581: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v187, vcc +; %bb.2582: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i642.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2583: + v_bfe_u32 v25, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v186, v25, s6 + ; implicit-def: $vgpr186 +; %bb.2584: ; %Flow1193 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2585: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v186, vcc +; %bb.2586: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i645.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2587: + v_bfe_u32 v26, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v185, v26, s6 + ; implicit-def: $vgpr185 +; %bb.2588: ; %Flow1192 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2589: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v185, vcc +; %bb.2590: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i648.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2591: + v_bfe_u32 v27, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v184, v27, s6 + ; implicit-def: $vgpr184 +; %bb.2592: ; %Flow1191 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2593: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v184, vcc +; %bb.2594: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i651.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2595: + v_bfe_u32 v28, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v183, v28, s6 + ; implicit-def: $vgpr183 +; %bb.2596: ; %Flow1190 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2597: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v183, vcc +; %bb.2598: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i654.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2599: + v_bfe_u32 v29, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v182, v29, s6 + ; implicit-def: $vgpr182 +; %bb.2600: ; %Flow1189 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2601: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v182, vcc +; %bb.2602: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i657.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2603: + v_bfe_u32 v30, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v181, v30, s6 + ; implicit-def: $vgpr181 +; %bb.2604: ; %Flow1188 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2605: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v181, vcc +; %bb.2606: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i660.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2607: + v_bfe_u32 v31, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v180, v31, s6 + ; implicit-def: $vgpr180 +; %bb.2608: ; %Flow1187 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2609: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v180, vcc +; %bb.2610: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i663.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2611: + v_bfe_u32 v32, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v179, v32, s6 + ; implicit-def: $vgpr179 +; %bb.2612: ; %Flow1186 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2613: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v179, vcc +; %bb.2614: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i666.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2615: + v_bfe_u32 v33, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v178, v33, s6 + ; implicit-def: $vgpr178 +; %bb.2616: ; %Flow1185 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2617: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v178, vcc +; %bb.2618: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i669.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2619: + v_bfe_u32 v34, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v177, v34, s6 + ; implicit-def: $vgpr177 +; %bb.2620: ; %Flow1184 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2621: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v177, vcc +; %bb.2622: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i672.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2623: + v_bfe_u32 v35, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v176, v35, s6 + ; implicit-def: $vgpr176 +; %bb.2624: ; %Flow1183 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2625: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v176, vcc +; %bb.2626: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i675.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2627: + v_bfe_u32 v36, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v175, v36, s6 + ; implicit-def: $vgpr175 +; %bb.2628: ; %Flow1182 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2629: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v175, vcc +; %bb.2630: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i678.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2631: + v_bfe_u32 v37, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v174, v37, s6 + ; implicit-def: $vgpr174 +; %bb.2632: ; %Flow1181 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2633: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v174, vcc +; %bb.2634: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i681.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2635: + v_bfe_u32 v38, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v172, v38, s6 + ; implicit-def: $vgpr172 +; %bb.2636: ; %Flow1180 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2637: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v172, vcc +; %bb.2638: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i684.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2639: + v_bfe_u32 v39, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v173, v39, s6 + ; implicit-def: $vgpr173 +; %bb.2640: ; %Flow1179 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2641: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v173, vcc +; %bb.2642: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i687.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2643: + v_bfe_u32 v40, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v171, v40, s6 + ; implicit-def: $vgpr171 +; %bb.2644: ; %Flow1178 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2645: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v171, vcc +; %bb.2646: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i690.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2647: + v_bfe_u32 v41, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v170, v41, s6 + ; implicit-def: $vgpr170 +; %bb.2648: ; %Flow1177 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2649: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v170, vcc +; %bb.2650: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i693.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2651: + v_bfe_u32 v42, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v169, v42, s6 + ; implicit-def: $vgpr169 +; %bb.2652: ; %Flow1176 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2653: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v169, vcc +; %bb.2654: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i696.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2655: + v_bfe_u32 v43, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v168, v43, s6 + ; implicit-def: $vgpr168 +; %bb.2656: ; %Flow1175 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2657: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v168, vcc +; %bb.2658: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i699.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2659: + v_bfe_u32 v44, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v167, v44, s6 + ; implicit-def: $vgpr167 +; %bb.2660: ; %Flow1174 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2661: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v167, vcc +; %bb.2662: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i702.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2663: + v_bfe_u32 v45, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v166, v45, s6 + ; implicit-def: $vgpr166 +; %bb.2664: ; %Flow1173 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2665: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v166, vcc +; %bb.2666: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i705.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2667: + v_bfe_u32 v46, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v165, v46, s6 + ; implicit-def: $vgpr165 +; %bb.2668: ; %Flow1172 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2669: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v165, vcc +; %bb.2670: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i708.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2671: + v_bfe_u32 v47, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v164, v47, s6 + ; implicit-def: $vgpr164 +; %bb.2672: ; %Flow1171 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2673: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v164, vcc +; %bb.2674: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i711.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2675: + v_bfe_u32 v48, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v163, v48, s6 + ; implicit-def: $vgpr163 +; %bb.2676: ; %Flow1170 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2677: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v163, vcc +; %bb.2678: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i714.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2679: + v_bfe_u32 v49, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v162, v49, s6 + ; implicit-def: $vgpr162 +; %bb.2680: ; %Flow1169 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2681: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v162, vcc +; %bb.2682: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i717.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2683: + v_bfe_u32 v50, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v161, v50, s6 + ; implicit-def: $vgpr161 +; %bb.2684: ; %Flow1168 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2685: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v161, vcc +; %bb.2686: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i720.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2687: + v_bfe_u32 v51, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v160, v51, s6 + ; implicit-def: $vgpr160 +; %bb.2688: ; %Flow1167 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2689: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v160, vcc +; %bb.2690: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i723.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2691: + v_bfe_u32 v52, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v159, v52, s6 + ; implicit-def: $vgpr159 +; %bb.2692: ; %Flow1166 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2693: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v159, vcc +; %bb.2694: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i726.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2695: + v_bfe_u32 v53, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v158, v53, s6 + ; implicit-def: $vgpr158 +; %bb.2696: ; %Flow1165 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2697: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v158, vcc +; %bb.2698: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i729.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v54, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s4, v54 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2699: + v_bfe_u32 v54, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v157, v54, s6 + ; implicit-def: $vgpr157 +; %bb.2700: ; %Flow1164 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2701: + v_mov_b32_e32 v54, 0 + v_or_b32_e32 v55, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v54 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v55, v157, vcc +; %bb.2702: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_861 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v23 + ds_write_b16_d16_hi v1, v24 offset:128 + ds_write_b16_d16_hi v1, v25 offset:256 + ds_write_b16_d16_hi v1, v26 offset:384 + ds_write_b16_d16_hi v1, v27 offset:1024 + ds_write_b16_d16_hi v1, v28 offset:1152 + ds_write_b16_d16_hi v1, v29 offset:1280 + ds_write_b16_d16_hi v1, v30 offset:1408 + ds_write_b16_d16_hi v1, v31 offset:2048 + ds_write_b16_d16_hi v1, v32 offset:2176 + ds_write_b16_d16_hi v1, v33 offset:2304 + ds_write_b16_d16_hi v1, v34 offset:2432 + ds_write_b16_d16_hi v1, v35 offset:3072 + ds_write_b16_d16_hi v1, v36 offset:3200 + ds_write_b16_d16_hi v1, v37 offset:3328 + ds_write_b16_d16_hi v1, v38 offset:3456 + ds_write_b16_d16_hi v1, v39 offset:8192 + ds_write_b16_d16_hi v1, v40 offset:8320 + ds_write_b16_d16_hi v1, v41 offset:8448 + ds_write_b16_d16_hi v1, v42 offset:8576 + ds_write_b16_d16_hi v1, v43 offset:9216 + ds_write_b16_d16_hi v1, v44 offset:9344 + ds_write_b16_d16_hi v1, v45 offset:9472 + ds_write_b16_d16_hi v1, v46 offset:9600 + ds_write_b16_d16_hi v1, v47 offset:10240 + ds_write_b16_d16_hi v1, v48 offset:10368 + ds_write_b16_d16_hi v1, v49 offset:10496 + ds_write_b16_d16_hi v1, v50 offset:10624 + ds_write_b16_d16_hi v1, v51 offset:11264 + ds_write_b16_d16_hi v1, v52 offset:11392 + ds_write_b16_d16_hi v1, v53 offset:11520 + ds_write_b16_d16_hi v1, v54 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v23, s4, v19 + v_lshl_or_b32 v24, v23, 7, v21 + ds_read_b128 v[28:31], v24 + ds_read_b128 v[32:35], v24 offset:128 + ds_read_b128 v[36:39], v24 offset:256 + ds_read_b128 v[40:43], v24 offset:384 + v_add_u32_e32 v23, s18, v23 + v_or_b32_e32 v24, 0xc0, v18 + v_mad_u64_u32 v[26:27], s[4:5], v23, s16, v[24:25] + v_lshlrev_b32_e32 v23, 1, v26 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v26 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[32:33], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v25, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[36:37], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v25, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[40:41], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[42:43], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2703: + v_bfe_u32 v23, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v156, v23, s6 + ; implicit-def: $vgpr156 +; %bb.2704: ; %Flow1163 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2705: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v25, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v25, v156, vcc +; %bb.2706: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i926.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2707: + v_bfe_u32 v25, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v155, v25, s6 + ; implicit-def: $vgpr155 +; %bb.2708: ; %Flow1162 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2709: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v155, vcc +; %bb.2710: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i929.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2711: + v_bfe_u32 v26, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v154, v26, s6 + ; implicit-def: $vgpr154 +; %bb.2712: ; %Flow1161 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2713: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v154, vcc +; %bb.2714: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i932.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2715: + v_bfe_u32 v27, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v153, v27, s6 + ; implicit-def: $vgpr153 +; %bb.2716: ; %Flow1160 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2717: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v153, vcc +; %bb.2718: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i935.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2719: + v_bfe_u32 v28, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v152, v28, s6 + ; implicit-def: $vgpr152 +; %bb.2720: ; %Flow1159 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2721: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v152, vcc +; %bb.2722: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i938.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2723: + v_bfe_u32 v29, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v151, v29, s6 + ; implicit-def: $vgpr151 +; %bb.2724: ; %Flow1158 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2725: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v151, vcc +; %bb.2726: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i941.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2727: + v_bfe_u32 v30, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v150, v30, s6 + ; implicit-def: $vgpr150 +; %bb.2728: ; %Flow1157 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2729: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v150, vcc +; %bb.2730: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i944.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2731: + v_bfe_u32 v31, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v149, v31, s6 + ; implicit-def: $vgpr149 +; %bb.2732: ; %Flow1156 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2733: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v149, vcc +; %bb.2734: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i947.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2735: + v_bfe_u32 v32, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v148, v32, s6 + ; implicit-def: $vgpr148 +; %bb.2736: ; %Flow1155 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2737: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v148, vcc +; %bb.2738: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i950.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2739: + v_bfe_u32 v33, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v147, v33, s6 + ; implicit-def: $vgpr147 +; %bb.2740: ; %Flow1154 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2741: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v147, vcc +; %bb.2742: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i953.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2743: + v_bfe_u32 v34, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v146, v34, s6 + ; implicit-def: $vgpr146 +; %bb.2744: ; %Flow1153 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2745: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v146, vcc +; %bb.2746: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i956.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2747: + v_bfe_u32 v35, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v145, v35, s6 + ; implicit-def: $vgpr145 +; %bb.2748: ; %Flow1152 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2749: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v145, vcc +; %bb.2750: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i959.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2751: + v_bfe_u32 v36, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v144, v36, s6 + ; implicit-def: $vgpr144 +; %bb.2752: ; %Flow1151 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2753: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v144, vcc +; %bb.2754: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i962.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2755: + v_bfe_u32 v37, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v143, v37, s6 + ; implicit-def: $vgpr143 +; %bb.2756: ; %Flow1150 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2757: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v143, vcc +; %bb.2758: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i965.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2759: + v_bfe_u32 v38, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v142, v38, s6 + ; implicit-def: $vgpr142 +; %bb.2760: ; %Flow1149 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2761: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v142, vcc +; %bb.2762: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i968.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2763: + v_bfe_u32 v39, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v141, v39, s6 + ; implicit-def: $vgpr141 +; %bb.2764: ; %Flow1148 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2765: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v141, vcc +; %bb.2766: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i971.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2767: + v_bfe_u32 v40, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v2, v40, s6 +; %bb.2768: ; %Flow1147 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2769: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v2, vcc +; %bb.2770: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i974.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2771: + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v3, v2, s6 +; %bb.2772: ; %Flow1146 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2773: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v41, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v3, vcc +; %bb.2774: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i977.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2775: + v_bfe_u32 v2, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v4, v2, s6 +; %bb.2776: ; %Flow1145 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2777: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v3, v4, vcc +; %bb.2778: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i980.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2779: + v_bfe_u32 v2, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v5, v2, s6 +; %bb.2780: ; %Flow1144 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2781: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v3, v5, vcc +; %bb.2782: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i983.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2783: + v_bfe_u32 v2, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v6, v2, s6 +; %bb.2784: ; %Flow1143 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2785: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v3, v6, vcc +; %bb.2786: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i986.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2787: + v_bfe_u32 v2, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v7, v2, s6 +; %bb.2788: ; %Flow1142 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2789: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v3, v7, vcc +; %bb.2790: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i989.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2791: + v_bfe_u32 v2, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v8, v2, s6 +; %bb.2792: ; %Flow1141 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2793: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v3, v8, vcc +; %bb.2794: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i992.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2795: + v_bfe_u32 v2, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v9, v2, s6 +; %bb.2796: ; %Flow1140 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2797: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v3, v9, vcc +; %bb.2798: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i995.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2799: + v_bfe_u32 v2, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v10, v2, s6 +; %bb.2800: ; %Flow1139 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2801: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v3, v10, vcc +; %bb.2802: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i998.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2803: + v_bfe_u32 v2, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v11, v2, s6 +; %bb.2804: ; %Flow1138 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2805: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v3, v11, vcc +; %bb.2806: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1001.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2807: + v_bfe_u32 v2, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v12, v2, s6 +; %bb.2808: ; %Flow1137 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2809: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v3, v12, vcc +; %bb.2810: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1004.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2811: + v_bfe_u32 v2, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v13, v2, s6 +; %bb.2812: ; %Flow1136 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2813: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v3, v13, vcc +; %bb.2814: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1007.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2815: + v_bfe_u32 v2, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v14, v2, s6 +; %bb.2816: ; %Flow1135 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2817: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v3, v14, vcc +; %bb.2818: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1010.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2819: + v_bfe_u32 v2, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v15, v2, s6 +; %bb.2820: ; %Flow1134 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2821: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v3, v15, vcc +; %bb.2822: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1013.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2823: + v_bfe_u32 v2, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v16, v2, s6 +; %bb.2824: ; %Flow1133 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2825: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v3, v16, vcc +; %bb.2826: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1016.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr55 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2827: + v_bfe_u32 v2, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v55, v17, v2, s6 + ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 +; %bb.2828: ; %Flow1132 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2829: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v55, v3, v17, vcc +; %bb.2830: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1148 + s_or_b64 exec, exec, s[4:5] + s_bitset1_b32 s18, 7 + ds_write_b16_d16_hi v1, v23 + ds_write_b16_d16_hi v1, v25 offset:128 + ds_write_b16_d16_hi v1, v26 offset:256 + ds_write_b16_d16_hi v1, v27 offset:384 + ds_write_b16_d16_hi v1, v28 offset:1024 + ds_write_b16_d16_hi v1, v29 offset:1152 + ds_write_b16_d16_hi v1, v30 offset:1280 + ds_write_b16_d16_hi v1, v31 offset:1408 + ds_write_b16_d16_hi v1, v32 offset:2048 + ds_write_b16_d16_hi v1, v33 offset:2176 + ds_write_b16_d16_hi v1, v34 offset:2304 + ds_write_b16_d16_hi v1, v35 offset:2432 + ds_write_b16_d16_hi v1, v36 offset:3072 + ds_write_b16_d16_hi v1, v37 offset:3200 + ds_write_b16_d16_hi v1, v38 offset:3328 + ds_write_b16_d16_hi v1, v39 offset:3456 + ds_write_b16_d16_hi v1, v40 offset:8192 + ds_write_b16_d16_hi v1, v41 offset:8320 + ds_write_b16_d16_hi v1, v42 offset:8448 + ds_write_b16_d16_hi v1, v43 offset:8576 + ds_write_b16_d16_hi v1, v44 offset:9216 + ds_write_b16_d16_hi v1, v45 offset:9344 + ds_write_b16_d16_hi v1, v46 offset:9472 + ds_write_b16_d16_hi v1, v47 offset:9600 + ds_write_b16_d16_hi v1, v48 offset:10240 + ds_write_b16_d16_hi v1, v49 offset:10368 + ds_write_b16_d16_hi v1, v50 offset:10496 + ds_write_b16_d16_hi v1, v51 offset:10624 + ds_write_b16_d16_hi v1, v52 offset:11264 + ds_write_b16_d16_hi v1, v53 offset:11392 + ds_write_b16_d16_hi v1, v54 offset:11520 + ds_write_b16_d16_hi v1, v55 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v19 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[26:29], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[24:25] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[26:27], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2831: + v_bfe_u32 v2, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v140, v2, s6 + ; implicit-def: $vgpr140 +; %bb.2832: ; %Flow1131 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2833: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v140, vcc +; %bb.2834: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1213.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2835: + v_bfe_u32 v3, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v139, v3, s6 + ; implicit-def: $vgpr139 +; %bb.2836: ; %Flow1130 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2837: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v139, vcc +; %bb.2838: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1216.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2839: + v_bfe_u32 v4, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v138, v4, s6 + ; implicit-def: $vgpr138 +; %bb.2840: ; %Flow1129 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2841: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v138, vcc +; %bb.2842: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1219.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2843: + v_bfe_u32 v5, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v137, v5, s6 + ; implicit-def: $vgpr137 +; %bb.2844: ; %Flow1128 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2845: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v137, vcc +; %bb.2846: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1222.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2847: + v_bfe_u32 v6, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v136, v6, s6 + ; implicit-def: $vgpr136 +; %bb.2848: ; %Flow1127 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2849: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v136, vcc +; %bb.2850: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1225.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2851: + v_bfe_u32 v7, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v135, v7, s6 + ; implicit-def: $vgpr135 +; %bb.2852: ; %Flow1126 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2853: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v135, vcc +; %bb.2854: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1228.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2855: + v_bfe_u32 v8, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v134, v8, s6 + ; implicit-def: $vgpr134 +; %bb.2856: ; %Flow1125 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2857: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v134, vcc +; %bb.2858: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1231.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2859: + v_bfe_u32 v9, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v133, v9, s6 + ; implicit-def: $vgpr133 +; %bb.2860: ; %Flow1124 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2861: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v133, vcc +; %bb.2862: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1234.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2863: + v_bfe_u32 v10, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v132, v10, s6 + ; implicit-def: $vgpr132 +; %bb.2864: ; %Flow1123 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2865: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v132, vcc +; %bb.2866: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1237.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2867: + v_bfe_u32 v11, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v131, v11, s6 + ; implicit-def: $vgpr131 +; %bb.2868: ; %Flow1122 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2869: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v131, vcc +; %bb.2870: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1240.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2871: + v_bfe_u32 v12, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v130, v12, s6 + ; implicit-def: $vgpr130 +; %bb.2872: ; %Flow1121 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2873: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v130, vcc +; %bb.2874: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1243.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2875: + v_bfe_u32 v13, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v129, v13, s6 + ; implicit-def: $vgpr129 +; %bb.2876: ; %Flow1120 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2877: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v129, vcc +; %bb.2878: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1246.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2879: + v_bfe_u32 v14, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v128, v14, s6 + ; implicit-def: $vgpr128 +; %bb.2880: ; %Flow1119 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2881: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v128, vcc +; %bb.2882: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1249.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2883: + v_bfe_u32 v15, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v127, v15, s6 + ; implicit-def: $vgpr127 +; %bb.2884: ; %Flow1118 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2885: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v127, vcc +; %bb.2886: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1252.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2887: + v_bfe_u32 v16, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v126, v16, s6 + ; implicit-def: $vgpr126 +; %bb.2888: ; %Flow1117 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2889: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v126, vcc +; %bb.2890: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1255.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2891: + v_bfe_u32 v17, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v124, v17, s6 + ; implicit-def: $vgpr124 +; %bb.2892: ; %Flow1116 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2893: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v23, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v23, v124, vcc +; %bb.2894: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1258.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2895: + v_bfe_u32 v23, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v125, v23, s6 + ; implicit-def: $vgpr125 +; %bb.2896: ; %Flow1115 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2897: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v125, vcc +; %bb.2898: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1261.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2899: + v_bfe_u32 v24, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v123, v24, s6 + ; implicit-def: $vgpr123 +; %bb.2900: ; %Flow1114 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2901: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v123, vcc +; %bb.2902: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1264.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2903: + v_bfe_u32 v25, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v122, v25, s6 + ; implicit-def: $vgpr122 +; %bb.2904: ; %Flow1113 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2905: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v122, vcc +; %bb.2906: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1267.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2907: + v_bfe_u32 v26, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v121, v26, s6 + ; implicit-def: $vgpr121 +; %bb.2908: ; %Flow1112 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2909: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v121, vcc +; %bb.2910: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1270.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2911: + v_bfe_u32 v27, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v120, v27, s6 + ; implicit-def: $vgpr120 +; %bb.2912: ; %Flow1111 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2913: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v120, vcc +; %bb.2914: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1273.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2915: + v_bfe_u32 v28, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v119, v28, s6 + ; implicit-def: $vgpr119 +; %bb.2916: ; %Flow1110 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2917: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v119, vcc +; %bb.2918: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1276.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2919: + v_bfe_u32 v29, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v118, v29, s6 + ; implicit-def: $vgpr118 +; %bb.2920: ; %Flow1109 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2921: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v118, vcc +; %bb.2922: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1279.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2923: + v_bfe_u32 v30, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v117, v30, s6 + ; implicit-def: $vgpr117 +; %bb.2924: ; %Flow1108 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2925: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v117, vcc +; %bb.2926: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1282.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2927: + v_bfe_u32 v31, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v116, v31, s6 + ; implicit-def: $vgpr116 +; %bb.2928: ; %Flow1107 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2929: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v116, vcc +; %bb.2930: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1285.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2931: + v_bfe_u32 v32, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v115, v32, s6 + ; implicit-def: $vgpr115 +; %bb.2932: ; %Flow1106 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2933: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v115, vcc +; %bb.2934: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1288.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2935: + v_bfe_u32 v33, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v114, v33, s6 + ; implicit-def: $vgpr114 +; %bb.2936: ; %Flow1105 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2937: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v114, vcc +; %bb.2938: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1291.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2939: + v_bfe_u32 v34, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v113, v34, s6 + ; implicit-def: $vgpr113 +; %bb.2940: ; %Flow1104 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2941: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v113, vcc +; %bb.2942: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1294.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2943: + v_bfe_u32 v35, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v112, v35, s6 + ; implicit-def: $vgpr112 +; %bb.2944: ; %Flow1103 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2945: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v112, vcc +; %bb.2946: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1297.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2947: + v_bfe_u32 v36, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v111, v36, s6 + ; implicit-def: $vgpr111 +; %bb.2948: ; %Flow1102 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2949: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v111, vcc +; %bb.2950: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1300.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2951: + v_bfe_u32 v37, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v110, v37, s6 + ; implicit-def: $vgpr110 +; %bb.2952: ; %Flow1101 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2953: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v110, vcc +; %bb.2954: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1303.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2955: + v_bfe_u32 v38, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v109, v38, s6 + ; implicit-def: $vgpr109 +; %bb.2956: ; %Flow1100 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2957: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v109, vcc +; %bb.2958: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1435 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v2 + ds_write_b16_d16_hi v1, v3 offset:128 + ds_write_b16_d16_hi v1, v4 offset:256 + ds_write_b16_d16_hi v1, v5 offset:384 + ds_write_b16_d16_hi v1, v6 offset:1024 + ds_write_b16_d16_hi v1, v7 offset:1152 + ds_write_b16_d16_hi v1, v8 offset:1280 + ds_write_b16_d16_hi v1, v9 offset:1408 + ds_write_b16_d16_hi v1, v10 offset:2048 + ds_write_b16_d16_hi v1, v11 offset:2176 + ds_write_b16_d16_hi v1, v12 offset:2304 + ds_write_b16_d16_hi v1, v13 offset:2432 + ds_write_b16_d16_hi v1, v14 offset:3072 + ds_write_b16_d16_hi v1, v15 offset:3200 + ds_write_b16_d16_hi v1, v16 offset:3328 + ds_write_b16_d16_hi v1, v17 offset:3456 + ds_write_b16_d16_hi v1, v23 offset:8192 + ds_write_b16_d16_hi v1, v24 offset:8320 + ds_write_b16_d16_hi v1, v25 offset:8448 + ds_write_b16_d16_hi v1, v26 offset:8576 + ds_write_b16_d16_hi v1, v27 offset:9216 + ds_write_b16_d16_hi v1, v28 offset:9344 + ds_write_b16_d16_hi v1, v29 offset:9472 + ds_write_b16_d16_hi v1, v30 offset:9600 + ds_write_b16_d16_hi v1, v31 offset:10240 + ds_write_b16_d16_hi v1, v32 offset:10368 + ds_write_b16_d16_hi v1, v33 offset:10496 + ds_write_b16_d16_hi v1, v34 offset:10624 + ds_write_b16_d16_hi v1, v35 offset:11264 + ds_write_b16_d16_hi v1, v36 offset:11392 + ds_write_b16_d16_hi v1, v37 offset:11520 + ds_write_b16_d16_hi v1, v38 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v19 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[24:27], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[22:23] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[24:25], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2959: + v_bfe_u32 v2, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v108, v2, s6 + ; implicit-def: $vgpr108 +; %bb.2960: ; %Flow1099 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2961: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v108, vcc +; %bb.2962: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1500.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2963: + v_bfe_u32 v3, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v107, v3, s6 + ; implicit-def: $vgpr107 +; %bb.2964: ; %Flow1098 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2965: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v107, vcc +; %bb.2966: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1503.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2967: + v_bfe_u32 v4, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v106, v4, s6 + ; implicit-def: $vgpr106 +; %bb.2968: ; %Flow1097 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2969: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v106, vcc +; %bb.2970: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1506.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2971: + v_bfe_u32 v5, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v105, v5, s6 + ; implicit-def: $vgpr105 +; %bb.2972: ; %Flow1096 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2973: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v105, vcc +; %bb.2974: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1509.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2975: + v_bfe_u32 v6, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v104, v6, s6 + ; implicit-def: $vgpr104 +; %bb.2976: ; %Flow1095 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2977: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v104, vcc +; %bb.2978: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1512.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2979: + v_bfe_u32 v7, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v103, v7, s6 + ; implicit-def: $vgpr103 +; %bb.2980: ; %Flow1094 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2981: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v103, vcc +; %bb.2982: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1515.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2983: + v_bfe_u32 v8, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v102, v8, s6 + ; implicit-def: $vgpr102 +; %bb.2984: ; %Flow1093 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2985: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v102, vcc +; %bb.2986: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1518.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2987: + v_bfe_u32 v9, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v101, v9, s6 + ; implicit-def: $vgpr101 +; %bb.2988: ; %Flow1092 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2989: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v101, vcc +; %bb.2990: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1521.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2991: + v_bfe_u32 v10, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v100, v10, s6 + ; implicit-def: $vgpr100 +; %bb.2992: ; %Flow1091 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2993: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v100, vcc +; %bb.2994: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1524.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2995: + v_bfe_u32 v11, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v99, v11, s6 + ; implicit-def: $vgpr99 +; %bb.2996: ; %Flow1090 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2997: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v99, vcc +; %bb.2998: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1527.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2999: + v_bfe_u32 v12, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v98, v12, s6 + ; implicit-def: $vgpr98 +; %bb.3000: ; %Flow1089 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3001: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v98, vcc +; %bb.3002: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1530.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3003: + v_bfe_u32 v13, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v97, v13, s6 + ; implicit-def: $vgpr97 +; %bb.3004: ; %Flow1088 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3005: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v97, vcc +; %bb.3006: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1533.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3007: + v_bfe_u32 v14, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v96, v14, s6 + ; implicit-def: $vgpr96 +; %bb.3008: ; %Flow1087 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3009: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v96, vcc +; %bb.3010: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1536.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3011: + v_bfe_u32 v15, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v95, v15, s6 + ; implicit-def: $vgpr95 +; %bb.3012: ; %Flow1086 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3013: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v95, vcc +; %bb.3014: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1539.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3015: + v_bfe_u32 v16, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v94, v16, s6 + ; implicit-def: $vgpr94 +; %bb.3016: ; %Flow1085 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3017: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v94, vcc +; %bb.3018: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1542.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3019: + v_bfe_u32 v17, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v92, v17, s6 + ; implicit-def: $vgpr92 +; %bb.3020: ; %Flow1084 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3021: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v22, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v22, v92, vcc +; %bb.3022: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1545.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3023: + v_bfe_u32 v22, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v93, v22, s6 + ; implicit-def: $vgpr93 +; %bb.3024: ; %Flow1083 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3025: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v93, vcc +; %bb.3026: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1548.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3027: + v_bfe_u32 v23, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v91, v23, s6 + ; implicit-def: $vgpr91 +; %bb.3028: ; %Flow1082 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3029: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v91, vcc +; %bb.3030: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1551.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3031: + v_bfe_u32 v24, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v90, v24, s6 + ; implicit-def: $vgpr90 +; %bb.3032: ; %Flow1081 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3033: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v90, vcc +; %bb.3034: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1554.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3035: + v_bfe_u32 v25, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v89, v25, s6 + ; implicit-def: $vgpr89 +; %bb.3036: ; %Flow1080 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3037: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v89, vcc +; %bb.3038: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1557.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3039: + v_bfe_u32 v26, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v88, v26, s6 + ; implicit-def: $vgpr88 +; %bb.3040: ; %Flow1079 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3041: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v88, vcc +; %bb.3042: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1560.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a41 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3043: + v_accvgpr_read_b32 v28, a41 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr41 +; %bb.3044: ; %Flow1078 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3045: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a41 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3046: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1563.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a40 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3047: + v_accvgpr_read_b32 v29, a40 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr40 +; %bb.3048: ; %Flow1077 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3049: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a40 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3050: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1566.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a23 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3051: + v_accvgpr_read_b32 v30, a23 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr23 +; %bb.3052: ; %Flow1076 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3053: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a23 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3054: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1569.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a22 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3055: + v_accvgpr_read_b32 v31, a22 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr22 +; %bb.3056: ; %Flow1075 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3057: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a22 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3058: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1572.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a21 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3059: + v_accvgpr_read_b32 v32, a21 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr21 +; %bb.3060: ; %Flow1074 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3061: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a21 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3062: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1575.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a20 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3063: + v_accvgpr_read_b32 v33, a20 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr20 +; %bb.3064: ; %Flow1073 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3065: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a20 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3066: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1578.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a19 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3067: + v_accvgpr_read_b32 v34, a19 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr19 +; %bb.3068: ; %Flow1072 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3069: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a19 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3070: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1581.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a18 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3071: + v_accvgpr_read_b32 v35, a18 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr18 +; %bb.3072: ; %Flow1071 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3073: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a18 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3074: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1584.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a17 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3075: + v_accvgpr_read_b32 v36, a17 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr17 +; %bb.3076: ; %Flow1070 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3077: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a17 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3078: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1587.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3079: + v_bfe_u32 v36, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v87, v36, s6 + ; implicit-def: $vgpr87 +; %bb.3080: ; %Flow1069 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3081: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v87, vcc +; %bb.3082: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1590.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v37, a16 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3083: + v_accvgpr_read_b32 v38, a16 + v_bfe_u32 v37, v38, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v38, v37, s6 + ; implicit-def: $agpr16 +; %bb.3084: ; %Flow1068 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3085: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v39, a16 + v_or_b32_e32 v38, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v39, vcc +; %bb.3086: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1722 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v2 + ds_write_b16_d16_hi v1, v3 offset:128 + ds_write_b16_d16_hi v1, v4 offset:256 + ds_write_b16_d16_hi v1, v5 offset:384 + ds_write_b16_d16_hi v1, v6 offset:1024 + ds_write_b16_d16_hi v1, v7 offset:1152 + ds_write_b16_d16_hi v1, v8 offset:1280 + ds_write_b16_d16_hi v1, v9 offset:1408 + ds_write_b16_d16_hi v1, v10 offset:2048 + ds_write_b16_d16_hi v1, v11 offset:2176 + ds_write_b16_d16_hi v1, v12 offset:2304 + ds_write_b16_d16_hi v1, v13 offset:2432 + ds_write_b16_d16_hi v1, v14 offset:3072 + ds_write_b16_d16_hi v1, v15 offset:3200 + ds_write_b16_d16_hi v1, v16 offset:3328 + ds_write_b16_d16_hi v1, v17 offset:3456 + ds_write_b16_d16_hi v1, v22 offset:8192 + ds_write_b16_d16_hi v1, v23 offset:8320 + ds_write_b16_d16_hi v1, v24 offset:8448 + ds_write_b16_d16_hi v1, v25 offset:8576 + ds_write_b16_d16_hi v1, v26 offset:9216 + ds_write_b16_d16_hi v1, v27 offset:9344 + ds_write_b16_d16_hi v1, v28 offset:9472 + ds_write_b16_d16_hi v1, v29 offset:9600 + ds_write_b16_d16_hi v1, v30 offset:10240 + ds_write_b16_d16_hi v1, v31 offset:10368 + ds_write_b16_d16_hi v1, v32 offset:10496 + ds_write_b16_d16_hi v1, v33 offset:10624 + ds_write_b16_d16_hi v1, v34 offset:11264 + ds_write_b16_d16_hi v1, v35 offset:11392 + ds_write_b16_d16_hi v1, v36 offset:11520 + ds_write_b16_d16_hi v1, v37 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v19 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[22:25], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[20:21] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[22:23], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[24:25], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v2, a119 + v_and_b32_e32 v2, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3087: + v_accvgpr_read_b32 v3, a119 + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v3, v2, s6 + ; implicit-def: $agpr119 +; %bb.3088: ; %Flow1067 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3089: + v_mov_b32_e32 v2, 0 + v_accvgpr_read_b32 v4, a119 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v4, vcc +; %bb.3090: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1787.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v3, a118 + v_and_b32_e32 v3, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3091: + v_accvgpr_read_b32 v4, a118 + v_bfe_u32 v3, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v4, v3, s6 + ; implicit-def: $agpr118 +; %bb.3092: ; %Flow1066 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3093: + v_mov_b32_e32 v3, 0 + v_accvgpr_read_b32 v5, a118 + v_or_b32_e32 v4, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v5, vcc +; %bb.3094: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1790.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v4, a117 + v_and_b32_e32 v4, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3095: + v_accvgpr_read_b32 v5, a117 + v_bfe_u32 v4, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v5, v4, s6 + ; implicit-def: $agpr117 +; %bb.3096: ; %Flow1065 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3097: + v_mov_b32_e32 v4, 0 + v_accvgpr_read_b32 v6, a117 + v_or_b32_e32 v5, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v6, vcc +; %bb.3098: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1793.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v5, a116 + v_and_b32_e32 v5, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3099: + v_accvgpr_read_b32 v6, a116 + v_bfe_u32 v5, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v6, v5, s6 + ; implicit-def: $agpr116 +; %bb.3100: ; %Flow1064 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3101: + v_mov_b32_e32 v5, 0 + v_accvgpr_read_b32 v7, a116 + v_or_b32_e32 v6, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v7, vcc +; %bb.3102: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1796.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v6, a115 + v_and_b32_e32 v6, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3103: + v_accvgpr_read_b32 v7, a115 + v_bfe_u32 v6, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v7, v6, s6 + ; implicit-def: $agpr115 +; %bb.3104: ; %Flow1063 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3105: + v_mov_b32_e32 v6, 0 + v_accvgpr_read_b32 v8, a115 + v_or_b32_e32 v7, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v8, vcc +; %bb.3106: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1799.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v7, a114 + v_and_b32_e32 v7, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3107: + v_accvgpr_read_b32 v8, a114 + v_bfe_u32 v7, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v8, v7, s6 + ; implicit-def: $agpr114 +; %bb.3108: ; %Flow1062 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3109: + v_mov_b32_e32 v7, 0 + v_accvgpr_read_b32 v9, a114 + v_or_b32_e32 v8, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v9, vcc +; %bb.3110: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1802.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v8, a113 + v_and_b32_e32 v8, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3111: + v_accvgpr_read_b32 v9, a113 + v_bfe_u32 v8, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v9, v8, s6 + ; implicit-def: $agpr113 +; %bb.3112: ; %Flow1061 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3113: + v_mov_b32_e32 v8, 0 + v_accvgpr_read_b32 v10, a113 + v_or_b32_e32 v9, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v10, vcc +; %bb.3114: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1805.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v9, a112 + v_and_b32_e32 v9, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3115: + v_accvgpr_read_b32 v10, a112 + v_bfe_u32 v9, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v10, v9, s6 + ; implicit-def: $agpr112 +; %bb.3116: ; %Flow1060 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3117: + v_mov_b32_e32 v9, 0 + v_accvgpr_read_b32 v11, a112 + v_or_b32_e32 v10, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v11, vcc +; %bb.3118: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1808.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v10, a103 + v_and_b32_e32 v10, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3119: + v_accvgpr_read_b32 v11, a103 + v_bfe_u32 v10, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v11, v10, s6 + ; implicit-def: $agpr103 +; %bb.3120: ; %Flow1059 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3121: + v_mov_b32_e32 v10, 0 + v_accvgpr_read_b32 v12, a103 + v_or_b32_e32 v11, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v12, vcc +; %bb.3122: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1811.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v11, a102 + v_and_b32_e32 v11, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3123: + v_accvgpr_read_b32 v12, a102 + v_bfe_u32 v11, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v12, v11, s6 + ; implicit-def: $agpr102 +; %bb.3124: ; %Flow1058 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3125: + v_mov_b32_e32 v11, 0 + v_accvgpr_read_b32 v13, a102 + v_or_b32_e32 v12, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v13, vcc +; %bb.3126: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1814.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v12, a101 + v_and_b32_e32 v12, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3127: + v_accvgpr_read_b32 v13, a101 + v_bfe_u32 v12, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v13, v12, s6 + ; implicit-def: $agpr101 +; %bb.3128: ; %Flow1057 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3129: + v_mov_b32_e32 v12, 0 + v_accvgpr_read_b32 v14, a101 + v_or_b32_e32 v13, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v14, vcc +; %bb.3130: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1817.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v13, a100 + v_and_b32_e32 v13, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3131: + v_accvgpr_read_b32 v14, a100 + v_bfe_u32 v13, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v14, v13, s6 + ; implicit-def: $agpr100 +; %bb.3132: ; %Flow1056 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3133: + v_mov_b32_e32 v13, 0 + v_accvgpr_read_b32 v15, a100 + v_or_b32_e32 v14, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v15, vcc +; %bb.3134: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1820.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v14, a99 + v_and_b32_e32 v14, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3135: + v_accvgpr_read_b32 v15, a99 + v_bfe_u32 v14, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v15, v14, s6 + ; implicit-def: $agpr99 +; %bb.3136: ; %Flow1055 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3137: + v_mov_b32_e32 v14, 0 + v_accvgpr_read_b32 v16, a99 + v_or_b32_e32 v15, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v16, vcc +; %bb.3138: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1823.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v15, a98 + v_and_b32_e32 v15, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3139: + v_accvgpr_read_b32 v16, a98 + v_bfe_u32 v15, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v16, v15, s6 + ; implicit-def: $agpr98 +; %bb.3140: ; %Flow1054 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3141: + v_mov_b32_e32 v15, 0 + v_accvgpr_read_b32 v17, a98 + v_or_b32_e32 v16, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v17, vcc +; %bb.3142: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1826.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v16, a97 + v_and_b32_e32 v16, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3143: + v_accvgpr_read_b32 v17, a97 + v_bfe_u32 v16, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v17, v16, s6 + ; implicit-def: $agpr97 +; %bb.3144: ; %Flow1053 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3145: + v_mov_b32_e32 v16, 0 + v_accvgpr_read_b32 v20, a97 + v_or_b32_e32 v17, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v20, vcc +; %bb.3146: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1829.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v17, a96 + v_and_b32_e32 v17, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3147: + v_accvgpr_read_b32 v20, a96 + v_bfe_u32 v17, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v20, v17, s6 + ; implicit-def: $agpr96 +; %bb.3148: ; %Flow1052 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3149: + v_mov_b32_e32 v17, 0 + v_accvgpr_read_b32 v22, a96 + v_or_b32_e32 v20, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v20, v22, vcc +; %bb.3150: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1832.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v20, a54 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s4, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3151: + v_accvgpr_read_b32 v22, a54 + v_bfe_u32 v20, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v22, v20, s6 + ; implicit-def: $agpr54 +; %bb.3152: ; %Flow1051 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3153: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v23, a54 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v22, v23, vcc +; %bb.3154: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1835.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v22, a53 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3155: + v_accvgpr_read_b32 v23, a53 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 + ; implicit-def: $agpr53 +; %bb.3156: ; %Flow1050 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3157: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a53 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.3158: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1838.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v23, a52 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3159: + v_accvgpr_read_b32 v24, a52 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 + ; implicit-def: $agpr52 +; %bb.3160: ; %Flow1049 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3161: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a52 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.3162: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1841.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v24, a51 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3163: + v_accvgpr_read_b32 v25, a51 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 + ; implicit-def: $agpr51 +; %bb.3164: ; %Flow1048 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3165: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a51 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.3166: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1844.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v25, a50 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3167: + v_accvgpr_read_b32 v26, a50 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 + ; implicit-def: $agpr50 +; %bb.3168: ; %Flow1047 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3169: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a50 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.3170: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1847.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v26, a49 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3171: + v_accvgpr_read_b32 v27, a49 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 + ; implicit-def: $agpr49 +; %bb.3172: ; %Flow1046 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3173: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a49 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.3174: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1850.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a48 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3175: + v_accvgpr_read_b32 v28, a48 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr48 +; %bb.3176: ; %Flow1045 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3177: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a48 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3178: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1853.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a39 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3179: + v_accvgpr_read_b32 v29, a39 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr39 +; %bb.3180: ; %Flow1044 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3181: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a39 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3182: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1856.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a38 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3183: + v_accvgpr_read_b32 v30, a38 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr38 +; %bb.3184: ; %Flow1043 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3185: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a38 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3186: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1859.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a37 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3187: + v_accvgpr_read_b32 v31, a37 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr37 +; %bb.3188: ; %Flow1042 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3189: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a37 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3190: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1862.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a36 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3191: + v_accvgpr_read_b32 v32, a36 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr36 +; %bb.3192: ; %Flow1041 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3193: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a36 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1865.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a35 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3195: + v_accvgpr_read_b32 v33, a35 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr35 +; %bb.3196: ; %Flow1040 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3197: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a35 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1868.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a34 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3199: + v_accvgpr_read_b32 v34, a34 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr34 +; %bb.3200: ; %Flow1039 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3201: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a34 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1871.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a33 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3203: + v_accvgpr_read_b32 v35, a33 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr33 +; %bb.3204: ; %Flow1038 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3205: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a33 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1874.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a32 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3207: + v_accvgpr_read_b32 v36, a32 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr32 +; %bb.3208: ; %Flow1037 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3209: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a32 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1877.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3211: + v_bfe_u32 v36, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v86, v36, s6 + ; implicit-def: $vgpr86 +; %bb.3212: ; %Flow1036 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3213: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v86, vcc +; %bb.3214: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP_ + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v1, v2 + ds_write_b16_d16_hi v1, v3 offset:128 + ds_write_b16_d16_hi v1, v4 offset:256 + ds_write_b16_d16_hi v1, v5 offset:384 + ds_write_b16_d16_hi v1, v6 offset:1024 + ds_write_b16_d16_hi v1, v7 offset:1152 + ds_write_b16_d16_hi v1, v8 offset:1280 + ds_write_b16_d16_hi v1, v9 offset:1408 + ds_write_b16_d16_hi v1, v10 offset:2048 + ds_write_b16_d16_hi v1, v11 offset:2176 + ds_write_b16_d16_hi v1, v12 offset:2304 + ds_write_b16_d16_hi v1, v13 offset:2432 + ds_write_b16_d16_hi v1, v14 offset:3072 + ds_write_b16_d16_hi v1, v15 offset:3200 + ds_write_b16_d16_hi v1, v16 offset:3328 + ds_write_b16_d16_hi v1, v17 offset:3456 + ds_write_b16_d16_hi v1, v20 offset:8192 + ds_write_b16_d16_hi v1, v22 offset:8320 + ds_write_b16_d16_hi v1, v23 offset:8448 + ds_write_b16_d16_hi v1, v24 offset:8576 + ds_write_b16_d16_hi v1, v25 offset:9216 + ds_write_b16_d16_hi v1, v26 offset:9344 + ds_write_b16_d16_hi v1, v27 offset:9472 + ds_write_b16_d16_hi v1, v28 offset:9600 + ds_write_b16_d16_hi v1, v29 offset:10240 + ds_write_b16_d16_hi v1, v30 offset:10368 + ds_write_b16_d16_hi v1, v31 offset:10496 + ds_write_b16_d16_hi v1, v32 offset:10624 + ds_write_b16_d16_hi v1, v33 offset:11264 + ds_write_b16_d16_hi v1, v34 offset:11392 + ds_write_b16_d16_hi v1, v35 offset:11520 + ds_write_b16_d16_hi v1, v36 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v0, s4, v19 + v_lshl_or_b32 v1, v0, 7, v21 + ds_read_b128 v[2:5], v1 + ds_read_b128 v[6:9], v1 offset:128 + ds_read_b128 v[10:13], v1 offset:256 + ds_read_b128 v[14:17], v1 offset:384 + v_add_u32_e32 v0, s18, v0 + v_mad_u64_u32 v[0:1], s[4:5], v0, s16, v[18:19] + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[2:3], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[4:5], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[6:7], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[8:9], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[10:11], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[12:13], v1, s[0:3], 8 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[14:15], v0, s[0:3], 0 offen + buffer_store_dwordx2 v[16:17], v0, s[0:3], 8 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end13: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end13-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 27 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16bNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 97136 +; TotalNumSgprs: 33 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB14_9 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB14_4 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v4, s8 + v_mov_b32_e32 v5, s9 + v_mov_b32_e32 v2, s10 + v_mov_b32_e32 v3, s11 + v_mul_lo_u32 v8, v6, s7 + v_mul_lo_u32 v10, v0, s2 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshl_add_u64 v[2:3], v[10:11], 1, v[2:3] + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[4:5], v[8:9], 1, v[4:5] + v_mov_b32_e32 v1, 0 +.LBB14_3: ; =>This Inner Loop Header: Depth=1 + global_load_ushort v7, v[4:5], off + global_load_ushort v8, v[2:3], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_lshl_add_u64 v[4:5], v[4:5], 0, 2 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(1) + v_lshlrev_b32_e32 v7, 16, v7 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v8, 16, v8 + v_fmac_f32_e32 v1, v8, v7 + s_cbranch_scc0 .LBB14_3 +.LBB14_4: ; %._crit_edge + s_mov_b32 s0, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s0, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[0:1], vcc + s_xor_b64 s[0:1], exec, s[0:1] + s_cbranch_execz .LBB14_6 +; %bb.5: + v_bfe_u32 v2, v1, 16, 1 + s_waitcnt lgkmcnt(0) + s_movk_i32 s2, 0x7fff + v_add3_u32 v2, v1, v2, s2 + ; implicit-def: $vgpr1 +.LBB14_6: ; %Flow + s_andn2_saveexec_b64 s[0:1], s[0:1] +; %bb.7: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v1, vcc +; %bb.8: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit + s_or_b64 exec, exec, s[0:1] + s_waitcnt lgkmcnt(0) + v_mad_u64_u32 v[0:1], s[0:1], v6, s3, v[0:1] + v_mov_b32_e32 v4, s12 + v_mov_b32_e32 v5, s13 + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[4:5] + global_store_short_d16_hi v[0:1], v2, off +.LBB14_9: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 12 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end14: + .size _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end14-_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 12 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 544 +; TotalNumSgprs: 20 +; NumVgprs: 12 +; NumAgprs: 0 +; TotalNumVgprs: 12 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 12 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v1, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v1 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s13, s2, 4 + s_add_i32 s21, s13, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s13, s2 + s_sub_i32 s12, s3, s14 + s_max_i32 s12, s12, 0 + s_mul_i32 s12, s21, s12 + s_add_i32 s2, s12, s2 + s_mul_i32 s12, s2, s20 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s13, s13, s21 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s13 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_ashr_i32 s13, s12, 31 + s_lshl_b64 s[2:3], s[12:13], 1 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s2, s4, -1 + s_mul_i32 s2, s7, s2 + s_add_i32 s3, s6, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s22, s2, 1 + s_mul_i32 s2, s20, s3 + s_add_i32 s5, s5, -1 + s_add_u32 s2, s5, s2 + s_add_u32 s21, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s23, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v1 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v1, -1, v1 + v_and_b32_e32 v72, 0x78, v1 + v_and_b32_e32 v73, 31, v1 + v_lshrrev_b32_e32 v2, 5, v1 + v_and_b32_e32 v67, 7, v1 + v_lshrrev_b32_e32 v3, 2, v1 + s_cbranch_scc0 .LBB15_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + v_lshlrev_b32_e32 v18, 3, v67 + s_and_b32 s10, s15, 0xffffffc0 + v_add_u32_e32 v66, s10, v72 + v_add_u32_e32 v4, s18, v66 + v_mad_u64_u32 v[4:5], s[10:11], v4, s7, v[18:19] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v5, 1, v4 + s_nop 1 + buffer_load_dwordx4 v[6:9], v5, s[8:11], 0 offen + v_add_u32_e32 v14, s7, v4 + v_lshlrev_b32_e32 v4, 1, v14 + buffer_load_dwordx4 v[10:13], v4, s[8:11], 0 offen + v_xor_b32_e32 v4, v2, v67 + v_lshlrev_b32_e32 v74, 3, v2 + v_lshl_or_b32 v20, v73, 3, s19 + v_lshlrev_b32_e32 v5, 12, v2 + s_lshl_b32 s14, s21, 1 + s_lshr_b32 s24, s15, 2 + s_lshr_b32 s25, s15, 1 + v_lshl_or_b32 v75, v67, 8, v5 + s_mov_b32 s15, s11 + s_and_b32 s26, s24, 0x1ffffe0 + s_and_b32 s24, s24, 0x3ffffff0 + v_and_or_b32 v5, s25, 32, v73 + v_or_b32_e32 v76, s26, v73 + v_add_u32_e32 v19, s24, v74 + v_lshrrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v21, s7, v14 + v_lshlrev_b32_e32 v14, 1, v21 + buffer_load_dwordx4 v[14:17], v14, s[8:11], 0 offen + v_lshl_or_b32 v77, v66, 6, v18 + v_or_b32_e32 v78, 1, v66 + v_ashrrev_i32_e32 v22, 31, v66 + v_or_b32_e32 v79, 2, v66 + v_mad_u64_u32 v[18:19], s[26:27], v19, s20, v[20:21] + v_xor_b32_e32 v80, v5, v67 + v_lshlrev_b32_e32 v81, 1, v77 + v_lshrrev_b32_e32 v82, 29, v22 + v_lshlrev_b32_e32 v26, 1, v18 + v_add_u32_e32 v18, s20, v18 + v_lshlrev_b32_e32 v27, 1, v18 + v_add_u32_e32 v30, s20, v18 + v_add_u32_e32 v31, s7, v21 + buffer_load_dwordx4 v[18:21], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[22:25], v27, s[12:15], 0 offen + v_lshlrev_b32_e32 v26, 1, v31 + buffer_load_dwordx4 v[26:29], v26, s[8:11], 0 offen + v_lshlrev_b32_e32 v38, 1, v30 + v_add_u32_e32 v30, s20, v30 + v_add_u32_e32 v31, s7, v31 + v_lshlrev_b32_e32 v39, 1, v30 + v_add_u32_e32 v54, s20, v30 + v_lshlrev_b32_e32 v40, 1, v31 + v_add_u32_e32 v42, s7, v31 + buffer_load_dwordx4 v[30:33], v38, s[12:15], 0 offen + buffer_load_dwordx4 v[34:37], v39, s[12:15], 0 offen + v_lshlrev_b32_e32 v62, 1, v54 + buffer_load_dwordx4 v[38:41], v40, s[8:11], 0 offen + v_lshlrev_b32_e32 v43, 1, v42 + v_add_u32_e32 v46, s7, v42 + buffer_load_dwordx4 v[42:45], v43, s[8:11], 0 offen + v_lshlrev_b32_e32 v55, 1, v46 + v_add_lshl_u32 v56, v46, s7, 1 + buffer_load_dwordx4 v[46:49], v55, s[8:11], 0 offen + buffer_load_dwordx4 v[50:53], v56, s[8:11], 0 offen + v_add_u32_e32 v54, s20, v54 + v_lshlrev_b32_e32 v63, 1, v54 + v_add_u32_e32 v64, s20, v54 + buffer_load_dwordx4 v[54:57], v62, s[12:15], 0 offen + buffer_load_dwordx4 v[58:61], v63, s[12:15], 0 offen + v_lshlrev_b32_e32 v83, 1, v64 + v_add_lshl_u32 v84, v64, s20, 1 + buffer_load_dwordx4 v[62:65], v83, s[12:15], 0 offen + buffer_load_dwordx4 v[68:71], v84, s[12:15], 0 offen + v_lshl_or_b32 v75, v80, 3, v75 + v_add_u32_e32 v83, v78, v82 + v_add_u32_e32 v84, v79, v82 + v_and_b32_e32 v83, -8, v83 + v_and_b32_e32 v84, -8, v84 + v_sub_u32_e32 v78, v78, v83 + v_xor_b32_e32 v78, v78, v67 + v_sub_u32_e32 v83, v78, v67 + v_lshlrev_b32_e32 v85, 3, v83 + s_waitcnt vmcnt(15) + ds_write_b128 v81, v[6:9] + v_sub_u32_e32 v6, v79, v84 + v_xor_b32_e32 v6, v6, v67 + v_sub_u32_e32 v7, v6, v78 + v_lshlrev_b32_e32 v8, 3, v7 + v_add3_u32 v8, v85, v77, v8 + v_lshl_add_u32 v9, v83, 4, v81 + s_waitcnt vmcnt(14) + ds_write_b128 v9, v[10:13] offset:128 + v_or_b32_e32 v10, 3, v66 + v_add_u32_e32 v11, v10, v82 + v_and_b32_e32 v11, -8, v11 + v_sub_u32_e32 v10, v10, v11 + v_xor_b32_e32 v10, v10, v67 + v_sub_u32_e32 v6, v10, v6 + v_lshlrev_b32_e32 v11, 3, v6 + v_or_b32_e32 v12, 4, v66 + v_add_u32_e32 v13, v12, v82 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v67 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v13, 3, v10 + v_add3_u32 v8, v8, v11, v13 + v_lshlrev_b32_e32 v7, 4, v7 + v_add3_u32 v7, v9, s23, v7 + s_waitcnt vmcnt(13) + ds_write_b128 v7, v[14:17] offset:128 + v_or_b32_e32 v9, 5, v66 + v_add_u32_e32 v11, v9, v82 + v_and_b32_e32 v11, -8, v11 + v_sub_u32_e32 v9, v9, v11 + v_xor_b32_e32 v9, v9, v67 + v_sub_u32_e32 v11, v9, v12 + v_lshlrev_b32_e32 v12, 3, v11 + v_or_b32_e32 v13, 6, v66 + v_add_u32_e32 v14, v13, v82 + v_and_b32_e32 v14, -8, v14 + v_sub_u32_e32 v13, v13, v14 + v_xor_b32_e32 v13, v13, v67 + v_sub_u32_e32 v9, v13, v9 + v_lshlrev_b32_e32 v14, 3, v9 + v_add3_u32 v8, v8, v12, v14 + v_lshlrev_b32_e32 v6, 4, v6 + v_add3_u32 v6, v7, s23, v6 + s_waitcnt vmcnt(10) + ds_write_b128 v6, v[26:29] offset:128 + v_or_b32_e32 v7, 7, v66 + v_add_u32_e32 v12, v7, v82 + v_and_b32_e32 v12, 0xffffff8, v12 + v_sub_u32_e32 v7, v7, v12 + v_xor_b32_e32 v7, v7, v67 + v_sub_u32_e32 v7, v7, v13 + v_lshlrev_b32_e32 v7, 4, v7 + v_lshl_add_u32 v7, v8, 1, v7 + v_lshlrev_b32_e32 v8, 4, v10 + v_add3_u32 v6, v6, s23, v8 + s_waitcnt vmcnt(7) + ds_write_b128 v6, v[38:41] offset:128 + v_lshlrev_b32_e32 v8, 4, v11 + v_add3_u32 v6, v6, s23, v8 + s_waitcnt vmcnt(6) + ds_write_b128 v6, v[42:45] offset:128 + v_lshlrev_b32_e32 v8, 4, v9 + v_add3_u32 v6, v6, s23, v8 + s_waitcnt vmcnt(5) + ds_write_b128 v6, v[46:49] offset:128 + s_waitcnt vmcnt(4) + ds_write_b128 v7, v[50:53] offset:896 + s_mov_b32 s10, 0x1000504 + v_perm_b32 v6, v18, v22, s10 + s_mov_b32 s11, 0x3020706 + v_perm_b32 v10, v18, v22, s11 + v_perm_b32 v7, v30, v34, s10 + v_perm_b32 v11, v30, v34, s11 + s_waitcnt vmcnt(2) + v_perm_b32 v8, v54, v58, s10 + v_perm_b32 v12, v54, v58, s11 + s_waitcnt vmcnt(0) + v_perm_b32 v9, v62, v68, s10 + v_perm_b32 v13, v62, v68, s11 + v_perm_b32 v14, v19, v23, s10 + v_perm_b32 v26, v19, v23, s11 + v_perm_b32 v15, v31, v35, s10 + v_perm_b32 v27, v31, v35, s11 + v_perm_b32 v16, v55, v59, s10 + v_perm_b32 v28, v55, v59, s11 + v_perm_b32 v17, v63, v69, s10 + v_perm_b32 v29, v63, v69, s11 + v_perm_b32 v38, v20, v24, s10 + v_perm_b32 v42, v20, v24, s11 + v_perm_b32 v39, v32, v36, s10 + v_perm_b32 v43, v32, v36, s11 + v_perm_b32 v40, v56, v60, s10 + v_perm_b32 v44, v56, v60, s11 + v_perm_b32 v41, v64, v70, s10 + v_perm_b32 v45, v64, v70, s11 + v_perm_b32 v18, v21, v25, s10 + v_perm_b32 v22, v21, v25, s11 + v_perm_b32 v19, v33, v37, s10 + v_perm_b32 v23, v33, v37, s11 + v_perm_b32 v20, v57, v61, s10 + v_perm_b32 v24, v57, v61, s11 + v_perm_b32 v21, v65, v71, s10 + v_perm_b32 v25, v65, v71, s11 + v_and_b32_e32 v30, 24, v3 + v_add_u32_e32 v30, s24, v30 + v_lshrrev_b32_e32 v31, 2, v30 + v_and_b32_e32 v31, 24, v31 + v_xor_b32_e32 v32, v31, v73 + v_lshlrev_b32_e32 v33, 9, v30 + v_and_b32_e32 v33, 0x3000, v33 + v_lshlrev_b32_e32 v30, 6, v30 + v_and_b32_e32 v30, 0xfffff800, v30 + v_add_u32_e32 v30, v30, v33 + v_lshl_or_b32 v30, v32, 3, v30 + v_lshlrev_b32_e32 v33, 1, v30 + ds_write_b128 v33, v[6:9] offset:32768 + v_or_b32_e32 v6, 1, v31 + v_xor_b32_e32 v6, v6, v73 + v_sub_u32_e32 v7, v6, v32 + v_lshl_add_u32 v8, v7, 3, v30 + v_lshl_add_u32 v7, v7, 4, v33 + ds_write_b128 v7, v[10:13] offset:33280 + v_or_b32_e32 v7, 2, v31 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v6, v7, v6 + v_lshlrev_b32_e32 v6, 3, v6 + s_movk_i32 s10, 0x100 + v_add3_u32 v6, v8, v6, s10 + v_lshlrev_b32_e32 v8, 1, v6 + ds_write_b128 v8, v[14:17] offset:33280 + v_or_b32_e32 v8, 3, v31 + v_xor_b32_e32 v8, v8, v73 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v6, v6, v7, s10 + v_lshlrev_b32_e32 v7, 1, v6 + ds_write_b128 v7, v[26:29] offset:33280 + v_or_b32_e32 v7, 4, v31 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v8, v7, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v6, v6, v8, s10 + v_lshlrev_b32_e32 v8, 1, v6 + ds_write_b128 v8, v[38:41] offset:33280 + v_or_b32_e32 v8, 5, v31 + v_xor_b32_e32 v8, v8, v73 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_add3_u32 v6, v6, v7, s10 + v_lshlrev_b32_e32 v7, 1, v6 + ds_write_b128 v7, v[42:45] offset:33280 + v_or_b32_e32 v7, 6, v31 + v_xor_b32_e32 v7, v7, v73 + v_sub_u32_e32 v8, v7, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_lshl_u32 v6, v6, v8, 1 + v_or_b32_e32 v8, 7, v31 + v_xor_b32_e32 v8, v8, v73 + v_sub_u32_e32 v7, v8, v7 + v_lshl_add_u32 v7, v7, 4, v6 + ds_write_b128 v6, v[18:21] offset:33792 + ds_write_b128 v7, v[22:25] offset:34304 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v6, 7, v76 + v_lshl_or_b32 v7, v4, 4, v6 + v_add_u32_e32 v8, 2, v2 + v_xor_b32_e32 v8, v8, v67 + v_lshl_or_b32 v9, v8, 4, v6 + ds_read_b128 v[36:39], v7 + ds_read_b128 v[40:43], v9 + v_lshlrev_b32_e32 v7, 1, v75 + v_add_u32_e32 v9, 16, v74 + v_lshrrev_b32_e32 v10, 5, v9 + v_bfe_u32 v9, v9, 3, 2 + v_lshl_or_b32 v11, v10, 3, v67 + v_and_b32_e32 v12, 31, v11 + v_xor_b32_e32 v13, v5, v12 + v_sub_u32_e32 v14, v13, v80 + v_lshlrev_b32_e32 v15, 11, v10 + v_lshlrev_b32_e32 v14, 3, v14 + v_sub_u32_e32 v16, v9, v2 + v_lshl_or_b32 v15, v16, 12, v15 + v_add3_u32 v14, v75, v15, v14 + v_lshlrev_b32_e32 v16, 1, v14 + ds_read_b128 v[44:47], v7 offset:32768 + ds_read_b128 v[48:51], v16 offset:32768 + v_xor_b32_e32 v7, 1, v10 + v_sub_u32_e32 v9, v2, v9 + v_lshl_add_u32 v10, v7, 3, v11 + v_and_b32_e32 v11, 31, v10 + v_xor_b32_e32 v17, v5, v11 + v_sub_u32_e32 v13, v17, v13 + v_lshlrev_b32_e32 v7, 11, v7 + v_lshl_add_u32 v7, v9, 12, v7 + v_lshl_add_u32 v9, v13, 3, v7 + v_lshl_add_u32 v13, v9, 1, v16 + v_add_u32_e32 v16, 48, v74 + v_lshrrev_b32_e32 v18, 5, v16 + v_add_u32_e32 v19, -1, v18 + v_bfe_u32 v16, v16, 3, 2 + v_sub_u32_e32 v20, v16, v2 + v_lshl_add_u32 v10, v19, 3, v10 + v_ashrrev_i32_e32 v21, 31, v10 + v_lshrrev_b32_e32 v21, 27, v21 + v_add_u32_e32 v21, v10, v21 + v_and_b32_e32 v21, 0xffffffe0, v21 + v_sub_u32_e32 v21, v10, v21 + v_xor_b32_e32 v22, v5, v21 + v_sub_u32_e32 v17, v22, v17 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshl_add_u32 v19, v20, 12, v19 + v_lshl_add_u32 v17, v17, 3, v19 + v_lshl_add_u32 v20, v17, 1, v13 + v_or_b32_e32 v23, 8, v5 + v_sub_u32_e32 v16, v2, v16 + v_lshlrev_b32_e32 v24, 3, v18 + v_sub_u32_e32 v10, v10, v24 + v_ashrrev_i32_e32 v24, 31, v10 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v10, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v10, v10, v24 + v_xor_b32_e32 v24, v23, v10 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v16, 12, v16 + v_lshlrev_b32_e32 v18, 11, v18 + v_sub_u32_e32 v16, v16, v18 + v_lshl_add_u32 v18, v22, 3, v16 + v_lshl_add_u32 v22, v18, 1, v20 + v_xor_b32_e32 v25, v23, v12 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[36:37], v[44:45], 0 + v_sub_u32_e32 v24, v25, v24 + v_lshl_add_u32 v24, v24, 3, v15 + v_lshl_add_u32 v26, v24, 1, v22 + ds_read_b128 v[52:55], v22 offset:32768 + ds_read_b128 v[56:59], v26 offset:32768 + v_xor_b32_e32 v22, v23, v11 + v_sub_u32_e32 v25, v22, v25 + v_mfma_f32_32x32x8_bf16 a[96:111], v[38:39], v[46:47], a[96:111] + v_lshl_add_u32 v25, v25, 3, v7 + v_lshl_add_u32 v26, v25, 1, v26 + v_xor_b32_e32 v23, v23, v21 + v_sub_u32_e32 v22, v23, v22 + v_lshl_add_u32 v22, v22, 3, v19 + v_lshl_add_u32 v27, v22, 1, v26 + v_or_b32_e32 v28, 16, v5 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[144:159], v[36:37], v[52:53], 0 + v_xor_b32_e32 v29, v28, v10 + v_sub_u32_e32 v23, v29, v23 + v_lshl_add_u32 v23, v23, 3, v16 + v_lshl_add_u32 v30, v23, 1, v27 + v_xor_b32_e32 v31, v28, v12 + v_sub_u32_e32 v29, v31, v29 + v_lshl_add_u32 v29, v29, 3, v15 + v_mfma_f32_32x32x8_bf16 a[144:159], v[38:39], v[54:55], a[144:159] + v_lshl_add_u32 v32, v29, 1, v30 + ds_read_b128 v[60:63], v30 offset:32768 + ds_read_b128 v[68:71], v32 offset:32768 + v_xor_b32_e32 v30, v28, v11 + v_sub_u32_e32 v31, v30, v31 + v_lshl_add_u32 v31, v31, 3, v7 + v_lshl_add_u32 v32, v31, 1, v32 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[36:37], v[60:61], 0 + v_xor_b32_e32 v28, v28, v21 + v_sub_u32_e32 v30, v28, v30 + v_lshl_add_u32 v30, v30, 3, v19 + v_lshl_add_u32 v33, v30, 1, v32 + v_or_b32_e32 v5, 24, v5 + v_xor_b32_e32 v10, v5, v10 + v_sub_u32_e32 v28, v10, v28 + v_mfma_f32_32x32x8_bf16 a[176:191], v[38:39], v[62:63], a[176:191] + v_lshl_add_u32 v16, v28, 3, v16 + v_lshl_add_u32 v28, v16, 1, v33 + ds_read_b128 v[74:77], v28 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[36:37], v[74:75], 0 + v_add_u32_e32 v34, 6, v2 + v_xor_b32_e32 v34, v34, v67 + v_lshl_add_u32 v35, v34, 4, v6 + v_sub_u32_e32 v36, v4, v34 + v_lshl_add_u32 v36, v36, 4, v35 + v_mfma_f32_32x32x8_bf16 a[208:223], v[38:39], v[76:77], a[208:223] + ds_read_b128 v[78:81], v36 offset:8192 + ds_read_b128 v[82:85], v36 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[78:79], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[80:81], v[46:47], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[78:79], v[52:53], 0 + v_mfma_f32_32x32x8_bf16 a[192:207], v[80:81], v[54:55], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[78:79], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[160:175], v[80:81], v[62:63], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[78:79], v[74:75], 0 + v_mfma_f32_32x32x8_bf16 a[128:143], v[80:81], v[76:77], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[82:83], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[112:127], v[84:85], v[46:47], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[82:83], v[52:53], 0 + v_mfma_f32_32x32x8_bf16 a[80:95], v[84:85], v[54:55], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[82:83], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[64:79], v[84:85], v[62:63], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[82:83], v[74:75], 0 + v_mfma_f32_32x32x8_bf16 a[48:63], v[84:85], v[76:77], a[48:63] + ds_read_b128 v[78:81], v36 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[78:79], v[44:45], 0 + v_mfma_f32_32x32x8_bf16 a[32:47], v[80:81], v[46:47], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[78:79], v[52:53], 0 + v_mfma_f32_32x32x8_bf16 a[16:31], v[80:81], v[54:55], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[78:79], v[60:61], 0 + v_mfma_f32_32x32x8_bf16 a[0:15], v[80:81], v[62:63], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[78:79], v[74:75], 0 + v_mfma_f32_32x32x8_bf16 a[240:255], v[80:81], v[76:77], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[40:41], v[48:49], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[42:43], v[50:51], a[96:111] + v_mfma_f32_32x32x8_bf16 a[144:159], v[40:41], v[56:57], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[42:43], v[58:59], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[40:41], v[68:69], a[176:191] + v_xor_b32_e32 v12, v5, v12 + v_sub_u32_e32 v10, v12, v10 + v_mfma_f32_32x32x8_bf16 a[176:191], v[42:43], v[70:71], a[176:191] + v_lshl_add_u32 v10, v10, 3, v15 + v_lshl_add_u32 v15, v10, 1, v28 + ds_read_b128 v[44:47], v15 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[40:41], v[44:45], a[208:223] + v_sub_u32_e32 v8, v8, v4 + v_lshl_add_u32 v8, v8, 4, v36 + v_mfma_f32_32x32x8_bf16 a[208:223], v[42:43], v[46:47], a[208:223] + ds_read_b128 v[38:41], v8 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[38:39], v[48:49], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[40:41], v[50:51], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[38:39], v[56:57], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[40:41], v[58:59], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[38:39], v[68:69], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[40:41], v[70:71], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[38:39], v[44:45], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[40:41], v[46:47], a[128:143] + ds_read_b128 v[38:41], v8 offset:16384 + ds_read_b128 v[52:55], v8 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[38:39], v[48:49], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[40:41], v[50:51], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[38:39], v[56:57], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[40:41], v[58:59], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[38:39], v[68:69], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[40:41], v[70:71], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[38:39], v[44:45], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[40:41], v[46:47], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[52:53], v[48:49], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[54:55], v[50:51], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[52:53], v[56:57], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[54:55], v[58:59], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[52:53], v[68:69], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[54:55], v[70:71], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[52:53], v[44:45], a[240:255] + v_or_b32_e32 v8, 4, v2 + v_xor_b32_e32 v8, v8, v67 + v_lshl_or_b32 v6, v8, 4, v6 + v_mfma_f32_32x32x8_bf16 a[240:255], v[54:55], v[46:47], a[240:255] + ds_read_b128 v[38:41], v6 + ds_read_b128 v[42:45], v13 offset:32768 + ds_read_b128 v[46:49], v35 + ds_read_b128 v[50:53], v20 offset:32768 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x8_bf16 a[96:111], v[38:39], v[42:43], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[40:41], v[44:45], a[96:111] + ds_read_b128 v[54:57], v26 offset:32768 + ds_read_b128 v[58:61], v27 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[144:159], v[38:39], v[54:55], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[40:41], v[56:57], a[144:159] + ds_read_b128 v[62:65], v32 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[38:39], v[62:63], a[176:191] + v_xor_b32_e32 v6, v5, v11 + v_sub_u32_e32 v11, v6, v12 + v_mfma_f32_32x32x8_bf16 a[176:191], v[40:41], v[64:65], a[176:191] + v_lshl_add_u32 v7, v11, 3, v7 + v_lshl_add_u32 v11, v7, 1, v15 + ds_read_b128 v[68:71], v11 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[38:39], v[68:69], a[208:223] + v_sub_u32_e32 v8, v8, v4 + v_lshl_add_u32 v8, v8, 4, v36 + v_mfma_f32_32x32x8_bf16 a[208:223], v[40:41], v[70:71], a[208:223] + ds_read_b128 v[38:41], v8 offset:8192 + ds_read_b128 v[74:77], v8 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[38:39], v[42:43], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[40:41], v[44:45], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[38:39], v[54:55], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[40:41], v[56:57], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[38:39], v[62:63], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[40:41], v[64:65], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[38:39], v[68:69], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[40:41], v[70:71], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[74:75], v[42:43], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[76:77], v[44:45], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[74:75], v[54:55], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[76:77], v[56:57], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[74:75], v[62:63], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[76:77], v[64:65], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[74:75], v[68:69], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[76:77], v[70:71], a[48:63] + ds_read_b128 v[38:41], v8 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[38:39], v[42:43], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[40:41], v[44:45], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[38:39], v[54:55], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[40:41], v[56:57], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[38:39], v[62:63], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[40:41], v[64:65], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[38:39], v[68:69], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[40:41], v[70:71], a[240:255] + v_mfma_f32_32x32x8_bf16 a[96:111], v[46:47], v[50:51], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[48:49], v[52:53], a[96:111] + v_mfma_f32_32x32x8_bf16 a[144:159], v[46:47], v[58:59], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[48:49], v[60:61], a[144:159] + ds_read_b128 v[38:41], v33 offset:32768 + v_add3_u32 v8, v9, v14, v17 + v_add3_u32 v8, v18, v8, v24 + v_add3_u32 v8, v25, v8, v22 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[176:191], v[46:47], v[38:39], a[176:191] + v_add3_u32 v8, v23, v8, v29 + v_add3_u32 v8, v31, v8, v30 + v_add3_u32 v8, v16, v8, v10 + v_xor_b32_e32 v5, v5, v21 + v_sub_u32_e32 v5, v5, v6 + v_lshlrev_b32_e32 v5, 4, v5 + v_lshlrev_b32_e32 v6, 1, v19 + v_mfma_f32_32x32x8_bf16 a[176:191], v[48:49], v[40:41], a[176:191] + v_add_lshl_u32 v7, v7, v8, 1 + v_add3_u32 v5, v5, v6, v7 + ds_read_b128 v[6:9], v5 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[208:223], v[46:47], v[6:7], a[208:223] + v_sub_u32_e32 v4, v34, v4 + v_lshl_add_u32 v4, v4, 4, v36 + v_mfma_f32_32x32x8_bf16 a[208:223], v[48:49], v[8:9], a[208:223] + ds_read_b128 v[10:13], v4 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[10:11], v[50:51], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[12:13], v[52:53], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[10:11], v[58:59], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[12:13], v[60:61], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[10:11], v[38:39], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[12:13], v[40:41], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[10:11], v[6:7], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[12:13], v[8:9], a[128:143] + ds_read_b128 v[10:13], v4 offset:16384 + ds_read_b128 v[14:17], v4 offset:24576 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[10:11], v[50:51], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[12:13], v[52:53], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[10:11], v[58:59], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[12:13], v[60:61], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[10:11], v[38:39], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[12:13], v[40:41], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[10:11], v[6:7], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[12:13], v[8:9], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[14:15], v[50:51], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[16:17], v[52:53], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[14:15], v[58:59], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[16:17], v[60:61], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[14:15], v[38:39], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[16:17], v[40:41], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[14:15], v[6:7], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[16:17], v[8:9], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB15_3 + s_branch .LBB15_10 +.LBB15_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr191 + ; implicit-def: $agpr159 + ; implicit-def: $agpr111 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB15_3: + v_readfirstlane_b32 s15, v0 + v_lshlrev_b32_e32 v66, 3, v67 + s_and_b32 s10, s15, 0xffffffc0 + v_add_u32_e32 v9, s10, v72 + v_add_u32_e32 v4, s18, v9 + v_mad_u64_u32 v[68:69], s[10:11], v4, s7, v[66:67] + s_lshl_b32 s10, s22, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v4, 1, v68 + s_nop 1 + buffer_load_dwordx4 v[10:13], v4, s[8:11], 0 offen + v_xor_b32_e32 v5, v2, v67 + v_add_u32_e32 v7, s7, v68 + v_lshlrev_b32_e32 v4, 1, v7 + buffer_load_dwordx4 v[14:17], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v69, 3, v2 + v_lshl_or_b32 v6, v73, 3, s19 + v_lshlrev_b32_e32 v4, 12, v2 + s_lshl_b32 s14, s21, 1 + s_lshr_b32 s21, s15, 2 + s_lshr_b32 s22, s15, 1 + v_lshl_or_b32 v22, v67, 8, v4 + s_mov_b32 s15, s11 + s_and_b32 s23, s21, 0x3ffffe0 + s_and_b32 s21, s21, 0x3ffffff0 + v_and_or_b32 v4, s22, 32, v73 + v_or_b32_e32 v8, s23, v73 + v_add_u32_e32 v23, s21, v69 + v_lshrrev_b32_e32 v4, 3, v4 + v_lshl_or_b32 v82, v9, 6, v66 + v_or_b32_e32 v83, 1, v9 + v_add_u32_e32 v24, s7, v7 + v_lshlrev_b32_e32 v7, 1, v24 + buffer_load_dwordx4 v[18:21], v7, s[8:11], 0 offen + v_ashrrev_i32_e32 v25, 31, v9 + v_or_b32_e32 v84, 2, v9 + v_lshlrev_b32_e32 v8, 6, v8 + v_mad_u64_u32 v[70:71], s[22:23], v23, s20, v[6:7] + v_xor_b32_e32 v7, v4, v67 + v_lshlrev_b32_e32 v71, 1, v82 + v_lshrrev_b32_e32 v85, 29, v25 + v_lshl_or_b32 v6, v7, 3, v22 + v_lshlrev_b32_e32 v30, 1, v70 + v_add_u32_e32 v22, s20, v70 + v_lshlrev_b32_e32 v31, 1, v22 + v_add_u32_e32 v34, s20, v22 + v_add_u32_e32 v35, s7, v24 + buffer_load_dwordx4 v[22:25], v30, s[12:15], 0 offen + buffer_load_dwordx4 v[26:29], v31, s[12:15], 0 offen + v_lshlrev_b32_e32 v30, 1, v35 + buffer_load_dwordx4 v[30:33], v30, s[8:11], 0 offen + v_lshlrev_b32_e32 v42, 1, v34 + v_add_u32_e32 v34, s20, v34 + v_add_u32_e32 v35, s7, v35 + v_lshlrev_b32_e32 v43, 1, v34 + v_add_u32_e32 v58, s20, v34 + v_lshlrev_b32_e32 v44, 1, v35 + v_add_u32_e32 v46, s7, v35 + buffer_load_dwordx4 v[34:37], v42, s[12:15], 0 offen + buffer_load_dwordx4 v[38:41], v43, s[12:15], 0 offen + v_lshlrev_b32_e32 v74, 1, v58 + buffer_load_dwordx4 v[42:45], v44, s[8:11], 0 offen + v_lshlrev_b32_e32 v47, 1, v46 + v_add_u32_e32 v50, s7, v46 + buffer_load_dwordx4 v[46:49], v47, s[8:11], 0 offen + v_lshlrev_b32_e32 v59, 1, v50 + v_add_lshl_u32 v60, v50, s7, 1 + buffer_load_dwordx4 v[50:53], v59, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v60, s[8:11], 0 offen + v_add_u32_e32 v58, s20, v58 + v_lshlrev_b32_e32 v75, 1, v58 + v_add_u32_e32 v76, s20, v58 + buffer_load_dwordx4 v[58:61], v74, s[12:15], 0 offen + buffer_load_dwordx4 v[62:65], v75, s[12:15], 0 offen + v_lshlrev_b32_e32 v86, 1, v76 + v_add_lshl_u32 v87, v76, s20, 1 + buffer_load_dwordx4 v[74:77], v86, s[12:15], 0 offen + buffer_load_dwordx4 v[78:81], v87, s[12:15], 0 offen + v_add_u32_e32 v86, v83, v85 + v_add_u32_e32 v87, v84, v85 + v_and_b32_e32 v86, -8, v86 + v_sub_u32_e32 v83, v83, v86 + v_xor_b32_e32 v83, v83, v67 + v_sub_u32_e32 v86, v83, v67 + v_lshlrev_b32_e32 v88, 3, v86 + s_waitcnt vmcnt(15) + ds_write_b128 v71, v[10:13] + v_and_b32_e32 v10, -8, v87 + v_sub_u32_e32 v10, v84, v10 + v_xor_b32_e32 v10, v10, v67 + v_sub_u32_e32 v11, v10, v83 + v_lshlrev_b32_e32 v12, 3, v11 + v_add3_u32 v12, v88, v82, v12 + v_lshl_add_u32 v13, v86, 4, v71 + s_waitcnt vmcnt(14) + ds_write_b128 v13, v[14:17] offset:128 + v_or_b32_e32 v14, 3, v9 + v_add_u32_e32 v15, v14, v85 + v_and_b32_e32 v15, -8, v15 + v_sub_u32_e32 v14, v14, v15 + v_xor_b32_e32 v14, v14, v67 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v15, 3, v10 + v_or_b32_e32 v16, 4, v9 + v_add_u32_e32 v17, v16, v85 + v_and_b32_e32 v17, -8, v17 + v_sub_u32_e32 v16, v16, v17 + v_xor_b32_e32 v16, v16, v67 + v_sub_u32_e32 v14, v16, v14 + v_lshlrev_b32_e32 v17, 3, v14 + v_add3_u32 v12, v12, v15, v17 + v_lshlrev_b32_e32 v11, 4, v11 + s_movk_i32 s22, 0x80 + v_add3_u32 v11, v13, s22, v11 + s_waitcnt vmcnt(13) + ds_write_b128 v11, v[18:21] offset:128 + v_or_b32_e32 v13, 5, v9 + v_add_u32_e32 v15, v13, v85 + v_and_b32_e32 v15, -8, v15 + v_sub_u32_e32 v13, v13, v15 + v_xor_b32_e32 v13, v13, v67 + v_sub_u32_e32 v15, v13, v16 + v_lshlrev_b32_e32 v16, 3, v15 + v_or_b32_e32 v17, 6, v9 + v_add_u32_e32 v18, v17, v85 + v_and_b32_e32 v18, -8, v18 + v_sub_u32_e32 v17, v17, v18 + v_xor_b32_e32 v17, v17, v67 + v_sub_u32_e32 v13, v17, v13 + v_lshlrev_b32_e32 v18, 3, v13 + v_add3_u32 v12, v12, v16, v18 + v_lshlrev_b32_e32 v10, 4, v10 + v_add3_u32 v10, v11, s22, v10 + s_waitcnt vmcnt(10) + ds_write_b128 v10, v[30:33] offset:128 + v_or_b32_e32 v9, 7, v9 + v_add_u32_e32 v11, v9, v85 + v_and_b32_e32 v11, 0xffffff8, v11 + v_sub_u32_e32 v9, v9, v11 + v_xor_b32_e32 v9, v9, v67 + v_sub_u32_e32 v9, v9, v17 + v_lshlrev_b32_e32 v9, 4, v9 + v_lshl_add_u32 v9, v12, 1, v9 + v_lshlrev_b32_e32 v11, 4, v14 + v_add3_u32 v10, v10, s22, v11 + s_waitcnt vmcnt(7) + ds_write_b128 v10, v[42:45] offset:128 + v_lshlrev_b32_e32 v11, 4, v15 + v_add3_u32 v10, v10, s22, v11 + s_waitcnt vmcnt(6) + ds_write_b128 v10, v[46:49] offset:128 + v_lshlrev_b32_e32 v11, 4, v13 + v_add3_u32 v10, v10, s22, v11 + s_waitcnt vmcnt(5) + ds_write_b128 v10, v[50:53] offset:128 + s_waitcnt vmcnt(4) + ds_write_b128 v9, v[54:57] offset:896 + s_mov_b32 s22, 0x1000504 + v_perm_b32 v10, v22, v26, s22 + s_mov_b32 s23, 0x3020706 + v_perm_b32 v14, v22, v26, s23 + v_perm_b32 v11, v34, v38, s22 + v_perm_b32 v15, v34, v38, s23 + s_waitcnt vmcnt(2) + v_perm_b32 v12, v58, v62, s22 + v_perm_b32 v16, v58, v62, s23 + s_waitcnt vmcnt(0) + v_perm_b32 v13, v74, v78, s22 + v_perm_b32 v17, v74, v78, s23 + v_perm_b32 v18, v23, v27, s22 + v_perm_b32 v30, v23, v27, s23 + v_perm_b32 v19, v35, v39, s22 + v_perm_b32 v31, v35, v39, s23 + v_perm_b32 v20, v59, v63, s22 + v_perm_b32 v32, v59, v63, s23 + v_perm_b32 v21, v75, v79, s22 + v_perm_b32 v33, v75, v79, s23 + v_perm_b32 v42, v24, v28, s22 + v_perm_b32 v46, v24, v28, s23 + v_perm_b32 v43, v36, v40, s22 + v_perm_b32 v47, v36, v40, s23 + v_perm_b32 v44, v60, v64, s22 + v_perm_b32 v48, v60, v64, s23 + v_perm_b32 v45, v76, v80, s22 + v_perm_b32 v49, v76, v80, s23 + v_perm_b32 v22, v25, v29, s22 + v_perm_b32 v26, v25, v29, s23 + v_perm_b32 v23, v37, v41, s22 + v_perm_b32 v27, v37, v41, s23 + v_perm_b32 v24, v61, v65, s22 + v_perm_b32 v28, v61, v65, s23 + v_perm_b32 v25, v77, v81, s22 + v_perm_b32 v29, v77, v81, s23 + v_and_b32_e32 v104, 24, v3 + v_add_u32_e32 v3, s21, v104 + v_lshrrev_b32_e32 v9, 2, v3 + v_and_b32_e32 v9, 24, v9 + v_xor_b32_e32 v34, v9, v73 + v_lshlrev_b32_e32 v35, 9, v3 + v_and_b32_e32 v35, 0x3000, v35 + v_lshlrev_b32_e32 v3, 6, v3 + v_and_b32_e32 v3, 0xfffff800, v3 + v_add_u32_e32 v3, v3, v35 + v_lshl_or_b32 v3, v34, 3, v3 + v_lshlrev_b32_e32 v35, 1, v3 + ds_write_b128 v35, v[10:13] offset:32768 + v_or_b32_e32 v10, 1, v9 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v11, v10, v34 + v_lshl_add_u32 v3, v11, 3, v3 + v_lshl_add_u32 v11, v11, 4, v35 + ds_write_b128 v11, v[14:17] offset:33280 + v_or_b32_e32 v11, 2, v9 + v_xor_b32_e32 v11, v11, v73 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + s_movk_i32 s21, 0x100 + v_add3_u32 v3, v3, v10, s21 + v_lshlrev_b32_e32 v10, 1, v3 + ds_write_b128 v10, v[18:21] offset:33280 + v_or_b32_e32 v10, 3, v9 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v11, v10, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v3, v3, v11, s21 + v_lshlrev_b32_e32 v11, 1, v3 + ds_write_b128 v11, v[30:33] offset:33280 + v_or_b32_e32 v11, 4, v9 + v_xor_b32_e32 v11, v11, v73 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add3_u32 v3, v3, v10, s21 + v_lshlrev_b32_e32 v10, 1, v3 + ds_write_b128 v10, v[42:45] offset:33280 + v_or_b32_e32 v10, 5, v9 + v_xor_b32_e32 v10, v10, v73 + v_sub_u32_e32 v11, v10, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_add3_u32 v3, v3, v11, s21 + v_lshlrev_b32_e32 v11, 1, v3 + ds_write_b128 v11, v[46:49] offset:33280 + v_or_b32_e32 v11, 6, v9 + v_xor_b32_e32 v11, v11, v73 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_add_lshl_u32 v3, v3, v10, 1 + v_or_b32_e32 v9, 7, v9 + v_xor_b32_e32 v9, v9, v73 + v_sub_u32_e32 v9, v9, v11 + v_lshl_add_u32 v9, v9, 4, v3 + ds_write_b128 v3, v[22:25] offset:33792 + ds_write_b128 v9, v[26:29] offset:34304 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v15, 2, v2 + v_or_b32_e32 v14, 4, v2 + v_add_u32_e32 v13, 6, v2 + v_add_u32_e32 v12, 16, v69 + v_add_u32_e32 v11, 48, v69 + v_or_b32_e32 v10, 8, v4 + v_or_b32_e32 v9, 16, v4 + v_or_b32_e32 v3, 24, v4 + s_cbranch_vccnz .LBB15_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit193.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v16, v15, v67 + v_lshl_add_u32 v78, v16, 3, v8 + v_xor_b32_e32 v17, v14, v67 + v_lshl_add_u32 v79, v17, 3, v8 + v_xor_b32_e32 v18, v13, v67 + v_lshl_add_u32 v69, v18, 3, v8 + v_sub_u32_e32 v19, v5, v18 + v_mov_b32_e32 v20, 0x1000 + v_lshl_add_u32 v19, v19, 3, v20 + v_add_u32_e32 v95, v69, v19 + v_sub_u32_e32 v16, v16, v5 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v80, v95, v16 + v_sub_u32_e32 v17, v17, v5 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v83, v95, v17 + v_sub_u32_e32 v18, v18, v5 + v_lshlrev_b32_e32 v18, 3, v18 + v_add_u32_e32 v75, v95, v18 + v_add_u32_e32 v94, v75, v19 + v_add_u32_e32 v81, v94, v16 + v_add_u32_e32 v82, v94, v17 + v_add_u32_e32 v74, v94, v18 + v_add_u32_e32 v91, v74, v19 + v_add_u32_e32 v76, v91, v16 + v_add_u32_e32 v77, v91, v17 + v_add_u32_e32 v71, v91, v18 + v_lshrrev_b32_e32 v16, 5, v12 + v_bfe_u32 v17, v12, 3, 2 + v_lshl_or_b32 v18, v16, 3, v67 + v_xor_b32_e32 v19, v4, v18 + v_sub_u32_e32 v20, v19, v7 + v_lshlrev_b32_e32 v21, 11, v16 + v_lshlrev_b32_e32 v20, 3, v20 + v_sub_u32_e32 v22, v17, v2 + v_lshl_or_b32 v21, v22, 12, v21 + v_add3_u32 v86, v6, v21, v20 + v_xor_b32_e32 v16, 1, v16 + v_sub_u32_e32 v17, v2, v17 + v_lshl_add_u32 v20, v16, 3, v18 + v_xor_b32_e32 v22, v4, v20 + v_sub_u32_e32 v19, v22, v19 + v_lshlrev_b32_e32 v16, 11, v16 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshl_or_b32 v16, v17, 12, v16 + v_add3_u32 v84, v19, v16, v86 + v_lshrrev_b32_e32 v17, 5, v11 + v_add_u32_e32 v19, -1, v17 + v_bfe_u32 v23, v11, 3, 2 + v_sub_u32_e32 v24, v23, v2 + v_lshl_add_u32 v25, v19, 3, v20 + v_ashrrev_i32_e32 v26, 31, v25 + v_lshrrev_b32_e32 v26, 27, v26 + v_add_u32_e32 v26, v25, v26 + v_and_b32_e32 v26, 0xffffffe0, v26 + v_sub_u32_e32 v26, v25, v26 + v_xor_b32_e32 v27, v4, v26 + v_sub_u32_e32 v22, v27, v22 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshl_add_u32 v19, v24, 12, v19 + v_add3_u32 v85, v22, v19, v84 + v_sub_u32_e32 v22, v2, v23 + v_lshlrev_b32_e32 v23, 3, v17 + v_sub_u32_e32 v23, v25, v23 + v_ashrrev_i32_e32 v24, 31, v23 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v23, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v23, v23, v24 + v_xor_b32_e32 v24, v10, v23 + v_sub_u32_e32 v25, v24, v27 + v_lshlrev_b32_e32 v25, 3, v25 + v_lshlrev_b32_e32 v22, 12, v22 + v_lshlrev_b32_e32 v17, 11, v17 + v_sub_u32_e32 v17, v22, v17 + v_add3_u32 v96, v25, v17, v85 + v_xor_b32_e32 v22, v10, v18 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v97, v24, v21, v96 + v_xor_b32_e32 v24, v10, v20 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v87, v22, v16, v97 + v_xor_b32_e32 v22, v10, v26 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v88, v24, v19, v87 + v_xor_b32_e32 v24, v9, v23 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v98, v22, v17, v88 + v_xor_b32_e32 v22, v9, v18 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v99, v24, v21, v98 + v_xor_b32_e32 v24, v9, v20 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v89, v22, v16, v99 + v_xor_b32_e32 v22, v9, v26 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v90, v24, v19, v89 + v_xor_b32_e32 v23, v3, v23 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v100, v22, v17, v90 + v_xor_b32_e32 v17, v3, v18 + v_sub_u32_e32 v18, v17, v23 + v_lshlrev_b32_e32 v18, 3, v18 + v_add3_u32 v101, v18, v21, v100 + v_xor_b32_e32 v18, v3, v20 + v_sub_u32_e32 v17, v18, v17 + v_lshlrev_b32_e32 v17, 3, v17 + v_add3_u32 v92, v17, v16, v101 + v_xor_b32_e32 v16, v3, v26 + v_sub_u32_e32 v16, v16, v18 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v93, v16, v19, v92 + s_mov_b64 s[2:3], 0 + s_branch .LBB15_6 +.LBB15_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr93 +.LBB15_6: ; %Flow1296 + v_lshl_or_b32 v16, v5, 3, v8 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a96, 0 + v_lshlrev_b32_e32 v103, 1, v16 + v_lshlrev_b32_e32 v102, 1, v6 + s_cbranch_vccnz .LBB15_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i530.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s20, 6 + v_xor_b32_e32 v15, v15, v67 + v_lshl_add_u32 v78, v15, 3, v8 + v_xor_b32_e32 v14, v14, v67 + v_lshl_add_u32 v79, v14, 3, v8 + v_xor_b32_e32 v13, v13, v67 + v_lshl_add_u32 v69, v13, 3, v8 + v_sub_u32_e32 v8, v5, v13 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_u32_e32 v16, 0x1000, v8 + v_add_u32_e32 v95, v69, v16 + v_add_u32_e32 v8, v69, v8 + v_lshlrev_b32_e32 v105, 1, v8 + v_sub_u32_e32 v15, v15, v5 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v80, v95, v15 + v_add_lshl_u32 v106, v8, v15, 1 + v_sub_u32_e32 v14, v14, v5 + v_lshlrev_b32_e32 v14, 3, v14 + v_add_u32_e32 v83, v95, v14 + v_add_lshl_u32 v107, v8, v14, 1 + v_sub_u32_e32 v5, v13, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v75, v95, v5 + v_add_u32_e32 v8, v8, v5 + v_lshlrev_b32_e32 v108, 1, v8 + v_add_u32_e32 v94, v75, v16 + v_add_lshl_u32 v109, v8, v16, 1 + v_add_u32_e32 v81, v94, v15 + v_add_u32_e32 v82, v94, v14 + v_add_u32_e32 v74, v94, v5 + v_add_u32_e32 v91, v74, v16 + v_add_u32_e32 v76, v91, v15 + v_add_u32_e32 v77, v91, v14 + v_add_u32_e32 v71, v91, v5 + v_lshrrev_b32_e32 v5, 5, v12 + v_bfe_u32 v8, v12, 3, 2 + v_lshl_or_b32 v12, v5, 3, v67 + v_xor_b32_e32 v13, v4, v12 + v_sub_u32_e32 v7, v13, v7 + v_lshlrev_b32_e32 v14, 11, v5 + v_lshlrev_b32_e32 v7, 3, v7 + v_sub_u32_e32 v15, v8, v2 + v_lshl_or_b32 v14, v15, 12, v14 + v_add3_u32 v86, v6, v14, v7 + v_xor_b32_e32 v5, 1, v5 + v_sub_u32_e32 v6, v2, v8 + v_lshl_add_u32 v7, v5, 3, v12 + v_xor_b32_e32 v8, v4, v7 + v_sub_u32_e32 v13, v8, v13 + v_lshlrev_b32_e32 v5, 11, v5 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshl_or_b32 v5, v6, 12, v5 + v_add3_u32 v84, v13, v5, v86 + v_lshrrev_b32_e32 v6, 5, v11 + v_add_u32_e32 v13, -1, v6 + v_bfe_u32 v11, v11, 3, 2 + v_sub_u32_e32 v15, v11, v2 + v_lshl_add_u32 v16, v13, 3, v7 + v_ashrrev_i32_e32 v17, 31, v16 + v_lshrrev_b32_e32 v17, 27, v17 + v_add_u32_e32 v17, v16, v17 + v_and_b32_e32 v17, 0xffffffe0, v17 + v_sub_u32_e32 v17, v16, v17 + v_xor_b32_e32 v4, v4, v17 + v_sub_u32_e32 v8, v4, v8 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v8, 3, v8 + v_lshl_add_u32 v13, v15, 12, v13 + v_add3_u32 v85, v8, v13, v84 + v_sub_u32_e32 v2, v2, v11 + v_lshlrev_b32_e32 v8, 3, v6 + v_sub_u32_e32 v8, v16, v8 + v_ashrrev_i32_e32 v11, 31, v8 + v_lshrrev_b32_e32 v11, 27, v11 + v_add_u32_e32 v11, v8, v11 + v_and_b32_e32 v11, 0xffffffe0, v11 + v_sub_u32_e32 v8, v8, v11 + v_xor_b32_e32 v11, v10, v8 + v_sub_u32_e32 v4, v11, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_lshlrev_b32_e32 v2, 12, v2 + v_lshlrev_b32_e32 v6, 11, v6 + v_sub_u32_e32 v2, v2, v6 + v_add3_u32 v96, v4, v2, v85 + v_xor_b32_e32 v4, v10, v12 + v_sub_u32_e32 v6, v4, v11 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v97, v6, v14, v96 + v_xor_b32_e32 v6, v10, v7 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v87, v4, v5, v97 + v_xor_b32_e32 v4, v10, v17 + v_sub_u32_e32 v6, v4, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v88, v6, v13, v87 + v_xor_b32_e32 v6, v9, v8 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v98, v4, v2, v88 + v_xor_b32_e32 v4, v9, v12 + v_sub_u32_e32 v6, v4, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v99, v6, v14, v98 + v_xor_b32_e32 v6, v9, v7 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v89, v4, v5, v99 + v_xor_b32_e32 v4, v9, v17 + v_sub_u32_e32 v6, v4, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_add3_u32 v90, v6, v13, v89 + v_xor_b32_e32 v6, v3, v8 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v100, v4, v2, v90 + v_xor_b32_e32 v2, v3, v12 + v_sub_u32_e32 v4, v2, v6 + v_lshlrev_b32_e32 v4, 3, v4 + v_add3_u32 v101, v4, v14, v100 + v_xor_b32_e32 v4, v3, v7 + v_sub_u32_e32 v2, v4, v2 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v92, v2, v5, v101 + v_xor_b32_e32 v2, v3, v17 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v93, v2, v13, v92 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a96, 0 + s_movk_i32 s6, 0x80 + s_mov_b32 s21, 0x1000504 + s_mov_b32 s22, 0x3020706 + s_movk_i32 s23, 0x100 +.LBB15_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i530.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v70, s2, v70 + v_add_u32_e32 v68, 64, v68 + v_lshlrev_b32_e32 v6, 1, v68 + v_add_u32_e32 v2, s7, v68 + v_lshlrev_b32_e32 v3, 1, v70 + v_add_u32_e32 v7, s20, v70 + v_lshlrev_b32_e32 v8, 1, v2 + v_add_u32_e32 v9, s7, v2 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 1, v7 + v_add_u32_e32 v7, s20, v7 + buffer_load_dwordx4 v[34:37], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v8, s[8:11], 0 offen + v_lshlrev_b32_e32 v11, 1, v9 + v_add_u32_e32 v6, s7, v9 + buffer_load_dwordx4 v[18:21], v10, s[12:15], 0 offen + v_lshlrev_b32_e32 v8, 1, v7 + v_add_u32_e32 v10, s20, v7 + v_lshlrev_b32_e32 v12, 1, v6 + v_add_u32_e32 v13, s7, v6 + buffer_load_dwordx4 v[6:9], v8, s[12:15], 0 offen + v_lshlrev_b32_e32 v14, 1, v10 + v_add_u32_e32 v10, s20, v10 + buffer_load_dwordx4 v[50:53], v11, s[8:11], 0 offen + buffer_load_dwordx4 v[54:57], v12, s[8:11], 0 offen + v_lshlrev_b32_e32 v15, 1, v13 + v_add_u32_e32 v11, s7, v13 + buffer_load_dwordx4 v[26:29], v14, s[12:15], 0 offen + v_lshlrev_b32_e32 v12, 1, v10 + v_add_u32_e32 v14, s20, v10 + v_lshlrev_b32_e32 v16, 1, v11 + v_add_u32_e32 v17, s7, v11 + buffer_load_dwordx4 v[10:13], v12, s[12:15], 0 offen + v_lshlrev_b32_e32 v22, 1, v14 + v_add_u32_e32 v14, s20, v14 + buffer_load_dwordx4 v[58:61], v15, s[8:11], 0 offen + buffer_load_dwordx4 v[62:65], v16, s[8:11], 0 offen + v_lshlrev_b32_e32 v15, 1, v17 + v_add_lshl_u32 v16, v17, s7, 1 + buffer_load_dwordx4 v[30:33], v22, s[12:15], 0 offen + v_lshlrev_b32_e32 v17, 1, v14 + v_add_lshl_u32 v22, v14, s20, 1 + buffer_load_dwordx4 v[42:45], v15, s[8:11], 0 offen + buffer_load_dwordx4 v[46:49], v16, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[14:17], v17, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[22:25], v22, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[114:117], v103 + ds_read_b128 v[110:113], v102 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[114:115], v[110:111], a[96:111] + v_lshlrev_b32_e32 v118, 1, v96 + ds_read_b128 v[120:123], v118 offset:32768 + v_lshlrev_b32_e32 v118, 1, v97 + ds_read_b128 v[124:127], v118 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[114:115], v[120:121], a[80:95] + v_lshlrev_b32_e32 v118, 1, v98 + ds_read_b128 v[128:131], v118 offset:32768 + v_lshlrev_b32_e32 v118, 1, v99 + ds_read_b128 v[132:135], v118 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[114:115], v[128:129], a[64:79] + v_lshlrev_b32_e32 v118, 1, v100 + ds_read_b128 v[136:139], v118 offset:32768 + v_lshlrev_b32_e32 v118, 1, v101 + ds_read_b128 v[140:143], v118 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[114:115], v[136:137], a[128:143] + ds_read_b128 v[144:147], v105 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[144:145], v[110:111], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[144:145], v[120:121], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[144:145], v[128:129], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[144:145], v[136:137], a[176:191] + ds_read_b128 v[148:151], v109 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[148:149], v[110:111], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[148:149], v[120:121], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[148:149], v[128:129], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[148:149], v[136:137], a[240:255] + v_lshlrev_b32_e32 v114, 1, v94 + ds_read_b128 v[152:155], v114 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[110:111], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[120:121], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[128:129], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[136:137], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[116:117], v[112:113], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[116:117], v[122:123], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[116:117], v[130:131], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[116:117], v[138:139], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[146:147], v[112:113], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[146:147], v[122:123], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[146:147], v[130:131], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[146:147], v[138:139], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[150:151], v[112:113], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[150:151], v[122:123], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[150:151], v[130:131], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[150:151], v[138:139], a[240:255] + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[112:113], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[122:123], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[130:131], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[154:155], v[138:139], a[48:63] + v_lshlrev_b32_e32 v110, 1, v78 + ds_read_b128 v[112:115], v110 + v_lshlrev_b32_e32 v110, 1, v86 + ds_read_b128 v[116:119], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v79 + ds_read_b128 v[128:131], v110 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[112:113], v[116:117], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[112:113], v[124:125], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[112:113], v[132:133], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[112:113], v[140:141], a[128:143] + ds_read_b128 v[110:113], v106 offset:8192 + ds_read_b128 v[136:139], v107 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[110:111], v[116:117], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[110:111], v[124:125], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[110:111], v[132:133], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[110:111], v[140:141], a[176:191] + v_lshlrev_b32_e32 v110, 1, v80 + ds_read_b128 v[120:123], v110 offset:8192 + v_lshlrev_b32_e32 v110, 1, v83 + ds_read_b128 v[144:147], v110 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[192:207], v[120:121], v[116:117], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[120:121], v[124:125], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[120:121], v[132:133], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[120:121], v[140:141], a[240:255] + v_lshlrev_b32_e32 v110, 1, v81 + ds_read_b128 v[148:151], v110 offset:8192 + v_lshlrev_b32_e32 v110, 1, v82 + ds_read_b128 v[152:155], v110 offset:8192 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[0:15], v[148:149], v[116:117], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[148:149], v[124:125], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[148:149], v[132:133], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[148:149], v[140:141], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[114:115], v[118:119], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[114:115], v[126:127], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[114:115], v[134:135], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[114:115], v[142:143], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[112:113], v[118:119], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[112:113], v[126:127], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[112:113], v[134:135], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[112:113], v[142:143], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[122:123], v[118:119], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[122:123], v[126:127], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[122:123], v[134:135], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[122:123], v[142:143], a[240:255] + v_mfma_f32_32x32x8_bf16 a[0:15], v[150:151], v[118:119], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[150:151], v[126:127], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[150:151], v[134:135], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[150:151], v[142:143], a[48:63] + v_lshlrev_b32_e32 v110, 1, v84 + ds_read_b128 v[132:135], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v85 + ds_read_b128 v[122:125], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[128:129], v[132:133], a[96:111] + v_lshlrev_b32_e32 v110, 1, v87 + ds_read_b128 v[140:143], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v88 + ds_read_b128 v[118:121], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[80:95], v[128:129], v[140:141], a[80:95] + v_lshlrev_b32_e32 v110, 1, v89 + ds_read_b128 v[148:151], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v90 + ds_read_b128 v[114:117], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[64:79], v[128:129], v[148:149], a[64:79] + v_lshlrev_b32_e32 v110, 1, v92 + ds_read_b128 v[156:159], v110 offset:32768 + v_lshlrev_b32_e32 v110, 1, v93 + ds_read_b128 v[110:113], v110 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[156:157], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[136:137], v[132:133], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[136:137], v[140:141], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[136:137], v[148:149], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[136:137], v[156:157], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[144:145], v[132:133], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[144:145], v[140:141], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[144:145], v[148:149], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[156:157], a[240:255] + v_mfma_f32_32x32x8_bf16 a[0:15], v[152:153], v[132:133], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[152:153], v[140:141], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[152:153], v[148:149], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[152:153], v[156:157], a[48:63] + v_mfma_f32_32x32x8_bf16 a[96:111], v[130:131], v[134:135], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[130:131], v[142:143], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[130:131], v[150:151], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[130:131], v[158:159], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[138:139], v[134:135], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[138:139], v[142:143], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[138:139], v[150:151], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[138:139], v[158:159], a[176:191] + v_mfma_f32_32x32x8_bf16 a[192:207], v[146:147], v[134:135], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[146:147], v[142:143], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[146:147], v[150:151], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[158:159], a[240:255] + v_mfma_f32_32x32x8_bf16 a[0:15], v[154:155], v[134:135], a[0:15] + v_mfma_f32_32x32x8_bf16 a[32:47], v[154:155], v[142:143], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[154:155], v[150:151], a[16:31] + v_mfma_f32_32x32x8_bf16 a[48:63], v[154:155], v[158:159], a[48:63] + v_lshlrev_b32_e32 v126, 1, v69 + ds_read_b128 v[126:129], v126 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[126:127], v[122:123], a[96:111] + v_mfma_f32_32x32x8_bf16 a[80:95], v[126:127], v[118:119], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_f32_32x32x8_bf16 a[128:143], v[126:127], v[110:111], a[128:143] + ds_read_b128 v[130:133], v108 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[130:131], v[122:123], a[112:127] + v_mfma_f32_32x32x8_bf16 a[144:159], v[130:131], v[118:119], a[144:159] + v_mfma_f32_32x32x8_bf16 a[160:175], v[130:131], v[114:115], a[160:175] + v_mfma_f32_32x32x8_bf16 a[176:191], v[130:131], v[110:111], a[176:191] + v_lshlrev_b32_e32 v126, 1, v75 + ds_read_b128 v[144:147], v126 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[192:207], v[144:145], v[122:123], a[192:207] + v_mfma_f32_32x32x8_bf16 a[208:223], v[144:145], v[118:119], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[144:145], v[114:115], a[224:239] + v_mfma_f32_32x32x8_bf16 a[240:255], v[144:145], v[110:111], a[240:255] + v_lshlrev_b32_e32 v126, 1, v74 + ds_read_b128 v[148:151], v126 offset:8192 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[0:15], v[148:149], v[122:123], a[0:15] + s_add_i32 s24, s3, -1 + v_mfma_f32_32x32x8_bf16 a[32:47], v[148:149], v[118:119], a[32:47] + v_readfirstlane_b32 s25, v0 + s_and_b32 s26, s25, 0xffffffc0 + s_lshr_b32 s25, s25, 2 + v_add_u32_e32 v118, s26, v72 + s_and_b32 s25, s25, 0x3ffffff0 + v_lshl_or_b32 v119, v118, 6, v66 + v_or_b32_e32 v122, 1, v118 + v_mfma_f32_32x32x8_bf16 a[16:31], v[148:149], v[114:115], a[16:31] + v_ashrrev_i32_e32 v114, 31, v118 + v_or_b32_e32 v115, 2, v118 + v_or_b32_e32 v123, 3, v118 + v_or_b32_e32 v126, 4, v118 + v_or_b32_e32 v127, 5, v118 + v_or_b32_e32 v130, 6, v118 + v_or_b32_e32 v118, 7, v118 + v_mfma_f32_32x32x8_bf16 a[48:63], v[148:149], v[110:111], a[48:63] + v_add_u32_e32 v110, s25, v104 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s24 + v_lshlrev_b32_e32 v111, 1, v119 + v_lshrrev_b32_e32 v114, 29, v114 + v_lshrrev_b32_e32 v131, 2, v110 + v_lshlrev_b32_e32 v134, 9, v110 + v_mfma_f32_32x32x8_bf16 a[96:111], v[128:129], v[124:125], a[96:111] + v_lshlrev_b32_e32 v110, 6, v110 + v_add_u32_e32 v135, v122, v114 + v_add_u32_e32 v136, v115, v114 + v_add_u32_e32 v137, v123, v114 + v_add_u32_e32 v138, v126, v114 + v_add_u32_e32 v139, v127, v114 + v_add_u32_e32 v140, v130, v114 + v_mfma_f32_32x32x8_bf16 a[80:95], v[128:129], v[120:121], a[80:95] + v_add_u32_e32 v114, v118, v114 + v_and_b32_e32 v131, 24, v131 + v_and_b32_e32 v134, 0x3000, v134 + v_and_b32_e32 v110, 0xfffff800, v110 + v_and_b32_e32 v135, -8, v135 + v_and_b32_e32 v136, -8, v136 + v_and_b32_e32 v137, -8, v137 + v_mfma_f32_32x32x8_bf16 a[64:79], v[128:129], v[116:117], a[64:79] + v_and_b32_e32 v138, -8, v138 + v_and_b32_e32 v139, -8, v139 + v_and_b32_e32 v140, -8, v140 + v_and_b32_e32 v114, 0xffffff8, v114 + v_xor_b32_e32 v141, v131, v73 + v_add_u32_e32 v110, v110, v134 + v_or_b32_e32 v134, 1, v131 + v_mfma_f32_32x32x8_bf16 a[128:143], v[128:129], v[112:113], a[128:143] + v_or_b32_e32 v128, 2, v131 + v_or_b32_e32 v129, 3, v131 + v_or_b32_e32 v142, 4, v131 + v_or_b32_e32 v143, 5, v131 + v_or_b32_e32 v144, 6, v131 + v_or_b32_e32 v131, 7, v131 + v_sub_u32_e32 v122, v122, v135 + v_mfma_f32_32x32x8_bf16 a[112:127], v[132:133], v[124:125], a[112:127] + v_sub_u32_e32 v115, v115, v136 + v_sub_u32_e32 v123, v123, v137 + v_sub_u32_e32 v126, v126, v138 + v_sub_u32_e32 v127, v127, v139 + v_sub_u32_e32 v130, v130, v140 + v_sub_u32_e32 v114, v118, v114 + v_lshl_or_b32 v110, v141, 3, v110 + v_mfma_f32_32x32x8_bf16 a[144:159], v[132:133], v[120:121], a[144:159] + v_xor_b32_e32 v118, v134, v73 + v_xor_b32_e32 v128, v128, v73 + v_xor_b32_e32 v129, v129, v73 + v_xor_b32_e32 v134, v142, v73 + v_xor_b32_e32 v135, v143, v73 + v_xor_b32_e32 v136, v144, v73 + v_xor_b32_e32 v131, v131, v73 + v_mfma_f32_32x32x8_bf16 a[160:175], v[132:133], v[116:117], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_xor_b32_e32 v122, v122, v67 + v_xor_b32_e32 v115, v115, v67 + v_xor_b32_e32 v123, v123, v67 + v_xor_b32_e32 v126, v126, v67 + v_xor_b32_e32 v127, v127, v67 + v_mfma_f32_32x32x8_bf16 a[176:191], v[132:133], v[112:113], a[176:191] + v_xor_b32_e32 v130, v130, v67 + v_xor_b32_e32 v114, v114, v67 + v_lshlrev_b32_e32 v132, 1, v110 + v_sub_u32_e32 v133, v118, v141 + v_sub_u32_e32 v118, v128, v118 + v_sub_u32_e32 v128, v129, v128 + v_sub_u32_e32 v129, v134, v129 + v_mfma_f32_32x32x8_bf16 a[192:207], v[146:147], v[124:125], a[192:207] + v_sub_u32_e32 v134, v135, v134 + v_sub_u32_e32 v135, v136, v135 + v_sub_u32_e32 v131, v131, v136 + v_sub_u32_e32 v136, v122, v67 + v_sub_u32_e32 v122, v115, v122 + v_sub_u32_e32 v115, v123, v115 + v_sub_u32_e32 v123, v126, v123 + v_mfma_f32_32x32x8_bf16 a[208:223], v[146:147], v[120:121], a[208:223] + v_sub_u32_e32 v126, v127, v126 + v_sub_u32_e32 v127, v130, v127 + v_sub_u32_e32 v114, v114, v130 + v_lshl_add_u32 v110, v133, 3, v110 + v_lshl_add_u32 v130, v133, 4, v132 + v_lshlrev_b32_e32 v118, 3, v118 + v_lshlrev_b32_e32 v128, 3, v128 + v_mfma_f32_32x32x8_bf16 a[224:239], v[146:147], v[116:117], a[224:239] + v_lshlrev_b32_e32 v129, 3, v129 + v_lshlrev_b32_e32 v133, 3, v134 + v_lshlrev_b32_e32 v134, 3, v135 + v_lshlrev_b32_e32 v135, 3, v136 + v_lshlrev_b32_e32 v137, 3, v122 + v_lshl_add_u32 v136, v136, 4, v111 + v_lshlrev_b32_e32 v138, 3, v115 + v_mfma_f32_32x32x8_bf16 a[240:255], v[146:147], v[112:113], a[240:255] + v_lshlrev_b32_e32 v139, 3, v123 + v_lshlrev_b32_e32 v122, 4, v122 + v_lshlrev_b32_e32 v140, 3, v126 + v_lshlrev_b32_e32 v141, 3, v127 + v_lshlrev_b32_e32 v115, 4, v115 + v_lshlrev_b32_e32 v114, 4, v114 + v_lshlrev_b32_e32 v123, 4, v123 + v_mfma_f32_32x32x8_bf16 a[0:15], v[150:151], v[124:125], a[0:15] + v_lshlrev_b32_e32 v124, 4, v126 + v_add3_u32 v110, v110, v118, s23 + v_add3_u32 v118, v135, v119, v137 + v_add3_u32 v119, v136, s6, v122 + v_lshlrev_b32_e32 v126, 1, v110 + v_add3_u32 v110, v110, v128, s23 + v_add3_u32 v118, v118, v138, v139 + v_mfma_f32_32x32x8_bf16 a[32:47], v[150:151], v[120:121], a[32:47] + v_add3_u32 v115, v119, s6, v115 + v_lshlrev_b32_e32 v128, 1, v110 + v_add3_u32 v110, v110, v129, s23 + v_add3_u32 v118, v118, v140, v141 + v_add3_u32 v120, v115, s6, v123 + v_lshlrev_b32_e32 v129, 1, v110 + v_add3_u32 v110, v110, v133, s23 + v_mfma_f32_32x32x8_bf16 a[16:31], v[150:151], v[116:117], a[16:31] + v_lshl_add_u32 v117, v118, 1, v114 + v_add3_u32 v116, v120, s6, v124 + v_lshlrev_b32_e32 v133, 1, v110 + v_add_lshl_u32 v134, v110, v134, 1 + v_add_u32_e32 v110, 0x80, v116 + v_lshl_add_u32 v131, v131, 4, v134 + v_lshl_add_u32 v121, v127, 4, v110 + v_mfma_f32_32x32x8_bf16 a[48:63], v[150:151], v[112:113], a[48:63] + s_waitcnt vmcnt(14) + ds_write_b128 v111, v[34:37] + s_waitcnt vmcnt(13) + ds_write_b128 v136, v[38:41] offset:128 + s_waitcnt vmcnt(12) + v_perm_b32 v34, v2, v18, s21 + v_perm_b32 v2, v2, v18, s22 + v_perm_b32 v18, v3, v19, s21 + v_perm_b32 v38, v3, v19, s22 + v_perm_b32 v110, v4, v20, s21 + v_perm_b32 v114, v4, v20, s22 + v_perm_b32 v118, v5, v21, s21 + v_perm_b32 v122, v5, v21, s22 + s_waitcnt vmcnt(10) + ds_write_b128 v119, v[50:53] offset:128 + s_waitcnt vmcnt(9) + ds_write_b128 v115, v[54:57] offset:128 + s_waitcnt vmcnt(8) + v_perm_b32 v35, v6, v26, s21 + v_perm_b32 v3, v6, v26, s22 + v_perm_b32 v19, v7, v27, s21 + v_perm_b32 v39, v7, v27, s22 + v_perm_b32 v111, v8, v28, s21 + v_perm_b32 v115, v8, v28, s22 + v_perm_b32 v119, v9, v29, s21 + v_perm_b32 v123, v9, v29, s22 + s_waitcnt vmcnt(6) + ds_write_b128 v120, v[58:61] offset:128 + s_waitcnt vmcnt(5) + ds_write_b128 v116, v[62:65] offset:128 + s_waitcnt vmcnt(4) + v_perm_b32 v36, v10, v30, s21 + v_perm_b32 v4, v10, v30, s22 + v_perm_b32 v20, v11, v31, s21 + v_perm_b32 v40, v11, v31, s22 + v_perm_b32 v112, v12, v32, s21 + v_perm_b32 v116, v12, v32, s22 + v_perm_b32 v120, v13, v33, s21 + v_perm_b32 v124, v13, v33, s22 + s_waitcnt vmcnt(3) + ds_write_b128 v121, v[42:45] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v117, v[46:49] offset:896 + s_waitcnt vmcnt(0) + v_perm_b32 v37, v14, v22, s21 + v_perm_b32 v5, v14, v22, s22 + v_perm_b32 v21, v15, v23, s21 + v_perm_b32 v41, v15, v23, s22 + v_perm_b32 v113, v16, v24, s21 + v_perm_b32 v117, v16, v24, s22 + v_perm_b32 v121, v17, v25, s21 + v_perm_b32 v125, v17, v25, s22 + ds_write_b128 v132, v[34:37] offset:32768 + ds_write_b128 v130, v[2:5] offset:33280 + ds_write_b128 v126, v[18:21] offset:33280 + ds_write_b128 v128, v[38:41] offset:33280 + ds_write_b128 v129, v[110:113] offset:33280 + ds_write_b128 v133, v[114:117] offset:33280 + ds_write_b128 v134, v[118:121] offset:33792 + ds_write_b128 v131, v[122:125] offset:34304 + s_cbranch_scc1 .LBB15_8 +.LBB15_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEDF16bNS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDa + v_accvgpr_read_b32 v152, a144 + v_accvgpr_read_b32 v153, a145 + v_accvgpr_read_b32 v154, a146 + v_accvgpr_read_b32 v155, a147 + v_accvgpr_read_b32 v156, a148 + v_accvgpr_read_b32 v157, a149 + v_accvgpr_read_b32 v158, a150 + v_accvgpr_read_b32 v159, a151 + v_accvgpr_read_b32 v160, a152 + v_accvgpr_read_b32 v161, a153 + v_accvgpr_read_b32 v162, a154 + v_accvgpr_read_b32 v163, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v165, a157 + v_accvgpr_read_b32 v166, a158 + v_accvgpr_read_b32 v167, a159 + v_accvgpr_read_b32 v136, a176 + v_accvgpr_read_b32 v137, a177 + v_accvgpr_read_b32 v138, a178 + v_accvgpr_read_b32 v139, a179 + v_accvgpr_read_b32 v140, a180 + v_accvgpr_read_b32 v141, a181 + v_accvgpr_read_b32 v142, a182 + v_accvgpr_read_b32 v143, a183 + v_accvgpr_read_b32 v144, a184 + v_accvgpr_read_b32 v145, a185 + v_accvgpr_read_b32 v146, a186 + v_accvgpr_read_b32 v147, a187 + v_accvgpr_read_b32 v148, a188 + v_accvgpr_read_b32 v149, a189 + v_accvgpr_read_b32 v150, a190 + v_accvgpr_read_b32 v151, a191 + v_accvgpr_read_b32 v120, a192 + v_accvgpr_read_b32 v121, a193 + v_accvgpr_read_b32 v122, a194 + v_accvgpr_read_b32 v123, a195 + v_accvgpr_read_b32 v124, a196 + v_accvgpr_read_b32 v125, a197 + v_accvgpr_read_b32 v126, a198 + v_accvgpr_read_b32 v127, a199 + v_accvgpr_read_b32 v128, a200 + v_accvgpr_read_b32 v129, a201 + v_accvgpr_read_b32 v130, a202 + v_accvgpr_read_b32 v131, a203 + v_accvgpr_read_b32 v132, a204 + v_accvgpr_read_b32 v133, a205 + v_accvgpr_read_b32 v134, a206 + v_accvgpr_read_b32 v135, a207 + v_accvgpr_read_b32 v104, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v106, a210 + v_accvgpr_read_b32 v107, a211 + v_accvgpr_read_b32 v108, a212 + v_accvgpr_read_b32 v109, a213 + v_accvgpr_read_b32 v110, a214 + v_accvgpr_read_b32 v111, a215 + v_accvgpr_read_b32 v112, a216 + v_accvgpr_read_b32 v113, a217 + v_accvgpr_read_b32 v114, a218 + v_accvgpr_read_b32 v115, a219 + v_accvgpr_read_b32 v116, a220 + v_accvgpr_read_b32 v117, a221 + v_accvgpr_read_b32 v118, a222 + v_accvgpr_read_b32 v119, a223 + v_accvgpr_read_b32 v50, a224 + v_accvgpr_read_b32 v51, a225 + v_accvgpr_read_b32 v52, a226 + v_accvgpr_read_b32 v53, a227 + v_accvgpr_read_b32 v54, a228 + v_accvgpr_read_b32 v55, a229 + v_accvgpr_read_b32 v56, a230 + v_accvgpr_read_b32 v57, a231 + v_accvgpr_read_b32 v58, a232 + v_accvgpr_read_b32 v59, a233 + v_accvgpr_read_b32 v60, a234 + v_accvgpr_read_b32 v61, a235 + v_accvgpr_read_b32 v62, a236 + v_accvgpr_read_b32 v63, a237 + v_accvgpr_read_b32 v64, a238 + v_accvgpr_read_b32 v65, a239 + v_accvgpr_read_b32 v34, a240 + v_accvgpr_read_b32 v35, a241 + v_accvgpr_read_b32 v36, a242 + v_accvgpr_read_b32 v37, a243 + v_accvgpr_read_b32 v38, a244 + v_accvgpr_read_b32 v39, a245 + v_accvgpr_read_b32 v40, a246 + v_accvgpr_read_b32 v41, a247 + v_accvgpr_read_b32 v42, a248 + v_accvgpr_read_b32 v43, a249 + v_accvgpr_read_b32 v44, a250 + v_accvgpr_read_b32 v45, a251 + v_accvgpr_read_b32 v46, a252 + v_accvgpr_read_b32 v47, a253 + v_accvgpr_read_b32 v48, a254 + v_accvgpr_read_b32 v49, a255 + v_accvgpr_read_b32 v18, a0 + v_accvgpr_read_b32 v19, a1 + v_accvgpr_read_b32 v20, a2 + v_accvgpr_read_b32 v21, a3 + v_accvgpr_read_b32 v22, a4 + v_accvgpr_read_b32 v23, a5 + v_accvgpr_read_b32 v24, a6 + v_accvgpr_read_b32 v25, a7 + v_accvgpr_read_b32 v26, a8 + v_accvgpr_read_b32 v27, a9 + v_accvgpr_read_b32 v28, a10 + v_accvgpr_read_b32 v29, a11 + v_accvgpr_read_b32 v30, a12 + v_accvgpr_read_b32 v31, a13 + v_accvgpr_read_b32 v32, a14 + v_accvgpr_read_b32 v33, a15 + v_accvgpr_read_b32 v2, a32 + v_accvgpr_read_b32 v3, a33 + v_accvgpr_read_b32 v4, a34 + v_accvgpr_read_b32 v5, a35 + v_accvgpr_read_b32 v6, a36 + v_accvgpr_read_b32 v7, a37 + v_accvgpr_read_b32 v8, a38 + v_accvgpr_read_b32 v9, a39 + v_accvgpr_read_b32 v10, a40 + v_accvgpr_read_b32 v11, a41 + v_accvgpr_read_b32 v12, a42 + v_accvgpr_read_b32 v13, a43 + v_accvgpr_read_b32 v14, a44 + v_accvgpr_read_b32 v15, a45 + v_accvgpr_read_b32 v16, a46 + v_accvgpr_read_b32 v17, a47 + v_accvgpr_mov_b32 a0, a16 + v_accvgpr_mov_b32 a1, a17 + v_accvgpr_mov_b32 a2, a18 + v_accvgpr_mov_b32 a3, a19 + v_accvgpr_mov_b32 a4, a20 + v_accvgpr_mov_b32 a5, a21 + v_accvgpr_mov_b32 a6, a22 + v_accvgpr_mov_b32 a7, a23 + v_accvgpr_mov_b32 a8, a24 + v_accvgpr_mov_b32 a9, a25 + v_accvgpr_mov_b32 a10, a26 + v_accvgpr_mov_b32 a11, a27 + v_accvgpr_mov_b32 a12, a28 + v_accvgpr_mov_b32 a13, a29 + v_accvgpr_mov_b32 a14, a30 + v_accvgpr_mov_b32 a15, a31 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[168:171], v103 + ds_read_b128 v[172:175], v102 offset:32768 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[168:169], v[172:173], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[170:171], v[174:175], a[96:111] + v_lshlrev_b32_e32 v66, 1, v96 + ds_read_b128 v[176:179], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v97 + v_accvgpr_mov_b32 a159, a95 + v_accvgpr_mov_b32 a158, a94 + v_accvgpr_mov_b32 a157, a93 + v_accvgpr_mov_b32 a156, a92 + v_accvgpr_mov_b32 a155, a91 + v_accvgpr_mov_b32 a154, a90 + v_accvgpr_mov_b32 a153, a89 + v_accvgpr_mov_b32 a152, a88 + v_accvgpr_mov_b32 a151, a87 + v_accvgpr_mov_b32 a150, a86 + v_accvgpr_mov_b32 a149, a85 + v_accvgpr_mov_b32 a148, a84 + v_accvgpr_mov_b32 a147, a83 + v_accvgpr_mov_b32 a146, a82 + v_accvgpr_mov_b32 a145, a81 + v_accvgpr_mov_b32 a144, a80 + ds_read_b128 v[180:183], v66 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[144:159], v[168:169], v[176:177], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[170:171], v[178:179], a[144:159] + v_lshlrev_b32_e32 v66, 1, v98 + ds_read_b128 v[184:187], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v99 + ds_read_b128 v[96:99], v66 offset:32768 + v_accvgpr_mov_b32 a191, a79 + v_accvgpr_mov_b32 a190, a78 + v_accvgpr_mov_b32 a189, a77 + v_accvgpr_mov_b32 a188, a76 + v_accvgpr_mov_b32 a187, a75 + v_accvgpr_mov_b32 a186, a74 + v_accvgpr_mov_b32 a185, a73 + v_accvgpr_mov_b32 a184, a72 + v_accvgpr_mov_b32 a183, a71 + v_accvgpr_mov_b32 a182, a70 + v_accvgpr_mov_b32 a181, a69 + v_accvgpr_mov_b32 a180, a68 + v_accvgpr_mov_b32 a179, a67 + v_accvgpr_mov_b32 a178, a66 + v_accvgpr_mov_b32 a177, a65 + v_accvgpr_mov_b32 a176, a64 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[176:191], v[168:169], v[184:185], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[170:171], v[186:187], a[176:191] + v_lshlrev_b32_e32 v66, 1, v100 + ds_read_b128 v[188:191], v66 offset:32768 + v_lshlrev_b32_e32 v66, 1, v101 + ds_read_b128 v[100:103], v66 offset:32768 + v_accvgpr_mov_b32 a223, a143 + v_accvgpr_mov_b32 a222, a142 + v_accvgpr_mov_b32 a221, a141 + v_accvgpr_mov_b32 a220, a140 + v_accvgpr_mov_b32 a219, a139 + v_accvgpr_mov_b32 a218, a138 + v_accvgpr_mov_b32 a217, a137 + v_accvgpr_mov_b32 a216, a136 + v_accvgpr_mov_b32 a215, a135 + v_accvgpr_mov_b32 a214, a134 + v_accvgpr_mov_b32 a213, a133 + v_accvgpr_mov_b32 a212, a132 + v_accvgpr_mov_b32 a211, a131 + v_accvgpr_mov_b32 a210, a130 + v_accvgpr_mov_b32 a209, a129 + v_accvgpr_mov_b32 a208, a128 + s_waitcnt lgkmcnt(1) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[208:223], v[168:169], v[188:189], a[208:223] + v_lshlrev_b32_e32 v66, 1, v95 + v_mfma_f32_32x32x8_bf16 a[208:223], v[170:171], v[190:191], a[208:223] + ds_read_b128 v[168:171], v66 + v_accvgpr_mov_b32 a239, a127 + v_accvgpr_mov_b32 a238, a126 + v_accvgpr_mov_b32 a237, a125 + v_accvgpr_mov_b32 a236, a124 + v_accvgpr_mov_b32 a235, a123 + v_accvgpr_mov_b32 a234, a122 + v_accvgpr_mov_b32 a233, a121 + v_accvgpr_mov_b32 a232, a120 + v_accvgpr_mov_b32 a231, a119 + v_accvgpr_mov_b32 a230, a118 + v_accvgpr_mov_b32 a229, a117 + v_accvgpr_mov_b32 a228, a116 + v_accvgpr_mov_b32 a227, a115 + v_accvgpr_mov_b32 a226, a114 + v_accvgpr_mov_b32 a225, a113 + v_accvgpr_mov_b32 a224, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[224:239], v[168:169], v[172:173], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[170:171], v[174:175], a[224:239] + v_accvgpr_write_b32 a207, v167 + v_accvgpr_write_b32 a206, v166 + v_accvgpr_write_b32 a205, v165 + v_accvgpr_write_b32 a204, v164 + v_accvgpr_write_b32 a203, v163 + v_accvgpr_write_b32 a202, v162 + v_accvgpr_write_b32 a201, v161 + v_accvgpr_write_b32 a200, v160 + v_accvgpr_write_b32 a199, v159 + v_accvgpr_write_b32 a198, v158 + v_accvgpr_write_b32 a197, v157 + v_accvgpr_write_b32 a196, v156 + v_accvgpr_write_b32 a195, v155 + v_accvgpr_write_b32 a194, v154 + v_accvgpr_write_b32 a193, v153 + v_accvgpr_write_b32 a192, v152 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[192:207], v[168:169], v[176:177], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[170:171], v[178:179], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[168:169], v[184:185], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[170:171], v[186:187], a[160:175] + v_accvgpr_write_b32 a128, v136 + v_accvgpr_write_b32 a129, v137 + v_accvgpr_write_b32 a130, v138 + v_accvgpr_write_b32 a131, v139 + v_accvgpr_write_b32 a132, v140 + v_accvgpr_write_b32 a133, v141 + v_accvgpr_write_b32 a134, v142 + v_accvgpr_write_b32 a135, v143 + v_accvgpr_write_b32 a136, v144 + v_accvgpr_write_b32 a137, v145 + v_accvgpr_write_b32 a138, v146 + v_accvgpr_write_b32 a139, v147 + v_accvgpr_write_b32 a140, v148 + v_accvgpr_write_b32 a141, v149 + v_accvgpr_write_b32 a142, v150 + v_accvgpr_write_b32 a143, v151 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[128:143], v[168:169], v[188:189], a[128:143] + v_lshlrev_b32_e32 v66, 1, v94 + v_mfma_f32_32x32x8_bf16 a[128:143], v[170:171], v[190:191], a[128:143] + ds_read_b128 v[136:139], v66 + v_accvgpr_write_b32 a112, v120 + v_accvgpr_write_b32 a113, v121 + v_accvgpr_write_b32 a114, v122 + v_accvgpr_write_b32 a115, v123 + v_accvgpr_write_b32 a116, v124 + v_accvgpr_write_b32 a117, v125 + v_accvgpr_write_b32 a118, v126 + v_accvgpr_write_b32 a119, v127 + v_accvgpr_write_b32 a120, v128 + v_accvgpr_write_b32 a121, v129 + v_accvgpr_write_b32 a122, v130 + v_accvgpr_write_b32 a123, v131 + v_accvgpr_write_b32 a124, v132 + v_accvgpr_write_b32 a125, v133 + v_accvgpr_write_b32 a126, v134 + v_accvgpr_write_b32 a127, v135 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[112:127], v[136:137], v[172:173], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[138:139], v[174:175], a[112:127] + v_accvgpr_write_b32 a80, v104 + v_accvgpr_write_b32 a81, v105 + v_accvgpr_write_b32 a82, v106 + v_accvgpr_write_b32 a83, v107 + v_accvgpr_write_b32 a84, v108 + v_accvgpr_write_b32 a85, v109 + v_accvgpr_write_b32 a86, v110 + v_accvgpr_write_b32 a87, v111 + v_accvgpr_write_b32 a88, v112 + v_accvgpr_write_b32 a89, v113 + v_accvgpr_write_b32 a90, v114 + v_accvgpr_write_b32 a91, v115 + v_accvgpr_write_b32 a92, v116 + v_accvgpr_write_b32 a93, v117 + v_accvgpr_write_b32 a94, v118 + v_accvgpr_write_b32 a95, v119 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[80:95], v[136:137], v[176:177], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[138:139], v[178:179], a[80:95] + v_accvgpr_write_b32 a79, v65 + v_accvgpr_write_b32 a78, v64 + v_accvgpr_write_b32 a77, v63 + v_accvgpr_write_b32 a76, v62 + v_accvgpr_write_b32 a75, v61 + v_accvgpr_write_b32 a74, v60 + v_accvgpr_write_b32 a73, v59 + v_accvgpr_write_b32 a72, v58 + v_accvgpr_write_b32 a71, v57 + v_accvgpr_write_b32 a70, v56 + v_accvgpr_write_b32 a69, v55 + v_accvgpr_write_b32 a68, v54 + v_accvgpr_write_b32 a67, v53 + v_accvgpr_write_b32 a66, v52 + v_accvgpr_write_b32 a65, v51 + v_accvgpr_write_b32 a64, v50 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[64:79], v[136:137], v[184:185], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[138:139], v[186:187], a[64:79] + v_accvgpr_write_b32 a63, v49 + v_accvgpr_write_b32 a62, v48 + v_accvgpr_write_b32 a61, v47 + v_accvgpr_write_b32 a60, v46 + v_accvgpr_write_b32 a59, v45 + v_accvgpr_write_b32 a58, v44 + v_accvgpr_write_b32 a57, v43 + v_accvgpr_write_b32 a56, v42 + v_accvgpr_write_b32 a55, v41 + v_accvgpr_write_b32 a54, v40 + v_accvgpr_write_b32 a53, v39 + v_accvgpr_write_b32 a52, v38 + v_accvgpr_write_b32 a51, v37 + v_accvgpr_write_b32 a50, v36 + v_accvgpr_write_b32 a49, v35 + v_accvgpr_write_b32 a48, v34 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[48:63], v[136:137], v[188:189], a[48:63] + v_lshlrev_b32_e32 v34, 1, v91 + v_mfma_f32_32x32x8_bf16 a[48:63], v[138:139], v[190:191], a[48:63] + ds_read_b128 v[34:37], v34 + v_accvgpr_write_b32 a47, v33 + v_accvgpr_write_b32 a46, v32 + v_accvgpr_write_b32 a45, v31 + v_accvgpr_write_b32 a44, v30 + v_accvgpr_write_b32 a43, v29 + v_accvgpr_write_b32 a42, v28 + v_accvgpr_write_b32 a41, v27 + v_accvgpr_write_b32 a40, v26 + v_accvgpr_write_b32 a39, v25 + v_accvgpr_write_b32 a38, v24 + v_accvgpr_write_b32 a37, v23 + v_accvgpr_write_b32 a36, v22 + v_accvgpr_write_b32 a35, v21 + v_accvgpr_write_b32 a34, v20 + v_accvgpr_write_b32 a33, v19 + v_accvgpr_write_b32 a32, v18 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x8_bf16 a[32:47], v[34:35], v[172:173], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[36:37], v[174:175], a[32:47] + v_accvgpr_write_b32 a31, v17 + v_accvgpr_write_b32 a30, v16 + v_accvgpr_write_b32 a29, v15 + v_accvgpr_write_b32 a28, v14 + v_accvgpr_write_b32 a27, v13 + v_accvgpr_write_b32 a26, v12 + v_accvgpr_write_b32 a25, v11 + v_accvgpr_write_b32 a24, v10 + v_accvgpr_write_b32 a23, v9 + v_accvgpr_write_b32 a22, v8 + v_accvgpr_write_b32 a21, v7 + v_accvgpr_write_b32 a20, v6 + v_accvgpr_write_b32 a19, v5 + v_accvgpr_write_b32 a18, v4 + v_accvgpr_write_b32 a17, v3 + v_accvgpr_write_b32 a16, v2 + s_nop 1 + v_mfma_f32_32x32x8_bf16 a[16:31], v[34:35], v[176:177], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[36:37], v[178:179], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[34:35], v[184:185], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[36:37], v[186:187], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[34:35], v[188:189], a[240:255] + v_lshlrev_b32_e32 v2, 1, v78 + v_mfma_f32_32x32x8_bf16 a[240:255], v[36:37], v[190:191], a[240:255] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v86 + ds_read_b128 v[8:11], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v79 + ds_read_b128 v[12:15], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[6:7], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[180:181], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[6:7], v[182:183], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[96:97], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[6:7], v[98:99], a[176:191] + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[100:101], a[208:223] + v_lshlrev_b32_e32 v2, 1, v80 + v_mfma_f32_32x32x8_bf16 a[208:223], v[6:7], v[102:103], a[208:223] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v83 + ds_read_b128 v[16:19], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[6:7], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[180:181], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[6:7], v[182:183], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[96:97], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[6:7], v[98:99], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[100:101], a[128:143] + v_lshlrev_b32_e32 v2, 1, v81 + v_mfma_f32_32x32x8_bf16 a[128:143], v[6:7], v[102:103], a[128:143] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v82 + ds_read_b128 v[20:23], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[8:9], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[6:7], v[10:11], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[180:181], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[6:7], v[182:183], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[96:97], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[6:7], v[98:99], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[100:101], a[48:63] + v_lshlrev_b32_e32 v2, 1, v76 + v_mfma_f32_32x32x8_bf16 a[48:63], v[6:7], v[102:103], a[48:63] + ds_read_b128 v[4:7], v2 + v_lshlrev_b32_e32 v2, 1, v77 + ds_read_b128 v[24:27], v2 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[8:9], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[6:7], v[10:11], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[180:181], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[6:7], v[182:183], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[96:97], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[6:7], v[98:99], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[100:101], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[6:7], v[102:103], a[240:255] + v_lshlrev_b32_e32 v2, 1, v84 + ds_read_b128 v[4:7], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v85 + ds_read_b128 v[8:11], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[96:111], v[12:13], v[4:5], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[14:15], v[6:7], a[96:111] + v_lshlrev_b32_e32 v2, 1, v87 + ds_read_b128 v[28:31], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v88 + ds_read_b128 v[32:35], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[144:159], v[12:13], v[28:29], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[14:15], v[30:31], a[144:159] + v_lshlrev_b32_e32 v2, 1, v89 + ds_read_b128 v[36:39], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v90 + ds_read_b128 v[40:43], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[176:191], v[12:13], v[36:37], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[14:15], v[38:39], a[176:191] + v_lshlrev_b32_e32 v2, 1, v92 + ds_read_b128 v[44:47], v2 offset:32768 + v_lshlrev_b32_e32 v2, 1, v93 + ds_read_b128 v[48:51], v2 offset:32768 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x8_bf16 a[208:223], v[12:13], v[44:45], a[208:223] + v_mfma_f32_32x32x8_bf16 a[208:223], v[14:15], v[46:47], a[208:223] + v_mfma_f32_32x32x8_bf16 a[224:239], v[16:17], v[4:5], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[18:19], v[6:7], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[16:17], v[28:29], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[18:19], v[30:31], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[16:17], v[36:37], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[18:19], v[38:39], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[16:17], v[44:45], a[128:143] + v_mfma_f32_32x32x8_bf16 a[128:143], v[18:19], v[46:47], a[128:143] + v_mfma_f32_32x32x8_bf16 a[112:127], v[20:21], v[4:5], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[22:23], v[6:7], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[20:21], v[28:29], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[22:23], v[30:31], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[20:21], v[36:37], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[22:23], v[38:39], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[20:21], v[44:45], a[48:63] + v_mfma_f32_32x32x8_bf16 a[48:63], v[22:23], v[46:47], a[48:63] + v_mfma_f32_32x32x8_bf16 a[32:47], v[24:25], v[4:5], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[26:27], v[6:7], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[24:25], v[28:29], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[26:27], v[30:31], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[24:25], v[36:37], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[26:27], v[38:39], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[24:25], v[44:45], a[240:255] + v_lshlrev_b32_e32 v2, 1, v69 + v_mfma_f32_32x32x8_bf16 a[240:255], v[26:27], v[46:47], a[240:255] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_f32_32x32x8_bf16 a[96:111], v[4:5], v[10:11], a[96:111] + v_mfma_f32_32x32x8_bf16 a[144:159], v[2:3], v[32:33], a[144:159] + v_mfma_f32_32x32x8_bf16 a[144:159], v[4:5], v[34:35], a[144:159] + v_mfma_f32_32x32x8_bf16 a[176:191], v[2:3], v[40:41], a[176:191] + v_mfma_f32_32x32x8_bf16 a[176:191], v[4:5], v[42:43], a[176:191] + v_mfma_f32_32x32x8_bf16 a[208:223], v[2:3], v[48:49], a[208:223] + v_lshlrev_b32_e32 v2, 1, v75 + v_mfma_f32_32x32x8_bf16 a[208:223], v[4:5], v[50:51], a[208:223] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[224:239], v[2:3], v[8:9], a[224:239] + v_mfma_f32_32x32x8_bf16 a[224:239], v[4:5], v[10:11], a[224:239] + v_mfma_f32_32x32x8_bf16 a[192:207], v[2:3], v[32:33], a[192:207] + v_mfma_f32_32x32x8_bf16 a[192:207], v[4:5], v[34:35], a[192:207] + v_mfma_f32_32x32x8_bf16 a[160:175], v[2:3], v[40:41], a[160:175] + v_mfma_f32_32x32x8_bf16 a[160:175], v[4:5], v[42:43], a[160:175] + v_mfma_f32_32x32x8_bf16 a[128:143], v[2:3], v[48:49], a[128:143] + v_lshlrev_b32_e32 v2, 1, v74 + v_mfma_f32_32x32x8_bf16 a[128:143], v[4:5], v[50:51], a[128:143] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[112:127], v[2:3], v[8:9], a[112:127] + v_mfma_f32_32x32x8_bf16 a[112:127], v[4:5], v[10:11], a[112:127] + v_mfma_f32_32x32x8_bf16 a[80:95], v[2:3], v[32:33], a[80:95] + v_mfma_f32_32x32x8_bf16 a[80:95], v[4:5], v[34:35], a[80:95] + v_mfma_f32_32x32x8_bf16 a[64:79], v[2:3], v[40:41], a[64:79] + v_mfma_f32_32x32x8_bf16 a[64:79], v[4:5], v[42:43], a[64:79] + v_mfma_f32_32x32x8_bf16 a[48:63], v[2:3], v[48:49], a[48:63] + v_lshlrev_b32_e32 v2, 1, v71 + v_mfma_f32_32x32x8_bf16 a[48:63], v[4:5], v[50:51], a[48:63] + ds_read_b128 v[2:5], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_bf16 a[32:47], v[2:3], v[8:9], a[32:47] + v_mfma_f32_32x32x8_bf16 a[32:47], v[4:5], v[10:11], a[32:47] + v_mfma_f32_32x32x8_bf16 a[16:31], v[2:3], v[32:33], a[16:31] + v_mfma_f32_32x32x8_bf16 a[16:31], v[4:5], v[34:35], a[16:31] + v_mfma_f32_32x32x8_bf16 a[0:15], v[2:3], v[40:41], a[0:15] + v_mfma_f32_32x32x8_bf16 a[0:15], v[4:5], v[42:43], a[0:15] + v_mfma_f32_32x32x8_bf16 a[240:255], v[2:3], v[48:49], a[240:255] + v_mfma_f32_32x32x8_bf16 a[240:255], v[4:5], v[50:51], a[240:255] +.LBB15_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEDF16bNS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi8ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDaR + v_accvgpr_read_b32 v73, a96 + v_accvgpr_read_b32 v72, a97 + v_accvgpr_read_b32 v71, a98 + v_accvgpr_read_b32 v70, a99 + v_accvgpr_read_b32 v69, a100 + v_accvgpr_read_b32 v68, a101 + v_accvgpr_read_b32 v66, a102 + v_accvgpr_read_b32 v65, a103 + v_accvgpr_read_b32 v64, a104 + v_accvgpr_read_b32 v63, a105 + v_accvgpr_read_b32 v62, a106 + v_accvgpr_read_b32 v61, a107 + v_accvgpr_read_b32 v60, a108 + v_accvgpr_read_b32 v59, a109 + v_accvgpr_read_b32 v58, a110 + v_accvgpr_read_b32 v56, a111 + v_accvgpr_read_b32 v252, a144 + v_accvgpr_read_b32 v251, a145 + v_accvgpr_read_b32 v250, a146 + v_accvgpr_read_b32 v249, a147 + v_accvgpr_read_b32 v248, a148 + v_accvgpr_read_b32 v247, a149 + v_accvgpr_read_b32 v246, a150 + v_accvgpr_read_b32 v245, a151 + v_accvgpr_read_b32 v244, a152 + v_accvgpr_read_b32 v243, a153 + v_accvgpr_read_b32 v242, a154 + v_accvgpr_read_b32 v241, a155 + v_accvgpr_read_b32 v240, a156 + v_accvgpr_read_b32 v239, a157 + v_accvgpr_read_b32 v238, a158 + v_accvgpr_read_b32 v236, a159 + v_accvgpr_read_b32 v220, a176 + v_accvgpr_read_b32 v219, a177 + v_accvgpr_read_b32 v218, a178 + v_accvgpr_read_b32 v217, a179 + v_accvgpr_read_b32 v216, a180 + v_accvgpr_read_b32 v215, a181 + v_accvgpr_read_b32 v214, a182 + v_accvgpr_read_b32 v213, a183 + v_accvgpr_read_b32 v212, a184 + v_accvgpr_read_b32 v211, a185 + v_accvgpr_read_b32 v210, a186 + v_accvgpr_read_b32 v209, a187 + v_accvgpr_read_b32 v208, a188 + v_accvgpr_read_b32 v207, a189 + v_accvgpr_read_b32 v206, a190 + v_accvgpr_read_b32 v204, a191 + v_accvgpr_read_b32 v188, a208 + v_accvgpr_read_b32 v187, a209 + v_accvgpr_read_b32 v186, a210 + v_accvgpr_read_b32 v185, a211 + v_accvgpr_read_b32 v184, a212 + v_accvgpr_read_b32 v183, a213 + v_accvgpr_read_b32 v182, a214 + v_accvgpr_read_b32 v181, a215 + v_accvgpr_read_b32 v180, a216 + v_accvgpr_read_b32 v179, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v177, a219 + v_accvgpr_read_b32 v176, a220 + v_accvgpr_read_b32 v175, a221 + v_accvgpr_read_b32 v174, a222 + v_accvgpr_read_b32 v172, a223 + v_accvgpr_read_b32 v57, a224 + v_accvgpr_read_b32 v55, a225 + v_accvgpr_read_b32 v54, a226 + v_accvgpr_read_b32 v53, a227 + v_accvgpr_read_b32 v52, a228 + v_accvgpr_read_b32 v51, a229 + v_accvgpr_read_b32 v50, a230 + v_accvgpr_read_b32 v49, a231 + v_accvgpr_read_b32 v48, a232 + v_accvgpr_read_b32 v47, a233 + v_accvgpr_read_b32 v46, a234 + v_accvgpr_read_b32 v45, a235 + v_accvgpr_read_b32 v44, a236 + v_accvgpr_read_b32 v255, a237 + v_accvgpr_read_b32 v254, a238 + v_accvgpr_read_b32 v253, a239 + v_accvgpr_read_b32 v237, a192 + v_accvgpr_read_b32 v235, a193 + v_accvgpr_read_b32 v234, a194 + v_accvgpr_read_b32 v233, a195 + v_accvgpr_read_b32 v232, a196 + v_accvgpr_read_b32 v231, a197 + v_accvgpr_read_b32 v230, a198 + v_accvgpr_read_b32 v229, a199 + v_accvgpr_read_b32 v228, a200 + v_accvgpr_read_b32 v227, a201 + v_accvgpr_read_b32 v226, a202 + v_accvgpr_read_b32 v225, a203 + v_accvgpr_read_b32 v224, a204 + v_accvgpr_read_b32 v223, a205 + v_accvgpr_read_b32 v222, a206 + v_accvgpr_read_b32 v221, a207 + v_accvgpr_read_b32 v205, a160 + v_accvgpr_read_b32 v203, a161 + v_accvgpr_read_b32 v202, a162 + v_accvgpr_read_b32 v201, a163 + v_accvgpr_read_b32 v200, a164 + v_accvgpr_read_b32 v199, a165 + v_accvgpr_read_b32 v198, a166 + v_accvgpr_read_b32 v197, a167 + v_accvgpr_read_b32 v196, a168 + v_accvgpr_read_b32 v195, a169 + v_accvgpr_read_b32 v194, a170 + v_accvgpr_read_b32 v193, a171 + v_accvgpr_read_b32 v192, a172 + v_accvgpr_read_b32 v191, a173 + v_accvgpr_read_b32 v190, a174 + v_accvgpr_read_b32 v189, a175 + v_accvgpr_read_b32 v173, a128 + v_accvgpr_read_b32 v171, a129 + v_accvgpr_read_b32 v170, a130 + v_accvgpr_read_b32 v169, a131 + v_accvgpr_read_b32 v168, a132 + v_accvgpr_read_b32 v167, a133 + v_accvgpr_read_b32 v166, a134 + v_accvgpr_read_b32 v165, a135 + v_accvgpr_read_b32 v164, a136 + v_accvgpr_read_b32 v163, a137 + v_accvgpr_read_b32 v162, a138 + v_accvgpr_read_b32 v161, a139 + v_accvgpr_read_b32 v160, a140 + v_accvgpr_read_b32 v159, a141 + v_accvgpr_read_b32 v158, a142 + v_accvgpr_read_b32 v157, a143 + v_accvgpr_mov_b32 a111, a112 + v_accvgpr_mov_b32 a110, a113 + v_accvgpr_mov_b32 a109, a114 + v_accvgpr_mov_b32 a108, a115 + v_accvgpr_mov_b32 a107, a116 + v_accvgpr_mov_b32 a106, a117 + v_accvgpr_mov_b32 a105, a118 + v_accvgpr_mov_b32 a104, a119 + v_accvgpr_mov_b32 a103, a120 + v_accvgpr_mov_b32 a102, a121 + v_accvgpr_mov_b32 a101, a122 + v_accvgpr_mov_b32 a100, a123 + v_accvgpr_mov_b32 a99, a124 + v_accvgpr_mov_b32 a98, a125 + v_accvgpr_mov_b32 a97, a126 + v_accvgpr_mov_b32 a96, a127 + v_accvgpr_read_b32 v108, a80 + v_accvgpr_read_b32 v107, a81 + v_accvgpr_read_b32 v106, a82 + v_accvgpr_read_b32 v105, a83 + v_accvgpr_read_b32 v104, a84 + v_accvgpr_read_b32 v103, a85 + v_accvgpr_read_b32 v102, a86 + v_accvgpr_read_b32 v101, a87 + v_accvgpr_read_b32 v100, a88 + v_accvgpr_read_b32 v99, a89 + v_accvgpr_read_b32 v98, a90 + v_accvgpr_read_b32 v97, a91 + v_accvgpr_read_b32 v96, a92 + v_accvgpr_read_b32 v95, a93 + v_accvgpr_read_b32 v94, a94 + v_accvgpr_read_b32 v92, a95 + v_accvgpr_read_b32 v140, a64 + v_accvgpr_read_b32 v139, a65 + v_accvgpr_read_b32 v138, a66 + v_accvgpr_read_b32 v137, a67 + v_accvgpr_read_b32 v136, a68 + v_accvgpr_read_b32 v135, a69 + v_accvgpr_read_b32 v134, a70 + v_accvgpr_read_b32 v133, a71 + v_accvgpr_read_b32 v132, a72 + v_accvgpr_read_b32 v131, a73 + v_accvgpr_read_b32 v130, a74 + v_accvgpr_read_b32 v129, a75 + v_accvgpr_read_b32 v128, a76 + v_accvgpr_read_b32 v127, a77 + v_accvgpr_read_b32 v126, a78 + v_accvgpr_read_b32 v124, a79 + v_accvgpr_read_b32 v156, a48 + v_accvgpr_read_b32 v155, a49 + v_accvgpr_read_b32 v154, a50 + v_accvgpr_read_b32 v153, a51 + v_accvgpr_read_b32 v152, a52 + v_accvgpr_read_b32 v151, a53 + v_accvgpr_read_b32 v150, a54 + v_accvgpr_read_b32 v149, a55 + v_accvgpr_read_b32 v148, a56 + v_accvgpr_read_b32 v147, a57 + v_accvgpr_read_b32 v146, a58 + v_accvgpr_read_b32 v145, a59 + v_accvgpr_read_b32 v144, a60 + v_accvgpr_read_b32 v143, a61 + v_accvgpr_read_b32 v142, a62 + v_accvgpr_read_b32 v141, a63 + v_accvgpr_mov_b32 a54, a32 + v_accvgpr_mov_b32 a53, a33 + v_accvgpr_mov_b32 a52, a34 + v_accvgpr_mov_b32 a51, a35 + v_accvgpr_mov_b32 a50, a36 + v_accvgpr_mov_b32 a49, a37 + v_accvgpr_mov_b32 a48, a38 + v_accvgpr_mov_b32 a38, a40 + v_accvgpr_mov_b32 a37, a41 + v_accvgpr_mov_b32 a36, a42 + v_accvgpr_mov_b32 a35, a43 + v_accvgpr_mov_b32 a34, a44 + v_accvgpr_mov_b32 a33, a45 + v_accvgpr_mov_b32 a32, a46 + v_accvgpr_read_b32 v86, a47 + v_accvgpr_read_b32 v93, a16 + v_accvgpr_read_b32 v91, a17 + v_accvgpr_read_b32 v90, a18 + v_accvgpr_read_b32 v89, a19 + v_accvgpr_read_b32 v88, a20 + v_accvgpr_mov_b32 a41, a21 + v_accvgpr_mov_b32 a40, a22 + v_accvgpr_mov_b32 a22, a24 + v_accvgpr_mov_b32 a21, a25 + v_accvgpr_mov_b32 a20, a26 + v_accvgpr_mov_b32 a19, a27 + v_accvgpr_mov_b32 a18, a28 + v_accvgpr_mov_b32 a17, a29 + v_accvgpr_read_b32 v87, a30 + v_accvgpr_mov_b32 a16, a31 + v_accvgpr_read_b32 v125, a0 + v_accvgpr_read_b32 v123, a1 + v_accvgpr_read_b32 v122, a2 + v_accvgpr_read_b32 v121, a3 + v_accvgpr_read_b32 v120, a4 + v_accvgpr_read_b32 v119, a5 + v_accvgpr_read_b32 v118, a6 + v_accvgpr_read_b32 v117, a7 + v_accvgpr_read_b32 v116, a8 + v_accvgpr_read_b32 v115, a9 + v_accvgpr_read_b32 v114, a10 + v_accvgpr_read_b32 v113, a11 + v_accvgpr_read_b32 v112, a12 + v_accvgpr_read_b32 v111, a13 + v_accvgpr_read_b32 v110, a14 + v_accvgpr_read_b32 v109, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mov_b64 s[2:3], -1 + s_cmp_lg_u32 s17, 1 + s_cbranch_scc1 .LBB15_13 +; %bb.11: ; %Flow1293 + s_and_b64 vcc, exec, s[2:3] + s_cbranch_vccnz .LBB15_2190 +.LBB15_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESE_SE_Li1EEEDF16bNS_12element_wise11PassThroughESH_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSO_SE_SH_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB15_13: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.14: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 +; %bb.15: ; %Flow1036 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.16: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.17: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i304.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.18: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v19, v72, v19, s7 +; %bb.19: ; %Flow1035 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.20: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v72, vcc +; %bb.21: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i307.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.22: + v_bfe_u32 v20, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v71, v20, s7 +; %bb.23: ; %Flow1034 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.24: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v71, vcc +; %bb.25: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i310.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.26: + v_bfe_u32 v21, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v70, v21, s7 +; %bb.27: ; %Flow1033 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.28: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v70, vcc +; %bb.29: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i313.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v69 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.30: + v_bfe_u32 v22, v69, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v69, v22, s7 +; %bb.31: ; %Flow1032 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.32: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v69 + v_cmp_eq_u32_sdwa vcc, v69, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v69, vcc +; %bb.33: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i316.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.34: + v_bfe_u32 v23, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v68, v23, s7 +; %bb.35: ; %Flow1031 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.36: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v68, vcc +; %bb.37: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i319.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.38: + v_bfe_u32 v24, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v66, v24, s7 +; %bb.39: ; %Flow1030 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.40: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v66, vcc +; %bb.41: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i322.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.42: + v_bfe_u32 v25, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v65, v25, s7 +; %bb.43: ; %Flow1029 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.44: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v65, vcc +; %bb.45: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i325.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.46: + v_bfe_u32 v26, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v64, v26, s7 +; %bb.47: ; %Flow1028 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.48: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v64, vcc +; %bb.49: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i328.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.50: + v_bfe_u32 v27, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v63, v27, s7 +; %bb.51: ; %Flow1027 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.52: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v63, vcc +; %bb.53: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i331.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.54: + v_bfe_u32 v28, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v62, v28, s7 +; %bb.55: ; %Flow1026 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.56: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v62, vcc +; %bb.57: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i334.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.58: + v_bfe_u32 v29, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v61, v29, s7 +; %bb.59: ; %Flow1025 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.60: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v61, vcc +; %bb.61: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i337.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.62: + v_bfe_u32 v30, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v60, v30, s7 +; %bb.63: ; %Flow1024 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.64: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v60, vcc +; %bb.65: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i340.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.66: + v_bfe_u32 v31, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v59, v31, s7 +; %bb.67: ; %Flow1023 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.68: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v59, vcc +; %bb.69: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i343.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.70: + v_bfe_u32 v32, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v58, v32, s7 +; %bb.71: ; %Flow1022 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.72: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v58, vcc +; %bb.73: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i346.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.74: + v_bfe_u32 v33, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v56, v33, s7 +; %bb.75: ; %Flow1021 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.76: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v56, vcc +; %bb.77: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i349.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.78: + v_bfe_u32 v34, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v57, v34, s7 +; %bb.79: ; %Flow1020 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.80: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v57, vcc +; %bb.81: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i352.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.82: + v_bfe_u32 v35, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v55, v35, s7 +; %bb.83: ; %Flow1019 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.84: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v55, vcc +; %bb.85: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i355.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.86: + v_bfe_u32 v36, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v54, v36, s7 +; %bb.87: ; %Flow1018 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.88: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v54, vcc +; %bb.89: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i358.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.90: + v_bfe_u32 v37, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v53, v37, s7 +; %bb.91: ; %Flow1017 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.92: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v53, vcc +; %bb.93: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i361.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.94: + v_bfe_u32 v38, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v52, v38, s7 +; %bb.95: ; %Flow1016 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.96: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v52, vcc +; %bb.97: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i364.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.98: + v_bfe_u32 v39, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v51, v39, s7 +; %bb.99: ; %Flow1015 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.100: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v51, vcc +; %bb.101: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i367.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.102: + v_bfe_u32 v40, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v50, v40, s7 +; %bb.103: ; %Flow1014 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.104: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v50, vcc +; %bb.105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i370.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.106: + v_bfe_u32 v41, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v49, v41, s7 +; %bb.107: ; %Flow1013 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.108: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v49, vcc +; %bb.109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i373.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.110: + v_bfe_u32 v42, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v48, v42, s7 +; %bb.111: ; %Flow1012 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.112: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v48, vcc +; %bb.113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i376.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.114: + v_bfe_u32 v43, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v47, v43, s7 +; %bb.115: ; %Flow1011 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.116: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v74, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v74, v47, vcc +; %bb.117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i379.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr75 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.118: + v_bfe_u32 v74, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v75, v46, v74, s7 +; %bb.119: ; %Flow1010 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.120: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v75, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v75, v75, v46, vcc +; %bb.121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i382.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.122: + v_bfe_u32 v74, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v76, v45, v74, s7 +; %bb.123: ; %Flow1009 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.124: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v76, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v45, vcc +; %bb.125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i385.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.126: + v_bfe_u32 v74, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v77, v44, v74, s7 +; %bb.127: ; %Flow1008 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.128: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v77, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v44, vcc +; %bb.129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i388.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.130: + v_bfe_u32 v74, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v78, v255, v74, s7 +; %bb.131: ; %Flow1007 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.132: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v78, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v255, vcc +; %bb.133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i391.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.134: + v_bfe_u32 v74, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v79, v254, v74, s7 +; %bb.135: ; %Flow1006 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.136: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v79, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v254, vcc +; %bb.137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i394.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v74, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v74 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.138: + v_bfe_u32 v74, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v80, v253, v74, s7 +; %bb.139: ; %Flow1005 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.140: + v_mov_b32_e32 v74, 0 + v_or_b32_e32 v80, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v74 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v253, vcc +; %bb.141: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1ELi2E + s_or_b64 exec, exec, s[2:3] + v_and_b32_e32 v74, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v81, 3, v1 + v_and_or_b32 v81, v81, 12, s2 + v_lshlrev_b32_e32 v81, 7, v81 + v_lshl_or_b32 v81, v67, 1, v81 + v_lshlrev_b32_e32 v74, 1, v74 + s_and_b32 s2, s6, 64 + v_or3_b32 v74, v81, v74, s2 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v38 offset:9216 + ds_write_b16_d16_hi v74, v39 offset:9344 + ds_write_b16_d16_hi v74, v40 offset:9472 + ds_write_b16_d16_hi v74, v41 offset:9600 + ds_write_b16_d16_hi v74, v42 offset:10240 + ds_write_b16_d16_hi v74, v43 offset:10368 + ds_write_b16_d16_hi v74, v75 offset:10496 + ds_write_b16_d16_hi v74, v76 offset:10624 + ds_write_b16_d16_hi v74, v77 offset:11264 + ds_write_b16_d16_hi v74, v78 offset:11392 + ds_write_b16_d16_hi v74, v79 offset:11520 + ds_write_b16_d16_hi v74, v80 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v76, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v18, 1, v1 + v_and_b32_e32 v75, 60, v18 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s18, v18 + v_or_b32_e32 v38, s19, v76 + v_mad_u64_u32 v[40:41], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[42:43], v[40:41], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off + v_lshlrev_b32_e32 v18, 7, v18 + v_lshl_or_b32 v18, v76, 1, v18 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB15_143 +.LBB15_142: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s10 + v_perm_b32 v34, v78, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_159 +.LBB15_143: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.144: ; in Loop: Header=BB15_143 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.145: ; %Flow1004 + ; in Loop: Header=BB15_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.146: ; in Loop: Header=BB15_143 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.147: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.148: ; in Loop: Header=BB15_143 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s9 + ; implicit-def: $vgpr35 +; %bb.149: ; %Flow1003 + ; in Loop: Header=BB15_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.150: ; in Loop: Header=BB15_143 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.151: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.152: ; in Loop: Header=BB15_143 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s9 + ; implicit-def: $vgpr79 +; %bb.153: ; %Flow1002 + ; in Loop: Header=BB15_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.154: ; in Loop: Header=BB15_143 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.155: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_143 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s8, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.156: ; in Loop: Header=BB15_143 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s9 + ; implicit-def: $vgpr79 +; %bb.157: ; %Flow1001 + ; in Loop: Header=BB15_143 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_142 +; %bb.158: ; in Loop: Header=BB15_143 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB15_142 +.LBB15_159: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB15_161 +.LBB15_160: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s10 + v_perm_b32 v32, v41, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_177 +.LBB15_161: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.162: ; in Loop: Header=BB15_161 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.163: ; %Flow1000 + ; in Loop: Header=BB15_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.164: ; in Loop: Header=BB15_161 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.165: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.166: ; in Loop: Header=BB15_161 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s9 + ; implicit-def: $vgpr33 +; %bb.167: ; %Flow999 + ; in Loop: Header=BB15_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.168: ; in Loop: Header=BB15_161 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.169: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.170: ; in Loop: Header=BB15_161 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s9 + ; implicit-def: $vgpr77 +; %bb.171: ; %Flow998 + ; in Loop: Header=BB15_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.172: ; in Loop: Header=BB15_161 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.173: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_161 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.174: ; in Loop: Header=BB15_161 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s9 + ; implicit-def: $vgpr77 +; %bb.175: ; %Flow997 + ; in Loop: Header=BB15_161 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_160 +; %bb.176: ; in Loop: Header=BB15_161 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB15_160 +.LBB15_177: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_di + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v40 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB15_179 +.LBB15_178: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s10 + v_perm_b32 v30, v41, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_195 +.LBB15_179: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.180: ; in Loop: Header=BB15_179 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.181: ; %Flow996 + ; in Loop: Header=BB15_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.182: ; in Loop: Header=BB15_179 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.183: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.184: ; in Loop: Header=BB15_179 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s9 + ; implicit-def: $vgpr31 +; %bb.185: ; %Flow995 + ; in Loop: Header=BB15_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.186: ; in Loop: Header=BB15_179 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.187: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.188: ; in Loop: Header=BB15_179 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s9 + ; implicit-def: $vgpr42 +; %bb.189: ; %Flow994 + ; in Loop: Header=BB15_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.190: ; in Loop: Header=BB15_179 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.191: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_179 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s8, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.192: ; in Loop: Header=BB15_179 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s9 + ; implicit-def: $vgpr42 +; %bb.193: ; %Flow993 + ; in Loop: Header=BB15_179 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_178 +; %bb.194: ; in Loop: Header=BB15_179 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB15_178 +.LBB15_195: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_197 +.LBB15_196: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s10 + v_perm_b32 v28, v39, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_213 +.LBB15_197: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.198: ; in Loop: Header=BB15_197 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.199: ; %Flow992 + ; in Loop: Header=BB15_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.200: ; in Loop: Header=BB15_197 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.201: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.202: ; in Loop: Header=BB15_197 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s9 + ; implicit-def: $vgpr29 +; %bb.203: ; %Flow991 + ; in Loop: Header=BB15_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.204: ; in Loop: Header=BB15_197 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.205: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.206: ; in Loop: Header=BB15_197 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s9 + ; implicit-def: $vgpr40 +; %bb.207: ; %Flow990 + ; in Loop: Header=BB15_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.208: ; in Loop: Header=BB15_197 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.209: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_197 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s8, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.210: ; in Loop: Header=BB15_197 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s9 + ; implicit-def: $vgpr40 +; %bb.211: ; %Flow989 + ; in Loop: Header=BB15_197 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_196 +; %bb.212: ; in Loop: Header=BB15_197 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB15_196 +.LBB15_213: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile_65 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_215 +.LBB15_214: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_231 +.LBB15_215: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.216: ; in Loop: Header=BB15_215 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.217: ; %Flow988 + ; in Loop: Header=BB15_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.218: ; in Loop: Header=BB15_215 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.219: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.220: ; in Loop: Header=BB15_215 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.221: ; %Flow987 + ; in Loop: Header=BB15_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.222: ; in Loop: Header=BB15_215 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.223: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.224: ; in Loop: Header=BB15_215 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.225: ; %Flow986 + ; in Loop: Header=BB15_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.226: ; in Loop: Header=BB15_215 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.227: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_215 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.228: ; in Loop: Header=BB15_215 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s9 + ; implicit-def: $vgpr37 +; %bb.229: ; %Flow985 + ; in Loop: Header=BB15_215 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_214 +; %bb.230: ; in Loop: Header=BB15_215 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB15_214 +.LBB15_231: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_233 +.LBB15_232: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_249 +.LBB15_233: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.234: ; in Loop: Header=BB15_233 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.235: ; %Flow984 + ; in Loop: Header=BB15_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.236: ; in Loop: Header=BB15_233 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.237: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.238: ; in Loop: Header=BB15_233 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.239: ; %Flow983 + ; in Loop: Header=BB15_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.240: ; in Loop: Header=BB15_233 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.241: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.242: ; in Loop: Header=BB15_233 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.243: ; %Flow982 + ; in Loop: Header=BB15_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.244: ; in Loop: Header=BB15_233 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.245: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_233 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.246: ; in Loop: Header=BB15_233 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.247: ; %Flow981 + ; in Loop: Header=BB15_233 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_232 +; %bb.248: ; in Loop: Header=BB15_233 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_232 +.LBB15_249: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile130 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_251 +.LBB15_250: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_267 +.LBB15_251: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.252: ; in Loop: Header=BB15_251 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.253: ; %Flow980 + ; in Loop: Header=BB15_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.254: ; in Loop: Header=BB15_251 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.255: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.256: ; in Loop: Header=BB15_251 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.257: ; %Flow979 + ; in Loop: Header=BB15_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.258: ; in Loop: Header=BB15_251 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.259: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.260: ; in Loop: Header=BB15_251 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.261: ; %Flow978 + ; in Loop: Header=BB15_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.262: ; in Loop: Header=BB15_251 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.263: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_251 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.264: ; in Loop: Header=BB15_251 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.265: ; %Flow977 + ; in Loop: Header=BB15_251 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_250 +; %bb.266: ; in Loop: Header=BB15_251 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_250 +.LBB15_267: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_269 +.LBB15_268: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_285 +.LBB15_269: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.270: ; in Loop: Header=BB15_269 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.271: ; %Flow976 + ; in Loop: Header=BB15_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.272: ; in Loop: Header=BB15_269 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.273: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.274: ; in Loop: Header=BB15_269 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.275: ; %Flow975 + ; in Loop: Header=BB15_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.276: ; in Loop: Header=BB15_269 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.277: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.278: ; in Loop: Header=BB15_269 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.279: ; %Flow974 + ; in Loop: Header=BB15_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.280: ; in Loop: Header=BB15_269 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.281: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i.i.i.i.i.i + ; in Loop: Header=BB15_269 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.282: ; in Loop: Header=BB15_269 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.283: ; %Flow973 + ; in Loop: Header=BB15_269 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_268 +; %bb.284: ; in Loop: Header=BB15_269 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_268 +.LBB15_285: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.286: + v_bfe_u32 v18, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v252, v18, s6 +; %bb.287: ; %Flow972 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.288: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v252, vcc +; %bb.289: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i437.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.290: + v_bfe_u32 v19, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v251, v19, s6 +; %bb.291: ; %Flow971 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.292: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v251, vcc +; %bb.293: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i440.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.294: + v_bfe_u32 v20, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v250, v20, s6 +; %bb.295: ; %Flow970 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.296: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v250, vcc +; %bb.297: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i443.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.298: + v_bfe_u32 v21, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v249, v21, s6 +; %bb.299: ; %Flow969 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.300: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v249, vcc +; %bb.301: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i446.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.302: + v_bfe_u32 v22, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v248, v22, s6 +; %bb.303: ; %Flow968 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.304: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v248, vcc +; %bb.305: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i449.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.306: + v_bfe_u32 v23, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v247, v23, s6 +; %bb.307: ; %Flow967 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.308: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v247, vcc +; %bb.309: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i452.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.310: + v_bfe_u32 v24, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v246, v24, s6 +; %bb.311: ; %Flow966 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.312: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v246, vcc +; %bb.313: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i455.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.314: + v_bfe_u32 v25, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v245, v25, s6 +; %bb.315: ; %Flow965 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.316: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v245, vcc +; %bb.317: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i458.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.318: + v_bfe_u32 v26, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v244, v26, s6 +; %bb.319: ; %Flow964 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.320: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v244, vcc +; %bb.321: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i461.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.322: + v_bfe_u32 v27, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v243, v27, s6 +; %bb.323: ; %Flow963 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.324: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v243, vcc +; %bb.325: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i464.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.326: + v_bfe_u32 v28, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v242, v28, s6 +; %bb.327: ; %Flow962 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.328: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v242, vcc +; %bb.329: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i467.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.330: + v_bfe_u32 v29, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v241, v29, s6 +; %bb.331: ; %Flow961 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.332: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v241, vcc +; %bb.333: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i470.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.334: + v_bfe_u32 v30, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v240, v30, s6 +; %bb.335: ; %Flow960 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.336: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v240, vcc +; %bb.337: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i473.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.338: + v_bfe_u32 v31, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v239, v31, s6 +; %bb.339: ; %Flow959 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.340: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v239, vcc +; %bb.341: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i476.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.342: + v_bfe_u32 v32, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v238, v32, s6 +; %bb.343: ; %Flow958 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.344: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v238, vcc +; %bb.345: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i479.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.346: + v_bfe_u32 v33, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v236, v33, s6 +; %bb.347: ; %Flow957 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.348: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v236, vcc +; %bb.349: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i482.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.350: + v_bfe_u32 v34, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v237, v34, s6 +; %bb.351: ; %Flow956 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.352: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v237, vcc +; %bb.353: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i485.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.354: + v_bfe_u32 v35, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v235, v35, s6 +; %bb.355: ; %Flow955 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.356: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v235, vcc +; %bb.357: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i488.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.358: + v_bfe_u32 v36, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v234, v36, s6 +; %bb.359: ; %Flow954 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.360: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v234, vcc +; %bb.361: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i491.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.362: + v_bfe_u32 v37, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v233, v37, s6 +; %bb.363: ; %Flow953 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.364: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v39, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v233, vcc +; %bb.365: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i494.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.366: + v_bfe_u32 v39, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v232, v39, s6 +; %bb.367: ; %Flow952 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.368: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v232, vcc +; %bb.369: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i497.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.370: + v_bfe_u32 v40, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v231, v40, s6 +; %bb.371: ; %Flow951 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.372: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v231, vcc +; %bb.373: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i500.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.374: + v_bfe_u32 v41, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v230, v41, s6 +; %bb.375: ; %Flow950 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.376: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v230, vcc +; %bb.377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i503.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.378: + v_bfe_u32 v42, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v229, v42, s6 +; %bb.379: ; %Flow949 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.380: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v229, vcc +; %bb.381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i506.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.382: + v_bfe_u32 v43, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v228, v43, s6 +; %bb.383: ; %Flow948 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.384: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v228, vcc +; %bb.385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i509.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.386: + v_bfe_u32 v77, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v227, v77, s6 +; %bb.387: ; %Flow947 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.388: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v227, vcc +; %bb.389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i512.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.390: + v_bfe_u32 v78, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v226, v78, s6 +; %bb.391: ; %Flow946 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.392: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v226, vcc +; %bb.393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i515.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.394: + v_bfe_u32 v79, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v225, v79, s6 +; %bb.395: ; %Flow945 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.396: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v225, vcc +; %bb.397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i518.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.398: + v_bfe_u32 v80, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v224, v80, s6 +; %bb.399: ; %Flow944 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.400: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v224, vcc +; %bb.401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i521.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.402: + v_bfe_u32 v81, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v223, v81, s6 +; %bb.403: ; %Flow943 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.404: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v223, vcc +; %bb.405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i524.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.406: + v_bfe_u32 v82, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v222, v82, s6 +; %bb.407: ; %Flow942 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.408: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v222, vcc +; %bb.409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i527.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.410: + v_bfe_u32 v83, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v221, v83, s6 +; %bb.411: ; %Flow941 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.412: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v221, vcc +; %bb.413: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL159 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshlrev_b32_e32 v76, 1, v76 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB15_415 +.LBB15_414: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i222.i.i.i.i.i + ; in Loop: Header=BB15_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_431 +.LBB15_415: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.416: ; in Loop: Header=BB15_415 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.417: ; %Flow940 + ; in Loop: Header=BB15_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.418: ; in Loop: Header=BB15_415 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.419: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i213.i.i.i.i.i + ; in Loop: Header=BB15_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.420: ; in Loop: Header=BB15_415 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.421: ; %Flow939 + ; in Loop: Header=BB15_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.422: ; in Loop: Header=BB15_415 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.423: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i216.i.i.i.i.i + ; in Loop: Header=BB15_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.424: ; in Loop: Header=BB15_415 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.425: ; %Flow938 + ; in Loop: Header=BB15_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.426: ; in Loop: Header=BB15_415 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.427: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i219.i.i.i.i.i + ; in Loop: Header=BB15_415 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.428: ; in Loop: Header=BB15_415 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.429: ; %Flow937 + ; in Loop: Header=BB15_415 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_414 +; %bb.430: ; in Loop: Header=BB15_415 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB15_414 +.LBB15_431: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i225.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_433 +.LBB15_432: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i238.i.i.i.i.i + ; in Loop: Header=BB15_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_449 +.LBB15_433: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.434: ; in Loop: Header=BB15_433 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.435: ; %Flow936 + ; in Loop: Header=BB15_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.436: ; in Loop: Header=BB15_433 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.437: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i229.i.i.i.i.i + ; in Loop: Header=BB15_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.438: ; in Loop: Header=BB15_433 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.439: ; %Flow935 + ; in Loop: Header=BB15_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.440: ; in Loop: Header=BB15_433 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.441: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i232.i.i.i.i.i + ; in Loop: Header=BB15_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.442: ; in Loop: Header=BB15_433 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.443: ; %Flow934 + ; in Loop: Header=BB15_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.444: ; in Loop: Header=BB15_433 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.445: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i235.i.i.i.i.i + ; in Loop: Header=BB15_433 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.446: ; in Loop: Header=BB15_433 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.447: ; %Flow933 + ; in Loop: Header=BB15_433 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_432 +; %bb.448: ; in Loop: Header=BB15_433 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB15_432 +.LBB15_449: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile242 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 64, v38 + v_accvgpr_write_b32 a1, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_451 +.LBB15_450: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i255.i.i.i.i.i + ; in Loop: Header=BB15_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_467 +.LBB15_451: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.452: ; in Loop: Header=BB15_451 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.453: ; %Flow932 + ; in Loop: Header=BB15_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.454: ; in Loop: Header=BB15_451 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.455: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i246.i.i.i.i.i + ; in Loop: Header=BB15_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.456: ; in Loop: Header=BB15_451 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.457: ; %Flow931 + ; in Loop: Header=BB15_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.458: ; in Loop: Header=BB15_451 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.459: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i249.i.i.i.i.i + ; in Loop: Header=BB15_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.460: ; in Loop: Header=BB15_451 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.461: ; %Flow930 + ; in Loop: Header=BB15_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.462: ; in Loop: Header=BB15_451 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.463: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i252.i.i.i.i.i + ; in Loop: Header=BB15_451 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.464: ; in Loop: Header=BB15_451 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.465: ; %Flow929 + ; in Loop: Header=BB15_451 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_450 +; %bb.466: ; in Loop: Header=BB15_451 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB15_450 +.LBB15_467: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i258.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_469 +.LBB15_468: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i271.i.i.i.i.i + ; in Loop: Header=BB15_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_485 +.LBB15_469: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.470: ; in Loop: Header=BB15_469 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.471: ; %Flow928 + ; in Loop: Header=BB15_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.472: ; in Loop: Header=BB15_469 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.473: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i262.i.i.i.i.i + ; in Loop: Header=BB15_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.474: ; in Loop: Header=BB15_469 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.475: ; %Flow927 + ; in Loop: Header=BB15_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.476: ; in Loop: Header=BB15_469 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.477: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i265.i.i.i.i.i + ; in Loop: Header=BB15_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.478: ; in Loop: Header=BB15_469 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.479: ; %Flow926 + ; in Loop: Header=BB15_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.480: ; in Loop: Header=BB15_469 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.481: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i268.i.i.i.i.i + ; in Loop: Header=BB15_469 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.482: ; in Loop: Header=BB15_469 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.483: ; %Flow925 + ; in Loop: Header=BB15_469 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_468 +; %bb.484: ; in Loop: Header=BB15_469 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_468 +.LBB15_485: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile275 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_487 +.LBB15_486: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i288.i.i.i.i.i + ; in Loop: Header=BB15_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_503 +.LBB15_487: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.488: ; in Loop: Header=BB15_487 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.489: ; %Flow924 + ; in Loop: Header=BB15_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.490: ; in Loop: Header=BB15_487 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.491: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i279.i.i.i.i.i + ; in Loop: Header=BB15_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.492: ; in Loop: Header=BB15_487 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.493: ; %Flow923 + ; in Loop: Header=BB15_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.494: ; in Loop: Header=BB15_487 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.495: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i282.i.i.i.i.i + ; in Loop: Header=BB15_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.496: ; in Loop: Header=BB15_487 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.497: ; %Flow922 + ; in Loop: Header=BB15_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.498: ; in Loop: Header=BB15_487 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.499: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i285.i.i.i.i.i + ; in Loop: Header=BB15_487 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.500: ; in Loop: Header=BB15_487 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.501: ; %Flow921 + ; in Loop: Header=BB15_487 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_486 +; %bb.502: ; in Loop: Header=BB15_487 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB15_486 +.LBB15_503: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i291.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_505 +.LBB15_504: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i304.i.i.i.i.i + ; in Loop: Header=BB15_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_521 +.LBB15_505: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.506: ; in Loop: Header=BB15_505 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.507: ; %Flow920 + ; in Loop: Header=BB15_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.508: ; in Loop: Header=BB15_505 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.509: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i295.i.i.i.i.i + ; in Loop: Header=BB15_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.510: ; in Loop: Header=BB15_505 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.511: ; %Flow919 + ; in Loop: Header=BB15_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.512: ; in Loop: Header=BB15_505 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.513: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i298.i.i.i.i.i + ; in Loop: Header=BB15_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.514: ; in Loop: Header=BB15_505 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.515: ; %Flow918 + ; in Loop: Header=BB15_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.516: ; in Loop: Header=BB15_505 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.517: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i301.i.i.i.i.i + ; in Loop: Header=BB15_505 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.518: ; in Loop: Header=BB15_505 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.519: ; %Flow917 + ; in Loop: Header=BB15_505 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_504 +; %bb.520: ; in Loop: Header=BB15_505 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_504 +.LBB15_521: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile308 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_523 +.LBB15_522: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i321.i.i.i.i.i + ; in Loop: Header=BB15_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_539 +.LBB15_523: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.524: ; in Loop: Header=BB15_523 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.525: ; %Flow916 + ; in Loop: Header=BB15_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.526: ; in Loop: Header=BB15_523 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.527: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i312.i.i.i.i.i + ; in Loop: Header=BB15_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.528: ; in Loop: Header=BB15_523 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.529: ; %Flow915 + ; in Loop: Header=BB15_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.530: ; in Loop: Header=BB15_523 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.531: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i315.i.i.i.i.i + ; in Loop: Header=BB15_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.532: ; in Loop: Header=BB15_523 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.533: ; %Flow914 + ; in Loop: Header=BB15_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.534: ; in Loop: Header=BB15_523 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.535: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i318.i.i.i.i.i + ; in Loop: Header=BB15_523 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.536: ; in Loop: Header=BB15_523 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.537: ; %Flow913 + ; in Loop: Header=BB15_523 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_522 +; %bb.538: ; in Loop: Header=BB15_523 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_522 +.LBB15_539: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i324.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_541 +.LBB15_540: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i337.i.i.i.i.i + ; in Loop: Header=BB15_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_557 +.LBB15_541: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.542: ; in Loop: Header=BB15_541 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.543: ; %Flow912 + ; in Loop: Header=BB15_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.544: ; in Loop: Header=BB15_541 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.545: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i328.i.i.i.i.i + ; in Loop: Header=BB15_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.546: ; in Loop: Header=BB15_541 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.547: ; %Flow911 + ; in Loop: Header=BB15_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.548: ; in Loop: Header=BB15_541 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.549: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i331.i.i.i.i.i + ; in Loop: Header=BB15_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.550: ; in Loop: Header=BB15_541 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.551: ; %Flow910 + ; in Loop: Header=BB15_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.552: ; in Loop: Header=BB15_541 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.553: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i334.i.i.i.i.i + ; in Loop: Header=BB15_541 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.554: ; in Loop: Header=BB15_541 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.555: ; %Flow909 + ; in Loop: Header=BB15_541 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_540 +; %bb.556: ; in Loop: Header=BB15_541 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_540 +.LBB15_557: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_469 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.558: + v_bfe_u32 v18, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v220, v18, s6 +; %bb.559: ; %Flow908 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.560: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v220, vcc +; %bb.561: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i534.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.562: + v_bfe_u32 v19, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v219, v19, s6 +; %bb.563: ; %Flow907 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.564: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v219, vcc +; %bb.565: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i537.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.566: + v_bfe_u32 v20, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v218, v20, s6 +; %bb.567: ; %Flow906 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.568: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v218, vcc +; %bb.569: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i540.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.570: + v_bfe_u32 v21, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v217, v21, s6 +; %bb.571: ; %Flow905 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.572: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v217, vcc +; %bb.573: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i543.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.574: + v_bfe_u32 v22, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v216, v22, s6 +; %bb.575: ; %Flow904 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.576: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v216, vcc +; %bb.577: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i546.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.578: + v_bfe_u32 v23, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v215, v23, s6 +; %bb.579: ; %Flow903 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.580: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v215, vcc +; %bb.581: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i549.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.582: + v_bfe_u32 v24, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v214, v24, s6 +; %bb.583: ; %Flow902 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.584: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v214, vcc +; %bb.585: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i552.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.586: + v_bfe_u32 v25, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v213, v25, s6 +; %bb.587: ; %Flow901 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.588: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v213, vcc +; %bb.589: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i555.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.590: + v_bfe_u32 v26, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v212, v26, s6 +; %bb.591: ; %Flow900 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.592: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v212, vcc +; %bb.593: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i558.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.594: + v_bfe_u32 v27, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v211, v27, s6 +; %bb.595: ; %Flow899 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.596: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v211, vcc +; %bb.597: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i561.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.598: + v_bfe_u32 v28, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v210, v28, s6 +; %bb.599: ; %Flow898 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.600: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v210, vcc +; %bb.601: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i564.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.602: + v_bfe_u32 v29, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v209, v29, s6 +; %bb.603: ; %Flow897 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.604: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v209, vcc +; %bb.605: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i567.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.606: + v_bfe_u32 v30, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v208, v30, s6 +; %bb.607: ; %Flow896 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.608: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v208, vcc +; %bb.609: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.610: + v_bfe_u32 v31, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v207, v31, s6 +; %bb.611: ; %Flow895 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.612: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v207, vcc +; %bb.613: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i573.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.614: + v_bfe_u32 v32, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v206, v32, s6 +; %bb.615: ; %Flow894 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.616: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v206, vcc +; %bb.617: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i576.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.618: + v_bfe_u32 v33, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v204, v33, s6 +; %bb.619: ; %Flow893 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.620: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v204, vcc +; %bb.621: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i579.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.622: + v_bfe_u32 v34, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v205, v34, s6 +; %bb.623: ; %Flow892 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.624: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v205, vcc +; %bb.625: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i582.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.626: + v_bfe_u32 v35, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v203, v35, s6 +; %bb.627: ; %Flow891 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.628: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v203, vcc +; %bb.629: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i585.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.630: + v_bfe_u32 v36, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v202, v36, s6 +; %bb.631: ; %Flow890 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.632: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v202, vcc +; %bb.633: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i588.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.634: + v_bfe_u32 v37, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v201, v37, s6 +; %bb.635: ; %Flow889 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.636: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v201, vcc +; %bb.637: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i591.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.638: + v_bfe_u32 v40, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v200, v40, s6 +; %bb.639: ; %Flow888 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.640: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v200, vcc +; %bb.641: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i594.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.642: + v_bfe_u32 v41, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v199, v41, s6 +; %bb.643: ; %Flow887 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.644: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v199, vcc +; %bb.645: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i597.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.646: + v_bfe_u32 v42, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v198, v42, s6 +; %bb.647: ; %Flow886 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.648: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v198, vcc +; %bb.649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i600.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.650: + v_bfe_u32 v43, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v197, v43, s6 +; %bb.651: ; %Flow885 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.652: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v197, vcc +; %bb.653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.654: + v_bfe_u32 v77, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v196, v77, s6 +; %bb.655: ; %Flow884 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.656: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v196, vcc +; %bb.657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i606.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.658: + v_bfe_u32 v78, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v195, v78, s6 +; %bb.659: ; %Flow883 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.660: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v195, vcc +; %bb.661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i609.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.662: + v_bfe_u32 v79, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v194, v79, s6 +; %bb.663: ; %Flow882 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.664: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v194, vcc +; %bb.665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i612.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.666: + v_bfe_u32 v80, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v193, v80, s6 +; %bb.667: ; %Flow881 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.668: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v193, vcc +; %bb.669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i615.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.670: + v_bfe_u32 v81, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v192, v81, s6 +; %bb.671: ; %Flow880 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.672: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v192, vcc +; %bb.673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i618.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.674: + v_bfe_u32 v82, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v191, v82, s6 +; %bb.675: ; %Flow879 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.676: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v191, vcc +; %bb.677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i621.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.678: + v_bfe_u32 v83, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v190, v83, s6 +; %bb.679: ; %Flow878 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.680: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v190, vcc +; %bb.681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i624.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.682: + v_bfe_u32 v84, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v189, v84, s6 +; %bb.683: ; %Flow877 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.684: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v189, vcc +; %bb.685: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1EL628 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB15_687 +.LBB15_686: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i691.i.i.i.i.i + ; in Loop: Header=BB15_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_703 +.LBB15_687: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.688: ; in Loop: Header=BB15_687 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.689: ; %Flow876 + ; in Loop: Header=BB15_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.690: ; in Loop: Header=BB15_687 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.691: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i682.i.i.i.i.i + ; in Loop: Header=BB15_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.692: ; in Loop: Header=BB15_687 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.693: ; %Flow875 + ; in Loop: Header=BB15_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.694: ; in Loop: Header=BB15_687 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.695: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i685.i.i.i.i.i + ; in Loop: Header=BB15_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.696: ; in Loop: Header=BB15_687 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.697: ; %Flow874 + ; in Loop: Header=BB15_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.698: ; in Loop: Header=BB15_687 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.699: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i688.i.i.i.i.i + ; in Loop: Header=BB15_687 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.700: ; in Loop: Header=BB15_687 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.701: ; %Flow873 + ; in Loop: Header=BB15_687 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_686 +; %bb.702: ; in Loop: Header=BB15_687 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB15_686 +.LBB15_703: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i694.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_705 +.LBB15_704: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i707.i.i.i.i.i + ; in Loop: Header=BB15_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_721 +.LBB15_705: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.706: ; in Loop: Header=BB15_705 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.707: ; %Flow872 + ; in Loop: Header=BB15_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.708: ; in Loop: Header=BB15_705 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.709: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i698.i.i.i.i.i + ; in Loop: Header=BB15_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.710: ; in Loop: Header=BB15_705 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.711: ; %Flow871 + ; in Loop: Header=BB15_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.712: ; in Loop: Header=BB15_705 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.713: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i701.i.i.i.i.i + ; in Loop: Header=BB15_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.714: ; in Loop: Header=BB15_705 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.715: ; %Flow870 + ; in Loop: Header=BB15_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.716: ; in Loop: Header=BB15_705 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.717: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i704.i.i.i.i.i + ; in Loop: Header=BB15_705 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.718: ; in Loop: Header=BB15_705 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.719: ; %Flow869 + ; in Loop: Header=BB15_705 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_704 +; %bb.720: ; in Loop: Header=BB15_705 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB15_704 +.LBB15_721: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile711 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v30, 0x80, v38 + v_accvgpr_write_b32 a2, v30 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_723 +.LBB15_722: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i724.i.i.i.i.i + ; in Loop: Header=BB15_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_739 +.LBB15_723: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.724: ; in Loop: Header=BB15_723 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.725: ; %Flow868 + ; in Loop: Header=BB15_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.726: ; in Loop: Header=BB15_723 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.727: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i715.i.i.i.i.i + ; in Loop: Header=BB15_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.728: ; in Loop: Header=BB15_723 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.729: ; %Flow867 + ; in Loop: Header=BB15_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.730: ; in Loop: Header=BB15_723 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.731: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i718.i.i.i.i.i + ; in Loop: Header=BB15_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.732: ; in Loop: Header=BB15_723 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.733: ; %Flow866 + ; in Loop: Header=BB15_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.734: ; in Loop: Header=BB15_723 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.735: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i721.i.i.i.i.i + ; in Loop: Header=BB15_723 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.736: ; in Loop: Header=BB15_723 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s9 + ; implicit-def: $vgpr43 +; %bb.737: ; %Flow865 + ; in Loop: Header=BB15_723 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_722 +; %bb.738: ; in Loop: Header=BB15_723 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB15_722 +.LBB15_739: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i727.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_741 +.LBB15_740: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i740.i.i.i.i.i + ; in Loop: Header=BB15_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_757 +.LBB15_741: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.742: ; in Loop: Header=BB15_741 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.743: ; %Flow864 + ; in Loop: Header=BB15_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.744: ; in Loop: Header=BB15_741 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.745: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i731.i.i.i.i.i + ; in Loop: Header=BB15_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.746: ; in Loop: Header=BB15_741 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.747: ; %Flow863 + ; in Loop: Header=BB15_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.748: ; in Loop: Header=BB15_741 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.749: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i734.i.i.i.i.i + ; in Loop: Header=BB15_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.750: ; in Loop: Header=BB15_741 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.751: ; %Flow862 + ; in Loop: Header=BB15_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.752: ; in Loop: Header=BB15_741 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.753: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i737.i.i.i.i.i + ; in Loop: Header=BB15_741 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.754: ; in Loop: Header=BB15_741 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.755: ; %Flow861 + ; in Loop: Header=BB15_741 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_740 +; %bb.756: ; in Loop: Header=BB15_741 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_740 +.LBB15_757: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile744 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_759 +.LBB15_758: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i757.i.i.i.i.i + ; in Loop: Header=BB15_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_775 +.LBB15_759: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.760: ; in Loop: Header=BB15_759 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.761: ; %Flow860 + ; in Loop: Header=BB15_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.762: ; in Loop: Header=BB15_759 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.763: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i748.i.i.i.i.i + ; in Loop: Header=BB15_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.764: ; in Loop: Header=BB15_759 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.765: ; %Flow859 + ; in Loop: Header=BB15_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.766: ; in Loop: Header=BB15_759 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.767: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i751.i.i.i.i.i + ; in Loop: Header=BB15_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.768: ; in Loop: Header=BB15_759 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.769: ; %Flow858 + ; in Loop: Header=BB15_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.770: ; in Loop: Header=BB15_759 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.771: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i754.i.i.i.i.i + ; in Loop: Header=BB15_759 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.772: ; in Loop: Header=BB15_759 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.773: ; %Flow857 + ; in Loop: Header=BB15_759 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_758 +; %bb.774: ; in Loop: Header=BB15_759 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB15_758 +.LBB15_775: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i760.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_777 +.LBB15_776: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i773.i.i.i.i.i + ; in Loop: Header=BB15_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_793 +.LBB15_777: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.778: ; in Loop: Header=BB15_777 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.779: ; %Flow856 + ; in Loop: Header=BB15_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.780: ; in Loop: Header=BB15_777 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.781: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i764.i.i.i.i.i + ; in Loop: Header=BB15_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.782: ; in Loop: Header=BB15_777 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.783: ; %Flow855 + ; in Loop: Header=BB15_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.784: ; in Loop: Header=BB15_777 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.785: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i767.i.i.i.i.i + ; in Loop: Header=BB15_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.786: ; in Loop: Header=BB15_777 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.787: ; %Flow854 + ; in Loop: Header=BB15_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.788: ; in Loop: Header=BB15_777 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.789: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i770.i.i.i.i.i + ; in Loop: Header=BB15_777 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.790: ; in Loop: Header=BB15_777 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.791: ; %Flow853 + ; in Loop: Header=BB15_777 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_776 +; %bb.792: ; in Loop: Header=BB15_777 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_776 +.LBB15_793: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26tile777 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_795 +.LBB15_794: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i790.i.i.i.i.i + ; in Loop: Header=BB15_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_811 +.LBB15_795: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.796: ; in Loop: Header=BB15_795 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.797: ; %Flow852 + ; in Loop: Header=BB15_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.798: ; in Loop: Header=BB15_795 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.799: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i781.i.i.i.i.i + ; in Loop: Header=BB15_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.800: ; in Loop: Header=BB15_795 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.801: ; %Flow851 + ; in Loop: Header=BB15_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.802: ; in Loop: Header=BB15_795 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.803: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i784.i.i.i.i.i + ; in Loop: Header=BB15_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.804: ; in Loop: Header=BB15_795 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.805: ; %Flow850 + ; in Loop: Header=BB15_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.806: ; in Loop: Header=BB15_795 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.807: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i787.i.i.i.i.i + ; in Loop: Header=BB15_795 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.808: ; in Loop: Header=BB15_795 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.809: ; %Flow849 + ; in Loop: Header=BB15_795 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_794 +; %bb.810: ; in Loop: Header=BB15_795 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_794 +.LBB15_811: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i793.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_813 +.LBB15_812: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i806.i.i.i.i.i + ; in Loop: Header=BB15_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_829 +.LBB15_813: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.814: ; in Loop: Header=BB15_813 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.815: ; %Flow848 + ; in Loop: Header=BB15_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.816: ; in Loop: Header=BB15_813 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.817: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i797.i.i.i.i.i + ; in Loop: Header=BB15_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.818: ; in Loop: Header=BB15_813 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.819: ; %Flow847 + ; in Loop: Header=BB15_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.820: ; in Loop: Header=BB15_813 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.821: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i800.i.i.i.i.i + ; in Loop: Header=BB15_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.822: ; in Loop: Header=BB15_813 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.823: ; %Flow846 + ; in Loop: Header=BB15_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.824: ; in Loop: Header=BB15_813 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.825: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i803.i.i.i.i.i + ; in Loop: Header=BB15_813 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.826: ; in Loop: Header=BB15_813 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.827: ; %Flow845 + ; in Loop: Header=BB15_813 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_812 +; %bb.828: ; in Loop: Header=BB15_813 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_812 +.LBB15_829: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_938 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.830: + v_bfe_u32 v18, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v188, v18, s6 +; %bb.831: ; %Flow844 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.832: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v188, vcc +; %bb.833: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1003.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.834: + v_bfe_u32 v19, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v187, v19, s6 +; %bb.835: ; %Flow843 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.836: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v187, vcc +; %bb.837: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1006.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.838: + v_bfe_u32 v20, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v186, v20, s6 +; %bb.839: ; %Flow842 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.840: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v186, vcc +; %bb.841: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1009.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.842: + v_bfe_u32 v21, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v185, v21, s6 +; %bb.843: ; %Flow841 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.844: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v185, vcc +; %bb.845: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1012.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.846: + v_bfe_u32 v22, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v184, v22, s6 +; %bb.847: ; %Flow840 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.848: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v184, vcc +; %bb.849: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1015.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.850: + v_bfe_u32 v23, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v183, v23, s6 +; %bb.851: ; %Flow839 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.852: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v183, vcc +; %bb.853: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1018.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.854: + v_bfe_u32 v24, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v182, v24, s6 +; %bb.855: ; %Flow838 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.856: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v182, vcc +; %bb.857: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1021.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.858: + v_bfe_u32 v25, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v181, v25, s6 +; %bb.859: ; %Flow837 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.860: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v181, vcc +; %bb.861: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1024.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.862: + v_bfe_u32 v26, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v180, v26, s6 +; %bb.863: ; %Flow836 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.864: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v180, vcc +; %bb.865: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1027.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.866: + v_bfe_u32 v27, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v179, v27, s6 +; %bb.867: ; %Flow835 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.868: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v179, vcc +; %bb.869: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1030.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.870: + v_bfe_u32 v28, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v178, v28, s6 +; %bb.871: ; %Flow834 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.872: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v178, vcc +; %bb.873: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1033.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.874: + v_bfe_u32 v29, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v177, v29, s6 +; %bb.875: ; %Flow833 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.876: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v177, vcc +; %bb.877: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1036.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.878: + v_bfe_u32 v30, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v176, v30, s6 +; %bb.879: ; %Flow832 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.880: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v176, vcc +; %bb.881: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.882: + v_bfe_u32 v31, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v175, v31, s6 +; %bb.883: ; %Flow831 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.884: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v175, vcc +; %bb.885: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1042.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.886: + v_bfe_u32 v32, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v174, v32, s6 +; %bb.887: ; %Flow830 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.888: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v174, vcc +; %bb.889: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1045.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.890: + v_bfe_u32 v33, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v172, v33, s6 +; %bb.891: ; %Flow829 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.892: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v172, vcc +; %bb.893: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1048.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.894: + v_bfe_u32 v34, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v173, v34, s6 +; %bb.895: ; %Flow828 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.896: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v173, vcc +; %bb.897: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1051.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.898: + v_bfe_u32 v35, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v171, v35, s6 +; %bb.899: ; %Flow827 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.900: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v171, vcc +; %bb.901: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1054.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.902: + v_bfe_u32 v36, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v170, v36, s6 +; %bb.903: ; %Flow826 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.904: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v170, vcc +; %bb.905: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1057.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.906: + v_bfe_u32 v37, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v169, v37, s6 +; %bb.907: ; %Flow825 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.908: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v169, vcc +; %bb.909: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1060.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.910: + v_bfe_u32 v40, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v168, v40, s6 +; %bb.911: ; %Flow824 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.912: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v168, vcc +; %bb.913: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1063.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.914: + v_bfe_u32 v41, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v167, v41, s6 +; %bb.915: ; %Flow823 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.916: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v167, vcc +; %bb.917: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1066.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.918: + v_bfe_u32 v42, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v166, v42, s6 +; %bb.919: ; %Flow822 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.920: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v166, vcc +; %bb.921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1069.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.922: + v_bfe_u32 v43, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v165, v43, s6 +; %bb.923: ; %Flow821 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.924: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v165, vcc +; %bb.925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.926: + v_bfe_u32 v77, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v164, v77, s6 +; %bb.927: ; %Flow820 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.928: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v164, vcc +; %bb.929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1075.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.930: + v_bfe_u32 v78, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v163, v78, s6 +; %bb.931: ; %Flow819 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.932: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v163, vcc +; %bb.933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1078.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.934: + v_bfe_u32 v79, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v162, v79, s6 +; %bb.935: ; %Flow818 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.936: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v162, vcc +; %bb.937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1081.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.938: + v_bfe_u32 v80, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v161, v80, s6 +; %bb.939: ; %Flow817 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.940: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v161, vcc +; %bb.941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1084.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.942: + v_bfe_u32 v81, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v160, v81, s6 +; %bb.943: ; %Flow816 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.944: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v160, vcc +; %bb.945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1087.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.946: + v_bfe_u32 v82, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v159, v82, s6 +; %bb.947: ; %Flow815 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.948: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v159, vcc +; %bb.949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1090.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.950: + v_bfe_u32 v83, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v158, v83, s6 +; %bb.951: ; %Flow814 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.952: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v158, vcc +; %bb.953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1093.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.954: + v_bfe_u32 v84, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v157, v84, s6 +; %bb.955: ; %Flow813 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.956: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v157, vcc +; %bb.957: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1097 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s18, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB15_959 +.LBB15_958: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1160.i.i.i.i.i + ; in Loop: Header=BB15_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s10 + v_perm_b32 v34, v79, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_975 +.LBB15_959: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.960: ; in Loop: Header=BB15_959 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.961: ; %Flow812 + ; in Loop: Header=BB15_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.962: ; in Loop: Header=BB15_959 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.963: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1151.i.i.i.i.i + ; in Loop: Header=BB15_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.964: ; in Loop: Header=BB15_959 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s9 + ; implicit-def: $vgpr35 +; %bb.965: ; %Flow811 + ; in Loop: Header=BB15_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.966: ; in Loop: Header=BB15_959 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.967: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1154.i.i.i.i.i + ; in Loop: Header=BB15_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.968: ; in Loop: Header=BB15_959 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s9 + ; implicit-def: $vgpr80 +; %bb.969: ; %Flow810 + ; in Loop: Header=BB15_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.970: ; in Loop: Header=BB15_959 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.971: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1157.i.i.i.i.i + ; in Loop: Header=BB15_959 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s8, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.972: ; in Loop: Header=BB15_959 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s9 + ; implicit-def: $vgpr80 +; %bb.973: ; %Flow809 + ; in Loop: Header=BB15_959 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_958 +; %bb.974: ; in Loop: Header=BB15_959 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB15_958 +.LBB15_975: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1163.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_977 +.LBB15_976: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1176.i.i.i.i.i + ; in Loop: Header=BB15_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s10 + v_perm_b32 v32, v77, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_993 +.LBB15_977: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.978: ; in Loop: Header=BB15_977 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.979: ; %Flow808 + ; in Loop: Header=BB15_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.980: ; in Loop: Header=BB15_977 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.981: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1167.i.i.i.i.i + ; in Loop: Header=BB15_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.982: ; in Loop: Header=BB15_977 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s9 + ; implicit-def: $vgpr33 +; %bb.983: ; %Flow807 + ; in Loop: Header=BB15_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.984: ; in Loop: Header=BB15_977 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.985: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1170.i.i.i.i.i + ; in Loop: Header=BB15_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.986: ; in Loop: Header=BB15_977 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s9 + ; implicit-def: $vgpr78 +; %bb.987: ; %Flow806 + ; in Loop: Header=BB15_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.988: ; in Loop: Header=BB15_977 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.989: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1173.i.i.i.i.i + ; in Loop: Header=BB15_977 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s8, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.990: ; in Loop: Header=BB15_977 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s9 + ; implicit-def: $vgpr78 +; %bb.991: ; %Flow805 + ; in Loop: Header=BB15_977 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_976 +; %bb.992: ; in Loop: Header=BB15_977 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB15_976 +.LBB15_993: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1180 + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v77, 0xc0, v38 + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_995 +.LBB15_994: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1193.i.i.i.i.i + ; in Loop: Header=BB15_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v78, v31, s10 + v_perm_b32 v30, v42, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1011 +.LBB15_995: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.996: ; in Loop: Header=BB15_995 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.997: ; %Flow804 + ; in Loop: Header=BB15_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.998: ; in Loop: Header=BB15_995 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.999: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1184.i.i.i.i.i + ; in Loop: Header=BB15_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1000: ; in Loop: Header=BB15_995 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s9 + ; implicit-def: $vgpr31 +; %bb.1001: ; %Flow803 + ; in Loop: Header=BB15_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1002: ; in Loop: Header=BB15_995 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1003: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1187.i.i.i.i.i + ; in Loop: Header=BB15_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1004: ; in Loop: Header=BB15_995 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s9 + ; implicit-def: $vgpr43 +; %bb.1005: ; %Flow802 + ; in Loop: Header=BB15_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1006: ; in Loop: Header=BB15_995 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1007: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1190.i.i.i.i.i + ; in Loop: Header=BB15_995 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v78, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1008: ; in Loop: Header=BB15_995 Depth=1 + v_bfe_u32 v78, v43, 16, 1 + v_add3_u32 v78, v43, v78, s9 + ; implicit-def: $vgpr43 +; %bb.1009: ; %Flow801 + ; in Loop: Header=BB15_995 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_994 +; %bb.1010: ; in Loop: Header=BB15_995 Depth=1 + v_or_b32_e32 v78, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v43, vcc + s_branch .LBB15_994 +.LBB15_1011: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1196.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1013 +.LBB15_1012: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1209.i.i.i.i.i + ; in Loop: Header=BB15_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s10 + v_perm_b32 v28, v40, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1029 +.LBB15_1013: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1014: ; in Loop: Header=BB15_1013 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.1015: ; %Flow800 + ; in Loop: Header=BB15_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1016: ; in Loop: Header=BB15_1013 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1017: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1200.i.i.i.i.i + ; in Loop: Header=BB15_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1018: ; in Loop: Header=BB15_1013 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s9 + ; implicit-def: $vgpr29 +; %bb.1019: ; %Flow799 + ; in Loop: Header=BB15_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1020: ; in Loop: Header=BB15_1013 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1021: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1203.i.i.i.i.i + ; in Loop: Header=BB15_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1022: ; in Loop: Header=BB15_1013 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s9 + ; implicit-def: $vgpr41 +; %bb.1023: ; %Flow798 + ; in Loop: Header=BB15_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1024: ; in Loop: Header=BB15_1013 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1025: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1206.i.i.i.i.i + ; in Loop: Header=BB15_1013 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1026: ; in Loop: Header=BB15_1013 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.1027: ; %Flow797 + ; in Loop: Header=BB15_1013 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1012 +; %bb.1028: ; in Loop: Header=BB15_1013 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_1012 +.LBB15_1029: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1213 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1031 +.LBB15_1030: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1226.i.i.i.i.i + ; in Loop: Header=BB15_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1047 +.LBB15_1031: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1032: ; in Loop: Header=BB15_1031 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.1033: ; %Flow796 + ; in Loop: Header=BB15_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1034: ; in Loop: Header=BB15_1031 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1035: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1217.i.i.i.i.i + ; in Loop: Header=BB15_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1036: ; in Loop: Header=BB15_1031 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.1037: ; %Flow795 + ; in Loop: Header=BB15_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1038: ; in Loop: Header=BB15_1031 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1039: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1220.i.i.i.i.i + ; in Loop: Header=BB15_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1040: ; in Loop: Header=BB15_1031 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.1041: ; %Flow794 + ; in Loop: Header=BB15_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1042: ; in Loop: Header=BB15_1031 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1043: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1223.i.i.i.i.i + ; in Loop: Header=BB15_1031 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1044: ; in Loop: Header=BB15_1031 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s9 + ; implicit-def: $vgpr37 +; %bb.1045: ; %Flow793 + ; in Loop: Header=BB15_1031 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1030 +; %bb.1046: ; in Loop: Header=BB15_1031 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB15_1030 +.LBB15_1047: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1229.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_1049 +.LBB15_1048: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1242.i.i.i.i.i + ; in Loop: Header=BB15_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1065 +.LBB15_1049: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1050: ; in Loop: Header=BB15_1049 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.1051: ; %Flow792 + ; in Loop: Header=BB15_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1052: ; in Loop: Header=BB15_1049 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1053: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1233.i.i.i.i.i + ; in Loop: Header=BB15_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1054: ; in Loop: Header=BB15_1049 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.1055: ; %Flow791 + ; in Loop: Header=BB15_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1056: ; in Loop: Header=BB15_1049 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1057: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1236.i.i.i.i.i + ; in Loop: Header=BB15_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1058: ; in Loop: Header=BB15_1049 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.1059: ; %Flow790 + ; in Loop: Header=BB15_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1060: ; in Loop: Header=BB15_1049 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1061: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1239.i.i.i.i.i + ; in Loop: Header=BB15_1049 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1062: ; in Loop: Header=BB15_1049 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.1063: ; %Flow789 + ; in Loop: Header=BB15_1049 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1048 +; %bb.1064: ; in Loop: Header=BB15_1049 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_1048 +.LBB15_1065: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1246 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_1067 +.LBB15_1066: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1259.i.i.i.i.i + ; in Loop: Header=BB15_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1083 +.LBB15_1067: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1068: ; in Loop: Header=BB15_1067 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.1069: ; %Flow788 + ; in Loop: Header=BB15_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1070: ; in Loop: Header=BB15_1067 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1071: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1250.i.i.i.i.i + ; in Loop: Header=BB15_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1072: ; in Loop: Header=BB15_1067 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.1073: ; %Flow787 + ; in Loop: Header=BB15_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1074: ; in Loop: Header=BB15_1067 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1075: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1253.i.i.i.i.i + ; in Loop: Header=BB15_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1076: ; in Loop: Header=BB15_1067 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.1077: ; %Flow786 + ; in Loop: Header=BB15_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1078: ; in Loop: Header=BB15_1067 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1079: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1256.i.i.i.i.i + ; in Loop: Header=BB15_1067 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1080: ; in Loop: Header=BB15_1067 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.1081: ; %Flow785 + ; in Loop: Header=BB15_1067 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1066 +; %bb.1082: ; in Loop: Header=BB15_1067 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_1066 +.LBB15_1083: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1262.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_1085 +.LBB15_1084: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1275.i.i.i.i.i + ; in Loop: Header=BB15_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1101 +.LBB15_1085: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1086: ; in Loop: Header=BB15_1085 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.1087: ; %Flow784 + ; in Loop: Header=BB15_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1088: ; in Loop: Header=BB15_1085 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1089: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1266.i.i.i.i.i + ; in Loop: Header=BB15_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1090: ; in Loop: Header=BB15_1085 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.1091: ; %Flow783 + ; in Loop: Header=BB15_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1092: ; in Loop: Header=BB15_1085 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1093: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1269.i.i.i.i.i + ; in Loop: Header=BB15_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1094: ; in Loop: Header=BB15_1085 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.1095: ; %Flow782 + ; in Loop: Header=BB15_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1096: ; in Loop: Header=BB15_1085 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1097: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1272.i.i.i.i.i + ; in Loop: Header=BB15_1085 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1098: ; in Loop: Header=BB15_1085 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.1099: ; %Flow781 + ; in Loop: Header=BB15_1085 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1084 +; %bb.1100: ; in Loop: Header=BB15_1085 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_1084 +.LBB15_1101: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1407 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1102: + v_bfe_u32 v18, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v156, v18, s6 +; %bb.1103: ; %Flow780 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1104: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v156, vcc +; %bb.1105: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1472.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1106: + v_bfe_u32 v19, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v155, v19, s6 +; %bb.1107: ; %Flow779 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1108: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v155, vcc +; %bb.1109: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1475.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1110: + v_bfe_u32 v20, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v154, v20, s6 +; %bb.1111: ; %Flow778 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1112: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v154, vcc +; %bb.1113: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1478.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1114: + v_bfe_u32 v21, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v153, v21, s6 +; %bb.1115: ; %Flow777 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1116: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v153, vcc +; %bb.1117: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1481.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1118: + v_bfe_u32 v22, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v152, v22, s6 +; %bb.1119: ; %Flow776 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1120: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v152, vcc +; %bb.1121: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1484.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1122: + v_bfe_u32 v23, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v151, v23, s6 +; %bb.1123: ; %Flow775 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1124: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v151, vcc +; %bb.1125: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1487.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1126: + v_bfe_u32 v24, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v150, v24, s6 +; %bb.1127: ; %Flow774 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1128: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v150, vcc +; %bb.1129: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1490.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1130: + v_bfe_u32 v25, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v149, v25, s6 +; %bb.1131: ; %Flow773 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1132: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v149, vcc +; %bb.1133: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1493.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1134: + v_bfe_u32 v26, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v148, v26, s6 +; %bb.1135: ; %Flow772 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1136: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v148, vcc +; %bb.1137: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1496.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1138: + v_bfe_u32 v27, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v147, v27, s6 +; %bb.1139: ; %Flow771 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1140: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v147, vcc +; %bb.1141: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1499.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1142: + v_bfe_u32 v28, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v146, v28, s6 +; %bb.1143: ; %Flow770 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1144: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v146, vcc +; %bb.1145: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1502.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1146: + v_bfe_u32 v29, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v145, v29, s6 +; %bb.1147: ; %Flow769 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1148: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v145, vcc +; %bb.1149: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1505.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1150: + v_bfe_u32 v30, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v144, v30, s6 +; %bb.1151: ; %Flow768 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1152: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v144, vcc +; %bb.1153: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1508.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1154: + v_bfe_u32 v31, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v143, v31, s6 +; %bb.1155: ; %Flow767 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1156: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v143, vcc +; %bb.1157: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1511.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1158: + v_bfe_u32 v32, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v142, v32, s6 +; %bb.1159: ; %Flow766 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1160: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v142, vcc +; %bb.1161: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1514.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1162: + v_bfe_u32 v33, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v141, v33, s6 +; %bb.1163: ; %Flow765 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1164: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v141, vcc +; %bb.1165: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1517.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1166: + v_bfe_u32 v34, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v2, v34, s6 +; %bb.1167: ; %Flow764 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1168: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v2, vcc +; %bb.1169: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1520.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1170: + v_bfe_u32 v35, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v3, v35, s6 +; %bb.1171: ; %Flow763 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1172: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v3, vcc +; %bb.1173: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1523.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1174: + v_bfe_u32 v36, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v4, v36, s6 +; %bb.1175: ; %Flow762 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1176: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v4, vcc +; %bb.1177: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1526.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1178: + v_bfe_u32 v37, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v5, v37, s6 +; %bb.1179: ; %Flow761 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1180: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v5, vcc +; %bb.1181: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1529.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1182: + v_bfe_u32 v40, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v6, v40, s6 +; %bb.1183: ; %Flow760 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1184: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v6, vcc +; %bb.1185: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1532.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1186: + v_bfe_u32 v41, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v7, v41, s6 +; %bb.1187: ; %Flow759 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1188: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v7, vcc +; %bb.1189: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1535.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1190: + v_bfe_u32 v42, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v8, v42, s6 +; %bb.1191: ; %Flow758 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1192: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v8, vcc +; %bb.1193: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1538.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1194: + v_bfe_u32 v43, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v9, v43, s6 +; %bb.1195: ; %Flow757 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1196: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v78, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v78, v9, vcc +; %bb.1197: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1541.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1198: + v_bfe_u32 v78, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v10, v78, s6 +; %bb.1199: ; %Flow756 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1200: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v10, vcc +; %bb.1201: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1544.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1202: + v_bfe_u32 v79, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v11, v79, s6 +; %bb.1203: ; %Flow755 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1204: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v11, vcc +; %bb.1205: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1547.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1206: + v_bfe_u32 v80, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v12, v80, s6 +; %bb.1207: ; %Flow754 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1208: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v12, vcc +; %bb.1209: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1550.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1210: + v_bfe_u32 v81, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v13, v81, s6 +; %bb.1211: ; %Flow753 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1212: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v13, vcc +; %bb.1213: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1553.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1214: + v_bfe_u32 v82, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v14, v82, s6 +; %bb.1215: ; %Flow752 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1216: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v14, vcc +; %bb.1217: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1556.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1218: + v_bfe_u32 v83, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v15, v83, s6 +; %bb.1219: ; %Flow751 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1220: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v15, vcc +; %bb.1221: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1559.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1222: + v_bfe_u32 v84, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v16, v84, s6 +; %bb.1223: ; %Flow750 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1224: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v16, vcc +; %bb.1225: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1562.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v85, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s2, v85 + ; implicit-def: $vgpr85 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1226: + v_bfe_u32 v85, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v85, v17, v85, s6 +; %bb.1227: ; %Flow749 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1228: + v_mov_b32_e32 v85, 0 + v_accvgpr_write_b32 a0, v86 + v_or_b32_e32 v86, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v85 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v85, v86, v17, vcc + v_accvgpr_read_b32 v86, a0 +; %bb.1229: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E1566 + s_or_b64 exec, exec, s[2:3] + s_or_b32 s8, s18, 0x80 + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v78 offset:10240 + ds_write_b16_d16_hi v74, v79 offset:10368 + ds_write_b16_d16_hi v74, v80 offset:10496 + ds_write_b16_d16_hi v74, v81 offset:10624 + ds_write_b16_d16_hi v74, v82 offset:11264 + ds_write_b16_d16_hi v74, v83 offset:11392 + ds_write_b16_d16_hi v74, v84 offset:11520 + ds_write_b16_d16_hi v74, v85 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:384 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v78, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v79, 0 + s_branch .LBB15_1231 +.LBB15_1230: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i1629.i.i.i.i.i + ; in Loop: Header=BB15_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v82, v35, s11 + v_perm_b32 v34, v80, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:384 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1247 +.LBB15_1231: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1232: ; in Loop: Header=BB15_1231 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1233: ; %Flow748 + ; in Loop: Header=BB15_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1234: ; in Loop: Header=BB15_1231 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1235: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i1620.i.i.i.i.i + ; in Loop: Header=BB15_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v80, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1236: ; in Loop: Header=BB15_1231 Depth=1 + v_bfe_u32 v80, v35, 16, 1 + v_add3_u32 v80, v35, v80, s10 + ; implicit-def: $vgpr35 +; %bb.1237: ; %Flow747 + ; in Loop: Header=BB15_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1238: ; in Loop: Header=BB15_1231 Depth=1 + v_or_b32_e32 v80, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v35, vcc +; %bb.1239: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i1623.i.i.i.i.i + ; in Loop: Header=BB15_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v81, v78, v35 + v_and_b32_e32 v35, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1240: ; in Loop: Header=BB15_1231 Depth=1 + v_bfe_u32 v35, v81, 16, 1 + v_add3_u32 v35, v81, v35, s10 + ; implicit-def: $vgpr81 +; %bb.1241: ; %Flow746 + ; in Loop: Header=BB15_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1242: ; in Loop: Header=BB15_1231 Depth=1 + v_or_b32_e32 v35, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v81, vcc +; %bb.1243: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i1626.i.i.i.i.i + ; in Loop: Header=BB15_1231 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v81, 0xffff0000, v37 + v_add_f32_e32 v81, v31, v81 + v_and_b32_e32 v82, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s9, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1244: ; in Loop: Header=BB15_1231 Depth=1 + v_bfe_u32 v82, v81, 16, 1 + v_add3_u32 v82, v81, v82, s10 + ; implicit-def: $vgpr81 +; %bb.1245: ; %Flow745 + ; in Loop: Header=BB15_1231 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1230 +; %bb.1246: ; in Loop: Header=BB15_1231 Depth=1 + v_or_b32_e32 v82, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v82, v81, vcc + s_branch .LBB15_1230 +.LBB15_1247: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i1632.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:392 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_1249 +.LBB15_1248: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i1645.i.i.i.i.i + ; in Loop: Header=BB15_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v80, v33, s11 + v_perm_b32 v32, v78, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:392 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1265 +.LBB15_1249: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1250: ; in Loop: Header=BB15_1249 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1251: ; %Flow744 + ; in Loop: Header=BB15_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1252: ; in Loop: Header=BB15_1249 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1253: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i1636.i.i.i.i.i + ; in Loop: Header=BB15_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v78, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1254: ; in Loop: Header=BB15_1249 Depth=1 + v_bfe_u32 v78, v33, 16, 1 + v_add3_u32 v78, v33, v78, s10 + ; implicit-def: $vgpr33 +; %bb.1255: ; %Flow743 + ; in Loop: Header=BB15_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1256: ; in Loop: Header=BB15_1249 Depth=1 + v_or_b32_e32 v78, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v33, vcc +; %bb.1257: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i1639.i.i.i.i.i + ; in Loop: Header=BB15_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v79, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1258: ; in Loop: Header=BB15_1249 Depth=1 + v_bfe_u32 v33, v79, 16, 1 + v_add3_u32 v33, v79, v33, s10 + ; implicit-def: $vgpr79 +; %bb.1259: ; %Flow742 + ; in Loop: Header=BB15_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1260: ; in Loop: Header=BB15_1249 Depth=1 + v_or_b32_e32 v33, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v79, vcc +; %bb.1261: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i1642.i.i.i.i.i + ; in Loop: Header=BB15_1249 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v35 + v_add_f32_e32 v79, v37, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1262: ; in Loop: Header=BB15_1249 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1263: ; %Flow741 + ; in Loop: Header=BB15_1249 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1248 +; %bb.1264: ; in Loop: Header=BB15_1249 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB15_1248 +.LBB15_1265: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1649 + s_or_b64 exec, exec, s[2:3] + v_add3_u32 v34, v40, v77, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_1267 +.LBB15_1266: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i1662.i.i.i.i.i + ; in Loop: Header=BB15_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1283 +.LBB15_1267: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1268: ; in Loop: Header=BB15_1267 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1269: ; %Flow740 + ; in Loop: Header=BB15_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1270: ; in Loop: Header=BB15_1267 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1271: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i1653.i.i.i.i.i + ; in Loop: Header=BB15_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1272: ; in Loop: Header=BB15_1267 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1273: ; %Flow739 + ; in Loop: Header=BB15_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1274: ; in Loop: Header=BB15_1267 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1275: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i1656.i.i.i.i.i + ; in Loop: Header=BB15_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1276: ; in Loop: Header=BB15_1267 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1277: ; %Flow738 + ; in Loop: Header=BB15_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1278: ; in Loop: Header=BB15_1267 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1279: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i1659.i.i.i.i.i + ; in Loop: Header=BB15_1267 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1280: ; in Loop: Header=BB15_1267 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1281: ; %Flow737 + ; in Loop: Header=BB15_1267 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1266 +; %bb.1282: ; in Loop: Header=BB15_1267 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB15_1266 +.LBB15_1283: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i1665.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1285 +.LBB15_1284: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i1678.i.i.i.i.i + ; in Loop: Header=BB15_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1301 +.LBB15_1285: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1286: ; in Loop: Header=BB15_1285 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1287: ; %Flow736 + ; in Loop: Header=BB15_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1288: ; in Loop: Header=BB15_1285 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1289: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i1669.i.i.i.i.i + ; in Loop: Header=BB15_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1290: ; in Loop: Header=BB15_1285 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1291: ; %Flow735 + ; in Loop: Header=BB15_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1292: ; in Loop: Header=BB15_1285 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1293: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i1672.i.i.i.i.i + ; in Loop: Header=BB15_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1294: ; in Loop: Header=BB15_1285 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1295: ; %Flow734 + ; in Loop: Header=BB15_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1296: ; in Loop: Header=BB15_1285 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1297: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i1675.i.i.i.i.i + ; in Loop: Header=BB15_1285 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1298: ; in Loop: Header=BB15_1285 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1299: ; %Flow733 + ; in Loop: Header=BB15_1285 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1284 +; %bb.1300: ; in Loop: Header=BB15_1285 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_1284 +.LBB15_1301: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1682 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1303 +.LBB15_1302: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i1695.i.i.i.i.i + ; in Loop: Header=BB15_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1319 +.LBB15_1303: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1304: ; in Loop: Header=BB15_1303 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1305: ; %Flow732 + ; in Loop: Header=BB15_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1306: ; in Loop: Header=BB15_1303 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1307: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i1686.i.i.i.i.i + ; in Loop: Header=BB15_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1308: ; in Loop: Header=BB15_1303 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1309: ; %Flow731 + ; in Loop: Header=BB15_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1310: ; in Loop: Header=BB15_1303 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1311: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i1689.i.i.i.i.i + ; in Loop: Header=BB15_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1312: ; in Loop: Header=BB15_1303 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1313: ; %Flow730 + ; in Loop: Header=BB15_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1314: ; in Loop: Header=BB15_1303 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1315: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i1692.i.i.i.i.i + ; in Loop: Header=BB15_1303 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1316: ; in Loop: Header=BB15_1303 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1317: ; %Flow729 + ; in Loop: Header=BB15_1303 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1302 +; %bb.1318: ; in Loop: Header=BB15_1303 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB15_1302 +.LBB15_1319: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i1698.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_1321 +.LBB15_1320: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i1711.i.i.i.i.i + ; in Loop: Header=BB15_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1337 +.LBB15_1321: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1322: ; in Loop: Header=BB15_1321 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1323: ; %Flow728 + ; in Loop: Header=BB15_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1324: ; in Loop: Header=BB15_1321 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1325: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i1702.i.i.i.i.i + ; in Loop: Header=BB15_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1326: ; in Loop: Header=BB15_1321 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1327: ; %Flow727 + ; in Loop: Header=BB15_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1328: ; in Loop: Header=BB15_1321 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1329: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i1705.i.i.i.i.i + ; in Loop: Header=BB15_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1330: ; in Loop: Header=BB15_1321 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1331: ; %Flow726 + ; in Loop: Header=BB15_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1332: ; in Loop: Header=BB15_1321 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1333: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i1708.i.i.i.i.i + ; in Loop: Header=BB15_1321 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1334: ; in Loop: Header=BB15_1321 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1335: ; %Flow725 + ; in Loop: Header=BB15_1321 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1320 +; %bb.1336: ; in Loop: Header=BB15_1321 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_1320 +.LBB15_1337: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til1715 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_1339 +.LBB15_1338: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i1728.i.i.i.i.i + ; in Loop: Header=BB15_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1355 +.LBB15_1339: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1340: ; in Loop: Header=BB15_1339 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1341: ; %Flow724 + ; in Loop: Header=BB15_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1342: ; in Loop: Header=BB15_1339 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1343: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i1719.i.i.i.i.i + ; in Loop: Header=BB15_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1344: ; in Loop: Header=BB15_1339 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1345: ; %Flow723 + ; in Loop: Header=BB15_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1346: ; in Loop: Header=BB15_1339 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1347: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i1722.i.i.i.i.i + ; in Loop: Header=BB15_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1348: ; in Loop: Header=BB15_1339 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1349: ; %Flow722 + ; in Loop: Header=BB15_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1350: ; in Loop: Header=BB15_1339 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1351: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i1725.i.i.i.i.i + ; in Loop: Header=BB15_1339 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1352: ; in Loop: Header=BB15_1339 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1353: ; %Flow721 + ; in Loop: Header=BB15_1339 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1338 +; %bb.1354: ; in Loop: Header=BB15_1339 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_1338 +.LBB15_1355: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i1731.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_1357 +.LBB15_1356: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i1744.i.i.i.i.i + ; in Loop: Header=BB15_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1373 +.LBB15_1357: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1358: ; in Loop: Header=BB15_1357 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1359: ; %Flow720 + ; in Loop: Header=BB15_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1360: ; in Loop: Header=BB15_1357 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1361: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i1735.i.i.i.i.i + ; in Loop: Header=BB15_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1362: ; in Loop: Header=BB15_1357 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1363: ; %Flow719 + ; in Loop: Header=BB15_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1364: ; in Loop: Header=BB15_1357 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1365: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i1738.i.i.i.i.i + ; in Loop: Header=BB15_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1366: ; in Loop: Header=BB15_1357 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1367: ; %Flow718 + ; in Loop: Header=BB15_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1368: ; in Loop: Header=BB15_1357 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1369: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i1741.i.i.i.i.i + ; in Loop: Header=BB15_1357 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1370: ; in Loop: Header=BB15_1357 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1371: ; %Flow717 + ; in Loop: Header=BB15_1357 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1356 +; %bb.1372: ; in Loop: Header=BB15_1357 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_1356 +.LBB15_1373: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1876 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1374: + v_bfe_u32 v18, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v140, v18, s6 +; %bb.1375: ; %Flow716 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1376: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v140, vcc +; %bb.1377: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1941.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1378: + v_bfe_u32 v19, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v139, v19, s6 +; %bb.1379: ; %Flow715 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1380: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v139, vcc +; %bb.1381: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1944.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1382: + v_bfe_u32 v20, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v138, v20, s6 +; %bb.1383: ; %Flow714 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1384: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v138, vcc +; %bb.1385: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1947.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1386: + v_bfe_u32 v21, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v137, v21, s6 +; %bb.1387: ; %Flow713 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1388: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v137, vcc +; %bb.1389: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1950.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1390: + v_bfe_u32 v22, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v136, v22, s6 +; %bb.1391: ; %Flow712 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1392: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v136, vcc +; %bb.1393: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1953.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1394: + v_bfe_u32 v23, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v135, v23, s6 +; %bb.1395: ; %Flow711 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1396: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v135, vcc +; %bb.1397: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1956.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1398: + v_bfe_u32 v24, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v134, v24, s6 +; %bb.1399: ; %Flow710 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1400: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v134, vcc +; %bb.1401: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1959.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1402: + v_bfe_u32 v25, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v133, v25, s6 +; %bb.1403: ; %Flow709 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1404: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v133, vcc +; %bb.1405: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1962.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1406: + v_bfe_u32 v26, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v132, v26, s6 +; %bb.1407: ; %Flow708 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1408: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v132, vcc +; %bb.1409: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1965.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1410: + v_bfe_u32 v27, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v131, v27, s6 +; %bb.1411: ; %Flow707 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1412: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v131, vcc +; %bb.1413: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1968.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1414: + v_bfe_u32 v28, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v130, v28, s6 +; %bb.1415: ; %Flow706 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1416: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v130, vcc +; %bb.1417: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1971.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1418: + v_bfe_u32 v29, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v129, v29, s6 +; %bb.1419: ; %Flow705 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1420: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v129, vcc +; %bb.1421: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1974.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1422: + v_bfe_u32 v30, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v128, v30, s6 +; %bb.1423: ; %Flow704 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1424: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v128, vcc +; %bb.1425: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1977.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1426: + v_bfe_u32 v31, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v127, v31, s6 +; %bb.1427: ; %Flow703 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1428: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v127, vcc +; %bb.1429: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1980.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1430: + v_bfe_u32 v32, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v126, v32, s6 +; %bb.1431: ; %Flow702 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1432: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v126, vcc +; %bb.1433: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1983.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1434: + v_bfe_u32 v33, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v124, v33, s6 +; %bb.1435: ; %Flow701 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1436: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v124, vcc +; %bb.1437: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1986.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1438: + v_bfe_u32 v34, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v125, v34, s6 +; %bb.1439: ; %Flow700 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1440: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v125, vcc +; %bb.1441: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1989.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1442: + v_bfe_u32 v35, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v123, v35, s6 +; %bb.1443: ; %Flow699 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1444: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v123, vcc +; %bb.1445: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1992.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1446: + v_bfe_u32 v36, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v122, v36, s6 +; %bb.1447: ; %Flow698 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1448: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v122, vcc +; %bb.1449: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1995.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1450: + v_bfe_u32 v37, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v121, v37, s6 +; %bb.1451: ; %Flow697 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1452: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v121, vcc +; %bb.1453: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1998.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1454: + v_bfe_u32 v40, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v120, v40, s6 +; %bb.1455: ; %Flow696 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1456: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v120, vcc +; %bb.1457: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2001.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1458: + v_bfe_u32 v41, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v119, v41, s6 +; %bb.1459: ; %Flow695 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1460: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v119, vcc +; %bb.1461: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2004.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1462: + v_bfe_u32 v42, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v118, v42, s6 +; %bb.1463: ; %Flow694 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1464: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v118, vcc +; %bb.1465: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2007.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1466: + v_bfe_u32 v43, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v117, v43, s6 +; %bb.1467: ; %Flow693 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1468: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v77, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v117, vcc +; %bb.1469: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2010.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v77, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1470: + v_bfe_u32 v77, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v116, v77, s6 +; %bb.1471: ; %Flow692 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1472: + v_mov_b32_e32 v77, 0 + v_or_b32_e32 v78, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v116, vcc +; %bb.1473: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2013.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v78, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1474: + v_bfe_u32 v78, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v115, v78, s6 +; %bb.1475: ; %Flow691 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1476: + v_mov_b32_e32 v78, 0 + v_or_b32_e32 v79, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v115, vcc +; %bb.1477: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2016.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v79, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1478: + v_bfe_u32 v79, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v114, v79, s6 +; %bb.1479: ; %Flow690 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1480: + v_mov_b32_e32 v79, 0 + v_or_b32_e32 v80, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v114, vcc +; %bb.1481: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2019.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v80, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1482: + v_bfe_u32 v80, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v113, v80, s6 +; %bb.1483: ; %Flow689 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1484: + v_mov_b32_e32 v80, 0 + v_or_b32_e32 v81, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v113, vcc +; %bb.1485: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2022.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v81, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1486: + v_bfe_u32 v81, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v112, v81, s6 +; %bb.1487: ; %Flow688 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1488: + v_mov_b32_e32 v81, 0 + v_or_b32_e32 v82, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v112, vcc +; %bb.1489: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2025.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v82, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1490: + v_bfe_u32 v82, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v111, v82, s6 +; %bb.1491: ; %Flow687 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1492: + v_mov_b32_e32 v82, 0 + v_or_b32_e32 v83, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v111, vcc +; %bb.1493: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2028.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1494: + v_bfe_u32 v83, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v110, v83, s6 +; %bb.1495: ; %Flow686 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1496: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v110, vcc +; %bb.1497: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2031.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v84, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1498: + v_bfe_u32 v84, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v109, v84, s6 +; %bb.1499: ; %Flow685 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1500: + v_mov_b32_e32 v84, 0 + v_or_b32_e32 v85, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v109, vcc +; %bb.1501: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2035 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:256 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v41, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v77, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v78, 0 + s_branch .LBB15_1503 +.LBB15_1502: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2098.i.i.i.i.i + ; in Loop: Header=BB15_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v81, v35, s11 + v_perm_b32 v34, v79, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:256 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1519 +.LBB15_1503: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v41, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1504: ; in Loop: Header=BB15_1503 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1505: ; %Flow684 + ; in Loop: Header=BB15_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1506: ; in Loop: Header=BB15_1503 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1507: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2089.i.i.i.i.i + ; in Loop: Header=BB15_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v79, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1508: ; in Loop: Header=BB15_1503 Depth=1 + v_bfe_u32 v79, v35, 16, 1 + v_add3_u32 v79, v35, v79, s10 + ; implicit-def: $vgpr35 +; %bb.1509: ; %Flow683 + ; in Loop: Header=BB15_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1510: ; in Loop: Header=BB15_1503 Depth=1 + v_or_b32_e32 v79, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v35, vcc +; %bb.1511: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2092.i.i.i.i.i + ; in Loop: Header=BB15_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v80, v77, v35 + v_and_b32_e32 v35, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1512: ; in Loop: Header=BB15_1503 Depth=1 + v_bfe_u32 v35, v80, 16, 1 + v_add3_u32 v35, v80, v35, s10 + ; implicit-def: $vgpr80 +; %bb.1513: ; %Flow682 + ; in Loop: Header=BB15_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1514: ; in Loop: Header=BB15_1503 Depth=1 + v_or_b32_e32 v35, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v80, vcc +; %bb.1515: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2095.i.i.i.i.i + ; in Loop: Header=BB15_1503 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v80, 0xffff0000, v37 + v_add_f32_e32 v80, v31, v80 + v_and_b32_e32 v81, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s9, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1516: ; in Loop: Header=BB15_1503 Depth=1 + v_bfe_u32 v81, v80, 16, 1 + v_add3_u32 v81, v80, v81, s10 + ; implicit-def: $vgpr80 +; %bb.1517: ; %Flow681 + ; in Loop: Header=BB15_1503 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1502 +; %bb.1518: ; in Loop: Header=BB15_1503 Depth=1 + v_or_b32_e32 v81, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v81, v80, vcc + s_branch .LBB15_1502 +.LBB15_1519: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2101.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:264 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_1521 +.LBB15_1520: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2114.i.i.i.i.i + ; in Loop: Header=BB15_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v79, v33, s11 + v_perm_b32 v32, v77, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:264 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1537 +.LBB15_1521: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1522: ; in Loop: Header=BB15_1521 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1523: ; %Flow680 + ; in Loop: Header=BB15_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1524: ; in Loop: Header=BB15_1521 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1525: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2105.i.i.i.i.i + ; in Loop: Header=BB15_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v77, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1526: ; in Loop: Header=BB15_1521 Depth=1 + v_bfe_u32 v77, v33, 16, 1 + v_add3_u32 v77, v33, v77, s10 + ; implicit-def: $vgpr33 +; %bb.1527: ; %Flow679 + ; in Loop: Header=BB15_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1528: ; in Loop: Header=BB15_1521 Depth=1 + v_or_b32_e32 v77, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v33, vcc +; %bb.1529: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2108.i.i.i.i.i + ; in Loop: Header=BB15_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v78, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1530: ; in Loop: Header=BB15_1521 Depth=1 + v_bfe_u32 v33, v78, 16, 1 + v_add3_u32 v33, v78, v33, s10 + ; implicit-def: $vgpr78 +; %bb.1531: ; %Flow678 + ; in Loop: Header=BB15_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1532: ; in Loop: Header=BB15_1521 Depth=1 + v_or_b32_e32 v33, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v78, vcc +; %bb.1533: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2111.i.i.i.i.i + ; in Loop: Header=BB15_1521 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v78, 0xffff0000, v35 + v_add_f32_e32 v78, v37, v78 + v_and_b32_e32 v79, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s9, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1534: ; in Loop: Header=BB15_1521 Depth=1 + v_bfe_u32 v79, v78, 16, 1 + v_add3_u32 v79, v78, v79, s10 + ; implicit-def: $vgpr78 +; %bb.1535: ; %Flow677 + ; in Loop: Header=BB15_1521 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1520 +; %bb.1536: ; in Loop: Header=BB15_1521 Depth=1 + v_or_b32_e32 v79, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v79, v78, vcc + s_branch .LBB15_1520 +.LBB15_1537: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2118 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a2 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v40, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v41, 0 + s_branch .LBB15_1539 +.LBB15_1538: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2131.i.i.i.i.i + ; in Loop: Header=BB15_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v77, v31, s11 + v_perm_b32 v30, v42, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1555 +.LBB15_1539: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1540: ; in Loop: Header=BB15_1539 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1541: ; %Flow676 + ; in Loop: Header=BB15_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1542: ; in Loop: Header=BB15_1539 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1543: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2122.i.i.i.i.i + ; in Loop: Header=BB15_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v42, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1544: ; in Loop: Header=BB15_1539 Depth=1 + v_bfe_u32 v42, v31, 16, 1 + v_add3_u32 v42, v31, v42, s10 + ; implicit-def: $vgpr31 +; %bb.1545: ; %Flow675 + ; in Loop: Header=BB15_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1546: ; in Loop: Header=BB15_1539 Depth=1 + v_or_b32_e32 v42, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v31, vcc +; %bb.1547: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2125.i.i.i.i.i + ; in Loop: Header=BB15_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v43, v40, v31 + v_and_b32_e32 v31, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1548: ; in Loop: Header=BB15_1539 Depth=1 + v_bfe_u32 v31, v43, 16, 1 + v_add3_u32 v31, v43, v31, s10 + ; implicit-def: $vgpr43 +; %bb.1549: ; %Flow674 + ; in Loop: Header=BB15_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1550: ; in Loop: Header=BB15_1539 Depth=1 + v_or_b32_e32 v31, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v43, vcc +; %bb.1551: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2128.i.i.i.i.i + ; in Loop: Header=BB15_1539 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v33 + v_add_f32_e32 v43, v27, v43 + v_and_b32_e32 v77, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s9, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1552: ; in Loop: Header=BB15_1539 Depth=1 + v_bfe_u32 v77, v43, 16, 1 + v_add3_u32 v77, v43, v77, s10 + ; implicit-def: $vgpr43 +; %bb.1553: ; %Flow673 + ; in Loop: Header=BB15_1539 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1538 +; %bb.1554: ; in Loop: Header=BB15_1539 Depth=1 + v_or_b32_e32 v77, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v77, v43, vcc + s_branch .LBB15_1538 +.LBB15_1555: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2134.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1557 +.LBB15_1556: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2147.i.i.i.i.i + ; in Loop: Header=BB15_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v42, v29, s11 + v_perm_b32 v28, v40, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1573 +.LBB15_1557: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1558: ; in Loop: Header=BB15_1557 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1559: ; %Flow672 + ; in Loop: Header=BB15_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1560: ; in Loop: Header=BB15_1557 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1561: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2138.i.i.i.i.i + ; in Loop: Header=BB15_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v40, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1562: ; in Loop: Header=BB15_1557 Depth=1 + v_bfe_u32 v40, v29, 16, 1 + v_add3_u32 v40, v29, v40, s10 + ; implicit-def: $vgpr29 +; %bb.1563: ; %Flow671 + ; in Loop: Header=BB15_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1564: ; in Loop: Header=BB15_1557 Depth=1 + v_or_b32_e32 v40, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v29, vcc +; %bb.1565: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2141.i.i.i.i.i + ; in Loop: Header=BB15_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v41, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1566: ; in Loop: Header=BB15_1557 Depth=1 + v_bfe_u32 v29, v41, 16, 1 + v_add3_u32 v29, v41, v29, s10 + ; implicit-def: $vgpr41 +; %bb.1567: ; %Flow670 + ; in Loop: Header=BB15_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1568: ; in Loop: Header=BB15_1557 Depth=1 + v_or_b32_e32 v29, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v41, vcc +; %bb.1569: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2144.i.i.i.i.i + ; in Loop: Header=BB15_1557 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v31 + v_add_f32_e32 v41, v33, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s9, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1570: ; in Loop: Header=BB15_1557 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s10 + ; implicit-def: $vgpr41 +; %bb.1571: ; %Flow669 + ; in Loop: Header=BB15_1557 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1556 +; %bb.1572: ; in Loop: Header=BB15_1557 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_1556 +.LBB15_1573: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2151 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1575 +.LBB15_1574: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2164.i.i.i.i.i + ; in Loop: Header=BB15_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v40, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1591 +.LBB15_1575: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1576: ; in Loop: Header=BB15_1575 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1577: ; %Flow668 + ; in Loop: Header=BB15_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1578: ; in Loop: Header=BB15_1575 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1579: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2155.i.i.i.i.i + ; in Loop: Header=BB15_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1580: ; in Loop: Header=BB15_1575 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1581: ; %Flow667 + ; in Loop: Header=BB15_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1582: ; in Loop: Header=BB15_1575 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1583: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2158.i.i.i.i.i + ; in Loop: Header=BB15_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1584: ; in Loop: Header=BB15_1575 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1585: ; %Flow666 + ; in Loop: Header=BB15_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1586: ; in Loop: Header=BB15_1575 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1587: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2161.i.i.i.i.i + ; in Loop: Header=BB15_1575 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v40, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1588: ; in Loop: Header=BB15_1575 Depth=1 + v_bfe_u32 v40, v37, 16, 1 + v_add3_u32 v40, v37, v40, s10 + ; implicit-def: $vgpr37 +; %bb.1589: ; %Flow665 + ; in Loop: Header=BB15_1575 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1574 +; %bb.1590: ; in Loop: Header=BB15_1575 Depth=1 + v_or_b32_e32 v40, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v37, vcc + s_branch .LBB15_1574 +.LBB15_1591: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2167.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_1593 +.LBB15_1592: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2180.i.i.i.i.i + ; in Loop: Header=BB15_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1609 +.LBB15_1593: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1594: ; in Loop: Header=BB15_1593 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1595: ; %Flow664 + ; in Loop: Header=BB15_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1596: ; in Loop: Header=BB15_1593 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1597: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2171.i.i.i.i.i + ; in Loop: Header=BB15_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1598: ; in Loop: Header=BB15_1593 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1599: ; %Flow663 + ; in Loop: Header=BB15_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1600: ; in Loop: Header=BB15_1593 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1601: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2174.i.i.i.i.i + ; in Loop: Header=BB15_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1602: ; in Loop: Header=BB15_1593 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1603: ; %Flow662 + ; in Loop: Header=BB15_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1604: ; in Loop: Header=BB15_1593 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1605: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2177.i.i.i.i.i + ; in Loop: Header=BB15_1593 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1606: ; in Loop: Header=BB15_1593 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1607: ; %Flow661 + ; in Loop: Header=BB15_1593 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1592 +; %bb.1608: ; in Loop: Header=BB15_1593 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_1592 +.LBB15_1609: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2184 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_1611 +.LBB15_1610: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2197.i.i.i.i.i + ; in Loop: Header=BB15_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1627 +.LBB15_1611: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1612: ; in Loop: Header=BB15_1611 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1613: ; %Flow660 + ; in Loop: Header=BB15_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1614: ; in Loop: Header=BB15_1611 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1615: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2188.i.i.i.i.i + ; in Loop: Header=BB15_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1616: ; in Loop: Header=BB15_1611 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1617: ; %Flow659 + ; in Loop: Header=BB15_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1618: ; in Loop: Header=BB15_1611 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1619: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2191.i.i.i.i.i + ; in Loop: Header=BB15_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1620: ; in Loop: Header=BB15_1611 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1621: ; %Flow658 + ; in Loop: Header=BB15_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1622: ; in Loop: Header=BB15_1611 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1623: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2194.i.i.i.i.i + ; in Loop: Header=BB15_1611 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1624: ; in Loop: Header=BB15_1611 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1625: ; %Flow657 + ; in Loop: Header=BB15_1611 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1610 +; %bb.1626: ; in Loop: Header=BB15_1611 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_1610 +.LBB15_1627: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2200.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_1629 +.LBB15_1628: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2213.i.i.i.i.i + ; in Loop: Header=BB15_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1645 +.LBB15_1629: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1630: ; in Loop: Header=BB15_1629 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1631: ; %Flow656 + ; in Loop: Header=BB15_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1632: ; in Loop: Header=BB15_1629 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1633: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2204.i.i.i.i.i + ; in Loop: Header=BB15_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1634: ; in Loop: Header=BB15_1629 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1635: ; %Flow655 + ; in Loop: Header=BB15_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1636: ; in Loop: Header=BB15_1629 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1637: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2207.i.i.i.i.i + ; in Loop: Header=BB15_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1638: ; in Loop: Header=BB15_1629 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1639: ; %Flow654 + ; in Loop: Header=BB15_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1640: ; in Loop: Header=BB15_1629 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1641: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2210.i.i.i.i.i + ; in Loop: Header=BB15_1629 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1642: ; in Loop: Header=BB15_1629 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1643: ; %Flow653 + ; in Loop: Header=BB15_1629 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1628 +; %bb.1644: ; in Loop: Header=BB15_1629 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_1628 +.LBB15_1645: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2345 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1646: + v_bfe_u32 v18, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v108, v18, s6 +; %bb.1647: ; %Flow652 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1648: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v108, vcc +; %bb.1649: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2410.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1650: + v_bfe_u32 v19, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v107, v19, s6 +; %bb.1651: ; %Flow651 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1652: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v107, vcc +; %bb.1653: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2413.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v20, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1654: + v_bfe_u32 v20, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v106, v20, s6 +; %bb.1655: ; %Flow650 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1656: + v_mov_b32_e32 v20, 0 + v_or_b32_e32 v21, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v106, vcc +; %bb.1657: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2416.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1658: + v_bfe_u32 v21, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v105, v21, s6 +; %bb.1659: ; %Flow649 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1660: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v105, vcc +; %bb.1661: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2419.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1662: + v_bfe_u32 v22, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v104, v22, s6 +; %bb.1663: ; %Flow648 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1664: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v104, vcc +; %bb.1665: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2422.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1666: + v_bfe_u32 v23, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v103, v23, s6 +; %bb.1667: ; %Flow647 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1668: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v103, vcc +; %bb.1669: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2425.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1670: + v_bfe_u32 v24, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v102, v24, s6 +; %bb.1671: ; %Flow646 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1672: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v102, vcc +; %bb.1673: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2428.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1674: + v_bfe_u32 v25, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v101, v25, s6 +; %bb.1675: ; %Flow645 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1676: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v101, vcc +; %bb.1677: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2431.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1678: + v_bfe_u32 v26, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v100, v26, s6 +; %bb.1679: ; %Flow644 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1680: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v100, vcc +; %bb.1681: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2434.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1682: + v_bfe_u32 v27, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v99, v27, s6 +; %bb.1683: ; %Flow643 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1684: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v99, vcc +; %bb.1685: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2437.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1686: + v_bfe_u32 v28, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v98, v28, s6 +; %bb.1687: ; %Flow642 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1688: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v98, vcc +; %bb.1689: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2440.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1690: + v_bfe_u32 v29, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v97, v29, s6 +; %bb.1691: ; %Flow641 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1692: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v97, vcc +; %bb.1693: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2443.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1694: + v_bfe_u32 v30, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v96, v30, s6 +; %bb.1695: ; %Flow640 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1696: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v96, vcc +; %bb.1697: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2446.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1698: + v_bfe_u32 v31, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v95, v31, s6 +; %bb.1699: ; %Flow639 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1700: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v95, vcc +; %bb.1701: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2449.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1702: + v_bfe_u32 v32, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v94, v32, s6 +; %bb.1703: ; %Flow638 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1704: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v94, vcc +; %bb.1705: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2452.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1706: + v_bfe_u32 v33, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v92, v33, s6 +; %bb.1707: ; %Flow637 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1708: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v92, vcc +; %bb.1709: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2455.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1710: + v_bfe_u32 v34, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v93, v34, s6 +; %bb.1711: ; %Flow636 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1712: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v93, vcc +; %bb.1713: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2458.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1714: + v_bfe_u32 v35, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v91, v35, s6 +; %bb.1715: ; %Flow635 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1716: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v91, vcc +; %bb.1717: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2461.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1718: + v_bfe_u32 v36, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v90, v36, s6 +; %bb.1719: ; %Flow634 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1720: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v90, vcc +; %bb.1721: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2464.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1722: + v_bfe_u32 v37, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v89, v37, s6 +; %bb.1723: ; %Flow633 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1724: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v40, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v40, v89, vcc +; %bb.1725: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2467.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1726: + v_bfe_u32 v40, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v88, v40, s6 +; %bb.1727: ; %Flow632 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1728: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v88, vcc +; %bb.1729: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2470.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a41 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1730: + v_accvgpr_read_b32 v42, a41 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.1731: ; %Flow631 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1732: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a41 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.1733: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2473.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a40 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1734: + v_accvgpr_read_b32 v43, a40 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.1735: ; %Flow630 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1736: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a40 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.1737: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2476.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a23 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1738: + v_accvgpr_read_b32 v77, a23 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.1739: ; %Flow629 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1740: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a23 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.1741: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2479.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a22 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1742: + v_accvgpr_read_b32 v78, a22 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.1743: ; %Flow628 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1744: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a22 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.1745: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2482.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a21 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1746: + v_accvgpr_read_b32 v79, a21 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.1747: ; %Flow627 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1748: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a21 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.1749: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2485.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a20 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1750: + v_accvgpr_read_b32 v80, a20 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.1751: ; %Flow626 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1752: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a20 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.1753: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2488.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a19 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1754: + v_accvgpr_read_b32 v81, a19 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.1755: ; %Flow625 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1756: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a19 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.1757: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2491.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a18 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1758: + v_accvgpr_read_b32 v82, a18 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.1759: ; %Flow624 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1760: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a18 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.1761: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2494.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a17 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1762: + v_accvgpr_read_b32 v83, a17 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.1763: ; %Flow623 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1764: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a17 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.1765: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2497.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1766: + v_bfe_u32 v83, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v87, v83, s6 +; %bb.1767: ; %Flow622 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1768: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v87, vcc +; %bb.1769: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2500.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v84, a16 + v_and_b32_e32 v84, 0x7f800000, v84 + v_cmp_ne_u32_e32 vcc, s2, v84 + ; implicit-def: $vgpr84 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1770: + v_accvgpr_read_b32 v85, a16 + v_bfe_u32 v84, v85, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v84, v85, v84, s6 +; %bb.1771: ; %Flow621 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1772: + v_mov_b32_e32 v84, 0 + v_accvgpr_write_b32 a0, v87 + v_accvgpr_read_b32 v87, a16 + v_or_b32_e32 v85, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v84 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v84, v85, v87, vcc + v_accvgpr_read_b32 v87, a0 +; %bb.1773: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2504 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v40 offset:9216 + ds_write_b16_d16_hi v74, v41 offset:9344 + ds_write_b16_d16_hi v74, v42 offset:9472 + ds_write_b16_d16_hi v74, v43 offset:9600 + ds_write_b16_d16_hi v74, v77 offset:10240 + ds_write_b16_d16_hi v74, v78 offset:10368 + ds_write_b16_d16_hi v74, v79 offset:10496 + ds_write_b16_d16_hi v74, v80 offset:10624 + ds_write_b16_d16_hi v74, v81 offset:11264 + ds_write_b16_d16_hi v74, v82 offset:11392 + ds_write_b16_d16_hi v74, v83 offset:11520 + ds_write_b16_d16_hi v74, v84 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v20, s2, v75 + v_add_u32_e32 v18, s8, v20 + v_mul_lo_u32 v40, v18, s16 + v_ashrrev_i32_e32 v41, 31, v40 + v_lshl_add_u64 v[18:19], v[40:41], 0, v[38:39] + v_lshl_add_u64 v[42:43], v[18:19], 1, s[0:1] + global_load_dwordx2 v[36:37], v[42:43], off offset:128 + v_lshl_or_b32 v18, v20, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v41, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v77, 0 + s_branch .LBB15_1775 +.LBB15_1774: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i2567.i.i.i.i.i + ; in Loop: Header=BB15_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v80, v35, s11 + v_perm_b32 v34, v78, v34, s11 + global_atomic_cmpswap_x2 v[34:35], v[42:43], v[34:37], off offset:128 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1791 +.LBB15_1775: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1776: ; in Loop: Header=BB15_1775 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s10 + ; implicit-def: $vgpr35 +; %bb.1777: ; %Flow620 + ; in Loop: Header=BB15_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1778: ; in Loop: Header=BB15_1775 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.1779: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i2558.i.i.i.i.i + ; in Loop: Header=BB15_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v78, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1780: ; in Loop: Header=BB15_1775 Depth=1 + v_bfe_u32 v78, v35, 16, 1 + v_add3_u32 v78, v35, v78, s10 + ; implicit-def: $vgpr35 +; %bb.1781: ; %Flow619 + ; in Loop: Header=BB15_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1782: ; in Loop: Header=BB15_1775 Depth=1 + v_or_b32_e32 v78, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v35, vcc +; %bb.1783: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i2561.i.i.i.i.i + ; in Loop: Header=BB15_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v79, v41, v35 + v_and_b32_e32 v35, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1784: ; in Loop: Header=BB15_1775 Depth=1 + v_bfe_u32 v35, v79, 16, 1 + v_add3_u32 v35, v79, v35, s10 + ; implicit-def: $vgpr79 +; %bb.1785: ; %Flow618 + ; in Loop: Header=BB15_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1786: ; in Loop: Header=BB15_1775 Depth=1 + v_or_b32_e32 v35, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v79, vcc +; %bb.1787: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i2564.i.i.i.i.i + ; in Loop: Header=BB15_1775 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v79, 0xffff0000, v37 + v_add_f32_e32 v79, v31, v79 + v_and_b32_e32 v80, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s9, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1788: ; in Loop: Header=BB15_1775 Depth=1 + v_bfe_u32 v80, v79, 16, 1 + v_add3_u32 v80, v79, v80, s10 + ; implicit-def: $vgpr79 +; %bb.1789: ; %Flow617 + ; in Loop: Header=BB15_1775 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1774 +; %bb.1790: ; in Loop: Header=BB15_1775 Depth=1 + v_or_b32_e32 v80, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v80, v79, vcc + s_branch .LBB15_1774 +.LBB15_1791: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i2570.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[42:43], off offset:136 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB15_1793 +.LBB15_1792: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i2583.i.i.i.i.i + ; in Loop: Header=BB15_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v78, v33, s11 + v_perm_b32 v32, v41, v32, s11 + global_atomic_cmpswap_x2 v[32:33], v[42:43], v[32:35], off offset:136 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1809 +.LBB15_1793: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1794: ; in Loop: Header=BB15_1793 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s10 + ; implicit-def: $vgpr33 +; %bb.1795: ; %Flow616 + ; in Loop: Header=BB15_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1796: ; in Loop: Header=BB15_1793 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.1797: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i2574.i.i.i.i.i + ; in Loop: Header=BB15_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v41, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1798: ; in Loop: Header=BB15_1793 Depth=1 + v_bfe_u32 v41, v33, 16, 1 + v_add3_u32 v41, v33, v41, s10 + ; implicit-def: $vgpr33 +; %bb.1799: ; %Flow615 + ; in Loop: Header=BB15_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1800: ; in Loop: Header=BB15_1793 Depth=1 + v_or_b32_e32 v41, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v33, vcc +; %bb.1801: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i2577.i.i.i.i.i + ; in Loop: Header=BB15_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v77, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1802: ; in Loop: Header=BB15_1793 Depth=1 + v_bfe_u32 v33, v77, 16, 1 + v_add3_u32 v33, v77, v33, s10 + ; implicit-def: $vgpr77 +; %bb.1803: ; %Flow614 + ; in Loop: Header=BB15_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1804: ; in Loop: Header=BB15_1793 Depth=1 + v_or_b32_e32 v33, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v77, vcc +; %bb.1805: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i2580.i.i.i.i.i + ; in Loop: Header=BB15_1793 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v77, 0xffff0000, v35 + v_add_f32_e32 v77, v37, v77 + v_and_b32_e32 v78, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s9, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1806: ; in Loop: Header=BB15_1793 Depth=1 + v_bfe_u32 v78, v77, 16, 1 + v_add3_u32 v78, v77, v78, s10 + ; implicit-def: $vgpr77 +; %bb.1807: ; %Flow613 + ; in Loop: Header=BB15_1793 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1792 +; %bb.1808: ; in Loop: Header=BB15_1793 Depth=1 + v_or_b32_e32 v78, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v78, v77, vcc + s_branch .LBB15_1792 +.LBB15_1809: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2587 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_read_b32 v30, a1 + v_add3_u32 v34, v40, v30, s16 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v39, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v40, 0 + s_branch .LBB15_1811 +.LBB15_1810: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i2600.i.i.i.i.i + ; in Loop: Header=BB15_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v43, v31, s11 + v_perm_b32 v30, v41, v30, s11 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1827 +.LBB15_1811: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1812: ; in Loop: Header=BB15_1811 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s10 + ; implicit-def: $vgpr31 +; %bb.1813: ; %Flow612 + ; in Loop: Header=BB15_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1814: ; in Loop: Header=BB15_1811 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.1815: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i2591.i.i.i.i.i + ; in Loop: Header=BB15_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v41, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1816: ; in Loop: Header=BB15_1811 Depth=1 + v_bfe_u32 v41, v31, 16, 1 + v_add3_u32 v41, v31, v41, s10 + ; implicit-def: $vgpr31 +; %bb.1817: ; %Flow611 + ; in Loop: Header=BB15_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1818: ; in Loop: Header=BB15_1811 Depth=1 + v_or_b32_e32 v41, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v31, vcc +; %bb.1819: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i2594.i.i.i.i.i + ; in Loop: Header=BB15_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v42, v39, v31 + v_and_b32_e32 v31, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1820: ; in Loop: Header=BB15_1811 Depth=1 + v_bfe_u32 v31, v42, 16, 1 + v_add3_u32 v31, v42, v31, s10 + ; implicit-def: $vgpr42 +; %bb.1821: ; %Flow610 + ; in Loop: Header=BB15_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1822: ; in Loop: Header=BB15_1811 Depth=1 + v_or_b32_e32 v31, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v42, vcc +; %bb.1823: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i2597.i.i.i.i.i + ; in Loop: Header=BB15_1811 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v42, 0xffff0000, v33 + v_add_f32_e32 v42, v27, v42 + v_and_b32_e32 v43, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s9, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1824: ; in Loop: Header=BB15_1811 Depth=1 + v_bfe_u32 v43, v42, 16, 1 + v_add3_u32 v43, v42, v43, s10 + ; implicit-def: $vgpr42 +; %bb.1825: ; %Flow609 + ; in Loop: Header=BB15_1811 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1810 +; %bb.1826: ; in Loop: Header=BB15_1811 Depth=1 + v_or_b32_e32 v43, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v42, vcc + s_branch .LBB15_1810 +.LBB15_1827: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i2603.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1829 +.LBB15_1828: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i2616.i.i.i.i.i + ; in Loop: Header=BB15_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v41, v29, s11 + v_perm_b32 v28, v39, v28, s11 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1845 +.LBB15_1829: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1830: ; in Loop: Header=BB15_1829 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s10 + ; implicit-def: $vgpr29 +; %bb.1831: ; %Flow608 + ; in Loop: Header=BB15_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1832: ; in Loop: Header=BB15_1829 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.1833: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i2607.i.i.i.i.i + ; in Loop: Header=BB15_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v39, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1834: ; in Loop: Header=BB15_1829 Depth=1 + v_bfe_u32 v39, v29, 16, 1 + v_add3_u32 v39, v29, v39, s10 + ; implicit-def: $vgpr29 +; %bb.1835: ; %Flow607 + ; in Loop: Header=BB15_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1836: ; in Loop: Header=BB15_1829 Depth=1 + v_or_b32_e32 v39, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v29, vcc +; %bb.1837: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i2610.i.i.i.i.i + ; in Loop: Header=BB15_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v40, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1838: ; in Loop: Header=BB15_1829 Depth=1 + v_bfe_u32 v29, v40, 16, 1 + v_add3_u32 v29, v40, v29, s10 + ; implicit-def: $vgpr40 +; %bb.1839: ; %Flow606 + ; in Loop: Header=BB15_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1840: ; in Loop: Header=BB15_1829 Depth=1 + v_or_b32_e32 v29, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v40, vcc +; %bb.1841: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i2613.i.i.i.i.i + ; in Loop: Header=BB15_1829 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v40, 0xffff0000, v31 + v_add_f32_e32 v40, v33, v40 + v_and_b32_e32 v41, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s9, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1842: ; in Loop: Header=BB15_1829 Depth=1 + v_bfe_u32 v41, v40, 16, 1 + v_add3_u32 v41, v40, v41, s10 + ; implicit-def: $vgpr40 +; %bb.1843: ; %Flow605 + ; in Loop: Header=BB15_1829 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1828 +; %bb.1844: ; in Loop: Header=BB15_1829 Depth=1 + v_or_b32_e32 v41, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v40, vcc + s_branch .LBB15_1828 +.LBB15_1845: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2620 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_1847 +.LBB15_1846: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i2633.i.i.i.i.i + ; in Loop: Header=BB15_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v39, v27, s11 + v_perm_b32 v26, v36, v26, s11 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1863 +.LBB15_1847: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1848: ; in Loop: Header=BB15_1847 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s10 + ; implicit-def: $vgpr27 +; %bb.1849: ; %Flow604 + ; in Loop: Header=BB15_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1850: ; in Loop: Header=BB15_1847 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.1851: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i2624.i.i.i.i.i + ; in Loop: Header=BB15_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1852: ; in Loop: Header=BB15_1847 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s10 + ; implicit-def: $vgpr27 +; %bb.1853: ; %Flow603 + ; in Loop: Header=BB15_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1854: ; in Loop: Header=BB15_1847 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.1855: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i2627.i.i.i.i.i + ; in Loop: Header=BB15_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1856: ; in Loop: Header=BB15_1847 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s10 + ; implicit-def: $vgpr37 +; %bb.1857: ; %Flow602 + ; in Loop: Header=BB15_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1858: ; in Loop: Header=BB15_1847 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.1859: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i2630.i.i.i.i.i + ; in Loop: Header=BB15_1847 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v39, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s9, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1860: ; in Loop: Header=BB15_1847 Depth=1 + v_bfe_u32 v39, v37, 16, 1 + v_add3_u32 v39, v37, v39, s10 + ; implicit-def: $vgpr37 +; %bb.1861: ; %Flow601 + ; in Loop: Header=BB15_1847 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1846 +; %bb.1862: ; in Loop: Header=BB15_1847 Depth=1 + v_or_b32_e32 v39, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v37, vcc + s_branch .LBB15_1846 +.LBB15_1863: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i2636.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_1865 +.LBB15_1864: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i2649.i.i.i.i.i + ; in Loop: Header=BB15_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s11 + v_perm_b32 v24, v34, v24, s11 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1881 +.LBB15_1865: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1866: ; in Loop: Header=BB15_1865 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s10 + ; implicit-def: $vgpr25 +; %bb.1867: ; %Flow600 + ; in Loop: Header=BB15_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1868: ; in Loop: Header=BB15_1865 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.1869: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i2640.i.i.i.i.i + ; in Loop: Header=BB15_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s9, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1870: ; in Loop: Header=BB15_1865 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s10 + ; implicit-def: $vgpr25 +; %bb.1871: ; %Flow599 + ; in Loop: Header=BB15_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1872: ; in Loop: Header=BB15_1865 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.1873: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i2643.i.i.i.i.i + ; in Loop: Header=BB15_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1874: ; in Loop: Header=BB15_1865 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s10 + ; implicit-def: $vgpr35 +; %bb.1875: ; %Flow598 + ; in Loop: Header=BB15_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1876: ; in Loop: Header=BB15_1865 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.1877: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i2646.i.i.i.i.i + ; in Loop: Header=BB15_1865 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s9, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1878: ; in Loop: Header=BB15_1865 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s10 + ; implicit-def: $vgpr35 +; %bb.1879: ; %Flow597 + ; in Loop: Header=BB15_1865 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1864 +; %bb.1880: ; in Loop: Header=BB15_1865 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_1864 +.LBB15_1881: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til2653 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_1883 +.LBB15_1882: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i2666.i.i.i.i.i + ; in Loop: Header=BB15_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s11 + v_perm_b32 v22, v31, v22, s11 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1899 +.LBB15_1883: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1884: ; in Loop: Header=BB15_1883 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s10 + ; implicit-def: $vgpr23 +; %bb.1885: ; %Flow596 + ; in Loop: Header=BB15_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1886: ; in Loop: Header=BB15_1883 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.1887: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i2657.i.i.i.i.i + ; in Loop: Header=BB15_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1888: ; in Loop: Header=BB15_1883 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s10 + ; implicit-def: $vgpr23 +; %bb.1889: ; %Flow595 + ; in Loop: Header=BB15_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1890: ; in Loop: Header=BB15_1883 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.1891: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i2660.i.i.i.i.i + ; in Loop: Header=BB15_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1892: ; in Loop: Header=BB15_1883 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s10 + ; implicit-def: $vgpr32 +; %bb.1893: ; %Flow594 + ; in Loop: Header=BB15_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1894: ; in Loop: Header=BB15_1883 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.1895: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i2663.i.i.i.i.i + ; in Loop: Header=BB15_1883 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s9, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1896: ; in Loop: Header=BB15_1883 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s10 + ; implicit-def: $vgpr32 +; %bb.1897: ; %Flow593 + ; in Loop: Header=BB15_1883 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1882 +; %bb.1898: ; in Loop: Header=BB15_1883 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_1882 +.LBB15_1899: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i2669.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s9, 0x7f800000 + s_movk_i32 s10, 0x7fff + s_mov_b32 s11, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_1901 +.LBB15_1900: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i2682.i.i.i.i.i + ; in Loop: Header=BB15_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s11 + v_perm_b32 v20, v29, v20, s11 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_1917 +.LBB15_1901: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1902: ; in Loop: Header=BB15_1901 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s10 + ; implicit-def: $vgpr21 +; %bb.1903: ; %Flow592 + ; in Loop: Header=BB15_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1904: ; in Loop: Header=BB15_1901 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.1905: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i2673.i.i.i.i.i + ; in Loop: Header=BB15_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s9, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1906: ; in Loop: Header=BB15_1901 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s10 + ; implicit-def: $vgpr21 +; %bb.1907: ; %Flow591 + ; in Loop: Header=BB15_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1908: ; in Loop: Header=BB15_1901 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.1909: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i2676.i.i.i.i.i + ; in Loop: Header=BB15_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1910: ; in Loop: Header=BB15_1901 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s10 + ; implicit-def: $vgpr30 +; %bb.1911: ; %Flow590 + ; in Loop: Header=BB15_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.1912: ; in Loop: Header=BB15_1901 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.1913: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i2679.i.i.i.i.i + ; in Loop: Header=BB15_1901 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s9, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.1914: ; in Loop: Header=BB15_1901 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s10 + ; implicit-def: $vgpr30 +; %bb.1915: ; %Flow589 + ; in Loop: Header=BB15_1901 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_1900 +; %bb.1916: ; in Loop: Header=BB15_1901 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_1900 +.LBB15_1917: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR2814 + s_or_b64 exec, exec, s[2:3] + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v18, a111 + v_and_b32_e32 v18, 0x7f800000, v18 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1918: + v_accvgpr_read_b32 v19, a111 + v_bfe_u32 v18, v19, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v18, v19, v18, s6 +; %bb.1919: ; %Flow588 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1920: + v_mov_b32_e32 v18, 0 + v_accvgpr_read_b32 v20, a111 + v_or_b32_e32 v19, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v20, vcc +; %bb.1921: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i2879.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v19, a110 + v_and_b32_e32 v19, 0x7f800000, v19 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr19 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1922: + v_accvgpr_read_b32 v20, a110 + v_bfe_u32 v19, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v19, v20, v19, s6 +; %bb.1923: ; %Flow587 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1924: + v_mov_b32_e32 v19, 0 + v_accvgpr_read_b32 v21, a110 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v19, v20, v21, vcc +; %bb.1925: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i2882.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v20, a109 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s2, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1926: + v_accvgpr_read_b32 v21, a109 + v_bfe_u32 v20, v21, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v21, v20, s6 +; %bb.1927: ; %Flow586 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1928: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v22, a109 + v_or_b32_e32 v21, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v21, v22, vcc +; %bb.1929: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i2885.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v21, a108 + v_and_b32_e32 v21, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s2, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1930: + v_accvgpr_read_b32 v22, a108 + v_bfe_u32 v21, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v22, v21, s6 +; %bb.1931: ; %Flow585 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1932: + v_mov_b32_e32 v21, 0 + v_accvgpr_read_b32 v23, a108 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v23, vcc +; %bb.1933: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i2888.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v22, a107 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s2, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1934: + v_accvgpr_read_b32 v23, a107 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 +; %bb.1935: ; %Flow584 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1936: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a107 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.1937: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i2891.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v23, a106 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s2, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1938: + v_accvgpr_read_b32 v24, a106 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 +; %bb.1939: ; %Flow583 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1940: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a106 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.1941: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i2894.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v24, a105 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s2, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1942: + v_accvgpr_read_b32 v25, a105 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 +; %bb.1943: ; %Flow582 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1944: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a105 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.1945: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i2897.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v25, a104 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s2, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1946: + v_accvgpr_read_b32 v26, a104 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 +; %bb.1947: ; %Flow581 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1948: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a104 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.1949: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i2900.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v26, a103 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s2, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1950: + v_accvgpr_read_b32 v27, a103 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 +; %bb.1951: ; %Flow580 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1952: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a103 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.1953: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i2903.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v27, a102 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s2, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1954: + v_accvgpr_read_b32 v28, a102 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 +; %bb.1955: ; %Flow579 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1956: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a102 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.1957: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i2906.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v28, a101 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s2, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1958: + v_accvgpr_read_b32 v29, a101 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 +; %bb.1959: ; %Flow578 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1960: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a101 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.1961: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i2909.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v29, a100 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s2, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1962: + v_accvgpr_read_b32 v30, a100 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 +; %bb.1963: ; %Flow577 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1964: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a100 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.1965: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i2912.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v30, a99 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s2, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1966: + v_accvgpr_read_b32 v31, a99 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 +; %bb.1967: ; %Flow576 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1968: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a99 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.1969: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i2915.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v31, a98 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s2, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1970: + v_accvgpr_read_b32 v32, a98 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 +; %bb.1971: ; %Flow575 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1972: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a98 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.1973: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i2918.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v32, a97 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s2, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1974: + v_accvgpr_read_b32 v33, a97 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 +; %bb.1975: ; %Flow574 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1976: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a97 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.1977: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i2921.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v33, a96 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s2, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1978: + v_accvgpr_read_b32 v34, a96 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 +; %bb.1979: ; %Flow573 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1980: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a96 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.1981: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i2924.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v34, a54 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s2, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1982: + v_accvgpr_read_b32 v35, a54 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 +; %bb.1983: ; %Flow572 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1984: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a54 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.1985: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i2927.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v35, a53 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s2, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1986: + v_accvgpr_read_b32 v36, a53 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 +; %bb.1987: ; %Flow571 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1988: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a53 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.1989: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i2930.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v36, a52 + v_and_b32_e32 v36, 0x7f800000, v36 + v_cmp_ne_u32_e32 vcc, s2, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1990: + v_accvgpr_read_b32 v37, a52 + v_bfe_u32 v36, v37, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v37, v36, s6 +; %bb.1991: ; %Flow570 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1992: + v_mov_b32_e32 v36, 0 + v_accvgpr_read_b32 v39, a52 + v_or_b32_e32 v37, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v39, vcc +; %bb.1993: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i2933.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v37, a51 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s2, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1994: + v_accvgpr_read_b32 v39, a51 + v_bfe_u32 v37, v39, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v39, v37, s6 +; %bb.1995: ; %Flow569 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.1996: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v40, a51 + v_or_b32_e32 v39, 0x10000, v40 + v_cmp_eq_u32_sdwa vcc, v40, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v39, v40, vcc +; %bb.1997: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i2936.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v39, a50 + v_and_b32_e32 v39, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s2, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.1998: + v_accvgpr_read_b32 v40, a50 + v_bfe_u32 v39, v40, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v40, v39, s6 +; %bb.1999: ; %Flow568 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2000: + v_mov_b32_e32 v39, 0 + v_accvgpr_read_b32 v41, a50 + v_or_b32_e32 v40, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v41, vcc +; %bb.2001: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i2939.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v40, a49 + v_and_b32_e32 v40, 0x7f800000, v40 + v_cmp_ne_u32_e32 vcc, s2, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2002: + v_accvgpr_read_b32 v41, a49 + v_bfe_u32 v40, v41, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v41, v40, s6 +; %bb.2003: ; %Flow567 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2004: + v_mov_b32_e32 v40, 0 + v_accvgpr_read_b32 v42, a49 + v_or_b32_e32 v41, 0x10000, v42 + v_cmp_eq_u32_sdwa vcc, v42, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v42, vcc +; %bb.2005: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i2942.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v41, a48 + v_and_b32_e32 v41, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s2, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2006: + v_accvgpr_read_b32 v42, a48 + v_bfe_u32 v41, v42, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v42, v41, s6 +; %bb.2007: ; %Flow566 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2008: + v_mov_b32_e32 v41, 0 + v_accvgpr_read_b32 v43, a48 + v_or_b32_e32 v42, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v43, vcc +; %bb.2009: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i2945.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v42, a39 + v_and_b32_e32 v42, 0x7f800000, v42 + v_cmp_ne_u32_e32 vcc, s2, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2010: + v_accvgpr_read_b32 v43, a39 + v_bfe_u32 v42, v43, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v43, v42, s6 +; %bb.2011: ; %Flow565 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2012: + v_mov_b32_e32 v42, 0 + v_accvgpr_read_b32 v77, a39 + v_or_b32_e32 v43, 0x10000, v77 + v_cmp_eq_u32_sdwa vcc, v77, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v77, vcc +; %bb.2013: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i2948.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v43, a38 + v_and_b32_e32 v43, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s2, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2014: + v_accvgpr_read_b32 v77, a38 + v_bfe_u32 v43, v77, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v77, v43, s6 +; %bb.2015: ; %Flow564 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2016: + v_mov_b32_e32 v43, 0 + v_accvgpr_read_b32 v78, a38 + v_or_b32_e32 v77, 0x10000, v78 + v_cmp_eq_u32_sdwa vcc, v78, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v77, v78, vcc +; %bb.2017: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i2951.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v77, a37 + v_and_b32_e32 v77, 0x7f800000, v77 + v_cmp_ne_u32_e32 vcc, s2, v77 + ; implicit-def: $vgpr77 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2018: + v_accvgpr_read_b32 v78, a37 + v_bfe_u32 v77, v78, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v77, v78, v77, s6 +; %bb.2019: ; %Flow563 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2020: + v_mov_b32_e32 v77, 0 + v_accvgpr_read_b32 v79, a37 + v_or_b32_e32 v78, 0x10000, v79 + v_cmp_eq_u32_sdwa vcc, v79, v77 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v77, v78, v79, vcc +; %bb.2021: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i2954.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v78, a36 + v_and_b32_e32 v78, 0x7f800000, v78 + v_cmp_ne_u32_e32 vcc, s2, v78 + ; implicit-def: $vgpr78 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2022: + v_accvgpr_read_b32 v79, a36 + v_bfe_u32 v78, v79, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v78, v79, v78, s6 +; %bb.2023: ; %Flow562 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2024: + v_mov_b32_e32 v78, 0 + v_accvgpr_read_b32 v80, a36 + v_or_b32_e32 v79, 0x10000, v80 + v_cmp_eq_u32_sdwa vcc, v80, v78 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v78, v79, v80, vcc +; %bb.2025: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i2957.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v79, a35 + v_and_b32_e32 v79, 0x7f800000, v79 + v_cmp_ne_u32_e32 vcc, s2, v79 + ; implicit-def: $vgpr79 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2026: + v_accvgpr_read_b32 v80, a35 + v_bfe_u32 v79, v80, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v79, v80, v79, s6 +; %bb.2027: ; %Flow561 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2028: + v_mov_b32_e32 v79, 0 + v_accvgpr_read_b32 v81, a35 + v_or_b32_e32 v80, 0x10000, v81 + v_cmp_eq_u32_sdwa vcc, v81, v79 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v79, v80, v81, vcc +; %bb.2029: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i2960.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v80, a34 + v_and_b32_e32 v80, 0x7f800000, v80 + v_cmp_ne_u32_e32 vcc, s2, v80 + ; implicit-def: $vgpr80 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2030: + v_accvgpr_read_b32 v81, a34 + v_bfe_u32 v80, v81, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v80, v81, v80, s6 +; %bb.2031: ; %Flow560 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2032: + v_mov_b32_e32 v80, 0 + v_accvgpr_read_b32 v82, a34 + v_or_b32_e32 v81, 0x10000, v82 + v_cmp_eq_u32_sdwa vcc, v82, v80 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v80, v81, v82, vcc +; %bb.2033: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i2963.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v81, a33 + v_and_b32_e32 v81, 0x7f800000, v81 + v_cmp_ne_u32_e32 vcc, s2, v81 + ; implicit-def: $vgpr81 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2034: + v_accvgpr_read_b32 v82, a33 + v_bfe_u32 v81, v82, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v81, v82, v81, s6 +; %bb.2035: ; %Flow559 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2036: + v_mov_b32_e32 v81, 0 + v_accvgpr_read_b32 v83, a33 + v_or_b32_e32 v82, 0x10000, v83 + v_cmp_eq_u32_sdwa vcc, v83, v81 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v81, v82, v83, vcc +; %bb.2037: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i2966.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_accvgpr_read_b32 v82, a32 + v_and_b32_e32 v82, 0x7f800000, v82 + v_cmp_ne_u32_e32 vcc, s2, v82 + ; implicit-def: $vgpr82 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2038: + v_accvgpr_read_b32 v83, a32 + v_bfe_u32 v82, v83, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v82, v83, v82, s6 +; %bb.2039: ; %Flow558 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2040: + v_mov_b32_e32 v82, 0 + v_accvgpr_read_b32 v84, a32 + v_or_b32_e32 v83, 0x10000, v84 + v_cmp_eq_u32_sdwa vcc, v84, v82 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v82, v83, v84, vcc +; %bb.2041: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i2969.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v83, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s2, v83 + ; implicit-def: $vgpr83 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2042: + v_bfe_u32 v83, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v83, v86, v83, s6 +; %bb.2043: ; %Flow557 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2044: + v_mov_b32_e32 v83, 0 + v_or_b32_e32 v84, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v83 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v83, v84, v86, vcc +; %bb.2045: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvE13cast_lds_tileINS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS_8constantILi2EEESJ_NSI_ILi4EEESJ_SK_EEELb0EEENSH_INS2_IJNSI_ILi1EEESJ_NSI_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJSJ_SJ_EEEEENSR_INS2_IJSJ_SO_EEEEEEEENS2_IJNS_8sequenceIJEEENSX_IJLi0EEEENSX_IJLi1EEEENSX_IJLi3ELi8EEEENSX_IJLi5ELi9EEEEEEENS2_IJSY_NSX_IJLi2ELi3ELi4ELi5ELi6EEEENSX_IJLi7ELi8ELi9EEEENSX_IJLi10EEEENSX_IJLi11EEEEEEENSX_IJLi0ELi1EEEENSX_IJLi10ELi11ELi2ELi7ELi4ELi6EEEEEENS_17tensor_descriptorINS2_IJNSH_INS2_IJSJ_SN_SK_SK_EEELb0EEEEEENS2_IJSZ_EEENS2_IJNSX_IJLi1ELi2ELi3ELi4EEEEEEES1H_SO_NSX_IJLin1ELin1ELin1ELin1ELin1EEEES1J_EENS_26tile_distribution_encodingISY_NS2_IJNSX_IJLi2ELi2ELi4ELi2ELi4EEEENSX_IJLi1ELi2ELi32EEEEEEENS2_IJNSX_IJLi1E2973 + s_or_b64 exec, exec, s[2:3] + ds_write_b16_d16_hi v74, v18 + ds_write_b16_d16_hi v74, v19 offset:128 + ds_write_b16_d16_hi v74, v20 offset:256 + ds_write_b16_d16_hi v74, v21 offset:384 + ds_write_b16_d16_hi v74, v22 offset:1024 + ds_write_b16_d16_hi v74, v23 offset:1152 + ds_write_b16_d16_hi v74, v24 offset:1280 + ds_write_b16_d16_hi v74, v25 offset:1408 + ds_write_b16_d16_hi v74, v26 offset:2048 + ds_write_b16_d16_hi v74, v27 offset:2176 + ds_write_b16_d16_hi v74, v28 offset:2304 + ds_write_b16_d16_hi v74, v29 offset:2432 + ds_write_b16_d16_hi v74, v30 offset:3072 + ds_write_b16_d16_hi v74, v31 offset:3200 + ds_write_b16_d16_hi v74, v32 offset:3328 + ds_write_b16_d16_hi v74, v33 offset:3456 + ds_write_b16_d16_hi v74, v34 offset:8192 + ds_write_b16_d16_hi v74, v35 offset:8320 + ds_write_b16_d16_hi v74, v36 offset:8448 + ds_write_b16_d16_hi v74, v37 offset:8576 + ds_write_b16_d16_hi v74, v39 offset:9216 + ds_write_b16_d16_hi v74, v40 offset:9344 + ds_write_b16_d16_hi v74, v41 offset:9472 + ds_write_b16_d16_hi v74, v42 offset:9600 + ds_write_b16_d16_hi v74, v43 offset:10240 + ds_write_b16_d16_hi v74, v77 offset:10368 + ds_write_b16_d16_hi v74, v78 offset:10496 + ds_write_b16_d16_hi v74, v79 offset:10624 + ds_write_b16_d16_hi v74, v80 offset:11264 + ds_write_b16_d16_hi v74, v81 offset:11392 + ds_write_b16_d16_hi v74, v82 offset:11520 + ds_write_b16_d16_hi v74, v83 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_add_u32_e32 v18, s2, v75 + v_add_u32_e32 v19, s8, v18 + v_mad_u64_u32 v[38:39], s[2:3], v19, s16, v[38:39] + v_ashrrev_i32_e32 v39, 31, v38 + v_lshl_add_u64 v[40:41], v[38:39], 1, s[0:1] + global_load_dwordx2 v[36:37], v[40:41], off + v_lshl_or_b32 v18, v18, 7, v76 + ds_read_b128 v[30:33], v18 + ds_read_b128 v[26:29], v18 offset:128 + ds_read_b128 v[22:25], v18 offset:256 + ds_read_b128 v[18:21], v18 offset:384 + s_waitcnt lgkmcnt(3) + v_lshlrev_b32_e32 v39, 16, v30 + v_and_b32_e32 v30, 0xffff0000, v30 + v_lshlrev_b32_e32 v42, 16, v31 + v_and_b32_e32 v31, 0xffff0000, v31 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v43, 0 + s_branch .LBB15_2047 +.LBB15_2046: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i3036.i.i.i.i.i + ; in Loop: Header=BB15_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v35, v76, v35, s10 + v_perm_b32 v34, v74, v34, s10 + global_atomic_cmpswap_x2 v[34:35], v[40:41], v[34:37], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[34:35], v[36:37] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[36:37], v[34:35] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2063 +.LBB15_2047: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v34, 16, v36 + v_add_f32_e32 v35, v39, v34 + v_and_b32_e32 v34, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2048: ; in Loop: Header=BB15_2047 Depth=1 + v_bfe_u32 v34, v35, 16, 1 + v_add3_u32 v34, v35, v34, s9 + ; implicit-def: $vgpr35 +; %bb.2049: ; %Flow556 + ; in Loop: Header=BB15_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2050: ; in Loop: Header=BB15_2047 Depth=1 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v35, vcc +; %bb.2051: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i.i.i.i.i.i.i.i3027.i.i.i.i.i + ; in Loop: Header=BB15_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v36 + v_add_f32_e32 v35, v30, v35 + v_and_b32_e32 v74, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2052: ; in Loop: Header=BB15_2047 Depth=1 + v_bfe_u32 v74, v35, 16, 1 + v_add3_u32 v74, v35, v74, s9 + ; implicit-def: $vgpr35 +; %bb.2053: ; %Flow555 + ; in Loop: Header=BB15_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2054: ; in Loop: Header=BB15_2047 Depth=1 + v_or_b32_e32 v74, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v35, vcc +; %bb.2055: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i.i.i.i.i.i.i.i3030.i.i.i.i.i + ; in Loop: Header=BB15_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v35, 16, v37 + v_add_f32_e32 v75, v42, v35 + v_and_b32_e32 v35, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2056: ; in Loop: Header=BB15_2047 Depth=1 + v_bfe_u32 v35, v75, 16, 1 + v_add3_u32 v35, v75, v35, s9 + ; implicit-def: $vgpr75 +; %bb.2057: ; %Flow554 + ; in Loop: Header=BB15_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2058: ; in Loop: Header=BB15_2047 Depth=1 + v_or_b32_e32 v35, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v75, vcc +; %bb.2059: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i.i.i.i.i.i.i.i3033.i.i.i.i.i + ; in Loop: Header=BB15_2047 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v75, 0xffff0000, v37 + v_add_f32_e32 v75, v31, v75 + v_and_b32_e32 v76, 0x7f800000, v75 + v_cmp_ne_u32_e32 vcc, s8, v76 + ; implicit-def: $vgpr76 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2060: ; in Loop: Header=BB15_2047 Depth=1 + v_bfe_u32 v76, v75, 16, 1 + v_add3_u32 v76, v75, v76, s9 + ; implicit-def: $vgpr75 +; %bb.2061: ; %Flow553 + ; in Loop: Header=BB15_2047 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2046 +; %bb.2062: ; in Loop: Header=BB15_2047 Depth=1 + v_or_b32_e32 v76, 0x10000, v75 + v_cmp_eq_u32_sdwa vcc, v75, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v76, v76, v75, vcc + s_branch .LBB15_2046 +.LBB15_2063: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i.i.i.i.i.i.i.i3039.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[34:35], v[40:41], off offset:8 + v_lshlrev_b32_e32 v30, 16, v32 + v_and_b32_e32 v31, 0xffff0000, v32 + v_lshlrev_b32_e32 v36, 16, v33 + v_and_b32_e32 v37, 0xffff0000, v33 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB15_2065 +.LBB15_2064: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i.i.i.i.i.i.i.i3052.i.i.i.i.i + ; in Loop: Header=BB15_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v33, v74, v33, s10 + v_perm_b32 v32, v42, v32, s10 + global_atomic_cmpswap_x2 v[32:33], v[40:41], v[32:35], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[32:33], v[34:35] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[34:35], v[32:33] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2081 +.LBB15_2065: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v32, 16, v34 + v_add_f32_e32 v33, v30, v32 + v_and_b32_e32 v32, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2066: ; in Loop: Header=BB15_2065 Depth=1 + v_bfe_u32 v32, v33, 16, 1 + v_add3_u32 v32, v33, v32, s9 + ; implicit-def: $vgpr33 +; %bb.2067: ; %Flow552 + ; in Loop: Header=BB15_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2068: ; in Loop: Header=BB15_2065 Depth=1 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v33, vcc +; %bb.2069: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i.i.i.i.i.i.i.i3043.i.i.i.i.i + ; in Loop: Header=BB15_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v33, 0xffff0000, v34 + v_add_f32_e32 v33, v31, v33 + v_and_b32_e32 v42, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2070: ; in Loop: Header=BB15_2065 Depth=1 + v_bfe_u32 v42, v33, 16, 1 + v_add3_u32 v42, v33, v42, s9 + ; implicit-def: $vgpr33 +; %bb.2071: ; %Flow551 + ; in Loop: Header=BB15_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2072: ; in Loop: Header=BB15_2065 Depth=1 + v_or_b32_e32 v42, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v33, vcc +; %bb.2073: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i.i.i.i.i.i.i.i3046.i.i.i.i.i + ; in Loop: Header=BB15_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v33, 16, v35 + v_add_f32_e32 v43, v36, v33 + v_and_b32_e32 v33, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2074: ; in Loop: Header=BB15_2065 Depth=1 + v_bfe_u32 v33, v43, 16, 1 + v_add3_u32 v33, v43, v33, s9 + ; implicit-def: $vgpr43 +; %bb.2075: ; %Flow550 + ; in Loop: Header=BB15_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2076: ; in Loop: Header=BB15_2065 Depth=1 + v_or_b32_e32 v33, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v43, vcc +; %bb.2077: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i.i.i.i.i.i.i.i3049.i.i.i.i.i + ; in Loop: Header=BB15_2065 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v43, 0xffff0000, v35 + v_add_f32_e32 v43, v37, v43 + v_and_b32_e32 v74, 0x7f800000, v43 + v_cmp_ne_u32_e32 vcc, s8, v74 + ; implicit-def: $vgpr74 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2078: ; in Loop: Header=BB15_2065 Depth=1 + v_bfe_u32 v74, v43, 16, 1 + v_add3_u32 v74, v43, v74, s9 + ; implicit-def: $vgpr43 +; %bb.2079: ; %Flow549 + ; in Loop: Header=BB15_2065 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2064 +; %bb.2080: ; in Loop: Header=BB15_2065 Depth=1 + v_or_b32_e32 v74, 0x10000, v43 + v_cmp_eq_u32_sdwa vcc, v43, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v74, v74, v43, vcc + s_branch .LBB15_2064 +.LBB15_2081: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3056 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v34, s16, v38 + v_ashrrev_i32_e32 v35, 31, v34 + v_lshl_add_u64 v[36:37], v[34:35], 1, s[0:1] + global_load_dwordx2 v[32:33], v[36:37], off + s_waitcnt lgkmcnt(2) + v_lshlrev_b32_e32 v35, 16, v26 + v_and_b32_e32 v26, 0xffff0000, v26 + v_lshlrev_b32_e32 v38, 16, v27 + v_and_b32_e32 v27, 0xffff0000, v27 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v39, 0 + s_branch .LBB15_2083 +.LBB15_2082: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i23.i.i.i.i.i.i.i3069.i.i.i.i.i + ; in Loop: Header=BB15_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v31, v42, v31, s10 + v_perm_b32 v30, v40, v30, s10 + global_atomic_cmpswap_x2 v[30:31], v[36:37], v[30:33], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[30:31], v[32:33] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[32:33], v[30:31] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2099 +.LBB15_2083: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v30, 16, v32 + v_add_f32_e32 v31, v35, v30 + v_and_b32_e32 v30, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2084: ; in Loop: Header=BB15_2083 Depth=1 + v_bfe_u32 v30, v31, 16, 1 + v_add3_u32 v30, v31, v30, s9 + ; implicit-def: $vgpr31 +; %bb.2085: ; %Flow548 + ; in Loop: Header=BB15_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2086: ; in Loop: Header=BB15_2083 Depth=1 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v31, vcc +; %bb.2087: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i14.i.i.i.i.i.i.i3060.i.i.i.i.i + ; in Loop: Header=BB15_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v31, 0xffff0000, v32 + v_add_f32_e32 v31, v26, v31 + v_and_b32_e32 v40, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2088: ; in Loop: Header=BB15_2083 Depth=1 + v_bfe_u32 v40, v31, 16, 1 + v_add3_u32 v40, v31, v40, s9 + ; implicit-def: $vgpr31 +; %bb.2089: ; %Flow547 + ; in Loop: Header=BB15_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2090: ; in Loop: Header=BB15_2083 Depth=1 + v_or_b32_e32 v40, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v31, vcc +; %bb.2091: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i17.i.i.i.i.i.i.i3063.i.i.i.i.i + ; in Loop: Header=BB15_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v31, 16, v33 + v_add_f32_e32 v41, v38, v31 + v_and_b32_e32 v31, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2092: ; in Loop: Header=BB15_2083 Depth=1 + v_bfe_u32 v31, v41, 16, 1 + v_add3_u32 v31, v41, v31, s9 + ; implicit-def: $vgpr41 +; %bb.2093: ; %Flow546 + ; in Loop: Header=BB15_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2094: ; in Loop: Header=BB15_2083 Depth=1 + v_or_b32_e32 v31, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v41, vcc +; %bb.2095: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i20.i.i.i.i.i.i.i3066.i.i.i.i.i + ; in Loop: Header=BB15_2083 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v41, 0xffff0000, v33 + v_add_f32_e32 v41, v27, v41 + v_and_b32_e32 v42, 0x7f800000, v41 + v_cmp_ne_u32_e32 vcc, s8, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2096: ; in Loop: Header=BB15_2083 Depth=1 + v_bfe_u32 v42, v41, 16, 1 + v_add3_u32 v42, v41, v42, s9 + ; implicit-def: $vgpr41 +; %bb.2097: ; %Flow545 + ; in Loop: Header=BB15_2083 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2082 +; %bb.2098: ; in Loop: Header=BB15_2083 Depth=1 + v_or_b32_e32 v42, 0x10000, v41 + v_cmp_eq_u32_sdwa vcc, v41, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v41, vcc + s_branch .LBB15_2082 +.LBB15_2099: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i26.i.i.i.i.i.i.i3072.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[30:31], v[36:37], off offset:8 + v_lshlrev_b32_e32 v26, 16, v28 + v_and_b32_e32 v27, 0xffff0000, v28 + v_lshlrev_b32_e32 v32, 16, v29 + v_and_b32_e32 v33, 0xffff0000, v29 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_2101 +.LBB15_2100: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i39.i.i.i.i.i.i.i3085.i.i.i.i.i + ; in Loop: Header=BB15_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v29, v40, v29, s10 + v_perm_b32 v28, v38, v28, s10 + global_atomic_cmpswap_x2 v[28:29], v[36:37], v[28:31], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[28:29], v[30:31] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[30:31], v[28:29] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2117 +.LBB15_2101: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v28, 16, v30 + v_add_f32_e32 v29, v26, v28 + v_and_b32_e32 v28, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2102: ; in Loop: Header=BB15_2101 Depth=1 + v_bfe_u32 v28, v29, 16, 1 + v_add3_u32 v28, v29, v28, s9 + ; implicit-def: $vgpr29 +; %bb.2103: ; %Flow544 + ; in Loop: Header=BB15_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2104: ; in Loop: Header=BB15_2101 Depth=1 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v29, vcc +; %bb.2105: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i30.i.i.i.i.i.i.i3076.i.i.i.i.i + ; in Loop: Header=BB15_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v29, 0xffff0000, v30 + v_add_f32_e32 v29, v27, v29 + v_and_b32_e32 v38, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2106: ; in Loop: Header=BB15_2101 Depth=1 + v_bfe_u32 v38, v29, 16, 1 + v_add3_u32 v38, v29, v38, s9 + ; implicit-def: $vgpr29 +; %bb.2107: ; %Flow543 + ; in Loop: Header=BB15_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2108: ; in Loop: Header=BB15_2101 Depth=1 + v_or_b32_e32 v38, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v29, vcc +; %bb.2109: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i33.i.i.i.i.i.i.i3079.i.i.i.i.i + ; in Loop: Header=BB15_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v29, 16, v31 + v_add_f32_e32 v39, v32, v29 + v_and_b32_e32 v29, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2110: ; in Loop: Header=BB15_2101 Depth=1 + v_bfe_u32 v29, v39, 16, 1 + v_add3_u32 v29, v39, v29, s9 + ; implicit-def: $vgpr39 +; %bb.2111: ; %Flow542 + ; in Loop: Header=BB15_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2112: ; in Loop: Header=BB15_2101 Depth=1 + v_or_b32_e32 v29, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v39, vcc +; %bb.2113: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i36.i.i.i.i.i.i.i3082.i.i.i.i.i + ; in Loop: Header=BB15_2101 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v39, 0xffff0000, v31 + v_add_f32_e32 v39, v33, v39 + v_and_b32_e32 v40, 0x7f800000, v39 + v_cmp_ne_u32_e32 vcc, s8, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2114: ; in Loop: Header=BB15_2101 Depth=1 + v_bfe_u32 v40, v39, 16, 1 + v_add3_u32 v40, v39, v40, s9 + ; implicit-def: $vgpr39 +; %bb.2115: ; %Flow541 + ; in Loop: Header=BB15_2101 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2100 +; %bb.2116: ; in Loop: Header=BB15_2101 Depth=1 + v_or_b32_e32 v40, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v39, vcc + s_branch .LBB15_2100 +.LBB15_2117: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3089 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v30, s16, v34 + v_ashrrev_i32_e32 v31, 31, v30 + v_lshl_add_u64 v[32:33], v[30:31], 1, s[0:1] + global_load_dwordx2 v[28:29], v[32:33], off + s_waitcnt lgkmcnt(1) + v_lshlrev_b32_e32 v31, 16, v22 + v_and_b32_e32 v22, 0xffff0000, v22 + v_lshlrev_b32_e32 v34, 16, v23 + v_and_b32_e32 v23, 0xffff0000, v23 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v35, 0 + s_branch .LBB15_2119 +.LBB15_2118: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i88.i.i.i.i.i.i.i3102.i.i.i.i.i + ; in Loop: Header=BB15_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v27, v38, v27, s10 + v_perm_b32 v26, v36, v26, s10 + global_atomic_cmpswap_x2 v[26:27], v[32:33], v[26:29], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[26:27], v[28:29] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[28:29], v[26:27] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2135 +.LBB15_2119: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v26, 16, v28 + v_add_f32_e32 v27, v31, v26 + v_and_b32_e32 v26, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2120: ; in Loop: Header=BB15_2119 Depth=1 + v_bfe_u32 v26, v27, 16, 1 + v_add3_u32 v26, v27, v26, s9 + ; implicit-def: $vgpr27 +; %bb.2121: ; %Flow540 + ; in Loop: Header=BB15_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2122: ; in Loop: Header=BB15_2119 Depth=1 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v27, vcc +; %bb.2123: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i79.i.i.i.i.i.i.i3093.i.i.i.i.i + ; in Loop: Header=BB15_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v27, 0xffff0000, v28 + v_add_f32_e32 v27, v22, v27 + v_and_b32_e32 v36, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2124: ; in Loop: Header=BB15_2119 Depth=1 + v_bfe_u32 v36, v27, 16, 1 + v_add3_u32 v36, v27, v36, s9 + ; implicit-def: $vgpr27 +; %bb.2125: ; %Flow539 + ; in Loop: Header=BB15_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2126: ; in Loop: Header=BB15_2119 Depth=1 + v_or_b32_e32 v36, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v27, vcc +; %bb.2127: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i82.i.i.i.i.i.i.i3096.i.i.i.i.i + ; in Loop: Header=BB15_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v27, 16, v29 + v_add_f32_e32 v37, v34, v27 + v_and_b32_e32 v27, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2128: ; in Loop: Header=BB15_2119 Depth=1 + v_bfe_u32 v27, v37, 16, 1 + v_add3_u32 v27, v37, v27, s9 + ; implicit-def: $vgpr37 +; %bb.2129: ; %Flow538 + ; in Loop: Header=BB15_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2130: ; in Loop: Header=BB15_2119 Depth=1 + v_or_b32_e32 v27, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v37, vcc +; %bb.2131: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i85.i.i.i.i.i.i.i3099.i.i.i.i.i + ; in Loop: Header=BB15_2119 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v37, 0xffff0000, v29 + v_add_f32_e32 v37, v23, v37 + v_and_b32_e32 v38, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s8, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2132: ; in Loop: Header=BB15_2119 Depth=1 + v_bfe_u32 v38, v37, 16, 1 + v_add3_u32 v38, v37, v38, s9 + ; implicit-def: $vgpr37 +; %bb.2133: ; %Flow537 + ; in Loop: Header=BB15_2119 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2118 +; %bb.2134: ; in Loop: Header=BB15_2119 Depth=1 + v_or_b32_e32 v38, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v37, vcc + s_branch .LBB15_2118 +.LBB15_2135: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i91.i.i.i.i.i.i.i3105.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[26:27], v[32:33], off offset:8 + v_lshlrev_b32_e32 v22, 16, v24 + v_and_b32_e32 v23, 0xffff0000, v24 + v_lshlrev_b32_e32 v28, 16, v25 + v_and_b32_e32 v29, 0xffff0000, v25 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v31, 0 + s_branch .LBB15_2137 +.LBB15_2136: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i104.i.i.i.i.i.i.i3118.i.i.i.i.i + ; in Loop: Header=BB15_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v25, v36, v25, s10 + v_perm_b32 v24, v34, v24, s10 + global_atomic_cmpswap_x2 v[24:25], v[32:33], v[24:27], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[24:25], v[26:27] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[26:27], v[24:25] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2153 +.LBB15_2137: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v24, 16, v26 + v_add_f32_e32 v25, v22, v24 + v_and_b32_e32 v24, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2138: ; in Loop: Header=BB15_2137 Depth=1 + v_bfe_u32 v24, v25, 16, 1 + v_add3_u32 v24, v25, v24, s9 + ; implicit-def: $vgpr25 +; %bb.2139: ; %Flow536 + ; in Loop: Header=BB15_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2140: ; in Loop: Header=BB15_2137 Depth=1 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v25, vcc +; %bb.2141: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i95.i.i.i.i.i.i.i3109.i.i.i.i.i + ; in Loop: Header=BB15_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v25, 0xffff0000, v26 + v_add_f32_e32 v25, v23, v25 + v_and_b32_e32 v34, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s8, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2142: ; in Loop: Header=BB15_2137 Depth=1 + v_bfe_u32 v34, v25, 16, 1 + v_add3_u32 v34, v25, v34, s9 + ; implicit-def: $vgpr25 +; %bb.2143: ; %Flow535 + ; in Loop: Header=BB15_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2144: ; in Loop: Header=BB15_2137 Depth=1 + v_or_b32_e32 v34, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v25, vcc +; %bb.2145: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i98.i.i.i.i.i.i.i3112.i.i.i.i.i + ; in Loop: Header=BB15_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v25, 16, v27 + v_add_f32_e32 v35, v28, v25 + v_and_b32_e32 v25, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2146: ; in Loop: Header=BB15_2137 Depth=1 + v_bfe_u32 v25, v35, 16, 1 + v_add3_u32 v25, v35, v25, s9 + ; implicit-def: $vgpr35 +; %bb.2147: ; %Flow534 + ; in Loop: Header=BB15_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2148: ; in Loop: Header=BB15_2137 Depth=1 + v_or_b32_e32 v25, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v35, vcc +; %bb.2149: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i101.i.i.i.i.i.i.i3115.i.i.i.i.i + ; in Loop: Header=BB15_2137 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v35, 0xffff0000, v27 + v_add_f32_e32 v35, v29, v35 + v_and_b32_e32 v36, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s8, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2150: ; in Loop: Header=BB15_2137 Depth=1 + v_bfe_u32 v36, v35, 16, 1 + v_add3_u32 v36, v35, v36, s9 + ; implicit-def: $vgpr35 +; %bb.2151: ; %Flow533 + ; in Loop: Header=BB15_2137 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2136 +; %bb.2152: ; in Loop: Header=BB15_2137 Depth=1 + v_or_b32_e32 v36, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v35, vcc + s_branch .LBB15_2136 +.LBB15_2153: ; %_ZZZNK7ck_tile36tile_window_with_static_distributionINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS_5tupleIJNS_5embedINS7_IJiiEEES9_Lb0EEENS_12pass_throughIiEESC_EEENS7_IJNS_8sequenceIJLi0EEEENSE_IJLi1EEEENSE_IJLi2EEEEEEENS7_IJNSE_IJLi1ELi2EEEENSE_IJLi3EEEENSE_IJLi4EEEEEEENSE_IJLi3ELi4EEEElNSE_IJLin1ELin1ELi8ELin1ELin1EEEENSE_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE1EEENS7_IJNS_8constantILi256EEESU_EEENS_17tile_distributionINS_14tensor_adaptorINS7_IJNS_9replicateINS7_IJNST_ILi1EEEEEEEENS_7unmergeINS7_IJNST_ILi4EEENST_ILi8EEES13_EEELb0EEENS12_INS7_IJS14_S14_EEELb0EEENS_23merge_v2_magic_divisionINS7_IJS13_EEEEENS19_IS17_EEEEENS7_IJNSE_IJEEESF_SG_SK_NSE_IJLi4ELi6EEEEEEENS7_IJSH_NSE_IJLi3ELi4ELi5EEEENSE_IJLi6ELi7EEEENSE_IJLi8EEEENSE_IJLi9EEEEEEENSE_IJLi0ELi1EEEENSE_IJLi8ELi9ELi5ELi7EEEEEENS6_INS7_IJNS12_INS7_IJS13_S14_EEELb0EEEEEENS7_IJSF_EEENS7_IJSJ_EEESJ_NST_ILi32EEENSE_IJLin1ELin1ELin1EEEES1V_EENS_26til3122 + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v22, s16, v30 + v_ashrrev_i32_e32 v23, 31, v22 + v_lshl_add_u64 v[26:27], v[22:23], 1, s[0:1] + global_load_dwordx2 v[24:25], v[26:27], off + s_waitcnt lgkmcnt(0) + v_lshlrev_b32_e32 v28, 16, v18 + v_and_b32_e32 v18, 0xffff0000, v18 + v_lshlrev_b32_e32 v29, 16, v19 + v_and_b32_e32 v19, 0xffff0000, v19 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v30, 0 + s_branch .LBB15_2155 +.LBB15_2154: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i.i.i.i.i.i145.i.i.i.i.i.i.i3135.i.i.i.i.i + ; in Loop: Header=BB15_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v23, v33, v23, s10 + v_perm_b32 v22, v31, v22, s10 + global_atomic_cmpswap_x2 v[22:23], v[26:27], v[22:25], off sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[22:23], v[24:25] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[24:25], v[22:23] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2171 +.LBB15_2155: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v22, 16, v24 + v_add_f32_e32 v23, v28, v22 + v_and_b32_e32 v22, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2156: ; in Loop: Header=BB15_2155 Depth=1 + v_bfe_u32 v22, v23, 16, 1 + v_add3_u32 v22, v23, v22, s9 + ; implicit-def: $vgpr23 +; %bb.2157: ; %Flow532 + ; in Loop: Header=BB15_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2158: ; in Loop: Header=BB15_2155 Depth=1 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v23, vcc +; %bb.2159: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i.i.i.i.i.i136.i.i.i.i.i.i.i3126.i.i.i.i.i + ; in Loop: Header=BB15_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v23, 0xffff0000, v24 + v_add_f32_e32 v23, v18, v23 + v_and_b32_e32 v31, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2160: ; in Loop: Header=BB15_2155 Depth=1 + v_bfe_u32 v31, v23, 16, 1 + v_add3_u32 v31, v23, v31, s9 + ; implicit-def: $vgpr23 +; %bb.2161: ; %Flow531 + ; in Loop: Header=BB15_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2162: ; in Loop: Header=BB15_2155 Depth=1 + v_or_b32_e32 v31, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v23, vcc +; %bb.2163: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i.i.i.i.i.i139.i.i.i.i.i.i.i3129.i.i.i.i.i + ; in Loop: Header=BB15_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v23, 16, v25 + v_add_f32_e32 v32, v29, v23 + v_and_b32_e32 v23, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2164: ; in Loop: Header=BB15_2155 Depth=1 + v_bfe_u32 v23, v32, 16, 1 + v_add3_u32 v23, v32, v23, s9 + ; implicit-def: $vgpr32 +; %bb.2165: ; %Flow530 + ; in Loop: Header=BB15_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2166: ; in Loop: Header=BB15_2155 Depth=1 + v_or_b32_e32 v23, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v32, vcc +; %bb.2167: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i.i.i.i.i.i142.i.i.i.i.i.i.i3132.i.i.i.i.i + ; in Loop: Header=BB15_2155 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v32, 0xffff0000, v25 + v_add_f32_e32 v32, v19, v32 + v_and_b32_e32 v33, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s8, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2168: ; in Loop: Header=BB15_2155 Depth=1 + v_bfe_u32 v33, v32, 16, 1 + v_add3_u32 v33, v32, v33, s9 + ; implicit-def: $vgpr32 +; %bb.2169: ; %Flow529 + ; in Loop: Header=BB15_2155 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2154 +; %bb.2170: ; in Loop: Header=BB15_2155 Depth=1 + v_or_b32_e32 v33, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v32, vcc + s_branch .LBB15_2154 +.LBB15_2171: ; %_ZN7ck_tile10atomic_addIDv4_DF16bEEvPT_RKS2_.exit.i.i.i.i.i148.i.i.i.i.i.i.i3138.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + global_load_dwordx2 v[22:23], v[26:27], off offset:8 + v_lshlrev_b32_e32 v18, 16, v20 + v_and_b32_e32 v19, 0xffff0000, v20 + v_lshlrev_b32_e32 v24, 16, v21 + v_and_b32_e32 v25, 0xffff0000, v21 + s_mov_b64 s[2:3], 0 + s_mov_b32 s8, 0x7f800000 + s_movk_i32 s9, 0x7fff + s_mov_b32 s10, 0x7060302 + v_mov_b32_e32 v28, 0 + s_branch .LBB15_2173 +.LBB15_2172: ; %_ZN7ck_tile12add_bf16x4_tERKDv4_DF16bS2_.exit.i27.i.i.i.i.i161.i.i.i.i.i.i.i3151.i.i.i.i.i + ; in Loop: Header=BB15_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_perm_b32 v21, v31, v21, s10 + v_perm_b32 v20, v29, v20, s10 + global_atomic_cmpswap_x2 v[20:21], v[26:27], v[20:23], off offset:8 sc0 + s_waitcnt vmcnt(0) + v_cmp_eq_u64_e32 vcc, v[20:21], v[22:23] + s_or_b64 s[2:3], vcc, s[2:3] + v_mov_b64_e32 v[22:23], v[20:21] + s_andn2_b64 exec, exec, s[2:3] + s_cbranch_execz .LBB15_2189 +.LBB15_2173: ; =>This Inner Loop Header: Depth=1 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 16, v22 + v_add_f32_e32 v21, v18, v20 + v_and_b32_e32 v20, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2174: ; in Loop: Header=BB15_2173 Depth=1 + v_bfe_u32 v20, v21, 16, 1 + v_add3_u32 v20, v21, v20, s9 + ; implicit-def: $vgpr21 +; %bb.2175: ; %Flow527 + ; in Loop: Header=BB15_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2176: ; in Loop: Header=BB15_2173 Depth=1 + v_or_b32_e32 v20, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v21, vcc +; %bb.2177: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit.i.i18.i.i.i.i.i152.i.i.i.i.i.i.i3142.i.i.i.i.i + ; in Loop: Header=BB15_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v21, 0xffff0000, v22 + v_add_f32_e32 v21, v19, v21 + v_and_b32_e32 v29, 0x7f800000, v21 + v_cmp_ne_u32_e32 vcc, s8, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2178: ; in Loop: Header=BB15_2173 Depth=1 + v_bfe_u32 v29, v21, 16, 1 + v_add3_u32 v29, v21, v29, s9 + ; implicit-def: $vgpr21 +; %bb.2179: ; %Flow526 + ; in Loop: Header=BB15_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2180: ; in Loop: Header=BB15_2173 Depth=1 + v_or_b32_e32 v29, 0x10000, v21 + v_cmp_eq_u32_sdwa vcc, v21, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v21, vcc +; %bb.2181: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit23.i.i21.i.i.i.i.i155.i.i.i.i.i.i.i3145.i.i.i.i.i + ; in Loop: Header=BB15_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_lshlrev_b32_e32 v21, 16, v23 + v_add_f32_e32 v30, v24, v21 + v_and_b32_e32 v21, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2182: ; in Loop: Header=BB15_2173 Depth=1 + v_bfe_u32 v21, v30, 16, 1 + v_add3_u32 v21, v30, v21, s9 + ; implicit-def: $vgpr30 +; %bb.2183: ; %Flow525 + ; in Loop: Header=BB15_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] +; %bb.2184: ; in Loop: Header=BB15_2173 Depth=1 + v_or_b32_e32 v21, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v30, vcc +; %bb.2185: ; %_ZN7ck_tile3addIDF16bfEET_RKS1_S3_.exit28.i.i24.i.i.i.i.i158.i.i.i.i.i.i.i3148.i.i.i.i.i + ; in Loop: Header=BB15_2173 Depth=1 + s_or_b64 exec, exec, s[6:7] + v_and_b32_e32 v30, 0xffff0000, v23 + v_add_f32_e32 v30, v25, v30 + v_and_b32_e32 v31, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s8, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[6:7], vcc + s_xor_b64 s[6:7], exec, s[6:7] +; %bb.2186: ; in Loop: Header=BB15_2173 Depth=1 + v_bfe_u32 v31, v30, 16, 1 + v_add3_u32 v31, v30, v31, s9 + ; implicit-def: $vgpr30 +; %bb.2187: ; %Flow + ; in Loop: Header=BB15_2173 Depth=1 + s_andn2_saveexec_b64 s[6:7], s[6:7] + s_cbranch_execz .LBB15_2172 +; %bb.2188: ; in Loop: Header=BB15_2173 Depth=1 + v_or_b32_e32 v31, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v30, vcc + s_branch .LBB15_2172 +.LBB15_2189: ; %Flow528 + s_or_b64 exec, exec, s[2:3] + s_mov_b64 vcc, 0 + s_branch .LBB15_12 +.LBB15_2190: + v_readfirstlane_b32 s6, v0 + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v18, 0x7f800000, v73 + v_cmp_ne_u32_e32 vcc, s2, v18 + ; implicit-def: $vgpr18 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2191: + v_bfe_u32 v18, v73, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v18, v73, v18, s7 + ; implicit-def: $vgpr73 +; %bb.2192: ; %Flow1292 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2193: + v_mov_b32_e32 v18, 0 + v_or_b32_e32 v19, 0x10000, v73 + v_cmp_eq_u32_sdwa vcc, v73, v18 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v18, v19, v73, vcc +; %bb.2194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v72 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2195: + v_bfe_u32 v19, v72, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v20, v72, v19, s7 + ; implicit-def: $vgpr72 +; %bb.2196: ; %Flow1291 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2197: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v20, 0x10000, v72 + v_cmp_eq_u32_sdwa vcc, v72, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v20, v72, vcc +; %bb.2198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v71 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2199: + v_bfe_u32 v19, v71, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v21, v71, v19, s7 + ; implicit-def: $vgpr71 +; %bb.2200: ; %Flow1290 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2201: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v21, 0x10000, v71 + v_cmp_eq_u32_sdwa vcc, v71, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v21, v71, vcc +; %bb.2202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v70 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2203: + v_bfe_u32 v19, v70, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v22, v70, v19, s7 + ; implicit-def: $vgpr70 +; %bb.2204: ; %Flow1289 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2205: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v22, 0x10000, v70 + v_cmp_eq_u32_sdwa vcc, v70, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v22, v70, vcc +; %bb.2206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v69 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2207: + v_bfe_u32 v19, v69, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v23, v69, v19, s7 + ; implicit-def: $vgpr69 +; %bb.2208: ; %Flow1288 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2209: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v23, 0x10000, v69 + v_cmp_eq_u32_sdwa vcc, v69, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v23, v69, vcc +; %bb.2210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v68 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2211: + v_bfe_u32 v19, v68, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v24, v68, v19, s7 + ; implicit-def: $vgpr68 +; %bb.2212: ; %Flow1287 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2213: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v24, 0x10000, v68 + v_cmp_eq_u32_sdwa vcc, v68, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v24, v68, vcc +; %bb.2214: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v66 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2215: + v_bfe_u32 v19, v66, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v25, v66, v19, s7 + ; implicit-def: $vgpr66 +; %bb.2216: ; %Flow1286 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2217: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v25, 0x10000, v66 + v_cmp_eq_u32_sdwa vcc, v66, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v25, v66, vcc +; %bb.2218: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v65 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2219: + v_bfe_u32 v19, v65, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v26, v65, v19, s7 + ; implicit-def: $vgpr65 +; %bb.2220: ; %Flow1285 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2221: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v26, 0x10000, v65 + v_cmp_eq_u32_sdwa vcc, v65, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v26, v65, vcc +; %bb.2222: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v64 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2223: + v_bfe_u32 v19, v64, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v27, v64, v19, s7 + ; implicit-def: $vgpr64 +; %bb.2224: ; %Flow1284 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2225: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v27, 0x10000, v64 + v_cmp_eq_u32_sdwa vcc, v64, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v27, v64, vcc +; %bb.2226: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v63 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2227: + v_bfe_u32 v19, v63, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v28, v63, v19, s7 + ; implicit-def: $vgpr63 +; %bb.2228: ; %Flow1283 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2229: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v28, 0x10000, v63 + v_cmp_eq_u32_sdwa vcc, v63, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v28, v63, vcc +; %bb.2230: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v62 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2231: + v_bfe_u32 v19, v62, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v29, v62, v19, s7 + ; implicit-def: $vgpr62 +; %bb.2232: ; %Flow1282 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2233: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v29, 0x10000, v62 + v_cmp_eq_u32_sdwa vcc, v62, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v29, v62, vcc +; %bb.2234: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v61 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2235: + v_bfe_u32 v19, v61, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v30, v61, v19, s7 + ; implicit-def: $vgpr61 +; %bb.2236: ; %Flow1281 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2237: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v30, 0x10000, v61 + v_cmp_eq_u32_sdwa vcc, v61, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v30, v61, vcc +; %bb.2238: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v60 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2239: + v_bfe_u32 v19, v60, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v31, v60, v19, s7 + ; implicit-def: $vgpr60 +; %bb.2240: ; %Flow1280 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2241: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v31, 0x10000, v60 + v_cmp_eq_u32_sdwa vcc, v60, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v31, v60, vcc +; %bb.2242: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v59 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2243: + v_bfe_u32 v19, v59, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v32, v59, v19, s7 + ; implicit-def: $vgpr59 +; %bb.2244: ; %Flow1279 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2245: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v32, 0x10000, v59 + v_cmp_eq_u32_sdwa vcc, v59, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v32, v59, vcc +; %bb.2246: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v58 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2247: + v_bfe_u32 v19, v58, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v33, v58, v19, s7 + ; implicit-def: $vgpr58 +; %bb.2248: ; %Flow1278 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2249: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v33, 0x10000, v58 + v_cmp_eq_u32_sdwa vcc, v58, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v33, v58, vcc +; %bb.2250: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v56 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2251: + v_bfe_u32 v19, v56, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v34, v56, v19, s7 + ; implicit-def: $vgpr56 +; %bb.2252: ; %Flow1277 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2253: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v34, 0x10000, v56 + v_cmp_eq_u32_sdwa vcc, v56, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v34, v56, vcc +; %bb.2254: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v57 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2255: + v_bfe_u32 v19, v57, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v35, v57, v19, s7 + ; implicit-def: $vgpr57 +; %bb.2256: ; %Flow1276 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2257: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v35, 0x10000, v57 + v_cmp_eq_u32_sdwa vcc, v57, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v35, v57, vcc +; %bb.2258: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v55 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2259: + v_bfe_u32 v19, v55, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v36, v55, v19, s7 + ; implicit-def: $vgpr55 +; %bb.2260: ; %Flow1275 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2261: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v36, 0x10000, v55 + v_cmp_eq_u32_sdwa vcc, v55, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v36, v55, vcc +; %bb.2262: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v54 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2263: + v_bfe_u32 v19, v54, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v37, v54, v19, s7 + ; implicit-def: $vgpr54 +; %bb.2264: ; %Flow1274 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2265: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v37, 0x10000, v54 + v_cmp_eq_u32_sdwa vcc, v54, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v37, v54, vcc +; %bb.2266: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v53 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2267: + v_bfe_u32 v19, v53, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v38, v53, v19, s7 + ; implicit-def: $vgpr53 +; %bb.2268: ; %Flow1273 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2269: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v38, 0x10000, v53 + v_cmp_eq_u32_sdwa vcc, v53, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v38, v53, vcc +; %bb.2270: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v52 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2271: + v_bfe_u32 v19, v52, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v39, v52, v19, s7 + ; implicit-def: $vgpr52 +; %bb.2272: ; %Flow1272 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2273: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v39, 0x10000, v52 + v_cmp_eq_u32_sdwa vcc, v52, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v39, v52, vcc +; %bb.2274: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v51 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2275: + v_bfe_u32 v19, v51, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v40, v51, v19, s7 + ; implicit-def: $vgpr51 +; %bb.2276: ; %Flow1271 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2277: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v40, 0x10000, v51 + v_cmp_eq_u32_sdwa vcc, v51, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v40, v51, vcc +; %bb.2278: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v50 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2279: + v_bfe_u32 v19, v50, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v41, v50, v19, s7 + ; implicit-def: $vgpr50 +; %bb.2280: ; %Flow1270 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2281: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v41, 0x10000, v50 + v_cmp_eq_u32_sdwa vcc, v50, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v50, vcc +; %bb.2282: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v49 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2283: + v_bfe_u32 v19, v49, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v42, v49, v19, s7 + ; implicit-def: $vgpr49 +; %bb.2284: ; %Flow1269 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2285: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v42, 0x10000, v49 + v_cmp_eq_u32_sdwa vcc, v49, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v42, v49, vcc +; %bb.2286: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v48 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2287: + v_bfe_u32 v19, v48, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v43, v48, v19, s7 + ; implicit-def: $vgpr48 +; %bb.2288: ; %Flow1268 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2289: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v43, 0x10000, v48 + v_cmp_eq_u32_sdwa vcc, v48, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v43, v48, vcc +; %bb.2290: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v47 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2291: + v_bfe_u32 v19, v47, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v48, v47, v19, s7 + ; implicit-def: $vgpr47 +; %bb.2292: ; %Flow1267 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2293: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v48, 0x10000, v47 + v_cmp_eq_u32_sdwa vcc, v47, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v48, v47, vcc +; %bb.2294: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v46 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2295: + v_bfe_u32 v19, v46, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v47, v46, v19, s7 + ; implicit-def: $vgpr46 +; %bb.2296: ; %Flow1266 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2297: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v47, 0x10000, v46 + v_cmp_eq_u32_sdwa vcc, v46, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v47, v46, vcc +; %bb.2298: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v45 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2299: + v_bfe_u32 v19, v45, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v46, v45, v19, s7 + ; implicit-def: $vgpr45 +; %bb.2300: ; %Flow1265 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2301: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v46, 0x10000, v45 + v_cmp_eq_u32_sdwa vcc, v45, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v46, v45, vcc +; %bb.2302: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v44 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2303: + v_bfe_u32 v19, v44, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v45, v44, v19, s7 + ; implicit-def: $vgpr44 +; %bb.2304: ; %Flow1264 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2305: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v45, 0x10000, v44 + v_cmp_eq_u32_sdwa vcc, v44, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v45, v44, vcc +; %bb.2306: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v255 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2307: + v_bfe_u32 v19, v255, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v44, v255, v19, s7 + ; implicit-def: $vgpr255 +; %bb.2308: ; %Flow1263 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2309: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v44, 0x10000, v255 + v_cmp_eq_u32_sdwa vcc, v255, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v44, v255, vcc +; %bb.2310: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v254 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2311: + v_bfe_u32 v19, v254, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v49, v254, v19, s7 + ; implicit-def: $vgpr254 +; %bb.2312: ; %Flow1262 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2313: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v49, 0x10000, v254 + v_cmp_eq_u32_sdwa vcc, v254, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v49, v254, vcc +; %bb.2314: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i.i.i.i.i.i + s_or_b64 exec, exec, s[2:3] + s_mov_b32 s2, 0x7f800000 + v_and_b32_e32 v19, 0x7f800000, v253 + v_cmp_ne_u32_e32 vcc, s2, v19 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[2:3], vcc + s_xor_b64 s[2:3], exec, s[2:3] +; %bb.2315: + v_bfe_u32 v19, v253, 16, 1 + s_movk_i32 s7, 0x7fff + v_add3_u32 v50, v253, v19, s7 + ; implicit-def: $vgpr253 +; %bb.2316: ; %Flow1261 + s_andn2_saveexec_b64 s[2:3], s[2:3] +; %bb.2317: + v_mov_b32_e32 v19, 0 + v_or_b32_e32 v50, 0x10000, v253 + v_cmp_eq_u32_sdwa vcc, v253, v19 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v50, v253, vcc +; %bb.2318: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP + s_or_b64 exec, exec, s[2:3] + s_add_i32 s2, s4, 0x7fffffff + s_mul_i32 s2, s2, s16 + s_add_i32 s5, s5, s2 + s_lshl_b32 s4, s5, 1 + v_and_b32_e32 v19, 24, v1 + s_lshr_b32 s2, s6, 2 + s_and_b32 s2, s2, 0x1ffffe0 + v_lshrrev_b32_e32 v51, 3, v1 + v_and_or_b32 v51, v51, 12, s2 + v_lshlrev_b32_e32 v51, 7, v51 + v_lshl_or_b32 v51, v67, 1, v51 + v_lshlrev_b32_e32 v19, 1, v19 + s_and_b32 s2, s6, 64 + v_or3_b32 v19, v51, v19, s2 + ds_write_b16_d16_hi v19, v18 + ds_write_b16_d16_hi v19, v20 offset:128 + ds_write_b16_d16_hi v19, v21 offset:256 + ds_write_b16_d16_hi v19, v22 offset:384 + ds_write_b16_d16_hi v19, v23 offset:1024 + ds_write_b16_d16_hi v19, v24 offset:1152 + ds_write_b16_d16_hi v19, v25 offset:1280 + ds_write_b16_d16_hi v19, v26 offset:1408 + ds_write_b16_d16_hi v19, v27 offset:2048 + ds_write_b16_d16_hi v19, v28 offset:2176 + ds_write_b16_d16_hi v19, v29 offset:2304 + ds_write_b16_d16_hi v19, v30 offset:2432 + ds_write_b16_d16_hi v19, v31 offset:3072 + ds_write_b16_d16_hi v19, v32 offset:3200 + ds_write_b16_d16_hi v19, v33 offset:3328 + ds_write_b16_d16_hi v19, v34 offset:3456 + ds_write_b16_d16_hi v19, v35 offset:8192 + ds_write_b16_d16_hi v19, v36 offset:8320 + ds_write_b16_d16_hi v19, v37 offset:8448 + ds_write_b16_d16_hi v19, v38 offset:8576 + ds_write_b16_d16_hi v19, v39 offset:9216 + ds_write_b16_d16_hi v19, v40 offset:9344 + ds_write_b16_d16_hi v19, v41 offset:9472 + ds_write_b16_d16_hi v19, v42 offset:9600 + ds_write_b16_d16_hi v19, v43 offset:10240 + ds_write_b16_d16_hi v19, v48 offset:10368 + ds_write_b16_d16_hi v19, v47 offset:10496 + ds_write_b16_d16_hi v19, v46 offset:10624 + ds_write_b16_d16_hi v19, v45 offset:11264 + ds_write_b16_d16_hi v19, v44 offset:11392 + ds_write_b16_d16_hi v19, v49 offset:11520 + ds_write_b16_d16_hi v19, v50 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s2, v0 + v_lshlrev_b32_e32 v18, 3, v1 + v_and_b32_e32 v20, 56, v18 + s_lshr_b32 s2, s2, 1 + s_and_b32 s2, s2, 0x7fffffe0 + v_lshrrev_b32_e32 v1, 1, v1 + v_and_b32_e32 v1, 60, v1 + v_add_u32_e32 v18, s2, v1 + v_lshlrev_b32_e32 v21, 7, v18 + v_lshl_or_b32 v21, v20, 1, v21 + ds_read_b128 v[24:27], v21 + ds_read_b128 v[28:31], v21 offset:128 + ds_read_b128 v[32:35], v21 offset:256 + ds_read_b128 v[36:39], v21 offset:384 + v_add_u32_e32 v21, s18, v18 + v_or_b32_e32 v18, s19, v20 + v_mad_u64_u32 v[22:23], s[2:3], v21, s16, v[18:19] + s_add_i32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v21, 1, v22 + s_waitcnt lgkmcnt(3) + s_nop 0 + buffer_store_dwordx2 v[24:25], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v21, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v22 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v22, s[0:3], 8 offen + v_add_u32_e32 v21, s16, v21 + v_lshlrev_b32_e32 v22, 1, v21 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v22, s[0:3], 8 offen + v_add_lshl_u32 v21, v21, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v21, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v21, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v21, 0x7f800000, v252 + v_cmp_ne_u32_e32 vcc, s4, v21 + ; implicit-def: $vgpr21 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2319: + v_bfe_u32 v21, v252, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v21, v252, v21, s6 + ; implicit-def: $vgpr252 +; %bb.2320: ; %Flow1260 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2321: + v_mov_b32_e32 v21, 0 + v_or_b32_e32 v22, 0x10000, v252 + v_cmp_eq_u32_sdwa vcc, v252, v21 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v21, v22, v252, vcc +; %bb.2322: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i65.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v251 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2323: + v_bfe_u32 v22, v251, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v251, v22, s6 + ; implicit-def: $vgpr251 +; %bb.2324: ; %Flow1259 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2325: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v251 + v_cmp_eq_u32_sdwa vcc, v251, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v251, vcc +; %bb.2326: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i68.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v250 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2327: + v_bfe_u32 v23, v250, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v250, v23, s6 + ; implicit-def: $vgpr250 +; %bb.2328: ; %Flow1258 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2329: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v250 + v_cmp_eq_u32_sdwa vcc, v250, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v250, vcc +; %bb.2330: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i71.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v249 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2331: + v_bfe_u32 v24, v249, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v249, v24, s6 + ; implicit-def: $vgpr249 +; %bb.2332: ; %Flow1257 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2333: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v249 + v_cmp_eq_u32_sdwa vcc, v249, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v249, vcc +; %bb.2334: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i74.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v248 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2335: + v_bfe_u32 v25, v248, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v248, v25, s6 + ; implicit-def: $vgpr248 +; %bb.2336: ; %Flow1256 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2337: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v248 + v_cmp_eq_u32_sdwa vcc, v248, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v248, vcc +; %bb.2338: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i77.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v247 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2339: + v_bfe_u32 v26, v247, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v247, v26, s6 + ; implicit-def: $vgpr247 +; %bb.2340: ; %Flow1255 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2341: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v247 + v_cmp_eq_u32_sdwa vcc, v247, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v247, vcc +; %bb.2342: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i80.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v246 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2343: + v_bfe_u32 v27, v246, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v246, v27, s6 + ; implicit-def: $vgpr246 +; %bb.2344: ; %Flow1254 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2345: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v246 + v_cmp_eq_u32_sdwa vcc, v246, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v246, vcc +; %bb.2346: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i83.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v245 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2347: + v_bfe_u32 v28, v245, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v245, v28, s6 + ; implicit-def: $vgpr245 +; %bb.2348: ; %Flow1253 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2349: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v245 + v_cmp_eq_u32_sdwa vcc, v245, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v245, vcc +; %bb.2350: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i86.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v244 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2351: + v_bfe_u32 v29, v244, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v244, v29, s6 + ; implicit-def: $vgpr244 +; %bb.2352: ; %Flow1252 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2353: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v244 + v_cmp_eq_u32_sdwa vcc, v244, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v244, vcc +; %bb.2354: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i89.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v243 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2355: + v_bfe_u32 v30, v243, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v243, v30, s6 + ; implicit-def: $vgpr243 +; %bb.2356: ; %Flow1251 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2357: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v243 + v_cmp_eq_u32_sdwa vcc, v243, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v243, vcc +; %bb.2358: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i92.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v242 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2359: + v_bfe_u32 v31, v242, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v242, v31, s6 + ; implicit-def: $vgpr242 +; %bb.2360: ; %Flow1250 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2361: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v242 + v_cmp_eq_u32_sdwa vcc, v242, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v242, vcc +; %bb.2362: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i95.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v241 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2363: + v_bfe_u32 v32, v241, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v241, v32, s6 + ; implicit-def: $vgpr241 +; %bb.2364: ; %Flow1249 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2365: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v241 + v_cmp_eq_u32_sdwa vcc, v241, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v241, vcc +; %bb.2366: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i98.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v240 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2367: + v_bfe_u32 v33, v240, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v240, v33, s6 + ; implicit-def: $vgpr240 +; %bb.2368: ; %Flow1248 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2369: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v240 + v_cmp_eq_u32_sdwa vcc, v240, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v240, vcc +; %bb.2370: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i101.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v239 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2371: + v_bfe_u32 v34, v239, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v239, v34, s6 + ; implicit-def: $vgpr239 +; %bb.2372: ; %Flow1247 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2373: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v239 + v_cmp_eq_u32_sdwa vcc, v239, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v239, vcc +; %bb.2374: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i104.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v238 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2375: + v_bfe_u32 v35, v238, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v238, v35, s6 + ; implicit-def: $vgpr238 +; %bb.2376: ; %Flow1246 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2377: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v238 + v_cmp_eq_u32_sdwa vcc, v238, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v238, vcc +; %bb.2378: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i107.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v236 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2379: + v_bfe_u32 v36, v236, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v236, v36, s6 + ; implicit-def: $vgpr236 +; %bb.2380: ; %Flow1245 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2381: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v236 + v_cmp_eq_u32_sdwa vcc, v236, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v236, vcc +; %bb.2382: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i110.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v237 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2383: + v_bfe_u32 v37, v237, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v237, v37, s6 + ; implicit-def: $vgpr237 +; %bb.2384: ; %Flow1244 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2385: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v237 + v_cmp_eq_u32_sdwa vcc, v237, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v237, vcc +; %bb.2386: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i113.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v235 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2387: + v_bfe_u32 v38, v235, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v235, v38, s6 + ; implicit-def: $vgpr235 +; %bb.2388: ; %Flow1243 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2389: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v235 + v_cmp_eq_u32_sdwa vcc, v235, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v235, vcc +; %bb.2390: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i116.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v234 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2391: + v_bfe_u32 v39, v234, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v234, v39, s6 + ; implicit-def: $vgpr234 +; %bb.2392: ; %Flow1242 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2393: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v234 + v_cmp_eq_u32_sdwa vcc, v234, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v234, vcc +; %bb.2394: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i119.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v233 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2395: + v_bfe_u32 v40, v233, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v233, v40, s6 + ; implicit-def: $vgpr233 +; %bb.2396: ; %Flow1241 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2397: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v233 + v_cmp_eq_u32_sdwa vcc, v233, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v233, vcc +; %bb.2398: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i122.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v232 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2399: + v_bfe_u32 v41, v232, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v232, v41, s6 + ; implicit-def: $vgpr232 +; %bb.2400: ; %Flow1240 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2401: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v232 + v_cmp_eq_u32_sdwa vcc, v232, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v232, vcc +; %bb.2402: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i125.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v231 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2403: + v_bfe_u32 v42, v231, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v231, v42, s6 + ; implicit-def: $vgpr231 +; %bb.2404: ; %Flow1239 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2405: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v231 + v_cmp_eq_u32_sdwa vcc, v231, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v231, vcc +; %bb.2406: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i128.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v230 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2407: + v_bfe_u32 v43, v230, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v230, v43, s6 + ; implicit-def: $vgpr230 +; %bb.2408: ; %Flow1238 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2409: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v230 + v_cmp_eq_u32_sdwa vcc, v230, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v230, vcc +; %bb.2410: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i131.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v229 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2411: + v_bfe_u32 v44, v229, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v229, v44, s6 + ; implicit-def: $vgpr229 +; %bb.2412: ; %Flow1237 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2413: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v229 + v_cmp_eq_u32_sdwa vcc, v229, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v229, vcc +; %bb.2414: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i134.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v228 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2415: + v_bfe_u32 v45, v228, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v228, v45, s6 + ; implicit-def: $vgpr228 +; %bb.2416: ; %Flow1236 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2417: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v228 + v_cmp_eq_u32_sdwa vcc, v228, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v228, vcc +; %bb.2418: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i137.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v227 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2419: + v_bfe_u32 v46, v227, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v227, v46, s6 + ; implicit-def: $vgpr227 +; %bb.2420: ; %Flow1235 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2421: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v227 + v_cmp_eq_u32_sdwa vcc, v227, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v227, vcc +; %bb.2422: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i140.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v226 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2423: + v_bfe_u32 v47, v226, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v226, v47, s6 + ; implicit-def: $vgpr226 +; %bb.2424: ; %Flow1234 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2425: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v226 + v_cmp_eq_u32_sdwa vcc, v226, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v226, vcc +; %bb.2426: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i143.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v225 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2427: + v_bfe_u32 v48, v225, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v225, v48, s6 + ; implicit-def: $vgpr225 +; %bb.2428: ; %Flow1233 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2429: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v225 + v_cmp_eq_u32_sdwa vcc, v225, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v225, vcc +; %bb.2430: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i146.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v224 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2431: + v_bfe_u32 v49, v224, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v224, v49, s6 + ; implicit-def: $vgpr224 +; %bb.2432: ; %Flow1232 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2433: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v224 + v_cmp_eq_u32_sdwa vcc, v224, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v224, vcc +; %bb.2434: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i149.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v223 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2435: + v_bfe_u32 v50, v223, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v223, v50, s6 + ; implicit-def: $vgpr223 +; %bb.2436: ; %Flow1231 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2437: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v223 + v_cmp_eq_u32_sdwa vcc, v223, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v223, vcc +; %bb.2438: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i152.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v222 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2439: + v_bfe_u32 v51, v222, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v222, v51, s6 + ; implicit-def: $vgpr222 +; %bb.2440: ; %Flow1230 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2441: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v222 + v_cmp_eq_u32_sdwa vcc, v222, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v222, vcc +; %bb.2442: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i155.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v221 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2443: + v_bfe_u32 v52, v221, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v221, v52, s6 + ; implicit-def: $vgpr221 +; %bb.2444: ; %Flow1229 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2445: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v221 + v_cmp_eq_u32_sdwa vcc, v221, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v221, vcc +; %bb.2446: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_287 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v21 + ds_write_b16_d16_hi v19, v22 offset:128 + ds_write_b16_d16_hi v19, v23 offset:256 + ds_write_b16_d16_hi v19, v24 offset:384 + ds_write_b16_d16_hi v19, v25 offset:1024 + ds_write_b16_d16_hi v19, v26 offset:1152 + ds_write_b16_d16_hi v19, v27 offset:1280 + ds_write_b16_d16_hi v19, v28 offset:1408 + ds_write_b16_d16_hi v19, v29 offset:2048 + ds_write_b16_d16_hi v19, v30 offset:2176 + ds_write_b16_d16_hi v19, v31 offset:2304 + ds_write_b16_d16_hi v19, v32 offset:2432 + ds_write_b16_d16_hi v19, v33 offset:3072 + ds_write_b16_d16_hi v19, v34 offset:3200 + ds_write_b16_d16_hi v19, v35 offset:3328 + ds_write_b16_d16_hi v19, v36 offset:3456 + ds_write_b16_d16_hi v19, v37 offset:8192 + ds_write_b16_d16_hi v19, v38 offset:8320 + ds_write_b16_d16_hi v19, v39 offset:8448 + ds_write_b16_d16_hi v19, v40 offset:8576 + ds_write_b16_d16_hi v19, v41 offset:9216 + ds_write_b16_d16_hi v19, v42 offset:9344 + ds_write_b16_d16_hi v19, v43 offset:9472 + ds_write_b16_d16_hi v19, v44 offset:9600 + ds_write_b16_d16_hi v19, v45 offset:10240 + ds_write_b16_d16_hi v19, v46 offset:10368 + ds_write_b16_d16_hi v19, v47 offset:10496 + ds_write_b16_d16_hi v19, v48 offset:10624 + ds_write_b16_d16_hi v19, v49 offset:11264 + ds_write_b16_d16_hi v19, v50 offset:11392 + ds_write_b16_d16_hi v19, v51 offset:11520 + ds_write_b16_d16_hi v19, v52 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshlrev_b32_e32 v21, 1, v20 + v_lshl_or_b32 v20, v22, 7, v21 + ds_read_b128 v[24:27], v20 + ds_read_b128 v[28:31], v20 offset:128 + ds_read_b128 v[32:35], v20 offset:256 + ds_read_b128 v[36:39], v20 offset:384 + v_add_u32_e32 v22, s18, v22 + v_or_b32_e32 v20, 64, v18 + v_mad_u64_u32 v[22:23], s[4:5], v22, s16, v[20:21] + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[24:25], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[32:33], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v23, s[0:3], 8 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[36:37], v22, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v22, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v220 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2447: + v_bfe_u32 v22, v220, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v220, v22, s6 + ; implicit-def: $vgpr220 +; %bb.2448: ; %Flow1228 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2449: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v220 + v_cmp_eq_u32_sdwa vcc, v220, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v220, vcc +; %bb.2450: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i352.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v219 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2451: + v_bfe_u32 v23, v219, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v219, v23, s6 + ; implicit-def: $vgpr219 +; %bb.2452: ; %Flow1227 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2453: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v219 + v_cmp_eq_u32_sdwa vcc, v219, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v219, vcc +; %bb.2454: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i355.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v218 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2455: + v_bfe_u32 v24, v218, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v218, v24, s6 + ; implicit-def: $vgpr218 +; %bb.2456: ; %Flow1226 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2457: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v218 + v_cmp_eq_u32_sdwa vcc, v218, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v218, vcc +; %bb.2458: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i358.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v217 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2459: + v_bfe_u32 v25, v217, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v217, v25, s6 + ; implicit-def: $vgpr217 +; %bb.2460: ; %Flow1225 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2461: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v217 + v_cmp_eq_u32_sdwa vcc, v217, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v217, vcc +; %bb.2462: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i361.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v216 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2463: + v_bfe_u32 v26, v216, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v216, v26, s6 + ; implicit-def: $vgpr216 +; %bb.2464: ; %Flow1224 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2465: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v216 + v_cmp_eq_u32_sdwa vcc, v216, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v216, vcc +; %bb.2466: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i364.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v215 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2467: + v_bfe_u32 v27, v215, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v215, v27, s6 + ; implicit-def: $vgpr215 +; %bb.2468: ; %Flow1223 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2469: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v215 + v_cmp_eq_u32_sdwa vcc, v215, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v215, vcc +; %bb.2470: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i367.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v214 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2471: + v_bfe_u32 v28, v214, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v214, v28, s6 + ; implicit-def: $vgpr214 +; %bb.2472: ; %Flow1222 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2473: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v214 + v_cmp_eq_u32_sdwa vcc, v214, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v214, vcc +; %bb.2474: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i370.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v213 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2475: + v_bfe_u32 v29, v213, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v213, v29, s6 + ; implicit-def: $vgpr213 +; %bb.2476: ; %Flow1221 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2477: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v213 + v_cmp_eq_u32_sdwa vcc, v213, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v213, vcc +; %bb.2478: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i373.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v212 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2479: + v_bfe_u32 v30, v212, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v212, v30, s6 + ; implicit-def: $vgpr212 +; %bb.2480: ; %Flow1220 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2481: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v212 + v_cmp_eq_u32_sdwa vcc, v212, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v212, vcc +; %bb.2482: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i376.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v211 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2483: + v_bfe_u32 v31, v211, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v211, v31, s6 + ; implicit-def: $vgpr211 +; %bb.2484: ; %Flow1219 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2485: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v211 + v_cmp_eq_u32_sdwa vcc, v211, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v211, vcc +; %bb.2486: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i379.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v210 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2487: + v_bfe_u32 v32, v210, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v210, v32, s6 + ; implicit-def: $vgpr210 +; %bb.2488: ; %Flow1218 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2489: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v210 + v_cmp_eq_u32_sdwa vcc, v210, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v210, vcc +; %bb.2490: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i382.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v209 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2491: + v_bfe_u32 v33, v209, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v209, v33, s6 + ; implicit-def: $vgpr209 +; %bb.2492: ; %Flow1217 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2493: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v209 + v_cmp_eq_u32_sdwa vcc, v209, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v209, vcc +; %bb.2494: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i385.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v208 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2495: + v_bfe_u32 v34, v208, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v208, v34, s6 + ; implicit-def: $vgpr208 +; %bb.2496: ; %Flow1216 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2497: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v208 + v_cmp_eq_u32_sdwa vcc, v208, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v208, vcc +; %bb.2498: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i388.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v207 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2499: + v_bfe_u32 v35, v207, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v207, v35, s6 + ; implicit-def: $vgpr207 +; %bb.2500: ; %Flow1215 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2501: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v207 + v_cmp_eq_u32_sdwa vcc, v207, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v207, vcc +; %bb.2502: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i391.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v206 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2503: + v_bfe_u32 v36, v206, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v206, v36, s6 + ; implicit-def: $vgpr206 +; %bb.2504: ; %Flow1214 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2505: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v206 + v_cmp_eq_u32_sdwa vcc, v206, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v206, vcc +; %bb.2506: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i394.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v204 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2507: + v_bfe_u32 v37, v204, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v204, v37, s6 + ; implicit-def: $vgpr204 +; %bb.2508: ; %Flow1213 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2509: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v204 + v_cmp_eq_u32_sdwa vcc, v204, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v204, vcc +; %bb.2510: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i397.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v205 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2511: + v_bfe_u32 v38, v205, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v205, v38, s6 + ; implicit-def: $vgpr205 +; %bb.2512: ; %Flow1212 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2513: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v205 + v_cmp_eq_u32_sdwa vcc, v205, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v205, vcc +; %bb.2514: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i400.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v203 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2515: + v_bfe_u32 v39, v203, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v203, v39, s6 + ; implicit-def: $vgpr203 +; %bb.2516: ; %Flow1211 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2517: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v203 + v_cmp_eq_u32_sdwa vcc, v203, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v203, vcc +; %bb.2518: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i403.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v202 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2519: + v_bfe_u32 v40, v202, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v202, v40, s6 + ; implicit-def: $vgpr202 +; %bb.2520: ; %Flow1210 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2521: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v202 + v_cmp_eq_u32_sdwa vcc, v202, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v202, vcc +; %bb.2522: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i406.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v201 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2523: + v_bfe_u32 v41, v201, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v201, v41, s6 + ; implicit-def: $vgpr201 +; %bb.2524: ; %Flow1209 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2525: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v201 + v_cmp_eq_u32_sdwa vcc, v201, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v201, vcc +; %bb.2526: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i409.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v200 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2527: + v_bfe_u32 v42, v200, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v200, v42, s6 + ; implicit-def: $vgpr200 +; %bb.2528: ; %Flow1208 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2529: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v200 + v_cmp_eq_u32_sdwa vcc, v200, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v200, vcc +; %bb.2530: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i412.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v199 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2531: + v_bfe_u32 v43, v199, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v199, v43, s6 + ; implicit-def: $vgpr199 +; %bb.2532: ; %Flow1207 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2533: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v199 + v_cmp_eq_u32_sdwa vcc, v199, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v199, vcc +; %bb.2534: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i415.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v198 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2535: + v_bfe_u32 v44, v198, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v198, v44, s6 + ; implicit-def: $vgpr198 +; %bb.2536: ; %Flow1206 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2537: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v198 + v_cmp_eq_u32_sdwa vcc, v198, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v198, vcc +; %bb.2538: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i418.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v197 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2539: + v_bfe_u32 v45, v197, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v197, v45, s6 + ; implicit-def: $vgpr197 +; %bb.2540: ; %Flow1205 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2541: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v197 + v_cmp_eq_u32_sdwa vcc, v197, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v197, vcc +; %bb.2542: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i421.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v196 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2543: + v_bfe_u32 v46, v196, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v196, v46, s6 + ; implicit-def: $vgpr196 +; %bb.2544: ; %Flow1204 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2545: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v196 + v_cmp_eq_u32_sdwa vcc, v196, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v196, vcc +; %bb.2546: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i424.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v195 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2547: + v_bfe_u32 v47, v195, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v195, v47, s6 + ; implicit-def: $vgpr195 +; %bb.2548: ; %Flow1203 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2549: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v195 + v_cmp_eq_u32_sdwa vcc, v195, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v195, vcc +; %bb.2550: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i427.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v194 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2551: + v_bfe_u32 v48, v194, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v194, v48, s6 + ; implicit-def: $vgpr194 +; %bb.2552: ; %Flow1202 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2553: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v194 + v_cmp_eq_u32_sdwa vcc, v194, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v194, vcc +; %bb.2554: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i430.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v193 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2555: + v_bfe_u32 v49, v193, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v193, v49, s6 + ; implicit-def: $vgpr193 +; %bb.2556: ; %Flow1201 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2557: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v193 + v_cmp_eq_u32_sdwa vcc, v193, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v193, vcc +; %bb.2558: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i433.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v192 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2559: + v_bfe_u32 v50, v192, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v192, v50, s6 + ; implicit-def: $vgpr192 +; %bb.2560: ; %Flow1200 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2561: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v192 + v_cmp_eq_u32_sdwa vcc, v192, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v192, vcc +; %bb.2562: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i436.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v191 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2563: + v_bfe_u32 v51, v191, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v191, v51, s6 + ; implicit-def: $vgpr191 +; %bb.2564: ; %Flow1199 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2565: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v191 + v_cmp_eq_u32_sdwa vcc, v191, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v191, vcc +; %bb.2566: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i439.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v190 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2567: + v_bfe_u32 v52, v190, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v190, v52, s6 + ; implicit-def: $vgpr190 +; %bb.2568: ; %Flow1198 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2569: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v190 + v_cmp_eq_u32_sdwa vcc, v190, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v190, vcc +; %bb.2570: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i442.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v189 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2571: + v_bfe_u32 v53, v189, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v189, v53, s6 + ; implicit-def: $vgpr189 +; %bb.2572: ; %Flow1197 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2573: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v189 + v_cmp_eq_u32_sdwa vcc, v189, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v189, vcc +; %bb.2574: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_574 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v22 + ds_write_b16_d16_hi v19, v23 offset:128 + ds_write_b16_d16_hi v19, v24 offset:256 + ds_write_b16_d16_hi v19, v25 offset:384 + ds_write_b16_d16_hi v19, v26 offset:1024 + ds_write_b16_d16_hi v19, v27 offset:1152 + ds_write_b16_d16_hi v19, v28 offset:1280 + ds_write_b16_d16_hi v19, v29 offset:1408 + ds_write_b16_d16_hi v19, v30 offset:2048 + ds_write_b16_d16_hi v19, v31 offset:2176 + ds_write_b16_d16_hi v19, v32 offset:2304 + ds_write_b16_d16_hi v19, v33 offset:2432 + ds_write_b16_d16_hi v19, v34 offset:3072 + ds_write_b16_d16_hi v19, v35 offset:3200 + ds_write_b16_d16_hi v19, v36 offset:3328 + ds_write_b16_d16_hi v19, v37 offset:3456 + ds_write_b16_d16_hi v19, v38 offset:8192 + ds_write_b16_d16_hi v19, v39 offset:8320 + ds_write_b16_d16_hi v19, v40 offset:8448 + ds_write_b16_d16_hi v19, v41 offset:8576 + ds_write_b16_d16_hi v19, v42 offset:9216 + ds_write_b16_d16_hi v19, v43 offset:9344 + ds_write_b16_d16_hi v19, v44 offset:9472 + ds_write_b16_d16_hi v19, v45 offset:9600 + ds_write_b16_d16_hi v19, v46 offset:10240 + ds_write_b16_d16_hi v19, v47 offset:10368 + ds_write_b16_d16_hi v19, v48 offset:10496 + ds_write_b16_d16_hi v19, v49 offset:10624 + ds_write_b16_d16_hi v19, v50 offset:11264 + ds_write_b16_d16_hi v19, v51 offset:11392 + ds_write_b16_d16_hi v19, v52 offset:11520 + ds_write_b16_d16_hi v19, v53 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v22, s4, v1 + v_lshl_or_b32 v23, v22, 7, v21 + ds_read_b128 v[26:29], v23 + ds_read_b128 v[30:33], v23 offset:128 + ds_read_b128 v[34:37], v23 offset:256 + ds_read_b128 v[38:41], v23 offset:384 + v_add_u32_e32 v23, s18, v22 + v_or_b32_e32 v22, 0x80, v18 + v_mad_u64_u32 v[24:25], s[4:5], v23, s16, v[22:23] + v_lshlrev_b32_e32 v23, 1, v24 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[26:27], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v24 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[30:31], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[32:33], v24, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[34:35], v24, s[0:3], 0 offen + buffer_store_dwordx2 v[36:37], v24, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[38:39], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[40:41], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v188 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2575: + v_bfe_u32 v23, v188, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v188, v23, s6 + ; implicit-def: $vgpr188 +; %bb.2576: ; %Flow1196 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2577: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v188 + v_cmp_eq_u32_sdwa vcc, v188, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v188, vcc +; %bb.2578: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i639.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v187 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2579: + v_bfe_u32 v24, v187, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v187, v24, s6 + ; implicit-def: $vgpr187 +; %bb.2580: ; %Flow1195 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2581: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v187 + v_cmp_eq_u32_sdwa vcc, v187, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v187, vcc +; %bb.2582: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i642.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v186 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2583: + v_bfe_u32 v25, v186, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v186, v25, s6 + ; implicit-def: $vgpr186 +; %bb.2584: ; %Flow1194 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2585: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v186 + v_cmp_eq_u32_sdwa vcc, v186, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v186, vcc +; %bb.2586: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i645.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v185 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2587: + v_bfe_u32 v26, v185, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v185, v26, s6 + ; implicit-def: $vgpr185 +; %bb.2588: ; %Flow1193 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2589: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v185 + v_cmp_eq_u32_sdwa vcc, v185, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v185, vcc +; %bb.2590: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i648.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v184 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2591: + v_bfe_u32 v27, v184, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v184, v27, s6 + ; implicit-def: $vgpr184 +; %bb.2592: ; %Flow1192 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2593: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v184 + v_cmp_eq_u32_sdwa vcc, v184, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v184, vcc +; %bb.2594: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i651.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v183 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2595: + v_bfe_u32 v28, v183, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v183, v28, s6 + ; implicit-def: $vgpr183 +; %bb.2596: ; %Flow1191 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2597: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v183 + v_cmp_eq_u32_sdwa vcc, v183, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v183, vcc +; %bb.2598: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i654.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v182 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2599: + v_bfe_u32 v29, v182, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v182, v29, s6 + ; implicit-def: $vgpr182 +; %bb.2600: ; %Flow1190 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2601: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v182 + v_cmp_eq_u32_sdwa vcc, v182, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v182, vcc +; %bb.2602: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i657.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v181 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2603: + v_bfe_u32 v30, v181, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v181, v30, s6 + ; implicit-def: $vgpr181 +; %bb.2604: ; %Flow1189 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2605: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v181 + v_cmp_eq_u32_sdwa vcc, v181, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v181, vcc +; %bb.2606: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i660.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v180 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2607: + v_bfe_u32 v31, v180, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v180, v31, s6 + ; implicit-def: $vgpr180 +; %bb.2608: ; %Flow1188 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2609: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v180 + v_cmp_eq_u32_sdwa vcc, v180, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v180, vcc +; %bb.2610: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i663.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v179 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2611: + v_bfe_u32 v32, v179, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v179, v32, s6 + ; implicit-def: $vgpr179 +; %bb.2612: ; %Flow1187 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2613: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v179 + v_cmp_eq_u32_sdwa vcc, v179, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v179, vcc +; %bb.2614: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i666.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v178 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2615: + v_bfe_u32 v33, v178, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v178, v33, s6 + ; implicit-def: $vgpr178 +; %bb.2616: ; %Flow1186 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2617: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v178 + v_cmp_eq_u32_sdwa vcc, v178, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v178, vcc +; %bb.2618: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i669.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v177 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2619: + v_bfe_u32 v34, v177, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v177, v34, s6 + ; implicit-def: $vgpr177 +; %bb.2620: ; %Flow1185 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2621: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v177 + v_cmp_eq_u32_sdwa vcc, v177, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v177, vcc +; %bb.2622: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i672.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v176 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2623: + v_bfe_u32 v35, v176, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v176, v35, s6 + ; implicit-def: $vgpr176 +; %bb.2624: ; %Flow1184 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2625: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v176 + v_cmp_eq_u32_sdwa vcc, v176, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v176, vcc +; %bb.2626: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i675.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v175 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2627: + v_bfe_u32 v36, v175, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v175, v36, s6 + ; implicit-def: $vgpr175 +; %bb.2628: ; %Flow1183 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2629: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v175 + v_cmp_eq_u32_sdwa vcc, v175, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v175, vcc +; %bb.2630: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i678.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v174 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2631: + v_bfe_u32 v37, v174, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v174, v37, s6 + ; implicit-def: $vgpr174 +; %bb.2632: ; %Flow1182 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2633: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v174 + v_cmp_eq_u32_sdwa vcc, v174, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v174, vcc +; %bb.2634: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i681.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v172 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2635: + v_bfe_u32 v38, v172, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v172, v38, s6 + ; implicit-def: $vgpr172 +; %bb.2636: ; %Flow1181 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2637: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v172 + v_cmp_eq_u32_sdwa vcc, v172, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v172, vcc +; %bb.2638: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i684.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v173 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2639: + v_bfe_u32 v39, v173, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v173, v39, s6 + ; implicit-def: $vgpr173 +; %bb.2640: ; %Flow1180 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2641: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v173 + v_cmp_eq_u32_sdwa vcc, v173, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v173, vcc +; %bb.2642: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i687.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v171 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2643: + v_bfe_u32 v40, v171, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v171, v40, s6 + ; implicit-def: $vgpr171 +; %bb.2644: ; %Flow1179 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2645: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v171 + v_cmp_eq_u32_sdwa vcc, v171, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v171, vcc +; %bb.2646: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i690.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v41, 0x7f800000, v170 + v_cmp_ne_u32_e32 vcc, s4, v41 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2647: + v_bfe_u32 v41, v170, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v170, v41, s6 + ; implicit-def: $vgpr170 +; %bb.2648: ; %Flow1178 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2649: + v_mov_b32_e32 v41, 0 + v_or_b32_e32 v42, 0x10000, v170 + v_cmp_eq_u32_sdwa vcc, v170, v41 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v42, v170, vcc +; %bb.2650: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i693.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v42, 0x7f800000, v169 + v_cmp_ne_u32_e32 vcc, s4, v42 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2651: + v_bfe_u32 v42, v169, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v169, v42, s6 + ; implicit-def: $vgpr169 +; %bb.2652: ; %Flow1177 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2653: + v_mov_b32_e32 v42, 0 + v_or_b32_e32 v43, 0x10000, v169 + v_cmp_eq_u32_sdwa vcc, v169, v42 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v43, v169, vcc +; %bb.2654: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i696.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v43, 0x7f800000, v168 + v_cmp_ne_u32_e32 vcc, s4, v43 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2655: + v_bfe_u32 v43, v168, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v168, v43, s6 + ; implicit-def: $vgpr168 +; %bb.2656: ; %Flow1176 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2657: + v_mov_b32_e32 v43, 0 + v_or_b32_e32 v44, 0x10000, v168 + v_cmp_eq_u32_sdwa vcc, v168, v43 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v44, v168, vcc +; %bb.2658: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i699.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v44, 0x7f800000, v167 + v_cmp_ne_u32_e32 vcc, s4, v44 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2659: + v_bfe_u32 v44, v167, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v167, v44, s6 + ; implicit-def: $vgpr167 +; %bb.2660: ; %Flow1175 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2661: + v_mov_b32_e32 v44, 0 + v_or_b32_e32 v45, 0x10000, v167 + v_cmp_eq_u32_sdwa vcc, v167, v44 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v45, v167, vcc +; %bb.2662: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i702.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v45, 0x7f800000, v166 + v_cmp_ne_u32_e32 vcc, s4, v45 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2663: + v_bfe_u32 v45, v166, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v166, v45, s6 + ; implicit-def: $vgpr166 +; %bb.2664: ; %Flow1174 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2665: + v_mov_b32_e32 v45, 0 + v_or_b32_e32 v46, 0x10000, v166 + v_cmp_eq_u32_sdwa vcc, v166, v45 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v46, v166, vcc +; %bb.2666: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i705.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v46, 0x7f800000, v165 + v_cmp_ne_u32_e32 vcc, s4, v46 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2667: + v_bfe_u32 v46, v165, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v165, v46, s6 + ; implicit-def: $vgpr165 +; %bb.2668: ; %Flow1173 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2669: + v_mov_b32_e32 v46, 0 + v_or_b32_e32 v47, 0x10000, v165 + v_cmp_eq_u32_sdwa vcc, v165, v46 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v47, v165, vcc +; %bb.2670: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i708.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v47, 0x7f800000, v164 + v_cmp_ne_u32_e32 vcc, s4, v47 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2671: + v_bfe_u32 v47, v164, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v164, v47, s6 + ; implicit-def: $vgpr164 +; %bb.2672: ; %Flow1172 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2673: + v_mov_b32_e32 v47, 0 + v_or_b32_e32 v48, 0x10000, v164 + v_cmp_eq_u32_sdwa vcc, v164, v47 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v48, v164, vcc +; %bb.2674: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i711.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v48, 0x7f800000, v163 + v_cmp_ne_u32_e32 vcc, s4, v48 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2675: + v_bfe_u32 v48, v163, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v163, v48, s6 + ; implicit-def: $vgpr163 +; %bb.2676: ; %Flow1171 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2677: + v_mov_b32_e32 v48, 0 + v_or_b32_e32 v49, 0x10000, v163 + v_cmp_eq_u32_sdwa vcc, v163, v48 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v49, v163, vcc +; %bb.2678: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i714.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v49, 0x7f800000, v162 + v_cmp_ne_u32_e32 vcc, s4, v49 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2679: + v_bfe_u32 v49, v162, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v162, v49, s6 + ; implicit-def: $vgpr162 +; %bb.2680: ; %Flow1170 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2681: + v_mov_b32_e32 v49, 0 + v_or_b32_e32 v50, 0x10000, v162 + v_cmp_eq_u32_sdwa vcc, v162, v49 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v50, v162, vcc +; %bb.2682: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i717.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v50, 0x7f800000, v161 + v_cmp_ne_u32_e32 vcc, s4, v50 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2683: + v_bfe_u32 v50, v161, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v161, v50, s6 + ; implicit-def: $vgpr161 +; %bb.2684: ; %Flow1169 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2685: + v_mov_b32_e32 v50, 0 + v_or_b32_e32 v51, 0x10000, v161 + v_cmp_eq_u32_sdwa vcc, v161, v50 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v51, v161, vcc +; %bb.2686: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i720.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v51, 0x7f800000, v160 + v_cmp_ne_u32_e32 vcc, s4, v51 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2687: + v_bfe_u32 v51, v160, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v160, v51, s6 + ; implicit-def: $vgpr160 +; %bb.2688: ; %Flow1168 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2689: + v_mov_b32_e32 v51, 0 + v_or_b32_e32 v52, 0x10000, v160 + v_cmp_eq_u32_sdwa vcc, v160, v51 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v52, v160, vcc +; %bb.2690: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i723.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v52, 0x7f800000, v159 + v_cmp_ne_u32_e32 vcc, s4, v52 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2691: + v_bfe_u32 v52, v159, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v159, v52, s6 + ; implicit-def: $vgpr159 +; %bb.2692: ; %Flow1167 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2693: + v_mov_b32_e32 v52, 0 + v_or_b32_e32 v53, 0x10000, v159 + v_cmp_eq_u32_sdwa vcc, v159, v52 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v53, v159, vcc +; %bb.2694: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i726.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v53, 0x7f800000, v158 + v_cmp_ne_u32_e32 vcc, s4, v53 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2695: + v_bfe_u32 v53, v158, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v158, v53, s6 + ; implicit-def: $vgpr158 +; %bb.2696: ; %Flow1166 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2697: + v_mov_b32_e32 v53, 0 + v_or_b32_e32 v54, 0x10000, v158 + v_cmp_eq_u32_sdwa vcc, v158, v53 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v54, v158, vcc +; %bb.2698: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i729.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v54, 0x7f800000, v157 + v_cmp_ne_u32_e32 vcc, s4, v54 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2699: + v_bfe_u32 v54, v157, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v157, v54, s6 + ; implicit-def: $vgpr157 +; %bb.2700: ; %Flow1165 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2701: + v_mov_b32_e32 v54, 0 + v_or_b32_e32 v55, 0x10000, v157 + v_cmp_eq_u32_sdwa vcc, v157, v54 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v55, v157, vcc +; %bb.2702: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_861 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v24 offset:128 + ds_write_b16_d16_hi v19, v25 offset:256 + ds_write_b16_d16_hi v19, v26 offset:384 + ds_write_b16_d16_hi v19, v27 offset:1024 + ds_write_b16_d16_hi v19, v28 offset:1152 + ds_write_b16_d16_hi v19, v29 offset:1280 + ds_write_b16_d16_hi v19, v30 offset:1408 + ds_write_b16_d16_hi v19, v31 offset:2048 + ds_write_b16_d16_hi v19, v32 offset:2176 + ds_write_b16_d16_hi v19, v33 offset:2304 + ds_write_b16_d16_hi v19, v34 offset:2432 + ds_write_b16_d16_hi v19, v35 offset:3072 + ds_write_b16_d16_hi v19, v36 offset:3200 + ds_write_b16_d16_hi v19, v37 offset:3328 + ds_write_b16_d16_hi v19, v38 offset:3456 + ds_write_b16_d16_hi v19, v39 offset:8192 + ds_write_b16_d16_hi v19, v40 offset:8320 + ds_write_b16_d16_hi v19, v41 offset:8448 + ds_write_b16_d16_hi v19, v42 offset:8576 + ds_write_b16_d16_hi v19, v43 offset:9216 + ds_write_b16_d16_hi v19, v44 offset:9344 + ds_write_b16_d16_hi v19, v45 offset:9472 + ds_write_b16_d16_hi v19, v46 offset:9600 + ds_write_b16_d16_hi v19, v47 offset:10240 + ds_write_b16_d16_hi v19, v48 offset:10368 + ds_write_b16_d16_hi v19, v49 offset:10496 + ds_write_b16_d16_hi v19, v50 offset:10624 + ds_write_b16_d16_hi v19, v51 offset:11264 + ds_write_b16_d16_hi v19, v52 offset:11392 + ds_write_b16_d16_hi v19, v53 offset:11520 + ds_write_b16_d16_hi v19, v54 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v23, s4, v1 + v_lshl_or_b32 v24, v23, 7, v21 + ds_read_b128 v[28:31], v24 + ds_read_b128 v[32:35], v24 offset:128 + ds_read_b128 v[36:39], v24 offset:256 + ds_read_b128 v[40:43], v24 offset:384 + v_add_u32_e32 v23, s18, v23 + v_or_b32_e32 v24, 0xc0, v18 + v_mad_u64_u32 v[26:27], s[4:5], v23, s16, v[24:25] + v_lshlrev_b32_e32 v23, 1, v26 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[28:29], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[30:31], v23, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v26 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[32:33], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[34:35], v25, s[0:3], 8 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v25, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[36:37], v25, s[0:3], 0 offen + buffer_store_dwordx2 v[38:39], v25, s[0:3], 8 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[40:41], v23, s[0:3], 0 offen + buffer_store_dwordx2 v[42:43], v23, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v156 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2703: + v_bfe_u32 v23, v156, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v156, v23, s6 + ; implicit-def: $vgpr156 +; %bb.2704: ; %Flow1164 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2705: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v25, 0x10000, v156 + v_cmp_eq_u32_sdwa vcc, v156, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v25, v156, vcc +; %bb.2706: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i926.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v155 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2707: + v_bfe_u32 v25, v155, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v155, v25, s6 + ; implicit-def: $vgpr155 +; %bb.2708: ; %Flow1163 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2709: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v155 + v_cmp_eq_u32_sdwa vcc, v155, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v155, vcc +; %bb.2710: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i929.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v154 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2711: + v_bfe_u32 v26, v154, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v154, v26, s6 + ; implicit-def: $vgpr154 +; %bb.2712: ; %Flow1162 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2713: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v154 + v_cmp_eq_u32_sdwa vcc, v154, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v154, vcc +; %bb.2714: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i932.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v153 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2715: + v_bfe_u32 v27, v153, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v153, v27, s6 + ; implicit-def: $vgpr153 +; %bb.2716: ; %Flow1161 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2717: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v153 + v_cmp_eq_u32_sdwa vcc, v153, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v153, vcc +; %bb.2718: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i935.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v152 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2719: + v_bfe_u32 v28, v152, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v152, v28, s6 + ; implicit-def: $vgpr152 +; %bb.2720: ; %Flow1160 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2721: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v152 + v_cmp_eq_u32_sdwa vcc, v152, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v152, vcc +; %bb.2722: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i938.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v151 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2723: + v_bfe_u32 v29, v151, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v151, v29, s6 + ; implicit-def: $vgpr151 +; %bb.2724: ; %Flow1159 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2725: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v151 + v_cmp_eq_u32_sdwa vcc, v151, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v151, vcc +; %bb.2726: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i941.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v150 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2727: + v_bfe_u32 v30, v150, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v150, v30, s6 + ; implicit-def: $vgpr150 +; %bb.2728: ; %Flow1158 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2729: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v150 + v_cmp_eq_u32_sdwa vcc, v150, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v150, vcc +; %bb.2730: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i944.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v149 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2731: + v_bfe_u32 v31, v149, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v149, v31, s6 + ; implicit-def: $vgpr149 +; %bb.2732: ; %Flow1157 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2733: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v149 + v_cmp_eq_u32_sdwa vcc, v149, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v149, vcc +; %bb.2734: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i947.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v148 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2735: + v_bfe_u32 v32, v148, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v148, v32, s6 + ; implicit-def: $vgpr148 +; %bb.2736: ; %Flow1156 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2737: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v148 + v_cmp_eq_u32_sdwa vcc, v148, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v148, vcc +; %bb.2738: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i950.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v147 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2739: + v_bfe_u32 v33, v147, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v147, v33, s6 + ; implicit-def: $vgpr147 +; %bb.2740: ; %Flow1155 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2741: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v147 + v_cmp_eq_u32_sdwa vcc, v147, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v147, vcc +; %bb.2742: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i953.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v146 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2743: + v_bfe_u32 v34, v146, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v146, v34, s6 + ; implicit-def: $vgpr146 +; %bb.2744: ; %Flow1154 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2745: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v146 + v_cmp_eq_u32_sdwa vcc, v146, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v146, vcc +; %bb.2746: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i956.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v145 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2747: + v_bfe_u32 v35, v145, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v145, v35, s6 + ; implicit-def: $vgpr145 +; %bb.2748: ; %Flow1153 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2749: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v145 + v_cmp_eq_u32_sdwa vcc, v145, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v145, vcc +; %bb.2750: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i959.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v144 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2751: + v_bfe_u32 v36, v144, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v144, v36, s6 + ; implicit-def: $vgpr144 +; %bb.2752: ; %Flow1152 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2753: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v144 + v_cmp_eq_u32_sdwa vcc, v144, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v144, vcc +; %bb.2754: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i962.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v143 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2755: + v_bfe_u32 v37, v143, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v143, v37, s6 + ; implicit-def: $vgpr143 +; %bb.2756: ; %Flow1151 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2757: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v143 + v_cmp_eq_u32_sdwa vcc, v143, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v143, vcc +; %bb.2758: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i965.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v142 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2759: + v_bfe_u32 v38, v142, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v142, v38, s6 + ; implicit-def: $vgpr142 +; %bb.2760: ; %Flow1150 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2761: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v142 + v_cmp_eq_u32_sdwa vcc, v142, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v142, vcc +; %bb.2762: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i968.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v39, 0x7f800000, v141 + v_cmp_ne_u32_e32 vcc, s4, v39 + ; implicit-def: $vgpr39 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2763: + v_bfe_u32 v39, v141, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v39, v141, v39, s6 + ; implicit-def: $vgpr141 +; %bb.2764: ; %Flow1149 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2765: + v_mov_b32_e32 v39, 0 + v_or_b32_e32 v40, 0x10000, v141 + v_cmp_eq_u32_sdwa vcc, v141, v39 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v39, v40, v141, vcc +; %bb.2766: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i971.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v40, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v40 + ; implicit-def: $vgpr40 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2767: + v_bfe_u32 v40, v2, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v40, v2, v40, s6 +; %bb.2768: ; %Flow1148 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2769: + v_mov_b32_e32 v40, 0 + v_or_b32_e32 v41, 0x10000, v2 + v_cmp_eq_u32_sdwa vcc, v2, v40 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v40, v41, v2, vcc +; %bb.2770: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i974.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr41 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2771: + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v41, v3, v2, s6 +; %bb.2772: ; %Flow1147 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2773: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v41, 0x10000, v3 + v_cmp_eq_u32_sdwa vcc, v3, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v41, v41, v3, vcc +; %bb.2774: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i977.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr42 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2775: + v_bfe_u32 v2, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v42, v4, v2, s6 +; %bb.2776: ; %Flow1146 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2777: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v42, v3, v4, vcc +; %bb.2778: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i980.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr43 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2779: + v_bfe_u32 v2, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v43, v5, v2, s6 +; %bb.2780: ; %Flow1145 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2781: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v43, v3, v5, vcc +; %bb.2782: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i983.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr44 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2783: + v_bfe_u32 v2, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v44, v6, v2, s6 +; %bb.2784: ; %Flow1144 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2785: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v44, v3, v6, vcc +; %bb.2786: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i986.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr45 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2787: + v_bfe_u32 v2, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v45, v7, v2, s6 +; %bb.2788: ; %Flow1143 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2789: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v45, v3, v7, vcc +; %bb.2790: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i989.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr46 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2791: + v_bfe_u32 v2, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v46, v8, v2, s6 +; %bb.2792: ; %Flow1142 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2793: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v46, v3, v8, vcc +; %bb.2794: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i992.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr47 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2795: + v_bfe_u32 v2, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v47, v9, v2, s6 +; %bb.2796: ; %Flow1141 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2797: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v47, v3, v9, vcc +; %bb.2798: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i995.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr48 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2799: + v_bfe_u32 v2, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v48, v10, v2, s6 +; %bb.2800: ; %Flow1140 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2801: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v48, v3, v10, vcc +; %bb.2802: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i998.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr49 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2803: + v_bfe_u32 v2, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v49, v11, v2, s6 +; %bb.2804: ; %Flow1139 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2805: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v49, v3, v11, vcc +; %bb.2806: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1001.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr50 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2807: + v_bfe_u32 v2, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v50, v12, v2, s6 +; %bb.2808: ; %Flow1138 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2809: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v50, v3, v12, vcc +; %bb.2810: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1004.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr51 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2811: + v_bfe_u32 v2, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v51, v13, v2, s6 +; %bb.2812: ; %Flow1137 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2813: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v51, v3, v13, vcc +; %bb.2814: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1007.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr52 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2815: + v_bfe_u32 v2, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v52, v14, v2, s6 +; %bb.2816: ; %Flow1136 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2817: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v52, v3, v14, vcc +; %bb.2818: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1010.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr53 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2819: + v_bfe_u32 v2, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v53, v15, v2, s6 +; %bb.2820: ; %Flow1135 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2821: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v53, v3, v15, vcc +; %bb.2822: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1013.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr54 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2823: + v_bfe_u32 v2, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v54, v16, v2, s6 +; %bb.2824: ; %Flow1134 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2825: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v54, v3, v16, vcc +; %bb.2826: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1016.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr55 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2827: + v_bfe_u32 v2, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v55, v17, v2, s6 + ; implicit-def: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 +; %bb.2828: ; %Flow1133 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2829: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v55, v3, v17, vcc +; %bb.2830: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1148 + s_or_b64 exec, exec, s[4:5] + s_bitset1_b32 s18, 7 + ds_write_b16_d16_hi v19, v23 + ds_write_b16_d16_hi v19, v25 offset:128 + ds_write_b16_d16_hi v19, v26 offset:256 + ds_write_b16_d16_hi v19, v27 offset:384 + ds_write_b16_d16_hi v19, v28 offset:1024 + ds_write_b16_d16_hi v19, v29 offset:1152 + ds_write_b16_d16_hi v19, v30 offset:1280 + ds_write_b16_d16_hi v19, v31 offset:1408 + ds_write_b16_d16_hi v19, v32 offset:2048 + ds_write_b16_d16_hi v19, v33 offset:2176 + ds_write_b16_d16_hi v19, v34 offset:2304 + ds_write_b16_d16_hi v19, v35 offset:2432 + ds_write_b16_d16_hi v19, v36 offset:3072 + ds_write_b16_d16_hi v19, v37 offset:3200 + ds_write_b16_d16_hi v19, v38 offset:3328 + ds_write_b16_d16_hi v19, v39 offset:3456 + ds_write_b16_d16_hi v19, v40 offset:8192 + ds_write_b16_d16_hi v19, v41 offset:8320 + ds_write_b16_d16_hi v19, v42 offset:8448 + ds_write_b16_d16_hi v19, v43 offset:8576 + ds_write_b16_d16_hi v19, v44 offset:9216 + ds_write_b16_d16_hi v19, v45 offset:9344 + ds_write_b16_d16_hi v19, v46 offset:9472 + ds_write_b16_d16_hi v19, v47 offset:9600 + ds_write_b16_d16_hi v19, v48 offset:10240 + ds_write_b16_d16_hi v19, v49 offset:10368 + ds_write_b16_d16_hi v19, v50 offset:10496 + ds_write_b16_d16_hi v19, v51 offset:10624 + ds_write_b16_d16_hi v19, v52 offset:11264 + ds_write_b16_d16_hi v19, v53 offset:11392 + ds_write_b16_d16_hi v19, v54 offset:11520 + ds_write_b16_d16_hi v19, v55 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[26:29], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[24:25] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[26:27], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[28:29], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v140 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2831: + v_bfe_u32 v2, v140, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v140, v2, s6 + ; implicit-def: $vgpr140 +; %bb.2832: ; %Flow1132 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2833: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v140 + v_cmp_eq_u32_sdwa vcc, v140, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v140, vcc +; %bb.2834: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1213.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v139 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2835: + v_bfe_u32 v3, v139, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v139, v3, s6 + ; implicit-def: $vgpr139 +; %bb.2836: ; %Flow1131 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2837: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v139 + v_cmp_eq_u32_sdwa vcc, v139, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v139, vcc +; %bb.2838: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1216.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v138 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2839: + v_bfe_u32 v4, v138, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v138, v4, s6 + ; implicit-def: $vgpr138 +; %bb.2840: ; %Flow1130 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2841: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v138 + v_cmp_eq_u32_sdwa vcc, v138, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v138, vcc +; %bb.2842: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1219.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v137 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2843: + v_bfe_u32 v5, v137, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v137, v5, s6 + ; implicit-def: $vgpr137 +; %bb.2844: ; %Flow1129 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2845: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v137 + v_cmp_eq_u32_sdwa vcc, v137, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v137, vcc +; %bb.2846: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1222.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v136 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2847: + v_bfe_u32 v6, v136, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v136, v6, s6 + ; implicit-def: $vgpr136 +; %bb.2848: ; %Flow1128 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2849: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v136 + v_cmp_eq_u32_sdwa vcc, v136, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v136, vcc +; %bb.2850: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1225.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v135 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2851: + v_bfe_u32 v7, v135, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v135, v7, s6 + ; implicit-def: $vgpr135 +; %bb.2852: ; %Flow1127 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2853: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v135 + v_cmp_eq_u32_sdwa vcc, v135, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v135, vcc +; %bb.2854: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1228.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v134 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2855: + v_bfe_u32 v8, v134, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v134, v8, s6 + ; implicit-def: $vgpr134 +; %bb.2856: ; %Flow1126 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2857: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v134 + v_cmp_eq_u32_sdwa vcc, v134, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v134, vcc +; %bb.2858: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1231.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v133 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2859: + v_bfe_u32 v9, v133, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v133, v9, s6 + ; implicit-def: $vgpr133 +; %bb.2860: ; %Flow1125 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2861: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v133 + v_cmp_eq_u32_sdwa vcc, v133, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v133, vcc +; %bb.2862: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1234.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v132 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2863: + v_bfe_u32 v10, v132, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v132, v10, s6 + ; implicit-def: $vgpr132 +; %bb.2864: ; %Flow1124 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2865: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v132 + v_cmp_eq_u32_sdwa vcc, v132, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v132, vcc +; %bb.2866: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1237.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v131 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2867: + v_bfe_u32 v11, v131, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v131, v11, s6 + ; implicit-def: $vgpr131 +; %bb.2868: ; %Flow1123 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2869: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v131 + v_cmp_eq_u32_sdwa vcc, v131, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v131, vcc +; %bb.2870: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1240.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v130 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2871: + v_bfe_u32 v12, v130, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v130, v12, s6 + ; implicit-def: $vgpr130 +; %bb.2872: ; %Flow1122 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2873: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v130 + v_cmp_eq_u32_sdwa vcc, v130, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v130, vcc +; %bb.2874: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1243.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v129 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2875: + v_bfe_u32 v13, v129, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v129, v13, s6 + ; implicit-def: $vgpr129 +; %bb.2876: ; %Flow1121 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2877: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v129 + v_cmp_eq_u32_sdwa vcc, v129, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v129, vcc +; %bb.2878: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1246.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v128 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2879: + v_bfe_u32 v14, v128, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v128, v14, s6 + ; implicit-def: $vgpr128 +; %bb.2880: ; %Flow1120 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2881: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v128 + v_cmp_eq_u32_sdwa vcc, v128, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v128, vcc +; %bb.2882: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1249.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v127 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2883: + v_bfe_u32 v15, v127, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v127, v15, s6 + ; implicit-def: $vgpr127 +; %bb.2884: ; %Flow1119 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2885: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v127 + v_cmp_eq_u32_sdwa vcc, v127, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v127, vcc +; %bb.2886: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1252.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v126 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2887: + v_bfe_u32 v16, v126, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v126, v16, s6 + ; implicit-def: $vgpr126 +; %bb.2888: ; %Flow1118 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2889: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v126 + v_cmp_eq_u32_sdwa vcc, v126, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v126, vcc +; %bb.2890: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1255.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v124 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2891: + v_bfe_u32 v17, v124, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v124, v17, s6 + ; implicit-def: $vgpr124 +; %bb.2892: ; %Flow1117 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2893: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v23, 0x10000, v124 + v_cmp_eq_u32_sdwa vcc, v124, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v23, v124, vcc +; %bb.2894: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1258.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v125 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2895: + v_bfe_u32 v23, v125, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v125, v23, s6 + ; implicit-def: $vgpr125 +; %bb.2896: ; %Flow1116 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2897: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v125 + v_cmp_eq_u32_sdwa vcc, v125, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v125, vcc +; %bb.2898: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1261.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v123 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2899: + v_bfe_u32 v24, v123, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v123, v24, s6 + ; implicit-def: $vgpr123 +; %bb.2900: ; %Flow1115 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2901: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v123 + v_cmp_eq_u32_sdwa vcc, v123, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v123, vcc +; %bb.2902: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1264.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v122 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2903: + v_bfe_u32 v25, v122, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v122, v25, s6 + ; implicit-def: $vgpr122 +; %bb.2904: ; %Flow1114 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2905: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v122 + v_cmp_eq_u32_sdwa vcc, v122, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v122, vcc +; %bb.2906: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1267.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v121 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2907: + v_bfe_u32 v26, v121, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v121, v26, s6 + ; implicit-def: $vgpr121 +; %bb.2908: ; %Flow1113 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2909: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v121 + v_cmp_eq_u32_sdwa vcc, v121, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v121, vcc +; %bb.2910: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1270.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v27, 0x7f800000, v120 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2911: + v_bfe_u32 v27, v120, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v120, v27, s6 + ; implicit-def: $vgpr120 +; %bb.2912: ; %Flow1112 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2913: + v_mov_b32_e32 v27, 0 + v_or_b32_e32 v28, 0x10000, v120 + v_cmp_eq_u32_sdwa vcc, v120, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v120, vcc +; %bb.2914: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1273.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v28, 0x7f800000, v119 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2915: + v_bfe_u32 v28, v119, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v119, v28, s6 + ; implicit-def: $vgpr119 +; %bb.2916: ; %Flow1111 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2917: + v_mov_b32_e32 v28, 0 + v_or_b32_e32 v29, 0x10000, v119 + v_cmp_eq_u32_sdwa vcc, v119, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v119, vcc +; %bb.2918: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1276.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v29, 0x7f800000, v118 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2919: + v_bfe_u32 v29, v118, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v118, v29, s6 + ; implicit-def: $vgpr118 +; %bb.2920: ; %Flow1110 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2921: + v_mov_b32_e32 v29, 0 + v_or_b32_e32 v30, 0x10000, v118 + v_cmp_eq_u32_sdwa vcc, v118, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v118, vcc +; %bb.2922: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1279.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v30, 0x7f800000, v117 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2923: + v_bfe_u32 v30, v117, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v117, v30, s6 + ; implicit-def: $vgpr117 +; %bb.2924: ; %Flow1109 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2925: + v_mov_b32_e32 v30, 0 + v_or_b32_e32 v31, 0x10000, v117 + v_cmp_eq_u32_sdwa vcc, v117, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v117, vcc +; %bb.2926: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1282.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v31, 0x7f800000, v116 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2927: + v_bfe_u32 v31, v116, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v116, v31, s6 + ; implicit-def: $vgpr116 +; %bb.2928: ; %Flow1108 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2929: + v_mov_b32_e32 v31, 0 + v_or_b32_e32 v32, 0x10000, v116 + v_cmp_eq_u32_sdwa vcc, v116, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v116, vcc +; %bb.2930: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1285.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v32, 0x7f800000, v115 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2931: + v_bfe_u32 v32, v115, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v115, v32, s6 + ; implicit-def: $vgpr115 +; %bb.2932: ; %Flow1107 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2933: + v_mov_b32_e32 v32, 0 + v_or_b32_e32 v33, 0x10000, v115 + v_cmp_eq_u32_sdwa vcc, v115, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v115, vcc +; %bb.2934: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1288.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v33, 0x7f800000, v114 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2935: + v_bfe_u32 v33, v114, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v114, v33, s6 + ; implicit-def: $vgpr114 +; %bb.2936: ; %Flow1106 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2937: + v_mov_b32_e32 v33, 0 + v_or_b32_e32 v34, 0x10000, v114 + v_cmp_eq_u32_sdwa vcc, v114, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v114, vcc +; %bb.2938: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1291.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v34, 0x7f800000, v113 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2939: + v_bfe_u32 v34, v113, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v113, v34, s6 + ; implicit-def: $vgpr113 +; %bb.2940: ; %Flow1105 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2941: + v_mov_b32_e32 v34, 0 + v_or_b32_e32 v35, 0x10000, v113 + v_cmp_eq_u32_sdwa vcc, v113, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v113, vcc +; %bb.2942: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1294.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v35, 0x7f800000, v112 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2943: + v_bfe_u32 v35, v112, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v112, v35, s6 + ; implicit-def: $vgpr112 +; %bb.2944: ; %Flow1104 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2945: + v_mov_b32_e32 v35, 0 + v_or_b32_e32 v36, 0x10000, v112 + v_cmp_eq_u32_sdwa vcc, v112, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v112, vcc +; %bb.2946: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1297.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v111 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2947: + v_bfe_u32 v36, v111, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v111, v36, s6 + ; implicit-def: $vgpr111 +; %bb.2948: ; %Flow1103 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2949: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v111 + v_cmp_eq_u32_sdwa vcc, v111, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v111, vcc +; %bb.2950: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1300.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v37, 0x7f800000, v110 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2951: + v_bfe_u32 v37, v110, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v110, v37, s6 + ; implicit-def: $vgpr110 +; %bb.2952: ; %Flow1102 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2953: + v_mov_b32_e32 v37, 0 + v_or_b32_e32 v38, 0x10000, v110 + v_cmp_eq_u32_sdwa vcc, v110, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v110, vcc +; %bb.2954: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1303.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v38, 0x7f800000, v109 + v_cmp_ne_u32_e32 vcc, s4, v38 + ; implicit-def: $vgpr38 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2955: + v_bfe_u32 v38, v109, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v38, v109, v38, s6 + ; implicit-def: $vgpr109 +; %bb.2956: ; %Flow1101 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2957: + v_mov_b32_e32 v38, 0 + v_or_b32_e32 v39, 0x10000, v109 + v_cmp_eq_u32_sdwa vcc, v109, v38 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v38, v39, v109, vcc +; %bb.2958: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1435 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v23 offset:8192 + ds_write_b16_d16_hi v19, v24 offset:8320 + ds_write_b16_d16_hi v19, v25 offset:8448 + ds_write_b16_d16_hi v19, v26 offset:8576 + ds_write_b16_d16_hi v19, v27 offset:9216 + ds_write_b16_d16_hi v19, v28 offset:9344 + ds_write_b16_d16_hi v19, v29 offset:9472 + ds_write_b16_d16_hi v19, v30 offset:9600 + ds_write_b16_d16_hi v19, v31 offset:10240 + ds_write_b16_d16_hi v19, v32 offset:10368 + ds_write_b16_d16_hi v19, v33 offset:10496 + ds_write_b16_d16_hi v19, v34 offset:10624 + ds_write_b16_d16_hi v19, v35 offset:11264 + ds_write_b16_d16_hi v19, v36 offset:11392 + ds_write_b16_d16_hi v19, v37 offset:11520 + ds_write_b16_d16_hi v19, v38 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[24:27], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[22:23] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[24:25], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[26:27], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v108 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2959: + v_bfe_u32 v2, v108, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v108, v2, s6 + ; implicit-def: $vgpr108 +; %bb.2960: ; %Flow1100 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2961: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v108 + v_cmp_eq_u32_sdwa vcc, v108, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v108, vcc +; %bb.2962: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1500.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v3, 0x7f800000, v107 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2963: + v_bfe_u32 v3, v107, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v107, v3, s6 + ; implicit-def: $vgpr107 +; %bb.2964: ; %Flow1099 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2965: + v_mov_b32_e32 v3, 0 + v_or_b32_e32 v4, 0x10000, v107 + v_cmp_eq_u32_sdwa vcc, v107, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v107, vcc +; %bb.2966: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1503.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v4, 0x7f800000, v106 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2967: + v_bfe_u32 v4, v106, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v106, v4, s6 + ; implicit-def: $vgpr106 +; %bb.2968: ; %Flow1098 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2969: + v_mov_b32_e32 v4, 0 + v_or_b32_e32 v5, 0x10000, v106 + v_cmp_eq_u32_sdwa vcc, v106, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v106, vcc +; %bb.2970: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1506.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v5, 0x7f800000, v105 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2971: + v_bfe_u32 v5, v105, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v105, v5, s6 + ; implicit-def: $vgpr105 +; %bb.2972: ; %Flow1097 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2973: + v_mov_b32_e32 v5, 0 + v_or_b32_e32 v6, 0x10000, v105 + v_cmp_eq_u32_sdwa vcc, v105, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v105, vcc +; %bb.2974: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1509.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v6, 0x7f800000, v104 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2975: + v_bfe_u32 v6, v104, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v104, v6, s6 + ; implicit-def: $vgpr104 +; %bb.2976: ; %Flow1096 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2977: + v_mov_b32_e32 v6, 0 + v_or_b32_e32 v7, 0x10000, v104 + v_cmp_eq_u32_sdwa vcc, v104, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v104, vcc +; %bb.2978: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1512.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v7, 0x7f800000, v103 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2979: + v_bfe_u32 v7, v103, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v103, v7, s6 + ; implicit-def: $vgpr103 +; %bb.2980: ; %Flow1095 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2981: + v_mov_b32_e32 v7, 0 + v_or_b32_e32 v8, 0x10000, v103 + v_cmp_eq_u32_sdwa vcc, v103, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v103, vcc +; %bb.2982: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1515.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v8, 0x7f800000, v102 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2983: + v_bfe_u32 v8, v102, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v102, v8, s6 + ; implicit-def: $vgpr102 +; %bb.2984: ; %Flow1094 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2985: + v_mov_b32_e32 v8, 0 + v_or_b32_e32 v9, 0x10000, v102 + v_cmp_eq_u32_sdwa vcc, v102, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v102, vcc +; %bb.2986: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1518.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v9, 0x7f800000, v101 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2987: + v_bfe_u32 v9, v101, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v101, v9, s6 + ; implicit-def: $vgpr101 +; %bb.2988: ; %Flow1093 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2989: + v_mov_b32_e32 v9, 0 + v_or_b32_e32 v10, 0x10000, v101 + v_cmp_eq_u32_sdwa vcc, v101, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v101, vcc +; %bb.2990: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1521.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v10, 0x7f800000, v100 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2991: + v_bfe_u32 v10, v100, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v100, v10, s6 + ; implicit-def: $vgpr100 +; %bb.2992: ; %Flow1092 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2993: + v_mov_b32_e32 v10, 0 + v_or_b32_e32 v11, 0x10000, v100 + v_cmp_eq_u32_sdwa vcc, v100, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v100, vcc +; %bb.2994: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1524.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v11, 0x7f800000, v99 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2995: + v_bfe_u32 v11, v99, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v99, v11, s6 + ; implicit-def: $vgpr99 +; %bb.2996: ; %Flow1091 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.2997: + v_mov_b32_e32 v11, 0 + v_or_b32_e32 v12, 0x10000, v99 + v_cmp_eq_u32_sdwa vcc, v99, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v99, vcc +; %bb.2998: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1527.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v12, 0x7f800000, v98 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.2999: + v_bfe_u32 v12, v98, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v98, v12, s6 + ; implicit-def: $vgpr98 +; %bb.3000: ; %Flow1090 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3001: + v_mov_b32_e32 v12, 0 + v_or_b32_e32 v13, 0x10000, v98 + v_cmp_eq_u32_sdwa vcc, v98, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v98, vcc +; %bb.3002: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1530.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v13, 0x7f800000, v97 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3003: + v_bfe_u32 v13, v97, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v97, v13, s6 + ; implicit-def: $vgpr97 +; %bb.3004: ; %Flow1089 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3005: + v_mov_b32_e32 v13, 0 + v_or_b32_e32 v14, 0x10000, v97 + v_cmp_eq_u32_sdwa vcc, v97, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v97, vcc +; %bb.3006: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1533.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v14, 0x7f800000, v96 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3007: + v_bfe_u32 v14, v96, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v96, v14, s6 + ; implicit-def: $vgpr96 +; %bb.3008: ; %Flow1088 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3009: + v_mov_b32_e32 v14, 0 + v_or_b32_e32 v15, 0x10000, v96 + v_cmp_eq_u32_sdwa vcc, v96, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v96, vcc +; %bb.3010: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1536.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v15, 0x7f800000, v95 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3011: + v_bfe_u32 v15, v95, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v95, v15, s6 + ; implicit-def: $vgpr95 +; %bb.3012: ; %Flow1087 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3013: + v_mov_b32_e32 v15, 0 + v_or_b32_e32 v16, 0x10000, v95 + v_cmp_eq_u32_sdwa vcc, v95, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v95, vcc +; %bb.3014: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1539.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v16, 0x7f800000, v94 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3015: + v_bfe_u32 v16, v94, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v94, v16, s6 + ; implicit-def: $vgpr94 +; %bb.3016: ; %Flow1086 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3017: + v_mov_b32_e32 v16, 0 + v_or_b32_e32 v17, 0x10000, v94 + v_cmp_eq_u32_sdwa vcc, v94, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v94, vcc +; %bb.3018: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1542.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v17, 0x7f800000, v92 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3019: + v_bfe_u32 v17, v92, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v92, v17, s6 + ; implicit-def: $vgpr92 +; %bb.3020: ; %Flow1085 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3021: + v_mov_b32_e32 v17, 0 + v_or_b32_e32 v22, 0x10000, v92 + v_cmp_eq_u32_sdwa vcc, v92, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v22, v92, vcc +; %bb.3022: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1545.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v22, 0x7f800000, v93 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3023: + v_bfe_u32 v22, v93, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v93, v22, s6 + ; implicit-def: $vgpr93 +; %bb.3024: ; %Flow1084 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3025: + v_mov_b32_e32 v22, 0 + v_or_b32_e32 v23, 0x10000, v93 + v_cmp_eq_u32_sdwa vcc, v93, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v93, vcc +; %bb.3026: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1548.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v23, 0x7f800000, v91 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3027: + v_bfe_u32 v23, v91, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v91, v23, s6 + ; implicit-def: $vgpr91 +; %bb.3028: ; %Flow1083 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3029: + v_mov_b32_e32 v23, 0 + v_or_b32_e32 v24, 0x10000, v91 + v_cmp_eq_u32_sdwa vcc, v91, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v91, vcc +; %bb.3030: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1551.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v24, 0x7f800000, v90 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3031: + v_bfe_u32 v24, v90, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v90, v24, s6 + ; implicit-def: $vgpr90 +; %bb.3032: ; %Flow1082 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3033: + v_mov_b32_e32 v24, 0 + v_or_b32_e32 v25, 0x10000, v90 + v_cmp_eq_u32_sdwa vcc, v90, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v90, vcc +; %bb.3034: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1554.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v25, 0x7f800000, v89 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3035: + v_bfe_u32 v25, v89, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v89, v25, s6 + ; implicit-def: $vgpr89 +; %bb.3036: ; %Flow1081 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3037: + v_mov_b32_e32 v25, 0 + v_or_b32_e32 v26, 0x10000, v89 + v_cmp_eq_u32_sdwa vcc, v89, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v89, vcc +; %bb.3038: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1557.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v26, 0x7f800000, v88 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3039: + v_bfe_u32 v26, v88, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v88, v26, s6 + ; implicit-def: $vgpr88 +; %bb.3040: ; %Flow1080 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3041: + v_mov_b32_e32 v26, 0 + v_or_b32_e32 v27, 0x10000, v88 + v_cmp_eq_u32_sdwa vcc, v88, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v88, vcc +; %bb.3042: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1560.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a41 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3043: + v_accvgpr_read_b32 v28, a41 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr41 +; %bb.3044: ; %Flow1079 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3045: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a41 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3046: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1563.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a40 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3047: + v_accvgpr_read_b32 v29, a40 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr40 +; %bb.3048: ; %Flow1078 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3049: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a40 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3050: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1566.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a23 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3051: + v_accvgpr_read_b32 v30, a23 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr23 +; %bb.3052: ; %Flow1077 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3053: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a23 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3054: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1569.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a22 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3055: + v_accvgpr_read_b32 v31, a22 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr22 +; %bb.3056: ; %Flow1076 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3057: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a22 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3058: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1572.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a21 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3059: + v_accvgpr_read_b32 v32, a21 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr21 +; %bb.3060: ; %Flow1075 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3061: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a21 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3062: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1575.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a20 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3063: + v_accvgpr_read_b32 v33, a20 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr20 +; %bb.3064: ; %Flow1074 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3065: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a20 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3066: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1578.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a19 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3067: + v_accvgpr_read_b32 v34, a19 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr19 +; %bb.3068: ; %Flow1073 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3069: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a19 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3070: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1581.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a18 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3071: + v_accvgpr_read_b32 v35, a18 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr18 +; %bb.3072: ; %Flow1072 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3073: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a18 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3074: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1584.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a17 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3075: + v_accvgpr_read_b32 v36, a17 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr17 +; %bb.3076: ; %Flow1071 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3077: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a17 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3078: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1587.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v87 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3079: + v_bfe_u32 v36, v87, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v87, v36, s6 + ; implicit-def: $vgpr87 +; %bb.3080: ; %Flow1070 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3081: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v87 + v_cmp_eq_u32_sdwa vcc, v87, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v87, vcc +; %bb.3082: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1590.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v37, a16 + v_and_b32_e32 v37, 0x7f800000, v37 + v_cmp_ne_u32_e32 vcc, s4, v37 + ; implicit-def: $vgpr37 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3083: + v_accvgpr_read_b32 v38, a16 + v_bfe_u32 v37, v38, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v37, v38, v37, s6 + ; implicit-def: $agpr16 +; %bb.3084: ; %Flow1069 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3085: + v_mov_b32_e32 v37, 0 + v_accvgpr_read_b32 v39, a16 + v_or_b32_e32 v38, 0x10000, v39 + v_cmp_eq_u32_sdwa vcc, v39, v37 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v37, v38, v39, vcc +; %bb.3086: ; %_ZZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR1722 + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v22 offset:8192 + ds_write_b16_d16_hi v19, v23 offset:8320 + ds_write_b16_d16_hi v19, v24 offset:8448 + ds_write_b16_d16_hi v19, v25 offset:8576 + ds_write_b16_d16_hi v19, v26 offset:9216 + ds_write_b16_d16_hi v19, v27 offset:9344 + ds_write_b16_d16_hi v19, v28 offset:9472 + ds_write_b16_d16_hi v19, v29 offset:9600 + ds_write_b16_d16_hi v19, v30 offset:10240 + ds_write_b16_d16_hi v19, v31 offset:10368 + ds_write_b16_d16_hi v19, v32 offset:10496 + ds_write_b16_d16_hi v19, v33 offset:10624 + ds_write_b16_d16_hi v19, v34 offset:11264 + ds_write_b16_d16_hi v19, v35 offset:11392 + ds_write_b16_d16_hi v19, v36 offset:11520 + ds_write_b16_d16_hi v19, v37 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v2, s4, v1 + v_lshl_or_b32 v3, v2, 7, v21 + ds_read_b128 v[4:7], v3 + ds_read_b128 v[8:11], v3 offset:128 + ds_read_b128 v[12:15], v3 offset:256 + ds_read_b128 v[22:25], v3 offset:384 + v_add_u32_e32 v2, s18, v2 + v_mad_u64_u32 v[2:3], s[4:5], v2, s16, v[20:21] + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[4:5], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[6:7], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[8:9], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[10:11], v3, s[0:3], 8 offen + v_add_u32_e32 v2, s16, v2 + v_lshlrev_b32_e32 v3, 1, v2 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[12:13], v3, s[0:3], 0 offen + buffer_store_dwordx2 v[14:15], v3, s[0:3], 8 offen + v_add_lshl_u32 v2, v2, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[22:23], v2, s[0:3], 0 offen + buffer_store_dwordx2 v[24:25], v2, s[0:3], 8 offen + s_waitcnt lgkmcnt(0) + s_barrier + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v2, a111 + v_and_b32_e32 v2, 0x7f800000, v2 + v_cmp_ne_u32_e32 vcc, s4, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3087: + v_accvgpr_read_b32 v3, a111 + v_bfe_u32 v2, v3, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v2, v3, v2, s6 + ; implicit-def: $agpr111 +; %bb.3088: ; %Flow1068 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3089: + v_mov_b32_e32 v2, 0 + v_accvgpr_read_b32 v4, a111 + v_or_b32_e32 v3, 0x10000, v4 + v_cmp_eq_u32_sdwa vcc, v4, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v4, vcc +; %bb.3090: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit.i.i.i.i.i1787.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v3, a110 + v_and_b32_e32 v3, 0x7f800000, v3 + v_cmp_ne_u32_e32 vcc, s4, v3 + ; implicit-def: $vgpr3 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3091: + v_accvgpr_read_b32 v4, a110 + v_bfe_u32 v3, v4, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v3, v4, v3, s6 + ; implicit-def: $agpr110 +; %bb.3092: ; %Flow1067 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3093: + v_mov_b32_e32 v3, 0 + v_accvgpr_read_b32 v5, a110 + v_or_b32_e32 v4, 0x10000, v5 + v_cmp_eq_u32_sdwa vcc, v5, v3 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v3, v4, v5, vcc +; %bb.3094: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit98.i.i.i.i.i1790.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v4, a109 + v_and_b32_e32 v4, 0x7f800000, v4 + v_cmp_ne_u32_e32 vcc, s4, v4 + ; implicit-def: $vgpr4 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3095: + v_accvgpr_read_b32 v5, a109 + v_bfe_u32 v4, v5, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v4, v5, v4, s6 + ; implicit-def: $agpr109 +; %bb.3096: ; %Flow1066 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3097: + v_mov_b32_e32 v4, 0 + v_accvgpr_read_b32 v6, a109 + v_or_b32_e32 v5, 0x10000, v6 + v_cmp_eq_u32_sdwa vcc, v6, v4 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v4, v5, v6, vcc +; %bb.3098: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit103.i.i.i.i.i1793.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v5, a108 + v_and_b32_e32 v5, 0x7f800000, v5 + v_cmp_ne_u32_e32 vcc, s4, v5 + ; implicit-def: $vgpr5 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3099: + v_accvgpr_read_b32 v6, a108 + v_bfe_u32 v5, v6, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v5, v6, v5, s6 + ; implicit-def: $agpr108 +; %bb.3100: ; %Flow1065 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3101: + v_mov_b32_e32 v5, 0 + v_accvgpr_read_b32 v7, a108 + v_or_b32_e32 v6, 0x10000, v7 + v_cmp_eq_u32_sdwa vcc, v7, v5 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v5, v6, v7, vcc +; %bb.3102: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit108.i.i.i.i.i1796.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v6, a107 + v_and_b32_e32 v6, 0x7f800000, v6 + v_cmp_ne_u32_e32 vcc, s4, v6 + ; implicit-def: $vgpr6 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3103: + v_accvgpr_read_b32 v7, a107 + v_bfe_u32 v6, v7, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v6, v7, v6, s6 + ; implicit-def: $agpr107 +; %bb.3104: ; %Flow1064 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3105: + v_mov_b32_e32 v6, 0 + v_accvgpr_read_b32 v8, a107 + v_or_b32_e32 v7, 0x10000, v8 + v_cmp_eq_u32_sdwa vcc, v8, v6 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v6, v7, v8, vcc +; %bb.3106: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit113.i.i.i.i.i1799.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v7, a106 + v_and_b32_e32 v7, 0x7f800000, v7 + v_cmp_ne_u32_e32 vcc, s4, v7 + ; implicit-def: $vgpr7 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3107: + v_accvgpr_read_b32 v8, a106 + v_bfe_u32 v7, v8, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v7, v8, v7, s6 + ; implicit-def: $agpr106 +; %bb.3108: ; %Flow1063 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3109: + v_mov_b32_e32 v7, 0 + v_accvgpr_read_b32 v9, a106 + v_or_b32_e32 v8, 0x10000, v9 + v_cmp_eq_u32_sdwa vcc, v9, v7 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v7, v8, v9, vcc +; %bb.3110: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit118.i.i.i.i.i1802.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v8, a105 + v_and_b32_e32 v8, 0x7f800000, v8 + v_cmp_ne_u32_e32 vcc, s4, v8 + ; implicit-def: $vgpr8 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3111: + v_accvgpr_read_b32 v9, a105 + v_bfe_u32 v8, v9, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v8, v9, v8, s6 + ; implicit-def: $agpr105 +; %bb.3112: ; %Flow1062 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3113: + v_mov_b32_e32 v8, 0 + v_accvgpr_read_b32 v10, a105 + v_or_b32_e32 v9, 0x10000, v10 + v_cmp_eq_u32_sdwa vcc, v10, v8 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v8, v9, v10, vcc +; %bb.3114: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit123.i.i.i.i.i1805.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v9, a104 + v_and_b32_e32 v9, 0x7f800000, v9 + v_cmp_ne_u32_e32 vcc, s4, v9 + ; implicit-def: $vgpr9 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3115: + v_accvgpr_read_b32 v10, a104 + v_bfe_u32 v9, v10, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v9, v10, v9, s6 + ; implicit-def: $agpr104 +; %bb.3116: ; %Flow1061 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3117: + v_mov_b32_e32 v9, 0 + v_accvgpr_read_b32 v11, a104 + v_or_b32_e32 v10, 0x10000, v11 + v_cmp_eq_u32_sdwa vcc, v11, v9 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v9, v10, v11, vcc +; %bb.3118: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit128.i.i.i.i.i1808.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v10, a103 + v_and_b32_e32 v10, 0x7f800000, v10 + v_cmp_ne_u32_e32 vcc, s4, v10 + ; implicit-def: $vgpr10 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3119: + v_accvgpr_read_b32 v11, a103 + v_bfe_u32 v10, v11, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v10, v11, v10, s6 + ; implicit-def: $agpr103 +; %bb.3120: ; %Flow1060 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3121: + v_mov_b32_e32 v10, 0 + v_accvgpr_read_b32 v12, a103 + v_or_b32_e32 v11, 0x10000, v12 + v_cmp_eq_u32_sdwa vcc, v12, v10 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v10, v11, v12, vcc +; %bb.3122: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit133.i.i.i.i.i1811.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v11, a102 + v_and_b32_e32 v11, 0x7f800000, v11 + v_cmp_ne_u32_e32 vcc, s4, v11 + ; implicit-def: $vgpr11 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3123: + v_accvgpr_read_b32 v12, a102 + v_bfe_u32 v11, v12, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v11, v12, v11, s6 + ; implicit-def: $agpr102 +; %bb.3124: ; %Flow1059 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3125: + v_mov_b32_e32 v11, 0 + v_accvgpr_read_b32 v13, a102 + v_or_b32_e32 v12, 0x10000, v13 + v_cmp_eq_u32_sdwa vcc, v13, v11 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v11, v12, v13, vcc +; %bb.3126: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit138.i.i.i.i.i1814.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v12, a101 + v_and_b32_e32 v12, 0x7f800000, v12 + v_cmp_ne_u32_e32 vcc, s4, v12 + ; implicit-def: $vgpr12 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3127: + v_accvgpr_read_b32 v13, a101 + v_bfe_u32 v12, v13, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v12, v13, v12, s6 + ; implicit-def: $agpr101 +; %bb.3128: ; %Flow1058 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3129: + v_mov_b32_e32 v12, 0 + v_accvgpr_read_b32 v14, a101 + v_or_b32_e32 v13, 0x10000, v14 + v_cmp_eq_u32_sdwa vcc, v14, v12 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v12, v13, v14, vcc +; %bb.3130: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit143.i.i.i.i.i1817.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v13, a100 + v_and_b32_e32 v13, 0x7f800000, v13 + v_cmp_ne_u32_e32 vcc, s4, v13 + ; implicit-def: $vgpr13 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3131: + v_accvgpr_read_b32 v14, a100 + v_bfe_u32 v13, v14, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v13, v14, v13, s6 + ; implicit-def: $agpr100 +; %bb.3132: ; %Flow1057 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3133: + v_mov_b32_e32 v13, 0 + v_accvgpr_read_b32 v15, a100 + v_or_b32_e32 v14, 0x10000, v15 + v_cmp_eq_u32_sdwa vcc, v15, v13 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v13, v14, v15, vcc +; %bb.3134: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit148.i.i.i.i.i1820.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v14, a99 + v_and_b32_e32 v14, 0x7f800000, v14 + v_cmp_ne_u32_e32 vcc, s4, v14 + ; implicit-def: $vgpr14 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3135: + v_accvgpr_read_b32 v15, a99 + v_bfe_u32 v14, v15, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v14, v15, v14, s6 + ; implicit-def: $agpr99 +; %bb.3136: ; %Flow1056 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3137: + v_mov_b32_e32 v14, 0 + v_accvgpr_read_b32 v16, a99 + v_or_b32_e32 v15, 0x10000, v16 + v_cmp_eq_u32_sdwa vcc, v16, v14 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v14, v15, v16, vcc +; %bb.3138: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit153.i.i.i.i.i1823.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v15, a98 + v_and_b32_e32 v15, 0x7f800000, v15 + v_cmp_ne_u32_e32 vcc, s4, v15 + ; implicit-def: $vgpr15 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3139: + v_accvgpr_read_b32 v16, a98 + v_bfe_u32 v15, v16, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v15, v16, v15, s6 + ; implicit-def: $agpr98 +; %bb.3140: ; %Flow1055 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3141: + v_mov_b32_e32 v15, 0 + v_accvgpr_read_b32 v17, a98 + v_or_b32_e32 v16, 0x10000, v17 + v_cmp_eq_u32_sdwa vcc, v17, v15 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v15, v16, v17, vcc +; %bb.3142: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit158.i.i.i.i.i1826.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v16, a97 + v_and_b32_e32 v16, 0x7f800000, v16 + v_cmp_ne_u32_e32 vcc, s4, v16 + ; implicit-def: $vgpr16 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3143: + v_accvgpr_read_b32 v17, a97 + v_bfe_u32 v16, v17, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v16, v17, v16, s6 + ; implicit-def: $agpr97 +; %bb.3144: ; %Flow1054 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3145: + v_mov_b32_e32 v16, 0 + v_accvgpr_read_b32 v20, a97 + v_or_b32_e32 v17, 0x10000, v20 + v_cmp_eq_u32_sdwa vcc, v20, v16 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v16, v17, v20, vcc +; %bb.3146: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit163.i.i.i.i.i1829.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v17, a96 + v_and_b32_e32 v17, 0x7f800000, v17 + v_cmp_ne_u32_e32 vcc, s4, v17 + ; implicit-def: $vgpr17 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3147: + v_accvgpr_read_b32 v20, a96 + v_bfe_u32 v17, v20, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v17, v20, v17, s6 + ; implicit-def: $agpr96 +; %bb.3148: ; %Flow1053 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3149: + v_mov_b32_e32 v17, 0 + v_accvgpr_read_b32 v22, a96 + v_or_b32_e32 v20, 0x10000, v22 + v_cmp_eq_u32_sdwa vcc, v22, v17 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v17, v20, v22, vcc +; %bb.3150: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit168.i.i.i.i.i1832.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v20, a54 + v_and_b32_e32 v20, 0x7f800000, v20 + v_cmp_ne_u32_e32 vcc, s4, v20 + ; implicit-def: $vgpr20 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3151: + v_accvgpr_read_b32 v22, a54 + v_bfe_u32 v20, v22, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v20, v22, v20, s6 + ; implicit-def: $agpr54 +; %bb.3152: ; %Flow1052 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3153: + v_mov_b32_e32 v20, 0 + v_accvgpr_read_b32 v23, a54 + v_or_b32_e32 v22, 0x10000, v23 + v_cmp_eq_u32_sdwa vcc, v23, v20 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v20, v22, v23, vcc +; %bb.3154: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit173.i.i.i.i.i1835.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v22, a53 + v_and_b32_e32 v22, 0x7f800000, v22 + v_cmp_ne_u32_e32 vcc, s4, v22 + ; implicit-def: $vgpr22 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3155: + v_accvgpr_read_b32 v23, a53 + v_bfe_u32 v22, v23, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v22, v23, v22, s6 + ; implicit-def: $agpr53 +; %bb.3156: ; %Flow1051 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3157: + v_mov_b32_e32 v22, 0 + v_accvgpr_read_b32 v24, a53 + v_or_b32_e32 v23, 0x10000, v24 + v_cmp_eq_u32_sdwa vcc, v24, v22 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v22, v23, v24, vcc +; %bb.3158: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit178.i.i.i.i.i1838.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v23, a52 + v_and_b32_e32 v23, 0x7f800000, v23 + v_cmp_ne_u32_e32 vcc, s4, v23 + ; implicit-def: $vgpr23 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3159: + v_accvgpr_read_b32 v24, a52 + v_bfe_u32 v23, v24, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v23, v24, v23, s6 + ; implicit-def: $agpr52 +; %bb.3160: ; %Flow1050 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3161: + v_mov_b32_e32 v23, 0 + v_accvgpr_read_b32 v25, a52 + v_or_b32_e32 v24, 0x10000, v25 + v_cmp_eq_u32_sdwa vcc, v25, v23 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v23, v24, v25, vcc +; %bb.3162: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit183.i.i.i.i.i1841.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v24, a51 + v_and_b32_e32 v24, 0x7f800000, v24 + v_cmp_ne_u32_e32 vcc, s4, v24 + ; implicit-def: $vgpr24 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3163: + v_accvgpr_read_b32 v25, a51 + v_bfe_u32 v24, v25, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v24, v25, v24, s6 + ; implicit-def: $agpr51 +; %bb.3164: ; %Flow1049 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3165: + v_mov_b32_e32 v24, 0 + v_accvgpr_read_b32 v26, a51 + v_or_b32_e32 v25, 0x10000, v26 + v_cmp_eq_u32_sdwa vcc, v26, v24 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v24, v25, v26, vcc +; %bb.3166: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit188.i.i.i.i.i1844.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v25, a50 + v_and_b32_e32 v25, 0x7f800000, v25 + v_cmp_ne_u32_e32 vcc, s4, v25 + ; implicit-def: $vgpr25 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3167: + v_accvgpr_read_b32 v26, a50 + v_bfe_u32 v25, v26, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v25, v26, v25, s6 + ; implicit-def: $agpr50 +; %bb.3168: ; %Flow1048 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3169: + v_mov_b32_e32 v25, 0 + v_accvgpr_read_b32 v27, a50 + v_or_b32_e32 v26, 0x10000, v27 + v_cmp_eq_u32_sdwa vcc, v27, v25 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v25, v26, v27, vcc +; %bb.3170: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit193.i.i.i.i.i1847.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v26, a49 + v_and_b32_e32 v26, 0x7f800000, v26 + v_cmp_ne_u32_e32 vcc, s4, v26 + ; implicit-def: $vgpr26 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3171: + v_accvgpr_read_b32 v27, a49 + v_bfe_u32 v26, v27, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v26, v27, v26, s6 + ; implicit-def: $agpr49 +; %bb.3172: ; %Flow1047 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3173: + v_mov_b32_e32 v26, 0 + v_accvgpr_read_b32 v28, a49 + v_or_b32_e32 v27, 0x10000, v28 + v_cmp_eq_u32_sdwa vcc, v28, v26 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v26, v27, v28, vcc +; %bb.3174: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit198.i.i.i.i.i1850.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v27, a48 + v_and_b32_e32 v27, 0x7f800000, v27 + v_cmp_ne_u32_e32 vcc, s4, v27 + ; implicit-def: $vgpr27 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3175: + v_accvgpr_read_b32 v28, a48 + v_bfe_u32 v27, v28, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v27, v28, v27, s6 + ; implicit-def: $agpr48 +; %bb.3176: ; %Flow1046 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3177: + v_mov_b32_e32 v27, 0 + v_accvgpr_read_b32 v29, a48 + v_or_b32_e32 v28, 0x10000, v29 + v_cmp_eq_u32_sdwa vcc, v29, v27 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v27, v28, v29, vcc +; %bb.3178: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit203.i.i.i.i.i1853.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v28, a39 + v_and_b32_e32 v28, 0x7f800000, v28 + v_cmp_ne_u32_e32 vcc, s4, v28 + ; implicit-def: $vgpr28 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3179: + v_accvgpr_read_b32 v29, a39 + v_bfe_u32 v28, v29, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v28, v29, v28, s6 + ; implicit-def: $agpr39 +; %bb.3180: ; %Flow1045 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3181: + v_mov_b32_e32 v28, 0 + v_accvgpr_read_b32 v30, a39 + v_or_b32_e32 v29, 0x10000, v30 + v_cmp_eq_u32_sdwa vcc, v30, v28 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v28, v29, v30, vcc +; %bb.3182: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit208.i.i.i.i.i1856.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v29, a38 + v_and_b32_e32 v29, 0x7f800000, v29 + v_cmp_ne_u32_e32 vcc, s4, v29 + ; implicit-def: $vgpr29 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3183: + v_accvgpr_read_b32 v30, a38 + v_bfe_u32 v29, v30, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v29, v30, v29, s6 + ; implicit-def: $agpr38 +; %bb.3184: ; %Flow1044 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3185: + v_mov_b32_e32 v29, 0 + v_accvgpr_read_b32 v31, a38 + v_or_b32_e32 v30, 0x10000, v31 + v_cmp_eq_u32_sdwa vcc, v31, v29 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v29, v30, v31, vcc +; %bb.3186: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit213.i.i.i.i.i1859.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v30, a37 + v_and_b32_e32 v30, 0x7f800000, v30 + v_cmp_ne_u32_e32 vcc, s4, v30 + ; implicit-def: $vgpr30 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3187: + v_accvgpr_read_b32 v31, a37 + v_bfe_u32 v30, v31, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v30, v31, v30, s6 + ; implicit-def: $agpr37 +; %bb.3188: ; %Flow1043 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3189: + v_mov_b32_e32 v30, 0 + v_accvgpr_read_b32 v32, a37 + v_or_b32_e32 v31, 0x10000, v32 + v_cmp_eq_u32_sdwa vcc, v32, v30 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v30, v31, v32, vcc +; %bb.3190: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit218.i.i.i.i.i1862.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v31, a36 + v_and_b32_e32 v31, 0x7f800000, v31 + v_cmp_ne_u32_e32 vcc, s4, v31 + ; implicit-def: $vgpr31 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3191: + v_accvgpr_read_b32 v32, a36 + v_bfe_u32 v31, v32, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v31, v32, v31, s6 + ; implicit-def: $agpr36 +; %bb.3192: ; %Flow1042 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3193: + v_mov_b32_e32 v31, 0 + v_accvgpr_read_b32 v33, a36 + v_or_b32_e32 v32, 0x10000, v33 + v_cmp_eq_u32_sdwa vcc, v33, v31 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v31, v32, v33, vcc +; %bb.3194: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit223.i.i.i.i.i1865.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v32, a35 + v_and_b32_e32 v32, 0x7f800000, v32 + v_cmp_ne_u32_e32 vcc, s4, v32 + ; implicit-def: $vgpr32 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3195: + v_accvgpr_read_b32 v33, a35 + v_bfe_u32 v32, v33, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v32, v33, v32, s6 + ; implicit-def: $agpr35 +; %bb.3196: ; %Flow1041 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3197: + v_mov_b32_e32 v32, 0 + v_accvgpr_read_b32 v34, a35 + v_or_b32_e32 v33, 0x10000, v34 + v_cmp_eq_u32_sdwa vcc, v34, v32 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v32, v33, v34, vcc +; %bb.3198: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit228.i.i.i.i.i1868.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v33, a34 + v_and_b32_e32 v33, 0x7f800000, v33 + v_cmp_ne_u32_e32 vcc, s4, v33 + ; implicit-def: $vgpr33 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3199: + v_accvgpr_read_b32 v34, a34 + v_bfe_u32 v33, v34, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v33, v34, v33, s6 + ; implicit-def: $agpr34 +; %bb.3200: ; %Flow1040 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3201: + v_mov_b32_e32 v33, 0 + v_accvgpr_read_b32 v35, a34 + v_or_b32_e32 v34, 0x10000, v35 + v_cmp_eq_u32_sdwa vcc, v35, v33 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v33, v34, v35, vcc +; %bb.3202: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit233.i.i.i.i.i1871.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v34, a33 + v_and_b32_e32 v34, 0x7f800000, v34 + v_cmp_ne_u32_e32 vcc, s4, v34 + ; implicit-def: $vgpr34 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3203: + v_accvgpr_read_b32 v35, a33 + v_bfe_u32 v34, v35, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v34, v35, v34, s6 + ; implicit-def: $agpr33 +; %bb.3204: ; %Flow1039 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3205: + v_mov_b32_e32 v34, 0 + v_accvgpr_read_b32 v36, a33 + v_or_b32_e32 v35, 0x10000, v36 + v_cmp_eq_u32_sdwa vcc, v36, v34 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v34, v35, v36, vcc +; %bb.3206: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit238.i.i.i.i.i1874.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_accvgpr_read_b32 v35, a32 + v_and_b32_e32 v35, 0x7f800000, v35 + v_cmp_ne_u32_e32 vcc, s4, v35 + ; implicit-def: $vgpr35 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3207: + v_accvgpr_read_b32 v36, a32 + v_bfe_u32 v35, v36, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v35, v36, v35, s6 + ; implicit-def: $agpr32 +; %bb.3208: ; %Flow1038 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3209: + v_mov_b32_e32 v35, 0 + v_accvgpr_read_b32 v37, a32 + v_or_b32_e32 v36, 0x10000, v37 + v_cmp_eq_u32_sdwa vcc, v37, v35 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v35, v36, v37, vcc +; %bb.3210: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit243.i.i.i.i.i1877.i.i.i.i.i + s_or_b64 exec, exec, s[4:5] + s_mov_b32 s4, 0x7f800000 + v_and_b32_e32 v36, 0x7f800000, v86 + v_cmp_ne_u32_e32 vcc, s4, v36 + ; implicit-def: $vgpr36 + s_and_saveexec_b64 s[4:5], vcc + s_xor_b64 s[4:5], exec, s[4:5] +; %bb.3211: + v_bfe_u32 v36, v86, 16, 1 + s_movk_i32 s6, 0x7fff + v_add3_u32 v36, v86, v36, s6 + ; implicit-def: $vgpr86 +; %bb.3212: ; %Flow1037 + s_andn2_saveexec_b64 s[4:5], s[4:5] +; %bb.3213: + v_mov_b32_e32 v36, 0 + v_or_b32_e32 v37, 0x10000, v86 + v_cmp_eq_u32_sdwa vcc, v86, v36 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v36, v37, v86, vcc +; %bb.3214: ; %_ZN7ck_tile16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bS3_NS_13tensor_layout4gemm8RowMajorENS_12element_wise11PassThroughELi256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEclINS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EDF16blLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINS2_IJNS_5embedINS2_IJiiEEESK_Lb0EEENS_12pass_throughIiEESN_EEENS2_IJNS_8sequenceIJLi0EEEENSP_IJLi1EEEENSP_IJLi2EEEEEEENS2_IJNSP_IJLi1ELi2EEEENSP_IJLi3EEEENSP_IJLi4EEEEEEENSP_IJLi3ELi4EEEElNSP_IJLin1ELin1ELi8ELin1ELin1EEEENSP_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENS2_IJNS_8constantILi256EEES15_EEEEENS_25static_distributed_tensorIfNS_17tile_distributionINS_14tensor_adaptorINS2_IJNS_9replicateIS3_EENS_7unmergeINS2_IJNS14_ILi4EEENS14_ILi2EEES1E_S1F_S1E_EEELb0EEENS1D_INS2_IJS1E_S1F_NS14_ILi32EEEEEELb0EEENS_23merge_v2_magic_divisionINS2_IJS1F_S1F_EEEEENS1L_INS2_IJS1F_S1I_EEEEEEEENS2_IJNSP_IJEEESQ_SR_NSP_ + s_or_b64 exec, exec, s[4:5] + ds_write_b16_d16_hi v19, v2 + ds_write_b16_d16_hi v19, v3 offset:128 + ds_write_b16_d16_hi v19, v4 offset:256 + ds_write_b16_d16_hi v19, v5 offset:384 + ds_write_b16_d16_hi v19, v6 offset:1024 + ds_write_b16_d16_hi v19, v7 offset:1152 + ds_write_b16_d16_hi v19, v8 offset:1280 + ds_write_b16_d16_hi v19, v9 offset:1408 + ds_write_b16_d16_hi v19, v10 offset:2048 + ds_write_b16_d16_hi v19, v11 offset:2176 + ds_write_b16_d16_hi v19, v12 offset:2304 + ds_write_b16_d16_hi v19, v13 offset:2432 + ds_write_b16_d16_hi v19, v14 offset:3072 + ds_write_b16_d16_hi v19, v15 offset:3200 + ds_write_b16_d16_hi v19, v16 offset:3328 + ds_write_b16_d16_hi v19, v17 offset:3456 + ds_write_b16_d16_hi v19, v20 offset:8192 + ds_write_b16_d16_hi v19, v22 offset:8320 + ds_write_b16_d16_hi v19, v23 offset:8448 + ds_write_b16_d16_hi v19, v24 offset:8576 + ds_write_b16_d16_hi v19, v25 offset:9216 + ds_write_b16_d16_hi v19, v26 offset:9344 + ds_write_b16_d16_hi v19, v27 offset:9472 + ds_write_b16_d16_hi v19, v28 offset:9600 + ds_write_b16_d16_hi v19, v29 offset:10240 + ds_write_b16_d16_hi v19, v30 offset:10368 + ds_write_b16_d16_hi v19, v31 offset:10496 + ds_write_b16_d16_hi v19, v32 offset:10624 + ds_write_b16_d16_hi v19, v33 offset:11264 + ds_write_b16_d16_hi v19, v34 offset:11392 + ds_write_b16_d16_hi v19, v35 offset:11520 + ds_write_b16_d16_hi v19, v36 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_readfirstlane_b32 s4, v0 + s_lshr_b32 s4, s4, 1 + s_and_b32 s4, s4, 0x7fffffe0 + v_add_u32_e32 v0, s4, v1 + v_lshl_or_b32 v1, v0, 7, v21 + ds_read_b128 v[2:5], v1 + ds_read_b128 v[6:9], v1 offset:128 + ds_read_b128 v[10:13], v1 offset:256 + ds_read_b128 v[14:17], v1 offset:384 + v_add_u32_e32 v0, s18, v0 + v_mad_u64_u32 v[0:1], s[4:5], v0, s16, v[18:19] + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx2 v[2:3], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[4:5], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx2 v[6:7], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[8:9], v1, s[0:3], 8 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx2 v[10:11], v1, s[0:3], 0 offen + buffer_store_dwordx2 v[12:13], v1, s[0:3], 8 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx2 v[14:15], v0, s[0:3], 0 offen + buffer_store_dwordx2 v[16:17], v0, s[0:3], 8 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end15: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end15-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 28 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16bDF16bfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEDF16bNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16bDF16bNS_5tupleIJEEEfDF16bSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 100216 +; TotalNumSgprs: 34 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB16_9 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB16_4 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s8 + v_mov_b32_e32 v3, s9 + v_mul_lo_u32 v4, v6, s7 + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v0 +.LBB16_3: ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_ushort v7, v[2:3], off + v_lshl_add_u64 v[8:9], v[4:5], 1, s[10:11] + global_load_ushort v5, v[8:9], off + s_add_i32 s6, s6, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + s_waitcnt vmcnt(1) + v_lshlrev_b32_e32 v7, 16, v7 + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v5, 16, v5 + v_fmac_f32_e32 v1, v5, v7 + s_cbranch_scc0 .LBB16_3 +.LBB16_4: ; %._crit_edge + s_mov_b32 s0, 0x7f800000 + v_and_b32_e32 v2, 0x7f800000, v1 + v_cmp_ne_u32_e32 vcc, s0, v2 + ; implicit-def: $vgpr2 + s_and_saveexec_b64 s[0:1], vcc + s_xor_b64 s[0:1], exec, s[0:1] + s_cbranch_execz .LBB16_6 +; %bb.5: + v_bfe_u32 v2, v1, 16, 1 + s_waitcnt lgkmcnt(0) + s_movk_i32 s2, 0x7fff + v_add3_u32 v2, v1, v2, s2 + ; implicit-def: $vgpr1 +.LBB16_6: ; %Flow + s_andn2_saveexec_b64 s[0:1], s[0:1] +; %bb.7: + v_mov_b32_e32 v2, 0 + v_or_b32_e32 v3, 0x10000, v1 + v_cmp_eq_u32_sdwa vcc, v1, v2 src0_sel:WORD_0 src1_sel:DWORD + s_nop 1 + v_cndmask_b32_e32 v2, v3, v1, vcc +; %bb.8: ; %_ZN7ck_tile12type_convertIDF16bfTnNSt9enable_ifIXntoosr3stdE10is_const_vIT_Esr3stdE10is_const_vIT0_EEbE4typeELb0EEES2_S3_.exit + s_or_b64 exec, exec, s[0:1] + s_waitcnt lgkmcnt(0) + v_mad_u64_u32 v[0:1], s[0:1], v6, s3, v[0:1] + v_mov_b32_e32 v4, s12 + v_mov_b32_e32 v5, s13 + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[4:5] + global_store_short_d16_hi v[0:1], v2, off +.LBB16_9: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end16: + .size _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end16-_ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16bDF16bfDF16bNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 528 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s12, s10, s15 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s22, s3 + s_add_u32 s2, s2, s3 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v2, -1, 0 + s_cbranch_scc0 .LBB17_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v2 + s_lshr_b32 s19, s15, 2 + v_and_b32_e32 v25, 15, v225 + s_and_b32 s11, s19, 0x3ffffff0 + v_lshrrev_b32_e32 v0, 2, v225 + v_and_b32_e32 v1, 28, v0 + v_lshl_or_b32 v0, v25, 4, s20 + v_add_u32_e32 v28, s11, v1 + v_mad_u64_u32 v[0:1], s[24:25], v28, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[8:11], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[12:15], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[16:19], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[20:23], v0, s[8:11], 0 offen + s_mov_b32 s23, 0x3020504 + s_mov_b32 s26, 0x5010400 + s_mov_b32 s27, 0x5040100 + s_mov_b32 s28, 0x7060302 + s_mov_b32 s29, 0x7030602 + v_and_b32_e32 v1, 31, v225 + v_lshrrev_b32_e32 v29, 5, v225 + v_lshlrev_b32_e32 v0, 4, v225 + s_and_b32 s24, s15, 0xffffffc0 + v_and_b32_e32 v3, 0x7c, v225 + s_lshr_b32 s25, s15, 1 + v_lshlrev_b32_e32 v4, 3, v225 + s_mov_b32 s15, s11 + s_and_b32 s19, s19, 0x3fffffe0 + v_lshlrev_b32_e32 v30, 3, v29 + v_lshlrev_b32_e32 v6, 12, v29 + v_and_b32_e32 v24, 48, v0 + v_add_u32_e32 v31, s24, v3 + s_and_b32 s11, s25, 32 + v_and_or_b32 v5, v4, 8, v29 + v_or_b32_e32 v0, s19, v1 + v_lshl_or_b32 v32, v25, 7, v6 + v_add_u32_e32 v3, s21, v31 + v_or_b32_e32 v4, s11, v1 + v_lshrrev_b32_e32 v33, 4, v0 + v_mad_u64_u32 v[26:27], s[24:25], v3, s22, v[24:25] + v_lshrrev_b32_e32 v7, 1, v4 + v_bfe_u32 v4, v4, 1, 4 + v_xor_b32_e32 v27, v25, v33 + v_xor_b32_e32 v3, v4, v5 + v_lshlrev_b32_e32 v6, 7, v7 + v_add_u32_e32 v34, s22, v26 + buffer_load_dwordx4 v[38:41], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v34, s[12:15], 0 offen + v_add_u32_e32 v26, s22, v34 + v_add_u32_e32 v34, s22, v26 + buffer_load_dwordx4 v[46:49], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[50:53], v34, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v8, v8, v8, s23 + v_perm_b32 v9, v9, v9, s23 + v_perm_b32 v10, v10, v10, s23 + v_perm_b32 v11, v11, v11, s23 + s_waitcnt vmcnt(6) + v_perm_b32 v12, v12, v12, s23 + v_perm_b32 v13, v13, v13, s23 + v_perm_b32 v14, v14, v14, s23 + v_perm_b32 v15, v15, v15, s23 + s_waitcnt vmcnt(5) + v_perm_b32 v16, v16, v16, s23 + v_perm_b32 v17, v17, v17, s23 + v_perm_b32 v18, v18, v18, s23 + v_perm_b32 v19, v19, v19, s23 + v_perm_b32 v26, v12, v8, s26 + v_perm_b32 v8, v12, v8, s29 + v_perm_b32 v12, v13, v9, s26 + v_perm_b32 v9, v13, v9, s29 + v_perm_b32 v13, v14, v10, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v20, v20, v20, s23 + v_perm_b32 v21, v21, v21, s23 + v_perm_b32 v22, v22, v22, s23 + v_perm_b32 v23, v23, v23, s23 + v_perm_b32 v34, v20, v16, s26 + v_perm_b32 v16, v20, v16, s29 + v_perm_b32 v20, v21, v17, s26 + v_perm_b32 v17, v21, v17, s29 + v_perm_b32 v21, v34, v26, s27 + v_perm_b32 v26, v34, v26, s28 + v_perm_b32 v34, v16, v8, s27 + v_perm_b32 v8, v16, v8, s28 + v_perm_b32 v16, v20, v12, s27 + v_perm_b32 v12, v20, v12, s28 + v_perm_b32 v20, v17, v9, s27 + v_perm_b32 v9, v17, v9, s28 + v_perm_b32 v17, v22, v18, s26 + v_perm_b32 v35, v17, v13, s27 + v_perm_b32 v13, v17, v13, s28 + v_perm_b32 v10, v14, v10, s29 + v_perm_b32 v14, v22, v18, s29 + v_perm_b32 v17, v14, v10, s27 + v_perm_b32 v10, v14, v10, s28 + v_perm_b32 v14, v15, v11, s26 + v_perm_b32 v18, v23, v19, s26 + v_perm_b32 v22, v18, v14, s27 + v_perm_b32 v14, v18, v14, s28 + v_perm_b32 v11, v15, v11, s29 + v_perm_b32 v15, v23, v19, s29 + v_perm_b32 v18, v15, v11, s27 + v_perm_b32 v11, v15, v11, s28 + v_lshrrev_b32_e32 v15, 1, v28 + v_and_b32_e32 v15, 16, v15 + v_xor_b32_e32 v19, v15, v1 + v_lshlrev_b32_e32 v23, 9, v28 + v_and_b32_e32 v23, 0x3000, v23 + v_lshlrev_b32_e32 v28, 6, v28 + s_movk_i32 s15, 0xf800 + v_and_b32_e32 v28, 0xfffff800, v28 + v_add_u32_e32 v23, v23, v28 + v_lshl_or_b32 v23, v19, 2, v23 + ds_write_b32 v23, v21 + v_or_b32_e32 v21, 1, v15 + v_xor_b32_e32 v21, v21, v1 + v_sub_u32_e32 v19, v21, v19 + v_lshl_add_u32 v19, v19, 2, v23 + ds_write_b32 v19, v26 offset:128 + v_or_b32_e32 v23, 2, v15 + v_xor_b32_e32 v23, v23, v1 + v_sub_u32_e32 v21, v23, v21 + v_mov_b32_e32 v26, 0x80 + v_lshl_add_u32 v21, v21, 2, v26 + v_or_b32_e32 v28, 3, v15 + v_xor_b32_e32 v28, v28, v1 + v_sub_u32_e32 v23, v28, v23 + v_lshl_add_u32 v23, v23, 2, v26 + v_add3_u32 v36, v19, v21, v23 + v_add3_u32 v19, v19, s18, v21 + ds_write_b32 v19, v34 + v_add_u32_e32 v19, v23, v19 + ds_write_b32 v19, v8 + v_or_b32_e32 v8, 4, v15 + v_xor_b32_e32 v8, v8, v1 + v_sub_u32_e32 v21, v8, v28 + v_lshl_add_u32 v21, v21, 2, v26 + v_or_b32_e32 v23, 5, v15 + v_xor_b32_e32 v23, v23, v1 + v_sub_u32_e32 v8, v23, v8 + v_lshl_add_u32 v8, v8, 2, v26 + v_add3_u32 v28, v36, v21, v8 + v_add_u32_e32 v19, v21, v19 + ds_write_b32 v19, v16 + v_add_u32_e32 v8, v8, v19 + ds_write_b32 v8, v12 + v_or_b32_e32 v12, 6, v15 + v_xor_b32_e32 v12, v12, v1 + v_sub_u32_e32 v16, v12, v23 + v_lshl_add_u32 v16, v16, 2, v26 + v_or_b32_e32 v19, 7, v15 + v_xor_b32_e32 v19, v19, v1 + v_sub_u32_e32 v12, v19, v12 + v_lshl_add_u32 v12, v12, 2, v26 + v_add3_u32 v21, v28, v16, v12 + v_add_u32_e32 v8, v16, v8 + ds_write_b32 v8, v20 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v9 + v_or_b32_e32 v9, 8, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v12, v9, v19 + v_lshl_add_u32 v12, v12, 2, v26 + v_or_b32_e32 v16, 9, v15 + v_xor_b32_e32 v16, v16, v1 + v_sub_u32_e32 v9, v16, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v19, v21, v12, v9 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v35 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v13 + v_or_b32_e32 v9, 10, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v12, v9, v16 + v_lshl_add_u32 v12, v12, 2, v26 + v_or_b32_e32 v13, 11, v15 + v_xor_b32_e32 v13, v13, v1 + v_sub_u32_e32 v9, v13, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v16, v19, v12, v9 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v17 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v10 + v_or_b32_e32 v9, 12, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v10, v9, v13 + v_lshl_add_u32 v10, v10, 2, v26 + v_or_b32_e32 v12, 13, v15 + v_xor_b32_e32 v12, v12, v1 + v_sub_u32_e32 v9, v12, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v13, v16, v10, v9 + v_add_u32_e32 v8, v10, v8 + ds_write_b32 v8, v22 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v14 + v_or_b32_e32 v9, 14, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v10, v9, v12 + v_lshlrev_b32_e32 v10, 2, v10 + v_or_b32_e32 v12, 15, v15 + v_xor_b32_e32 v1, v12, v1 + v_sub_u32_e32 v1, v1, v9 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v13, v10, v1 + v_add_u32_e32 v8, v8, v10 + ds_write_b32 v8, v18 offset:128 + ds_write_b32 v1, v11 offset:384 + v_lshrrev_b32_e32 v1, 3, v24 + v_ashrrev_i32_e32 v8, 1, v31 + v_ashrrev_i32_e32 v9, 31, v31 + v_lshrrev_b32_e32 v9, 28, v9 + v_add_u32_e32 v10, v8, v9 + v_and_b32_e32 v10, -16, v10 + v_sub_u32_e32 v10, v8, v10 + v_xor_b32_e32 v11, v10, v1 + v_lshlrev_b32_e32 v12, 6, v31 + v_lshl_add_u32 v11, v11, 3, v12 + s_waitcnt vmcnt(3) + ds_write_b64 v11, v[38:39] offset:16384 + v_or_b32_e32 v11, 1, v1 + v_xor_b32_e32 v10, v10, v11 + v_lshl_add_u32 v12, v10, 3, v12 + ds_write_b64 v12, v[40:41] offset:16384 + v_or_b32_e32 v13, 1, v31 + v_sub_u32_e32 v14, v1, v11 + v_lshrrev_b32_e32 v15, 31, v31 + v_add_u32_e32 v16, v13, v15 + v_ashrrev_i32_e32 v17, 1, v16 + v_sub_u32_e32 v18, v17, v8 + v_and_b32_e32 v19, 0x1ffffffe, v16 + v_sub_u32_e32 v13, v13, v19 + v_lshl_or_b32 v13, v13, 3, v11 + v_add_u32_e32 v19, v13, v14 + v_ashrrev_i32_e32 v16, 31, v16 + v_lshrrev_b32_e32 v16, 28, v16 + v_add_u32_e32 v16, v17, v16 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v16, v17, v16 + v_xor_b32_e32 v19, v19, v16 + v_sub_u32_e32 v19, v19, v10 + v_lshl_add_u32 v12, v18, 7, v12 + v_lshl_add_u32 v18, v19, 3, v12 + s_waitcnt vmcnt(2) + ds_write_b64 v18, v[42:43] offset:16384 + v_xor_b32_e32 v13, v13, v16 + v_sub_u32_e32 v10, v13, v10 + v_lshl_add_u32 v10, v10, 3, v12 + ds_write_b64 v10, v[44:45] offset:16384 + v_or_b32_e32 v8, 1, v8 + v_sub_u32_e32 v12, v8, v17 + v_add_u32_e32 v9, v8, v9 + v_and_b32_e32 v9, -16, v9 + v_sub_u32_e32 v9, v8, v9 + v_xor_b32_e32 v1, v9, v1 + v_sub_u32_e32 v13, v1, v13 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshlrev_b32_e32 v12, 7, v12 + v_add3_u32 v10, v13, v12, v10 + s_waitcnt vmcnt(1) + ds_write_b64 v10, v[46:47] offset:16384 + v_xor_b32_e32 v9, v9, v11 + v_sub_u32_e32 v1, v9, v1 + v_lshl_add_u32 v1, v1, 3, v10 + ds_write_b64 v1, v[48:49] offset:16384 + v_or_b32_e32 v10, 3, v31 + v_add_u32_e32 v12, v10, v15 + v_ashrrev_i32_e32 v13, 1, v12 + v_sub_u32_e32 v8, v13, v8 + v_and_b32_e32 v15, 0x1ffffffe, v12 + v_sub_u32_e32 v10, v10, v15 + v_lshl_or_b32 v10, v10, 3, v11 + v_add_u32_e32 v11, v10, v14 + v_ashrrev_i32_e32 v12, 31, v12 + v_lshrrev_b32_e32 v12, 28, v12 + v_add_u32_e32 v12, v13, v12 + v_and_b32_e32 v12, -16, v12 + v_sub_u32_e32 v12, v13, v12 + v_xor_b32_e32 v11, v11, v12 + v_sub_u32_e32 v9, v11, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_lshlrev_b32_e32 v8, 7, v8 + v_add3_u32 v1, v9, v8, v1 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[50:51] offset:16384 + v_xor_b32_e32 v8, v10, v12 + v_sub_u32_e32 v8, v8, v11 + v_lshl_add_u32 v1, v8, 3, v1 + ds_write_b64 v1, v[52:53] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v1, v27, 2, v32 + v_lshrrev_b16_e32 v9, 3, v30 + v_add_u32_e32 v10, 16, v33 + v_xor_b32_e32 v8, v25, v10 + v_sub_u32_e32 v11, v9, v29 + v_lshlrev_b32_e32 v11, 12, v11 + v_lshlrev_b32_e32 v12, 2, v8 + v_add3_u32 v11, v12, v32, v11 + v_add_u32_e32 v12, 16, v30 + v_lshrrev_b32_e32 v13, 5, v12 + v_lshrrev_b16_e32 v12, 3, v12 + v_and_b32_e32 v12, 3, v12 + v_sub_u16_e32 v14, v12, v9 + v_bfe_i32 v14, v14, 0, 16 + v_lshlrev_b32_e32 v15, 4, v13 + v_or_b32_e32 v16, v15, v25 + v_and_b32_e32 v16, 31, v16 + v_xor_b32_e32 v16, v16, v33 + v_sub_u32_e32 v8, v16, v8 + v_lshlrev_b32_e32 v17, 11, v13 + v_lshlrev_b32_e32 v8, 2, v8 + v_lshl_add_u32 v31, v14, 12, v17 + v_add3_u32 v14, v31, v11, v8 + v_add_u32_e32 v8, 20, v30 + v_lshrrev_b32_e32 v17, 5, v8 + v_sub_u32_e32 v13, v17, v13 + v_lshrrev_b16_e32 v8, 3, v8 + v_and_b32_e32 v8, 3, v8 + v_sub_u16_e32 v12, v8, v12 + v_bfe_i32 v12, v12, 0, 16 + v_lshlrev_b32_e32 v18, 4, v17 + v_or_b32_e32 v19, v18, v25 + v_and_b32_e32 v19, 31, v19 + v_xor_b32_e32 v19, v19, v10 + v_sub_u32_e32 v16, v19, v16 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v16, 2, v16 + v_lshl_add_u32 v32, v12, 12, v13 + v_add3_u32 v12, v16, v32, v14 + v_sub_u16_e32 v8, v9, v8 + v_bfe_i32 v8, v8, 0, 16 + v_or_b32_e32 v13, 16, v25 + v_xor_b32_e32 v16, v13, v33 + v_sub_u32_e32 v19, v16, v19 + v_lshlrev_b32_e32 v17, 11, v17 + v_xor_b32_e32 v17, 0x800, v17 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_add_u32 v34, v8, 12, v17 + v_add3_u32 v17, v19, v34, v12 + v_xor_b32_e32 v8, v13, v10 + v_sub_u32_e32 v13, v8, v16 + v_lshl_add_u32 v13, v13, 2, v17 + v_add_u32_e32 v16, 48, v30 + v_lshrrev_b32_e32 v19, 5, v16 + v_lshlrev_b32_e32 v20, 11, v19 + v_lshrrev_b16_e32 v16, 3, v16 + v_and_b32_e32 v16, 3, v16 + v_sub_u16_e32 v21, v16, v9 + v_lshlrev_b32_e32 v22, 4, v19 + v_or_b32_e32 v23, v22, v25 + v_and_b32_e32 v23, 31, v23 + v_xor_b32_e32 v23, v23, v33 + v_sub_u32_e32 v8, v23, v8 + v_lshlrev_b32_e32 v24, 2, v8 + v_mov_b32_e32 v26, 12 + v_lshlrev_b32_sdwa v8, v26, sext(v21) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v8, v20, v8, s15 + v_add3_u32 v20, v24, v8, v13 + v_add_u32_e32 v21, 52, v30 + v_lshrrev_b32_e32 v24, 5, v21 + v_sub_u32_e32 v19, v24, v19 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v16, v21, v16 + v_bfe_i32 v16, v16, 0, 16 + v_lshlrev_b32_e32 v27, 4, v24 + v_or_b32_e32 v25, v27, v25 + v_and_b32_e32 v30, 31, v25 + v_xor_b32_e32 v10, v30, v10 + v_sub_u32_e32 v23, v10, v23 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_add_u32 v33, v16, 12, v19 + v_add3_u32 v16, v23, v33, v20 + ds_read_b32 v52, v1 + ds_read_b32 v53, v11 + ds_read_b32 v72, v14 + ds_read_b32 v73, v12 + ds_read_b32 v74, v17 + ds_read_b32 v75, v13 + ds_read_b32 v76, v20 + ds_read_b32 v77, v16 + v_add_u32_e32 v1, 64, v0 + v_lshrrev_b32_e32 v1, 4, v1 + v_sub_u16_e32 v9, v9, v21 + v_sub_u32_e32 v11, v25, v27 + v_ashrrev_i32_e32 v12, 31, v11 + v_lshrrev_b32_e32 v12, 27, v12 + v_add_u32_e32 v12, v11, v12 + v_and_b32_e32 v12, 0xffffffe0, v12 + v_sub_u32_e32 v35, v11, v12 + v_xor_b32_e32 v12, v35, v1 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_lshlrev_b32_sdwa v9, v26, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v13, 11, v24 + v_sub_u32_e32 v9, v9, v13 + v_add3_u32 v10, v10, v9, v16 + v_add_u32_e32 v36, 16, v1 + v_xor_b32_e32 v13, v35, v36 + v_sub_u32_e32 v12, v13, v12 + v_lshl_add_u32 v12, v12, 2, v10 + v_add_u32_e32 v14, v11, v15 + v_ashrrev_i32_e32 v15, 31, v14 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v14, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v37, v14, v15 + v_xor_b32_e32 v14, v37, v1 + v_sub_u32_e32 v13, v14, v13 + v_lshl_add_u32 v13, v13, 2, v31 + v_add_u32_e32 v38, v13, v12 + v_add_u32_e32 v13, v11, v18 + v_ashrrev_i32_e32 v15, 31, v13 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v13, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v39, v13, v15 + v_xor_b32_e32 v13, v39, v36 + v_sub_u32_e32 v14, v13, v14 + v_lshl_add_u32 v40, v14, 2, v32 + v_add_u32_e32 v14, v38, v40 + ds_read_b32 v62, v10 + ds_read_b32 v63, v12 + ds_read_b32 v78, v38 + ds_read_b32 v79, v14 + v_add_u32_e32 v10, 16, v11 + v_ashrrev_i32_e32 v12, 31, v10 + v_lshrrev_b32_e32 v12, 27, v12 + v_add_u32_e32 v12, v10, v12 + v_and_b32_e32 v12, 0xffffffe0, v12 + v_sub_u32_e32 v41, v10, v12 + v_xor_b32_e32 v10, v41, v1 + v_sub_u32_e32 v12, v10, v13 + v_lshl_add_u32 v42, v12, 2, v34 + v_add_u32_e32 v43, v14, v42 + v_xor_b32_e32 v44, v41, v36 + v_sub_u32_e32 v10, v44, v10 + v_lshlrev_b32_e32 v45, 2, v10 + v_add_u32_e32 v46, v43, v45 + v_add_u32_e32 v10, v11, v22 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshrrev_b32_e32 v11, 27, v11 + v_add_u32_e32 v11, v10, v11 + v_and_b32_e32 v11, 0xffffffe0, v11 + v_sub_u32_e32 v47, v10, v11 + v_xor_b32_e32 v1, v47, v1 + v_lshl_or_b32 v10, v3, 3, v6 + v_add_u32_e32 v16, 2, v5 + v_add_u32_e32 v11, -16, v7 + s_cmp_eq_u32 s11, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v7, v11, v7, vcc + v_xor_b32_e32 v11, v7, v16 + v_lshl_add_u32 v12, v11, 3, v6 + v_or_b32_e32 v17, 4, v5 + v_xor_b32_e32 v11, v7, v17 + v_lshl_add_u32 v14, v11, 3, v6 + ds_read_b64 v[10:11], v10 offset:16384 + ds_read_b64 v[12:13], v12 offset:16384 + ds_read_b64 v[14:15], v14 offset:16384 + v_add_u32_e32 v5, 6, v5 + v_xor_b32_e32 v7, v7, v5 + v_lshl_add_u32 v48, v7, 3, v6 + v_sub_u32_e32 v6, v3, v7 + v_lshl_add_u32 v20, v6, 3, v48 + v_xor_b32_e32 v6, v4, v16 + v_sub_u32_e32 v6, v6, v3 + v_lshlrev_b32_e32 v26, 3, v6 + v_add_u32_e32 v16, v20, v26 + v_xor_b32_e32 v6, v4, v17 + v_sub_u32_e32 v6, v6, v3 + v_lshlrev_b32_e32 v27, 3, v6 + v_add_u32_e32 v18, v20, v27 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[52:53], v[10:11], 0 + ds_read_b64 v[6:7], v20 offset:20480 + ds_read_b64 v[16:17], v16 offset:20480 + ds_read_b64 v[18:19], v18 offset:20480 + v_xor_b32_e32 v4, v4, v5 + v_sub_u32_e32 v5, v4, v3 + v_lshlrev_b32_e32 v49, 3, v5 + v_add_u32_e32 v50, v20, v49 + v_sub_u32_e32 v3, v3, v4 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[52:53], v[6:7], 0 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v24, v50, v3 + ds_read_b64 v[4:5], v24 offset:24576 + v_add_u32_e32 v20, v24, v26 + v_add_u32_e32 v22, v24, v27 + ds_read_b64 v[20:21], v20 offset:24576 + ds_read_b64 v[22:23], v22 offset:24576 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[52:53], v[4:5], 0 + v_add_u32_e32 v51, v24, v49 + v_add_u32_e32 v3, v51, v3 + ds_read_b64 v[24:25], v3 offset:28672 + v_add_u32_e32 v26, v3, v26 + v_add_u32_e32 v28, v3, v27 + ds_read_b64 v[26:27], v26 offset:28672 + ds_read_b64 v[28:29], v28 offset:28672 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[52:53], v[24:25], 0 + v_sub_u32_e32 v44, v1, v44 + v_lshl_add_u32 v44, v44, 2, v8 + v_add_u32_e32 v52, v46, v44 + v_xor_b32_e32 v36, v30, v36 + v_sub_u32_e32 v1, v36, v1 + v_lshl_add_u32 v53, v1, 2, v33 + v_add_u32_e32 v54, v52, v53 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[62:63], v[10:11], 0 + v_add_u32_e32 v1, 0x80, v0 + v_lshrrev_b32_e32 v1, 4, v1 + v_xor_b32_e32 v55, v35, v1 + v_sub_u32_e32 v36, v55, v36 + v_lshl_add_u32 v36, v36, 2, v9 + v_add_u32_e32 v56, v54, v36 + ds_read_b32 v80, v56 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[62:63], v[6:7], 0 + v_add_u32_e32 v57, 16, v1 + v_xor_b32_e32 v58, v35, v57 + v_sub_u32_e32 v55, v58, v55 + v_lshlrev_b32_e32 v55, 2, v55 + v_add_u32_e32 v56, v56, v55 + ds_read_b32 v81, v56 + v_xor_b32_e32 v59, v37, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[62:63], v[4:5], 0 + v_sub_u32_e32 v58, v59, v58 + v_lshl_add_u32 v58, v58, 2, v31 + v_add_u32_e32 v56, v56, v58 + v_xor_b32_e32 v60, v39, v57 + v_sub_u32_e32 v59, v60, v59 + v_lshl_add_u32 v59, v59, 2, v32 + v_add_u32_e32 v61, v56, v59 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[62:63], v[24:25], 0 + v_xor_b32_e32 v62, v41, v1 + v_sub_u32_e32 v60, v62, v60 + v_lshl_add_u32 v60, v60, 2, v34 + v_add_u32_e32 v63, v61, v60 + v_xor_b32_e32 v64, v41, v57 + v_sub_u32_e32 v62, v64, v62 + v_lshlrev_b32_e32 v62, 2, v62 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[80:81], v[10:11], 0 + v_add_u32_e32 v65, v63, v62 + v_xor_b32_e32 v1, v47, v1 + v_sub_u32_e32 v64, v1, v64 + v_lshl_add_u32 v64, v64, 2, v8 + v_add_u32_e32 v66, v65, v64 + v_xor_b32_e32 v57, v30, v57 + v_sub_u32_e32 v1, v57, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[80:81], v[6:7], 0 + v_lshl_add_u32 v67, v1, 2, v33 + v_add_u32_e32 v68, v66, v67 + v_add_u32_e32 v0, 0xc0, v0 + v_lshrrev_b32_e32 v69, 4, v0 + v_xor_b32_e32 v0, v35, v69 + v_sub_u32_e32 v1, v0, v57 + v_lshl_add_u32 v9, v1, 2, v9 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[80:81], v[4:5], 0 + v_add_u32_e32 v1, v68, v9 + ds_read_b32 v82, v1 + v_add_u32_e32 v57, 16, v69 + v_xor_b32_e32 v35, v35, v57 + v_sub_u32_e32 v0, v35, v0 + v_lshlrev_b32_e32 v70, 2, v0 + v_add_u32_e32 v0, v1, v70 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[80:81], v[24:25], 0 + ds_read_b32 v83, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[82:83], v[10:11], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[82:83], v[6:7], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[82:83], v[4:5], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[82:83], v[24:25], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[72:73], v[12:13], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[72:73], v[16:17], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[72:73], v[20:21], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[72:73], v[26:27], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[78:79], v[12:13], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[78:79], v[16:17], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[78:79], v[20:21], a[128:143] + ds_read_b32 v6, v56 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[78:79], v[26:27], a[112:127] + ds_read_b32 v7, v61 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[6:7], v[12:13], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[6:7], v[16:17], a[80:95] + v_xor_b32_e32 v1, v37, v69 + v_sub_u32_e32 v4, v1, v35 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[6:7], v[20:21], a[64:79] + v_lshl_add_u32 v24, v4, 2, v31 + v_add_u32_e32 v0, v0, v24 + ds_read_b32 v10, v0 + v_xor_b32_e32 v4, v39, v57 + v_sub_u32_e32 v1, v4, v1 + v_lshl_add_u32 v25, v1, 2, v32 + v_add_u32_e32 v0, v0, v25 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[6:7], v[26:27], a[48:63] + ds_read_b32 v11, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[10:11], v[12:13], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[10:11], v[16:17], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[10:11], v[20:21], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[10:11], v[26:27], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[74:75], v[14:15], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[74:75], v[18:19], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[74:75], v[22:23], a[192:207] + ds_read_b32 v6, v43 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[74:75], v[28:29], a[176:191] + ds_read_b32 v7, v46 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[6:7], v[14:15], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[6:7], v[18:19], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[6:7], v[22:23], a[128:143] + ds_read_b32 v10, v63 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[6:7], v[28:29], a[112:127] + ds_read_b32 v11, v65 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[10:11], v[14:15], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[10:11], v[18:19], a[80:95] + v_xor_b32_e32 v1, v41, v69 + v_sub_u32_e32 v4, v1, v4 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[10:11], v[22:23], a[64:79] + v_lshl_add_u32 v12, v4, 2, v34 + v_add_u32_e32 v0, v0, v12 + ds_read_b32 v4, v0 + v_xor_b32_e32 v13, v41, v57 + v_sub_u32_e32 v1, v13, v1 + v_lshlrev_b32_e32 v16, 2, v1 + v_add_u32_e32 v17, v0, v16 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[10:11], v[28:29], a[48:63] + ds_read_b32 v5, v17 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[4:5], v[14:15], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[4:5], v[18:19], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[4:5], v[22:23], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[4:5], v[28:29], a[240:255] + ds_read_b64 v[0:1], v48 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[76:77], v[0:1], a[224:239] + ds_read_b64 v[4:5], v50 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[76:77], v[4:5], a[208:223] + ds_read_b64 v[6:7], v51 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[76:77], v[6:7], a[192:207] + v_add_u32_e32 v3, v3, v49 + ds_read_b64 v[10:11], v3 offset:28672 + ds_read_b32 v14, v52 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[76:77], v[10:11], a[176:191] + ds_read_b32 v15, v54 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[14:15], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[14:15], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[14:15], v[6:7], a[128:143] + ds_read_b32 v18, v66 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[14:15], v[10:11], a[112:127] + ds_read_b32 v19, v68 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[18:19], v[0:1], a[96:111] + v_add3_u32 v3, v40, v38, v42 + v_add3_u32 v3, v45, v3, v44 + v_add3_u32 v3, v53, v3, v36 + v_add3_u32 v3, v3, v55, v58 + v_add3_u32 v3, v59, v3, v60 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[18:19], v[4:5], a[80:95] + v_add3_u32 v3, v62, v3, v64 + v_add3_u32 v3, v67, v3, v9 + v_add3_u32 v3, v3, v70, v24 + v_add3_u32 v3, v25, v3, v12 + v_xor_b32_e32 v9, v47, v69 + v_sub_u32_e32 v12, v9, v13 + v_lshl_add_u32 v8, v12, 2, v8 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[18:19], v[6:7], a[64:79] + v_add3_u32 v3, v16, v3, v8 + v_xor_b32_e32 v12, v30, v57 + v_sub_u32_e32 v9, v12, v9 + v_lshlrev_b32_e32 v9, 2, v9 + v_add3_u32 v3, v9, v33, v3 + ds_read_b32 v9, v3 + v_add_u32_e32 v3, v17, v8 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[18:19], v[10:11], a[48:63] + ds_read_b32 v8, v3 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[8:9], v[6:7], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[10:11], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB17_3 + s_branch .LBB17_10 +.LBB17_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr225 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB17_3: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v2 + v_and_b32_e32 v2, 15, v225 + s_lshr_b32 s23, s15, 2 + s_and_b32 s11, s23, 0x3ffffff0 + v_lshrrev_b32_e32 v1, 2, v225 + v_lshl_or_b32 v0, v2, 4, s20 + v_and_b32_e32 v83, 28, v1 + v_add_u32_e32 v1, s11, v83 + v_mad_u64_u32 v[18:19], s[18:19], v1, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v18 + buffer_load_dwordx4 v[14:17], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[22:25], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + s_mov_b32 s24, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s26, 0x5040100 + s_mov_b32 s27, 0x7060302 + s_mov_b32 s28, 0x7030602 + v_lshrrev_b32_e32 v8, 5, v225 + v_and_b32_e32 v84, 31, v225 + v_lshlrev_b32_e32 v0, 4, v225 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v85, 0x7c, v225 + s_lshr_b32 s19, s15, 1 + v_lshlrev_b32_e32 v3, 3, v225 + s_mov_b32 s15, s11 + s_and_b32 s23, s23, 0x3fffffe0 + v_lshlrev_b32_e32 v4, 12, v8 + v_lshlrev_b32_e32 v19, 3, v8 + v_and_b32_e32 v30, 48, v0 + v_add_u32_e32 v31, s18, v85 + v_and_or_b32 v0, s19, 32, v84 + v_and_or_b32 v32, v3, 8, v8 + v_or_b32_e32 v6, s23, v84 + v_lshl_or_b32 v9, v2, 7, v4 + v_add_u32_e32 v3, s21, v31 + v_lshrrev_b32_e32 v5, 1, v0 + v_bfe_u32 v4, v0, 1, 4 + v_lshrrev_b32_e32 v7, 4, v6 + v_mad_u64_u32 v[20:21], s[18:19], v3, s22, v[30:31] + v_xor_b32_e32 v3, v4, v32 + v_lshlrev_b32_e32 v5, 7, v5 + v_xor_b32_e32 v0, v2, v7 + v_add_u32_e32 v21, s22, v20 + buffer_load_dwordx4 v[36:39], v20, s[12:15], 0 offen + buffer_load_dwordx4 v[40:43], v21, s[12:15], 0 offen + v_add_u32_e32 v21, s22, v21 + v_add_u32_e32 v33, s22, v21 + buffer_load_dwordx4 v[44:47], v21, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v33, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v10, v10, s24 + v_perm_b32 v11, v11, v11, s24 + v_perm_b32 v12, v12, v12, s24 + v_perm_b32 v13, v13, v13, s24 + s_waitcnt vmcnt(6) + v_perm_b32 v14, v14, v14, s24 + v_perm_b32 v15, v15, v15, s24 + v_perm_b32 v16, v16, v16, s24 + v_perm_b32 v17, v17, v17, s24 + s_waitcnt vmcnt(5) + v_perm_b32 v21, v22, v22, s24 + v_perm_b32 v22, v23, v23, s24 + v_perm_b32 v23, v24, v24, s24 + v_perm_b32 v24, v25, v25, s24 + v_perm_b32 v25, v14, v10, s25 + v_perm_b32 v10, v14, v10, s28 + v_perm_b32 v14, v15, v11, s25 + v_perm_b32 v11, v15, v11, s28 + v_perm_b32 v15, v16, v12, s25 + s_waitcnt vmcnt(4) + v_perm_b32 v26, v26, v26, s24 + v_perm_b32 v27, v27, v27, s24 + v_perm_b32 v28, v28, v28, s24 + v_perm_b32 v29, v29, v29, s24 + v_perm_b32 v33, v26, v21, s25 + v_perm_b32 v21, v26, v21, s28 + v_perm_b32 v26, v27, v22, s25 + v_perm_b32 v22, v27, v22, s28 + v_perm_b32 v27, v28, v23, s25 + v_perm_b32 v34, v33, v25, s26 + v_perm_b32 v25, v33, v25, s27 + v_perm_b32 v33, v21, v10, s26 + v_perm_b32 v10, v21, v10, s27 + v_perm_b32 v21, v26, v14, s26 + v_perm_b32 v14, v26, v14, s27 + v_perm_b32 v26, v22, v11, s26 + v_perm_b32 v11, v22, v11, s27 + v_perm_b32 v22, v27, v15, s26 + v_perm_b32 v15, v27, v15, s27 + v_perm_b32 v12, v16, v12, s28 + v_perm_b32 v16, v28, v23, s28 + v_perm_b32 v23, v16, v12, s26 + v_perm_b32 v12, v16, v12, s27 + v_perm_b32 v16, v17, v13, s25 + v_perm_b32 v27, v29, v24, s25 + v_perm_b32 v28, v27, v16, s26 + v_perm_b32 v16, v27, v16, s27 + v_perm_b32 v13, v17, v13, s28 + v_perm_b32 v17, v29, v24, s28 + v_perm_b32 v24, v17, v13, s26 + v_perm_b32 v13, v17, v13, s27 + v_lshrrev_b32_e32 v17, 1, v1 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v27, v17, v84 + v_lshlrev_b32_e32 v29, 9, v1 + v_and_b32_e32 v29, 0x3000, v29 + v_lshlrev_b32_e32 v1, 6, v1 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v1, 0xfffff800, v1 + v_add_u32_e32 v1, v29, v1 + v_lshl_or_b32 v1, v27, 2, v1 + ds_write_b32 v1, v34 + v_or_b32_e32 v29, 1, v17 + v_xor_b32_e32 v29, v29, v84 + v_sub_u32_e32 v27, v29, v27 + v_lshl_add_u32 v1, v27, 2, v1 + ds_write_b32 v1, v25 offset:128 + v_or_b32_e32 v25, 2, v17 + v_xor_b32_e32 v25, v25, v84 + v_sub_u32_e32 v27, v25, v29 + s_movk_i32 s19, 0x80 + v_mov_b32_e32 v29, 0x80 + v_lshl_add_u32 v27, v27, 2, v29 + v_or_b32_e32 v34, 3, v17 + v_xor_b32_e32 v34, v34, v84 + v_sub_u32_e32 v25, v34, v25 + v_lshl_add_u32 v25, v25, 2, v29 + v_add3_u32 v35, v1, v27, v25 + v_add3_u32 v1, v1, s19, v27 + ds_write_b32 v1, v33 + v_add_u32_e32 v1, v25, v1 + ds_write_b32 v1, v10 + v_or_b32_e32 v10, 4, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v25, v10, v34 + v_lshl_add_u32 v25, v25, 2, v29 + v_or_b32_e32 v27, 5, v17 + v_xor_b32_e32 v27, v27, v84 + v_sub_u32_e32 v10, v27, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v33, v35, v25, v10 + v_add_u32_e32 v1, v25, v1 + ds_write_b32 v1, v21 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v14 + v_or_b32_e32 v10, 6, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v14, v10, v27 + v_lshl_add_u32 v14, v14, 2, v29 + v_or_b32_e32 v21, 7, v17 + v_xor_b32_e32 v21, v21, v84 + v_sub_u32_e32 v10, v21, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v25, v33, v14, v10 + v_add_u32_e32 v1, v14, v1 + ds_write_b32 v1, v26 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v11 + v_or_b32_e32 v10, 8, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v21 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v14, 9, v17 + v_xor_b32_e32 v14, v14, v84 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v21, v25, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v22 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v15 + v_or_b32_e32 v10, 10, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v14, 11, v17 + v_xor_b32_e32 v14, v14, v84 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v15, v21, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v23 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v12 + v_or_b32_e32 v10, 12, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v12, 13, v17 + v_xor_b32_e32 v12, v12, v84 + v_sub_u32_e32 v10, v12, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v14, v15, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v28 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v16 + v_or_b32_e32 v10, 14, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v12 + v_lshlrev_b32_e32 v11, 2, v11 + v_or_b32_e32 v12, 15, v17 + v_xor_b32_e32 v12, v12, v84 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v14, v11, v10 + v_add_u32_e32 v1, v1, v11 + ds_write_b32 v1, v24 offset:128 + ds_write_b32 v10, v13 offset:384 + v_lshrrev_b32_e32 v86, 3, v30 + v_ashrrev_i32_e32 v1, 1, v31 + v_ashrrev_i32_e32 v10, 31, v31 + v_lshrrev_b32_e32 v10, 28, v10 + v_add_u32_e32 v11, v1, v10 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v1, v11 + v_xor_b32_e32 v12, v11, v86 + v_lshlrev_b32_e32 v13, 6, v31 + v_lshl_add_u32 v12, v12, 3, v13 + s_waitcnt vmcnt(3) + ds_write_b64 v12, v[36:37] offset:16384 + v_or_b32_e32 v87, 1, v86 + v_xor_b32_e32 v11, v11, v87 + v_lshl_add_u32 v12, v11, 3, v13 + ds_write_b64 v12, v[38:39] offset:16384 + v_or_b32_e32 v13, 1, v31 + v_sub_u32_e32 v88, v86, v87 + v_lshrrev_b32_e32 v14, 31, v31 + v_add_u32_e32 v15, v13, v14 + v_ashrrev_i32_e32 v16, 1, v15 + v_sub_u32_e32 v17, v16, v1 + v_and_b32_e32 v21, 0x1ffffffe, v15 + v_sub_u32_e32 v13, v13, v21 + v_lshl_or_b32 v13, v13, 3, v87 + v_add_u32_e32 v21, v13, v88 + v_ashrrev_i32_e32 v15, 31, v15 + v_lshrrev_b32_e32 v15, 28, v15 + v_add_u32_e32 v15, v16, v15 + v_and_b32_e32 v15, -16, v15 + v_sub_u32_e32 v15, v16, v15 + v_xor_b32_e32 v21, v21, v15 + v_sub_u32_e32 v21, v21, v11 + v_lshl_add_u32 v12, v17, 7, v12 + v_lshl_add_u32 v17, v21, 3, v12 + s_waitcnt vmcnt(2) + ds_write_b64 v17, v[40:41] offset:16384 + v_xor_b32_e32 v13, v13, v15 + v_sub_u32_e32 v11, v13, v11 + v_lshl_add_u32 v11, v11, 3, v12 + ds_write_b64 v11, v[42:43] offset:16384 + v_or_b32_e32 v1, 1, v1 + v_sub_u32_e32 v12, v1, v16 + v_add_u32_e32 v10, v1, v10 + v_and_b32_e32 v10, -16, v10 + v_sub_u32_e32 v10, v1, v10 + v_xor_b32_e32 v15, v10, v86 + v_sub_u32_e32 v13, v15, v13 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshlrev_b32_e32 v12, 7, v12 + v_add3_u32 v11, v13, v12, v11 + s_waitcnt vmcnt(1) + ds_write_b64 v11, v[44:45] offset:16384 + v_xor_b32_e32 v10, v10, v87 + v_sub_u32_e32 v12, v10, v15 + v_lshl_add_u32 v11, v12, 3, v11 + ds_write_b64 v11, v[46:47] offset:16384 + v_or_b32_e32 v12, 3, v31 + v_add_u32_e32 v13, v12, v14 + v_ashrrev_i32_e32 v14, 1, v13 + v_sub_u32_e32 v1, v14, v1 + v_and_b32_e32 v15, 0x1ffffffe, v13 + v_sub_u32_e32 v12, v12, v15 + v_lshl_or_b32 v12, v12, 3, v87 + v_add_u32_e32 v15, v12, v88 + v_ashrrev_i32_e32 v13, 31, v13 + v_lshrrev_b32_e32 v13, 28, v13 + v_add_u32_e32 v13, v14, v13 + v_and_b32_e32 v13, -16, v13 + v_sub_u32_e32 v13, v14, v13 + v_xor_b32_e32 v14, v15, v13 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v1, v10, v1, v11 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[48:49] offset:16384 + v_xor_b32_e32 v10, v12, v13 + v_sub_u32_e32 v10, v10, v14 + v_lshl_add_u32 v1, v10, 3, v1 + ds_write_b64 v1, v[50:51] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v14, 3, v19 + v_add_u32_e32 v15, 16, v7 + v_add_u32_e32 v24, 16, v19 + v_add_u32_e32 v23, 20, v19 + v_or_b32_e32 v13, 16, v2 + v_add_u32_e32 v22, 36, v19 + v_add_u32_e32 v21, 48, v19 + v_add_u32_e32 v17, 52, v19 + v_add_u32_e32 v16, 64, v6 + v_add_u32_e32 v12, 2, v32 + v_add_u32_e32 v11, 4, v32 + v_add_u32_e32 v10, 6, v32 + s_cbranch_vccnz .LBB17_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit968.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v2, v15 + v_sub_u32_e32 v19, v14, v8 + v_lshlrev_b32_e32 v19, 12, v19 + v_lshlrev_b32_e32 v25, 2, v1 + v_add3_u32 v69, v25, v9, v19 + v_lshrrev_b32_e32 v19, 5, v24 + v_lshrrev_b16_e32 v25, 3, v24 + v_and_b32_e32 v25, 3, v25 + v_sub_u16_e32 v26, v25, v14 + v_bfe_i32 v26, v26, 0, 16 + v_lshl_or_b32 v27, v19, 4, v2 + v_xor_b32_e32 v28, v27, v7 + v_sub_u32_e32 v1, v28, v1 + v_lshlrev_b32_e32 v29, 11, v19 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_or_b32 v26, v26, 12, v29 + v_add3_u32 v41, v26, v69, v1 + v_lshrrev_b32_e32 v1, 5, v23 + v_sub_u32_e32 v19, v1, v19 + v_lshrrev_b16_e32 v29, 3, v23 + v_and_b32_e32 v29, 3, v29 + v_sub_u16_e32 v25, v29, v25 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v30, v1, 4, v2 + v_xor_b32_e32 v31, v30, v15 + v_sub_u32_e32 v28, v31, v28 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_add_u32 v25, v25, 12, v19 + v_add3_u32 v42, v28, v25, v41 + v_sub_u16_e32 v19, v14, v29 + v_bfe_i32 v19, v19, 0, 16 + v_xor_b32_e32 v28, v13, v7 + v_sub_u32_e32 v29, v28, v31 + v_lshlrev_b32_e32 v1, 11, v1 + v_xor_b32_e32 v1, 0x800, v1 + v_lshlrev_b32_e32 v29, 2, v29 + v_lshl_or_b32 v1, v19, 12, v1 + v_add3_u32 v36, v29, v1, v42 + v_lshrrev_b32_e32 v19, 5, v22 + v_lshlrev_b32_e32 v29, 11, v19 + v_lshrrev_b16_e32 v31, 3, v22 + v_and_b32_e32 v31, 3, v31 + v_sub_u16_e32 v32, v31, v14 + v_lshl_or_b32 v33, v19, 4, v2 + v_and_b32_e32 v33, 31, v33 + v_xor_b32_e32 v34, v33, v15 + v_sub_u32_e32 v28, v34, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_mov_b32_e32 v35, 12 + v_lshlrev_b32_sdwa v32, v35, sext(v32) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v29, v29, v32, s18 + v_add3_u32 v38, v28, v29, v36 + v_lshrrev_b32_e32 v28, 5, v21 + v_sub_u32_e32 v19, v28, v19 + v_lshrrev_b16_e32 v32, 3, v21 + v_and_b32_e32 v32, 3, v32 + v_sub_u16_e32 v31, v32, v31 + v_bfe_i32 v31, v31, 0, 16 + v_lshl_or_b32 v37, v28, 4, v2 + v_and_b32_e32 v45, 31, v37 + v_xor_b32_e32 v37, v45, v7 + v_sub_u32_e32 v34, v37, v34 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v34, 2, v34 + v_lshl_add_u32 v31, v31, 12, v19 + v_add3_u32 v19, v34, v31, v38 + v_lshrrev_b32_e32 v34, 5, v17 + v_sub_u32_e32 v28, v34, v28 + v_lshrrev_b16_e32 v39, 3, v17 + v_and_b32_e32 v39, 3, v39 + v_sub_u16_e32 v32, v39, v32 + v_bfe_i32 v32, v32, 0, 16 + v_lshl_or_b32 v40, v34, 4, v2 + v_and_b32_e32 v53, 31, v40 + v_xor_b32_e32 v40, v53, v15 + v_sub_u32_e32 v37, v40, v37 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v37, 2, v37 + v_lshl_add_u32 v28, v32, 12, v28 + v_add3_u32 v37, v37, v28, v19 + v_lshrrev_b32_e32 v32, 4, v16 + v_sub_u16_e32 v39, v14, v39 + v_xor_b32_e32 v43, v2, v32 + v_sub_u32_e32 v40, v43, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_lshlrev_b32_sdwa v35, v35, sext(v39) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v34, 11, v34 + v_sub_u32_e32 v34, v35, v34 + v_add3_u32 v72, v40, v34, v37 + v_add_u32_e32 v35, 16, v32 + v_xor_b32_e32 v39, v2, v35 + v_sub_u32_e32 v40, v39, v43 + v_lshl_add_u32 v73, v40, 2, v72 + v_xor_b32_e32 v40, v27, v32 + v_sub_u32_e32 v39, v40, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v49, v39, v26, v73 + v_xor_b32_e32 v39, v30, v35 + v_sub_u32_e32 v40, v39, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_add3_u32 v50, v40, v25, v49 + v_xor_b32_e32 v40, v13, v32 + v_sub_u32_e32 v39, v40, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v47, v39, v1, v50 + v_xor_b32_e32 v39, v33, v35 + v_sub_u32_e32 v40, v39, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_add3_u32 v48, v40, v29, v47 + v_xor_b32_e32 v32, v45, v32 + v_sub_u32_e32 v39, v32, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v39, v39, v31, v48 + v_xor_b32_e32 v35, v53, v35 + v_sub_u32_e32 v32, v35, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v40, v32, v28, v39 + v_add_u32_e32 v32, 0x80, v6 + v_lshrrev_b32_e32 v32, 4, v32 + v_xor_b32_e32 v43, v2, v32 + v_sub_u32_e32 v35, v43, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v74, v35, v34, v40 + v_add_u32_e32 v35, 16, v32 + v_xor_b32_e32 v44, v2, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshl_add_u32 v75, v43, 2, v74 + v_xor_b32_e32 v43, v27, v32 + v_sub_u32_e32 v44, v43, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v54, v44, v26, v75 + v_xor_b32_e32 v44, v30, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v55, v43, v25, v54 + v_xor_b32_e32 v43, v13, v32 + v_sub_u32_e32 v44, v43, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v51, v44, v1, v55 + v_xor_b32_e32 v44, v33, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v52, v43, v29, v51 + v_xor_b32_e32 v32, v45, v32 + v_sub_u32_e32 v43, v32, v44 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v43, v43, v31, v52 + v_xor_b32_e32 v35, v53, v35 + v_sub_u32_e32 v32, v35, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v44, v32, v28, v43 + v_add_u32_e32 v32, 0xc0, v6 + v_lshrrev_b32_e32 v32, 4, v32 + v_xor_b32_e32 v46, v2, v32 + v_sub_u32_e32 v35, v46, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v76, v35, v34, v44 + v_add_u32_e32 v34, 16, v32 + v_xor_b32_e32 v35, v2, v34 + v_sub_u32_e32 v46, v35, v46 + v_lshl_add_u32 v77, v46, 2, v76 + v_xor_b32_e32 v27, v27, v32 + v_sub_u32_e32 v35, v27, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v62, v35, v26, v77 + v_xor_b32_e32 v26, v30, v34 + v_sub_u32_e32 v27, v26, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v63, v27, v25, v62 + v_xor_b32_e32 v25, v13, v32 + v_sub_u32_e32 v26, v25, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v56, v26, v1, v63 + v_xor_b32_e32 v1, v33, v34 + v_sub_u32_e32 v25, v1, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v59, v25, v29, v56 + v_xor_b32_e32 v25, v45, v32 + v_sub_u32_e32 v1, v25, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v46, v1, v31, v59 + v_xor_b32_e32 v1, v53, v34 + v_sub_u32_e32 v1, v1, v25 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v45, v1, v28, v46 + v_xor_b32_e32 v1, v4, v12 + v_lshl_add_u32 v67, v1, 3, v5 + v_xor_b32_e32 v25, v4, v11 + v_lshl_add_u32 v61, v25, 3, v5 + v_xor_b32_e32 v26, v4, v10 + v_lshl_add_u32 v53, v26, 3, v5 + v_sub_u32_e32 v27, v3, v26 + v_mov_b32_e32 v28, 0x1000 + v_lshl_add_u32 v27, v27, 3, v28 + v_add_u32_e32 v80, v27, v53 + v_sub_u32_e32 v1, v1, v3 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v68, v80, v1 + v_sub_u32_e32 v25, v25, v3 + v_lshlrev_b32_e32 v25, 3, v25 + v_add_u32_e32 v64, v80, v25 + v_sub_u32_e32 v26, v26, v3 + v_lshlrev_b32_e32 v26, 3, v26 + v_add_u32_e32 v57, v80, v26 + v_add_u32_e32 v81, v57, v27 + v_add_u32_e32 v70, v81, v1 + v_add_u32_e32 v65, v81, v25 + v_add_u32_e32 v58, v81, v26 + v_add_u32_e32 v82, v58, v27 + v_add_u32_e32 v71, v82, v1 + v_add_u32_e32 v66, v82, v25 + v_add_u32_e32 v60, v82, v26 + s_mov_b64 s[2:3], 0 + s_branch .LBB17_6 +.LBB17_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr60 +.LBB17_6: ; %Flow98 + v_lshl_add_u32 v79, v0, 2, v9 + v_lshl_or_b32 v78, v3, 3, v5 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB17_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_xor_b32_e32 v0, v2, v15 + v_sub_u32_e32 v1, v14, v8 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v8, 2, v0 + v_add3_u32 v69, v8, v9, v1 + v_lshrrev_b32_e32 v1, 5, v24 + v_lshrrev_b16_e32 v8, 3, v24 + v_and_b32_e32 v8, 3, v8 + v_sub_u16_e32 v9, v8, v14 + v_bfe_i32 v9, v9, 0, 16 + v_lshl_or_b32 v24, v1, 4, v2 + v_xor_b32_e32 v19, v24, v7 + v_sub_u32_e32 v0, v19, v0 + v_lshlrev_b32_e32 v25, 11, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v9, v9, 12, v25 + v_add3_u32 v41, v9, v69, v0 + v_lshrrev_b32_e32 v0, 5, v23 + v_sub_u32_e32 v1, v0, v1 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v8, v23, v8 + v_bfe_i32 v8, v8, 0, 16 + v_lshl_or_b32 v25, v0, 4, v2 + v_xor_b32_e32 v26, v25, v15 + v_sub_u32_e32 v19, v26, v19 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_add_u32 v1, v8, 12, v1 + v_add3_u32 v42, v19, v1, v41 + v_sub_u16_e32 v8, v14, v23 + v_bfe_i32 v8, v8, 0, 16 + v_xor_b32_e32 v19, v13, v7 + v_sub_u32_e32 v23, v19, v26 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_or_b32 v0, v8, 12, v0 + v_add3_u32 v36, v23, v0, v42 + v_lshrrev_b32_e32 v8, 5, v22 + v_lshlrev_b32_e32 v23, 11, v8 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v26, v22, v14 + v_lshl_or_b32 v27, v8, 4, v2 + v_and_b32_e32 v27, 31, v27 + v_xor_b32_e32 v28, v27, v15 + v_sub_u32_e32 v19, v28, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_mov_b32_e32 v29, 12 + v_lshlrev_b32_sdwa v26, v29, sext(v26) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v23, v23, v26, s6 + v_add3_u32 v38, v19, v23, v36 + v_lshrrev_b32_e32 v26, 5, v21 + v_sub_u32_e32 v8, v26, v8 + v_lshrrev_b16_e32 v19, 3, v21 + v_and_b32_e32 v21, 3, v19 + v_sub_u16_e32 v19, v21, v22 + v_bfe_i32 v19, v19, 0, 16 + v_lshl_or_b32 v22, v26, 4, v2 + v_and_b32_e32 v22, 31, v22 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v28, v7, v28 + v_lshlrev_b32_e32 v8, 11, v8 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_add_u32 v8, v19, 12, v8 + v_add3_u32 v19, v28, v8, v38 + v_lshrrev_b32_e32 v28, 5, v17 + v_sub_u32_e32 v26, v28, v26 + v_lshrrev_b16_e32 v17, 3, v17 + v_and_b32_e32 v17, 3, v17 + v_sub_u16_e32 v21, v17, v21 + v_bfe_i32 v21, v21, 0, 16 + v_lshl_or_b32 v30, v28, 4, v2 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v26, 11, v26 + v_lshlrev_b32_e32 v7, 2, v7 + v_lshl_add_u32 v21, v21, 12, v26 + v_add3_u32 v37, v7, v21, v19 + v_lshrrev_b32_e32 v7, 4, v16 + v_sub_u16_e32 v14, v14, v17 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_lshlrev_b32_sdwa v14, v29, sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v17, 11, v28 + v_sub_u32_e32 v14, v14, v17 + v_add3_u32 v72, v15, v14, v37 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v73, v16, 2, v72 + v_xor_b32_e32 v16, v24, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v49, v17, v9, v73 + v_xor_b32_e32 v17, v25, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v50, v16, v1, v49 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v47, v17, v0, v50 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v48, v16, v23, v47 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v39, v16, v8, v48 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v40, v7, v21, v39 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v7, 0x80, v6 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v74, v15, v14, v40 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v75, v16, 2, v74 + v_xor_b32_e32 v16, v24, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v54, v17, v9, v75 + v_xor_b32_e32 v17, v25, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v55, v16, v1, v54 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v51, v17, v0, v55 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v52, v16, v23, v51 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v43, v16, v8, v52 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v44, v7, v21, v43 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 4, v6 + v_xor_b32_e32 v7, v2, v6 + v_sub_u32_e32 v15, v7, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v76, v15, v14, v44 + v_add_u32_e32 v14, 16, v6 + v_xor_b32_e32 v2, v2, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshl_add_u32 v77, v7, 2, v76 + v_xor_b32_e32 v7, v24, v6 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v62, v2, v9, v77 + v_xor_b32_e32 v2, v25, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v63, v7, v1, v62 + v_xor_b32_e32 v1, v13, v6 + v_sub_u32_e32 v2, v1, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v56, v2, v0, v63 + v_xor_b32_e32 v0, v27, v14 + v_sub_u32_e32 v1, v0, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v59, v1, v23, v56 + v_xor_b32_e32 v1, v22, v6 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v46, v0, v8, v59 + v_xor_b32_e32 v0, v30, v14 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v45, v0, v21, v46 + v_xor_b32_e32 v0, v4, v12 + v_lshl_add_u32 v67, v0, 3, v5 + v_xor_b32_e32 v1, v4, v11 + v_lshl_add_u32 v61, v1, 3, v5 + v_xor_b32_e32 v2, v4, v10 + v_lshl_add_u32 v53, v2, 3, v5 + v_sub_u32_e32 v4, v3, v2 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v5, 0x1000, v4 + v_add_u32_e32 v80, v5, v53 + v_add_u32_e32 v89, v4, v53 + v_sub_u32_e32 v0, v0, v3 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v68, v80, v0 + v_add_u32_e32 v90, v89, v0 + v_sub_u32_e32 v1, v1, v3 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v64, v80, v1 + v_add_u32_e32 v91, v89, v1 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v57, v80, v2 + v_add_u32_e32 v92, v89, v2 + v_add_u32_e32 v81, v57, v5 + v_add_u32_e32 v93, v92, v5 + v_add_u32_e32 v70, v81, v0 + v_add_u32_e32 v65, v81, v1 + v_add_u32_e32 v58, v81, v2 + v_add_u32_e32 v82, v58, v5 + v_add_u32_e32 v71, v82, v0 + v_add_u32_e32 v66, v82, v1 + v_add_u32_e32 v60, v82, v2 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_mov_b32_e32 v94, 0x80 +.LBB17_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v0, 64, v20 + v_add_u32_e32 v18, s2, v18 + buffer_load_dwordx4 v[100:103], v20, s[12:15], 0 offen offset:64 + v_add_u32_e32 v1, s7, v18 + v_add_u32_e32 v2, s22, v0 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + buffer_load_dwordx4 v[6:9], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[104:107], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[108:111], v2, s[12:15], 0 offen + v_add_u32_e32 v20, s22, v2 + buffer_load_dwordx4 v[14:17], v1, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v3, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[112:115], v20, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v35, v69 + ds_read_b32 v34, v79 + ds_read_b64 v[28:29], v78 offset:16384 + ds_read_b64 v[26:27], v89 offset:20480 + ds_read_b64 v[20:21], v90 offset:20480 + ds_read_b64 v[24:25], v93 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[34:35], v[28:29], a[64:79] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[34:35], v[26:27], a[80:95] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[34:35], v[24:25], a[96:111] + ds_read_b64 v[30:31], v81 offset:20480 + ds_read_b32 v96, v72 + ds_read_b64 v[32:33], v70 offset:20480 + ds_read_b64 v[22:23], v65 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[34:35], v[30:31], a[112:127] + ds_read_b32 v97, v73 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[96:97], v[28:29], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[96:97], v[26:27], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[96:97], v[24:25], a[160:175] + ds_read_b32 v34, v74 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[96:97], v[30:31], a[176:191] + ds_read_b32 v35, v75 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[34:35], v[28:29], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[34:35], v[26:27], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[34:35], v[24:25], a[224:239] + ds_read_b32 v96, v76 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[34:35], v[30:31], a[240:255] + ds_read_b32 v97, v77 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[96:97], v[28:29], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[96:97], v[26:27], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[96:97], v[24:25], a[0:15] + ds_read_b32 v34, v41 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[96:97], v[30:31], a[48:63] + ds_read_b32 v35, v42 + ds_read_b64 v[24:25], v67 offset:16384 + ds_read_b32 v96, v36 + ds_read_b32 v97, v38 + ds_read_b32 v122, v19 + ds_read_b32 v123, v37 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[34:35], v[24:25], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[34:35], v[20:21], a[80:95] + ds_read_b64 v[28:29], v68 offset:20480 + ds_read_b64 v[26:27], v64 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[34:35], v[28:29], a[96:111] + ds_read_b32 v30, v49 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[34:35], v[32:33], a[112:127] + ds_read_b32 v31, v50 + ds_read_b32 v34, v47 + ds_read_b32 v35, v48 + ds_read_b32 v120, v39 + ds_read_b32 v121, v40 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[30:31], v[24:25], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[30:31], v[20:21], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[30:31], v[28:29], a[160:175] + ds_read_b32 v98, v54 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[30:31], v[32:33], a[176:191] + ds_read_b32 v99, v55 + ds_read_b32 v126, v51 + ds_read_b32 v127, v52 + ds_read_b32 v118, v43 + ds_read_b32 v119, v44 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[98:99], v[24:25], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[98:99], v[20:21], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[98:99], v[28:29], a[224:239] + ds_read_b32 v30, v62 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[98:99], v[32:33], a[240:255] + ds_read_b32 v31, v63 + ds_read_b32 v124, v56 + ds_read_b32 v125, v59 + ds_read_b32 v116, v46 + ds_read_b32 v117, v45 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[30:31], v[24:25], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[30:31], v[20:21], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[30:31], v[28:29], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[30:31], v[32:33], a[48:63] + ds_read_b64 v[30:31], v61 offset:16384 + ds_read_b64 v[24:25], v53 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[96:97], v[30:31], a[64:79] + ds_read_b64 v[28:29], v91 offset:20480 + ds_read_b64 v[32:33], v92 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[96:97], v[28:29], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[96:97], v[26:27], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[96:97], v[22:23], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[34:35], v[30:31], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[34:35], v[28:29], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[34:35], v[26:27], a[160:175] + s_add_i32 s26, s3, -1 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[34:35], v[22:23], a[176:191] + v_readfirstlane_b32 s27, v227 + s_lshr_b32 s28, s27, 2 + s_andn2_b32 s27, s27, 63 + s_and_b32 s28, s28, 0x3ffffff0 + v_add_u32_e32 v1, s27, v85 + v_mov_b32_e32 v20, v0 + v_add_u32_e32 v97, s28, v83 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[126:127], v[30:31], a[192:207] + v_ashrrev_i32_e32 v21, 1, v1 + v_ashrrev_i32_e32 v98, 31, v1 + v_lshlrev_b32_e32 v0, 6, v1 + v_or_b32_e32 v96, 1, v1 + v_lshrrev_b32_e32 v99, 31, v1 + v_or_b32_e32 v95, 3, v1 + s_cmp_gt_u32 s3, 2 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[126:127], v[28:29], a[208:223] + s_mov_b32 s3, s26 + ds_read_b64 v[34:35], v57 offset:20480 + ds_read_b64 v[128:129], v58 offset:20480 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v1, 1, v97 + v_lshlrev_b32_e32 v130, 9, v97 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[126:127], v[26:27], a[224:239] + v_lshlrev_b32_e32 v97, 6, v97 + v_lshrrev_b32_e32 v98, 28, v98 + v_add_u32_e32 v131, v96, v99 + v_or_b32_e32 v132, 1, v21 + v_add_u32_e32 v99, v95, v99 + v_and_b32_e32 v1, 16, v1 + v_and_b32_e32 v130, 0x3000, v130 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[126:127], v[22:23], a[240:255] + v_and_b32_e32 v97, 0xfffff800, v97 + v_add_u32_e32 v126, v21, v98 + v_ashrrev_i32_e32 v127, 1, v131 + v_and_b32_e32 v133, 0x1ffffffe, v131 + v_ashrrev_i32_e32 v131, 31, v131 + v_add_u32_e32 v98, v132, v98 + v_ashrrev_i32_e32 v134, 1, v99 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[124:125], v[30:31], a[16:31] + v_and_b32_e32 v30, 0x1ffffffe, v99 + v_ashrrev_i32_e32 v31, 31, v99 + v_xor_b32_e32 v99, v1, v84 + v_add_u32_e32 v97, v130, v97 + v_or_b32_e32 v130, 1, v1 + v_or_b32_e32 v135, 2, v1 + v_or_b32_e32 v136, 3, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[124:125], v[28:29], a[32:47] + v_or_b32_e32 v28, 4, v1 + v_or_b32_e32 v29, 5, v1 + v_or_b32_e32 v137, 6, v1 + v_or_b32_e32 v138, 7, v1 + v_or_b32_e32 v139, 8, v1 + v_or_b32_e32 v140, 9, v1 + v_or_b32_e32 v141, 10, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[124:125], v[26:27], a[0:15] + v_or_b32_e32 v26, 11, v1 + v_or_b32_e32 v27, 12, v1 + v_or_b32_e32 v142, 13, v1 + v_or_b32_e32 v143, 14, v1 + v_or_b32_e32 v1, 15, v1 + v_and_b32_e32 v126, -16, v126 + v_sub_u32_e32 v144, v127, v21 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[124:125], v[22:23], a[48:63] + v_sub_u32_e32 v22, v96, v133 + v_lshrrev_b32_e32 v23, 28, v131 + v_sub_u32_e32 v96, v132, v127 + v_and_b32_e32 v98, -16, v98 + v_sub_u32_e32 v124, v134, v132 + v_sub_u32_e32 v30, v95, v30 + v_lshrrev_b32_e32 v31, 28, v31 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[122:123], v[24:25], a[64:79] + v_lshl_or_b32 v95, v99, 2, v97 + v_xor_b32_e32 v97, v130, v84 + v_xor_b32_e32 v125, v135, v84 + v_xor_b32_e32 v130, v136, v84 + v_xor_b32_e32 v28, v28, v84 + v_xor_b32_e32 v29, v29, v84 + v_xor_b32_e32 v131, v137, v84 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[122:123], v[32:33], a[80:95] + v_xor_b32_e32 v133, v138, v84 + v_xor_b32_e32 v135, v139, v84 + v_xor_b32_e32 v136, v140, v84 + v_xor_b32_e32 v137, v141, v84 + v_xor_b32_e32 v26, v26, v84 + v_xor_b32_e32 v27, v27, v84 + v_xor_b32_e32 v138, v142, v84 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[122:123], v[34:35], a[96:111] + v_xor_b32_e32 v139, v143, v84 + v_xor_b32_e32 v1, v1, v84 + v_sub_u32_e32 v21, v21, v126 + v_lshl_or_b32 v22, v22, 3, v87 + v_add_u32_e32 v23, v127, v23 + v_sub_u32_e32 v98, v132, v98 + v_lshlrev_b32_e32 v96, 7, v96 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[122:123], v[128:129], a[112:127] + v_lshl_or_b32 v30, v30, 3, v87 + v_add_u32_e32 v31, v134, v31 + v_lshlrev_b32_e32 v122, 7, v124 + v_sub_u32_e32 v99, v97, v99 + v_sub_u32_e32 v97, v125, v97 + v_sub_u32_e32 v123, v130, v125 + v_sub_u32_e32 v124, v28, v130 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[120:121], v[24:25], a[128:143] + v_sub_u32_e32 v28, v29, v28 + v_sub_u32_e32 v29, v131, v29 + v_sub_u32_e32 v125, v133, v131 + v_sub_u32_e32 v126, v135, v133 + v_sub_u32_e32 v130, v136, v135 + v_sub_u32_e32 v131, v137, v136 + v_sub_u32_e32 v132, v26, v137 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[120:121], v[32:33], a[144:159] + v_sub_u32_e32 v26, v27, v26 + v_sub_u32_e32 v27, v138, v27 + v_sub_u32_e32 v133, v139, v138 + v_sub_u32_e32 v1, v1, v139 + v_xor_b32_e32 v135, v21, v86 + v_xor_b32_e32 v21, v21, v87 + v_add_u32_e32 v136, v22, v88 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[120:121], v[34:35], a[160:175] + v_and_b32_e32 v23, -16, v23 + v_xor_b32_e32 v137, v98, v86 + v_xor_b32_e32 v98, v98, v87 + v_add_u32_e32 v138, v30, v88 + v_and_b32_e32 v31, -16, v31 + v_lshl_add_u32 v99, v99, 2, v95 + v_lshl_add_u32 v97, v97, 2, v94 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[120:121], v[128:129], a[176:191] + v_lshl_add_u32 v120, v123, 2, v94 + v_lshl_add_u32 v121, v124, 2, v94 + v_lshl_add_u32 v28, v28, 2, v94 + v_lshl_add_u32 v29, v29, 2, v94 + v_lshl_add_u32 v123, v125, 2, v94 + v_lshl_add_u32 v124, v126, 2, v94 + v_lshl_add_u32 v125, v130, 2, v94 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[118:119], v[24:25], a[192:207] + v_lshl_add_u32 v126, v131, 2, v94 + v_lshl_add_u32 v130, v132, 2, v94 + v_lshl_add_u32 v26, v26, 2, v94 + v_lshl_add_u32 v27, v27, 2, v94 + v_lshlrev_b32_e32 v131, 2, v133 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_add_u32 v132, v135, 3, v0 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[118:119], v[32:33], a[208:223] + v_lshl_add_u32 v0, v21, 3, v0 + v_sub_u32_e32 v23, v127, v23 + v_sub_u32_e32 v127, v98, v137 + v_sub_u32_e32 v31, v134, v31 + v_add3_u32 v133, v99, v97, v120 + v_add3_u32 v97, v99, s6, v97 + v_xor_b32_e32 v134, v136, v23 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[118:119], v[34:35], a[224:239] + v_lshl_add_u32 v135, v144, 7, v0 + v_xor_b32_e32 v22, v22, v23 + v_xor_b32_e32 v23, v138, v31 + v_xor_b32_e32 v30, v30, v31 + v_add_u32_e32 v31, v120, v97 + v_add3_u32 v120, v133, v121, v28 + v_sub_u32_e32 v133, v134, v21 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[118:119], v[128:129], a[240:255] + v_sub_u32_e32 v21, v22, v21 + v_sub_u32_e32 v22, v137, v22 + v_sub_u32_e32 v98, v23, v98 + v_sub_u32_e32 v23, v30, v23 + v_add_u32_e32 v30, v121, v31 + v_add3_u32 v118, v120, v29, v123 + v_lshl_add_u32 v119, v133, 3, v135 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[116:117], v[24:25], a[16:31] + v_lshl_add_u32 v21, v21, 3, v135 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshlrev_b32_e32 v24, 3, v98 + v_add_u32_e32 v25, v28, v30 + v_add3_u32 v28, v118, v124, v125 + v_add3_u32 v22, v22, v96, v21 + v_add_u32_e32 v29, v29, v25 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[116:117], v[32:33], a[32:47] + v_add3_u32 v28, v28, v126, v130 + v_lshl_add_u32 v32, v127, 3, v22 + v_add_u32_e32 v33, v123, v29 + v_add3_u32 v28, v28, v26, v27 + v_add3_u32 v24, v24, v122, v32 + v_add_u32_e32 v96, v124, v33 + v_add3_u32 v1, v28, v131, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[116:117], v[34:35], a[0:15] + v_lshl_add_u32 v23, v23, 3, v24 + v_add_u32_e32 v28, v125, v96 + v_add_u32_e32 v34, v126, v28 + v_add_u32_e32 v35, v130, v34 + v_add_u32_e32 v26, v26, v35 + v_add_u32_e32 v27, v27, v26 + v_add_u32_e32 v98, v27, v131 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[116:117], v[128:129], a[48:63] + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + s_waitcnt vmcnt(5) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v14, v14, v14, s18 + v_perm_b32 v15, v15, v15, s18 + v_perm_b32 v16, v16, v16, s18 + v_perm_b32 v17, v17, v17, s18 + v_perm_b32 v116, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + s_waitcnt vmcnt(1) + v_perm_b32 v2, v2, v2, s18 + v_perm_b32 v3, v3, v3, s18 + v_perm_b32 v4, v4, v4, s18 + v_perm_b32 v5, v5, v5, s18 + v_perm_b32 v13, v2, v14, s19 + v_perm_b32 v2, v2, v14, s25 + v_perm_b32 v14, v3, v15, s19 + v_perm_b32 v3, v3, v15, s25 + v_perm_b32 v15, v4, v16, s19 + v_perm_b32 v4, v4, v16, s25 + v_perm_b32 v16, v5, v17, s19 + v_perm_b32 v5, v5, v17, s25 + v_perm_b32 v17, v13, v116, s23 + v_perm_b32 v13, v13, v116, s24 + v_perm_b32 v116, v2, v6, s23 + v_perm_b32 v2, v2, v6, s24 + v_perm_b32 v6, v14, v10, s23 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v3, v7, s23 + v_perm_b32 v3, v3, v7, s24 + v_perm_b32 v7, v15, v11, s23 + v_perm_b32 v11, v15, v11, s24 + v_perm_b32 v15, v4, v8, s23 + v_perm_b32 v4, v4, v8, s24 + v_perm_b32 v8, v16, v12, s23 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v5, v9, s23 + v_perm_b32 v5, v5, v9, s24 + ds_write_b32 v95, v17 + ds_write_b32 v99, v13 offset:128 + ds_write_b32 v97, v116 + ds_write_b32 v31, v2 + ds_write_b32 v30, v6 + ds_write_b32 v25, v10 + ds_write_b32 v29, v14 + ds_write_b32 v33, v3 + ds_write_b32 v96, v7 + ds_write_b32 v28, v11 + ds_write_b32 v34, v15 + ds_write_b32 v35, v4 + ds_write_b32 v26, v8 + ds_write_b32 v27, v12 + ds_write_b32 v98, v16 offset:128 + ds_write_b32 v1, v5 offset:384 + ds_write_b64 v132, v[100:101] offset:16384 + ds_write_b64 v0, v[102:103] offset:16384 + ds_write_b64 v119, v[104:105] offset:16384 + ds_write_b64 v21, v[106:107] offset:16384 + ds_write_b64 v22, v[108:109] offset:16384 + ds_write_b64 v32, v[110:111] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v24, v[112:113] offset:16384 + ds_write_b64 v23, v[114:115] offset:16384 + s_cbranch_scc1 .LBB17_8 +.LBB17_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESC_NSB_8RowMajorELi1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEENSL_IJNSM_IS1D_NSL_IJS1G_S1F_EEEEEEEESG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1O_T0_EE5valueEbE4typeE + v_accvgpr_read_b32 v20, a160 + v_accvgpr_read_b32 v21, a161 + v_accvgpr_read_b32 v22, a162 + v_accvgpr_read_b32 v23, a163 + v_accvgpr_read_b32 v24, a164 + v_accvgpr_read_b32 v25, a165 + v_accvgpr_read_b32 v26, a166 + v_accvgpr_read_b32 v27, a167 + v_accvgpr_read_b32 v28, a168 + v_accvgpr_read_b32 v29, a169 + v_accvgpr_read_b32 v30, a170 + v_accvgpr_read_b32 v31, a171 + v_accvgpr_read_b32 v32, a172 + v_accvgpr_read_b32 v33, a173 + v_accvgpr_read_b32 v34, a174 + v_accvgpr_read_b32 v35, a175 + v_accvgpr_read_b32 v84, a176 + v_accvgpr_read_b32 v85, a177 + v_accvgpr_read_b32 v86, a178 + v_accvgpr_read_b32 v87, a179 + v_accvgpr_read_b32 v88, a180 + v_accvgpr_read_b32 v89, a181 + v_accvgpr_read_b32 v90, a182 + v_accvgpr_read_b32 v91, a183 + v_accvgpr_read_b32 v92, a184 + v_accvgpr_read_b32 v93, a185 + v_accvgpr_read_b32 v94, a186 + v_accvgpr_read_b32 v95, a187 + v_accvgpr_read_b32 v96, a188 + v_accvgpr_read_b32 v97, a189 + v_accvgpr_read_b32 v98, a190 + v_accvgpr_read_b32 v99, a191 + v_accvgpr_read_b32 v100, a192 + v_accvgpr_read_b32 v101, a193 + v_accvgpr_read_b32 v102, a194 + v_accvgpr_read_b32 v103, a195 + v_accvgpr_read_b32 v104, a196 + v_accvgpr_read_b32 v105, a197 + v_accvgpr_read_b32 v106, a198 + v_accvgpr_read_b32 v107, a199 + v_accvgpr_read_b32 v108, a200 + v_accvgpr_read_b32 v109, a201 + v_accvgpr_read_b32 v110, a202 + v_accvgpr_read_b32 v111, a203 + v_accvgpr_read_b32 v112, a204 + v_accvgpr_read_b32 v113, a205 + v_accvgpr_read_b32 v114, a206 + v_accvgpr_read_b32 v115, a207 + v_accvgpr_read_b32 v116, a208 + v_accvgpr_read_b32 v117, a209 + v_accvgpr_read_b32 v118, a210 + v_accvgpr_read_b32 v119, a211 + v_accvgpr_read_b32 v120, a212 + v_accvgpr_read_b32 v121, a213 + v_accvgpr_read_b32 v122, a214 + v_accvgpr_read_b32 v123, a215 + v_accvgpr_read_b32 v124, a216 + v_accvgpr_read_b32 v125, a217 + v_accvgpr_read_b32 v126, a218 + v_accvgpr_read_b32 v127, a219 + v_accvgpr_read_b32 v128, a220 + v_accvgpr_read_b32 v129, a221 + v_accvgpr_read_b32 v130, a222 + v_accvgpr_read_b32 v131, a223 + v_accvgpr_read_b32 v132, a224 + v_accvgpr_read_b32 v133, a225 + v_accvgpr_read_b32 v134, a226 + v_accvgpr_read_b32 v135, a227 + v_accvgpr_read_b32 v136, a228 + v_accvgpr_read_b32 v137, a229 + v_accvgpr_read_b32 v138, a230 + v_accvgpr_read_b32 v139, a231 + v_accvgpr_read_b32 v140, a232 + v_accvgpr_read_b32 v141, a233 + v_accvgpr_read_b32 v142, a234 + v_accvgpr_read_b32 v143, a235 + v_accvgpr_read_b32 v144, a236 + v_accvgpr_read_b32 v145, a237 + v_accvgpr_read_b32 v146, a238 + v_accvgpr_read_b32 v147, a239 + v_accvgpr_read_b32 v148, a240 + v_accvgpr_read_b32 v149, a241 + v_accvgpr_read_b32 v150, a242 + v_accvgpr_read_b32 v151, a243 + v_accvgpr_read_b32 v152, a244 + v_accvgpr_read_b32 v153, a245 + v_accvgpr_read_b32 v154, a246 + v_accvgpr_read_b32 v155, a247 + v_accvgpr_read_b32 v156, a248 + v_accvgpr_read_b32 v157, a249 + v_accvgpr_read_b32 v158, a250 + v_accvgpr_read_b32 v159, a251 + v_accvgpr_read_b32 v160, a252 + v_accvgpr_read_b32 v161, a253 + v_accvgpr_read_b32 v162, a254 + v_accvgpr_read_b32 v163, a255 + v_accvgpr_read_b32 v164, a32 + v_accvgpr_read_b32 v165, a33 + v_accvgpr_read_b32 v166, a34 + v_accvgpr_read_b32 v167, a35 + v_accvgpr_read_b32 v168, a36 + v_accvgpr_read_b32 v169, a37 + v_accvgpr_read_b32 v170, a38 + v_accvgpr_read_b32 v171, a39 + v_accvgpr_read_b32 v172, a40 + v_accvgpr_read_b32 v173, a41 + v_accvgpr_read_b32 v174, a42 + v_accvgpr_read_b32 v175, a43 + v_accvgpr_read_b32 v176, a44 + v_accvgpr_read_b32 v177, a45 + v_accvgpr_read_b32 v178, a46 + v_accvgpr_read_b32 v179, a47 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v8, v79 + ds_read_b32 v9, v69 + ds_read_b64 v[0:1], v78 offset:16384 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a224, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[8:9], v[0:1], a[224:239] + ds_read_b64 v[4:5], v80 offset:16384 + v_accvgpr_mov_b32 a223, a95 + v_accvgpr_mov_b32 a222, a94 + v_accvgpr_mov_b32 a221, a93 + v_accvgpr_mov_b32 a220, a92 + v_accvgpr_mov_b32 a219, a91 + v_accvgpr_mov_b32 a218, a90 + v_accvgpr_mov_b32 a217, a89 + v_accvgpr_mov_b32 a216, a88 + v_accvgpr_mov_b32 a215, a87 + v_accvgpr_mov_b32 a214, a86 + v_accvgpr_mov_b32 a213, a85 + v_accvgpr_mov_b32 a212, a84 + v_accvgpr_mov_b32 a211, a83 + v_accvgpr_mov_b32 a210, a82 + v_accvgpr_mov_b32 a209, a81 + v_accvgpr_mov_b32 a208, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[8:9], v[4:5], a[208:223] + ds_read_b64 v[6:7], v81 offset:16384 + v_accvgpr_mov_b32 a207, a111 + v_accvgpr_mov_b32 a206, a110 + v_accvgpr_mov_b32 a205, a109 + v_accvgpr_mov_b32 a204, a108 + v_accvgpr_mov_b32 a203, a107 + v_accvgpr_mov_b32 a202, a106 + v_accvgpr_mov_b32 a201, a105 + v_accvgpr_mov_b32 a200, a104 + v_accvgpr_mov_b32 a199, a103 + v_accvgpr_mov_b32 a198, a102 + v_accvgpr_mov_b32 a197, a101 + v_accvgpr_mov_b32 a196, a100 + v_accvgpr_mov_b32 a195, a99 + v_accvgpr_mov_b32 a194, a98 + v_accvgpr_mov_b32 a193, a97 + v_accvgpr_mov_b32 a192, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[8:9], v[6:7], a[192:207] + ds_read_b64 v[2:3], v82 offset:16384 + v_accvgpr_mov_b32 a191, a127 + v_accvgpr_mov_b32 a190, a126 + v_accvgpr_mov_b32 a189, a125 + v_accvgpr_mov_b32 a188, a124 + v_accvgpr_mov_b32 a187, a123 + v_accvgpr_mov_b32 a186, a122 + v_accvgpr_mov_b32 a185, a121 + v_accvgpr_mov_b32 a184, a120 + v_accvgpr_mov_b32 a183, a119 + v_accvgpr_mov_b32 a182, a118 + v_accvgpr_mov_b32 a181, a117 + v_accvgpr_mov_b32 a180, a116 + v_accvgpr_mov_b32 a179, a115 + v_accvgpr_mov_b32 a178, a114 + v_accvgpr_mov_b32 a177, a113 + v_accvgpr_mov_b32 a176, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[8:9], v[2:3], a[176:191] + ds_read_b32 v8, v72 + ds_read_b32 v9, v73 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[8:9], v[4:5], a[144:159] + v_accvgpr_write_b32 a143, v35 + v_accvgpr_write_b32 a142, v34 + v_accvgpr_write_b32 a141, v33 + v_accvgpr_write_b32 a140, v32 + v_accvgpr_write_b32 a139, v31 + v_accvgpr_write_b32 a138, v30 + v_accvgpr_write_b32 a137, v29 + v_accvgpr_write_b32 a136, v28 + v_accvgpr_write_b32 a135, v27 + v_accvgpr_write_b32 a134, v26 + v_accvgpr_write_b32 a133, v25 + v_accvgpr_write_b32 a132, v24 + v_accvgpr_write_b32 a131, v23 + v_accvgpr_write_b32 a130, v22 + v_accvgpr_write_b32 a129, v21 + v_accvgpr_write_b32 a128, v20 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[8:9], v[6:7], a[128:143] + v_accvgpr_write_b32 a127, v99 + v_accvgpr_write_b32 a126, v98 + v_accvgpr_write_b32 a125, v97 + v_accvgpr_write_b32 a124, v96 + v_accvgpr_write_b32 a123, v95 + v_accvgpr_write_b32 a122, v94 + v_accvgpr_write_b32 a121, v93 + v_accvgpr_write_b32 a120, v92 + v_accvgpr_write_b32 a119, v91 + v_accvgpr_write_b32 a118, v90 + v_accvgpr_write_b32 a117, v89 + v_accvgpr_write_b32 a116, v88 + v_accvgpr_write_b32 a115, v87 + v_accvgpr_write_b32 a114, v86 + v_accvgpr_write_b32 a113, v85 + v_accvgpr_write_b32 a112, v84 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[8:9], v[2:3], a[112:127] + ds_read_b32 v8, v74 + ds_read_b32 v9, v75 + v_accvgpr_write_b32 a96, v100 + v_accvgpr_write_b32 a97, v101 + v_accvgpr_write_b32 a98, v102 + v_accvgpr_write_b32 a99, v103 + v_accvgpr_write_b32 a100, v104 + v_accvgpr_write_b32 a101, v105 + v_accvgpr_write_b32 a102, v106 + v_accvgpr_write_b32 a103, v107 + v_accvgpr_write_b32 a104, v108 + v_accvgpr_write_b32 a105, v109 + v_accvgpr_write_b32 a106, v110 + v_accvgpr_write_b32 a107, v111 + v_accvgpr_write_b32 a108, v112 + v_accvgpr_write_b32 a109, v113 + v_accvgpr_write_b32 a110, v114 + v_accvgpr_write_b32 a111, v115 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[8:9], v[0:1], a[96:111] + v_accvgpr_write_b32 a80, v116 + v_accvgpr_write_b32 a81, v117 + v_accvgpr_write_b32 a82, v118 + v_accvgpr_write_b32 a83, v119 + v_accvgpr_write_b32 a84, v120 + v_accvgpr_write_b32 a85, v121 + v_accvgpr_write_b32 a86, v122 + v_accvgpr_write_b32 a87, v123 + v_accvgpr_write_b32 a88, v124 + v_accvgpr_write_b32 a89, v125 + v_accvgpr_write_b32 a90, v126 + v_accvgpr_write_b32 a91, v127 + v_accvgpr_write_b32 a92, v128 + v_accvgpr_write_b32 a93, v129 + v_accvgpr_write_b32 a94, v130 + v_accvgpr_write_b32 a95, v131 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[8:9], v[4:5], a[80:95] + v_accvgpr_write_b32 a64, v132 + v_accvgpr_write_b32 a65, v133 + v_accvgpr_write_b32 a66, v134 + v_accvgpr_write_b32 a67, v135 + v_accvgpr_write_b32 a68, v136 + v_accvgpr_write_b32 a69, v137 + v_accvgpr_write_b32 a70, v138 + v_accvgpr_write_b32 a71, v139 + v_accvgpr_write_b32 a72, v140 + v_accvgpr_write_b32 a73, v141 + v_accvgpr_write_b32 a74, v142 + v_accvgpr_write_b32 a75, v143 + v_accvgpr_write_b32 a76, v144 + v_accvgpr_write_b32 a77, v145 + v_accvgpr_write_b32 a78, v146 + v_accvgpr_write_b32 a79, v147 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[8:9], v[6:7], a[64:79] + v_accvgpr_write_b32 a48, v148 + v_accvgpr_write_b32 a49, v149 + v_accvgpr_write_b32 a50, v150 + v_accvgpr_write_b32 a51, v151 + v_accvgpr_write_b32 a52, v152 + v_accvgpr_write_b32 a53, v153 + v_accvgpr_write_b32 a54, v154 + v_accvgpr_write_b32 a55, v155 + v_accvgpr_write_b32 a56, v156 + v_accvgpr_write_b32 a57, v157 + v_accvgpr_write_b32 a58, v158 + v_accvgpr_write_b32 a59, v159 + v_accvgpr_write_b32 a60, v160 + v_accvgpr_write_b32 a61, v161 + v_accvgpr_write_b32 a62, v162 + v_accvgpr_write_b32 a63, v163 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[8:9], v[2:3], a[48:63] + ds_read_b32 v8, v76 + ds_read_b32 v9, v77 + v_accvgpr_mov_b32 a47, a31 + v_accvgpr_mov_b32 a46, a30 + v_accvgpr_mov_b32 a45, a29 + v_accvgpr_mov_b32 a44, a28 + v_accvgpr_mov_b32 a43, a27 + v_accvgpr_mov_b32 a42, a26 + v_accvgpr_mov_b32 a41, a25 + v_accvgpr_mov_b32 a40, a24 + v_accvgpr_mov_b32 a39, a23 + v_accvgpr_mov_b32 a38, a22 + v_accvgpr_mov_b32 a37, a21 + v_accvgpr_mov_b32 a36, a20 + v_accvgpr_mov_b32 a35, a19 + v_accvgpr_mov_b32 a34, a18 + v_accvgpr_mov_b32 a33, a17 + v_accvgpr_mov_b32 a32, a16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[0:1], a[32:47] + v_accvgpr_write_b32 a16, v164 + v_accvgpr_write_b32 a17, v165 + v_accvgpr_write_b32 a18, v166 + v_accvgpr_write_b32 a19, v167 + v_accvgpr_write_b32 a20, v168 + v_accvgpr_write_b32 a21, v169 + v_accvgpr_write_b32 a22, v170 + v_accvgpr_write_b32 a23, v171 + v_accvgpr_write_b32 a24, v172 + v_accvgpr_write_b32 a25, v173 + v_accvgpr_write_b32 a26, v174 + v_accvgpr_write_b32 a27, v175 + v_accvgpr_write_b32 a28, v176 + v_accvgpr_write_b32 a29, v177 + v_accvgpr_write_b32 a30, v178 + v_accvgpr_write_b32 a31, v179 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[8:9], v[6:7], a[0:15] + ds_read_b32 v10, v41 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[2:3], a[240:255] + ds_read_b32 v11, v42 + ds_read_b64 v[0:1], v67 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v70 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v71 offset:16384 + ds_read_b32 v8, v49 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v50 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v54 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v55 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v62 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v63 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[8:9], v[4:5], a[0:15] + ds_read_b32 v10, v36 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[6:7], a[240:255] + ds_read_b32 v11, v38 + ds_read_b64 v[0:1], v61 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v64 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v66 offset:16384 + ds_read_b32 v8, v47 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v48 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v51 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v52 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v56 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v59 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[8:9], v[4:5], a[0:15] + ds_read_b32 v10, v19 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[6:7], a[240:255] + ds_read_b32 v11, v37 + ds_read_b64 v[0:1], v53 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v57 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v58 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v60 offset:16384 + ds_read_b32 v8, v39 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v40 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v43 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v44 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v46 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v45 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[8:9], v[4:5], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[6:7], a[240:255] +.LBB17_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESC_NSB_8RowMajorELi1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEENSL_IJNSM_IS1D_NSL_IJS1G_S1F_EEEEEEEESG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1O_T0_EE5valueEbE4typeEL + v_accvgpr_read_b32 v143, a224 + v_accvgpr_read_b32 v142, a225 + v_accvgpr_read_b32 v141, a226 + v_accvgpr_read_b32 v140, a227 + v_accvgpr_read_b32 v139, a228 + v_accvgpr_read_b32 v18, a229 + v_accvgpr_read_b32 v0, a230 + v_accvgpr_read_b32 v138, a231 + v_accvgpr_read_b32 v137, a232 + v_accvgpr_read_b32 v136, a233 + v_accvgpr_read_b32 v135, a234 + v_accvgpr_read_b32 v134, a235 + v_accvgpr_read_b32 v133, a236 + v_accvgpr_read_b32 v132, a237 + v_accvgpr_read_b32 v131, a238 + v_accvgpr_read_b32 v130, a239 + v_accvgpr_read_b32 v107, a208 + v_accvgpr_read_b32 v106, a209 + v_accvgpr_read_b32 v105, a210 + v_accvgpr_read_b32 v104, a211 + v_accvgpr_read_b32 v103, a212 + v_accvgpr_read_b32 v102, a213 + v_accvgpr_read_b32 v101, a214 + v_accvgpr_read_b32 v100, a215 + v_accvgpr_read_b32 v99, a216 + v_accvgpr_read_b32 v98, a217 + v_accvgpr_read_b32 v97, a218 + v_accvgpr_read_b32 v96, a219 + v_accvgpr_read_b32 v95, a220 + v_accvgpr_read_b32 v94, a221 + v_accvgpr_read_b32 v93, a222 + v_accvgpr_read_b32 v92, a223 + v_accvgpr_read_b32 v91, a192 + v_accvgpr_read_b32 v90, a193 + v_accvgpr_read_b32 v89, a194 + v_accvgpr_read_b32 v88, a195 + v_accvgpr_read_b32 v87, a196 + v_accvgpr_read_b32 v86, a197 + v_accvgpr_read_b32 v85, a198 + v_accvgpr_read_b32 v84, a199 + v_accvgpr_read_b32 v83, a200 + v_accvgpr_read_b32 v82, a201 + v_accvgpr_read_b32 v81, a202 + v_accvgpr_read_b32 v80, a203 + v_accvgpr_read_b32 v79, a204 + v_accvgpr_read_b32 v78, a205 + v_accvgpr_read_b32 v77, a206 + v_accvgpr_read_b32 v76, a207 + v_accvgpr_read_b32 v75, a176 + v_accvgpr_read_b32 v74, a177 + v_accvgpr_read_b32 v73, a178 + v_accvgpr_read_b32 v72, a179 + v_accvgpr_read_b32 v71, a180 + v_accvgpr_read_b32 v70, a181 + v_accvgpr_read_b32 v69, a182 + v_accvgpr_read_b32 v68, a183 + v_accvgpr_read_b32 v67, a184 + v_accvgpr_read_b32 v66, a185 + v_accvgpr_read_b32 v65, a186 + v_accvgpr_read_b32 v64, a187 + v_accvgpr_read_b32 v63, a188 + v_accvgpr_read_b32 v62, a189 + v_accvgpr_read_b32 v61, a190 + v_accvgpr_read_b32 v20, a191 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v60, a80 + v_accvgpr_read_b32 v59, a81 + v_accvgpr_read_b32 v58, a82 + v_accvgpr_read_b32 v57, a83 + v_accvgpr_read_b32 v56, a84 + v_accvgpr_read_b32 v55, a85 + v_accvgpr_read_b32 v54, a86 + v_accvgpr_read_b32 v53, a87 + v_accvgpr_read_b32 v52, a88 + v_accvgpr_read_b32 v51, a89 + v_accvgpr_read_b32 v50, a90 + v_accvgpr_read_b32 v25, a91 + v_accvgpr_read_b32 v24, a92 + v_accvgpr_read_b32 v23, a93 + v_accvgpr_read_b32 v22, a94 + v_accvgpr_read_b32 v21, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v1, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s2, s4, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_u32 s2, s5, s3 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v19, 3, v225 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v209, v92 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v147 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v20, v205 + v_accvgpr_write_b32 a0, v20 + v_cvt_f16_f32_e32 v20, v204 + v_accvgpr_write_b32 a1, v20 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v20, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v1 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v201, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v225 + v_lshrrev_b32_e32 v1, 1, v225 + s_cbranch_scc1 .LBB17_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB17_14 +.LBB17_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB17_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_or_b32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v132 offset:3456 + ds_write_b16 v23, v133 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s20, v25 + v_or_b32_e32 v25, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v190, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v190, v31, v41 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v76 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 0x80, v25 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v72 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0xc0, v25 + v_add_u32_e32 v31, v31, v191 + v_lshlrev_b32_e32 v192, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v207 offset:128 + ds_write_b16 v23, v206 offset:256 + ds_write_b16 v23, a0 offset:384 + ds_write_b16 v23, a1 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v61 offset:2304 + ds_write_b16 v23, v62 offset:2432 + ds_write_b16 v23, v63 offset:3072 + ds_write_b16 v23, v64 offset:3200 + ds_write_b16 v23, v65 offset:3328 + ds_write_b16 v23, v66 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v115 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v191 + v_lshlrev_b32_e32 v191, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v114 + ds_write_b16 v23, v193 offset:128 + ds_write_b16 v23, v194 offset:256 + ds_write_b16 v23, v195 offset:384 + ds_write_b16 v23, v196 offset:1024 + ds_write_b16 v23, v197 offset:1152 + ds_write_b16 v23, v198 offset:1280 + ds_write_b16 v23, v199 offset:1408 + ds_write_b16 v23, v200 offset:2048 + ds_write_b16 v23, v201 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v43 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v108 offset:8320 + ds_write_b16 v23, v109 offset:8448 + ds_write_b16 v23, v110 offset:8576 + ds_write_b16 v23, v111 offset:9216 + ds_write_b16 v23, v112 offset:9344 + ds_write_b16 v23, v113 offset:9472 + ds_write_b16 v23, v185 offset:9600 + ds_write_b16 v23, v184 offset:10240 + ds_write_b16 v23, v183 offset:10368 + ds_write_b16 v23, v182 offset:10496 + ds_write_b16 v23, v181 offset:10624 + ds_write_b16 v23, v180 offset:11264 + ds_write_b16 v23, v179 offset:11392 + ds_write_b16 v23, v178 offset:11520 + ds_write_b16 v23, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v190 + v_lshlrev_b32_e32 v190, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v3 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB17_12 +.LBB17_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_or_b32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v132 offset:3456 + ds_write_b16 v31, v133 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v41, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v131, v0, v41 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v186, 1, v131 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v186, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v131 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v107 + ds_write_b16 v31, v106 offset:128 + ds_write_b16 v31, v105 offset:256 + ds_write_b16 v31, v104 offset:384 + ds_write_b16 v31, v103 offset:1024 + ds_write_b16 v31, v102 offset:1152 + ds_write_b16 v31, v101 offset:1280 + ds_write_b16 v31, v100 offset:1408 + ds_write_b16 v31, v99 offset:2048 + ds_write_b16 v31, v98 offset:2176 + ds_write_b16 v31, v97 offset:2304 + ds_write_b16 v31, v96 offset:2432 + ds_write_b16 v31, v95 offset:3072 + ds_write_b16 v31, v94 offset:3200 + ds_write_b16 v31, v93 offset:3328 + ds_write_b16 v31, v209 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v41 + v_add_u32_e32 v94, v0, v93 + v_lshlrev_b32_e32 v95, 1, v94 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v95, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v94 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v76 offset:3456 + ds_write_b16 v31, v77 offset:8192 + ds_write_b16 v31, v78 offset:8320 + ds_write_b16 v31, v79 offset:8448 + ds_write_b16 v31, v80 offset:8576 + ds_write_b16 v31, v81 offset:9216 + ds_write_b16 v31, v82 offset:9344 + ds_write_b16 v31, v83 offset:9472 + ds_write_b16 v31, v84 offset:9600 + ds_write_b16 v31, v85 offset:10240 + ds_write_b16 v31, v86 offset:10368 + ds_write_b16 v31, v87 offset:10496 + ds_write_b16 v31, v88 offset:10624 + ds_write_b16 v31, v89 offset:11264 + ds_write_b16 v31, v90 offset:11392 + ds_write_b16 v31, v91 offset:11520 + ds_write_b16 v31, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v76, 0x80, v41 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v75 + ds_write_b16 v31, v74 offset:128 + ds_write_b16 v31, v73 offset:256 + ds_write_b16 v31, v72 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v74, 0xc0, v41 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v208 + ds_write_b16 v31, v207 offset:128 + ds_write_b16 v31, v206 offset:256 + ds_write_b16 v31, a0 offset:384 + ds_write_b16 v31, a1 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v61 offset:2304 + ds_write_b16 v31, v62 offset:2432 + ds_write_b16 v31, v63 offset:3072 + ds_write_b16 v31, v64 offset:3200 + ds_write_b16 v31, v65 offset:3328 + ds_write_b16 v31, v66 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v115 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v114 + ds_write_b16 v31, v193 offset:128 + ds_write_b16 v31, v194 offset:256 + ds_write_b16 v31, v195 offset:384 + ds_write_b16 v31, v196 offset:1024 + ds_write_b16 v31, v197 offset:1152 + ds_write_b16 v31, v198 offset:1280 + ds_write_b16 v31, v199 offset:1408 + ds_write_b16 v31, v200 offset:2048 + ds_write_b16 v31, v201 offset:2176 + ds_write_b16 v31, v47 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v44 offset:3200 + ds_write_b16 v31, v43 offset:3328 + ds_write_b16 v31, v48 offset:3456 + ds_write_b16 v31, v49 offset:8192 + ds_write_b16 v31, v108 offset:8320 + ds_write_b16 v31, v109 offset:8448 + ds_write_b16 v31, v110 offset:8576 + ds_write_b16 v31, v111 offset:9216 + ds_write_b16 v31, v112 offset:9344 + ds_write_b16 v31, v113 offset:9472 + ds_write_b16 v31, v185 offset:9600 + ds_write_b16 v31, v184 offset:10240 + ds_write_b16 v31, v183 offset:10368 + ds_write_b16 v31, v182 offset:10496 + ds_write_b16 v31, v181 offset:10624 + ds_write_b16 v31, v180 offset:11264 + ds_write_b16 v31, v179 offset:11392 + ds_write_b16 v31, v178 offset:11520 + ds_write_b16 v31, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, v61, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v3 offset:128 + ds_write_b16 v31, v4 offset:256 + ds_write_b16 v31, v5 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v41 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end17: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end17-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 29528 +; TotalNumSgprs: 36 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB18_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB18_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v2, v0, s2 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v6 +.LBB18_3: ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_ubyte v7, v[2:3], off + v_lshl_add_u64 v[8:9], s[8:9], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_fp8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_fp8_sdwa v5, v5 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s7, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v5, v7 + s_cbranch_scc0 .LBB18_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB18_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB18_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end18: + .size _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end18-_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 440 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_mov_b32 s23, s7 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v0, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s24, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s24, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_mul_i32 s19, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s19, 31 + s_add_u32 s12, s10, s19 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_mul_i32 s2, s22, s2 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v225, -1, v0 + v_and_b32_e32 v37, 31, v225 + v_lshrrev_b32_e32 v5, 5, v225 + v_and_b32_e32 v4, 15, v225 + v_lshrrev_b32_e32 v1, 2, v225 + s_cbranch_scc0 .LBB19_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + s_lshr_b32 s28, s15, 2 + s_and_b32 s11, s28, 0x3ffffff0 + v_and_b32_e32 v2, 28, v1 + v_lshlrev_b32_e32 v14, 4, v4 + v_or_b32_e32 v0, s20, v14 + v_add_u32_e32 v16, s11, v2 + v_mad_u64_u32 v[2:3], s[24:25], v16, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[6:9], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[20:23], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[24:27], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v19, 3, v5 + v_lshlrev_b32_e32 v0, 12, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s19, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s26, 0x7030602 + v_lshl_or_b32 v3, v4, 7, v0 + v_or_b32_e32 v14, s21, v14 + s_lshr_b32 s29, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s28, 0x3fffffe0 + v_and_or_b32 v2, s29, 32, v37 + v_or_b32_e32 v0, s11, v37 + v_lshrrev_b32_e32 v2, 4, v2 + v_lshrrev_b32_e32 v36, 4, v0 + v_mad_u64_u32 v[14:15], s[28:29], v16, s22, v[14:15] + v_xor_b32_e32 v17, v2, v4 + v_xor_b32_e32 v15, v36, v4 + v_lshl_or_b32 v18, v17, 2, v3 + v_add_u32_e32 v38, s22, v14 + buffer_load_dwordx4 v[28:31], v14, s[12:15], 0 offen + buffer_load_dwordx4 v[32:35], v38, s[12:15], 0 offen + v_add_u32_e32 v14, s22, v38 + v_add_u32_e32 v46, s22, v14 + buffer_load_dwordx4 v[38:41], v14, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v46, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v6, v6, v6, s27 + v_perm_b32 v7, v7, v7, s27 + v_perm_b32 v8, v8, v8, s27 + v_perm_b32 v9, v9, v9, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s27 + v_perm_b32 v11, v11, v11, s27 + v_perm_b32 v12, v12, v12, s27 + v_perm_b32 v13, v13, v13, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v14, v20, v20, s27 + v_perm_b32 v20, v21, v21, s27 + v_perm_b32 v21, v22, v22, s27 + v_perm_b32 v22, v23, v23, s27 + v_perm_b32 v23, v10, v6, s25 + v_perm_b32 v6, v10, v6, s26 + v_perm_b32 v10, v11, v7, s25 + v_perm_b32 v7, v11, v7, s26 + v_perm_b32 v11, v12, v8, s25 + v_perm_b32 v8, v12, v8, s26 + v_perm_b32 v12, v13, v9, s25 + v_perm_b32 v9, v13, v9, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v13, v24, v24, s27 + v_perm_b32 v24, v25, v25, s27 + v_perm_b32 v25, v26, v26, s27 + v_perm_b32 v26, v27, v27, s27 + v_perm_b32 v27, v13, v14, s25 + v_perm_b32 v13, v13, v14, s26 + v_perm_b32 v14, v24, v20, s25 + v_perm_b32 v20, v24, v20, s26 + v_perm_b32 v24, v25, v21, s25 + v_perm_b32 v21, v25, v21, s26 + v_perm_b32 v25, v26, v22, s25 + v_perm_b32 v22, v26, v22, s26 + v_perm_b32 v26, v27, v23, s19 + v_perm_b32 v23, v27, v23, s24 + v_perm_b32 v27, v13, v6, s19 + v_perm_b32 v6, v13, v6, s24 + v_perm_b32 v13, v14, v10, s19 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v20, v7, s19 + v_perm_b32 v7, v20, v7, s24 + v_perm_b32 v20, v24, v11, s19 + v_perm_b32 v11, v24, v11, s24 + v_perm_b32 v24, v21, v8, s19 + v_perm_b32 v8, v21, v8, s24 + v_perm_b32 v21, v25, v12, s19 + v_perm_b32 v12, v25, v12, s24 + v_perm_b32 v25, v22, v9, s19 + v_perm_b32 v9, v22, v9, s24 + v_lshrrev_b32_e32 v22, 1, v16 + v_and_b32_e32 v22, 16, v22 + v_xor_b32_e32 v46, v22, v37 + v_lshlrev_b32_e32 v47, 9, v16 + v_and_b32_e32 v47, 0x3000, v47 + v_lshlrev_b32_e32 v16, 6, v16 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v16, 0xfffff800, v16 + v_add_u32_e32 v16, v47, v16 + v_lshl_or_b32 v16, v46, 2, v16 + ds_write_b32 v16, v26 + v_or_b32_e32 v26, 1, v22 + v_xor_b32_e32 v26, v26, v37 + v_sub_u32_e32 v46, v26, v46 + v_lshl_add_u32 v46, v46, 2, v16 + ds_write_b32 v46, v23 offset:128 + v_or_b32_e32 v23, 2, v22 + v_xor_b32_e32 v23, v23, v37 + v_sub_u32_e32 v26, v23, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v46, s18, v26 + ds_write_b32 v26, v27 offset:128 + v_or_b32_e32 v27, 3, v22 + v_xor_b32_e32 v27, v27, v37 + v_sub_u32_e32 v23, v27, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v26, s18, v23 + ds_write_b32 v23, v6 offset:128 + v_or_b32_e32 v6, 4, v22 + v_xor_b32_e32 v6, v6, v37 + v_sub_u32_e32 v27, v6, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v27, v23, s18, v27 + ds_write_b32 v27, v13 offset:128 + v_or_b32_e32 v13, 5, v22 + v_xor_b32_e32 v13, v13, v37 + v_sub_u32_e32 v6, v13, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v27, s18, v6 + ds_write_b32 v6, v10 offset:128 + v_or_b32_e32 v10, 6, v22 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v13, v10, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v6, s18, v13 + ds_write_b32 v13, v14 offset:128 + v_or_b32_e32 v14, 7, v22 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v13, s18, v10 + ds_write_b32 v10, v7 offset:128 + v_or_b32_e32 v7, 8, v22 + v_xor_b32_e32 v7, v7, v37 + v_sub_u32_e32 v14, v7, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v10, s18, v14 + ds_write_b32 v14, v20 offset:128 + v_or_b32_e32 v20, 9, v22 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v7, v20, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v7, v14, s18, v7 + ds_write_b32 v7, v11 offset:128 + v_or_b32_e32 v11, 10, v22 + v_xor_b32_e32 v11, v11, v37 + v_sub_u32_e32 v20, v11, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v7, s18, v20 + ds_write_b32 v20, v24 offset:128 + v_or_b32_e32 v24, 11, v22 + v_xor_b32_e32 v24, v24, v37 + v_sub_u32_e32 v11, v24, v11 + v_lshlrev_b32_e32 v11, 2, v11 + v_add3_u32 v11, v20, s18, v11 + ds_write_b32 v11, v8 offset:128 + v_or_b32_e32 v8, 12, v22 + v_xor_b32_e32 v8, v8, v37 + v_sub_u32_e32 v24, v8, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v11, s18, v24 + ds_write_b32 v24, v21 offset:128 + v_or_b32_e32 v21, 13, v22 + v_xor_b32_e32 v21, v21, v37 + v_sub_u32_e32 v8, v21, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v8, v24, s18, v8 + ds_write_b32 v8, v12 offset:128 + v_or_b32_e32 v12, 14, v22 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v21, v12, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v8, s18, v21 + ds_write_b32 v21, v25 offset:128 + v_or_b32_e32 v22, 15, v22 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v12, v22, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v21, s18, v12 + ds_write_b32 v12, v9 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v9, v28, v28, s27 + v_perm_b32 v22, v29, v29, s27 + v_perm_b32 v25, v30, v30, s27 + v_perm_b32 v28, v31, v31, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v29, v32, v32, s27 + v_perm_b32 v30, v33, v33, s27 + v_perm_b32 v31, v34, v34, s27 + v_perm_b32 v32, v35, v35, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v33, v38, v38, s27 + v_perm_b32 v34, v39, v39, s27 + v_perm_b32 v35, v40, v40, s27 + v_perm_b32 v38, v41, v41, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v39, v42, v42, s27 + v_perm_b32 v40, v43, v43, s27 + v_perm_b32 v41, v44, v44, s27 + v_perm_b32 v42, v45, v45, s27 + v_perm_b32 v43, v29, v9, s25 + v_perm_b32 v44, v39, v33, s25 + v_perm_b32 v45, v44, v43, s19 + v_perm_b32 v43, v44, v43, s24 + v_perm_b32 v9, v29, v9, s26 + v_perm_b32 v29, v39, v33, s26 + v_perm_b32 v33, v29, v9, s19 + v_perm_b32 v9, v29, v9, s24 + v_perm_b32 v29, v30, v22, s25 + v_perm_b32 v39, v40, v34, s25 + v_perm_b32 v44, v39, v29, s19 + v_perm_b32 v29, v39, v29, s24 + v_perm_b32 v22, v30, v22, s26 + v_perm_b32 v30, v40, v34, s26 + v_perm_b32 v34, v30, v22, s19 + v_perm_b32 v22, v30, v22, s24 + v_perm_b32 v30, v31, v25, s25 + v_perm_b32 v39, v41, v35, s25 + v_perm_b32 v40, v39, v30, s19 + v_perm_b32 v30, v39, v30, s24 + v_perm_b32 v25, v31, v25, s26 + v_perm_b32 v31, v41, v35, s26 + v_perm_b32 v35, v31, v25, s19 + v_perm_b32 v25, v31, v25, s24 + v_perm_b32 v31, v32, v28, s25 + v_perm_b32 v39, v42, v38, s25 + v_perm_b32 v41, v39, v31, s19 + v_perm_b32 v31, v39, v31, s24 + v_perm_b32 v28, v32, v28, s26 + v_perm_b32 v32, v42, v38, s26 + v_perm_b32 v38, v32, v28, s19 + v_perm_b32 v28, v32, v28, s24 + ds_write_b32 v16, v45 offset:16384 + ds_write_b32 v46, v43 offset:16512 + ds_write_b32 v26, v33 offset:16512 + ds_write_b32 v23, v9 offset:16512 + ds_write_b32 v27, v44 offset:16512 + ds_write_b32 v6, v29 offset:16512 + ds_write_b32 v13, v34 offset:16512 + ds_write_b32 v10, v22 offset:16512 + ds_write_b32 v14, v40 offset:16512 + ds_write_b32 v7, v30 offset:16512 + ds_write_b32 v20, v35 offset:16512 + ds_write_b32 v11, v25 offset:16512 + ds_write_b32 v24, v41 offset:16512 + ds_write_b32 v8, v31 offset:16512 + ds_write_b32 v21, v38 offset:16512 + ds_write_b32 v12, v28 offset:16512 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v20, v15, 2, v3 + v_lshrrev_b16_e32 v8, 3, v19 + v_add_u32_e32 v7, 16, v36 + v_xor_b32_e32 v6, v7, v4 + v_sub_u32_e32 v9, v8, v5 + v_lshlrev_b32_e32 v21, 12, v9 + v_lshlrev_b32_e32 v9, 2, v6 + v_add3_u32 v22, v21, v3, v9 + v_add_u32_e32 v3, 16, v19 + v_lshrrev_b32_e32 v9, 5, v3 + v_lshrrev_b16_e32 v3, 3, v3 + v_and_b32_e32 v3, 3, v3 + v_sub_u16_e32 v10, v3, v8 + v_bfe_i32 v10, v10, 0, 16 + v_lshlrev_b32_e32 v11, 4, v9 + v_or_b32_e32 v12, v11, v4 + v_and_b32_e32 v23, 31, v12 + v_xor_b32_e32 v12, v36, v23 + v_sub_u32_e32 v6, v12, v6 + v_lshlrev_b32_e32 v13, 11, v9 + v_lshlrev_b32_e32 v6, 2, v6 + v_lshl_or_b32 v14, v10, 12, v13 + v_add3_u32 v24, v6, v14, v22 + v_add_u32_e32 v6, 20, v19 + v_lshrrev_b32_e32 v10, 5, v6 + v_sub_u32_e32 v9, v10, v9 + v_lshrrev_b16_e32 v6, 3, v6 + v_and_b32_e32 v6, 3, v6 + v_sub_u16_e32 v3, v6, v3 + v_bfe_i32 v3, v3, 0, 16 + v_lshlrev_b32_e32 v16, 4, v10 + v_or_b32_e32 v13, v16, v4 + v_and_b32_e32 v25, 31, v13 + v_xor_b32_e32 v13, v7, v25 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v9, 11, v9 + v_lshlrev_b32_e32 v12, 2, v12 + v_lshl_add_u32 v15, v3, 12, v9 + v_add3_u32 v26, v12, v15, v24 + v_sub_u16_e32 v3, v8, v6 + v_bfe_i32 v3, v3, 0, 16 + v_or_b32_e32 v27, 16, v4 + v_xor_b32_e32 v6, v36, v27 + v_sub_u32_e32 v9, v6, v13 + v_lshlrev_b32_e32 v10, 11, v10 + v_xor_b32_e32 v10, 0x800, v10 + v_lshlrev_b32_e32 v12, 2, v9 + v_lshl_add_u32 v9, v3, 12, v10 + v_add3_u32 v28, v12, v9, v26 + v_xor_b32_e32 v3, v7, v27 + v_sub_u32_e32 v6, v3, v6 + v_lshl_add_u32 v29, v6, 2, v28 + v_add_u32_e32 v6, 48, v19 + v_lshrrev_b32_e32 v10, 5, v6 + v_lshlrev_b32_e32 v12, 11, v10 + v_lshrrev_b16_e32 v6, 3, v6 + v_and_b32_e32 v6, 3, v6 + v_sub_u16_e32 v13, v6, v8 + v_lshlrev_b32_e32 v30, 4, v10 + v_or_b32_e32 v31, v30, v4 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v32, v36, v31 + v_sub_u32_e32 v3, v32, v3 + v_lshlrev_b32_e32 v33, 2, v3 + v_mov_b32_e32 v34, 12 + v_lshlrev_b32_sdwa v3, v34, sext(v13) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v3, v12, v3, s11 + v_add3_u32 v33, v33, v3, v29 + v_add_u32_e32 v12, 52, v19 + v_lshrrev_b32_e32 v19, 5, v12 + v_sub_u32_e32 v10, v19, v10 + v_lshrrev_b16_e32 v12, 3, v12 + v_and_b32_e32 v12, 3, v12 + v_sub_u16_e32 v6, v12, v6 + v_bfe_i32 v13, v6, 0, 16 + v_lshlrev_b32_e32 v35, 4, v19 + v_or_b32_e32 v36, v35, v4 + v_and_b32_e32 v6, 31, v36 + v_xor_b32_e32 v38, v7, v6 + v_sub_u32_e32 v7, v38, v32 + v_lshlrev_b32_e32 v10, 11, v10 + v_lshlrev_b32_e32 v32, 2, v7 + v_lshl_add_u32 v7, v13, 12, v10 + v_add3_u32 v13, v32, v7, v33 + v_add_u32_e32 v10, 64, v0 + v_lshrrev_b32_e32 v32, 4, v10 + v_sub_u16_e32 v8, v8, v12 + v_sub_u32_e32 v12, v36, v35 + v_ashrrev_i32_e32 v10, 31, v12 + v_lshrrev_b32_e32 v10, 27, v10 + v_add_u32_e32 v10, v12, v10 + v_and_b32_e32 v10, 0xffffffe0, v10 + v_sub_u32_e32 v35, v12, v10 + v_xor_b32_e32 v10, v32, v35 + v_sub_u32_e32 v36, v10, v38 + v_lshlrev_b32_e32 v36, 2, v36 + v_lshlrev_b32_sdwa v8, v34, sext(v8) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v19, 11, v19 + v_sub_u32_e32 v34, v8, v19 + v_add3_u32 v19, v36, v34, v13 + v_add_u32_e32 v36, 16, v32 + v_xor_b32_e32 v8, v36, v35 + v_sub_u32_e32 v10, v8, v10 + v_lshl_add_u32 v10, v10, 2, v19 + v_add_u32_e32 v11, v12, v11 + v_ashrrev_i32_e32 v38, 31, v11 + v_lshrrev_b32_e32 v38, 27, v38 + v_add_u32_e32 v38, v11, v38 + v_and_b32_e32 v38, 0xffffffe0, v38 + v_sub_u32_e32 v38, v11, v38 + v_xor_b32_e32 v11, v32, v38 + v_sub_u32_e32 v8, v11, v8 + v_lshl_add_u32 v8, v8, 2, v14 + v_add_u32_e32 v8, v8, v10 + ds_read_b32 v70, v19 + ds_read_b32 v71, v10 + ds_read_b32 v78, v8 + v_add_u32_e32 v10, v12, v16 + v_ashrrev_i32_e32 v16, 31, v10 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v10, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v39, v10, v16 + v_xor_b32_e32 v19, v36, v39 + v_sub_u32_e32 v10, v19, v11 + v_lshl_add_u32 v10, v10, 2, v15 + v_add_u32_e32 v40, v8, v10 + v_add_u32_e32 v11, 16, v12 + v_ashrrev_i32_e32 v16, 31, v11 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v11, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v16, v11, v16 + v_xor_b32_e32 v41, v32, v16 + v_sub_u32_e32 v11, v41, v19 + v_lshl_add_u32 v11, v11, 2, v9 + v_add_u32_e32 v19, v40, v11 + v_xor_b32_e32 v42, v36, v16 + v_add_u32_e32 v12, v12, v30 + v_ashrrev_i32_e32 v30, 31, v12 + v_lshrrev_b32_e32 v30, 27, v30 + v_add_u32_e32 v30, v12, v30 + v_and_b32_e32 v30, 0xffffffe0, v30 + v_sub_u32_e32 v12, v12, v30 + ds_read_b32 v60, v20 + ds_read_b32 v61, v22 + ds_read_b32 v80, v24 + ds_read_b32 v81, v26 + ds_read_b32 v82, v28 + ds_read_b32 v83, v29 + ds_read_b32 v20, v33 + ds_read_b32 v84, v18 offset:16384 + v_or_b32_e32 v22, 16, v2 + v_xor_b32_e32 v24, v22, v4 + v_sub_u32_e32 v17, v24, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v18, v21, v17 + v_xor_b32_e32 v18, v2, v23 + v_sub_u32_e32 v21, v18, v24 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v21, v14, v17 + v_xor_b32_e32 v23, v22, v25 + v_sub_u32_e32 v18, v23, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v18, v15, v21 + v_xor_b32_e32 v24, v2, v27 + v_sub_u32_e32 v23, v24, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v23, v9, v18 + v_xor_b32_e32 v25, v22, v27 + v_sub_u32_e32 v24, v25, v24 + v_lshl_add_u32 v24, v24, 2, v23 + v_xor_b32_e32 v26, v2, v31 + v_sub_u32_e32 v25, v26, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v25, v3, v24 + v_xor_b32_e32 v22, v22, v6 + v_sub_u32_e32 v26, v22, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v26, v7, v25 + ds_read_b32 v85, v17 offset:16384 + ds_read_b32 v86, v21 offset:16384 + ds_read_b32 v87, v18 offset:16384 + ds_read_b32 v88, v23 offset:16384 + ds_read_b32 v89, v24 offset:16384 + ds_read_b32 v90, v25 offset:16384 + ds_read_b32 v91, v26 offset:16384 + v_or_b32_e32 v17, 4, v2 + v_xor_b32_e32 v18, v17, v35 + v_sub_u32_e32 v21, v18, v22 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v21, v34, v26 + v_or_b32_e32 v22, 20, v2 + v_xor_b32_e32 v23, v22, v35 + v_sub_u32_e32 v18, v23, v18 + v_lshl_add_u32 v18, v18, 2, v21 + ds_read_b32 v92, v21 offset:16384 + ds_read_b32 v93, v18 offset:16384 + v_xor_b32_e32 v21, v17, v38 + v_sub_u32_e32 v23, v21, v23 + v_lshl_add_u32 v23, v23, 2, v14 + v_add_u32_e32 v18, v23, v18 + v_xor_b32_e32 v23, v22, v39 + v_sub_u32_e32 v21, v23, v21 + v_lshl_add_u32 v24, v21, 2, v15 + v_add_u32_e32 v21, v18, v24 + v_xor_b32_e32 v25, v17, v16 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v23, v23, 2, v9 + v_add_u32_e32 v26, v21, v23 + v_xor_b32_e32 v27, v22, v16 + v_sub_u32_e32 v25, v27, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add_u32_e32 v28, v26, v25 + v_xor_b32_e32 v17, v17, v12 + v_sub_u32_e32 v27, v17, v27 + v_lshl_add_u32 v27, v27, 2, v3 + v_add_u32_e32 v29, v28, v27 + v_xor_b32_e32 v22, v22, v6 + v_sub_u32_e32 v17, v22, v17 + v_lshl_add_u32 v17, v17, 2, v7 + v_add_u32_e32 v30, v29, v17 + v_or_b32_e32 v31, 8, v2 + v_xor_b32_e32 v33, v31, v35 + v_sub_u32_e32 v22, v33, v22 + v_lshl_add_u32 v22, v22, 2, v34 + v_add_u32_e32 v43, v30, v22 + ds_read_b32 v94, v43 offset:16384 + v_or_b32_e32 v44, 24, v2 + v_xor_b32_e32 v45, v44, v35 + v_sub_u32_e32 v33, v45, v33 + v_lshlrev_b32_e32 v33, 2, v33 + v_add_u32_e32 v43, v43, v33 + ds_read_b32 v95, v43 offset:16384 + v_xor_b32_e32 v46, v31, v38 + v_sub_u32_e32 v45, v46, v45 + v_lshl_add_u32 v45, v45, 2, v14 + v_add_u32_e32 v43, v43, v45 + v_xor_b32_e32 v47, v44, v39 + v_sub_u32_e32 v46, v47, v46 + v_lshl_add_u32 v46, v46, 2, v15 + v_add_u32_e32 v48, v43, v46 + v_xor_b32_e32 v49, v31, v16 + v_sub_u32_e32 v47, v49, v47 + v_lshl_add_u32 v47, v47, 2, v9 + v_add_u32_e32 v50, v48, v47 + v_xor_b32_e32 v51, v44, v16 + v_sub_u32_e32 v49, v51, v49 + v_lshlrev_b32_e32 v49, 2, v49 + v_add_u32_e32 v52, v50, v49 + v_xor_b32_e32 v31, v31, v12 + v_sub_u32_e32 v51, v31, v51 + v_lshl_add_u32 v51, v51, 2, v3 + s_waitcnt lgkmcnt(10) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[60:61], v[84:85], 0 + v_add_u32_e32 v53, v52, v51 + v_xor_b32_e32 v44, v44, v6 + v_sub_u32_e32 v31, v44, v31 + v_lshl_add_u32 v31, v31, 2, v7 + v_add_u32_e32 v54, v53, v31 + v_or_b32_e32 v55, 12, v2 + v_xor_b32_e32 v56, v55, v35 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[60:61], v[92:93], 0 + v_sub_u32_e32 v44, v56, v44 + v_lshl_add_u32 v44, v44, 2, v34 + v_add_u32_e32 v57, v54, v44 + ds_read_b32 v96, v57 offset:16384 + v_or_b32_e32 v2, 28, v2 + v_xor_b32_e32 v58, v2, v35 + v_sub_u32_e32 v56, v58, v56 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[60:61], v[94:95], 0 + v_lshlrev_b32_e32 v56, 2, v56 + v_add_u32_e32 v57, v57, v56 + ds_read_b32 v97, v57 offset:16384 + v_sub_u32_e32 v41, v42, v41 + v_lshlrev_b32_e32 v41, 2, v41 + v_add_u32_e32 v59, v19, v41 + v_xor_b32_e32 v32, v32, v12 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[60:61], v[96:97], 0 + v_sub_u32_e32 v42, v32, v42 + v_lshl_add_u32 v42, v42, 2, v3 + v_add_u32_e32 v60, v59, v42 + v_xor_b32_e32 v36, v36, v6 + v_sub_u32_e32 v32, v36, v32 + v_lshl_add_u32 v32, v32, 2, v7 + v_add_u32_e32 v61, v60, v32 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[70:71], v[84:85], 0 + v_add_u32_e32 v62, 0x80, v0 + v_lshrrev_b32_e32 v62, 4, v62 + v_xor_b32_e32 v63, v62, v35 + v_sub_u32_e32 v36, v63, v36 + v_lshl_add_u32 v36, v36, 2, v34 + v_add_u32_e32 v64, v61, v36 + ds_read_b32 v98, v64 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[70:71], v[92:93], 0 + v_add_u32_e32 v65, 16, v62 + v_xor_b32_e32 v66, v65, v35 + v_sub_u32_e32 v63, v66, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add_u32_e32 v64, v64, v63 + ds_read_b32 v99, v64 + v_xor_b32_e32 v67, v62, v38 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[70:71], v[94:95], 0 + v_sub_u32_e32 v66, v67, v66 + v_lshl_add_u32 v66, v66, 2, v14 + v_add_u32_e32 v64, v64, v66 + v_xor_b32_e32 v68, v65, v39 + v_sub_u32_e32 v67, v68, v67 + v_lshl_add_u32 v67, v67, 2, v15 + v_add_u32_e32 v69, v64, v67 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[70:71], v[96:97], 0 + v_xor_b32_e32 v70, v62, v16 + v_sub_u32_e32 v68, v70, v68 + v_lshl_add_u32 v68, v68, 2, v9 + v_add_u32_e32 v71, v69, v68 + v_xor_b32_e32 v72, v65, v16 + v_sub_u32_e32 v70, v72, v70 + v_lshlrev_b32_e32 v70, 2, v70 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[98:99], v[84:85], 0 + v_add_u32_e32 v73, v71, v70 + v_xor_b32_e32 v62, v62, v12 + v_sub_u32_e32 v72, v62, v72 + v_lshl_add_u32 v72, v72, 2, v3 + v_add_u32_e32 v74, v73, v72 + v_xor_b32_e32 v65, v65, v6 + v_sub_u32_e32 v62, v65, v62 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[98:99], v[92:93], 0 + v_lshl_add_u32 v62, v62, 2, v7 + v_add_u32_e32 v75, v74, v62 + v_add_u32_e32 v0, 0xc0, v0 + v_lshrrev_b32_e32 v0, 4, v0 + v_xor_b32_e32 v76, v0, v35 + v_sub_u32_e32 v65, v76, v65 + v_lshl_add_u32 v34, v65, 2, v34 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[98:99], v[94:95], 0 + v_add_u32_e32 v65, v75, v34 + ds_read_b32 v100, v65 + v_add_u32_e32 v77, 16, v0 + v_xor_b32_e32 v35, v77, v35 + v_sub_u32_e32 v76, v35, v76 + v_lshlrev_b32_e32 v76, 2, v76 + v_add_u32_e32 v65, v65, v76 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[98:99], v[96:97], 0 + ds_read_b32 v101, v65 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[100:101], v[84:85], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[100:101], v[92:93], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[100:101], v[94:95], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[100:101], v[96:97], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[80:81], v[86:87], a[224:239] + ds_read_b32 v84, v18 offset:16384 + ds_read_b32 v85, v21 offset:16384 + ds_read_b32 v92, v43 offset:16384 + ds_read_b32 v93, v48 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[80:81], v[84:85], a[208:223] + v_xor_b32_e32 v21, v55, v38 + v_sub_u32_e32 v43, v21, v58 + v_lshl_add_u32 v43, v43, 2, v14 + v_add_u32_e32 v48, v57, v43 + ds_read_b32 v94, v48 offset:16384 + v_xor_b32_e32 v57, v2, v39 + v_sub_u32_e32 v21, v57, v21 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[80:81], v[92:93], a[192:207] + v_lshl_add_u32 v58, v21, 2, v15 + v_add_u32_e32 v21, v48, v58 + ds_read_b32 v95, v21 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[80:81], v[94:95], a[176:191] + ds_read_b32 v79, v40 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[78:79], v[86:87], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[78:79], v[84:85], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[78:79], v[92:93], a[128:143] + ds_read_b32 v80, v64 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[78:79], v[94:95], a[112:127] + ds_read_b32 v81, v69 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[80:81], v[86:87], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[80:81], v[84:85], a[80:95] + v_xor_b32_e32 v38, v0, v38 + v_sub_u32_e32 v35, v38, v35 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[80:81], v[92:93], a[64:79] + v_lshl_add_u32 v14, v35, 2, v14 + v_add_u32_e32 v35, v65, v14 + ds_read_b32 v64, v35 + v_xor_b32_e32 v39, v77, v39 + v_sub_u32_e32 v38, v39, v38 + v_lshl_add_u32 v15, v38, 2, v15 + v_add_u32_e32 v35, v35, v15 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[80:81], v[94:95], a[48:63] + ds_read_b32 v65, v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[64:65], v[86:87], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[64:65], v[84:85], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[64:65], v[92:93], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[64:65], v[94:95], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[82:83], v[88:89], a[224:239] + ds_read_b32 v64, v26 offset:16384 + ds_read_b32 v65, v28 offset:16384 + ds_read_b32 v78, v50 offset:16384 + ds_read_b32 v79, v52 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[82:83], v[64:65], a[208:223] + v_xor_b32_e32 v26, v55, v16 + v_sub_u32_e32 v28, v26, v57 + v_lshl_add_u32 v28, v28, 2, v9 + v_add_u32_e32 v21, v21, v28 + ds_read_b32 v80, v21 offset:16384 + v_xor_b32_e32 v38, v2, v16 + v_sub_u32_e32 v26, v38, v26 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[82:83], v[78:79], a[192:207] + v_lshlrev_b32_e32 v26, 2, v26 + v_add_u32_e32 v40, v21, v26 + ds_read_b32 v81, v40 offset:16384 + ds_read_b32 v84, v19 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[82:83], v[80:81], a[176:191] + ds_read_b32 v85, v59 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[84:85], v[88:89], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[84:85], v[64:65], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[84:85], v[78:79], a[128:143] + ds_read_b32 v82, v71 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[84:85], v[80:81], a[112:127] + ds_read_b32 v83, v73 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[82:83], v[88:89], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[82:83], v[64:65], a[80:95] + v_xor_b32_e32 v19, v0, v16 + v_sub_u32_e32 v21, v19, v39 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[82:83], v[78:79], a[64:79] + v_lshl_add_u32 v9, v21, 2, v9 + v_add_u32_e32 v21, v35, v9 + ds_read_b32 v84, v21 + v_xor_b32_e32 v16, v77, v16 + v_sub_u32_e32 v19, v16, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add_u32_e32 v35, v21, v19 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[82:83], v[80:81], a[48:63] + ds_read_b32 v85, v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[84:85], v[88:89], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[84:85], v[64:65], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[84:85], v[78:79], a[0:15] + ds_read_b32 v21, v13 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[84:85], v[80:81], a[240:255] + v_add3_u32 v13, v24, v18, v23 + v_add3_u32 v13, v25, v13, v27 + ds_read_b32 v24, v29 offset:16384 + ds_read_b32 v25, v30 offset:16384 + v_add3_u32 v13, v17, v13, v22 + v_add3_u32 v13, v13, v33, v45 + v_add3_u32 v13, v46, v13, v47 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[20:21], v[90:91], a[224:239] + v_add3_u32 v13, v49, v13, v51 + ds_read_b32 v22, v53 offset:16384 + ds_read_b32 v23, v54 offset:16384 + v_add3_u32 v13, v31, v13, v44 + v_add3_u32 v13, v13, v56, v43 + v_add3_u32 v13, v58, v13, v28 + v_xor_b32_e32 v17, v55, v12 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[20:21], v[24:25], a[208:223] + v_sub_u32_e32 v18, v17, v38 + v_lshl_add_u32 v18, v18, 2, v3 + v_add3_u32 v13, v26, v13, v18 + v_add_u32_e32 v18, v40, v18 + ds_read_b32 v26, v18 offset:16384 + v_xor_b32_e32 v2, v2, v6 + v_sub_u32_e32 v2, v2, v17 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[20:21], v[22:23], a[192:207] + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v2, v7, v13 + ds_read_b32 v27, v2 offset:16384 + ds_read_b32 v28, v60 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[20:21], v[26:27], a[176:191] + ds_read_b32 v29, v61 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[28:29], v[90:91], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[28:29], v[24:25], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[28:29], v[22:23], a[128:143] + ds_read_b32 v20, v74 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[28:29], v[26:27], a[112:127] + ds_read_b32 v21, v75 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[20:21], v[90:91], a[96:111] + v_add3_u32 v2, v10, v8, v11 + v_add3_u32 v2, v41, v2, v42 + v_add3_u32 v2, v32, v2, v36 + v_add3_u32 v2, v2, v63, v66 + v_add3_u32 v2, v67, v2, v68 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[20:21], v[24:25], a[80:95] + v_add3_u32 v2, v70, v2, v72 + v_add3_u32 v2, v62, v2, v34 + v_add3_u32 v2, v2, v76, v14 + v_add3_u32 v2, v15, v2, v9 + v_xor_b32_e32 v0, v0, v12 + v_sub_u32_e32 v8, v0, v16 + v_lshl_add_u32 v3, v8, 2, v3 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[20:21], v[22:23], a[64:79] + v_add3_u32 v2, v19, v2, v3 + v_xor_b32_e32 v6, v77, v6 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v0, v0, v7, v2 + ds_read_b32 v7, v0 + v_add_u32_e32 v0, v35, v3 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[20:21], v[26:27], a[48:63] + ds_read_b32 v6, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[6:7], v[90:91], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[6:7], v[24:25], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[6:7], v[22:23], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[6:7], v[26:27], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB19_3 + s_branch .LBB19_10 +.LBB19_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB19_3: + v_readfirstlane_b32 s15, v227 + v_lshlrev_b32_e32 v2, 4, v4 + s_lshr_b32 s26, s15, 2 + v_mov_b32_e32 v0, s26 + v_and_b32_e32 v1, 0x3ffffffc, v1 + v_and_b32_e32 v0, 0x3ffffff0, v0 + v_add_u32_e32 v9, v0, v1 + v_or_b32_e32 v0, s20, v2 + v_mad_u64_u32 v[34:35], s[18:19], v9, s23, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[14:17], v34, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v34 + buffer_load_dwordx4 v[18:21], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[22:25], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 12, v5 + v_lshlrev_b32_e32 v11, 3, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s24, 0x5010400 + s_mov_b32 s18, 0x5040100 + s_mov_b32 s19, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_lshl_or_b32 v13, v4, 7, v0 + v_or_b32_e32 v0, s21, v2 + s_lshr_b32 s28, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s29, s26, 0x3ffffff0 + s_and_b32 s26, s26, 0x3fffffe0 + v_and_or_b32 v2, s28, 32, v37 + v_or_b32_e32 v7, s26, v37 + v_add_u32_e32 v3, s29, v1 + v_lshrrev_b32_e32 v6, 4, v2 + v_lshrrev_b32_e32 v8, 4, v7 + v_mad_u64_u32 v[2:3], s[28:29], v3, s22, v[0:1] + v_xor_b32_e32 v3, v6, v4 + v_xor_b32_e32 v0, v8, v4 + v_lshl_or_b32 v56, v3, 2, v13 + v_add_u32_e32 v10, s22, v2 + buffer_load_dwordx4 v[30:33], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[38:41], v10, s[12:15], 0 offen + v_add_u32_e32 v10, s22, v10 + v_add_u32_e32 v12, s22, v10 + buffer_load_dwordx4 v[42:45], v10, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v12, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v14, v14, s27 + v_perm_b32 v12, v15, v15, s27 + v_perm_b32 v14, v16, v16, s27 + v_perm_b32 v15, v17, v17, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v16, v18, v18, s27 + v_perm_b32 v17, v19, v19, s27 + v_perm_b32 v18, v20, v20, s27 + v_perm_b32 v19, v21, v21, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v20, v22, v22, s27 + v_perm_b32 v21, v23, v23, s27 + v_perm_b32 v22, v24, v24, s27 + v_perm_b32 v23, v25, v25, s27 + v_perm_b32 v24, v16, v10, s24 + v_perm_b32 v10, v16, v10, s25 + v_perm_b32 v16, v17, v12, s24 + v_perm_b32 v12, v17, v12, s25 + v_perm_b32 v17, v18, v14, s24 + v_perm_b32 v14, v18, v14, s25 + v_perm_b32 v18, v19, v15, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v25, v26, v26, s27 + v_perm_b32 v26, v27, v27, s27 + v_perm_b32 v27, v28, v28, s27 + v_perm_b32 v28, v29, v29, s27 + v_perm_b32 v29, v25, v20, s24 + v_perm_b32 v20, v25, v20, s25 + v_perm_b32 v25, v26, v21, s24 + v_perm_b32 v21, v26, v21, s25 + v_perm_b32 v26, v27, v22, s24 + v_perm_b32 v22, v27, v22, s25 + v_perm_b32 v27, v28, v23, s24 + v_perm_b32 v35, v29, v24, s18 + v_perm_b32 v24, v29, v24, s19 + v_perm_b32 v29, v20, v10, s18 + v_perm_b32 v10, v20, v10, s19 + v_perm_b32 v20, v25, v16, s18 + v_perm_b32 v16, v25, v16, s19 + v_perm_b32 v25, v21, v12, s18 + v_perm_b32 v12, v21, v12, s19 + v_perm_b32 v21, v26, v17, s18 + v_perm_b32 v17, v26, v17, s19 + v_perm_b32 v26, v22, v14, s18 + v_perm_b32 v14, v22, v14, s19 + v_perm_b32 v22, v27, v18, s18 + v_perm_b32 v18, v27, v18, s19 + v_perm_b32 v15, v19, v15, s25 + v_perm_b32 v19, v28, v23, s25 + v_perm_b32 v23, v19, v15, s18 + v_perm_b32 v15, v19, v15, s19 + v_lshrrev_b32_e32 v19, 1, v9 + v_and_b32_e32 v19, 16, v19 + v_xor_b32_e32 v27, v19, v37 + v_lshlrev_b32_e32 v28, 9, v9 + v_and_b32_e32 v28, 0x3000, v28 + v_lshlrev_b32_e32 v9, 6, v9 + s_movk_i32 s26, 0xf800 + v_and_b32_e32 v9, 0xfffff800, v9 + v_add_u32_e32 v9, v28, v9 + v_lshl_or_b32 v9, v27, 2, v9 + ds_write_b32 v9, v35 + v_or_b32_e32 v28, 1, v19 + v_xor_b32_e32 v28, v28, v37 + v_sub_u32_e32 v27, v28, v27 + v_lshl_add_u32 v27, v27, 2, v9 + ds_write_b32 v27, v24 offset:128 + v_or_b32_e32 v24, 2, v19 + v_xor_b32_e32 v24, v24, v37 + v_sub_u32_e32 v28, v24, v28 + v_lshlrev_b32_e32 v28, 2, v28 + s_movk_i32 s28, 0x80 + v_add3_u32 v28, v27, s28, v28 + ds_write_b32 v28, v29 offset:128 + v_or_b32_e32 v29, 3, v19 + v_xor_b32_e32 v29, v29, v37 + v_sub_u32_e32 v24, v29, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v28, s28, v24 + ds_write_b32 v24, v10 offset:128 + v_or_b32_e32 v10, 4, v19 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v29, v10, v29 + v_lshlrev_b32_e32 v29, 2, v29 + v_add3_u32 v29, v24, s28, v29 + ds_write_b32 v29, v20 offset:128 + v_or_b32_e32 v20, 5, v19 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v10, v20, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v29, s28, v10 + ds_write_b32 v10, v16 offset:128 + v_or_b32_e32 v16, 6, v19 + v_xor_b32_e32 v16, v16, v37 + v_sub_u32_e32 v20, v16, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v10, s28, v20 + ds_write_b32 v20, v25 offset:128 + v_or_b32_e32 v25, 7, v19 + v_xor_b32_e32 v25, v25, v37 + v_sub_u32_e32 v16, v25, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v20, s28, v16 + ds_write_b32 v16, v12 offset:128 + v_or_b32_e32 v12, 8, v19 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v25, v12, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v16, s28, v25 + ds_write_b32 v25, v21 offset:128 + v_or_b32_e32 v21, 9, v19 + v_xor_b32_e32 v21, v21, v37 + v_sub_u32_e32 v12, v21, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v25, s28, v12 + ds_write_b32 v12, v17 offset:128 + v_or_b32_e32 v17, 10, v19 + v_xor_b32_e32 v17, v17, v37 + v_sub_u32_e32 v21, v17, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v12, s28, v21 + ds_write_b32 v21, v26 offset:128 + v_or_b32_e32 v26, 11, v19 + v_xor_b32_e32 v26, v26, v37 + v_sub_u32_e32 v17, v26, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v21, s28, v17 + ds_write_b32 v17, v14 offset:128 + v_or_b32_e32 v14, 12, v19 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v26, v14, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v17, s28, v26 + ds_write_b32 v26, v22 offset:128 + v_or_b32_e32 v22, 13, v19 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v14, v22, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v26, s28, v14 + ds_write_b32 v14, v18 offset:128 + v_or_b32_e32 v18, 14, v19 + v_xor_b32_e32 v18, v18, v37 + v_sub_u32_e32 v22, v18, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v14, s28, v22 + ds_write_b32 v22, v23 offset:128 + v_or_b32_e32 v19, 15, v19 + v_xor_b32_e32 v19, v19, v37 + v_sub_u32_e32 v18, v19, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v22, s28, v18 + ds_write_b32 v18, v15 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v15, v30, v30, s27 + v_perm_b32 v19, v31, v31, s27 + v_perm_b32 v23, v32, v32, s27 + v_perm_b32 v30, v33, v33, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v31, v38, v38, s27 + v_perm_b32 v32, v39, v39, s27 + v_perm_b32 v33, v40, v40, s27 + v_perm_b32 v35, v41, v41, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v36, v42, v42, s27 + v_perm_b32 v38, v43, v43, s27 + v_perm_b32 v39, v44, v44, s27 + v_perm_b32 v40, v45, v45, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v41, v46, v46, s27 + v_perm_b32 v42, v47, v47, s27 + v_perm_b32 v43, v48, v48, s27 + v_perm_b32 v44, v49, v49, s27 + v_perm_b32 v45, v31, v15, s24 + v_perm_b32 v46, v41, v36, s24 + v_perm_b32 v47, v46, v45, s18 + v_perm_b32 v45, v46, v45, s19 + v_perm_b32 v15, v31, v15, s25 + v_perm_b32 v31, v41, v36, s25 + v_perm_b32 v36, v31, v15, s18 + v_perm_b32 v15, v31, v15, s19 + v_perm_b32 v31, v32, v19, s24 + v_perm_b32 v41, v42, v38, s24 + v_perm_b32 v46, v41, v31, s18 + v_perm_b32 v31, v41, v31, s19 + v_perm_b32 v19, v32, v19, s25 + v_perm_b32 v32, v42, v38, s25 + v_perm_b32 v38, v32, v19, s18 + v_perm_b32 v19, v32, v19, s19 + v_perm_b32 v32, v33, v23, s24 + v_perm_b32 v41, v43, v39, s24 + v_perm_b32 v42, v41, v32, s18 + v_perm_b32 v32, v41, v32, s19 + v_perm_b32 v23, v33, v23, s25 + v_perm_b32 v33, v43, v39, s25 + v_perm_b32 v39, v33, v23, s18 + v_perm_b32 v23, v33, v23, s19 + v_perm_b32 v33, v35, v30, s24 + v_perm_b32 v41, v44, v40, s24 + v_perm_b32 v43, v41, v33, s18 + v_perm_b32 v33, v41, v33, s19 + v_perm_b32 v30, v35, v30, s25 + v_perm_b32 v35, v44, v40, s25 + v_perm_b32 v40, v35, v30, s18 + v_perm_b32 v30, v35, v30, s19 + ds_write_b32 v9, v47 offset:16384 + ds_write_b32 v27, v45 offset:16512 + ds_write_b32 v28, v36 offset:16512 + ds_write_b32 v24, v15 offset:16512 + ds_write_b32 v29, v46 offset:16512 + ds_write_b32 v10, v31 offset:16512 + ds_write_b32 v20, v38 offset:16512 + ds_write_b32 v16, v19 offset:16512 + ds_write_b32 v25, v42 offset:16512 + ds_write_b32 v12, v32 offset:16512 + ds_write_b32 v21, v39 offset:16512 + ds_write_b32 v17, v23 offset:16512 + ds_write_b32 v26, v43 offset:16512 + ds_write_b32 v14, v33 offset:16512 + ds_write_b32 v22, v40 offset:16512 + ds_write_b32 v18, v30 offset:16512 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v18, 3, v11 + v_add_u32_e32 v19, 16, v8 + v_add_u32_e32 v25, 16, v11 + v_add_u32_e32 v24, 20, v11 + v_or_b32_e32 v10, 16, v4 + v_add_u32_e32 v23, 36, v11 + v_add_u32_e32 v22, 48, v11 + v_add_u32_e32 v21, 52, v11 + v_add_u32_e32 v20, 64, v7 + v_or_b32_e32 v17, 16, v6 + v_or_b32_e32 v16, 4, v6 + v_or_b32_e32 v15, 20, v6 + v_or_b32_e32 v14, 8, v6 + v_or_b32_e32 v12, 24, v6 + v_or_b32_e32 v11, 12, v6 + v_or_b32_e32 v9, 28, v6 + s_cbranch_vccnz .LBB19_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit1774.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v26, v19, v4 + v_sub_u32_e32 v27, v18, v5 + v_lshlrev_b32_e32 v27, 12, v27 + v_lshlrev_b32_e32 v28, 2, v26 + v_add3_u32 v78, v27, v13, v28 + v_lshrrev_b32_e32 v28, 5, v25 + v_lshrrev_b16_e32 v29, 3, v25 + v_and_b32_e32 v29, 3, v29 + v_sub_u16_e32 v30, v29, v18 + v_bfe_i32 v30, v30, 0, 16 + v_lshl_or_b32 v31, v28, 4, v4 + v_xor_b32_e32 v32, v8, v31 + v_sub_u32_e32 v26, v32, v26 + v_lshlrev_b32_e32 v33, 11, v28 + v_lshlrev_b32_e32 v26, 2, v26 + v_lshl_or_b32 v30, v30, 12, v33 + v_add3_u32 v44, v26, v30, v78 + v_lshrrev_b32_e32 v26, 5, v24 + v_sub_u32_e32 v28, v26, v28 + v_lshrrev_b16_e32 v33, 3, v24 + v_and_b32_e32 v33, 3, v33 + v_sub_u16_e32 v29, v33, v29 + v_bfe_i32 v29, v29, 0, 16 + v_lshl_or_b32 v35, v26, 4, v4 + v_xor_b32_e32 v36, v19, v35 + v_sub_u32_e32 v32, v36, v32 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v32, 2, v32 + v_lshl_add_u32 v28, v29, 12, v28 + v_add3_u32 v45, v32, v28, v44 + v_sub_u16_e32 v29, v18, v33 + v_bfe_i32 v29, v29, 0, 16 + v_xor_b32_e32 v32, v8, v10 + v_sub_u32_e32 v33, v32, v36 + v_lshlrev_b32_e32 v26, 11, v26 + v_xor_b32_e32 v26, 0x800, v26 + v_lshlrev_b32_e32 v33, 2, v33 + v_lshl_or_b32 v26, v29, 12, v26 + v_add3_u32 v40, v33, v26, v45 + v_lshrrev_b32_e32 v29, 5, v23 + v_lshlrev_b32_e32 v33, 11, v29 + v_lshrrev_b16_e32 v36, 3, v23 + v_and_b32_e32 v36, 3, v36 + v_sub_u16_e32 v38, v36, v18 + v_lshl_or_b32 v39, v29, 4, v4 + v_and_b32_e32 v75, 31, v39 + v_xor_b32_e32 v39, v19, v75 + v_sub_u32_e32 v32, v39, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_mov_b32_e32 v42, 12 + v_lshlrev_b32_sdwa v38, v42, sext(v38) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v33, v33, v38, s26 + v_add3_u32 v41, v32, v33, v40 + v_lshrrev_b32_e32 v32, 5, v22 + v_sub_u32_e32 v29, v32, v29 + v_lshrrev_b16_e32 v38, 3, v22 + v_and_b32_e32 v43, 3, v38 + v_sub_u16_e32 v36, v43, v36 + v_bfe_i32 v36, v36, 0, 16 + v_lshl_or_b32 v38, v32, 4, v4 + v_and_b32_e32 v76, 31, v38 + v_xor_b32_e32 v46, v8, v76 + v_sub_u32_e32 v38, v46, v39 + v_lshlrev_b32_e32 v29, 11, v29 + v_lshlrev_b32_e32 v38, 2, v38 + v_lshl_add_u32 v29, v36, 12, v29 + v_add3_u32 v38, v38, v29, v41 + v_lshrrev_b32_e32 v36, 5, v21 + v_sub_u32_e32 v32, v36, v32 + v_lshrrev_b16_e32 v39, 3, v21 + v_and_b32_e32 v47, 3, v39 + v_sub_u16_e32 v39, v47, v43 + v_bfe_i32 v39, v39, 0, 16 + v_lshl_or_b32 v43, v36, 4, v4 + v_and_b32_e32 v97, 31, v43 + v_xor_b32_e32 v43, v19, v97 + v_sub_u32_e32 v46, v43, v46 + v_lshlrev_b32_e32 v32, 11, v32 + v_lshlrev_b32_e32 v46, 2, v46 + v_lshl_add_u32 v32, v39, 12, v32 + v_add3_u32 v39, v46, v32, v38 + v_lshrrev_b32_e32 v46, 4, v20 + v_sub_u16_e32 v47, v18, v47 + v_xor_b32_e32 v48, v46, v4 + v_sub_u32_e32 v43, v48, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_lshlrev_b32_sdwa v42, v42, sext(v47) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v36, 11, v36 + v_sub_u32_e32 v36, v42, v36 + v_add3_u32 v88, v43, v36, v39 + v_add_u32_e32 v43, 16, v46 + v_xor_b32_e32 v42, v43, v4 + v_sub_u32_e32 v47, v42, v48 + v_lshl_add_u32 v89, v47, 2, v88 + v_xor_b32_e32 v47, v46, v31 + v_sub_u32_e32 v42, v47, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v53, v42, v30, v89 + v_xor_b32_e32 v42, v43, v35 + v_sub_u32_e32 v47, v42, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v55, v47, v28, v53 + v_xor_b32_e32 v47, v46, v10 + v_sub_u32_e32 v42, v47, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v48, v42, v26, v55 + v_xor_b32_e32 v42, v43, v75 + v_sub_u32_e32 v47, v42, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v49, v47, v33, v48 + v_xor_b32_e32 v46, v46, v76 + v_sub_u32_e32 v42, v46, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v42, v42, v29, v49 + v_xor_b32_e32 v47, v43, v97 + v_sub_u32_e32 v43, v47, v46 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v43, v43, v32, v42 + v_add_u32_e32 v46, 0x80, v7 + v_lshrrev_b32_e32 v46, 4, v46 + v_xor_b32_e32 v50, v46, v4 + v_sub_u32_e32 v47, v50, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v90, v47, v36, v43 + v_add_u32_e32 v47, 16, v46 + v_xor_b32_e32 v51, v47, v4 + v_sub_u32_e32 v50, v51, v50 + v_lshl_add_u32 v91, v50, 2, v90 + v_xor_b32_e32 v50, v46, v31 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v59, v51, v30, v91 + v_xor_b32_e32 v51, v47, v35 + v_sub_u32_e32 v50, v51, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v62, v50, v28, v59 + v_xor_b32_e32 v50, v46, v10 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v52, v51, v26, v62 + v_xor_b32_e32 v51, v47, v75 + v_sub_u32_e32 v50, v51, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v54, v50, v33, v52 + v_xor_b32_e32 v50, v46, v76 + v_sub_u32_e32 v46, v50, v51 + v_lshlrev_b32_e32 v46, 2, v46 + v_add3_u32 v46, v46, v29, v54 + v_xor_b32_e32 v51, v47, v97 + v_sub_u32_e32 v47, v51, v50 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v47, v47, v32, v46 + v_add_u32_e32 v50, 0xc0, v7 + v_lshrrev_b32_e32 v50, 4, v50 + v_xor_b32_e32 v57, v50, v4 + v_sub_u32_e32 v51, v57, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v92, v51, v36, v47 + v_add_u32_e32 v58, 16, v50 + v_xor_b32_e32 v51, v58, v4 + v_sub_u32_e32 v57, v51, v57 + v_lshl_add_u32 v93, v57, 2, v92 + v_xor_b32_e32 v57, v50, v31 + v_sub_u32_e32 v51, v57, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v64, v51, v30, v93 + v_xor_b32_e32 v51, v58, v35 + v_sub_u32_e32 v57, v51, v57 + v_lshlrev_b32_e32 v57, 2, v57 + v_add3_u32 v66, v57, v28, v64 + v_xor_b32_e32 v60, v50, v10 + v_sub_u32_e32 v51, v60, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v57, v51, v26, v66 + v_xor_b32_e32 v51, v58, v75 + v_sub_u32_e32 v60, v51, v60 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v60, v60, v33, v57 + v_xor_b32_e32 v50, v50, v76 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v51, v51, v29, v60 + v_xor_b32_e32 v58, v58, v97 + v_sub_u32_e32 v50, v58, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v50, v50, v32, v51 + v_xor_b32_e32 v58, v17, v4 + v_sub_u32_e32 v61, v58, v3 + v_lshlrev_b32_e32 v61, 2, v61 + v_add3_u32 v94, v56, v27, v61 + v_xor_b32_e32 v27, v6, v31 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v73, v58, v30, v94 + v_xor_b32_e32 v58, v17, v35 + v_sub_u32_e32 v27, v58, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v74, v27, v28, v73 + v_xor_b32_e32 v27, v6, v10 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v67, v58, v26, v74 + v_xor_b32_e32 v58, v17, v75 + v_sub_u32_e32 v27, v58, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v68, v27, v33, v67 + v_xor_b32_e32 v27, v6, v76 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v58, v58, v29, v68 + v_xor_b32_e32 v63, v17, v97 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v61, v27, v32, v58 + v_xor_b32_e32 v27, v16, v4 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v95, v63, v36, v61 + v_xor_b32_e32 v63, v15, v4 + v_sub_u32_e32 v27, v63, v27 + v_lshl_add_u32 v96, v27, 2, v95 + v_xor_b32_e32 v27, v16, v31 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v80, v63, v30, v96 + v_xor_b32_e32 v63, v15, v35 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v81, v27, v28, v80 + v_xor_b32_e32 v27, v16, v10 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v71, v63, v26, v81 + v_xor_b32_e32 v63, v15, v75 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v72, v27, v33, v71 + v_xor_b32_e32 v27, v16, v76 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v63, v63, v29, v72 + v_xor_b32_e32 v69, v15, v97 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v65, v27, v32, v63 + v_xor_b32_e32 v27, v14, v4 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v98, v69, v36, v65 + v_xor_b32_e32 v69, v12, v4 + v_sub_u32_e32 v27, v69, v27 + v_lshl_add_u32 v99, v27, 2, v98 + v_xor_b32_e32 v27, v14, v31 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v84, v69, v30, v99 + v_xor_b32_e32 v69, v12, v35 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v85, v27, v28, v84 + v_xor_b32_e32 v27, v14, v10 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v77, v69, v26, v85 + v_xor_b32_e32 v69, v12, v75 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v79, v27, v33, v77 + v_xor_b32_e32 v27, v14, v76 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v69, v69, v29, v79 + v_xor_b32_e32 v82, v12, v97 + v_sub_u32_e32 v27, v82, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v70, v27, v32, v69 + v_xor_b32_e32 v27, v11, v4 + v_sub_u32_e32 v82, v27, v82 + v_lshlrev_b32_e32 v82, 2, v82 + v_add3_u32 v100, v82, v36, v70 + v_xor_b32_e32 v36, v9, v4 + v_sub_u32_e32 v27, v36, v27 + v_lshl_add_u32 v101, v27, 2, v100 + v_xor_b32_e32 v27, v11, v31 + v_sub_u32_e32 v31, v27, v36 + v_lshlrev_b32_e32 v31, 2, v31 + v_add3_u32 v86, v31, v30, v101 + v_xor_b32_e32 v30, v9, v35 + v_sub_u32_e32 v27, v30, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v87, v27, v28, v86 + v_xor_b32_e32 v27, v11, v10 + v_sub_u32_e32 v28, v27, v30 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v82, v28, v26, v87 + v_xor_b32_e32 v26, v9, v75 + v_sub_u32_e32 v27, v26, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v83, v27, v33, v82 + v_xor_b32_e32 v27, v11, v76 + v_sub_u32_e32 v26, v27, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v75, v26, v29, v83 + v_xor_b32_e32 v26, v9, v97 + v_sub_u32_e32 v26, v26, v27 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v76, v26, v32, v75 + s_mov_b64 s[2:3], 0 + s_branch .LBB19_6 +.LBB19_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 +.LBB19_6: ; %Flow120 + v_lshl_add_u32 v97, v0, 2, v13 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_cbranch_vccnz .LBB19_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2753.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v35, v2 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s18, s6, 6 + s_lshl_b32 s2, s22, 6 + s_lshl_b32 s3, s23, 6 + v_xor_b32_e32 v0, v19, v4 + v_sub_u32_e32 v2, v18, v5 + v_lshlrev_b32_e32 v2, 12, v2 + v_lshlrev_b32_e32 v5, 2, v0 + v_add3_u32 v78, v2, v13, v5 + v_lshrrev_b32_e32 v5, 5, v25 + v_lshrrev_b16_e32 v13, 3, v25 + v_and_b32_e32 v13, 3, v13 + v_sub_u16_e32 v25, v13, v18 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v26, v5, 4, v4 + v_xor_b32_e32 v27, v8, v26 + v_sub_u32_e32 v0, v27, v0 + v_lshlrev_b32_e32 v28, 11, v5 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v25, v25, 12, v28 + v_add3_u32 v44, v0, v25, v78 + v_lshrrev_b32_e32 v0, 5, v24 + v_sub_u32_e32 v5, v0, v5 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v13, v24, v13 + v_bfe_i32 v13, v13, 0, 16 + v_lshl_or_b32 v28, v0, 4, v4 + v_xor_b32_e32 v29, v19, v28 + v_sub_u32_e32 v27, v29, v27 + v_lshlrev_b32_e32 v5, 11, v5 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_add_u32 v5, v13, 12, v5 + v_add3_u32 v45, v27, v5, v44 + v_sub_u16_e32 v13, v18, v24 + v_bfe_i32 v13, v13, 0, 16 + v_xor_b32_e32 v24, v8, v10 + v_sub_u32_e32 v27, v24, v29 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_or_b32 v0, v13, 12, v0 + v_add3_u32 v40, v27, v0, v45 + v_lshrrev_b32_e32 v13, 5, v23 + v_lshlrev_b32_e32 v27, 11, v13 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v29, v23, v18 + v_lshl_or_b32 v30, v13, 4, v4 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v31, v19, v30 + v_sub_u32_e32 v24, v31, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_mov_b32_e32 v32, 12 + v_lshlrev_b32_sdwa v29, v32, sext(v29) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v27, v27, v29, s6 + v_add3_u32 v41, v24, v27, v40 + v_lshrrev_b32_e32 v24, 5, v22 + v_sub_u32_e32 v13, v24, v13 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v23, v22, v23 + v_bfe_i32 v23, v23, 0, 16 + v_lshl_or_b32 v29, v24, 4, v4 + v_and_b32_e32 v29, 31, v29 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v31, v8, v31 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_add_u32 v13, v23, 12, v13 + v_add3_u32 v38, v31, v13, v41 + v_lshrrev_b32_e32 v23, 5, v21 + v_sub_u32_e32 v24, v23, v24 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v22, v21, v22 + v_bfe_i32 v22, v22, 0, 16 + v_lshl_or_b32 v31, v23, 4, v4 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v24, 11, v24 + v_lshlrev_b32_e32 v8, 2, v8 + v_lshl_add_u32 v22, v22, 12, v24 + v_add3_u32 v39, v8, v22, v38 + v_lshrrev_b32_e32 v8, 4, v20 + v_sub_u16_e32 v18, v18, v21 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshlrev_b32_sdwa v18, v32, sext(v18) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v21, 11, v23 + v_sub_u32_e32 v18, v18, v21 + v_add3_u32 v88, v19, v18, v39 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v89, v20, 2, v88 + v_xor_b32_e32 v20, v8, v26 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v53, v21, v25, v89 + v_xor_b32_e32 v21, v19, v28 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v55, v20, v5, v53 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v48, v21, v0, v55 + v_xor_b32_e32 v21, v19, v30 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v49, v20, v27, v48 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v42, v20, v13, v49 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v43, v8, v22, v42 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v8, 0x80, v7 + v_lshrrev_b32_e32 v8, 4, v8 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v90, v19, v18, v43 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v91, v20, 2, v90 + v_xor_b32_e32 v20, v8, v26 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v59, v21, v25, v91 + v_xor_b32_e32 v21, v19, v28 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v62, v20, v5, v59 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v52, v21, v0, v62 + v_xor_b32_e32 v21, v19, v30 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v54, v20, v27, v52 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v46, v20, v13, v54 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v47, v8, v22, v46 + v_add_u32_e32 v7, 0xc0, v7 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v8, v7, v4 + v_sub_u32_e32 v19, v8, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v92, v19, v18, v47 + v_add_u32_e32 v19, 16, v7 + v_xor_b32_e32 v20, v19, v4 + v_sub_u32_e32 v8, v20, v8 + v_lshl_add_u32 v93, v8, 2, v92 + v_xor_b32_e32 v8, v7, v26 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v64, v20, v25, v93 + v_xor_b32_e32 v20, v19, v28 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v66, v8, v5, v64 + v_xor_b32_e32 v8, v7, v10 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v57, v20, v0, v66 + v_xor_b32_e32 v20, v19, v30 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v60, v8, v27, v57 + v_xor_b32_e32 v7, v7, v29 + v_sub_u32_e32 v8, v7, v20 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v51, v8, v13, v60 + v_xor_b32_e32 v8, v19, v31 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v50, v7, v22, v51 + v_xor_b32_e32 v7, v17, v4 + v_sub_u32_e32 v3, v7, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v94, v56, v2, v3 + v_xor_b32_e32 v2, v6, v26 + v_sub_u32_e32 v3, v2, v7 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v73, v3, v25, v94 + v_xor_b32_e32 v3, v17, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v74, v2, v5, v73 + v_xor_b32_e32 v2, v6, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v67, v3, v0, v74 + v_xor_b32_e32 v3, v17, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v68, v2, v27, v67 + v_xor_b32_e32 v2, v6, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v58, v3, v13, v68 + v_xor_b32_e32 v3, v17, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v61, v2, v22, v58 + v_xor_b32_e32 v2, v16, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v95, v3, v18, v61 + v_xor_b32_e32 v3, v15, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v96, v2, 2, v95 + v_xor_b32_e32 v2, v16, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v80, v3, v25, v96 + v_xor_b32_e32 v3, v15, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v81, v2, v5, v80 + v_xor_b32_e32 v2, v16, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v71, v3, v0, v81 + v_xor_b32_e32 v3, v15, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v72, v2, v27, v71 + v_xor_b32_e32 v2, v16, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v63, v3, v13, v72 + v_xor_b32_e32 v3, v15, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v65, v2, v22, v63 + v_xor_b32_e32 v2, v14, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v98, v3, v18, v65 + v_xor_b32_e32 v3, v12, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v99, v2, 2, v98 + v_xor_b32_e32 v2, v14, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v84, v3, v25, v99 + v_xor_b32_e32 v3, v12, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v85, v2, v5, v84 + v_xor_b32_e32 v2, v14, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v77, v3, v0, v85 + v_xor_b32_e32 v3, v12, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v79, v2, v27, v77 + v_xor_b32_e32 v2, v14, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v69, v3, v13, v79 + v_xor_b32_e32 v3, v12, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v70, v2, v22, v69 + v_xor_b32_e32 v2, v11, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v100, v3, v18, v70 + v_xor_b32_e32 v3, v9, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v101, v2, 2, v100 + v_xor_b32_e32 v2, v11, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v86, v3, v25, v101 + v_xor_b32_e32 v3, v9, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v87, v2, v5, v86 + v_xor_b32_e32 v2, v11, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v82, v3, v0, v87 + v_xor_b32_e32 v0, v9, v30 + v_sub_u32_e32 v2, v0, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v83, v2, v27, v82 + v_xor_b32_e32 v2, v11, v29 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v75, v0, v13, v83 + v_xor_b32_e32 v0, v9, v31 + v_sub_u32_e32 v0, v0, v2 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v76, v0, v22, v75 + s_add_i32 s18, s18, 1 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_mov_b32 s19, 0x3020504 + s_mov_b32 s23, 0x5010400 + s_mov_b32 s24, 0x5040100 + s_mov_b32 s25, 0x7060302 + s_mov_b32 s26, 0x7030602 +.LBB19_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2753.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v35, s2, v35 + v_add_u32_e32 v34, s3, v34 + buffer_load_dwordx4 v[26:29], v34, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v34 + buffer_load_dwordx4 v[18:21], v35, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v35 + v_add_u32_e32 v3, s7, v0 + buffer_load_dwordx4 v[22:25], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[30:33], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v3, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v3 + buffer_load_dwordx4 v[10:13], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[6:9], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v2, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v120, v88 + ds_read_b32 v122, v97 + ds_read_b32 v123, v78 + ds_read_b32 v110, v44 + ds_read_b32 v111, v45 + ds_read_b32 v106, v40 + ds_read_b32 v107, v41 + ds_read_b32 v104, v38 + ds_read_b32 v116, v56 offset:16384 + ds_read_b32 v118, v95 offset:16384 + ds_read_b32 v119, v96 offset:16384 + ds_read_b32 v112, v80 offset:16384 + ds_read_b32 v117, v94 offset:16384 + ds_read_b32 v114, v73 offset:16384 + ds_read_b32 v115, v74 offset:16384 + ds_read_b32 v108, v67 offset:16384 + ds_read_b32 v109, v68 offset:16384 + ds_read_b32 v102, v58 offset:16384 + ds_read_b32 v103, v61 offset:16384 + ds_read_b32 v125, v50 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[122:123], v[116:117], a[64:79] + ds_read_b32 v113, v81 offset:16384 + ds_read_b32 v126, v71 offset:16384 + ds_read_b32 v127, v72 offset:16384 + ds_read_b32 v128, v63 offset:16384 + ds_read_b32 v129, v65 offset:16384 + ds_read_b32 v130, v98 offset:16384 + ds_read_b32 v131, v99 offset:16384 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[122:123], v[118:119], a[80:95] + ds_read_b32 v132, v84 offset:16384 + ds_read_b32 v133, v85 offset:16384 + ds_read_b32 v134, v77 offset:16384 + ds_read_b32 v135, v79 offset:16384 + ds_read_b32 v136, v69 offset:16384 + ds_read_b32 v137, v70 offset:16384 + ds_read_b32 v138, v100 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[122:123], v[130:131], a[96:111] + ds_read_b32 v139, v101 offset:16384 + ds_read_b32 v140, v86 offset:16384 + ds_read_b32 v141, v87 offset:16384 + ds_read_b32 v142, v82 offset:16384 + ds_read_b32 v143, v83 offset:16384 + ds_read_b32 v144, v75 offset:16384 + ds_read_b32 v145, v76 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[122:123], v[138:139], a[112:127] + ds_read_b32 v121, v89 + ds_read_b32 v122, v53 + ds_read_b32 v123, v55 + ds_read_b32 v146, v48 + ds_read_b32 v147, v49 + ds_read_b32 v148, v42 + ds_read_b32 v105, v39 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[120:121], v[116:117], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[120:121], v[118:119], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[120:121], v[130:131], a[160:175] + ds_read_b32 v150, v90 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[120:121], v[138:139], a[176:191] + ds_read_b32 v151, v91 + ds_read_b32 v120, v59 + ds_read_b32 v121, v62 + ds_read_b32 v152, v52 + ds_read_b32 v153, v54 + ds_read_b32 v154, v46 + ds_read_b32 v149, v43 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[150:151], v[116:117], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[150:151], v[118:119], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[150:151], v[130:131], a[224:239] + ds_read_b32 v156, v92 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[150:151], v[138:139], a[240:255] + ds_read_b32 v157, v93 + ds_read_b32 v150, v64 + ds_read_b32 v151, v66 + ds_read_b32 v158, v57 + ds_read_b32 v159, v60 + ds_read_b32 v124, v51 + ds_read_b32 v155, v47 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[156:157], v[116:117], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[156:157], v[118:119], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[156:157], v[130:131], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[156:157], v[138:139], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[110:111], v[114:115], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[110:111], v[112:113], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[110:111], v[132:133], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[110:111], v[140:141], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[122:123], v[114:115], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[122:123], v[112:113], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[122:123], v[132:133], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[122:123], v[140:141], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[120:121], v[114:115], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[120:121], v[112:113], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[120:121], v[132:133], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[120:121], v[140:141], a[240:255] + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[150:151], v[114:115], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[150:151], v[112:113], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[150:151], v[132:133], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[150:151], v[140:141], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[106:107], v[108:109], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[106:107], v[126:127], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[106:107], v[134:135], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[106:107], v[142:143], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[146:147], v[108:109], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[146:147], v[126:127], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[146:147], v[134:135], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[146:147], v[142:143], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[152:153], v[108:109], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[152:153], v[126:127], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[152:153], v[134:135], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[152:153], v[142:143], a[240:255] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[158:159], v[108:109], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[158:159], v[126:127], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[158:159], v[134:135], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[158:159], v[142:143], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[104:105], v[102:103], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[104:105], v[128:129], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[104:105], v[136:137], a[96:111] + v_readfirstlane_b32 s27, v227 + s_add_i32 s18, s18, -1 + s_lshr_b32 s27, s27, 2 + s_and_b32 s27, s27, 0x3ffffff0 + v_add_u32_e32 v0, s27, v1 + s_cmp_gt_u32 s18, 2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[104:105], v[144:145], a[112:127] + s_barrier + v_lshrrev_b32_e32 v36, 1, v0 + v_lshlrev_b32_e32 v104, 9, v0 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v36, 16, v36 + v_and_b32_e32 v104, 0x3000, v104 + v_and_b32_e32 v0, 0xfffff800, v0 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[148:149], v[102:103], a[128:143] + v_xor_b32_e32 v105, v36, v37 + v_add_u32_e32 v0, v104, v0 + v_or_b32_e32 v104, 1, v36 + v_or_b32_e32 v106, 2, v36 + v_or_b32_e32 v107, 3, v36 + v_or_b32_e32 v108, 4, v36 + v_or_b32_e32 v109, 5, v36 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[148:149], v[128:129], a[144:159] + v_or_b32_e32 v110, 6, v36 + v_or_b32_e32 v111, 7, v36 + v_or_b32_e32 v112, 8, v36 + v_or_b32_e32 v113, 9, v36 + v_or_b32_e32 v114, 10, v36 + v_or_b32_e32 v115, 11, v36 + v_or_b32_e32 v116, 12, v36 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[148:149], v[136:137], a[160:175] + v_or_b32_e32 v117, 13, v36 + v_or_b32_e32 v118, 14, v36 + v_or_b32_e32 v36, 15, v36 + v_lshl_or_b32 v0, v105, 2, v0 + v_xor_b32_e32 v104, v104, v37 + v_xor_b32_e32 v106, v106, v37 + v_xor_b32_e32 v107, v107, v37 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[148:149], v[144:145], a[176:191] + v_xor_b32_e32 v108, v108, v37 + v_xor_b32_e32 v109, v109, v37 + v_xor_b32_e32 v110, v110, v37 + v_xor_b32_e32 v111, v111, v37 + v_xor_b32_e32 v112, v112, v37 + v_xor_b32_e32 v113, v113, v37 + v_xor_b32_e32 v114, v114, v37 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[154:155], v[102:103], a[192:207] + v_xor_b32_e32 v115, v115, v37 + v_xor_b32_e32 v116, v116, v37 + v_xor_b32_e32 v117, v117, v37 + v_xor_b32_e32 v118, v118, v37 + v_xor_b32_e32 v36, v36, v37 + v_sub_u32_e32 v105, v104, v105 + v_sub_u32_e32 v104, v106, v104 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[154:155], v[128:129], a[208:223] + v_sub_u32_e32 v106, v107, v106 + v_sub_u32_e32 v107, v108, v107 + v_sub_u32_e32 v108, v109, v108 + v_sub_u32_e32 v109, v110, v109 + v_sub_u32_e32 v110, v111, v110 + v_sub_u32_e32 v111, v112, v111 + v_sub_u32_e32 v112, v113, v112 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[154:155], v[136:137], a[224:239] + v_sub_u32_e32 v113, v114, v113 + v_sub_u32_e32 v114, v115, v114 + v_sub_u32_e32 v115, v116, v115 + v_sub_u32_e32 v116, v117, v116 + v_sub_u32_e32 v117, v118, v117 + v_sub_u32_e32 v36, v36, v118 + v_lshl_add_u32 v105, v105, 2, v0 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[154:155], v[144:145], a[240:255] + v_lshlrev_b32_e32 v104, 2, v104 + v_lshlrev_b32_e32 v106, 2, v106 + v_lshlrev_b32_e32 v107, 2, v107 + v_lshlrev_b32_e32 v108, 2, v108 + v_lshlrev_b32_e32 v109, 2, v109 + v_lshlrev_b32_e32 v110, 2, v110 + v_lshlrev_b32_e32 v111, 2, v111 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[124:125], v[102:103], a[32:47] + v_lshlrev_b32_e32 v102, 2, v112 + v_lshlrev_b32_e32 v103, 2, v113 + v_lshlrev_b32_e32 v112, 2, v114 + v_lshlrev_b32_e32 v113, 2, v115 + v_lshlrev_b32_e32 v114, 2, v116 + v_lshlrev_b32_e32 v115, 2, v117 + v_lshlrev_b32_e32 v36, 2, v36 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[124:125], v[128:129], a[48:63] + v_add3_u32 v104, v105, s6, v104 + v_add3_u32 v106, v104, s6, v106 + v_add3_u32 v107, v106, s6, v107 + v_add3_u32 v108, v107, s6, v108 + v_add3_u32 v109, v108, s6, v109 + v_add3_u32 v110, v109, s6, v110 + v_add3_u32 v111, v110, s6, v111 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[124:125], v[136:137], a[0:15] + v_add3_u32 v102, v111, s6, v102 + v_add3_u32 v103, v102, s6, v103 + v_add3_u32 v112, v103, s6, v112 + v_add3_u32 v113, v112, s6, v113 + v_add3_u32 v114, v113, s6, v114 + v_add3_u32 v115, v114, s6, v115 + v_add3_u32 v36, v115, s6, v36 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[124:125], v[144:145], a[16:31] + s_waitcnt vmcnt(7) + v_perm_b32 v26, v26, v26, s19 + v_perm_b32 v27, v27, v27, s19 + v_perm_b32 v28, v28, v28, s19 + v_perm_b32 v29, v29, v29, s19 + s_waitcnt vmcnt(6) + v_perm_b32 v18, v18, v18, s19 + v_perm_b32 v19, v19, v19, s19 + v_perm_b32 v20, v20, v20, s19 + v_perm_b32 v21, v21, v21, s19 + s_waitcnt vmcnt(4) + v_perm_b32 v30, v30, v30, s19 + v_perm_b32 v31, v31, v31, s19 + v_perm_b32 v32, v32, v32, s19 + v_perm_b32 v33, v33, v33, s19 + v_perm_b32 v22, v22, v22, s19 + v_perm_b32 v23, v23, v23, s19 + v_perm_b32 v24, v24, v24, s19 + v_perm_b32 v25, v25, v25, s19 + s_waitcnt vmcnt(3) + v_perm_b32 v14, v14, v14, s19 + v_perm_b32 v15, v15, v15, s19 + v_perm_b32 v16, v16, v16, s19 + v_perm_b32 v17, v17, v17, s19 + v_perm_b32 v116, v30, v26, s23 + v_perm_b32 v26, v30, v26, s26 + v_perm_b32 v30, v31, v27, s23 + v_perm_b32 v27, v31, v27, s26 + v_perm_b32 v31, v32, v28, s23 + v_perm_b32 v28, v32, v28, s26 + v_perm_b32 v32, v33, v29, s23 + v_perm_b32 v29, v33, v29, s26 + s_waitcnt vmcnt(2) + v_perm_b32 v10, v10, v10, s19 + v_perm_b32 v11, v11, v11, s19 + v_perm_b32 v12, v12, v12, s19 + v_perm_b32 v13, v13, v13, s19 + v_perm_b32 v33, v22, v18, s23 + v_perm_b32 v18, v22, v18, s26 + v_perm_b32 v22, v23, v19, s23 + v_perm_b32 v19, v23, v19, s26 + v_perm_b32 v23, v24, v20, s23 + v_perm_b32 v20, v24, v20, s26 + v_perm_b32 v24, v25, v21, s23 + v_perm_b32 v21, v25, v21, s26 + s_waitcnt vmcnt(1) + v_perm_b32 v6, v6, v6, s19 + v_perm_b32 v7, v7, v7, s19 + v_perm_b32 v8, v8, v8, s19 + v_perm_b32 v9, v9, v9, s19 + s_waitcnt vmcnt(0) + v_perm_b32 v2, v2, v2, s19 + v_perm_b32 v3, v3, v3, s19 + v_perm_b32 v4, v4, v4, s19 + v_perm_b32 v5, v5, v5, s19 + v_perm_b32 v25, v6, v14, s23 + v_perm_b32 v6, v6, v14, s26 + v_perm_b32 v14, v7, v15, s23 + v_perm_b32 v7, v7, v15, s26 + v_perm_b32 v15, v8, v16, s23 + v_perm_b32 v8, v8, v16, s26 + v_perm_b32 v16, v9, v17, s23 + v_perm_b32 v9, v9, v17, s26 + v_perm_b32 v17, v2, v10, s23 + v_perm_b32 v2, v2, v10, s26 + v_perm_b32 v10, v3, v11, s23 + v_perm_b32 v3, v3, v11, s26 + v_perm_b32 v11, v4, v12, s23 + v_perm_b32 v4, v4, v12, s26 + v_perm_b32 v12, v5, v13, s23 + v_perm_b32 v5, v5, v13, s26 + v_perm_b32 v13, v25, v116, s24 + v_perm_b32 v25, v25, v116, s25 + v_perm_b32 v116, v6, v26, s24 + v_perm_b32 v6, v6, v26, s25 + v_perm_b32 v26, v14, v30, s24 + v_perm_b32 v14, v14, v30, s25 + v_perm_b32 v30, v7, v27, s24 + v_perm_b32 v7, v7, v27, s25 + v_perm_b32 v27, v15, v31, s24 + v_perm_b32 v15, v15, v31, s25 + v_perm_b32 v31, v8, v28, s24 + v_perm_b32 v8, v8, v28, s25 + v_perm_b32 v28, v16, v32, s24 + v_perm_b32 v16, v16, v32, s25 + v_perm_b32 v32, v9, v29, s24 + v_perm_b32 v9, v9, v29, s25 + v_perm_b32 v29, v17, v33, s24 + v_perm_b32 v17, v17, v33, s25 + v_perm_b32 v33, v2, v18, s24 + v_perm_b32 v2, v2, v18, s25 + v_perm_b32 v18, v10, v22, s24 + v_perm_b32 v10, v10, v22, s25 + v_perm_b32 v22, v3, v19, s24 + v_perm_b32 v3, v3, v19, s25 + v_perm_b32 v19, v11, v23, s24 + v_perm_b32 v11, v11, v23, s25 + v_perm_b32 v23, v4, v20, s24 + v_perm_b32 v4, v4, v20, s25 + v_perm_b32 v20, v12, v24, s24 + v_perm_b32 v12, v12, v24, s25 + v_perm_b32 v24, v5, v21, s24 + v_perm_b32 v5, v5, v21, s25 + ds_write_b32 v0, v13 + ds_write_b32 v105, v25 offset:128 + ds_write_b32 v104, v116 offset:128 + ds_write_b32 v106, v6 offset:128 + ds_write_b32 v107, v26 offset:128 + ds_write_b32 v108, v14 offset:128 + ds_write_b32 v109, v30 offset:128 + ds_write_b32 v110, v7 offset:128 + ds_write_b32 v111, v27 offset:128 + ds_write_b32 v102, v15 offset:128 + ds_write_b32 v103, v31 offset:128 + ds_write_b32 v112, v8 offset:128 + ds_write_b32 v113, v28 offset:128 + ds_write_b32 v114, v16 offset:128 + ds_write_b32 v115, v32 offset:128 + ds_write_b32 v36, v9 offset:128 + ds_write_b32 v0, v29 offset:16384 + ds_write_b32 v105, v17 offset:16512 + ds_write_b32 v104, v33 offset:16512 + ds_write_b32 v106, v2 offset:16512 + ds_write_b32 v107, v18 offset:16512 + ds_write_b32 v108, v10 offset:16512 + ds_write_b32 v109, v22 offset:16512 + ds_write_b32 v110, v3 offset:16512 + ds_write_b32 v111, v19 offset:16512 + ds_write_b32 v102, v11 offset:16512 + ds_write_b32 v103, v23 offset:16512 + ds_write_b32 v112, v4 offset:16512 + ds_write_b32 v113, v20 offset:16512 + ds_write_b32 v114, v12 offset:16512 + ds_write_b32 v115, v24 offset:16512 + ds_write_b32 v36, v5 offset:16512 + s_cbranch_scc1 .LBB19_8 +.LBB19_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSB_8RowMajorESD_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iP + v_accvgpr_read_b32 v0, a160 + v_accvgpr_read_b32 v1, a161 + v_accvgpr_read_b32 v2, a162 + v_accvgpr_read_b32 v3, a163 + v_accvgpr_read_b32 v4, a164 + v_accvgpr_read_b32 v5, a165 + v_accvgpr_read_b32 v6, a166 + v_accvgpr_read_b32 v7, a167 + v_accvgpr_read_b32 v8, a168 + v_accvgpr_read_b32 v9, a169 + v_accvgpr_read_b32 v10, a170 + v_accvgpr_read_b32 v11, a171 + v_accvgpr_read_b32 v12, a172 + v_accvgpr_read_b32 v13, a173 + v_accvgpr_read_b32 v14, a174 + v_accvgpr_read_b32 v15, a175 + v_accvgpr_read_b32 v16, a176 + v_accvgpr_read_b32 v17, a177 + v_accvgpr_read_b32 v18, a178 + v_accvgpr_read_b32 v19, a179 + v_accvgpr_read_b32 v20, a180 + v_accvgpr_read_b32 v21, a181 + v_accvgpr_read_b32 v22, a182 + v_accvgpr_read_b32 v23, a183 + v_accvgpr_read_b32 v24, a184 + v_accvgpr_read_b32 v25, a185 + v_accvgpr_read_b32 v26, a186 + v_accvgpr_read_b32 v27, a187 + v_accvgpr_read_b32 v28, a188 + v_accvgpr_read_b32 v29, a189 + v_accvgpr_read_b32 v30, a190 + v_accvgpr_read_b32 v31, a191 + v_accvgpr_read_b32 v102, a192 + v_accvgpr_read_b32 v103, a193 + v_accvgpr_read_b32 v104, a194 + v_accvgpr_read_b32 v105, a195 + v_accvgpr_read_b32 v106, a196 + v_accvgpr_read_b32 v107, a197 + v_accvgpr_read_b32 v108, a198 + v_accvgpr_read_b32 v109, a199 + v_accvgpr_read_b32 v110, a200 + v_accvgpr_read_b32 v111, a201 + v_accvgpr_read_b32 v112, a202 + v_accvgpr_read_b32 v113, a203 + v_accvgpr_read_b32 v114, a204 + v_accvgpr_read_b32 v115, a205 + v_accvgpr_read_b32 v116, a206 + v_accvgpr_read_b32 v117, a207 + v_accvgpr_read_b32 v118, a208 + v_accvgpr_read_b32 v119, a209 + v_accvgpr_read_b32 v120, a210 + v_accvgpr_read_b32 v121, a211 + v_accvgpr_read_b32 v122, a212 + v_accvgpr_read_b32 v123, a213 + v_accvgpr_read_b32 v124, a214 + v_accvgpr_read_b32 v125, a215 + v_accvgpr_read_b32 v126, a216 + v_accvgpr_read_b32 v127, a217 + v_accvgpr_read_b32 v128, a218 + v_accvgpr_read_b32 v129, a219 + v_accvgpr_read_b32 v130, a220 + v_accvgpr_read_b32 v131, a221 + v_accvgpr_read_b32 v132, a222 + v_accvgpr_read_b32 v133, a223 + v_accvgpr_read_b32 v134, a224 + v_accvgpr_read_b32 v135, a225 + v_accvgpr_read_b32 v136, a226 + v_accvgpr_read_b32 v137, a227 + v_accvgpr_read_b32 v138, a228 + v_accvgpr_read_b32 v139, a229 + v_accvgpr_read_b32 v140, a230 + v_accvgpr_read_b32 v141, a231 + v_accvgpr_read_b32 v142, a232 + v_accvgpr_read_b32 v143, a233 + v_accvgpr_read_b32 v144, a234 + v_accvgpr_read_b32 v145, a235 + v_accvgpr_read_b32 v146, a236 + v_accvgpr_read_b32 v147, a237 + v_accvgpr_read_b32 v148, a238 + v_accvgpr_read_b32 v149, a239 + v_accvgpr_read_b32 v150, a240 + v_accvgpr_read_b32 v151, a241 + v_accvgpr_read_b32 v152, a242 + v_accvgpr_read_b32 v153, a243 + v_accvgpr_read_b32 v154, a244 + v_accvgpr_read_b32 v155, a245 + v_accvgpr_read_b32 v156, a246 + v_accvgpr_read_b32 v157, a247 + v_accvgpr_read_b32 v158, a248 + v_accvgpr_read_b32 v159, a249 + v_accvgpr_read_b32 v160, a250 + v_accvgpr_read_b32 v161, a251 + v_accvgpr_read_b32 v162, a252 + v_accvgpr_read_b32 v163, a253 + v_accvgpr_read_b32 v164, a254 + v_accvgpr_read_b32 v165, a255 + v_accvgpr_read_b32 v166, a48 + v_accvgpr_read_b32 v167, a49 + v_accvgpr_read_b32 v168, a50 + v_accvgpr_read_b32 v169, a51 + v_accvgpr_read_b32 v170, a52 + v_accvgpr_read_b32 v171, a53 + v_accvgpr_read_b32 v172, a54 + v_accvgpr_read_b32 v173, a55 + v_accvgpr_read_b32 v174, a56 + v_accvgpr_read_b32 v175, a57 + v_accvgpr_read_b32 v176, a58 + v_accvgpr_read_b32 v177, a59 + v_accvgpr_read_b32 v178, a60 + v_accvgpr_read_b32 v179, a61 + v_accvgpr_read_b32 v180, a62 + v_accvgpr_read_b32 v181, a63 + v_accvgpr_mov_b32 a240, a16 + v_accvgpr_mov_b32 a241, a17 + v_accvgpr_mov_b32 a242, a18 + v_accvgpr_mov_b32 a243, a19 + v_accvgpr_mov_b32 a244, a20 + v_accvgpr_mov_b32 a245, a21 + v_accvgpr_mov_b32 a246, a22 + v_accvgpr_mov_b32 a247, a23 + v_accvgpr_mov_b32 a248, a24 + v_accvgpr_mov_b32 a249, a25 + v_accvgpr_mov_b32 a250, a26 + v_accvgpr_mov_b32 a251, a27 + v_accvgpr_mov_b32 a252, a28 + v_accvgpr_mov_b32 a253, a29 + v_accvgpr_mov_b32 a254, a30 + v_accvgpr_mov_b32 a255, a31 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v32, v97 + ds_read_b32 v33, v78 + ds_read_b32 v34, v56 offset:16384 + ds_read_b32 v35, v94 offset:16384 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a224, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[32:33], v[34:35], a[224:239] + ds_read_b32 v36, v95 offset:16384 + ds_read_b32 v37, v96 offset:16384 + v_accvgpr_mov_b32 a223, a95 + v_accvgpr_mov_b32 a222, a94 + v_accvgpr_mov_b32 a221, a93 + v_accvgpr_mov_b32 a220, a92 + v_accvgpr_mov_b32 a219, a91 + v_accvgpr_mov_b32 a218, a90 + v_accvgpr_mov_b32 a217, a89 + v_accvgpr_mov_b32 a216, a88 + v_accvgpr_mov_b32 a215, a87 + v_accvgpr_mov_b32 a214, a86 + v_accvgpr_mov_b32 a213, a85 + v_accvgpr_mov_b32 a212, a84 + v_accvgpr_mov_b32 a211, a83 + v_accvgpr_mov_b32 a210, a82 + v_accvgpr_mov_b32 a209, a81 + v_accvgpr_mov_b32 a208, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[32:33], v[36:37], a[208:223] + ds_read_b32 v94, v98 offset:16384 + ds_read_b32 v95, v99 offset:16384 + v_accvgpr_mov_b32 a207, a111 + v_accvgpr_mov_b32 a206, a110 + v_accvgpr_mov_b32 a205, a109 + v_accvgpr_mov_b32 a204, a108 + v_accvgpr_mov_b32 a203, a107 + v_accvgpr_mov_b32 a202, a106 + v_accvgpr_mov_b32 a201, a105 + v_accvgpr_mov_b32 a200, a104 + v_accvgpr_mov_b32 a199, a103 + v_accvgpr_mov_b32 a198, a102 + v_accvgpr_mov_b32 a197, a101 + v_accvgpr_mov_b32 a196, a100 + v_accvgpr_mov_b32 a195, a99 + v_accvgpr_mov_b32 a194, a98 + v_accvgpr_mov_b32 a193, a97 + v_accvgpr_mov_b32 a192, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[32:33], v[94:95], a[192:207] + ds_read_b32 v96, v100 offset:16384 + ds_read_b32 v97, v101 offset:16384 + v_accvgpr_mov_b32 a191, a127 + v_accvgpr_mov_b32 a190, a126 + v_accvgpr_mov_b32 a189, a125 + v_accvgpr_mov_b32 a188, a124 + v_accvgpr_mov_b32 a187, a123 + v_accvgpr_mov_b32 a186, a122 + v_accvgpr_mov_b32 a185, a121 + v_accvgpr_mov_b32 a184, a120 + v_accvgpr_mov_b32 a183, a119 + v_accvgpr_mov_b32 a182, a118 + v_accvgpr_mov_b32 a181, a117 + v_accvgpr_mov_b32 a180, a116 + v_accvgpr_mov_b32 a179, a115 + v_accvgpr_mov_b32 a178, a114 + v_accvgpr_mov_b32 a177, a113 + v_accvgpr_mov_b32 a176, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[32:33], v[96:97], a[176:191] + ds_read_b32 v32, v88 + ds_read_b32 v33, v89 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[32:33], v[34:35], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[32:33], v[36:37], a[144:159] + v_accvgpr_write_b32 a143, v15 + v_accvgpr_write_b32 a142, v14 + v_accvgpr_write_b32 a141, v13 + v_accvgpr_write_b32 a140, v12 + v_accvgpr_write_b32 a139, v11 + v_accvgpr_write_b32 a138, v10 + v_accvgpr_write_b32 a137, v9 + v_accvgpr_write_b32 a136, v8 + v_accvgpr_write_b32 a135, v7 + v_accvgpr_write_b32 a134, v6 + v_accvgpr_write_b32 a133, v5 + v_accvgpr_write_b32 a132, v4 + v_accvgpr_write_b32 a131, v3 + v_accvgpr_write_b32 a130, v2 + v_accvgpr_write_b32 a129, v1 + v_accvgpr_write_b32 a128, v0 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[32:33], v[94:95], a[128:143] + v_accvgpr_write_b32 a127, v31 + v_accvgpr_write_b32 a126, v30 + v_accvgpr_write_b32 a125, v29 + v_accvgpr_write_b32 a124, v28 + v_accvgpr_write_b32 a123, v27 + v_accvgpr_write_b32 a122, v26 + v_accvgpr_write_b32 a121, v25 + v_accvgpr_write_b32 a120, v24 + v_accvgpr_write_b32 a119, v23 + v_accvgpr_write_b32 a118, v22 + v_accvgpr_write_b32 a117, v21 + v_accvgpr_write_b32 a116, v20 + v_accvgpr_write_b32 a115, v19 + v_accvgpr_write_b32 a114, v18 + v_accvgpr_write_b32 a113, v17 + v_accvgpr_write_b32 a112, v16 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[32:33], v[96:97], a[112:127] + ds_read_b32 v0, v90 + ds_read_b32 v1, v91 + v_accvgpr_write_b32 a96, v102 + v_accvgpr_write_b32 a97, v103 + v_accvgpr_write_b32 a98, v104 + v_accvgpr_write_b32 a99, v105 + v_accvgpr_write_b32 a100, v106 + v_accvgpr_write_b32 a101, v107 + v_accvgpr_write_b32 a102, v108 + v_accvgpr_write_b32 a103, v109 + v_accvgpr_write_b32 a104, v110 + v_accvgpr_write_b32 a105, v111 + v_accvgpr_write_b32 a106, v112 + v_accvgpr_write_b32 a107, v113 + v_accvgpr_write_b32 a108, v114 + v_accvgpr_write_b32 a109, v115 + v_accvgpr_write_b32 a110, v116 + v_accvgpr_write_b32 a111, v117 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[34:35], a[96:111] + v_accvgpr_write_b32 a80, v118 + v_accvgpr_write_b32 a81, v119 + v_accvgpr_write_b32 a82, v120 + v_accvgpr_write_b32 a83, v121 + v_accvgpr_write_b32 a84, v122 + v_accvgpr_write_b32 a85, v123 + v_accvgpr_write_b32 a86, v124 + v_accvgpr_write_b32 a87, v125 + v_accvgpr_write_b32 a88, v126 + v_accvgpr_write_b32 a89, v127 + v_accvgpr_write_b32 a90, v128 + v_accvgpr_write_b32 a91, v129 + v_accvgpr_write_b32 a92, v130 + v_accvgpr_write_b32 a93, v131 + v_accvgpr_write_b32 a94, v132 + v_accvgpr_write_b32 a95, v133 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[36:37], a[80:95] + v_accvgpr_write_b32 a64, v134 + v_accvgpr_write_b32 a65, v135 + v_accvgpr_write_b32 a66, v136 + v_accvgpr_write_b32 a67, v137 + v_accvgpr_write_b32 a68, v138 + v_accvgpr_write_b32 a69, v139 + v_accvgpr_write_b32 a70, v140 + v_accvgpr_write_b32 a71, v141 + v_accvgpr_write_b32 a72, v142 + v_accvgpr_write_b32 a73, v143 + v_accvgpr_write_b32 a74, v144 + v_accvgpr_write_b32 a75, v145 + v_accvgpr_write_b32 a76, v146 + v_accvgpr_write_b32 a77, v147 + v_accvgpr_write_b32 a78, v148 + v_accvgpr_write_b32 a79, v149 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[94:95], a[64:79] + v_accvgpr_write_b32 a48, v150 + v_accvgpr_write_b32 a49, v151 + v_accvgpr_write_b32 a50, v152 + v_accvgpr_write_b32 a51, v153 + v_accvgpr_write_b32 a52, v154 + v_accvgpr_write_b32 a53, v155 + v_accvgpr_write_b32 a54, v156 + v_accvgpr_write_b32 a55, v157 + v_accvgpr_write_b32 a56, v158 + v_accvgpr_write_b32 a57, v159 + v_accvgpr_write_b32 a58, v160 + v_accvgpr_write_b32 a59, v161 + v_accvgpr_write_b32 a60, v162 + v_accvgpr_write_b32 a61, v163 + v_accvgpr_write_b32 a62, v164 + v_accvgpr_write_b32 a63, v165 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[96:97], a[48:63] + ds_read_b32 v0, v92 + ds_read_b32 v1, v93 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[34:35], a[32:47] + v_accvgpr_write_b32 a16, v166 + v_accvgpr_write_b32 a17, v167 + v_accvgpr_write_b32 a18, v168 + v_accvgpr_write_b32 a19, v169 + v_accvgpr_write_b32 a20, v170 + v_accvgpr_write_b32 a21, v171 + v_accvgpr_write_b32 a22, v172 + v_accvgpr_write_b32 a23, v173 + v_accvgpr_write_b32 a24, v174 + v_accvgpr_write_b32 a25, v175 + v_accvgpr_write_b32 a26, v176 + v_accvgpr_write_b32 a27, v177 + v_accvgpr_write_b32 a28, v178 + v_accvgpr_write_b32 a29, v179 + v_accvgpr_write_b32 a30, v180 + v_accvgpr_write_b32 a31, v181 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[36:37], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[94:95], a[0:15] + ds_read_b32 v2, v44 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[96:97], a[240:255] + ds_read_b32 v3, v45 + ds_read_b32 v0, v73 offset:16384 + ds_read_b32 v1, v74 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[2:3], v[0:1], a[224:239] + ds_read_b32 v4, v80 offset:16384 + ds_read_b32 v5, v81 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[2:3], v[4:5], a[208:223] + ds_read_b32 v6, v84 offset:16384 + ds_read_b32 v7, v85 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[2:3], v[6:7], a[192:207] + ds_read_b32 v8, v86 offset:16384 + ds_read_b32 v9, v87 offset:16384 + ds_read_b32 v10, v53 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[2:3], v[8:9], a[176:191] + ds_read_b32 v11, v55 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[10:11], v[0:1], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v2, v59 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v3, v62 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[2:3], v[0:1], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[2:3], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[2:3], v[6:7], a[64:79] + ds_read_b32 v10, v64 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v11, v66 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[10:11], v[0:1], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[10:11], v[6:7], a[0:15] + ds_read_b32 v0, v40 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v1, v41 + ds_read_b32 v2, v67 offset:16384 + ds_read_b32 v3, v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[2:3], a[224:239] + ds_read_b32 v4, v71 offset:16384 + ds_read_b32 v5, v72 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[4:5], a[208:223] + ds_read_b32 v6, v77 offset:16384 + ds_read_b32 v7, v79 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[6:7], a[192:207] + ds_read_b32 v8, v82 offset:16384 + ds_read_b32 v9, v83 offset:16384 + ds_read_b32 v10, v48 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b32 v11, v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v0, v52 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v1, v54 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b32 v10, v57 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b32 v11, v60 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[10:11], v[2:3], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[10:11], v[6:7], a[0:15] + ds_read_b32 v0, v38 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v1, v39 + ds_read_b32 v2, v58 offset:16384 + ds_read_b32 v3, v61 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[2:3], a[224:239] + ds_read_b32 v4, v63 offset:16384 + ds_read_b32 v5, v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[4:5], a[208:223] + ds_read_b32 v6, v69 offset:16384 + ds_read_b32 v7, v70 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[6:7], a[192:207] + ds_read_b32 v8, v75 offset:16384 + ds_read_b32 v9, v76 offset:16384 + ds_read_b32 v10, v42 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b32 v11, v43 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v0, v46 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v1, v47 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b32 v10, v51 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b32 v11, v50 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[10:11], v[2:3], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[10:11], v[6:7], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[10:11], v[8:9], a[240:255] +.LBB19_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSB_8RowMajorESD_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iPv + v_accvgpr_read_b32 v143, a224 + v_accvgpr_read_b32 v142, a225 + v_accvgpr_read_b32 v141, a226 + v_accvgpr_read_b32 v140, a227 + v_accvgpr_read_b32 v139, a228 + v_accvgpr_read_b32 v36, a229 + v_accvgpr_read_b32 v1, a230 + v_accvgpr_read_b32 v138, a231 + v_accvgpr_read_b32 v137, a232 + v_accvgpr_read_b32 v136, a233 + v_accvgpr_read_b32 v135, a234 + v_accvgpr_read_b32 v134, a235 + v_accvgpr_read_b32 v133, a236 + v_accvgpr_read_b32 v132, a237 + v_accvgpr_read_b32 v131, a238 + v_accvgpr_read_b32 v130, a239 + v_accvgpr_read_b32 v106, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v104, a210 + v_accvgpr_read_b32 v103, a211 + v_accvgpr_read_b32 v102, a212 + v_accvgpr_read_b32 v101, a213 + v_accvgpr_read_b32 v100, a214 + v_accvgpr_read_b32 v99, a215 + v_accvgpr_read_b32 v98, a216 + v_accvgpr_read_b32 v97, a217 + v_accvgpr_read_b32 v96, a218 + v_accvgpr_read_b32 v95, a219 + v_accvgpr_read_b32 v94, a220 + v_accvgpr_read_b32 v93, a221 + v_accvgpr_read_b32 v92, a222 + v_accvgpr_read_b32 v91, a223 + v_accvgpr_read_b32 v90, a192 + v_accvgpr_read_b32 v89, a193 + v_accvgpr_read_b32 v88, a194 + v_accvgpr_read_b32 v87, a195 + v_accvgpr_read_b32 v86, a196 + v_accvgpr_read_b32 v85, a197 + v_accvgpr_read_b32 v84, a198 + v_accvgpr_read_b32 v83, a199 + v_accvgpr_read_b32 v82, a200 + v_accvgpr_read_b32 v81, a201 + v_accvgpr_read_b32 v80, a202 + v_accvgpr_read_b32 v79, a203 + v_accvgpr_read_b32 v78, a204 + v_accvgpr_read_b32 v77, a205 + v_accvgpr_read_b32 v76, a206 + v_accvgpr_read_b32 v75, a207 + v_accvgpr_read_b32 v74, a176 + v_accvgpr_read_b32 v73, a177 + v_accvgpr_read_b32 v72, a178 + v_accvgpr_read_b32 v71, a179 + v_accvgpr_read_b32 v70, a180 + v_accvgpr_read_b32 v69, a181 + v_accvgpr_read_b32 v68, a182 + v_accvgpr_read_b32 v67, a183 + v_accvgpr_read_b32 v66, a184 + v_accvgpr_read_b32 v65, a185 + v_accvgpr_read_b32 v64, a186 + v_accvgpr_read_b32 v63, a187 + v_accvgpr_read_b32 v62, a188 + v_accvgpr_read_b32 v61, a189 + v_accvgpr_read_b32 v60, a190 + v_accvgpr_read_b32 v18, a191 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v59, a80 + v_accvgpr_read_b32 v58, a81 + v_accvgpr_read_b32 v57, a82 + v_accvgpr_read_b32 v56, a83 + v_accvgpr_read_b32 v55, a84 + v_accvgpr_read_b32 v54, a85 + v_accvgpr_read_b32 v53, a86 + v_accvgpr_read_b32 v52, a87 + v_accvgpr_read_b32 v51, a88 + v_accvgpr_read_b32 v50, a89 + v_accvgpr_read_b32 v24, a90 + v_accvgpr_read_b32 v23, a91 + v_accvgpr_read_b32 v22, a92 + v_accvgpr_read_b32 v21, a93 + v_accvgpr_read_b32 v20, a94 + v_accvgpr_read_b32 v19, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v107, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v35, a21 + v_accvgpr_read_b32 v34, a22 + v_accvgpr_read_b32 v33, a23 + v_accvgpr_read_b32 v32, a24 + v_accvgpr_read_b32 v31, a25 + v_accvgpr_read_b32 v30, a26 + v_accvgpr_read_b32 v29, a27 + v_accvgpr_read_b32 v28, a28 + v_accvgpr_read_b32 v27, a29 + v_accvgpr_read_b32 v26, a30 + v_accvgpr_read_b32 v25, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s3, s4, s16 + s_mul_hi_u32 s4, 0, s16 + s_add_i32 s4, s4, s3 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v0, 3, v225 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v36, v36 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v92, v92 + v_cvt_f16_f32_e32 v209, v91 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v90 + v_cvt_f16_f32_e32 v163, v89 + v_cvt_f16_f32_e32 v164, v88 + v_cvt_f16_f32_e32 v165, v87 + v_cvt_f16_f32_e32 v166, v86 + v_cvt_f16_f32_e32 v167, v85 + v_cvt_f16_f32_e32 v168, v84 + v_cvt_f16_f32_e32 v169, v83 + v_cvt_f16_f32_e32 v170, v82 + v_cvt_f16_f32_e32 v171, v81 + v_cvt_f16_f32_e32 v172, v80 + v_cvt_f16_f32_e32 v173, v79 + v_cvt_f16_f32_e32 v174, v78 + v_cvt_f16_f32_e32 v175, v77 + v_cvt_f16_f32_e32 v176, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v76, v160 + v_cvt_f16_f32_e32 v77, v159 + v_cvt_f16_f32_e32 v78, v158 + v_cvt_f16_f32_e32 v79, v157 + v_cvt_f16_f32_e32 v80, v156 + v_cvt_f16_f32_e32 v81, v155 + v_cvt_f16_f32_e32 v82, v154 + v_cvt_f16_f32_e32 v83, v153 + v_cvt_f16_f32_e32 v84, v152 + v_cvt_f16_f32_e32 v85, v151 + v_cvt_f16_f32_e32 v86, v150 + v_cvt_f16_f32_e32 v87, v149 + v_cvt_f16_f32_e32 v88, v148 + v_cvt_f16_f32_e32 v89, v147 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v71, v71 + v_cvt_f16_f32_e32 v134, v70 + v_cvt_f16_f32_e32 v135, v69 + v_cvt_f16_f32_e32 v136, v68 + v_cvt_f16_f32_e32 v137, v67 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v18 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v18, v205 + v_accvgpr_write_b32 a0, v18 + v_cvt_f16_f32_e32 v18, v204 + v_accvgpr_write_b32 a1, v18 + v_cvt_f16_f32_e32 v70, v203 + v_cvt_f16_f32_e32 v69, v202 + v_cvt_f16_f32_e32 v68, v201 + v_cvt_f16_f32_e32 v67, v200 + v_cvt_f16_f32_e32 v60, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v18, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v107 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v48, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v49, v42 + v_cvt_f16_f32_e32 v107, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v3, v58 + v_cvt_f16_f32_e32 v4, v57 + v_cvt_f16_f32_e32 v5, v56 + v_cvt_f16_f32_e32 v6, v55 + v_cvt_f16_f32_e32 v7, v54 + v_cvt_f16_f32_e32 v8, v53 + v_cvt_f16_f32_e32 v9, v52 + v_cvt_f16_f32_e32 v10, v51 + v_cvt_f16_f32_e32 v11, v50 + v_cvt_f16_f32_e32 v12, v24 + v_cvt_f16_f32_e32 v13, v23 + v_cvt_f16_f32_e32 v14, v22 + v_cvt_f16_f32_e32 v15, v21 + v_cvt_f16_f32_e32 v16, v20 + v_cvt_f16_f32_e32 v17, v19 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v35 + v_cvt_f16_f32_e32 v56, v34 + v_cvt_f16_f32_e32 v57, v33 + v_cvt_f16_f32_e32 v58, v32 + v_cvt_f16_f32_e32 v59, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_cvt_f16_f32_e32 v25, v25 + v_lshlrev_b32_e32 v21, 1, v228 + v_lshlrev_b32_e32 v20, 3, v225 + v_lshrrev_b32_e32 v19, 1, v225 + s_cbranch_scc1 .LBB19_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB19_14 +.LBB19_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB19_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v22, s5, v0 + v_lshl_or_b32 v22, v22, 7, v18 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v22, v21, s2 + ds_write_b16 v22, v251 + ds_write_b16 v22, v252 offset:128 + ds_write_b16 v22, v253 offset:256 + ds_write_b16 v22, v254 offset:384 + ds_write_b16 v22, v255 offset:1024 + ds_write_b16 v22, v36 offset:1152 + ds_write_b16 v22, v1 offset:1280 + ds_write_b16 v22, v244 offset:1408 + ds_write_b16 v22, v245 offset:2048 + ds_write_b16 v22, v246 offset:2176 + ds_write_b16 v22, v247 offset:2304 + ds_write_b16 v22, v248 offset:2432 + ds_write_b16 v22, v249 offset:3072 + ds_write_b16 v22, v250 offset:3200 + ds_write_b16 v22, v131 offset:3328 + ds_write_b16 v22, v132 offset:3456 + ds_write_b16 v22, v133 offset:8192 + ds_write_b16 v22, v229 offset:8320 + ds_write_b16 v22, v230 offset:8448 + ds_write_b16 v22, v231 offset:8576 + ds_write_b16 v22, v232 offset:9216 + ds_write_b16 v22, v233 offset:9344 + ds_write_b16 v22, v234 offset:9472 + ds_write_b16 v22, v235 offset:9600 + ds_write_b16 v22, v236 offset:10240 + ds_write_b16 v22, v237 offset:10368 + ds_write_b16 v22, v238 offset:10496 + ds_write_b16 v22, v239 offset:10624 + ds_write_b16 v22, v240 offset:11264 + ds_write_b16 v22, v241 offset:11392 + ds_write_b16 v22, v242 offset:11520 + ds_write_b16 v22, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v23, 60, v19 + v_add_u32_e32 v24, s2, v23 + v_and_b32_e32 v31, 56, v20 + v_lshlrev_b32_e32 v23, 7, v24 + v_lshl_or_b32 v23, v31, 1, v23 + v_add_u32_e32 v37, s20, v24 + v_or_b32_e32 v24, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v37, s16 + v_add_u32_e32 v190, v31, v24 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v106 + ds_write_b16 v22, v105 offset:128 + ds_write_b16 v22, v104 offset:256 + ds_write_b16 v22, v103 offset:384 + ds_write_b16 v22, v102 offset:1024 + ds_write_b16 v22, v101 offset:1152 + ds_write_b16 v22, v100 offset:1280 + ds_write_b16 v22, v99 offset:1408 + ds_write_b16 v22, v98 offset:2048 + ds_write_b16 v22, v97 offset:2176 + ds_write_b16 v22, v96 offset:2304 + ds_write_b16 v22, v95 offset:2432 + ds_write_b16 v22, v94 offset:3072 + ds_write_b16 v22, v93 offset:3200 + ds_write_b16 v22, v92 offset:3328 + ds_write_b16 v22, v209 offset:3456 + ds_write_b16 v22, v210 offset:8192 + ds_write_b16 v22, v211 offset:8320 + ds_write_b16 v22, v212 offset:8448 + ds_write_b16 v22, v213 offset:8576 + ds_write_b16 v22, v214 offset:9216 + ds_write_b16 v22, v215 offset:9344 + ds_write_b16 v22, v216 offset:9472 + ds_write_b16 v22, v217 offset:9600 + ds_write_b16 v22, v218 offset:10240 + ds_write_b16 v22, v219 offset:10368 + ds_write_b16 v22, v220 offset:10496 + ds_write_b16 v22, v221 offset:10624 + ds_write_b16 v22, v222 offset:11264 + ds_write_b16 v22, v223 offset:11392 + ds_write_b16 v22, v224 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 64, v24 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v162 + ds_write_b16 v22, v163 offset:128 + ds_write_b16 v22, v164 offset:256 + ds_write_b16 v22, v165 offset:384 + ds_write_b16 v22, v166 offset:1024 + ds_write_b16 v22, v167 offset:1152 + ds_write_b16 v22, v168 offset:1280 + ds_write_b16 v22, v169 offset:1408 + ds_write_b16 v22, v170 offset:2048 + ds_write_b16 v22, v171 offset:2176 + ds_write_b16 v22, v172 offset:2304 + ds_write_b16 v22, v173 offset:2432 + ds_write_b16 v22, v174 offset:3072 + ds_write_b16 v22, v175 offset:3200 + ds_write_b16 v22, v176 offset:3328 + ds_write_b16 v22, v75 offset:3456 + ds_write_b16 v22, v76 offset:8192 + ds_write_b16 v22, v77 offset:8320 + ds_write_b16 v22, v78 offset:8448 + ds_write_b16 v22, v79 offset:8576 + ds_write_b16 v22, v80 offset:9216 + ds_write_b16 v22, v81 offset:9344 + ds_write_b16 v22, v82 offset:9472 + ds_write_b16 v22, v83 offset:9600 + ds_write_b16 v22, v84 offset:10240 + ds_write_b16 v22, v85 offset:10368 + ds_write_b16 v22, v86 offset:10496 + ds_write_b16 v22, v87 offset:10624 + ds_write_b16 v22, v88 offset:11264 + ds_write_b16 v22, v89 offset:11392 + ds_write_b16 v22, v90 offset:11520 + ds_write_b16 v22, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0x80, v24 + v_add_u32_e32 v192, v31, v191 + v_lshlrev_b32_e32 v201, 1, v192 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v201, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v201, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v201, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v201, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v192 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v74 + ds_write_b16 v22, v73 offset:128 + ds_write_b16 v22, v72 offset:256 + ds_write_b16 v22, v71 offset:384 + ds_write_b16 v22, v134 offset:1024 + ds_write_b16 v22, v135 offset:1152 + ds_write_b16 v22, v136 offset:1280 + ds_write_b16 v22, v137 offset:1408 + ds_write_b16 v22, v138 offset:2048 + ds_write_b16 v22, v139 offset:2176 + ds_write_b16 v22, v140 offset:2304 + ds_write_b16 v22, v141 offset:2432 + ds_write_b16 v22, v142 offset:3072 + ds_write_b16 v22, v143 offset:3200 + ds_write_b16 v22, v144 offset:3328 + ds_write_b16 v22, v145 offset:3456 + ds_write_b16 v22, v146 offset:8192 + ds_write_b16 v22, v147 offset:8320 + ds_write_b16 v22, v148 offset:8448 + ds_write_b16 v22, v149 offset:8576 + ds_write_b16 v22, v150 offset:9216 + ds_write_b16 v22, v151 offset:9344 + ds_write_b16 v22, v152 offset:9472 + ds_write_b16 v22, v153 offset:9600 + ds_write_b16 v22, v154 offset:10240 + ds_write_b16 v22, v155 offset:10368 + ds_write_b16 v22, v156 offset:10496 + ds_write_b16 v22, v157 offset:10624 + ds_write_b16 v22, v158 offset:11264 + ds_write_b16 v22, v159 offset:11392 + ds_write_b16 v22, v160 offset:11520 + ds_write_b16 v22, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v192, 0xc0, v24 + v_add_u32_e32 v31, v31, v192 + v_lshlrev_b32_e32 v201, 1, v31 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v201, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v201, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v201, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v201, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, v207 offset:128 + ds_write_b16 v22, v206 offset:256 + ds_write_b16 v22, a0 offset:384 + ds_write_b16 v22, a1 offset:1024 + ds_write_b16 v22, v70 offset:1152 + ds_write_b16 v22, v69 offset:1280 + ds_write_b16 v22, v68 offset:1408 + ds_write_b16 v22, v67 offset:2048 + ds_write_b16 v22, v60 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v115 offset:8320 + ds_write_b16 v22, v116 offset:8448 + ds_write_b16 v22, v117 offset:8576 + ds_write_b16 v22, v118 offset:9216 + ds_write_b16 v22, v119 offset:9344 + ds_write_b16 v22, v120 offset:9472 + ds_write_b16 v22, v121 offset:9600 + ds_write_b16 v22, v122 offset:10240 + ds_write_b16 v22, v123 offset:10368 + ds_write_b16 v22, v124 offset:10496 + ds_write_b16 v22, v125 offset:10624 + ds_write_b16 v22, v126 offset:11264 + ds_write_b16 v22, v127 offset:11392 + ds_write_b16 v22, v128 offset:11520 + ds_write_b16 v22, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v37 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v37, v31, v192 + v_lshlrev_b32_e32 v192, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v114 + ds_write_b16 v22, v193 offset:128 + ds_write_b16 v22, v194 offset:256 + ds_write_b16 v22, v195 offset:384 + ds_write_b16 v22, v196 offset:1024 + ds_write_b16 v22, v197 offset:1152 + ds_write_b16 v22, v198 offset:1280 + ds_write_b16 v22, v199 offset:1408 + ds_write_b16 v22, v200 offset:2048 + ds_write_b16 v22, v48 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v49 offset:3456 + ds_write_b16 v22, v107 offset:8192 + ds_write_b16 v22, v108 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v185 offset:9600 + ds_write_b16 v22, v184 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v37, v31, v191 + v_lshlrev_b32_e32 v191, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v50 offset:8192 + ds_write_b16 v22, v51 offset:8320 + ds_write_b16 v22, v52 offset:8448 + ds_write_b16 v22, v53 offset:8576 + ds_write_b16 v22, v54 offset:9216 + ds_write_b16 v22, v55 offset:9344 + ds_write_b16 v22, v56 offset:9472 + ds_write_b16 v22, v57 offset:9600 + ds_write_b16 v22, v58 offset:10240 + ds_write_b16 v22, v59 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v37, v31, v190 + v_lshlrev_b32_e32 v190, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11648 + v_add_u32_e32 v22, v31, v24 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v24, 1, v22 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v24, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v23, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v23, s[0:3], 12 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v22, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v22, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v22, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v22, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB19_12 +.LBB19_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_or_b32 v0, v0, 7, v18 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v0, v21, s2 + ds_write_b16 v22, v251 + ds_write_b16 v22, v252 offset:128 + ds_write_b16 v22, v253 offset:256 + ds_write_b16 v22, v254 offset:384 + ds_write_b16 v22, v255 offset:1024 + ds_write_b16 v22, v36 offset:1152 + ds_write_b16 v22, v1 offset:1280 + ds_write_b16 v22, v244 offset:1408 + ds_write_b16 v22, v245 offset:2048 + ds_write_b16 v22, v246 offset:2176 + ds_write_b16 v22, v247 offset:2304 + ds_write_b16 v22, v248 offset:2432 + ds_write_b16 v22, v249 offset:3072 + ds_write_b16 v22, v250 offset:3200 + ds_write_b16 v22, v131 offset:3328 + ds_write_b16 v22, v132 offset:3456 + ds_write_b16 v22, v133 offset:8192 + ds_write_b16 v22, v229 offset:8320 + ds_write_b16 v22, v230 offset:8448 + ds_write_b16 v22, v231 offset:8576 + ds_write_b16 v22, v232 offset:9216 + ds_write_b16 v22, v233 offset:9344 + ds_write_b16 v22, v234 offset:9472 + ds_write_b16 v22, v235 offset:9600 + ds_write_b16 v22, v236 offset:10240 + ds_write_b16 v22, v237 offset:10368 + ds_write_b16 v22, v238 offset:10496 + ds_write_b16 v22, v239 offset:10624 + ds_write_b16 v22, v240 offset:11264 + ds_write_b16 v22, v241 offset:11392 + ds_write_b16 v22, v242 offset:11520 + ds_write_b16 v22, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v20 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v19 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v23, v0, 1, v18 + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[186:189], v23 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v24, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v31, v0, v24 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v40, 1, v31 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v40, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v31 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[186:189], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v106 + ds_write_b16 v22, v105 offset:128 + ds_write_b16 v22, v104 offset:256 + ds_write_b16 v22, v103 offset:384 + ds_write_b16 v22, v102 offset:1024 + ds_write_b16 v22, v101 offset:1152 + ds_write_b16 v22, v100 offset:1280 + ds_write_b16 v22, v99 offset:1408 + ds_write_b16 v22, v98 offset:2048 + ds_write_b16 v22, v97 offset:2176 + ds_write_b16 v22, v96 offset:2304 + ds_write_b16 v22, v95 offset:2432 + ds_write_b16 v22, v94 offset:3072 + ds_write_b16 v22, v93 offset:3200 + ds_write_b16 v22, v92 offset:3328 + ds_write_b16 v22, v209 offset:3456 + ds_write_b16 v22, v210 offset:8192 + ds_write_b16 v22, v211 offset:8320 + ds_write_b16 v22, v212 offset:8448 + ds_write_b16 v22, v213 offset:8576 + ds_write_b16 v22, v214 offset:9216 + ds_write_b16 v22, v215 offset:9344 + ds_write_b16 v22, v216 offset:9472 + ds_write_b16 v22, v217 offset:9600 + ds_write_b16 v22, v218 offset:10240 + ds_write_b16 v22, v219 offset:10368 + ds_write_b16 v22, v220 offset:10496 + ds_write_b16 v22, v221 offset:10624 + ds_write_b16 v22, v222 offset:11264 + ds_write_b16 v22, v223 offset:11392 + ds_write_b16 v22, v224 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[92:95], v23 offset:384 + v_or_b32_e32 v31, 64, v24 + v_add_u32_e32 v40, v0, v31 + v_lshlrev_b32_e32 v41, 1, v40 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v41, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v40 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[92:95], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v162 + ds_write_b16 v22, v163 offset:128 + ds_write_b16 v22, v164 offset:256 + ds_write_b16 v22, v165 offset:384 + ds_write_b16 v22, v166 offset:1024 + ds_write_b16 v22, v167 offset:1152 + ds_write_b16 v22, v168 offset:1280 + ds_write_b16 v22, v169 offset:1408 + ds_write_b16 v22, v170 offset:2048 + ds_write_b16 v22, v171 offset:2176 + ds_write_b16 v22, v172 offset:2304 + ds_write_b16 v22, v173 offset:2432 + ds_write_b16 v22, v174 offset:3072 + ds_write_b16 v22, v175 offset:3200 + ds_write_b16 v22, v176 offset:3328 + ds_write_b16 v22, v75 offset:3456 + ds_write_b16 v22, v76 offset:8192 + ds_write_b16 v22, v77 offset:8320 + ds_write_b16 v22, v78 offset:8448 + ds_write_b16 v22, v79 offset:8576 + ds_write_b16 v22, v80 offset:9216 + ds_write_b16 v22, v81 offset:9344 + ds_write_b16 v22, v82 offset:9472 + ds_write_b16 v22, v83 offset:9600 + ds_write_b16 v22, v84 offset:10240 + ds_write_b16 v22, v85 offset:10368 + ds_write_b16 v22, v86 offset:10496 + ds_write_b16 v22, v87 offset:10624 + ds_write_b16 v22, v88 offset:11264 + ds_write_b16 v22, v89 offset:11392 + ds_write_b16 v22, v90 offset:11520 + ds_write_b16 v22, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[76:79], v23 offset:384 + v_or_b32_e32 v40, 0x80, v24 + v_add_u32_e32 v41, v0, v40 + v_lshlrev_b32_e32 v75, 1, v41 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v41 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[76:79], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v74 + ds_write_b16 v22, v73 offset:128 + ds_write_b16 v22, v72 offset:256 + ds_write_b16 v22, v71 offset:384 + ds_write_b16 v22, v134 offset:1024 + ds_write_b16 v22, v135 offset:1152 + ds_write_b16 v22, v136 offset:1280 + ds_write_b16 v22, v137 offset:1408 + ds_write_b16 v22, v138 offset:2048 + ds_write_b16 v22, v139 offset:2176 + ds_write_b16 v22, v140 offset:2304 + ds_write_b16 v22, v141 offset:2432 + ds_write_b16 v22, v142 offset:3072 + ds_write_b16 v22, v143 offset:3200 + ds_write_b16 v22, v144 offset:3328 + ds_write_b16 v22, v145 offset:3456 + ds_write_b16 v22, v146 offset:8192 + ds_write_b16 v22, v147 offset:8320 + ds_write_b16 v22, v148 offset:8448 + ds_write_b16 v22, v149 offset:8576 + ds_write_b16 v22, v150 offset:9216 + ds_write_b16 v22, v151 offset:9344 + ds_write_b16 v22, v152 offset:9472 + ds_write_b16 v22, v153 offset:9600 + ds_write_b16 v22, v154 offset:10240 + ds_write_b16 v22, v155 offset:10368 + ds_write_b16 v22, v156 offset:10496 + ds_write_b16 v22, v157 offset:10624 + ds_write_b16 v22, v158 offset:11264 + ds_write_b16 v22, v159 offset:11392 + ds_write_b16 v22, v160 offset:11520 + ds_write_b16 v22, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[76:79], v23 offset:384 + v_or_b32_e32 v41, 0xc0, v24 + v_add_u32_e32 v0, v0, v41 + v_lshlrev_b32_e32 v73, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v73, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[76:79], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, v207 offset:128 + ds_write_b16 v22, v206 offset:256 + ds_write_b16 v22, a0 offset:384 + ds_write_b16 v22, a1 offset:1024 + ds_write_b16 v22, v70 offset:1152 + ds_write_b16 v22, v69 offset:1280 + ds_write_b16 v22, v68 offset:1408 + ds_write_b16 v22, v67 offset:2048 + ds_write_b16 v22, v60 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v115 offset:8320 + ds_write_b16 v22, v116 offset:8448 + ds_write_b16 v22, v117 offset:8576 + ds_write_b16 v22, v118 offset:9216 + ds_write_b16 v22, v119 offset:9344 + ds_write_b16 v22, v120 offset:9472 + ds_write_b16 v22, v121 offset:9600 + ds_write_b16 v22, v122 offset:10240 + ds_write_b16 v22, v123 offset:10368 + ds_write_b16 v22, v124 offset:10496 + ds_write_b16 v22, v125 offset:10624 + ds_write_b16 v22, v126 offset:11264 + ds_write_b16 v22, v127 offset:11392 + ds_write_b16 v22, v128 offset:11520 + ds_write_b16 v22, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[60:63], v23 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v64, v0, s16 + v_add_u32_e32 v0, v64, v41 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[60:63], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v114 + ds_write_b16 v22, v193 offset:128 + ds_write_b16 v22, v194 offset:256 + ds_write_b16 v22, v195 offset:384 + ds_write_b16 v22, v196 offset:1024 + ds_write_b16 v22, v197 offset:1152 + ds_write_b16 v22, v198 offset:1280 + ds_write_b16 v22, v199 offset:1408 + ds_write_b16 v22, v200 offset:2048 + ds_write_b16 v22, v48 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v49 offset:3456 + ds_write_b16 v22, v107 offset:8192 + ds_write_b16 v22, v108 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v185 offset:9600 + ds_write_b16 v22, v184 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[44:47], v23 offset:384 + v_add_u32_e32 v0, v64, v40 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[44:47], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v50 offset:8192 + ds_write_b16 v22, v51 offset:8320 + ds_write_b16 v22, v52 offset:8448 + ds_write_b16 v22, v53 offset:8576 + ds_write_b16 v22, v54 offset:9216 + ds_write_b16 v22, v55 offset:9344 + ds_write_b16 v22, v56 offset:9472 + ds_write_b16 v22, v57 offset:9600 + ds_write_b16 v22, v58 offset:10240 + ds_write_b16 v22, v59 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v64, v31 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v25, a49 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a48 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a39 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a38 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a37 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a36 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a35 + v_cvt_f16_f32_e32 v31, v31 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + v_accvgpr_read_b32 v33, a33 + v_cvt_f16_f32_e32 v33, v33 + v_accvgpr_read_b32 v34, a32 + v_cvt_f16_f32_e32 v34, v34 + ds_write_b16 v22, v0 + ds_write_b16 v22, v1 offset:128 + ds_write_b16 v22, v2 offset:256 + ds_write_b16 v22, v3 offset:384 + ds_write_b16 v22, v4 offset:1024 + ds_write_b16 v22, v5 offset:1152 + ds_write_b16 v22, v6 offset:1280 + ds_write_b16 v22, v7 offset:1408 + ds_write_b16 v22, v8 offset:2048 + ds_write_b16 v22, v9 offset:2176 + ds_write_b16 v22, v10 offset:2304 + ds_write_b16 v22, v11 offset:2432 + ds_write_b16 v22, v12 offset:3072 + ds_write_b16 v22, v13 offset:3200 + ds_write_b16 v22, v14 offset:3328 + ds_write_b16 v22, v15 offset:3456 + ds_write_b16 v22, v16 offset:8192 + ds_write_b16 v22, v17 offset:8320 + ds_write_b16 v22, v18 offset:8448 + ds_write_b16 v22, v19 offset:8576 + ds_write_b16 v22, v20 offset:9216 + ds_write_b16 v22, v21 offset:9344 + ds_write_b16 v22, v25 offset:9472 + ds_write_b16 v22, v26 offset:9600 + ds_write_b16 v22, v27 offset:10240 + ds_write_b16 v22, v28 offset:10368 + ds_write_b16 v22, v29 offset:10496 + ds_write_b16 v22, v30 offset:10624 + ds_write_b16 v22, v31 offset:11264 + ds_write_b16 v22, v32 offset:11392 + ds_write_b16 v22, v33 offset:11520 + ds_write_b16 v22, v34 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v64, v24 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end19: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end19-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 31436 +; TotalNumSgprs: 36 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB20_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB20_5 +; %bb.2: ; %.lr.ph.preheader + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v2, v6 + v_mov_b32_e32 v4, v0 +.LBB20_3: ; %.lr.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[8:9], s[8:9], 0, v[2:3] + global_load_ubyte v3, v[8:9], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_waitcnt vmcnt(1) + v_cvt_f32_fp8_sdwa v3, v3 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_fp8_sdwa v5, v5 src0_sel:BYTE_0 + s_add_i32 s6, s6, -1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v3, v5 + v_add_u32_e32 v2, s7, v2 + s_cbranch_scc0 .LBB20_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB20_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB20_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end20: + .size _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii, .Lfunc_end20-_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 432 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_waitcnt lgkmcnt(0) + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v0, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s23, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s18, s18, s15 + s_sub_i32 s6, s6, s18 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s3, s3, 1 + s_add_u32 s10, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s22, s2 + s_add_u32 s14, s2, s3 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[18:19], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[18:19] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v4, -1, 0 + s_cbranch_scc0 .LBB21_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v4 + v_lshlrev_b32_e32 v0, 4, v225 + v_and_b32_e32 v0, 48, v0 + v_and_b32_e32 v1, 0x7c, v225 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v5, s11, v1 + v_add_u32_e32 v1, s20, v5 + v_mad_u64_u32 v[2:3], s[18:19], v1, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[24:27], v2, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v2 + buffer_load_dwordx4 v[30:33], v1, s[8:11], 0 offen + v_and_b32_e32 v2, 31, v225 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[34:37], v3, s[8:11], 0 offen + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v1, 3, v225 + v_lshrrev_b32_e32 v6, 5, v225 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s23, s18, 0x3fffffe0 + v_and_or_b32 v54, v1, 8, v6 + s_and_b32 s18, s19, 32 + v_or_b32_e32 v55, s23, v2 + v_add_u32_e32 v1, s21, v5 + v_or_b32_e32 v2, s18, v2 + v_lshrrev_b32_e32 v6, 3, v0 + v_ashrrev_i32_e32 v7, 1, v5 + v_ashrrev_i32_e32 v8, 31, v5 + v_lshlrev_b32_e32 v9, 6, v5 + v_or_b32_e32 v10, 1, v5 + v_lshrrev_b32_e32 v11, 31, v5 + v_lshrrev_b32_e32 v12, 1, v55 + v_bfe_u32 v13, v55, 1, 4 + v_mad_u64_u32 v[0:1], s[24:25], v1, s22, v[0:1] + v_add_u32_e32 v1, s7, v3 + buffer_load_dwordx4 v[38:41], v1, s[8:11], 0 offen + v_lshrrev_b32_e32 v14, 1, v2 + v_bfe_u32 v20, v2, 1, 4 + v_lshrrev_b32_e32 v1, 28, v8 + v_or_b32_e32 v2, 1, v6 + buffer_load_dwordx4 v[42:45], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[46:49], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[50:53], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[56:59], v0, s[12:15], 0 offen + v_add_u32_e32 v0, v10, v11 + v_or_b32_e32 v3, 1, v7 + v_xor_b32_e32 v8, v13, v54 + v_lshlrev_b32_e32 v15, 7, v12 + v_xor_b32_e32 v28, v20, v54 + v_lshlrev_b32_e32 v16, 7, v14 + v_add_u32_e32 v17, v7, v1 + v_sub_u32_e32 v18, v6, v2 + v_ashrrev_i32_e32 v19, 1, v0 + v_and_b32_e32 v21, 0x1ffffffe, v0 + v_ashrrev_i32_e32 v0, 31, v0 + v_and_b32_e32 v17, -16, v17 + v_sub_u32_e32 v22, v19, v7 + v_sub_u32_e32 v10, v10, v21 + v_lshrrev_b32_e32 v0, 28, v0 + v_sub_u32_e32 v7, v7, v17 + v_lshl_or_b32 v10, v10, 3, v2 + v_add_u32_e32 v0, v19, v0 + v_xor_b32_e32 v17, v7, v6 + v_xor_b32_e32 v7, v7, v2 + v_add_u32_e32 v21, v10, v18 + v_and_b32_e32 v0, -16, v0 + v_lshl_add_u32 v17, v17, 3, v9 + v_lshl_add_u32 v9, v7, 3, v9 + v_sub_u32_e32 v0, v19, v0 + v_xor_b32_e32 v21, v21, v0 + v_lshl_add_u32 v22, v22, 7, v9 + v_xor_b32_e32 v0, v10, v0 + v_sub_u32_e32 v10, v21, v7 + v_sub_u32_e32 v7, v0, v7 + v_lshl_add_u32 v10, v10, 3, v22 + v_lshl_add_u32 v7, v7, 3, v22 + s_waitcnt vmcnt(7) + ds_write_b64 v17, v[24:25] + ds_write_b64 v9, v[26:27] + s_waitcnt vmcnt(6) + ds_write_b64 v10, v[30:31] + ds_write_b64 v7, v[32:33] + v_sub_u32_e32 v19, v3, v19 + v_add_u32_e32 v1, v3, v1 + v_and_b32_e32 v1, -16, v1 + v_sub_u32_e32 v1, v3, v1 + v_xor_b32_e32 v6, v1, v6 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v19, 7, v19 + v_add3_u32 v0, v0, v19, v7 + s_waitcnt vmcnt(5) + ds_write_b64 v0, v[34:35] + v_xor_b32_e32 v1, v1, v2 + v_sub_u32_e32 v6, v1, v6 + v_lshl_add_u32 v6, v6, 3, v0 + ds_write_b64 v6, v[36:37] + v_or_b32_e32 v5, 3, v5 + v_add_u32_e32 v11, v5, v11 + v_ashrrev_i32_e32 v19, 1, v11 + v_sub_u32_e32 v3, v19, v3 + v_and_b32_e32 v21, 0x1ffffffe, v11 + v_sub_u32_e32 v5, v5, v21 + v_lshl_or_b32 v2, v5, 3, v2 + v_add_u32_e32 v5, v2, v18 + v_ashrrev_i32_e32 v11, 31, v11 + v_lshrrev_b32_e32 v11, 28, v11 + v_add_u32_e32 v11, v19, v11 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v19, v11 + v_xor_b32_e32 v5, v5, v11 + v_sub_u32_e32 v1, v5, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v3, 7, v3 + v_add3_u32 v1, v1, v3, v6 + s_waitcnt vmcnt(4) + ds_write_b64 v1, v[38:39] + v_xor_b32_e32 v2, v2, v11 + v_sub_u32_e32 v2, v2, v5 + v_lshl_add_u32 v2, v2, 3, v1 + ds_write_b64 v2, v[40:41] + s_waitcnt vmcnt(3) + ds_write_b64 v17, v[42:43] offset:16384 + ds_write_b64 v9, v[44:45] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v10, v[46:47] offset:16384 + ds_write_b64 v7, v[48:49] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v0, v[50:51] offset:16384 + ds_write_b64 v6, v[52:53] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[56:57] offset:16384 + ds_write_b64 v2, v[58:59] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v0, v8, 3, v15 + v_add_u32_e32 v5, 2, v54 + v_xor_b32_e32 v1, v5, v13 + v_lshl_add_u32 v2, v1, 3, v15 + v_or_b32_e32 v56, 4, v54 + v_xor_b32_e32 v1, v56, v13 + v_lshl_add_u32 v3, v1, 3, v15 + v_add_u32_e32 v57, 6, v54 + v_xor_b32_e32 v44, v57, v13 + v_lshl_add_u32 v10, v44, 3, v15 + ds_read_b64 v[0:1], v0 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[8:9], v3 + ds_read_b64 v[2:3], v10 + v_add_u32_e32 v11, 64, v55 + v_lshrrev_b32_e32 v48, 1, v11 + v_sub_u32_e32 v12, v48, v12 + v_bfe_u32 v45, v11, 1, 4 + v_xor_b32_e32 v11, v45, v54 + v_sub_u32_e32 v11, v11, v44 + v_lshl_add_u32 v46, v12, 7, v10 + v_lshl_add_u32 v10, v11, 3, v46 + ds_read_b64 v[10:11], v10 + v_xor_b32_e32 v12, v45, v5 + v_sub_u32_e32 v12, v12, v44 + v_lshl_add_u32 v47, v12, 3, v46 + v_xor_b32_e32 v12, v45, v56 + v_sub_u32_e32 v12, v12, v44 + v_lshl_add_u32 v49, v12, 3, v46 + v_lshl_or_b32 v12, v28, 3, v16 + v_add_u32_e32 v13, -16, v14 + s_cmp_eq_u32 s18, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v13, v13, v14, vcc + v_xor_b32_e32 v14, v13, v5 + v_lshl_add_u32 v14, v14, 3, v16 + v_xor_b32_e32 v15, v13, v56 + v_lshl_add_u32 v17, v15, 3, v16 + v_xor_b32_e32 v21, v13, v57 + v_lshl_add_u32 v22, v21, 3, v16 + ds_read_b64 v[12:13], v12 offset:16384 + ds_read_b64 v[14:15], v14 offset:16384 + ds_read_b64 v[16:17], v17 offset:16384 + ds_read_b64 v[18:19], v22 offset:16384 + v_sub_u32_e32 v21, v28, v21 + v_lshl_add_u32 v21, v21, 3, v22 + v_xor_b32_e32 v22, v20, v5 + v_sub_u32_e32 v22, v22, v28 + v_lshlrev_b32_e32 v38, 3, v22 + v_add_u32_e32 v22, v21, v38 + v_xor_b32_e32 v23, v20, v56 + v_sub_u32_e32 v23, v23, v28 + v_lshlrev_b32_e32 v39, 3, v23 + v_add_u32_e32 v24, v21, v39 + v_xor_b32_e32 v29, v20, v57 + v_sub_u32_e32 v20, v29, v28 + v_lshlrev_b32_e32 v40, 3, v20 + v_add_u32_e32 v30, v21, v40 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[12:13], 0 + ds_read_b64 v[20:21], v21 offset:20480 + ds_read_b64 v[22:23], v22 offset:20480 + ds_read_b64 v[24:25], v24 offset:20480 + ds_read_b64 v[26:27], v30 offset:20480 + v_sub_u32_e32 v28, v28, v29 + v_lshlrev_b32_e32 v36, 3, v28 + v_add_u32_e32 v28, v30, v36 + v_add_u32_e32 v30, v28, v38 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[20:21], 0 + v_add_u32_e32 v32, v28, v39 + v_add_u32_e32 v37, v28, v40 + ds_read_b64 v[28:29], v28 offset:24576 + ds_read_b64 v[30:31], v30 offset:24576 + ds_read_b64 v[32:33], v32 offset:24576 + ds_read_b64 v[34:35], v37 offset:24576 + v_add_u32_e32 v41, v37, v36 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[28:29], 0 + ds_read_b64 v[36:37], v41 offset:28672 + v_add_u32_e32 v38, v41, v38 + v_add_u32_e32 v42, v41, v39 + v_add_u32_e32 v43, v41, v40 + ds_read_b64 v[38:39], v38 offset:28672 + ds_read_b64 v[40:41], v42 offset:28672 + ds_read_b64 v[42:43], v43 offset:28672 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[36:37], 0 + v_xor_b32_e32 v50, v45, v57 + v_sub_u32_e32 v0, v50, v44 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v58, v0, v46 + ds_read_b64 v[0:1], v47 + ds_read_b64 v[44:45], v49 + ds_read_b64 v[46:47], v58 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[10:11], v[12:13], 0 + v_add_u32_e32 v49, 0x80, v55 + v_lshrrev_b32_e32 v59, 1, v49 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[10:11], v[20:21], 0 + v_sub_u32_e32 v48, v59, v48 + v_bfe_u32 v51, v49, 1, 4 + v_xor_b32_e32 v52, v51, v54 + v_sub_u32_e32 v49, v52, v50 + v_lshlrev_b32_e32 v48, 7, v48 + v_lshl_add_u32 v60, v49, 3, v48 + v_add_u32_e32 v50, v58, v60 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[10:11], v[28:29], 0 + ds_read_b64 v[48:49], v50 + v_xor_b32_e32 v53, v51, v5 + v_sub_u32_e32 v53, v53, v52 + v_lshl_add_u32 v53, v53, 3, v50 + v_xor_b32_e32 v61, v51, v56 + v_sub_u32_e32 v61, v61, v52 + v_lshl_add_u32 v61, v61, 3, v50 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[10:11], v[36:37], 0 + v_xor_b32_e32 v62, v51, v57 + v_sub_u32_e32 v10, v62, v52 + v_lshlrev_b32_e32 v63, 3, v10 + v_add_u32_e32 v52, v50, v63 + ds_read_b64 v[10:11], v53 + ds_read_b64 v[50:51], v61 + ds_read_b64 v[52:53], v52 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[48:49], v[12:13], 0 + v_add3_u32 v58, v60, v58, v63 + v_add_u32_e32 v55, 0xc0, v55 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[48:49], v[20:21], 0 + v_lshrrev_b32_e32 v60, 1, v55 + v_sub_u32_e32 v59, v60, v59 + v_bfe_u32 v60, v55, 1, 4 + v_xor_b32_e32 v61, v60, v54 + v_sub_u32_e32 v54, v61, v62 + v_lshlrev_b32_e32 v54, 3, v54 + v_lshlrev_b32_e32 v55, 7, v59 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[48:49], v[28:29], 0 + v_add3_u32 v58, v54, v55, v58 + ds_read_b64 v[54:55], v58 + v_xor_b32_e32 v5, v60, v5 + v_sub_u32_e32 v5, v5, v61 + v_lshl_add_u32 v5, v5, 3, v58 + v_xor_b32_e32 v56, v60, v56 + v_sub_u32_e32 v56, v56, v61 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[48:49], v[36:37], 0 + v_lshl_add_u32 v56, v56, 3, v58 + v_xor_b32_e32 v48, v60, v57 + v_sub_u32_e32 v48, v48, v61 + v_lshl_add_u32 v58, v48, 3, v58 + ds_read_b64 v[48:49], v5 + ds_read_b64 v[56:57], v56 + ds_read_b64 v[58:59], v58 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[54:55], v[12:13], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[54:55], v[20:21], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[54:55], v[28:29], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[54:55], v[36:37], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[6:7], v[14:15], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[6:7], v[22:23], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[6:7], v[30:31], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[6:7], v[38:39], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[14:15], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[22:23], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[30:31], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[38:39], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[10:11], v[14:15], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[10:11], v[22:23], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[10:11], v[30:31], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[10:11], v[38:39], a[48:63] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[48:49], v[14:15], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[48:49], v[22:23], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[48:49], v[30:31], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[48:49], v[38:39], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[8:9], v[16:17], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[8:9], v[24:25], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[8:9], v[32:33], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[8:9], v[40:41], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[44:45], v[16:17], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[44:45], v[24:25], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[44:45], v[32:33], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[44:45], v[40:41], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[50:51], v[16:17], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[50:51], v[24:25], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[50:51], v[32:33], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[50:51], v[40:41], a[48:63] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[56:57], v[16:17], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[56:57], v[24:25], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[56:57], v[32:33], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[56:57], v[40:41], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[2:3], v[18:19], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[2:3], v[26:27], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[2:3], v[34:35], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[2:3], v[42:43], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[46:47], v[18:19], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[46:47], v[26:27], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[46:47], v[34:35], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[46:47], v[42:43], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[52:53], v[18:19], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[52:53], v[26:27], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[52:53], v[34:35], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[52:53], v[42:43], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[58:59], v[18:19], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[58:59], v[26:27], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[58:59], v[34:35], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[58:59], v[42:43], a[176:191] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB21_3 + s_branch .LBB21_10 +.LBB21_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr255 + ; implicit-def: $agpr176_agpr177_agpr178_agpr179_agpr180_agpr181_agpr182_agpr183_agpr184_agpr185_agpr186_agpr187_agpr188_agpr189_agpr190_agpr191 + ; implicit-def: $vgpr225 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB21_3: + s_mov_b32 s11, s7 + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v4 + v_lshlrev_b32_e32 v0, 4, v225 + v_and_b32_e32 v4, 48, v0 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v54, 0x7c, v225 + v_add_u32_e32 v1, s18, v54 + v_add_u32_e32 v0, s20, v1 + v_mad_u64_u32 v[2:3], s[18:19], v0, s11, v[4:5] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[24:27], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[28:31], v0, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v0 + buffer_load_dwordx4 v[32:35], v3, s[8:11], 0 offen + v_lshrrev_b32_e32 v0, 5, v225 + v_and_b32_e32 v5, 31, v225 + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v6, 3, v225 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s18, s18, 0x3fffffe0 + v_and_or_b32 v7, v6, 8, v0 + v_and_or_b32 v0, s19, 32, v5 + v_or_b32_e32 v8, s18, v5 + v_add_u32_e32 v5, s21, v1 + v_lshrrev_b32_e32 v9, 1, v0 + v_bfe_u32 v6, v0, 1, 4 + v_lshrrev_b32_e32 v55, 3, v4 + v_ashrrev_i32_e32 v12, 1, v1 + v_ashrrev_i32_e32 v11, 31, v1 + v_lshlrev_b32_e32 v13, 6, v1 + v_or_b32_e32 v14, 1, v1 + v_lshrrev_b32_e32 v15, 31, v1 + v_lshrrev_b32_e32 v0, 1, v8 + v_bfe_u32 v10, v8, 1, 4 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[36:39], v3, s[8:11], 0 offen + v_mad_u64_u32 v[4:5], s[18:19], v5, s22, v[4:5] + v_xor_b32_e32 v5, v6, v7 + v_lshlrev_b32_e32 v9, 7, v9 + buffer_load_dwordx4 v[40:43], v4, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v4 + buffer_load_dwordx4 v[44:47], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[48:51], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[58:61], v3, s[12:15], 0 offen + v_lshrrev_b32_e32 v16, 28, v11 + v_or_b32_e32 v56, 1, v55 + v_add_u32_e32 v17, v14, v15 + v_or_b32_e32 v18, 1, v12 + v_xor_b32_e32 v3, v10, v7 + v_lshlrev_b32_e32 v11, 7, v0 + v_add_u32_e32 v19, v12, v16 + v_sub_u32_e32 v57, v55, v56 + v_ashrrev_i32_e32 v20, 1, v17 + v_and_b32_e32 v21, 0x1ffffffe, v17 + v_ashrrev_i32_e32 v17, 31, v17 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v22, v20, v12 + v_sub_u32_e32 v14, v14, v21 + v_lshrrev_b32_e32 v17, 28, v17 + v_sub_u32_e32 v12, v12, v19 + v_lshl_or_b32 v14, v14, 3, v56 + v_add_u32_e32 v17, v20, v17 + v_xor_b32_e32 v19, v12, v55 + v_xor_b32_e32 v12, v12, v56 + v_add_u32_e32 v21, v14, v57 + v_and_b32_e32 v17, -16, v17 + v_lshl_add_u32 v19, v19, 3, v13 + v_lshl_add_u32 v13, v12, 3, v13 + v_sub_u32_e32 v17, v20, v17 + v_xor_b32_e32 v21, v21, v17 + v_lshl_add_u32 v22, v22, 7, v13 + v_xor_b32_e32 v14, v14, v17 + v_sub_u32_e32 v17, v21, v12 + v_sub_u32_e32 v12, v14, v12 + v_lshl_add_u32 v17, v17, 3, v22 + v_lshl_add_u32 v12, v12, 3, v22 + s_waitcnt vmcnt(7) + ds_write_b64 v19, v[24:25] + ds_write_b64 v13, v[26:27] + s_waitcnt vmcnt(6) + ds_write_b64 v17, v[28:29] + ds_write_b64 v12, v[30:31] + v_sub_u32_e32 v20, v18, v20 + v_add_u32_e32 v16, v18, v16 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v16, v18, v16 + v_xor_b32_e32 v21, v16, v55 + v_sub_u32_e32 v14, v21, v14 + v_lshlrev_b32_e32 v14, 3, v14 + v_lshlrev_b32_e32 v20, 7, v20 + v_add3_u32 v14, v14, v20, v12 + s_waitcnt vmcnt(5) + ds_write_b64 v14, v[32:33] + v_xor_b32_e32 v16, v16, v56 + v_sub_u32_e32 v20, v16, v21 + v_lshl_add_u32 v20, v20, 3, v14 + ds_write_b64 v20, v[34:35] + v_or_b32_e32 v1, 3, v1 + v_add_u32_e32 v15, v1, v15 + v_ashrrev_i32_e32 v21, 1, v15 + v_sub_u32_e32 v18, v21, v18 + v_and_b32_e32 v22, 0x1ffffffe, v15 + v_sub_u32_e32 v1, v1, v22 + v_lshl_or_b32 v1, v1, 3, v56 + v_add_u32_e32 v22, v1, v57 + v_ashrrev_i32_e32 v15, 31, v15 + v_lshrrev_b32_e32 v15, 28, v15 + v_add_u32_e32 v15, v21, v15 + v_and_b32_e32 v15, -16, v15 + v_sub_u32_e32 v15, v21, v15 + v_xor_b32_e32 v21, v22, v15 + v_sub_u32_e32 v16, v21, v16 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshlrev_b32_e32 v18, 7, v18 + v_add3_u32 v16, v16, v18, v20 + s_waitcnt vmcnt(4) + ds_write_b64 v16, v[36:37] + v_xor_b32_e32 v1, v1, v15 + v_sub_u32_e32 v1, v1, v21 + v_lshl_add_u32 v1, v1, 3, v16 + ds_write_b64 v1, v[38:39] + s_waitcnt vmcnt(3) + ds_write_b64 v19, v[40:41] offset:16384 + ds_write_b64 v13, v[42:43] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v17, v[44:45] offset:16384 + ds_write_b64 v12, v[46:47] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v14, v[48:49] offset:16384 + ds_write_b64 v20, v[50:51] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v16, v[58:59] offset:16384 + ds_write_b64 v1, v[60:61] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v14, 2, v7 + v_add_u32_e32 v13, 4, v7 + v_add_u32_e32 v12, 6, v7 + v_add_u32_e32 v15, 64, v8 + s_cbranch_vccnz .LBB21_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit993.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v14, v10 + v_lshl_add_u32 v29, v1, 3, v11 + v_xor_b32_e32 v1, v13, v10 + v_lshl_add_u32 v26, v1, 3, v11 + v_xor_b32_e32 v1, v12, v10 + v_lshl_add_u32 v25, v1, 3, v11 + v_lshrrev_b32_e32 v16, 1, v15 + v_sub_u32_e32 v17, v16, v0 + v_bfe_u32 v18, v15, 1, 4 + v_xor_b32_e32 v19, v18, v7 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v17, v17, 7, v25 + v_lshl_add_u32 v46, v19, 3, v17 + v_xor_b32_e32 v19, v18, v14 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v30, v19, 3, v17 + v_xor_b32_e32 v19, v18, v13 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v27, v19, 3, v17 + v_xor_b32_e32 v18, v18, v12 + v_sub_u32_e32 v1, v18, v1 + v_lshl_add_u32 v22, v1, 3, v17 + v_add_u32_e32 v1, 0x80, v8 + v_lshrrev_b32_e32 v17, 1, v1 + v_sub_u32_e32 v16, v17, v16 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v19, v1, v7 + v_sub_u32_e32 v18, v19, v18 + v_lshlrev_b32_e32 v18, 3, v18 + v_lshlrev_b32_e32 v16, 7, v16 + v_add3_u32 v47, v18, v16, v22 + v_xor_b32_e32 v16, v1, v14 + v_sub_u32_e32 v16, v16, v19 + v_lshl_add_u32 v36, v16, 3, v47 + v_xor_b32_e32 v16, v1, v13 + v_sub_u32_e32 v16, v16, v19 + v_lshl_add_u32 v28, v16, 3, v47 + v_xor_b32_e32 v1, v1, v12 + v_sub_u32_e32 v16, v1, v19 + v_lshl_add_u32 v23, v16, 3, v47 + v_add_u32_e32 v16, 0xc0, v8 + v_lshrrev_b32_e32 v18, 1, v16 + v_sub_u32_e32 v17, v18, v17 + v_bfe_u32 v16, v16, 1, 4 + v_xor_b32_e32 v18, v16, v7 + v_sub_u32_e32 v1, v18, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v17, 7, v17 + v_add3_u32 v48, v1, v17, v23 + v_xor_b32_e32 v1, v16, v14 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v39, v1, 3, v48 + v_xor_b32_e32 v1, v16, v13 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v31, v1, 3, v48 + v_xor_b32_e32 v1, v16, v12 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v24, v1, 3, v48 + v_xor_b32_e32 v1, v6, v14 + v_lshl_add_u32 v42, v1, 3, v9 + v_xor_b32_e32 v16, v6, v13 + v_lshl_add_u32 v37, v16, 3, v9 + v_xor_b32_e32 v17, v6, v12 + v_lshl_add_u32 v34, v17, 3, v9 + v_sub_u32_e32 v18, v5, v17 + v_mov_b32_e32 v19, 0x1000 + v_lshl_add_u32 v18, v18, 3, v19 + v_add_u32_e32 v49, v18, v34 + v_sub_u32_e32 v1, v1, v5 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v43, v49, v1 + v_sub_u32_e32 v16, v16, v5 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v38, v49, v16 + v_sub_u32_e32 v17, v17, v5 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v32, v49, v17 + v_add_u32_e32 v50, v32, v18 + v_add_u32_e32 v44, v50, v1 + v_add_u32_e32 v40, v50, v16 + v_add_u32_e32 v33, v50, v17 + v_add_u32_e32 v51, v33, v18 + v_add_u32_e32 v45, v51, v1 + v_add_u32_e32 v41, v51, v16 + v_add_u32_e32 v35, v51, v17 + s_mov_b64 s[2:3], 0 + s_branch .LBB21_6 +.LBB21_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr29 + ; implicit-def: $vgpr26 + ; implicit-def: $vgpr25 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr30 + ; implicit-def: $vgpr27 + ; implicit-def: $vgpr22 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr28 + ; implicit-def: $vgpr23 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr31 + ; implicit-def: $vgpr24 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr34 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr32 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr33 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr35 +.LBB21_6: ; %Flow80 + v_lshl_or_b32 v53, v3, 3, v11 + v_lshl_or_b32 v52, v5, 3, v9 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB21_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v3, v4 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v1, v14, v10 + v_lshl_add_u32 v29, v1, 3, v11 + v_xor_b32_e32 v1, v13, v10 + v_lshl_add_u32 v26, v1, 3, v11 + v_xor_b32_e32 v1, v12, v10 + v_lshl_add_u32 v25, v1, 3, v11 + v_lshrrev_b32_e32 v4, 1, v15 + v_sub_u32_e32 v0, v4, v0 + v_bfe_u32 v10, v15, 1, 4 + v_xor_b32_e32 v11, v10, v7 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v0, v0, 7, v25 + v_lshl_add_u32 v46, v11, 3, v0 + v_xor_b32_e32 v11, v10, v14 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v30, v11, 3, v0 + v_xor_b32_e32 v11, v10, v13 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v27, v11, 3, v0 + v_xor_b32_e32 v10, v10, v12 + v_sub_u32_e32 v1, v10, v1 + v_lshl_add_u32 v22, v1, 3, v0 + v_add_u32_e32 v0, 0x80, v8 + v_lshrrev_b32_e32 v1, 1, v0 + v_sub_u32_e32 v4, v1, v4 + v_bfe_u32 v0, v0, 1, 4 + v_xor_b32_e32 v11, v0, v7 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_lshlrev_b32_e32 v4, 7, v4 + v_add3_u32 v47, v10, v4, v22 + v_xor_b32_e32 v4, v0, v14 + v_sub_u32_e32 v4, v4, v11 + v_lshl_add_u32 v36, v4, 3, v47 + v_xor_b32_e32 v4, v0, v13 + v_sub_u32_e32 v4, v4, v11 + v_lshl_add_u32 v28, v4, 3, v47 + v_xor_b32_e32 v0, v0, v12 + v_sub_u32_e32 v4, v0, v11 + v_lshl_add_u32 v23, v4, 3, v47 + v_add_u32_e32 v4, 0xc0, v8 + v_lshrrev_b32_e32 v8, 1, v4 + v_sub_u32_e32 v1, v8, v1 + v_bfe_u32 v4, v4, 1, 4 + v_xor_b32_e32 v7, v4, v7 + v_sub_u32_e32 v0, v7, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v48, v0, v1, v23 + v_xor_b32_e32 v0, v4, v14 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v39, v0, 3, v48 + v_xor_b32_e32 v0, v4, v13 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v31, v0, 3, v48 + v_xor_b32_e32 v0, v4, v12 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v24, v0, 3, v48 + v_xor_b32_e32 v0, v6, v14 + v_lshl_add_u32 v42, v0, 3, v9 + v_xor_b32_e32 v1, v6, v13 + v_lshl_add_u32 v37, v1, 3, v9 + v_xor_b32_e32 v4, v6, v12 + v_lshl_add_u32 v34, v4, 3, v9 + v_sub_u32_e32 v6, v5, v4 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_u32_e32 v7, 0x1000, v6 + v_add_u32_e32 v49, v7, v34 + v_add_u32_e32 v58, v6, v34 + v_sub_u32_e32 v0, v0, v5 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v43, v49, v0 + v_add_u32_e32 v59, v58, v0 + v_sub_u32_e32 v1, v1, v5 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v38, v49, v1 + v_add_u32_e32 v60, v58, v1 + v_sub_u32_e32 v4, v4, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v32, v49, v4 + v_add_u32_e32 v61, v58, v4 + v_add_u32_e32 v50, v32, v7 + v_add_u32_e32 v62, v61, v7 + v_add_u32_e32 v44, v50, v0 + v_add_u32_e32 v40, v50, v1 + v_add_u32_e32 v33, v50, v4 + v_add_u32_e32 v51, v33, v7 + v_add_u32_e32 v45, v51, v0 + v_add_u32_e32 v41, v51, v1 + v_add_u32_e32 v35, v51, v4 + s_add_i32 s2, s2, 1 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 +.LBB21_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v5, 64, v3 + v_add_u32_e32 v4, 64, v2 + buffer_load_dwordx4 v[64:67], v2, s[8:11], 0 offen offset:64 + buffer_load_dwordx4 v[68:71], v3, s[12:15], 0 offen offset:64 + v_add_u32_e32 v0, s7, v4 + v_add_u32_e32 v1, s22, v5 + v_add_u32_e32 v2, s7, v0 + buffer_load_dwordx4 v[72:75], v1, s[12:15], 0 offen + v_add_u32_e32 v1, s22, v1 + buffer_load_dwordx4 v[88:91], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[84:87], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[76:79], v1, s[12:15], 0 offen + v_add_u32_e32 v1, s22, v1 + buffer_load_dwordx4 v[92:95], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[80:83], v1, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[0:1], v53 + ds_read_b64 v[8:9], v52 offset:16384 + ds_read_b64 v[20:21], v58 offset:20480 + ds_read_b64 v[10:11], v59 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[8:9], a[64:79] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[20:21], a[80:95] + ds_read_b64 v[96:97], v62 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[96:97], a[96:111] + ds_read_b64 v[98:99], v50 offset:20480 + ds_read_b64 v[12:13], v44 offset:20480 + ds_read_b64 v[2:3], v40 offset:20480 + ds_read_b64 v[6:7], v33 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[98:99], a[112:127] + ds_read_b64 v[0:1], v46 + ds_read_b64 v[14:15], v30 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[8:9], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[20:21], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[96:97], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[98:99], a[176:191] + ds_read_b64 v[0:1], v47 + ds_read_b64 v[16:17], v36 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[8:9], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[20:21], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[96:97], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[98:99], a[240:255] + ds_read_b64 v[0:1], v48 + ds_read_b64 v[18:19], v39 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[8:9], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[20:21], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[96:97], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[98:99], a[48:63] + ds_read_b64 v[0:1], v29 + ds_read_b64 v[20:21], v42 offset:16384 + ds_read_b64 v[96:97], v37 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[20:21], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[10:11], a[80:95] + ds_read_b64 v[98:99], v43 offset:20480 + ds_read_b64 v[100:101], v38 offset:20480 + ds_read_b64 v[8:9], v32 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[98:99], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[12:13], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[14:15], v[20:21], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[14:15], v[10:11], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[14:15], v[98:99], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[14:15], v[12:13], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[16:17], v[20:21], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[16:17], v[10:11], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[16:17], v[98:99], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[16:17], v[12:13], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[18:19], v[20:21], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[18:19], v[10:11], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[18:19], v[98:99], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[18:19], v[12:13], a[48:63] + ds_read_b64 v[0:1], v26 + ds_read_b64 v[20:21], v25 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[96:97], a[64:79] + ds_read_b64 v[18:19], v60 offset:20480 + ds_read_b64 v[10:11], v61 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[18:19], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[100:101], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[2:3], a[112:127] + ds_read_b64 v[0:1], v27 + ds_read_b64 v[12:13], v22 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[96:97], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[18:19], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[100:101], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[2:3], a[176:191] + ds_read_b64 v[0:1], v28 + ds_read_b64 v[14:15], v23 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[96:97], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[18:19], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[100:101], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[0:1], v31 + ds_read_b64 v[16:17], v24 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[96:97], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[18:19], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[100:101], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[2:3], a[48:63] + ds_read_b64 v[18:19], v34 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[20:21], v[18:19], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[20:21], v[10:11], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[20:21], v[8:9], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[20:21], v[6:7], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[12:13], v[18:19], a[128:143] + v_readfirstlane_b32 s3, v227 + s_add_i32 s2, s2, -1 + s_andn2_b32 s3, s3, 63 + v_add_u32_e32 v0, s3, v54 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[12:13], v[10:11], a[144:159] + s_cmp_gt_u32 s2, 2 + v_ashrrev_i32_e32 v1, 1, v0 + v_ashrrev_i32_e32 v2, 31, v0 + v_lshlrev_b32_e32 v20, 6, v0 + v_or_b32_e32 v21, 1, v0 + v_lshrrev_b32_e32 v3, 31, v0 + v_or_b32_e32 v0, 3, v0 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[12:13], v[8:9], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v63, 28, v2 + v_add_u32_e32 v96, v21, v3 + v_or_b32_e32 v97, 1, v1 + v_add_u32_e32 v98, v0, v3 + v_mov_b64_e32 v[2:3], v[4:5] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[12:13], v[6:7], a[176:191] + v_add_u32_e32 v4, v1, v63 + v_ashrrev_i32_e32 v5, 1, v96 + v_and_b32_e32 v12, 0x1ffffffe, v96 + v_ashrrev_i32_e32 v13, 31, v96 + v_add_u32_e32 v63, v97, v63 + v_ashrrev_i32_e32 v96, 1, v98 + v_and_b32_e32 v99, 0x1ffffffe, v98 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[14:15], v[18:19], a[192:207] + v_ashrrev_i32_e32 v98, 31, v98 + v_and_b32_e32 v4, -16, v4 + v_sub_u32_e32 v100, v5, v1 + v_sub_u32_e32 v12, v21, v12 + v_lshrrev_b32_e32 v13, 28, v13 + v_sub_u32_e32 v21, v97, v5 + v_and_b32_e32 v63, -16, v63 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[14:15], v[10:11], a[208:223] + v_sub_u32_e32 v101, v96, v97 + v_sub_u32_e32 v0, v0, v99 + v_lshrrev_b32_e32 v98, 28, v98 + v_sub_u32_e32 v1, v1, v4 + v_lshl_or_b32 v4, v12, 3, v56 + v_add_u32_e32 v12, v5, v13 + v_sub_u32_e32 v13, v97, v63 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[14:15], v[8:9], a[224:239] + v_lshlrev_b32_e32 v21, 7, v21 + v_lshl_or_b32 v0, v0, 3, v56 + v_add_u32_e32 v63, v96, v98 + v_lshlrev_b32_e32 v97, 7, v101 + v_xor_b32_e32 v98, v1, v55 + v_xor_b32_e32 v1, v1, v56 + v_add_u32_e32 v99, v4, v57 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[14:15], v[6:7], a[240:255] + v_and_b32_e32 v12, -16, v12 + v_xor_b32_e32 v14, v13, v55 + v_xor_b32_e32 v13, v13, v56 + v_add_u32_e32 v15, v0, v57 + v_and_b32_e32 v63, -16, v63 + v_lshl_add_u32 v98, v98, 3, v20 + v_lshl_add_u32 v20, v1, 3, v20 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[16:17], v[18:19], a[16:31] + v_sub_u32_e32 v5, v5, v12 + v_sub_u32_e32 v12, v13, v14 + v_sub_u32_e32 v18, v96, v63 + v_xor_b32_e32 v19, v99, v5 + v_lshl_add_u32 v63, v100, 7, v20 + v_xor_b32_e32 v4, v4, v5 + v_xor_b32_e32 v5, v15, v18 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[16:17], v[10:11], a[32:47] + v_xor_b32_e32 v0, v0, v18 + v_sub_u32_e32 v10, v19, v1 + v_sub_u32_e32 v1, v4, v1 + v_sub_u32_e32 v4, v14, v4 + v_sub_u32_e32 v11, v5, v13 + v_sub_u32_e32 v0, v0, v5 + v_lshl_add_u32 v5, v10, 3, v63 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[16:17], v[8:9], a[0:15] + v_lshl_add_u32 v1, v1, 3, v63 + v_lshlrev_b32_e32 v4, 3, v4 + v_lshlrev_b32_e32 v8, 3, v11 + v_add3_u32 v4, v4, v21, v1 + v_lshl_add_u32 v9, v12, 3, v4 + v_add3_u32 v8, v8, v97, v9 + v_lshl_add_u32 v0, v0, 3, v8 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[16:17], v[6:7], a[48:63] + s_waitcnt vmcnt(7) + ds_write_b64 v98, v[64:65] + ds_write_b64 v20, v[66:67] + s_waitcnt vmcnt(4) + ds_write_b64 v5, v[88:89] + ds_write_b64 v1, v[90:91] + s_waitcnt vmcnt(3) + ds_write_b64 v4, v[84:85] + ds_write_b64 v9, v[86:87] + s_waitcnt vmcnt(1) + ds_write_b64 v8, v[92:93] + ds_write_b64 v0, v[94:95] + ds_write_b64 v98, v[68:69] offset:16384 + ds_write_b64 v20, v[70:71] offset:16384 + ds_write_b64 v5, v[72:73] offset:16384 + ds_write_b64 v1, v[74:75] offset:16384 + ds_write_b64 v4, v[76:77] offset:16384 + ds_write_b64 v9, v[78:79] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v8, v[80:81] offset:16384 + ds_write_b64 v0, v[82:83] offset:16384 + s_cbranch_scc1 .LBB21_8 +.LBB21_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iP + v_accvgpr_read_b32 v0, a160 + v_accvgpr_read_b32 v1, a161 + v_accvgpr_read_b32 v2, a162 + v_accvgpr_read_b32 v3, a163 + v_accvgpr_read_b32 v4, a164 + v_accvgpr_read_b32 v5, a165 + v_accvgpr_read_b32 v6, a166 + v_accvgpr_read_b32 v7, a167 + v_accvgpr_read_b32 v8, a168 + v_accvgpr_read_b32 v9, a169 + v_accvgpr_read_b32 v10, a170 + v_accvgpr_read_b32 v11, a171 + v_accvgpr_read_b32 v12, a172 + v_accvgpr_read_b32 v13, a173 + v_accvgpr_read_b32 v14, a174 + v_accvgpr_read_b32 v15, a175 + v_accvgpr_read_b32 v54, a192 + v_accvgpr_read_b32 v55, a193 + v_accvgpr_read_b32 v56, a194 + v_accvgpr_read_b32 v57, a195 + v_accvgpr_read_b32 v58, a196 + v_accvgpr_read_b32 v59, a197 + v_accvgpr_read_b32 v60, a198 + v_accvgpr_read_b32 v61, a199 + v_accvgpr_read_b32 v62, a200 + v_accvgpr_read_b32 v63, a201 + v_accvgpr_read_b32 v64, a202 + v_accvgpr_read_b32 v65, a203 + v_accvgpr_read_b32 v66, a204 + v_accvgpr_read_b32 v67, a205 + v_accvgpr_read_b32 v68, a206 + v_accvgpr_read_b32 v69, a207 + v_accvgpr_read_b32 v70, a208 + v_accvgpr_read_b32 v71, a209 + v_accvgpr_read_b32 v72, a210 + v_accvgpr_read_b32 v73, a211 + v_accvgpr_read_b32 v74, a212 + v_accvgpr_read_b32 v75, a213 + v_accvgpr_read_b32 v76, a214 + v_accvgpr_read_b32 v77, a215 + v_accvgpr_read_b32 v78, a216 + v_accvgpr_read_b32 v79, a217 + v_accvgpr_read_b32 v80, a218 + v_accvgpr_read_b32 v81, a219 + v_accvgpr_read_b32 v82, a220 + v_accvgpr_read_b32 v83, a221 + v_accvgpr_read_b32 v84, a222 + v_accvgpr_read_b32 v85, a223 + v_accvgpr_read_b32 v86, a224 + v_accvgpr_read_b32 v87, a225 + v_accvgpr_read_b32 v88, a226 + v_accvgpr_read_b32 v89, a227 + v_accvgpr_read_b32 v90, a228 + v_accvgpr_read_b32 v91, a229 + v_accvgpr_read_b32 v92, a230 + v_accvgpr_read_b32 v93, a231 + v_accvgpr_read_b32 v94, a232 + v_accvgpr_read_b32 v95, a233 + v_accvgpr_read_b32 v96, a234 + v_accvgpr_read_b32 v97, a235 + v_accvgpr_read_b32 v98, a236 + v_accvgpr_read_b32 v99, a237 + v_accvgpr_read_b32 v100, a238 + v_accvgpr_read_b32 v101, a239 + v_accvgpr_read_b32 v102, a240 + v_accvgpr_read_b32 v103, a241 + v_accvgpr_read_b32 v104, a242 + v_accvgpr_read_b32 v105, a243 + v_accvgpr_read_b32 v106, a244 + v_accvgpr_read_b32 v107, a245 + v_accvgpr_read_b32 v108, a246 + v_accvgpr_read_b32 v109, a247 + v_accvgpr_read_b32 v110, a248 + v_accvgpr_read_b32 v111, a249 + v_accvgpr_read_b32 v112, a250 + v_accvgpr_read_b32 v113, a251 + v_accvgpr_read_b32 v114, a252 + v_accvgpr_read_b32 v115, a253 + v_accvgpr_read_b32 v116, a254 + v_accvgpr_read_b32 v117, a255 + v_accvgpr_read_b32 v118, a32 + v_accvgpr_read_b32 v119, a33 + v_accvgpr_read_b32 v120, a34 + v_accvgpr_read_b32 v121, a35 + v_accvgpr_read_b32 v122, a36 + v_accvgpr_read_b32 v123, a37 + v_accvgpr_read_b32 v124, a38 + v_accvgpr_read_b32 v125, a39 + v_accvgpr_read_b32 v126, a40 + v_accvgpr_read_b32 v127, a41 + v_accvgpr_read_b32 v128, a42 + v_accvgpr_read_b32 v129, a43 + v_accvgpr_read_b32 v130, a44 + v_accvgpr_read_b32 v131, a45 + v_accvgpr_read_b32 v132, a46 + v_accvgpr_read_b32 v133, a47 + v_accvgpr_read_b32 v134, a48 + v_accvgpr_read_b32 v135, a49 + v_accvgpr_read_b32 v136, a50 + v_accvgpr_read_b32 v137, a51 + v_accvgpr_read_b32 v138, a52 + v_accvgpr_read_b32 v139, a53 + v_accvgpr_read_b32 v140, a54 + v_accvgpr_read_b32 v141, a55 + v_accvgpr_read_b32 v142, a56 + v_accvgpr_read_b32 v143, a57 + v_accvgpr_read_b32 v144, a58 + v_accvgpr_read_b32 v145, a59 + v_accvgpr_read_b32 v146, a60 + v_accvgpr_read_b32 v147, a61 + v_accvgpr_read_b32 v148, a62 + v_accvgpr_read_b32 v149, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[16:17], v53 + ds_read_b64 v[18:19], v52 offset:16384 + v_accvgpr_mov_b32 a255, a79 + v_accvgpr_mov_b32 a254, a78 + v_accvgpr_mov_b32 a253, a77 + v_accvgpr_mov_b32 a252, a76 + v_accvgpr_mov_b32 a251, a75 + v_accvgpr_mov_b32 a250, a74 + v_accvgpr_mov_b32 a249, a73 + v_accvgpr_mov_b32 a248, a72 + v_accvgpr_mov_b32 a247, a71 + v_accvgpr_mov_b32 a246, a70 + v_accvgpr_mov_b32 a245, a69 + v_accvgpr_mov_b32 a244, a68 + v_accvgpr_mov_b32 a243, a67 + v_accvgpr_mov_b32 a242, a66 + v_accvgpr_mov_b32 a241, a65 + v_accvgpr_mov_b32 a240, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[16:17], v[18:19], a[240:255] + ds_read_b64 v[20:21], v49 offset:16384 + v_accvgpr_mov_b32 a239, a95 + v_accvgpr_mov_b32 a238, a94 + v_accvgpr_mov_b32 a237, a93 + v_accvgpr_mov_b32 a236, a92 + v_accvgpr_mov_b32 a235, a91 + v_accvgpr_mov_b32 a234, a90 + v_accvgpr_mov_b32 a233, a89 + v_accvgpr_mov_b32 a232, a88 + v_accvgpr_mov_b32 a231, a87 + v_accvgpr_mov_b32 a230, a86 + v_accvgpr_mov_b32 a229, a85 + v_accvgpr_mov_b32 a228, a84 + v_accvgpr_mov_b32 a227, a83 + v_accvgpr_mov_b32 a226, a82 + v_accvgpr_mov_b32 a225, a81 + v_accvgpr_mov_b32 a224, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[16:17], v[20:21], a[224:239] + ds_read_b64 v[52:53], v50 offset:16384 + v_accvgpr_mov_b32 a223, a111 + v_accvgpr_mov_b32 a222, a110 + v_accvgpr_mov_b32 a221, a109 + v_accvgpr_mov_b32 a220, a108 + v_accvgpr_mov_b32 a219, a107 + v_accvgpr_mov_b32 a218, a106 + v_accvgpr_mov_b32 a217, a105 + v_accvgpr_mov_b32 a216, a104 + v_accvgpr_mov_b32 a215, a103 + v_accvgpr_mov_b32 a214, a102 + v_accvgpr_mov_b32 a213, a101 + v_accvgpr_mov_b32 a212, a100 + v_accvgpr_mov_b32 a211, a99 + v_accvgpr_mov_b32 a210, a98 + v_accvgpr_mov_b32 a209, a97 + v_accvgpr_mov_b32 a208, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[16:17], v[52:53], a[208:223] + ds_read_b64 v[50:51], v51 offset:16384 + v_accvgpr_mov_b32 a207, a127 + v_accvgpr_mov_b32 a206, a126 + v_accvgpr_mov_b32 a205, a125 + v_accvgpr_mov_b32 a204, a124 + v_accvgpr_mov_b32 a203, a123 + v_accvgpr_mov_b32 a202, a122 + v_accvgpr_mov_b32 a201, a121 + v_accvgpr_mov_b32 a200, a120 + v_accvgpr_mov_b32 a199, a119 + v_accvgpr_mov_b32 a198, a118 + v_accvgpr_mov_b32 a197, a117 + v_accvgpr_mov_b32 a196, a116 + v_accvgpr_mov_b32 a195, a115 + v_accvgpr_mov_b32 a194, a114 + v_accvgpr_mov_b32 a193, a113 + v_accvgpr_mov_b32 a192, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[16:17], v[50:51], a[192:207] + ds_read_b64 v[16:17], v46 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[16:17], v[18:19], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[16:17], v[20:21], a[144:159] + v_accvgpr_write_b32 a143, v15 + v_accvgpr_write_b32 a142, v14 + v_accvgpr_write_b32 a141, v13 + v_accvgpr_write_b32 a140, v12 + v_accvgpr_write_b32 a139, v11 + v_accvgpr_write_b32 a138, v10 + v_accvgpr_write_b32 a137, v9 + v_accvgpr_write_b32 a136, v8 + v_accvgpr_write_b32 a135, v7 + v_accvgpr_write_b32 a134, v6 + v_accvgpr_write_b32 a133, v5 + v_accvgpr_write_b32 a132, v4 + v_accvgpr_write_b32 a131, v3 + v_accvgpr_write_b32 a130, v2 + v_accvgpr_write_b32 a129, v1 + v_accvgpr_write_b32 a128, v0 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[16:17], v[52:53], a[128:143] + v_accvgpr_mov_b32 a112, a176 + v_accvgpr_mov_b32 a113, a177 + v_accvgpr_mov_b32 a114, a178 + v_accvgpr_mov_b32 a115, a179 + v_accvgpr_mov_b32 a116, a180 + v_accvgpr_mov_b32 a117, a181 + v_accvgpr_mov_b32 a118, a182 + v_accvgpr_mov_b32 a119, a183 + v_accvgpr_mov_b32 a120, a184 + v_accvgpr_mov_b32 a121, a185 + v_accvgpr_mov_b32 a122, a186 + v_accvgpr_mov_b32 a123, a187 + v_accvgpr_mov_b32 a124, a188 + v_accvgpr_mov_b32 a125, a189 + v_accvgpr_mov_b32 a126, a190 + v_accvgpr_mov_b32 a127, a191 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[16:17], v[50:51], a[112:127] + ds_read_b64 v[0:1], v47 + v_accvgpr_write_b32 a111, v69 + v_accvgpr_write_b32 a110, v68 + v_accvgpr_write_b32 a109, v67 + v_accvgpr_write_b32 a108, v66 + v_accvgpr_write_b32 a107, v65 + v_accvgpr_write_b32 a106, v64 + v_accvgpr_write_b32 a105, v63 + v_accvgpr_write_b32 a104, v62 + v_accvgpr_write_b32 a103, v61 + v_accvgpr_write_b32 a102, v60 + v_accvgpr_write_b32 a101, v59 + v_accvgpr_write_b32 a100, v58 + v_accvgpr_write_b32 a99, v57 + v_accvgpr_write_b32 a98, v56 + v_accvgpr_write_b32 a97, v55 + v_accvgpr_write_b32 a96, v54 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[18:19], a[96:111] + v_accvgpr_write_b32 a95, v85 + v_accvgpr_write_b32 a94, v84 + v_accvgpr_write_b32 a93, v83 + v_accvgpr_write_b32 a92, v82 + v_accvgpr_write_b32 a91, v81 + v_accvgpr_write_b32 a90, v80 + v_accvgpr_write_b32 a89, v79 + v_accvgpr_write_b32 a88, v78 + v_accvgpr_write_b32 a87, v77 + v_accvgpr_write_b32 a86, v76 + v_accvgpr_write_b32 a85, v75 + v_accvgpr_write_b32 a84, v74 + v_accvgpr_write_b32 a83, v73 + v_accvgpr_write_b32 a82, v72 + v_accvgpr_write_b32 a81, v71 + v_accvgpr_write_b32 a80, v70 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[20:21], a[80:95] + v_accvgpr_write_b32 a64, v86 + v_accvgpr_write_b32 a65, v87 + v_accvgpr_write_b32 a66, v88 + v_accvgpr_write_b32 a67, v89 + v_accvgpr_write_b32 a68, v90 + v_accvgpr_write_b32 a69, v91 + v_accvgpr_write_b32 a70, v92 + v_accvgpr_write_b32 a71, v93 + v_accvgpr_write_b32 a72, v94 + v_accvgpr_write_b32 a73, v95 + v_accvgpr_write_b32 a74, v96 + v_accvgpr_write_b32 a75, v97 + v_accvgpr_write_b32 a76, v98 + v_accvgpr_write_b32 a77, v99 + v_accvgpr_write_b32 a78, v100 + v_accvgpr_write_b32 a79, v101 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[52:53], a[64:79] + v_accvgpr_write_b32 a48, v102 + v_accvgpr_write_b32 a49, v103 + v_accvgpr_write_b32 a50, v104 + v_accvgpr_write_b32 a51, v105 + v_accvgpr_write_b32 a52, v106 + v_accvgpr_write_b32 a53, v107 + v_accvgpr_write_b32 a54, v108 + v_accvgpr_write_b32 a55, v109 + v_accvgpr_write_b32 a56, v110 + v_accvgpr_write_b32 a57, v111 + v_accvgpr_write_b32 a58, v112 + v_accvgpr_write_b32 a59, v113 + v_accvgpr_write_b32 a60, v114 + v_accvgpr_write_b32 a61, v115 + v_accvgpr_write_b32 a62, v116 + v_accvgpr_write_b32 a63, v117 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[50:51], a[48:63] + ds_read_b64 v[0:1], v48 + v_accvgpr_mov_b32 a47, a31 + v_accvgpr_mov_b32 a46, a30 + v_accvgpr_mov_b32 a45, a29 + v_accvgpr_mov_b32 a44, a28 + v_accvgpr_mov_b32 a43, a27 + v_accvgpr_mov_b32 a42, a26 + v_accvgpr_mov_b32 a41, a25 + v_accvgpr_mov_b32 a40, a24 + v_accvgpr_mov_b32 a39, a23 + v_accvgpr_mov_b32 a38, a22 + v_accvgpr_mov_b32 a37, a21 + v_accvgpr_mov_b32 a36, a20 + v_accvgpr_mov_b32 a35, a19 + v_accvgpr_mov_b32 a34, a18 + v_accvgpr_mov_b32 a33, a17 + v_accvgpr_mov_b32 a32, a16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[18:19], a[32:47] + v_accvgpr_write_b32 a16, v118 + v_accvgpr_write_b32 a17, v119 + v_accvgpr_write_b32 a18, v120 + v_accvgpr_write_b32 a19, v121 + v_accvgpr_write_b32 a20, v122 + v_accvgpr_write_b32 a21, v123 + v_accvgpr_write_b32 a22, v124 + v_accvgpr_write_b32 a23, v125 + v_accvgpr_write_b32 a24, v126 + v_accvgpr_write_b32 a25, v127 + v_accvgpr_write_b32 a26, v128 + v_accvgpr_write_b32 a27, v129 + v_accvgpr_write_b32 a28, v130 + v_accvgpr_write_b32 a29, v131 + v_accvgpr_write_b32 a30, v132 + v_accvgpr_write_b32 a31, v133 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[20:21], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[52:53], a[0:15] + v_accvgpr_write_b32 a191, v149 + v_accvgpr_write_b32 a190, v148 + v_accvgpr_write_b32 a189, v147 + v_accvgpr_write_b32 a188, v146 + v_accvgpr_write_b32 a187, v145 + v_accvgpr_write_b32 a186, v144 + v_accvgpr_write_b32 a185, v143 + v_accvgpr_write_b32 a184, v142 + v_accvgpr_write_b32 a183, v141 + v_accvgpr_write_b32 a182, v140 + v_accvgpr_write_b32 a181, v139 + v_accvgpr_write_b32 a180, v138 + v_accvgpr_write_b32 a179, v137 + v_accvgpr_write_b32 a178, v136 + v_accvgpr_write_b32 a177, v135 + v_accvgpr_write_b32 a176, v134 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[50:51], a[176:191] + ds_read_b64 v[0:1], v29 + ds_read_b64 v[2:3], v42 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v43 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v44 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v45 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v30 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v36 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v39 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b64 v[0:1], v26 + ds_read_b64 v[2:3], v37 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v38 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v40 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v41 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v27 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v28 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v31 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b64 v[0:1], v25 + ds_read_b64 v[2:3], v34 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v32 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v33 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v35 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v22 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v23 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v24 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[8:9], a[176:191] +.LBB21_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iPv + v_accvgpr_read_b32 v143, a240 + v_accvgpr_read_b32 v142, a241 + v_accvgpr_read_b32 v141, a242 + v_accvgpr_read_b32 v140, a243 + v_accvgpr_read_b32 v139, a244 + v_accvgpr_read_b32 v18, a245 + v_accvgpr_read_b32 v0, a246 + v_accvgpr_read_b32 v138, a247 + v_accvgpr_read_b32 v137, a248 + v_accvgpr_read_b32 v136, a249 + v_accvgpr_read_b32 v135, a250 + v_accvgpr_read_b32 v134, a251 + v_accvgpr_read_b32 v133, a252 + v_accvgpr_read_b32 v132, a253 + v_accvgpr_read_b32 v131, a254 + v_accvgpr_read_b32 v130, a255 + v_accvgpr_read_b32 v107, a224 + v_accvgpr_read_b32 v106, a225 + v_accvgpr_read_b32 v105, a226 + v_accvgpr_read_b32 v104, a227 + v_accvgpr_read_b32 v103, a228 + v_accvgpr_read_b32 v102, a229 + v_accvgpr_read_b32 v101, a230 + v_accvgpr_read_b32 v100, a231 + v_accvgpr_read_b32 v99, a232 + v_accvgpr_read_b32 v98, a233 + v_accvgpr_read_b32 v97, a234 + v_accvgpr_read_b32 v96, a235 + v_accvgpr_read_b32 v95, a236 + v_accvgpr_read_b32 v94, a237 + v_accvgpr_read_b32 v93, a238 + v_accvgpr_read_b32 v92, a239 + v_accvgpr_read_b32 v91, a208 + v_accvgpr_read_b32 v90, a209 + v_accvgpr_read_b32 v89, a210 + v_accvgpr_read_b32 v88, a211 + v_accvgpr_read_b32 v87, a212 + v_accvgpr_read_b32 v86, a213 + v_accvgpr_read_b32 v85, a214 + v_accvgpr_read_b32 v84, a215 + v_accvgpr_read_b32 v83, a216 + v_accvgpr_read_b32 v82, a217 + v_accvgpr_read_b32 v81, a218 + v_accvgpr_read_b32 v80, a219 + v_accvgpr_read_b32 v79, a220 + v_accvgpr_read_b32 v78, a221 + v_accvgpr_read_b32 v77, a222 + v_accvgpr_read_b32 v76, a223 + v_accvgpr_read_b32 v75, a192 + v_accvgpr_read_b32 v74, a193 + v_accvgpr_read_b32 v73, a194 + v_accvgpr_read_b32 v72, a195 + v_accvgpr_read_b32 v71, a196 + v_accvgpr_read_b32 v70, a197 + v_accvgpr_read_b32 v69, a198 + v_accvgpr_read_b32 v68, a199 + v_accvgpr_read_b32 v67, a200 + v_accvgpr_read_b32 v66, a201 + v_accvgpr_read_b32 v65, a202 + v_accvgpr_read_b32 v64, a203 + v_accvgpr_read_b32 v63, a204 + v_accvgpr_read_b32 v62, a205 + v_accvgpr_read_b32 v61, a206 + v_accvgpr_read_b32 v20, a207 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v60, a80 + v_accvgpr_read_b32 v59, a81 + v_accvgpr_read_b32 v58, a82 + v_accvgpr_read_b32 v57, a83 + v_accvgpr_read_b32 v56, a84 + v_accvgpr_read_b32 v55, a85 + v_accvgpr_read_b32 v54, a86 + v_accvgpr_read_b32 v53, a87 + v_accvgpr_read_b32 v52, a88 + v_accvgpr_read_b32 v51, a89 + v_accvgpr_read_b32 v50, a90 + v_accvgpr_read_b32 v25, a91 + v_accvgpr_read_b32 v24, a92 + v_accvgpr_read_b32 v23, a93 + v_accvgpr_read_b32 v22, a94 + v_accvgpr_read_b32 v21, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v1, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a176 + v_accvgpr_read_b32 v3, a177 + v_accvgpr_read_b32 v4, a178 + v_accvgpr_read_b32 v5, a179 + v_accvgpr_read_b32 v6, a180 + v_accvgpr_read_b32 v7, a181 + v_accvgpr_read_b32 v8, a182 + v_accvgpr_read_b32 v9, a183 + v_accvgpr_read_b32 v10, a184 + v_accvgpr_read_b32 v11, a185 + v_accvgpr_read_b32 v12, a186 + v_accvgpr_read_b32 v13, a187 + v_accvgpr_read_b32 v14, a188 + v_accvgpr_read_b32 v15, a189 + v_accvgpr_read_b32 v16, a190 + v_accvgpr_read_b32 v17, a191 + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s5, s4 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v19, 3, v225 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v209, v92 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v147 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v20, v205 + v_accvgpr_write_b32 a0, v20 + v_cvt_f16_f32_e32 v20, v204 + v_accvgpr_write_b32 a1, v20 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v20, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v1 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v201, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v225 + v_lshrrev_b32_e32 v1, 1, v225 + s_cbranch_scc1 .LBB21_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB21_14 +.LBB21_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB21_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_or_b32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v132 offset:3456 + ds_write_b16 v23, v133 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s20, v25 + v_or_b32_e32 v25, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v190, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v190, v31, v41 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v76 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 0x80, v25 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v72 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0xc0, v25 + v_add_u32_e32 v31, v31, v191 + v_lshlrev_b32_e32 v192, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v207 offset:128 + ds_write_b16 v23, v206 offset:256 + ds_write_b16 v23, a0 offset:384 + ds_write_b16 v23, a1 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v61 offset:2304 + ds_write_b16 v23, v62 offset:2432 + ds_write_b16 v23, v63 offset:3072 + ds_write_b16 v23, v64 offset:3200 + ds_write_b16 v23, v65 offset:3328 + ds_write_b16 v23, v66 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v115 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v191 + v_lshlrev_b32_e32 v191, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v114 + ds_write_b16 v23, v193 offset:128 + ds_write_b16 v23, v194 offset:256 + ds_write_b16 v23, v195 offset:384 + ds_write_b16 v23, v196 offset:1024 + ds_write_b16 v23, v197 offset:1152 + ds_write_b16 v23, v198 offset:1280 + ds_write_b16 v23, v199 offset:1408 + ds_write_b16 v23, v200 offset:2048 + ds_write_b16 v23, v201 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v43 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v108 offset:8320 + ds_write_b16 v23, v109 offset:8448 + ds_write_b16 v23, v110 offset:8576 + ds_write_b16 v23, v111 offset:9216 + ds_write_b16 v23, v112 offset:9344 + ds_write_b16 v23, v113 offset:9472 + ds_write_b16 v23, v185 offset:9600 + ds_write_b16 v23, v184 offset:10240 + ds_write_b16 v23, v183 offset:10368 + ds_write_b16 v23, v182 offset:10496 + ds_write_b16 v23, v181 offset:10624 + ds_write_b16 v23, v180 offset:11264 + ds_write_b16 v23, v179 offset:11392 + ds_write_b16 v23, v178 offset:11520 + ds_write_b16 v23, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v190 + v_lshlrev_b32_e32 v190, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v3 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB21_12 +.LBB21_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_or_b32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v132 offset:3456 + ds_write_b16 v31, v133 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v41, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v131, v0, v41 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v186, 1, v131 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v186, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v131 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v107 + ds_write_b16 v31, v106 offset:128 + ds_write_b16 v31, v105 offset:256 + ds_write_b16 v31, v104 offset:384 + ds_write_b16 v31, v103 offset:1024 + ds_write_b16 v31, v102 offset:1152 + ds_write_b16 v31, v101 offset:1280 + ds_write_b16 v31, v100 offset:1408 + ds_write_b16 v31, v99 offset:2048 + ds_write_b16 v31, v98 offset:2176 + ds_write_b16 v31, v97 offset:2304 + ds_write_b16 v31, v96 offset:2432 + ds_write_b16 v31, v95 offset:3072 + ds_write_b16 v31, v94 offset:3200 + ds_write_b16 v31, v93 offset:3328 + ds_write_b16 v31, v209 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v41 + v_add_u32_e32 v94, v0, v93 + v_lshlrev_b32_e32 v95, 1, v94 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v95, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v94 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v76 offset:3456 + ds_write_b16 v31, v77 offset:8192 + ds_write_b16 v31, v78 offset:8320 + ds_write_b16 v31, v79 offset:8448 + ds_write_b16 v31, v80 offset:8576 + ds_write_b16 v31, v81 offset:9216 + ds_write_b16 v31, v82 offset:9344 + ds_write_b16 v31, v83 offset:9472 + ds_write_b16 v31, v84 offset:9600 + ds_write_b16 v31, v85 offset:10240 + ds_write_b16 v31, v86 offset:10368 + ds_write_b16 v31, v87 offset:10496 + ds_write_b16 v31, v88 offset:10624 + ds_write_b16 v31, v89 offset:11264 + ds_write_b16 v31, v90 offset:11392 + ds_write_b16 v31, v91 offset:11520 + ds_write_b16 v31, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v76, 0x80, v41 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v75 + ds_write_b16 v31, v74 offset:128 + ds_write_b16 v31, v73 offset:256 + ds_write_b16 v31, v72 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v74, 0xc0, v41 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v208 + ds_write_b16 v31, v207 offset:128 + ds_write_b16 v31, v206 offset:256 + ds_write_b16 v31, a0 offset:384 + ds_write_b16 v31, a1 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v61 offset:2304 + ds_write_b16 v31, v62 offset:2432 + ds_write_b16 v31, v63 offset:3072 + ds_write_b16 v31, v64 offset:3200 + ds_write_b16 v31, v65 offset:3328 + ds_write_b16 v31, v66 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v115 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v114 + ds_write_b16 v31, v193 offset:128 + ds_write_b16 v31, v194 offset:256 + ds_write_b16 v31, v195 offset:384 + ds_write_b16 v31, v196 offset:1024 + ds_write_b16 v31, v197 offset:1152 + ds_write_b16 v31, v198 offset:1280 + ds_write_b16 v31, v199 offset:1408 + ds_write_b16 v31, v200 offset:2048 + ds_write_b16 v31, v201 offset:2176 + ds_write_b16 v31, v47 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v44 offset:3200 + ds_write_b16 v31, v43 offset:3328 + ds_write_b16 v31, v48 offset:3456 + ds_write_b16 v31, v49 offset:8192 + ds_write_b16 v31, v108 offset:8320 + ds_write_b16 v31, v109 offset:8448 + ds_write_b16 v31, v110 offset:8576 + ds_write_b16 v31, v111 offset:9216 + ds_write_b16 v31, v112 offset:9344 + ds_write_b16 v31, v113 offset:9472 + ds_write_b16 v31, v185 offset:9600 + ds_write_b16 v31, v184 offset:10240 + ds_write_b16 v31, v183 offset:10368 + ds_write_b16 v31, v182 offset:10496 + ds_write_b16 v31, v181 offset:10624 + ds_write_b16 v31, v180 offset:11264 + ds_write_b16 v31, v179 offset:11392 + ds_write_b16 v31, v178 offset:11520 + ds_write_b16 v31, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, v61, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v3 offset:128 + ds_write_b16 v31, v4 offset:256 + ds_write_b16 v31, v5 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v41 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end21: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end21-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 26 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 24024 +; TotalNumSgprs: 32 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB22_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB22_5 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v4, v6, s7 + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v2, v0, s2 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[4:5], s[8:9], 0, v[4:5] + v_mov_b32_e32 v1, 0 +.LBB22_3: ; =>This Inner Loop Header: Depth=1 + global_load_ubyte v7, v[4:5], off + global_load_ubyte v8, v[2:3], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_fp8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_fp8_sdwa v8, v8 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_lshl_add_u64 v[4:5], v[4:5], 0, 1 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v7, v8 + s_cbranch_scc0 .LBB22_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB22_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB22_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 9 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end22: + .size _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end22-_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 9 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 448 +; TotalNumSgprs: 20 +; NumVgprs: 9 +; NumAgprs: 0 +; TotalNumVgprs: 9 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 9 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s8, s8, s15 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s10, s2, 1 + s_mul_i32 s2, s22, s3 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v225, -1, v0 + v_and_b32_e32 v35, 31, v225 + v_lshlrev_b32_e32 v228, 3, v225 + v_lshrrev_b32_e32 v9, 5, v225 + v_lshlrev_b32_e32 v11, 4, v225 + v_lshrrev_b32_e32 v10, 2, v225 + v_and_b32_e32 v8, 15, v225 + s_cbranch_scc0 .LBB23_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_and_b32_e32 v2, 48, v11 + v_and_b32_e32 v0, 0x7c, v225 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v13, s11, v0 + v_add_u32_e32 v0, s20, v13 + v_mad_u64_u32 v[0:1], s[24:25], v0, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[48:51], v0, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v0 + buffer_load_dwordx4 v[52:55], v1, s[8:11], 0 offen + v_and_or_b32 v0, v228, 8, v9 + v_lshlrev_b32_e32 v26, 3, v9 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[56:59], v3, s[8:11], 0 offen + v_and_b32_e32 v5, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v1, 12, v9 + s_lshr_b32 s19, s15, 2 + s_lshr_b32 s23, s15, 1 + v_lshl_or_b32 v22, v8, 7, v1 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v27, 3, v2 + s_and_b32 s24, s19, 0x3fffffe0 + s_and_b32 s19, s19, 0x3ffffff0 + v_and_or_b32 v2, s23, 32, v35 + v_or_b32_e32 v28, 1, v27 + v_or_b32_e32 v1, s24, v35 + v_add_u32_e32 v29, s19, v5 + v_lshrrev_b32_e32 v12, 4, v2 + v_ashrrev_i32_e32 v30, 1, v13 + v_ashrrev_i32_e32 v14, 31, v13 + v_lshlrev_b32_e32 v31, 6, v13 + v_or_b32_e32 v32, 1, v13 + v_sub_u32_e32 v33, v27, v28 + v_lshrrev_b32_e32 v34, 31, v13 + v_add_u32_e32 v2, s7, v3 + buffer_load_dwordx4 v[60:63], v2, s[8:11], 0 offen + v_lshrrev_b32_e32 v36, 1, v1 + v_bfe_u32 v37, v1, 1, 4 + v_mad_u64_u32 v[6:7], s[24:25], v29, s22, v[4:5] + v_xor_b32_e32 v38, v12, v8 + buffer_load_dwordx4 v[2:5], v6, s[12:15], 0 offen + v_lshrrev_b32_e32 v7, 28, v14 + v_add_u32_e32 v39, v32, v34 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[14:17], v6, s[12:15], 0 offen + v_or_b32_e32 v40, 1, v30 + v_xor_b32_e32 v41, v37, v0 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[18:21], v6, s[12:15], 0 offen + v_lshlrev_b32_e32 v42, 7, v36 + v_lshl_or_b32 v43, v38, 2, v22 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[22:25], v6, s[12:15], 0 offen + v_add_u32_e32 v6, v30, v7 + v_ashrrev_i32_e32 v44, 1, v39 + v_and_b32_e32 v45, 0x1ffffffe, v39 + v_ashrrev_i32_e32 v39, 31, v39 + v_and_b32_e32 v6, -16, v6 + v_sub_u32_e32 v46, v44, v30 + v_sub_u32_e32 v32, v32, v45 + v_lshrrev_b32_e32 v39, 28, v39 + v_sub_u32_e32 v45, v40, v44 + v_sub_u32_e32 v6, v30, v6 + v_lshl_or_b32 v30, v32, 3, v28 + v_add_u32_e32 v32, v44, v39 + v_xor_b32_e32 v39, v6, v27 + v_xor_b32_e32 v6, v6, v28 + v_add_u32_e32 v47, v30, v33 + v_and_b32_e32 v32, -16, v32 + v_lshl_add_u32 v39, v39, 3, v31 + v_lshl_add_u32 v31, v6, 3, v31 + v_sub_u32_e32 v32, v44, v32 + v_xor_b32_e32 v44, v47, v32 + v_lshl_add_u32 v46, v46, 7, v31 + v_xor_b32_e32 v30, v30, v32 + v_sub_u32_e32 v32, v44, v6 + v_sub_u32_e32 v6, v30, v6 + v_lshl_add_u32 v32, v32, 3, v46 + v_lshl_add_u32 v6, v6, 3, v46 + s_waitcnt vmcnt(7) + ds_write_b64 v39, v[48:49] + ds_write_b64 v31, v[50:51] + s_waitcnt vmcnt(6) + ds_write_b64 v32, v[52:53] + ds_write_b64 v6, v[54:55] + v_add_u32_e32 v7, v40, v7 + v_and_b32_e32 v7, -16, v7 + v_sub_u32_e32 v7, v40, v7 + v_xor_b32_e32 v27, v7, v27 + v_sub_u32_e32 v30, v27, v30 + v_lshlrev_b32_e32 v30, 3, v30 + v_lshlrev_b32_e32 v31, 7, v45 + v_add3_u32 v6, v30, v31, v6 + s_waitcnt vmcnt(5) + ds_write_b64 v6, v[56:57] + v_xor_b32_e32 v7, v7, v28 + v_sub_u32_e32 v27, v7, v27 + v_lshl_add_u32 v6, v27, 3, v6 + ds_write_b64 v6, v[58:59] + v_or_b32_e32 v13, 3, v13 + v_add_u32_e32 v27, v13, v34 + v_ashrrev_i32_e32 v30, 1, v27 + v_sub_u32_e32 v31, v30, v40 + v_and_b32_e32 v32, 0x1ffffffe, v27 + v_sub_u32_e32 v13, v13, v32 + v_lshl_or_b32 v13, v13, 3, v28 + v_add_u32_e32 v28, v13, v33 + v_ashrrev_i32_e32 v27, 31, v27 + v_lshrrev_b32_e32 v27, 28, v27 + v_add_u32_e32 v27, v30, v27 + v_and_b32_e32 v27, -16, v27 + v_sub_u32_e32 v27, v30, v27 + v_xor_b32_e32 v28, v28, v27 + v_sub_u32_e32 v7, v28, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v30, 7, v31 + v_add3_u32 v6, v7, v30, v6 + s_waitcnt vmcnt(4) + ds_write_b64 v6, v[60:61] + v_xor_b32_e32 v7, v13, v27 + v_sub_u32_e32 v7, v7, v28 + v_lshl_add_u32 v6, v7, 3, v6 + ds_write_b64 v6, v[62:63] + s_mov_b32 s11, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v2, v2, v2, s11 + v_perm_b32 v3, v3, v3, s11 + v_perm_b32 v4, v4, v4, s11 + v_perm_b32 v5, v5, v5, s11 + s_waitcnt vmcnt(2) + v_perm_b32 v6, v14, v14, s11 + v_perm_b32 v7, v15, v15, s11 + v_perm_b32 v13, v16, v16, s11 + v_perm_b32 v14, v17, v17, s11 + s_waitcnt vmcnt(1) + v_perm_b32 v15, v18, v18, s11 + v_perm_b32 v16, v19, v19, s11 + v_perm_b32 v17, v20, v20, s11 + v_perm_b32 v18, v21, v21, s11 + s_waitcnt vmcnt(0) + v_perm_b32 v19, v22, v22, s11 + v_perm_b32 v20, v23, v23, s11 + v_perm_b32 v21, v24, v24, s11 + v_perm_b32 v22, v25, v25, s11 + s_mov_b32 s11, 0x5010400 + v_perm_b32 v23, v6, v2, s11 + v_perm_b32 v24, v19, v15, s11 + s_mov_b32 s15, 0x5040100 + v_perm_b32 v25, v24, v23, s15 + s_mov_b32 s19, 0x7060302 + v_perm_b32 v23, v24, v23, s19 + s_mov_b32 s23, 0x7030602 + v_perm_b32 v2, v6, v2, s23 + v_perm_b32 v6, v19, v15, s23 + v_perm_b32 v15, v6, v2, s15 + v_perm_b32 v2, v6, v2, s19 + v_perm_b32 v6, v7, v3, s11 + v_perm_b32 v19, v20, v16, s11 + v_perm_b32 v24, v19, v6, s15 + v_perm_b32 v6, v19, v6, s19 + v_perm_b32 v3, v7, v3, s23 + v_perm_b32 v7, v20, v16, s23 + v_perm_b32 v16, v7, v3, s15 + v_perm_b32 v3, v7, v3, s19 + v_perm_b32 v7, v13, v4, s11 + v_perm_b32 v19, v21, v17, s11 + v_perm_b32 v20, v19, v7, s15 + v_perm_b32 v7, v19, v7, s19 + v_perm_b32 v4, v13, v4, s23 + v_perm_b32 v13, v21, v17, s23 + v_perm_b32 v17, v13, v4, s15 + v_perm_b32 v4, v13, v4, s19 + v_perm_b32 v13, v14, v5, s11 + v_perm_b32 v19, v22, v18, s11 + v_perm_b32 v21, v19, v13, s15 + v_perm_b32 v13, v19, v13, s19 + v_perm_b32 v5, v14, v5, s23 + v_perm_b32 v14, v22, v18, s23 + v_perm_b32 v18, v14, v5, s15 + v_perm_b32 v5, v14, v5, s19 + v_lshrrev_b32_e32 v14, 1, v29 + v_and_b32_e32 v14, 16, v14 + v_xor_b32_e32 v19, v14, v35 + v_lshlrev_b32_e32 v22, 9, v29 + v_and_b32_e32 v22, 0x3000, v22 + v_lshlrev_b32_e32 v27, 6, v29 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v27, 0xfffff800, v27 + v_add_u32_e32 v22, v22, v27 + v_lshl_or_b32 v22, v19, 2, v22 + ds_write_b32 v22, v25 offset:16384 + v_or_b32_e32 v25, 1, v14 + v_xor_b32_e32 v25, v25, v35 + v_sub_u32_e32 v19, v25, v19 + v_lshl_add_u32 v19, v19, 2, v22 + v_or_b32_e32 v22, 2, v14 + v_xor_b32_e32 v22, v22, v35 + v_sub_u32_e32 v25, v22, v25 + v_lshl_add_u32 v25, v25, 2, v19 + ds_write_b32 v19, v23 offset:16512 + v_or_b32_e32 v19, 3, v14 + v_xor_b32_e32 v19, v19, v35 + v_sub_u32_e32 v22, v19, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v25, s18, v22 + ds_write_b32 v25, v15 offset:16640 + v_or_b32_e32 v15, 4, v14 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v19, v15, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v19, v22, s18, v19 + ds_write_b32 v22, v2 offset:16640 + v_or_b32_e32 v2, 5, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v15, v2, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v19, s18, v15 + ds_write_b32 v19, v24 offset:16640 + v_or_b32_e32 v19, 6, v14 + v_xor_b32_e32 v19, v19, v35 + v_sub_u32_e32 v2, v19, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v15, s18, v2 + ds_write_b32 v15, v6 offset:16640 + v_or_b32_e32 v6, 7, v14 + v_xor_b32_e32 v6, v6, v35 + v_sub_u32_e32 v15, v6, v19 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v2, s18, v15 + ds_write_b32 v2, v16 offset:16640 + v_or_b32_e32 v2, 8, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v15, s18, v6 + ds_write_b32 v15, v3 offset:16640 + v_or_b32_e32 v3, 9, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v20 offset:16640 + v_or_b32_e32 v6, 10, v14 + v_xor_b32_e32 v6, v6, v35 + v_sub_u32_e32 v3, v6, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v7 offset:16640 + v_or_b32_e32 v2, 11, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v3, s18, v6 + ds_write_b32 v3, v17 offset:16640 + v_or_b32_e32 v3, 12, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v4 offset:16640 + v_or_b32_e32 v4, 13, v14 + v_xor_b32_e32 v4, v4, v35 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v21 offset:16640 + v_or_b32_e32 v2, 14, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v4, v2, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v4, v3, s18, v4 + ds_write_b32 v3, v13 offset:16640 + v_or_b32_e32 v3, 15, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v2, v2, 2, v4 + ds_write_b32 v4, v18 offset:16640 + ds_write_b32 v2, v5 offset:16768 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v2, v41, 3, v42 + v_add_u32_e32 v15, 2, v0 + v_xor_b32_e32 v3, v37, v15 + v_lshl_or_b32 v3, v3, 3, v42 + v_or_b32_e32 v24, 4, v0 + v_xor_b32_e32 v4, v37, v24 + v_lshl_or_b32 v16, v4, 3, v42 + v_add_u32_e32 v13, 6, v0 + v_xor_b32_e32 v20, v37, v13 + v_lshl_add_u32 v14, v20, 3, v42 + v_add_u32_e32 v4, 64, v1 + v_lshrrev_b32_e32 v21, 1, v4 + v_sub_u32_e32 v17, v21, v36 + v_bfe_u32 v22, v4, 1, 4 + v_xor_b32_e32 v4, v22, v0 + v_sub_u32_e32 v18, v4, v20 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[4:5], v3 + ds_read_b64 v[2:3], v16 + ds_read_b32 v74, v43 offset:16384 + v_lshrrev_b16_e32 v16, 3, v26 + v_or_b32_e32 v19, 16, v12 + v_xor_b32_e32 v23, v19, v8 + v_sub_u32_e32 v25, v23, v38 + v_lshlrev_b32_e32 v25, 2, v25 + v_sub_u32_e32 v27, v16, v9 + v_lshlrev_b32_e32 v27, 12, v27 + v_add3_u32 v25, v43, v27, v25 + v_add_u32_e32 v27, 16, v26 + v_lshrrev_b32_e32 v28, 5, v27 + v_lshrrev_b16_e32 v27, 3, v27 + v_and_b32_e32 v27, 3, v27 + v_sub_u16_e32 v29, v27, v16 + v_bfe_i32 v29, v29, 0, 16 + v_lshlrev_b32_e32 v30, 4, v28 + v_or_b32_e32 v31, v30, v8 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v31, v12, v31 + v_sub_u32_e32 v23, v31, v23 + v_lshlrev_b32_e32 v32, 11, v28 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_or_b32 v29, v29, 12, v32 + v_add3_u32 v23, v23, v29, v25 + v_add_u32_e32 v32, 20, v26 + v_lshrrev_b32_e32 v33, 5, v32 + v_sub_u32_e32 v28, v33, v28 + v_lshrrev_b16_e32 v32, 3, v32 + v_and_b32_e32 v32, 3, v32 + v_sub_u16_e32 v27, v32, v27 + v_bfe_i32 v27, v27, 0, 16 + v_lshlrev_b32_e32 v34, 4, v33 + v_or_b32_e32 v36, v34, v8 + v_and_b32_e32 v36, 31, v36 + v_xor_b32_e32 v36, v19, v36 + v_sub_u32_e32 v31, v36, v31 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_add_u32 v27, v27, 12, v28 + v_add3_u32 v28, v31, v27, v23 + v_sub_u16_e32 v31, v16, v32 + v_bfe_i32 v31, v31, 0, 16 + v_or_b32_e32 v32, 16, v8 + v_xor_b32_e32 v37, v12, v32 + v_sub_u32_e32 v36, v37, v36 + v_lshlrev_b32_e32 v33, 11, v33 + v_xor_b32_e32 v33, 0x800, v33 + v_lshlrev_b32_e32 v36, 2, v36 + v_lshl_add_u32 v31, v31, 12, v33 + v_add3_u32 v33, v36, v31, v28 + v_xor_b32_e32 v32, v19, v32 + v_sub_u32_e32 v36, v32, v37 + v_lshl_add_u32 v36, v36, 2, v33 + v_add_u32_e32 v37, 48, v26 + v_lshrrev_b32_e32 v38, 5, v37 + v_lshlrev_b32_e32 v39, 11, v38 + v_lshrrev_b16_e32 v37, 3, v37 + v_and_b32_e32 v37, 3, v37 + v_sub_u16_e32 v40, v37, v16 + v_lshlrev_b32_e32 v41, 4, v38 + v_or_b32_e32 v42, v41, v8 + v_and_b32_e32 v42, 31, v42 + v_xor_b32_e32 v42, v12, v42 + v_sub_u32_e32 v32, v42, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_mov_b32_e32 v43, 12 + v_lshlrev_b32_sdwa v40, v43, sext(v40) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v39, v39, v40, s11 + v_add3_u32 v32, v32, v39, v36 + v_add_u32_e32 v26, 52, v26 + v_lshrrev_b32_e32 v40, 5, v26 + v_sub_u32_e32 v38, v40, v38 + v_lshrrev_b16_e32 v26, 3, v26 + v_and_b32_e32 v26, 3, v26 + v_sub_u16_e32 v37, v26, v37 + v_bfe_i32 v37, v37, 0, 16 + v_lshlrev_b32_e32 v44, 4, v40 + v_or_b32_e32 v45, v44, v8 + v_and_b32_e32 v46, 31, v45 + v_xor_b32_e32 v19, v19, v46 + v_sub_u32_e32 v42, v19, v42 + v_lshlrev_b32_e32 v38, 11, v38 + v_lshlrev_b32_e32 v42, 2, v42 + v_lshl_add_u32 v37, v37, 12, v38 + v_add3_u32 v38, v42, v37, v32 + ds_read_b32 v75, v25 offset:16384 + ds_read_b32 v76, v23 offset:16384 + ds_read_b32 v77, v28 offset:16384 + ds_read_b32 v78, v33 offset:16384 + ds_read_b32 v79, v36 offset:16384 + ds_read_b32 v80, v32 offset:16384 + ds_read_b32 v81, v38 offset:16384 + v_or_b32_e32 v23, 4, v12 + v_sub_u16_e32 v16, v16, v26 + v_sub_u32_e32 v25, v45, v44 + v_ashrrev_i32_e32 v26, 31, v25 + v_lshrrev_b32_e32 v26, 27, v26 + v_add_u32_e32 v26, v25, v26 + v_and_b32_e32 v26, 0xffffffe0, v26 + v_sub_u32_e32 v26, v25, v26 + v_xor_b32_e32 v28, v23, v26 + v_sub_u32_e32 v19, v28, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshlrev_b32_sdwa v16, v43, sext(v16) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v32, 11, v40 + v_sub_u32_e32 v16, v16, v32 + v_add3_u32 v19, v19, v16, v38 + v_or_b32_e32 v32, 20, v12 + v_xor_b32_e32 v33, v32, v26 + v_sub_u32_e32 v28, v33, v28 + v_lshl_add_u32 v28, v28, 2, v19 + ds_read_b32 v82, v19 offset:16384 + ds_read_b32 v83, v28 offset:16384 + v_add_u32_e32 v19, v25, v30 + v_ashrrev_i32_e32 v30, 31, v19 + v_lshrrev_b32_e32 v30, 27, v30 + v_add_u32_e32 v30, v19, v30 + v_and_b32_e32 v30, 0xffffffe0, v30 + v_sub_u32_e32 v30, v19, v30 + v_xor_b32_e32 v19, v23, v30 + v_sub_u32_e32 v33, v19, v33 + v_lshl_add_u32 v33, v33, 2, v29 + v_add_u32_e32 v28, v33, v28 + v_add_u32_e32 v33, v25, v34 + v_ashrrev_i32_e32 v34, 31, v33 + v_lshrrev_b32_e32 v34, 27, v34 + v_add_u32_e32 v34, v33, v34 + v_and_b32_e32 v34, 0xffffffe0, v34 + v_sub_u32_e32 v33, v33, v34 + v_xor_b32_e32 v34, v32, v33 + v_sub_u32_e32 v19, v34, v19 + v_lshl_add_u32 v36, v19, 2, v27 + v_add_u32_e32 v38, v28, v36 + v_add_u32_e32 v19, 16, v25 + v_ashrrev_i32_e32 v40, 31, v19 + v_lshrrev_b32_e32 v40, 27, v40 + v_add_u32_e32 v40, v19, v40 + v_and_b32_e32 v40, 0xffffffe0, v40 + v_sub_u32_e32 v40, v19, v40 + v_xor_b32_e32 v19, v23, v40 + v_sub_u32_e32 v34, v19, v34 + v_lshl_add_u32 v34, v34, 2, v31 + v_add_u32_e32 v42, v38, v34 + v_xor_b32_e32 v43, v32, v40 + v_sub_u32_e32 v19, v43, v19 + v_lshlrev_b32_e32 v44, 2, v19 + v_add_u32_e32 v45, v42, v44 + v_add_u32_e32 v19, v25, v41 + v_ashrrev_i32_e32 v25, 31, v19 + v_lshrrev_b32_e32 v25, 27, v25 + v_add_u32_e32 v25, v19, v25 + v_and_b32_e32 v25, 0xffffffe0, v25 + v_sub_u32_e32 v41, v19, v25 + v_xor_b32_e32 v19, v23, v41 + v_sub_u32_e32 v23, v19, v43 + v_lshl_add_u32 v43, v23, 2, v39 + v_add_u32_e32 v47, v45, v43 + v_xor_b32_e32 v23, v32, v46 + v_sub_u32_e32 v19, v23, v19 + v_lshl_add_u32 v32, v19, 2, v37 + v_add_u32_e32 v48, v47, v32 + v_or_b32_e32 v19, 8, v12 + v_xor_b32_e32 v25, v19, v26 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v49, v23, 2, v16 + v_add_u32_e32 v23, v48, v49 + ds_read_b32 v84, v23 offset:16384 + v_or_b32_e32 v50, 24, v12 + v_xor_b32_e32 v51, v50, v26 + v_sub_u32_e32 v25, v51, v25 + v_lshlrev_b32_e32 v52, 2, v25 + v_add_u32_e32 v23, v23, v52 + ds_read_b32 v85, v23 offset:16384 + v_xor_b32_e32 v25, v19, v30 + v_sub_u32_e32 v51, v25, v51 + v_lshl_add_u32 v51, v51, 2, v29 + v_add_u32_e32 v53, v23, v51 + v_xor_b32_e32 v23, v50, v33 + v_sub_u32_e32 v25, v23, v25 + v_lshl_add_u32 v54, v25, 2, v27 + v_add_u32_e32 v55, v53, v54 + v_xor_b32_e32 v25, v19, v40 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v56, v23, 2, v31 + v_add_u32_e32 v57, v55, v56 + v_xor_b32_e32 v23, v50, v40 + v_sub_u32_e32 v25, v23, v25 + v_lshlrev_b32_e32 v58, 2, v25 + v_add_u32_e32 v59, v57, v58 + v_xor_b32_e32 v19, v19, v41 + v_sub_u32_e32 v23, v19, v23 + v_lshl_add_u32 v60, v23, 2, v39 + s_waitcnt lgkmcnt(10) + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[6:7], v[74:75], 0 + v_add_u32_e32 v61, v59, v60 + v_xor_b32_e32 v23, v50, v46 + v_sub_u32_e32 v19, v23, v19 + v_lshl_add_u32 v50, v19, 2, v37 + v_add_u32_e32 v62, v61, v50 + v_or_b32_e32 v63, 12, v12 + v_xor_b32_e32 v19, v63, v26 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[6:7], v[82:83], 0 + v_sub_u32_e32 v23, v19, v23 + v_lshl_add_u32 v64, v23, 2, v16 + v_add_u32_e32 v16, v62, v64 + ds_read_b32 v86, v16 offset:16384 + v_or_b32_e32 v12, 28, v12 + v_xor_b32_e32 v26, v12, v26 + v_sub_u32_e32 v19, v26, v19 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[6:7], v[84:85], 0 + v_lshlrev_b32_e32 v65, 2, v19 + v_add_u32_e32 v66, v16, v65 + ds_read_b32 v87, v66 offset:16384 + v_lshl_add_u32 v23, v17, 7, v14 + v_lshl_add_u32 v16, v18, 3, v23 + ds_read_b64 v[16:17], v16 + v_xor_b32_e32 v18, v22, v15 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[6:7], v[86:87], 0 + v_sub_u32_e32 v6, v18, v20 + v_lshl_add_u32 v6, v6, 3, v23 + v_xor_b32_e32 v7, v22, v24 + v_sub_u32_e32 v7, v7, v20 + v_lshl_add_u32 v18, v7, 3, v23 + ds_read_b64 v[6:7], v6 + ds_read_b64 v[18:19], v18 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[16:17], v[74:75], 0 + v_xor_b32_e32 v22, v22, v13 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[16:17], v[82:83], 0 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add_u32_e32 v67, v20, v23 + v_add_u32_e32 v20, 0x80, v1 + v_lshrrev_b32_e32 v25, 1, v20 + v_sub_u32_e32 v21, v25, v21 + v_bfe_u32 v68, v20, 1, 4 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[16:17], v[84:85], 0 + v_xor_b32_e32 v69, v68, v0 + v_sub_u32_e32 v20, v69, v22 + v_lshlrev_b32_e32 v21, 7, v21 + v_lshl_add_u32 v70, v20, 3, v21 + v_add_u32_e32 v71, v67, v70 + ds_read_b64 v[20:21], v71 + v_xor_b32_e32 v22, v68, v15 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[16:17], v[86:87], 0 + v_sub_u32_e32 v16, v22, v69 + v_lshl_add_u32 v16, v16, 3, v71 + v_xor_b32_e32 v17, v68, v24 + v_sub_u32_e32 v17, v17, v69 + v_lshl_add_u32 v22, v17, 3, v71 + ds_read_b64 v[16:17], v16 + ds_read_b64 v[22:23], v22 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[20:21], v[74:75], 0 + v_xor_b32_e32 v68, v68, v13 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[20:21], v[82:83], 0 + v_sub_u32_e32 v69, v68, v69 + v_lshlrev_b32_e32 v69, 3, v69 + v_add3_u32 v70, v70, v67, v69 + v_add_u32_e32 v1, 0xc0, v1 + v_lshrrev_b32_e32 v72, 1, v1 + v_sub_u32_e32 v25, v72, v25 + v_bfe_u32 v72, v1, 1, 4 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[20:21], v[84:85], 0 + v_xor_b32_e32 v73, v72, v0 + v_sub_u32_e32 v0, v73, v68 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v1, 7, v25 + v_add3_u32 v68, v0, v1, v70 + ds_read_b64 v[0:1], v68 + v_xor_b32_e32 v15, v72, v15 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[20:21], v[86:87], 0 + v_sub_u32_e32 v15, v15, v73 + v_lshl_add_u32 v15, v15, 3, v68 + v_xor_b32_e32 v20, v72, v24 + v_sub_u32_e32 v20, v20, v73 + v_lshl_add_u32 v24, v20, 3, v68 + ds_read_b64 v[20:21], v15 + ds_read_b64 v[24:25], v24 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[74:75], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[82:83], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[84:85], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[86:87], 0 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[4:5], v[76:77], a[0:15] + ds_read_b32 v74, v28 offset:16384 + ds_read_b32 v75, v38 offset:16384 + ds_read_b32 v82, v53 offset:16384 + ds_read_b32 v83, v55 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[4:5], v[74:75], a[240:255] + v_xor_b32_e32 v0, v63, v30 + v_sub_u32_e32 v1, v0, v26 + v_lshl_add_u32 v15, v1, 2, v29 + v_add_u32_e32 v1, v66, v15 + ds_read_b32 v84, v1 offset:16384 + v_xor_b32_e32 v26, v12, v33 + v_sub_u32_e32 v0, v26, v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[4:5], v[82:83], a[224:239] + v_lshl_add_u32 v27, v0, 2, v27 + v_add_u32_e32 v0, v1, v27 + ds_read_b32 v85, v0 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[4:5], v[84:85], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[6:7], v[76:77], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[6:7], v[74:75], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[6:7], v[82:83], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[6:7], v[84:85], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[16:17], v[76:77], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[16:17], v[74:75], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[16:17], v[82:83], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[16:17], v[84:85], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[20:21], v[76:77], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[20:21], v[74:75], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[20:21], v[82:83], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[20:21], v[84:85], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[2:3], v[78:79], a[0:15] + ds_read_b32 v16, v42 offset:16384 + ds_read_b32 v17, v45 offset:16384 + ds_read_b32 v20, v57 offset:16384 + ds_read_b32 v21, v59 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[2:3], v[16:17], a[240:255] + v_xor_b32_e32 v1, v63, v40 + v_sub_u32_e32 v4, v1, v26 + v_lshl_add_u32 v4, v4, 2, v31 + v_add_u32_e32 v0, v0, v4 + ds_read_b32 v30, v0 offset:16384 + v_xor_b32_e32 v5, v12, v40 + v_sub_u32_e32 v1, v5, v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[2:3], v[20:21], a[224:239] + v_lshlrev_b32_e32 v6, 2, v1 + v_add_u32_e32 v7, v0, v6 + ds_read_b32 v31, v7 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[2:3], v[30:31], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[18:19], v[78:79], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[18:19], v[16:17], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[18:19], v[20:21], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[18:19], v[30:31], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[22:23], v[78:79], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[22:23], v[16:17], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[22:23], v[20:21], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[22:23], v[30:31], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[24:25], v[78:79], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[24:25], v[16:17], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[24:25], v[20:21], a[16:31] + ds_read_b64 v[0:1], v14 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[24:25], v[30:31], a[192:207] + v_add3_u32 v2, v36, v28, v34 + v_add3_u32 v2, v44, v2, v43 + ds_read_b32 v16, v47 offset:16384 + ds_read_b32 v17, v48 offset:16384 + v_add3_u32 v2, v32, v2, v49 + v_add3_u32 v2, v2, v52, v51 + v_add3_u32 v2, v54, v2, v56 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[0:1], v[80:81], a[0:15] + v_add3_u32 v2, v58, v2, v60 + ds_read_b32 v18, v61 offset:16384 + ds_read_b32 v19, v62 offset:16384 + v_add3_u32 v2, v50, v2, v64 + v_add3_u32 v2, v2, v65, v15 + v_add3_u32 v2, v27, v2, v4 + v_xor_b32_e32 v3, v63, v41 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[0:1], v[16:17], a[240:255] + v_sub_u32_e32 v4, v3, v5 + v_lshl_add_u32 v4, v4, 2, v39 + v_add3_u32 v2, v6, v2, v4 + v_add_u32_e32 v4, v7, v4 + ds_read_b32 v6, v4 offset:16384 + v_xor_b32_e32 v4, v12, v46 + v_sub_u32_e32 v3, v4, v3 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[0:1], v[18:19], a[224:239] + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v2, v3, v37, v2 + ds_read_b32 v7, v2 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[0:1], v67 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[0:1], v[80:81], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[0:1], v[16:17], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[0:1], v[18:19], a[144:159] + v_add_u32_e32 v2, v71, v69 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[0:1], v[6:7], a[128:143] + ds_read_b64 v[0:1], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[0:1], v[80:81], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[0:1], v[16:17], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[0:1], v[18:19], a[80:95] + v_xor_b32_e32 v2, v72, v13 + v_sub_u32_e32 v2, v2, v73 + v_lshl_add_u32 v2, v2, 3, v68 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b64 v[0:1], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[0:1], v[80:81], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[0:1], v[16:17], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[0:1], v[18:19], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[0:1], v[6:7], a[192:207] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB23_3 + s_branch .LBB23_10 +.LBB23_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr255 + ; implicit-def: $agpr15 + ; implicit-def: $agpr192_agpr193_agpr194_agpr195_agpr196_agpr197_agpr198_agpr199_agpr200_agpr201_agpr202_agpr203_agpr204_agpr205_agpr206_agpr207 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB23_3: + v_readfirstlane_b32 s15, v227 + v_and_b32_e32 v0, 48, v11 + s_and_b32 s11, s15, 0xffffffc0 + v_and_b32_e32 v83, 0x7c, v225 + v_add_u32_e32 v1, s11, v83 + v_add_u32_e32 v2, s20, v1 + v_mad_u64_u32 v[20:21], s[18:19], v2, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[44:47], v20, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v20 + buffer_load_dwordx4 v[52:55], v2, s[8:11], 0 offen + v_and_or_b32 v3, v228, 8, v9 + v_lshlrev_b32_e32 v11, 3, v9 + v_add_u32_e32 v6, s7, v2 + buffer_load_dwordx4 v[56:59], v6, s[8:11], 0 offen + v_and_b32_e32 v84, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v2, 12, v9 + s_lshr_b32 s18, s15, 2 + s_lshr_b32 s19, s15, 1 + v_lshl_or_b32 v16, v8, 7, v2 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v85, 3, v0 + s_and_b32 s23, s18, 0x3fffffe0 + s_and_b32 s18, s18, 0x3ffffff0 + v_and_or_b32 v0, s19, 32, v35 + v_or_b32_e32 v86, 1, v85 + v_or_b32_e32 v5, s23, v35 + v_add_u32_e32 v17, s18, v84 + v_lshrrev_b32_e32 v2, 4, v0 + v_ashrrev_i32_e32 v21, 1, v1 + v_ashrrev_i32_e32 v0, 31, v1 + v_lshlrev_b32_e32 v34, 6, v1 + v_or_b32_e32 v36, 1, v1 + v_sub_u32_e32 v87, v85, v86 + v_lshrrev_b32_e32 v37, 31, v1 + v_add_u32_e32 v6, s7, v6 + buffer_load_dwordx4 v[60:63], v6, s[8:11], 0 offen + v_lshrrev_b32_e32 v6, 1, v5 + v_bfe_u32 v7, v5, 1, 4 + v_mad_u64_u32 v[18:19], s[18:19], v17, s22, v[4:5] + v_xor_b32_e32 v4, v2, v8 + buffer_load_dwordx4 v[12:15], v18, s[12:15], 0 offen + v_lshrrev_b32_e32 v19, 28, v0 + v_add_u32_e32 v38, v36, v37 + v_add_u32_e32 v10, s22, v18 + buffer_load_dwordx4 v[22:25], v10, s[12:15], 0 offen + v_or_b32_e32 v39, 1, v21 + v_xor_b32_e32 v0, v7, v3 + v_add_u32_e32 v30, s22, v10 + buffer_load_dwordx4 v[26:29], v30, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 7, v6 + v_lshl_or_b32 v50, v4, 2, v16 + v_add_u32_e32 v16, s22, v30 + buffer_load_dwordx4 v[30:33], v16, s[12:15], 0 offen + v_add_u32_e32 v16, v21, v19 + v_ashrrev_i32_e32 v40, 1, v38 + v_and_b32_e32 v41, 0x1ffffffe, v38 + v_ashrrev_i32_e32 v38, 31, v38 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v42, v40, v21 + v_sub_u32_e32 v36, v36, v41 + v_lshrrev_b32_e32 v38, 28, v38 + v_sub_u32_e32 v41, v39, v40 + v_sub_u32_e32 v16, v21, v16 + v_lshl_or_b32 v21, v36, 3, v86 + v_add_u32_e32 v36, v40, v38 + v_xor_b32_e32 v38, v16, v85 + v_xor_b32_e32 v16, v16, v86 + v_add_u32_e32 v43, v21, v87 + v_and_b32_e32 v36, -16, v36 + v_lshl_add_u32 v38, v38, 3, v34 + v_lshl_add_u32 v34, v16, 3, v34 + v_sub_u32_e32 v36, v40, v36 + v_xor_b32_e32 v40, v43, v36 + v_lshl_add_u32 v42, v42, 7, v34 + v_xor_b32_e32 v21, v21, v36 + v_sub_u32_e32 v36, v40, v16 + v_sub_u32_e32 v16, v21, v16 + v_lshl_add_u32 v36, v36, 3, v42 + v_lshl_add_u32 v16, v16, 3, v42 + s_waitcnt vmcnt(7) + ds_write_b64 v38, v[44:45] + ds_write_b64 v34, v[46:47] + s_waitcnt vmcnt(6) + ds_write_b64 v36, v[52:53] + ds_write_b64 v16, v[54:55] + v_add_u32_e32 v19, v39, v19 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v19, v39, v19 + v_xor_b32_e32 v34, v19, v85 + v_sub_u32_e32 v21, v34, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_lshlrev_b32_e32 v36, 7, v41 + v_add3_u32 v16, v21, v36, v16 + s_waitcnt vmcnt(5) + ds_write_b64 v16, v[56:57] + v_xor_b32_e32 v19, v19, v86 + v_sub_u32_e32 v21, v19, v34 + v_lshl_add_u32 v16, v21, 3, v16 + ds_write_b64 v16, v[58:59] + v_or_b32_e32 v1, 3, v1 + v_add_u32_e32 v21, v1, v37 + v_ashrrev_i32_e32 v34, 1, v21 + v_sub_u32_e32 v36, v34, v39 + v_and_b32_e32 v37, 0x1ffffffe, v21 + v_sub_u32_e32 v1, v1, v37 + v_lshl_or_b32 v1, v1, 3, v86 + v_add_u32_e32 v37, v1, v87 + v_ashrrev_i32_e32 v21, 31, v21 + v_lshrrev_b32_e32 v21, 28, v21 + v_add_u32_e32 v21, v34, v21 + v_and_b32_e32 v21, -16, v21 + v_sub_u32_e32 v21, v34, v21 + v_xor_b32_e32 v34, v37, v21 + v_sub_u32_e32 v19, v34, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshlrev_b32_e32 v36, 7, v36 + v_add3_u32 v16, v19, v36, v16 + s_waitcnt vmcnt(4) + ds_write_b64 v16, v[60:61] + v_xor_b32_e32 v1, v1, v21 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v1, v1, 3, v16 + ds_write_b64 v1, v[62:63] + s_mov_b32 s18, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v1, v12, v12, s18 + v_perm_b32 v12, v13, v13, s18 + v_perm_b32 v13, v14, v14, s18 + v_perm_b32 v14, v15, v15, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v15, v22, v22, s18 + v_perm_b32 v16, v23, v23, s18 + v_perm_b32 v19, v24, v24, s18 + v_perm_b32 v21, v25, v25, s18 + s_waitcnt vmcnt(1) + v_perm_b32 v22, v26, v26, s18 + v_perm_b32 v23, v27, v27, s18 + v_perm_b32 v24, v28, v28, s18 + v_perm_b32 v25, v29, v29, s18 + s_waitcnt vmcnt(0) + v_perm_b32 v26, v30, v30, s18 + v_perm_b32 v27, v31, v31, s18 + v_perm_b32 v28, v32, v32, s18 + v_perm_b32 v29, v33, v33, s18 + s_mov_b32 s18, 0x5010400 + v_perm_b32 v30, v15, v1, s18 + v_perm_b32 v31, v26, v22, s18 + s_mov_b32 s19, 0x5040100 + v_perm_b32 v32, v31, v30, s19 + s_mov_b32 s23, 0x7060302 + v_perm_b32 v30, v31, v30, s23 + s_mov_b32 s24, 0x7030602 + v_perm_b32 v1, v15, v1, s24 + v_perm_b32 v15, v26, v22, s24 + v_perm_b32 v22, v15, v1, s19 + v_perm_b32 v1, v15, v1, s23 + v_perm_b32 v15, v16, v12, s18 + v_perm_b32 v26, v27, v23, s18 + v_perm_b32 v31, v26, v15, s19 + v_perm_b32 v15, v26, v15, s23 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v27, v23, s24 + v_perm_b32 v23, v16, v12, s19 + v_perm_b32 v12, v16, v12, s23 + v_perm_b32 v16, v19, v13, s18 + v_perm_b32 v26, v28, v24, s18 + v_perm_b32 v27, v26, v16, s19 + v_perm_b32 v16, v26, v16, s23 + v_perm_b32 v13, v19, v13, s24 + v_perm_b32 v19, v28, v24, s24 + v_perm_b32 v24, v19, v13, s19 + v_perm_b32 v13, v19, v13, s23 + v_perm_b32 v19, v21, v14, s18 + v_perm_b32 v26, v29, v25, s18 + v_perm_b32 v28, v26, v19, s19 + v_perm_b32 v19, v26, v19, s23 + v_perm_b32 v14, v21, v14, s24 + v_perm_b32 v21, v29, v25, s24 + v_perm_b32 v25, v21, v14, s19 + v_perm_b32 v14, v21, v14, s23 + v_lshrrev_b32_e32 v21, 1, v17 + v_and_b32_e32 v21, 16, v21 + v_xor_b32_e32 v26, v21, v35 + v_lshlrev_b32_e32 v29, 9, v17 + v_and_b32_e32 v29, 0x3000, v29 + v_lshlrev_b32_e32 v17, 6, v17 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v17, 0xfffff800, v17 + v_add_u32_e32 v17, v29, v17 + v_lshl_or_b32 v17, v26, 2, v17 + ds_write_b32 v17, v32 offset:16384 + v_or_b32_e32 v29, 1, v21 + v_xor_b32_e32 v29, v29, v35 + v_sub_u32_e32 v26, v29, v26 + v_lshl_add_u32 v17, v26, 2, v17 + v_or_b32_e32 v26, 2, v21 + v_xor_b32_e32 v26, v26, v35 + v_sub_u32_e32 v29, v26, v29 + v_lshl_add_u32 v29, v29, 2, v17 + ds_write_b32 v17, v30 offset:16512 + v_or_b32_e32 v17, 3, v21 + v_xor_b32_e32 v17, v17, v35 + v_sub_u32_e32 v26, v17, v26 + v_lshlrev_b32_e32 v26, 2, v26 + s_movk_i32 s19, 0x80 + v_add3_u32 v26, v29, s19, v26 + ds_write_b32 v29, v22 offset:16640 + v_or_b32_e32 v22, 4, v21 + v_xor_b32_e32 v22, v22, v35 + v_sub_u32_e32 v17, v22, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v26, s19, v17 + ds_write_b32 v26, v1 offset:16640 + v_or_b32_e32 v1, 5, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v22, v1, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v17, s19, v22 + ds_write_b32 v17, v31 offset:16640 + v_or_b32_e32 v17, 6, v21 + v_xor_b32_e32 v17, v17, v35 + v_sub_u32_e32 v1, v17, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v22, s19, v1 + ds_write_b32 v22, v15 offset:16640 + v_or_b32_e32 v15, 7, v21 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v17, v15, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v1, s19, v17 + ds_write_b32 v1, v23 offset:16640 + v_or_b32_e32 v1, 8, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v15, v1, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v17, s19, v15 + ds_write_b32 v17, v12 offset:16640 + v_or_b32_e32 v12, 9, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v15, s19, v1 + ds_write_b32 v15, v27 offset:16640 + v_or_b32_e32 v15, 10, v21 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v12, v15, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v1, s19, v12 + ds_write_b32 v1, v16 offset:16640 + v_or_b32_e32 v1, 11, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v15, v1, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v12, s19, v15 + ds_write_b32 v12, v24 offset:16640 + v_or_b32_e32 v12, 12, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v15, s19, v1 + ds_write_b32 v15, v13 offset:16640 + v_or_b32_e32 v13, 13, v21 + v_xor_b32_e32 v13, v13, v35 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v1, s19, v12 + ds_write_b32 v1, v28 offset:16640 + v_or_b32_e32 v1, 14, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v13, v1, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v12, s19, v13 + ds_write_b32 v12, v19 offset:16640 + v_or_b32_e32 v12, 15, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshl_add_u32 v1, v1, 2, v13 + ds_write_b32 v13, v25 offset:16640 + ds_write_b32 v1, v14 offset:16768 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v30, 2, v3 + v_add_u32_e32 v29, 4, v3 + v_add_u32_e32 v28, 6, v3 + v_add_u32_e32 v31, 64, v5 + v_lshrrev_b16_e32 v21, 3, v11 + v_or_b32_e32 v22, 16, v2 + v_add_u32_e32 v27, 16, v11 + v_add_u32_e32 v26, 20, v11 + v_or_b32_e32 v12, 16, v8 + v_add_u32_e32 v25, 36, v11 + v_add_u32_e32 v24, 48, v11 + v_add_u32_e32 v23, 52, v11 + v_or_b32_e32 v17, 4, v2 + v_or_b32_e32 v16, 20, v2 + v_or_b32_e32 v15, 8, v2 + v_or_b32_e32 v14, 24, v2 + v_or_b32_e32 v13, 12, v2 + v_or_b32_e32 v11, 28, v2 + s_cbranch_vccnz .LBB23_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit967.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v7, v30 + v_lshl_add_u32 v49, v1, 3, v10 + v_xor_b32_e32 v1, v7, v29 + v_lshl_add_u32 v47, v1, 3, v10 + v_xor_b32_e32 v1, v7, v28 + v_lshl_add_u32 v19, v1, 3, v10 + v_lshrrev_b32_e32 v32, 1, v31 + v_sub_u32_e32 v33, v32, v6 + v_bfe_u32 v34, v31, 1, 4 + v_xor_b32_e32 v36, v34, v3 + v_sub_u32_e32 v36, v36, v1 + v_lshl_add_u32 v33, v33, 7, v19 + v_lshl_add_u32 v36, v36, 3, v33 + v_xor_b32_e32 v37, v34, v30 + v_sub_u32_e32 v37, v37, v1 + v_lshl_add_u32 v37, v37, 3, v33 + v_xor_b32_e32 v38, v34, v29 + v_sub_u32_e32 v38, v38, v1 + v_lshl_add_u32 v39, v38, 3, v33 + v_xor_b32_e32 v34, v34, v28 + v_sub_u32_e32 v1, v34, v1 + v_lshl_add_u32 v38, v1, 3, v33 + v_add_u32_e32 v1, 0x80, v5 + v_lshrrev_b32_e32 v33, 1, v1 + v_sub_u32_e32 v32, v33, v32 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v42, v1, v3 + v_sub_u32_e32 v34, v42, v34 + v_lshlrev_b32_e32 v34, 3, v34 + v_lshlrev_b32_e32 v32, 7, v32 + v_add3_u32 v40, v34, v32, v38 + v_xor_b32_e32 v32, v1, v30 + v_sub_u32_e32 v32, v32, v42 + v_lshl_add_u32 v41, v32, 3, v40 + v_xor_b32_e32 v32, v1, v29 + v_sub_u32_e32 v32, v32, v42 + v_lshl_add_u32 v43, v32, 3, v40 + v_xor_b32_e32 v1, v1, v28 + v_sub_u32_e32 v32, v1, v42 + v_lshl_add_u32 v42, v32, 3, v40 + v_add_u32_e32 v32, 0xc0, v5 + v_lshrrev_b32_e32 v34, 1, v32 + v_sub_u32_e32 v33, v34, v33 + v_bfe_u32 v32, v32, 1, 4 + v_xor_b32_e32 v34, v32, v3 + v_sub_u32_e32 v1, v34, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v33, 7, v33 + v_add3_u32 v44, v1, v33, v42 + v_xor_b32_e32 v1, v32, v30 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v45, v1, 3, v44 + v_xor_b32_e32 v1, v32, v29 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v46, v1, 3, v44 + v_xor_b32_e32 v1, v32, v28 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v48, v1, 3, v44 + v_xor_b32_e32 v1, v22, v8 + v_sub_u32_e32 v32, v1, v4 + v_lshlrev_b32_e32 v32, 2, v32 + v_sub_u32_e32 v33, v21, v9 + v_lshlrev_b32_e32 v33, 12, v33 + v_add3_u32 v51, v50, v33, v32 + v_lshrrev_b32_e32 v32, 5, v27 + v_lshrrev_b16_e32 v33, 3, v27 + v_and_b32_e32 v33, 3, v33 + v_sub_u16_e32 v34, v33, v21 + v_bfe_i32 v34, v34, 0, 16 + v_lshl_or_b32 v76, v32, 4, v8 + v_xor_b32_e32 v53, v2, v76 + v_sub_u32_e32 v1, v53, v1 + v_lshlrev_b32_e32 v52, 11, v32 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_or_b32 v34, v34, 12, v52 + v_add3_u32 v52, v1, v34, v51 + v_lshrrev_b32_e32 v1, 5, v26 + v_sub_u32_e32 v32, v1, v32 + v_lshrrev_b16_e32 v54, 3, v26 + v_and_b32_e32 v54, 3, v54 + v_sub_u16_e32 v33, v54, v33 + v_bfe_i32 v33, v33, 0, 16 + v_lshl_or_b32 v77, v1, 4, v8 + v_xor_b32_e32 v55, v22, v77 + v_sub_u32_e32 v53, v55, v53 + v_lshlrev_b32_e32 v32, 11, v32 + v_lshlrev_b32_e32 v53, 2, v53 + v_lshl_add_u32 v32, v33, 12, v32 + v_add3_u32 v53, v53, v32, v52 + v_sub_u16_e32 v33, v21, v54 + v_bfe_i32 v33, v33, 0, 16 + v_xor_b32_e32 v56, v2, v12 + v_sub_u32_e32 v54, v56, v55 + v_lshlrev_b32_e32 v1, 11, v1 + v_xor_b32_e32 v1, 0x800, v1 + v_lshlrev_b32_e32 v54, 2, v54 + v_lshl_or_b32 v1, v33, 12, v1 + v_add3_u32 v54, v54, v1, v53 + v_lshrrev_b32_e32 v33, 5, v25 + v_lshlrev_b32_e32 v55, 11, v33 + v_lshrrev_b16_e32 v57, 3, v25 + v_and_b32_e32 v57, 3, v57 + v_sub_u16_e32 v58, v57, v21 + v_lshl_or_b32 v59, v33, 4, v8 + v_and_b32_e32 v79, 31, v59 + v_xor_b32_e32 v60, v22, v79 + v_sub_u32_e32 v56, v60, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_mov_b32_e32 v62, 12 + v_lshlrev_b32_sdwa v58, v62, sext(v58) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v80, v55, v58, s18 + v_add3_u32 v59, v56, v80, v54 + v_lshrrev_b32_e32 v56, 5, v24 + v_sub_u32_e32 v33, v56, v33 + v_lshrrev_b16_e32 v55, 3, v24 + v_and_b32_e32 v58, 3, v55 + v_sub_u16_e32 v55, v58, v57 + v_bfe_i32 v55, v55, 0, 16 + v_lshl_or_b32 v57, v56, 4, v8 + v_and_b32_e32 v81, 31, v57 + v_xor_b32_e32 v57, v2, v81 + v_sub_u32_e32 v60, v57, v60 + v_lshlrev_b32_e32 v33, 11, v33 + v_lshlrev_b32_e32 v60, 2, v60 + v_lshl_add_u32 v33, v55, 12, v33 + v_add3_u32 v55, v60, v33, v59 + v_lshrrev_b32_e32 v60, 5, v23 + v_sub_u32_e32 v56, v60, v56 + v_lshrrev_b16_e32 v61, 3, v23 + v_and_b32_e32 v63, 3, v61 + v_sub_u16_e32 v58, v63, v58 + v_bfe_i32 v58, v58, 0, 16 + v_lshl_or_b32 v61, v60, 4, v8 + v_and_b32_e32 v82, 31, v61 + v_xor_b32_e32 v64, v22, v82 + v_sub_u32_e32 v57, v64, v57 + v_lshlrev_b32_e32 v56, 11, v56 + v_lshlrev_b32_e32 v57, 2, v57 + v_lshl_add_u32 v88, v58, 12, v56 + v_add3_u32 v61, v57, v88, v55 + v_sub_u16_e32 v56, v21, v63 + v_xor_b32_e32 v57, v17, v8 + v_sub_u32_e32 v58, v57, v64 + v_lshlrev_b32_e32 v58, 2, v58 + v_lshlrev_b32_sdwa v56, v62, sext(v56) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v60, 11, v60 + v_sub_u32_e32 v74, v56, v60 + v_add3_u32 v56, v58, v74, v61 + v_xor_b32_e32 v58, v16, v8 + v_sub_u32_e32 v57, v58, v57 + v_lshl_add_u32 v57, v57, 2, v56 + v_xor_b32_e32 v60, v17, v76 + v_sub_u32_e32 v58, v60, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v58, v58, v34, v57 + v_xor_b32_e32 v62, v16, v77 + v_sub_u32_e32 v60, v62, v60 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v60, v60, v32, v58 + v_xor_b32_e32 v63, v17, v12 + v_sub_u32_e32 v62, v63, v62 + v_lshlrev_b32_e32 v62, 2, v62 + v_add3_u32 v62, v62, v1, v60 + v_xor_b32_e32 v64, v16, v79 + v_sub_u32_e32 v63, v64, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v63, v63, v80, v62 + v_xor_b32_e32 v65, v17, v81 + v_sub_u32_e32 v64, v65, v64 + v_lshlrev_b32_e32 v64, 2, v64 + v_add3_u32 v64, v64, v33, v63 + v_xor_b32_e32 v66, v16, v82 + v_sub_u32_e32 v65, v66, v65 + v_lshlrev_b32_e32 v65, 2, v65 + v_add3_u32 v65, v65, v88, v64 + v_xor_b32_e32 v67, v15, v8 + v_sub_u32_e32 v66, v67, v66 + v_lshlrev_b32_e32 v66, 2, v66 + v_add3_u32 v66, v66, v74, v65 + v_xor_b32_e32 v68, v14, v8 + v_sub_u32_e32 v67, v68, v67 + v_lshl_add_u32 v67, v67, 2, v66 + v_xor_b32_e32 v69, v15, v76 + v_sub_u32_e32 v68, v69, v68 + v_lshlrev_b32_e32 v68, 2, v68 + v_add3_u32 v68, v68, v34, v67 + v_xor_b32_e32 v70, v14, v77 + v_sub_u32_e32 v69, v70, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v69, v69, v32, v68 + v_xor_b32_e32 v71, v15, v12 + v_sub_u32_e32 v70, v71, v70 + v_lshlrev_b32_e32 v70, 2, v70 + v_add3_u32 v70, v70, v1, v69 + v_xor_b32_e32 v72, v14, v79 + v_sub_u32_e32 v71, v72, v71 + v_lshlrev_b32_e32 v71, 2, v71 + v_add3_u32 v71, v71, v80, v70 + v_xor_b32_e32 v73, v15, v81 + v_sub_u32_e32 v72, v73, v72 + v_lshlrev_b32_e32 v72, 2, v72 + v_add3_u32 v72, v72, v33, v71 + v_xor_b32_e32 v75, v14, v82 + v_sub_u32_e32 v73, v75, v73 + v_lshlrev_b32_e32 v73, 2, v73 + v_add3_u32 v73, v73, v88, v72 + v_xor_b32_e32 v78, v13, v8 + v_sub_u32_e32 v75, v78, v75 + v_lshlrev_b32_e32 v75, 2, v75 + v_add3_u32 v74, v75, v74, v73 + v_xor_b32_e32 v89, v11, v8 + v_sub_u32_e32 v75, v89, v78 + v_lshl_add_u32 v75, v75, 2, v74 + v_xor_b32_e32 v78, v13, v76 + v_sub_u32_e32 v76, v78, v89 + v_lshlrev_b32_e32 v76, 2, v76 + v_add3_u32 v76, v76, v34, v75 + v_xor_b32_e32 v34, v11, v77 + v_sub_u32_e32 v77, v34, v78 + v_lshlrev_b32_e32 v77, 2, v77 + v_add3_u32 v77, v77, v32, v76 + v_xor_b32_e32 v32, v13, v12 + v_sub_u32_e32 v34, v32, v34 + v_lshlrev_b32_e32 v34, 2, v34 + v_add3_u32 v78, v34, v1, v77 + v_xor_b32_e32 v1, v11, v79 + v_sub_u32_e32 v32, v1, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v79, v32, v80, v78 + v_xor_b32_e32 v32, v13, v81 + v_sub_u32_e32 v1, v32, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v80, v1, v33, v79 + v_xor_b32_e32 v1, v11, v82 + v_sub_u32_e32 v1, v1, v32 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v81, v1, v88, v80 + s_mov_b64 s[2:3], 0 + s_branch .LBB23_6 +.LBB23_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 +.LBB23_6: ; %Flow116 + v_lshl_or_b32 v82, v0, 3, v10 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB23_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s22, 6 + v_xor_b32_e32 v0, v7, v30 + v_lshl_add_u32 v49, v0, 3, v10 + v_xor_b32_e32 v0, v7, v29 + v_lshl_add_u32 v47, v0, 3, v10 + v_xor_b32_e32 v0, v7, v28 + v_lshl_add_u32 v19, v0, 3, v10 + v_lshrrev_b32_e32 v1, 1, v31 + v_sub_u32_e32 v6, v1, v6 + v_bfe_u32 v7, v31, 1, 4 + v_xor_b32_e32 v10, v7, v3 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v6, v6, 7, v19 + v_lshl_add_u32 v36, v10, 3, v6 + v_xor_b32_e32 v10, v7, v30 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v37, v10, 3, v6 + v_xor_b32_e32 v10, v7, v29 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v39, v10, 3, v6 + v_xor_b32_e32 v7, v7, v28 + v_sub_u32_e32 v0, v7, v0 + v_lshl_add_u32 v38, v0, 3, v6 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v0, 0x80, v5 + v_lshrrev_b32_e32 v6, 1, v0 + v_sub_u32_e32 v1, v6, v1 + v_bfe_u32 v0, v0, 1, 4 + v_xor_b32_e32 v10, v0, v3 + v_sub_u32_e32 v7, v10, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v40, v7, v1, v38 + v_xor_b32_e32 v1, v0, v30 + v_sub_u32_e32 v1, v1, v10 + v_lshl_add_u32 v41, v1, 3, v40 + v_xor_b32_e32 v1, v0, v29 + v_sub_u32_e32 v1, v1, v10 + v_lshl_add_u32 v43, v1, 3, v40 + v_xor_b32_e32 v0, v0, v28 + v_sub_u32_e32 v1, v0, v10 + v_lshl_add_u32 v42, v1, 3, v40 + v_add_u32_e32 v1, 0xc0, v5 + v_lshrrev_b32_e32 v5, 1, v1 + v_sub_u32_e32 v5, v5, v6 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v3, v1, v3 + v_sub_u32_e32 v0, v3, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v5, 7, v5 + v_add3_u32 v44, v0, v5, v42 + v_xor_b32_e32 v0, v1, v30 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v45, v0, 3, v44 + v_xor_b32_e32 v0, v1, v29 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v46, v0, 3, v44 + v_xor_b32_e32 v0, v1, v28 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v48, v0, 3, v44 + v_xor_b32_e32 v0, v22, v8 + v_sub_u32_e32 v1, v0, v4 + v_lshlrev_b32_e32 v1, 2, v1 + v_sub_u32_e32 v3, v21, v9 + v_lshlrev_b32_e32 v3, 12, v3 + v_add3_u32 v51, v50, v3, v1 + v_lshrrev_b32_e32 v1, 5, v27 + v_lshrrev_b16_e32 v3, 3, v27 + v_and_b32_e32 v3, 3, v3 + v_sub_u16_e32 v4, v3, v21 + v_bfe_i32 v4, v4, 0, 16 + v_lshl_or_b32 v5, v1, 4, v8 + v_xor_b32_e32 v6, v2, v5 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v7, 11, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v4, v4, 12, v7 + v_add3_u32 v52, v0, v4, v51 + v_lshrrev_b32_e32 v0, 5, v26 + v_sub_u32_e32 v1, v0, v1 + v_lshrrev_b16_e32 v7, 3, v26 + v_and_b32_e32 v7, 3, v7 + v_sub_u16_e32 v3, v7, v3 + v_bfe_i32 v3, v3, 0, 16 + v_lshl_or_b32 v9, v0, 4, v8 + v_xor_b32_e32 v10, v22, v9 + v_sub_u32_e32 v6, v10, v6 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v6, 2, v6 + v_lshl_add_u32 v1, v3, 12, v1 + v_add3_u32 v53, v6, v1, v52 + v_sub_u16_e32 v3, v21, v7 + v_bfe_i32 v3, v3, 0, 16 + v_xor_b32_e32 v6, v2, v12 + v_sub_u32_e32 v7, v6, v10 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v7, 2, v7 + v_lshl_or_b32 v0, v3, 12, v0 + v_add3_u32 v54, v7, v0, v53 + v_lshrrev_b32_e32 v3, 5, v25 + v_lshlrev_b32_e32 v7, 11, v3 + v_lshrrev_b16_e32 v10, 3, v25 + v_and_b32_e32 v10, 3, v10 + v_sub_u16_e32 v25, v10, v21 + v_lshl_or_b32 v26, v3, 4, v8 + v_and_b32_e32 v26, 31, v26 + v_xor_b32_e32 v27, v22, v26 + v_sub_u32_e32 v6, v27, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_mov_b32_e32 v28, 12 + v_lshlrev_b32_sdwa v25, v28, sext(v25) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v7, v7, v25, s18 + v_add3_u32 v59, v6, v7, v54 + v_lshrrev_b32_e32 v6, 5, v24 + v_sub_u32_e32 v3, v6, v3 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v10, v24, v10 + v_bfe_i32 v10, v10, 0, 16 + v_lshl_or_b32 v25, v6, 4, v8 + v_and_b32_e32 v25, 31, v25 + v_xor_b32_e32 v2, v2, v25 + v_sub_u32_e32 v27, v2, v27 + v_lshlrev_b32_e32 v3, 11, v3 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_add_u32 v3, v10, 12, v3 + v_add3_u32 v55, v27, v3, v59 + v_lshrrev_b32_e32 v10, 5, v23 + v_sub_u32_e32 v6, v10, v6 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v24, v23, v24 + v_bfe_i32 v24, v24, 0, 16 + v_lshl_or_b32 v27, v10, 4, v8 + v_and_b32_e32 v27, 31, v27 + v_xor_b32_e32 v22, v22, v27 + v_sub_u32_e32 v2, v22, v2 + v_lshlrev_b32_e32 v6, 11, v6 + v_lshlrev_b32_e32 v2, 2, v2 + v_lshl_add_u32 v6, v24, 12, v6 + v_add3_u32 v61, v2, v6, v55 + v_sub_u16_e32 v2, v21, v23 + v_xor_b32_e32 v21, v17, v8 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_lshlrev_b32_sdwa v2, v28, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v10, 11, v10 + v_sub_u32_e32 v2, v2, v10 + v_add3_u32 v56, v22, v2, v61 + v_xor_b32_e32 v10, v16, v8 + v_sub_u32_e32 v21, v10, v21 + v_lshl_add_u32 v57, v21, 2, v56 + v_xor_b32_e32 v21, v17, v5 + v_sub_u32_e32 v10, v21, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v58, v10, v4, v57 + v_xor_b32_e32 v10, v16, v9 + v_sub_u32_e32 v21, v10, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v60, v21, v1, v58 + v_xor_b32_e32 v21, v17, v12 + v_sub_u32_e32 v10, v21, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v62, v10, v0, v60 + v_xor_b32_e32 v10, v16, v26 + v_sub_u32_e32 v21, v10, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v63, v21, v7, v62 + v_xor_b32_e32 v17, v17, v25 + v_sub_u32_e32 v10, v17, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v64, v10, v3, v63 + v_xor_b32_e32 v10, v16, v27 + v_sub_u32_e32 v16, v10, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v65, v16, v6, v64 + v_xor_b32_e32 v16, v15, v8 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v66, v10, v2, v65 + v_xor_b32_e32 v10, v14, v8 + v_sub_u32_e32 v16, v10, v16 + v_lshl_add_u32 v67, v16, 2, v66 + v_xor_b32_e32 v16, v15, v5 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v68, v10, v4, v67 + v_xor_b32_e32 v10, v14, v9 + v_sub_u32_e32 v16, v10, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v69, v16, v1, v68 + v_xor_b32_e32 v16, v15, v12 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v70, v10, v0, v69 + v_xor_b32_e32 v10, v14, v26 + v_sub_u32_e32 v16, v10, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v71, v16, v7, v70 + v_xor_b32_e32 v15, v15, v25 + v_sub_u32_e32 v10, v15, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v72, v10, v3, v71 + v_xor_b32_e32 v10, v14, v27 + v_sub_u32_e32 v14, v10, v15 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v73, v14, v6, v72 + v_xor_b32_e32 v14, v13, v8 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v74, v10, v2, v73 + v_xor_b32_e32 v2, v11, v8 + v_sub_u32_e32 v8, v2, v14 + v_lshl_add_u32 v75, v8, 2, v74 + v_xor_b32_e32 v5, v13, v5 + v_sub_u32_e32 v2, v5, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v76, v2, v4, v75 + v_xor_b32_e32 v2, v11, v9 + v_sub_u32_e32 v4, v2, v5 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v77, v4, v1, v76 + v_xor_b32_e32 v1, v13, v12 + v_sub_u32_e32 v2, v1, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v78, v2, v0, v77 + v_xor_b32_e32 v0, v11, v26 + v_sub_u32_e32 v1, v0, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v79, v1, v7, v78 + v_xor_b32_e32 v1, v13, v25 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v80, v0, v3, v79 + v_xor_b32_e32 v0, v11, v27 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v81, v0, v6, v80 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 +.LBB23_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v18, s2, v18 + v_add_u32_e32 v0, 64, v20 + buffer_load_dwordx4 v[92:95], v20, s[8:11], 0 offen offset:64 + v_add_u32_e32 v1, s7, v0 + buffer_load_dwordx4 v[2:5], v18, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v18 + buffer_load_dwordx4 v[100:103], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[14:17], v6, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v6 + v_add_u32_e32 v7, s7, v1 + buffer_load_dwordx4 v[10:13], v6, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[104:107], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[96:99], v7, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[6:9], v6, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[22:23], v82 + ds_read_b64 v[20:21], v47 + ds_read_b32 v90, v50 offset:16384 + ds_read_b32 v91, v51 offset:16384 + ds_read_b32 v124, v52 offset:16384 + ds_read_b32 v125, v53 offset:16384 + ds_read_b32 v116, v54 offset:16384 + ds_read_b32 v117, v59 offset:16384 + ds_read_b32 v108, v55 offset:16384 + ds_read_b32 v109, v61 offset:16384 + ds_read_b32 v126, v56 offset:16384 + ds_read_b32 v127, v57 offset:16384 + ds_read_b32 v128, v58 offset:16384 + s_waitcnt lgkmcnt(9) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[22:23], v[90:91], a[64:79] + ds_read_b32 v129, v60 offset:16384 + ds_read_b32 v118, v62 offset:16384 + ds_read_b32 v119, v63 offset:16384 + ds_read_b32 v110, v64 offset:16384 + ds_read_b32 v111, v65 offset:16384 + ds_read_b32 v130, v66 offset:16384 + ds_read_b32 v131, v67 offset:16384 + s_waitcnt lgkmcnt(8) + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[22:23], v[126:127], a[80:95] + ds_read_b32 v132, v68 offset:16384 + ds_read_b32 v133, v69 offset:16384 + ds_read_b32 v120, v70 offset:16384 + ds_read_b32 v121, v71 offset:16384 + ds_read_b32 v112, v72 offset:16384 + ds_read_b32 v113, v73 offset:16384 + ds_read_b32 v134, v74 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[22:23], v[130:131], a[96:111] + ds_read_b32 v135, v75 offset:16384 + ds_read_b32 v136, v76 offset:16384 + ds_read_b32 v137, v77 offset:16384 + ds_read_b32 v122, v78 offset:16384 + ds_read_b32 v123, v79 offset:16384 + ds_read_b32 v114, v80 offset:16384 + ds_read_b32 v115, v81 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[22:23], v[134:135], a[112:127] + ds_read_b64 v[22:23], v36 + ds_read_b64 v[28:29], v37 + ds_read_b64 v[26:27], v39 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[22:23], v[90:91], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[22:23], v[126:127], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[22:23], v[130:131], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[22:23], v[134:135], a[176:191] + ds_read_b64 v[22:23], v40 + ds_read_b64 v[30:31], v41 + ds_read_b64 v[24:25], v43 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[22:23], v[90:91], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[22:23], v[126:127], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[22:23], v[130:131], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[22:23], v[134:135], a[240:255] + ds_read_b64 v[88:89], v44 + ds_read_b64 v[32:33], v45 + ds_read_b64 v[22:23], v46 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[88:89], v[90:91], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[88:89], v[126:127], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[88:89], v[130:131], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[88:89], v[134:135], a[48:63] + ds_read_b64 v[88:89], v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[88:89], v[124:125], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[88:89], v[128:129], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[88:89], v[132:133], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[88:89], v[136:137], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[28:29], v[124:125], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[28:29], v[128:129], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[28:29], v[132:133], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[28:29], v[136:137], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[30:31], v[124:125], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[30:31], v[128:129], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[30:31], v[132:133], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[30:31], v[136:137], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[32:33], v[124:125], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[32:33], v[128:129], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[32:33], v[132:133], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[32:33], v[136:137], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[20:21], v[116:117], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[20:21], v[118:119], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[20:21], v[120:121], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[20:21], v[122:123], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[26:27], v[116:117], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[26:27], v[118:119], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[26:27], v[120:121], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[26:27], v[122:123], a[176:191] + s_add_i32 s26, s3, -1 + v_readfirstlane_b32 s27, v227 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[24:25], v[116:117], a[192:207] + s_and_b32 s28, s27, 0xffffffc0 + s_lshr_b32 s27, s27, 2 + v_add_u32_e32 v21, s28, v83 + s_and_b32 s27, s27, 0x3ffffff0 + v_mov_b32_e32 v20, v0 + v_ashrrev_i32_e32 v1, 1, v21 + v_ashrrev_i32_e32 v89, 31, v21 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[24:25], v[118:119], a[208:223] + v_lshlrev_b32_e32 v0, 6, v21 + v_or_b32_e32 v34, 1, v21 + v_lshrrev_b32_e32 v90, 31, v21 + v_or_b32_e32 v21, 3, v21 + v_add_u32_e32 v88, s27, v84 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s26 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[24:25], v[120:121], a[224:239] + ds_read_b64 v[30:31], v19 + ds_read_b64 v[28:29], v38 + ds_read_b64 v[26:27], v42 + ds_read_b64 v[32:33], v48 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v89, 28, v89 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[24:25], v[122:123], a[240:255] + v_add_u32_e32 v24, v34, v90 + v_or_b32_e32 v25, 1, v1 + v_add_u32_e32 v90, v21, v90 + v_lshrrev_b32_e32 v91, 1, v88 + v_lshlrev_b32_e32 v124, 9, v88 + v_lshlrev_b32_e32 v88, 6, v88 + v_add_u32_e32 v125, v1, v89 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[22:23], v[116:117], a[16:31] + v_ashrrev_i32_e32 v116, 1, v24 + v_and_b32_e32 v117, 0x1ffffffe, v24 + v_ashrrev_i32_e32 v24, 31, v24 + v_add_u32_e32 v89, v25, v89 + v_ashrrev_i32_e32 v126, 1, v90 + v_and_b32_e32 v127, 0x1ffffffe, v90 + v_ashrrev_i32_e32 v90, 31, v90 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[22:23], v[118:119], a[32:47] + v_and_b32_e32 v91, 16, v91 + v_and_b32_e32 v118, 0x3000, v124 + v_and_b32_e32 v88, 0xfffff800, v88 + v_and_b32_e32 v119, -16, v125 + v_sub_u32_e32 v124, v116, v1 + v_sub_u32_e32 v34, v34, v117 + v_lshrrev_b32_e32 v24, 28, v24 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[22:23], v[120:121], a[0:15] + v_sub_u32_e32 v117, v25, v116 + v_and_b32_e32 v89, -16, v89 + v_sub_u32_e32 v120, v126, v25 + v_sub_u32_e32 v21, v21, v127 + v_lshrrev_b32_e32 v90, 28, v90 + v_xor_b32_e32 v121, v91, v35 + v_add_u32_e32 v88, v118, v88 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[22:23], v[122:123], a[48:63] + v_or_b32_e32 v22, 1, v91 + v_or_b32_e32 v23, 2, v91 + v_or_b32_e32 v118, 3, v91 + v_or_b32_e32 v122, 4, v91 + v_or_b32_e32 v123, 5, v91 + v_or_b32_e32 v125, 6, v91 + v_or_b32_e32 v127, 7, v91 + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[30:31], v[108:109], a[64:79] + v_or_b32_e32 v128, 8, v91 + v_or_b32_e32 v129, 9, v91 + v_or_b32_e32 v130, 10, v91 + v_or_b32_e32 v131, 11, v91 + v_or_b32_e32 v132, 12, v91 + v_or_b32_e32 v133, 13, v91 + v_or_b32_e32 v134, 14, v91 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[30:31], v[110:111], a[80:95] + v_or_b32_e32 v91, 15, v91 + v_sub_u32_e32 v1, v1, v119 + v_lshl_or_b32 v34, v34, 3, v86 + v_add_u32_e32 v24, v116, v24 + v_sub_u32_e32 v25, v25, v89 + v_lshlrev_b32_e32 v89, 7, v117 + v_lshl_or_b32 v21, v21, 3, v86 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[30:31], v[112:113], a[96:111] + v_add_u32_e32 v90, v126, v90 + v_lshlrev_b32_e32 v117, 7, v120 + v_lshl_or_b32 v88, v121, 2, v88 + v_xor_b32_e32 v22, v22, v35 + v_xor_b32_e32 v23, v23, v35 + v_xor_b32_e32 v118, v118, v35 + v_xor_b32_e32 v119, v122, v35 + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[30:31], v[114:115], a[112:127] + v_xor_b32_e32 v30, v123, v35 + v_xor_b32_e32 v31, v125, v35 + v_xor_b32_e32 v120, v127, v35 + v_xor_b32_e32 v122, v128, v35 + v_xor_b32_e32 v123, v129, v35 + v_xor_b32_e32 v125, v130, v35 + v_xor_b32_e32 v127, v131, v35 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[28:29], v[108:109], a[128:143] + v_xor_b32_e32 v128, v132, v35 + v_xor_b32_e32 v129, v133, v35 + v_xor_b32_e32 v130, v134, v35 + v_xor_b32_e32 v91, v91, v35 + v_xor_b32_e32 v131, v1, v85 + v_xor_b32_e32 v1, v1, v86 + v_add_u32_e32 v132, v34, v87 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[28:29], v[110:111], a[144:159] + v_and_b32_e32 v24, -16, v24 + v_xor_b32_e32 v133, v25, v85 + v_xor_b32_e32 v25, v25, v86 + v_add_u32_e32 v134, v21, v87 + v_and_b32_e32 v90, -16, v90 + v_sub_u32_e32 v121, v22, v121 + v_sub_u32_e32 v22, v23, v22 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[28:29], v[112:113], a[160:175] + v_sub_u32_e32 v23, v118, v23 + v_sub_u32_e32 v118, v119, v118 + v_sub_u32_e32 v119, v30, v119 + v_sub_u32_e32 v30, v31, v30 + v_sub_u32_e32 v31, v120, v31 + v_sub_u32_e32 v120, v122, v120 + v_sub_u32_e32 v122, v123, v122 + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[28:29], v[114:115], a[176:191] + v_sub_u32_e32 v28, v125, v123 + v_sub_u32_e32 v29, v127, v125 + v_sub_u32_e32 v123, v128, v127 + v_sub_u32_e32 v125, v129, v128 + v_sub_u32_e32 v127, v130, v129 + v_sub_u32_e32 v91, v91, v130 + v_lshl_add_u32 v128, v131, 3, v0 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[26:27], v[108:109], a[192:207] + v_lshl_add_u32 v0, v1, 3, v0 + v_sub_u32_e32 v24, v116, v24 + v_sub_u32_e32 v116, v25, v133 + v_sub_u32_e32 v90, v126, v90 + v_lshl_add_u32 v121, v121, 2, v88 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshlrev_b32_e32 v118, 2, v118 + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[26:27], v[110:111], a[208:223] + v_lshlrev_b32_e32 v119, 2, v119 + v_lshlrev_b32_e32 v30, 2, v30 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshlrev_b32_e32 v120, 2, v120 + v_lshlrev_b32_e32 v122, 2, v122 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshlrev_b32_e32 v29, 2, v29 + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[26:27], v[112:113], a[224:239] + v_lshlrev_b32_e32 v123, 2, v123 + v_lshlrev_b32_e32 v125, 2, v125 + v_lshlrev_b32_e32 v126, 2, v127 + v_xor_b32_e32 v127, v132, v24 + v_lshl_add_u32 v124, v124, 7, v0 + v_xor_b32_e32 v24, v34, v24 + v_xor_b32_e32 v34, v134, v90 + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[26:27], v[114:115], a[240:255] + v_xor_b32_e32 v21, v21, v90 + v_lshl_add_u32 v22, v22, 2, v121 + v_sub_u32_e32 v26, v127, v1 + v_sub_u32_e32 v1, v24, v1 + v_sub_u32_e32 v24, v133, v24 + v_sub_u32_e32 v25, v34, v25 + v_sub_u32_e32 v21, v21, v34 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[32:33], v[108:109], a[16:31] + v_add3_u32 v23, v22, s6, v23 + v_lshl_add_u32 v26, v26, 3, v124 + v_lshl_add_u32 v1, v1, 3, v124 + v_lshlrev_b32_e32 v24, 3, v24 + v_lshlrev_b32_e32 v25, 3, v25 + v_add3_u32 v27, v23, s6, v118 + v_add3_u32 v24, v24, v89, v1 + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[32:33], v[110:111], a[32:47] + v_add3_u32 v34, v27, s6, v119 + v_lshl_add_u32 v89, v116, 3, v24 + v_add3_u32 v30, v34, s6, v30 + v_add3_u32 v25, v25, v117, v89 + v_add3_u32 v31, v30, s6, v31 + v_lshl_add_u32 v21, v21, 3, v25 + v_add3_u32 v90, v31, s6, v120 + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[32:33], v[112:113], a[0:15] + v_add3_u32 v108, v90, s6, v122 + v_add3_u32 v28, v108, s6, v28 + v_add3_u32 v29, v28, s6, v29 + v_add3_u32 v109, v29, s6, v123 + v_add3_u32 v110, v109, s6, v125 + v_add3_u32 v111, v110, s6, v126 + v_lshl_add_u32 v91, v91, 2, v111 + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[32:33], v[114:115], a[48:63] + s_waitcnt vmcnt(7) + ds_write_b64 v128, v[92:93] + ds_write_b64 v0, v[94:95] + s_waitcnt vmcnt(6) + v_perm_b32 v0, v2, v2, s18 + v_perm_b32 v2, v3, v3, s18 + v_perm_b32 v3, v4, v4, s18 + v_perm_b32 v4, v5, v5, s18 + s_waitcnt vmcnt(5) + ds_write_b64 v26, v[100:101] + ds_write_b64 v1, v[102:103] + s_waitcnt vmcnt(4) + v_perm_b32 v1, v14, v14, s18 + v_perm_b32 v5, v15, v15, s18 + v_perm_b32 v14, v16, v16, s18 + v_perm_b32 v15, v17, v17, s18 + s_waitcnt vmcnt(2) + ds_write_b64 v24, v[104:105] + ds_write_b64 v89, v[106:107] + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + v_perm_b32 v16, v1, v0, s19 + v_perm_b32 v0, v1, v0, s25 + v_perm_b32 v1, v5, v2, s19 + v_perm_b32 v2, v5, v2, s25 + v_perm_b32 v5, v14, v3, s19 + v_perm_b32 v3, v14, v3, s25 + v_perm_b32 v14, v15, v4, s19 + v_perm_b32 v4, v15, v4, s25 + s_waitcnt vmcnt(1) + ds_write_b64 v25, v[96:97] + ds_write_b64 v21, v[98:99] + s_waitcnt vmcnt(0) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + v_perm_b32 v15, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + v_perm_b32 v13, v15, v16, s23 + v_perm_b32 v15, v15, v16, s24 + v_perm_b32 v16, v6, v0, s23 + v_perm_b32 v0, v6, v0, s24 + v_perm_b32 v6, v10, v1, s23 + v_perm_b32 v1, v10, v1, s24 + v_perm_b32 v10, v7, v2, s23 + v_perm_b32 v2, v7, v2, s24 + v_perm_b32 v7, v11, v5, s23 + v_perm_b32 v5, v11, v5, s24 + v_perm_b32 v11, v8, v3, s23 + v_perm_b32 v3, v8, v3, s24 + v_perm_b32 v8, v12, v14, s23 + v_perm_b32 v12, v12, v14, s24 + v_perm_b32 v14, v9, v4, s23 + v_perm_b32 v4, v9, v4, s24 + ds_write_b32 v88, v13 offset:16384 + ds_write_b32 v121, v15 offset:16512 + ds_write_b32 v22, v16 offset:16640 + ds_write_b32 v23, v0 offset:16640 + ds_write_b32 v27, v6 offset:16640 + ds_write_b32 v34, v1 offset:16640 + ds_write_b32 v30, v10 offset:16640 + ds_write_b32 v31, v2 offset:16640 + ds_write_b32 v90, v7 offset:16640 + ds_write_b32 v108, v5 offset:16640 + ds_write_b32 v28, v11 offset:16640 + ds_write_b32 v29, v3 offset:16640 + ds_write_b32 v109, v8 offset:16640 + ds_write_b32 v110, v12 offset:16640 + ds_write_b32 v111, v14 offset:16640 + ds_write_b32 v91, v4 offset:16768 + s_cbranch_scc1 .LBB23_8 +.LBB23_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESC_SC_Li1EEES2_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSK_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDaRKS1O_ + v_accvgpr_read_b32 v0, a64 + v_accvgpr_read_b32 v1, a65 + v_accvgpr_read_b32 v2, a66 + v_accvgpr_read_b32 v3, a67 + v_accvgpr_read_b32 v4, a68 + v_accvgpr_read_b32 v5, a69 + v_accvgpr_read_b32 v6, a70 + v_accvgpr_read_b32 v7, a71 + v_accvgpr_read_b32 v8, a72 + v_accvgpr_read_b32 v9, a73 + v_accvgpr_read_b32 v10, a74 + v_accvgpr_read_b32 v11, a75 + v_accvgpr_read_b32 v12, a76 + v_accvgpr_read_b32 v13, a77 + v_accvgpr_read_b32 v14, a78 + v_accvgpr_read_b32 v15, a79 + v_accvgpr_read_b32 v20, a160 + v_accvgpr_read_b32 v21, a161 + v_accvgpr_read_b32 v22, a162 + v_accvgpr_read_b32 v23, a163 + v_accvgpr_read_b32 v24, a164 + v_accvgpr_read_b32 v25, a165 + v_accvgpr_read_b32 v26, a166 + v_accvgpr_read_b32 v27, a167 + v_accvgpr_read_b32 v28, a168 + v_accvgpr_read_b32 v29, a169 + v_accvgpr_read_b32 v30, a170 + v_accvgpr_read_b32 v31, a171 + v_accvgpr_read_b32 v32, a172 + v_accvgpr_read_b32 v33, a173 + v_accvgpr_read_b32 v34, a174 + v_accvgpr_read_b32 v35, a175 + v_accvgpr_read_b32 v84, a176 + v_accvgpr_read_b32 v85, a177 + v_accvgpr_read_b32 v86, a178 + v_accvgpr_read_b32 v87, a179 + v_accvgpr_read_b32 v88, a180 + v_accvgpr_read_b32 v89, a181 + v_accvgpr_read_b32 v90, a182 + v_accvgpr_read_b32 v91, a183 + v_accvgpr_read_b32 v92, a184 + v_accvgpr_read_b32 v93, a185 + v_accvgpr_read_b32 v94, a186 + v_accvgpr_read_b32 v95, a187 + v_accvgpr_read_b32 v96, a188 + v_accvgpr_read_b32 v97, a189 + v_accvgpr_read_b32 v98, a190 + v_accvgpr_read_b32 v99, a191 + v_accvgpr_read_b32 v100, a208 + v_accvgpr_read_b32 v101, a209 + v_accvgpr_read_b32 v102, a210 + v_accvgpr_read_b32 v103, a211 + v_accvgpr_read_b32 v104, a212 + v_accvgpr_read_b32 v105, a213 + v_accvgpr_read_b32 v106, a214 + v_accvgpr_read_b32 v107, a215 + v_accvgpr_read_b32 v108, a216 + v_accvgpr_read_b32 v109, a217 + v_accvgpr_read_b32 v110, a218 + v_accvgpr_read_b32 v111, a219 + v_accvgpr_read_b32 v112, a220 + v_accvgpr_read_b32 v113, a221 + v_accvgpr_read_b32 v114, a222 + v_accvgpr_read_b32 v115, a223 + v_accvgpr_read_b32 v116, a224 + v_accvgpr_read_b32 v117, a225 + v_accvgpr_read_b32 v118, a226 + v_accvgpr_read_b32 v119, a227 + v_accvgpr_read_b32 v120, a228 + v_accvgpr_read_b32 v121, a229 + v_accvgpr_read_b32 v122, a230 + v_accvgpr_read_b32 v123, a231 + v_accvgpr_read_b32 v124, a232 + v_accvgpr_read_b32 v125, a233 + v_accvgpr_read_b32 v126, a234 + v_accvgpr_read_b32 v127, a235 + v_accvgpr_read_b32 v128, a236 + v_accvgpr_read_b32 v129, a237 + v_accvgpr_read_b32 v130, a238 + v_accvgpr_read_b32 v131, a239 + v_accvgpr_mov_b32 a64, a240 + v_accvgpr_mov_b32 a65, a241 + v_accvgpr_mov_b32 a66, a242 + v_accvgpr_mov_b32 a67, a243 + v_accvgpr_mov_b32 a68, a244 + v_accvgpr_mov_b32 a69, a245 + v_accvgpr_mov_b32 a70, a246 + v_accvgpr_mov_b32 a71, a247 + v_accvgpr_mov_b32 a72, a248 + v_accvgpr_mov_b32 a73, a249 + v_accvgpr_mov_b32 a74, a250 + v_accvgpr_mov_b32 a75, a251 + v_accvgpr_mov_b32 a76, a252 + v_accvgpr_mov_b32 a77, a253 + v_accvgpr_mov_b32 a78, a254 + v_accvgpr_mov_b32 a79, a255 + v_accvgpr_read_b32 v132, a0 + v_accvgpr_read_b32 v133, a1 + v_accvgpr_read_b32 v134, a2 + v_accvgpr_read_b32 v135, a3 + v_accvgpr_read_b32 v136, a4 + v_accvgpr_read_b32 v137, a5 + v_accvgpr_read_b32 v138, a6 + v_accvgpr_read_b32 v139, a7 + v_accvgpr_read_b32 v140, a8 + v_accvgpr_read_b32 v141, a9 + v_accvgpr_read_b32 v142, a10 + v_accvgpr_read_b32 v143, a11 + v_accvgpr_read_b32 v144, a12 + v_accvgpr_read_b32 v145, a13 + v_accvgpr_read_b32 v146, a14 + v_accvgpr_read_b32 v147, a15 + v_accvgpr_read_b32 v148, a48 + v_accvgpr_read_b32 v149, a49 + v_accvgpr_read_b32 v150, a50 + v_accvgpr_read_b32 v151, a51 + v_accvgpr_read_b32 v152, a52 + v_accvgpr_read_b32 v153, a53 + v_accvgpr_read_b32 v154, a54 + v_accvgpr_read_b32 v155, a55 + v_accvgpr_read_b32 v156, a56 + v_accvgpr_read_b32 v157, a57 + v_accvgpr_read_b32 v158, a58 + v_accvgpr_read_b32 v159, a59 + v_accvgpr_read_b32 v160, a60 + v_accvgpr_read_b32 v161, a61 + v_accvgpr_read_b32 v162, a62 + v_accvgpr_read_b32 v163, a63 + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_write_b32 a0, v0 + v_accvgpr_write_b32 a1, v1 + v_accvgpr_write_b32 a2, v2 + v_accvgpr_write_b32 a3, v3 + v_accvgpr_write_b32 a4, v4 + v_accvgpr_write_b32 a5, v5 + v_accvgpr_write_b32 a6, v6 + v_accvgpr_write_b32 a7, v7 + v_accvgpr_write_b32 a8, v8 + v_accvgpr_write_b32 a9, v9 + v_accvgpr_write_b32 a10, v10 + v_accvgpr_write_b32 a11, v11 + v_accvgpr_write_b32 a12, v12 + v_accvgpr_write_b32 a13, v13 + v_accvgpr_write_b32 a14, v14 + v_accvgpr_write_b32 a15, v15 + ds_read_b64 v[2:3], v82 + ds_read_b32 v0, v50 offset:16384 + ds_read_b64 v[4:5], v49 + ds_read_b64 v[6:7], v47 + ds_read_b32 v1, v51 offset:16384 + ds_read_b32 v50, v52 offset:16384 + ds_read_b32 v51, v53 offset:16384 + ds_read_b32 v52, v54 offset:16384 + ds_read_b32 v53, v59 offset:16384 + ds_read_b32 v54, v55 offset:16384 + ds_read_b32 v55, v61 offset:16384 + ds_read_b64 v[8:9], v48 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[2:3], v[0:1], a[0:15] + v_accvgpr_mov_b32 a255, a95 + v_accvgpr_mov_b32 a254, a94 + v_accvgpr_mov_b32 a253, a93 + v_accvgpr_mov_b32 a252, a92 + v_accvgpr_mov_b32 a251, a91 + v_accvgpr_mov_b32 a250, a90 + v_accvgpr_mov_b32 a249, a89 + v_accvgpr_mov_b32 a248, a88 + v_accvgpr_mov_b32 a247, a87 + v_accvgpr_mov_b32 a246, a86 + v_accvgpr_mov_b32 a245, a85 + v_accvgpr_mov_b32 a244, a84 + v_accvgpr_mov_b32 a243, a83 + v_accvgpr_mov_b32 a242, a82 + v_accvgpr_mov_b32 a241, a81 + v_accvgpr_mov_b32 a240, a80 + ds_read_b32 v48, v56 offset:16384 + ds_read_b32 v49, v57 offset:16384 + ds_read_b32 v56, v58 offset:16384 + ds_read_b32 v57, v60 offset:16384 + ds_read_b32 v58, v62 offset:16384 + ds_read_b32 v59, v63 offset:16384 + ds_read_b32 v60, v64 offset:16384 + ds_read_b32 v61, v65 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[2:3], v[48:49], a[240:255] + v_accvgpr_mov_b32 a239, a111 + v_accvgpr_mov_b32 a238, a110 + v_accvgpr_mov_b32 a237, a109 + v_accvgpr_mov_b32 a236, a108 + v_accvgpr_mov_b32 a235, a107 + v_accvgpr_mov_b32 a234, a106 + v_accvgpr_mov_b32 a233, a105 + v_accvgpr_mov_b32 a232, a104 + v_accvgpr_mov_b32 a231, a103 + v_accvgpr_mov_b32 a230, a102 + v_accvgpr_mov_b32 a229, a101 + v_accvgpr_mov_b32 a228, a100 + v_accvgpr_mov_b32 a227, a99 + v_accvgpr_mov_b32 a226, a98 + v_accvgpr_mov_b32 a225, a97 + v_accvgpr_mov_b32 a224, a96 + ds_read_b32 v62, v66 offset:16384 + ds_read_b32 v63, v67 offset:16384 + ds_read_b32 v64, v68 offset:16384 + ds_read_b32 v65, v69 offset:16384 + ds_read_b32 v66, v70 offset:16384 + ds_read_b32 v67, v71 offset:16384 + ds_read_b32 v68, v72 offset:16384 + ds_read_b32 v69, v73 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[2:3], v[62:63], a[224:239] + v_accvgpr_mov_b32 a223, a127 + v_accvgpr_mov_b32 a222, a126 + v_accvgpr_mov_b32 a221, a125 + v_accvgpr_mov_b32 a220, a124 + v_accvgpr_mov_b32 a219, a123 + v_accvgpr_mov_b32 a218, a122 + v_accvgpr_mov_b32 a217, a121 + v_accvgpr_mov_b32 a216, a120 + v_accvgpr_mov_b32 a215, a119 + v_accvgpr_mov_b32 a214, a118 + v_accvgpr_mov_b32 a213, a117 + v_accvgpr_mov_b32 a212, a116 + v_accvgpr_mov_b32 a211, a115 + v_accvgpr_mov_b32 a210, a114 + v_accvgpr_mov_b32 a209, a113 + v_accvgpr_mov_b32 a208, a112 + ds_read_b32 v70, v74 offset:16384 + ds_read_b32 v71, v75 offset:16384 + ds_read_b32 v72, v76 offset:16384 + ds_read_b32 v73, v77 offset:16384 + ds_read_b32 v74, v78 offset:16384 + ds_read_b32 v75, v79 offset:16384 + ds_read_b32 v76, v80 offset:16384 + ds_read_b32 v77, v81 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[2:3], v[70:71], a[208:223] + ds_read_b64 v[2:3], v36 + v_accvgpr_mov_b32 a191, a143 + v_accvgpr_mov_b32 a190, a142 + v_accvgpr_mov_b32 a189, a141 + v_accvgpr_mov_b32 a188, a140 + v_accvgpr_mov_b32 a187, a139 + v_accvgpr_mov_b32 a186, a138 + v_accvgpr_mov_b32 a185, a137 + v_accvgpr_mov_b32 a184, a136 + v_accvgpr_mov_b32 a183, a135 + v_accvgpr_mov_b32 a182, a134 + v_accvgpr_mov_b32 a181, a133 + v_accvgpr_mov_b32 a180, a132 + v_accvgpr_mov_b32 a179, a131 + v_accvgpr_mov_b32 a178, a130 + v_accvgpr_mov_b32 a177, a129 + v_accvgpr_mov_b32 a176, a128 + ds_read_b64 v[10:11], v37 + ds_read_b64 v[12:13], v39 + ds_read_b64 v[14:15], v19 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[2:3], v[0:1], a[176:191] + v_accvgpr_mov_b32 a175, a159 + v_accvgpr_mov_b32 a174, a158 + v_accvgpr_mov_b32 a173, a157 + v_accvgpr_mov_b32 a172, a156 + v_accvgpr_mov_b32 a171, a155 + v_accvgpr_mov_b32 a170, a154 + v_accvgpr_mov_b32 a169, a153 + v_accvgpr_mov_b32 a168, a152 + v_accvgpr_mov_b32 a167, a151 + v_accvgpr_mov_b32 a166, a150 + v_accvgpr_mov_b32 a165, a149 + v_accvgpr_mov_b32 a164, a148 + v_accvgpr_mov_b32 a163, a147 + v_accvgpr_mov_b32 a162, a146 + v_accvgpr_mov_b32 a161, a145 + v_accvgpr_mov_b32 a160, a144 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[2:3], v[48:49], a[160:175] + v_accvgpr_write_b32 a159, v35 + v_accvgpr_write_b32 a158, v34 + v_accvgpr_write_b32 a157, v33 + v_accvgpr_write_b32 a156, v32 + v_accvgpr_write_b32 a155, v31 + v_accvgpr_write_b32 a154, v30 + v_accvgpr_write_b32 a153, v29 + v_accvgpr_write_b32 a152, v28 + v_accvgpr_write_b32 a151, v27 + v_accvgpr_write_b32 a150, v26 + v_accvgpr_write_b32 a149, v25 + v_accvgpr_write_b32 a148, v24 + v_accvgpr_write_b32 a147, v23 + v_accvgpr_write_b32 a146, v22 + v_accvgpr_write_b32 a145, v21 + v_accvgpr_write_b32 a144, v20 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[2:3], v[62:63], a[144:159] + v_accvgpr_write_b32 a143, v99 + v_accvgpr_write_b32 a142, v98 + v_accvgpr_write_b32 a141, v97 + v_accvgpr_write_b32 a140, v96 + v_accvgpr_write_b32 a139, v95 + v_accvgpr_write_b32 a138, v94 + v_accvgpr_write_b32 a137, v93 + v_accvgpr_write_b32 a136, v92 + v_accvgpr_write_b32 a135, v91 + v_accvgpr_write_b32 a134, v90 + v_accvgpr_write_b32 a133, v89 + v_accvgpr_write_b32 a132, v88 + v_accvgpr_write_b32 a131, v87 + v_accvgpr_write_b32 a130, v86 + v_accvgpr_write_b32 a129, v85 + v_accvgpr_write_b32 a128, v84 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[2:3], v[70:71], a[128:143] + ds_read_b64 v[2:3], v40 + v_accvgpr_mov_b32 a112, a192 + v_accvgpr_mov_b32 a113, a193 + v_accvgpr_mov_b32 a114, a194 + v_accvgpr_mov_b32 a115, a195 + v_accvgpr_mov_b32 a116, a196 + v_accvgpr_mov_b32 a117, a197 + v_accvgpr_mov_b32 a118, a198 + v_accvgpr_mov_b32 a119, a199 + v_accvgpr_mov_b32 a120, a200 + v_accvgpr_mov_b32 a121, a201 + v_accvgpr_mov_b32 a122, a202 + v_accvgpr_mov_b32 a123, a203 + v_accvgpr_mov_b32 a124, a204 + v_accvgpr_mov_b32 a125, a205 + v_accvgpr_mov_b32 a126, a206 + v_accvgpr_mov_b32 a127, a207 + ds_read_b64 v[16:17], v41 + ds_read_b64 v[18:19], v43 + ds_read_b64 v[20:21], v38 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[2:3], v[0:1], a[112:127] + v_accvgpr_write_b32 a96, v100 + v_accvgpr_write_b32 a97, v101 + v_accvgpr_write_b32 a98, v102 + v_accvgpr_write_b32 a99, v103 + v_accvgpr_write_b32 a100, v104 + v_accvgpr_write_b32 a101, v105 + v_accvgpr_write_b32 a102, v106 + v_accvgpr_write_b32 a103, v107 + v_accvgpr_write_b32 a104, v108 + v_accvgpr_write_b32 a105, v109 + v_accvgpr_write_b32 a106, v110 + v_accvgpr_write_b32 a107, v111 + v_accvgpr_write_b32 a108, v112 + v_accvgpr_write_b32 a109, v113 + v_accvgpr_write_b32 a110, v114 + v_accvgpr_write_b32 a111, v115 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[2:3], v[48:49], a[96:111] + v_accvgpr_write_b32 a80, v116 + v_accvgpr_write_b32 a81, v117 + v_accvgpr_write_b32 a82, v118 + v_accvgpr_write_b32 a83, v119 + v_accvgpr_write_b32 a84, v120 + v_accvgpr_write_b32 a85, v121 + v_accvgpr_write_b32 a86, v122 + v_accvgpr_write_b32 a87, v123 + v_accvgpr_write_b32 a88, v124 + v_accvgpr_write_b32 a89, v125 + v_accvgpr_write_b32 a90, v126 + v_accvgpr_write_b32 a91, v127 + v_accvgpr_write_b32 a92, v128 + v_accvgpr_write_b32 a93, v129 + v_accvgpr_write_b32 a94, v130 + v_accvgpr_write_b32 a95, v131 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[2:3], v[62:63], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[2:3], v[70:71], a[64:79] + ds_read_b64 v[2:3], v44 + v_accvgpr_mov_b32 a63, a31 + v_accvgpr_mov_b32 a62, a30 + v_accvgpr_mov_b32 a61, a29 + v_accvgpr_mov_b32 a60, a28 + v_accvgpr_mov_b32 a59, a27 + v_accvgpr_mov_b32 a58, a26 + v_accvgpr_mov_b32 a57, a25 + v_accvgpr_mov_b32 a56, a24 + v_accvgpr_mov_b32 a55, a23 + v_accvgpr_mov_b32 a54, a22 + v_accvgpr_mov_b32 a53, a21 + v_accvgpr_mov_b32 a52, a20 + v_accvgpr_mov_b32 a51, a19 + v_accvgpr_mov_b32 a50, a18 + v_accvgpr_mov_b32 a49, a17 + v_accvgpr_mov_b32 a48, a16 + ds_read_b64 v[22:23], v45 + ds_read_b64 v[24:25], v46 + ds_read_b64 v[26:27], v42 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[2:3], v[0:1], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[2:3], v[48:49], a[32:47] + v_accvgpr_write_b32 a16, v132 + v_accvgpr_write_b32 a17, v133 + v_accvgpr_write_b32 a18, v134 + v_accvgpr_write_b32 a19, v135 + v_accvgpr_write_b32 a20, v136 + v_accvgpr_write_b32 a21, v137 + v_accvgpr_write_b32 a22, v138 + v_accvgpr_write_b32 a23, v139 + v_accvgpr_write_b32 a24, v140 + v_accvgpr_write_b32 a25, v141 + v_accvgpr_write_b32 a26, v142 + v_accvgpr_write_b32 a27, v143 + v_accvgpr_write_b32 a28, v144 + v_accvgpr_write_b32 a29, v145 + v_accvgpr_write_b32 a30, v146 + v_accvgpr_write_b32 a31, v147 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[2:3], v[62:63], a[16:31] + v_accvgpr_write_b32 a207, v163 + v_accvgpr_write_b32 a206, v162 + v_accvgpr_write_b32 a205, v161 + v_accvgpr_write_b32 a204, v160 + v_accvgpr_write_b32 a203, v159 + v_accvgpr_write_b32 a202, v158 + v_accvgpr_write_b32 a201, v157 + v_accvgpr_write_b32 a200, v156 + v_accvgpr_write_b32 a199, v155 + v_accvgpr_write_b32 a198, v154 + v_accvgpr_write_b32 a197, v153 + v_accvgpr_write_b32 a196, v152 + v_accvgpr_write_b32 a195, v151 + v_accvgpr_write_b32 a194, v150 + v_accvgpr_write_b32 a193, v149 + v_accvgpr_write_b32 a192, v148 + s_nop 1 + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[2:3], v[70:71], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[4:5], v[50:51], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[4:5], v[56:57], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[4:5], v[64:65], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[4:5], v[72:73], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[10:11], v[50:51], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[10:11], v[56:57], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[10:11], v[64:65], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[10:11], v[72:73], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[16:17], v[50:51], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[16:17], v[56:57], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[16:17], v[64:65], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[16:17], v[72:73], a[64:79] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[22:23], v[50:51], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[22:23], v[56:57], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[22:23], v[64:65], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[22:23], v[72:73], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[6:7], v[52:53], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[6:7], v[58:59], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[6:7], v[66:67], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[6:7], v[74:75], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[12:13], v[52:53], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[12:13], v[58:59], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[12:13], v[66:67], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[12:13], v[74:75], a[128:143] + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[18:19], v[52:53], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[18:19], v[58:59], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[18:19], v[66:67], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[18:19], v[74:75], a[64:79] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[24:25], v[52:53], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[24:25], v[58:59], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[24:25], v[66:67], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[24:25], v[74:75], a[192:207] + v_mfma_f32_32x32x16_fp8_fp8 a[0:15], v[14:15], v[54:55], a[0:15] + v_mfma_f32_32x32x16_fp8_fp8 a[240:255], v[14:15], v[60:61], a[240:255] + v_mfma_f32_32x32x16_fp8_fp8 a[224:239], v[14:15], v[68:69], a[224:239] + v_mfma_f32_32x32x16_fp8_fp8 a[208:223], v[14:15], v[76:77], a[208:223] + v_mfma_f32_32x32x16_fp8_fp8 a[176:191], v[20:21], v[54:55], a[176:191] + v_mfma_f32_32x32x16_fp8_fp8 a[160:175], v[20:21], v[60:61], a[160:175] + v_mfma_f32_32x32x16_fp8_fp8 a[144:159], v[20:21], v[68:69], a[144:159] + v_mfma_f32_32x32x16_fp8_fp8 a[128:143], v[20:21], v[76:77], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_fp8_fp8 a[112:127], v[26:27], v[54:55], a[112:127] + v_mfma_f32_32x32x16_fp8_fp8 a[96:111], v[26:27], v[60:61], a[96:111] + v_mfma_f32_32x32x16_fp8_fp8 a[80:95], v[26:27], v[68:69], a[80:95] + v_mfma_f32_32x32x16_fp8_fp8 a[64:79], v[26:27], v[76:77], a[64:79] + v_mfma_f32_32x32x16_fp8_fp8 a[48:63], v[8:9], v[54:55], a[48:63] + v_mfma_f32_32x32x16_fp8_fp8 a[32:47], v[8:9], v[60:61], a[32:47] + v_mfma_f32_32x32x16_fp8_fp8 a[16:31], v[8:9], v[68:69], a[16:31] + v_mfma_f32_32x32x16_fp8_fp8 a[192:207], v[8:9], v[76:77], a[192:207] +.LBB23_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESC_SC_Li1EEES2_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSK_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDaRKS1O_R + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v1, a4 + v_accvgpr_read_b32 v34, a5 + v_accvgpr_read_b32 v0, a6 + v_accvgpr_read_b32 v139, a7 + v_accvgpr_read_b32 v138, a8 + v_accvgpr_read_b32 v137, a9 + v_accvgpr_read_b32 v136, a10 + v_accvgpr_read_b32 v135, a11 + v_accvgpr_read_b32 v134, a12 + v_accvgpr_read_b32 v133, a13 + v_accvgpr_read_b32 v132, a14 + v_accvgpr_read_b32 v131, a15 + v_accvgpr_read_b32 v108, a240 + v_accvgpr_read_b32 v107, a241 + v_accvgpr_read_b32 v106, a242 + v_accvgpr_read_b32 v105, a243 + v_accvgpr_read_b32 v104, a244 + v_accvgpr_read_b32 v103, a245 + v_accvgpr_read_b32 v102, a246 + v_accvgpr_read_b32 v101, a247 + v_accvgpr_read_b32 v100, a248 + v_accvgpr_read_b32 v99, a249 + v_accvgpr_read_b32 v98, a250 + v_accvgpr_read_b32 v97, a251 + v_accvgpr_read_b32 v96, a252 + v_accvgpr_read_b32 v95, a253 + v_accvgpr_read_b32 v94, a254 + v_accvgpr_read_b32 v93, a255 + v_accvgpr_read_b32 v92, a224 + v_accvgpr_read_b32 v91, a225 + v_accvgpr_read_b32 v90, a226 + v_accvgpr_read_b32 v89, a227 + v_accvgpr_read_b32 v88, a228 + v_accvgpr_read_b32 v87, a229 + v_accvgpr_read_b32 v86, a230 + v_accvgpr_read_b32 v85, a231 + v_accvgpr_read_b32 v84, a232 + v_accvgpr_read_b32 v83, a233 + v_accvgpr_read_b32 v82, a234 + v_accvgpr_read_b32 v81, a235 + v_accvgpr_read_b32 v80, a236 + v_accvgpr_read_b32 v79, a237 + v_accvgpr_read_b32 v78, a238 + v_accvgpr_read_b32 v77, a239 + v_accvgpr_read_b32 v76, a208 + v_accvgpr_read_b32 v75, a209 + v_accvgpr_read_b32 v74, a210 + v_accvgpr_read_b32 v73, a211 + v_accvgpr_read_b32 v72, a212 + v_accvgpr_read_b32 v71, a213 + v_accvgpr_read_b32 v70, a214 + v_accvgpr_read_b32 v69, a215 + v_accvgpr_read_b32 v68, a216 + v_accvgpr_read_b32 v67, a217 + v_accvgpr_read_b32 v66, a218 + v_accvgpr_read_b32 v65, a219 + v_accvgpr_read_b32 v64, a220 + v_accvgpr_read_b32 v63, a221 + v_accvgpr_read_b32 v62, a222 + v_accvgpr_read_b32 v61, a223 + v_accvgpr_read_b32 v224, a176 + v_accvgpr_read_b32 v223, a177 + v_accvgpr_read_b32 v222, a178 + v_accvgpr_read_b32 v221, a179 + v_accvgpr_read_b32 v220, a180 + v_accvgpr_read_b32 v219, a181 + v_accvgpr_read_b32 v218, a182 + v_accvgpr_read_b32 v217, a183 + v_accvgpr_read_b32 v216, a184 + v_accvgpr_read_b32 v215, a185 + v_accvgpr_read_b32 v214, a186 + v_accvgpr_read_b32 v213, a187 + v_accvgpr_read_b32 v212, a188 + v_accvgpr_read_b32 v211, a189 + v_accvgpr_read_b32 v210, a190 + v_accvgpr_read_b32 v209, a191 + v_accvgpr_read_b32 v176, a160 + v_accvgpr_read_b32 v175, a161 + v_accvgpr_read_b32 v174, a162 + v_accvgpr_read_b32 v173, a163 + v_accvgpr_read_b32 v172, a164 + v_accvgpr_read_b32 v171, a165 + v_accvgpr_read_b32 v170, a166 + v_accvgpr_read_b32 v169, a167 + v_accvgpr_read_b32 v168, a168 + v_accvgpr_read_b32 v167, a169 + v_accvgpr_read_b32 v166, a170 + v_accvgpr_read_b32 v165, a171 + v_accvgpr_read_b32 v164, a172 + v_accvgpr_read_b32 v163, a173 + v_accvgpr_read_b32 v162, a174 + v_accvgpr_read_b32 v161, a175 + v_accvgpr_read_b32 v160, a144 + v_accvgpr_read_b32 v159, a145 + v_accvgpr_read_b32 v158, a146 + v_accvgpr_read_b32 v157, a147 + v_accvgpr_read_b32 v156, a148 + v_accvgpr_read_b32 v155, a149 + v_accvgpr_read_b32 v154, a150 + v_accvgpr_read_b32 v153, a151 + v_accvgpr_read_b32 v152, a152 + v_accvgpr_read_b32 v151, a153 + v_accvgpr_read_b32 v150, a154 + v_accvgpr_read_b32 v149, a155 + v_accvgpr_read_b32 v148, a156 + v_accvgpr_read_b32 v146, a157 + v_accvgpr_read_b32 v145, a158 + v_accvgpr_read_b32 v144, a159 + v_accvgpr_read_b32 v147, a128 + v_accvgpr_read_b32 v130, a129 + v_accvgpr_read_b32 v129, a130 + v_accvgpr_read_b32 v128, a131 + v_accvgpr_read_b32 v127, a132 + v_accvgpr_read_b32 v126, a133 + v_accvgpr_read_b32 v125, a134 + v_accvgpr_read_b32 v124, a135 + v_accvgpr_read_b32 v123, a136 + v_accvgpr_read_b32 v122, a137 + v_accvgpr_read_b32 v121, a138 + v_accvgpr_read_b32 v120, a139 + v_accvgpr_read_b32 v119, a140 + v_accvgpr_read_b32 v118, a141 + v_accvgpr_read_b32 v117, a142 + v_accvgpr_read_b32 v116, a143 + v_accvgpr_mov_b32 a15, a112 + v_accvgpr_mov_b32 a14, a113 + v_accvgpr_mov_b32 a13, a114 + v_accvgpr_mov_b32 a12, a115 + v_accvgpr_mov_b32 a11, a116 + v_accvgpr_mov_b32 a10, a117 + v_accvgpr_mov_b32 a9, a118 + v_accvgpr_mov_b32 a8, a119 + v_accvgpr_mov_b32 a7, a120 + v_accvgpr_mov_b32 a6, a121 + v_accvgpr_mov_b32 a5, a122 + v_accvgpr_mov_b32 a4, a123 + v_accvgpr_mov_b32 a3, a124 + v_accvgpr_mov_b32 a2, a125 + v_accvgpr_mov_b32 a1, a126 + v_accvgpr_mov_b32 a0, a127 + v_accvgpr_read_b32 v60, a96 + v_accvgpr_read_b32 v59, a97 + v_accvgpr_read_b32 v58, a98 + v_accvgpr_read_b32 v57, a99 + v_accvgpr_read_b32 v56, a100 + v_accvgpr_read_b32 v55, a101 + v_accvgpr_read_b32 v54, a102 + v_accvgpr_read_b32 v53, a103 + v_accvgpr_read_b32 v52, a104 + v_accvgpr_read_b32 v51, a105 + v_accvgpr_read_b32 v24, a106 + v_accvgpr_read_b32 v23, a107 + v_accvgpr_read_b32 v22, a108 + v_accvgpr_read_b32 v21, a109 + v_accvgpr_read_b32 v20, a110 + v_accvgpr_read_b32 v19, a111 + v_accvgpr_read_b32 v115, a80 + v_accvgpr_read_b32 v114, a81 + v_accvgpr_read_b32 v113, a82 + v_accvgpr_read_b32 v112, a83 + v_accvgpr_read_b32 v111, a84 + v_accvgpr_read_b32 v110, a85 + v_accvgpr_read_b32 v109, a86 + v_accvgpr_read_b32 v50, a87 + v_accvgpr_read_b32 v49, a88 + v_accvgpr_read_b32 v48, a89 + v_accvgpr_read_b32 v47, a90 + v_accvgpr_read_b32 v46, a91 + v_accvgpr_read_b32 v45, a92 + v_accvgpr_read_b32 v44, a93 + v_accvgpr_read_b32 v43, a94 + v_accvgpr_read_b32 v42, a95 + v_accvgpr_read_b32 v208, a64 + v_accvgpr_read_b32 v207, a65 + v_accvgpr_read_b32 v206, a66 + v_accvgpr_read_b32 v205, a67 + v_accvgpr_read_b32 v204, a68 + v_accvgpr_read_b32 v203, a69 + v_accvgpr_read_b32 v202, a70 + v_accvgpr_read_b32 v201, a71 + v_accvgpr_read_b32 v200, a72 + v_accvgpr_read_b32 v199, a73 + v_accvgpr_read_b32 v198, a74 + v_accvgpr_read_b32 v197, a75 + v_accvgpr_read_b32 v196, a76 + v_accvgpr_read_b32 v195, a77 + v_accvgpr_read_b32 v194, a78 + v_accvgpr_read_b32 v193, a79 + v_accvgpr_mov_b32 a71, a48 + v_accvgpr_mov_b32 a70, a49 + v_accvgpr_mov_b32 a69, a50 + v_accvgpr_mov_b32 a68, a51 + v_accvgpr_mov_b32 a67, a52 + v_accvgpr_mov_b32 a66, a53 + v_accvgpr_mov_b32 a65, a54 + v_accvgpr_mov_b32 a64, a55 + v_accvgpr_mov_b32 a55, a56 + v_accvgpr_mov_b32 a54, a57 + v_accvgpr_mov_b32 a53, a58 + v_accvgpr_mov_b32 a52, a59 + v_accvgpr_mov_b32 a51, a60 + v_accvgpr_mov_b32 a50, a61 + v_accvgpr_mov_b32 a49, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v41, a32 + v_accvgpr_read_b32 v40, a33 + v_accvgpr_read_b32 v39, a34 + v_accvgpr_read_b32 v38, a35 + v_accvgpr_read_b32 v37, a36 + v_accvgpr_read_b32 v36, a37 + v_accvgpr_read_b32 v35, a38 + v_accvgpr_read_b32 v33, a39 + v_accvgpr_read_b32 v32, a40 + v_accvgpr_read_b32 v31, a41 + v_accvgpr_read_b32 v30, a42 + v_accvgpr_read_b32 v29, a43 + v_accvgpr_read_b32 v28, a44 + v_accvgpr_read_b32 v27, a45 + v_accvgpr_read_b32 v26, a46 + v_accvgpr_read_b32 v25, a47 + v_accvgpr_read_b32 v192, a16 + v_accvgpr_read_b32 v191, a17 + v_accvgpr_read_b32 v190, a18 + v_accvgpr_read_b32 v189, a19 + v_accvgpr_read_b32 v188, a20 + v_accvgpr_read_b32 v187, a21 + v_accvgpr_read_b32 v186, a22 + v_accvgpr_read_b32 v185, a23 + v_accvgpr_read_b32 v184, a24 + v_accvgpr_read_b32 v183, a25 + v_accvgpr_read_b32 v182, a26 + v_accvgpr_read_b32 v181, a27 + v_accvgpr_read_b32 v180, a28 + v_accvgpr_read_b32 v179, a29 + v_accvgpr_read_b32 v178, a30 + v_accvgpr_read_b32 v177, a31 + v_accvgpr_read_b32 v2, a192 + v_accvgpr_read_b32 v3, a193 + v_accvgpr_read_b32 v4, a194 + v_accvgpr_read_b32 v5, a195 + v_accvgpr_read_b32 v6, a196 + v_accvgpr_read_b32 v7, a197 + v_accvgpr_read_b32 v8, a198 + v_accvgpr_read_b32 v9, a199 + v_accvgpr_read_b32 v10, a200 + v_accvgpr_read_b32 v11, a201 + v_accvgpr_read_b32 v12, a202 + v_accvgpr_read_b32 v13, a203 + v_accvgpr_read_b32 v14, a204 + v_accvgpr_read_b32 v15, a205 + v_accvgpr_read_b32 v16, a206 + v_accvgpr_read_b32 v17, a207 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v229, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v18, 3, v225 + v_and_b32_e32 v18, 12, v18 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v252, v143 + v_cvt_f16_f32_e32 v253, v142 + v_cvt_f16_f32_e32 v254, v141 + v_cvt_f16_f32_e32 v255, v140 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v34, v34 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v245, v139 + v_cvt_f16_f32_e32 v246, v138 + v_cvt_f16_f32_e32 v247, v137 + v_cvt_f16_f32_e32 v248, v136 + v_cvt_f16_f32_e32 v249, v135 + v_cvt_f16_f32_e32 v250, v134 + v_cvt_f16_f32_e32 v251, v133 + v_cvt_f16_f32_e32 v133, v132 + v_cvt_f16_f32_e32 v134, v131 + v_cvt_f16_f32_e32 v135, v224 + v_cvt_f16_f32_e32 v230, v223 + v_cvt_f16_f32_e32 v231, v222 + v_cvt_f16_f32_e32 v232, v221 + v_cvt_f16_f32_e32 v233, v220 + v_cvt_f16_f32_e32 v234, v219 + v_cvt_f16_f32_e32 v235, v218 + v_cvt_f16_f32_e32 v236, v217 + v_cvt_f16_f32_e32 v237, v216 + v_cvt_f16_f32_e32 v238, v215 + v_cvt_f16_f32_e32 v239, v214 + v_cvt_f16_f32_e32 v240, v213 + v_cvt_f16_f32_e32 v241, v212 + v_cvt_f16_f32_e32 v242, v211 + v_cvt_f16_f32_e32 v243, v210 + v_cvt_f16_f32_e32 v244, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v108, v108 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v209, v94 + v_cvt_f16_f32_e32 v210, v93 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v131, v162 + v_cvt_f16_f32_e32 v132, v161 + v_cvt_f16_f32_e32 v163, v92 + v_cvt_f16_f32_e32 v164, v91 + v_cvt_f16_f32_e32 v165, v90 + v_cvt_f16_f32_e32 v166, v89 + v_cvt_f16_f32_e32 v167, v88 + v_cvt_f16_f32_e32 v168, v87 + v_cvt_f16_f32_e32 v169, v86 + v_cvt_f16_f32_e32 v170, v85 + v_cvt_f16_f32_e32 v171, v84 + v_cvt_f16_f32_e32 v172, v83 + v_cvt_f16_f32_e32 v173, v82 + v_cvt_f16_f32_e32 v174, v81 + v_cvt_f16_f32_e32 v175, v80 + v_cvt_f16_f32_e32 v176, v79 + v_cvt_f16_f32_e32 v78, v78 + v_cvt_f16_f32_e32 v77, v77 + v_cvt_f16_f32_e32 v79, v160 + v_cvt_f16_f32_e32 v80, v159 + v_cvt_f16_f32_e32 v81, v158 + v_cvt_f16_f32_e32 v82, v157 + v_cvt_f16_f32_e32 v83, v156 + v_cvt_f16_f32_e32 v84, v155 + v_cvt_f16_f32_e32 v85, v154 + v_cvt_f16_f32_e32 v86, v153 + v_cvt_f16_f32_e32 v87, v152 + v_cvt_f16_f32_e32 v88, v151 + v_cvt_f16_f32_e32 v89, v150 + v_cvt_f16_f32_e32 v90, v149 + v_cvt_f16_f32_e32 v91, v148 + v_cvt_f16_f32_e32 v92, v146 + v_cvt_f16_f32_e32 v93, v145 + v_cvt_f16_f32_e32 v94, v144 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v136, v71 + v_cvt_f16_f32_e32 v137, v70 + v_cvt_f16_f32_e32 v138, v69 + v_cvt_f16_f32_e32 v139, v68 + v_cvt_f16_f32_e32 v140, v67 + v_cvt_f16_f32_e32 v141, v66 + v_cvt_f16_f32_e32 v142, v65 + v_cvt_f16_f32_e32 v143, v64 + v_cvt_f16_f32_e32 v144, v63 + v_cvt_f16_f32_e32 v145, v62 + v_cvt_f16_f32_e32 v146, v61 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v130 + v_cvt_f16_f32_e32 v149, v129 + v_cvt_f16_f32_e32 v150, v128 + v_cvt_f16_f32_e32 v151, v127 + v_cvt_f16_f32_e32 v152, v126 + v_cvt_f16_f32_e32 v153, v125 + v_cvt_f16_f32_e32 v154, v124 + v_cvt_f16_f32_e32 v155, v123 + v_cvt_f16_f32_e32 v156, v122 + v_cvt_f16_f32_e32 v157, v121 + v_cvt_f16_f32_e32 v158, v120 + v_cvt_f16_f32_e32 v159, v119 + v_cvt_f16_f32_e32 v160, v118 + v_cvt_f16_f32_e32 v161, v117 + v_cvt_f16_f32_e32 v162, v116 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v61, v207 + v_accvgpr_write_b32 a16, v61 + v_cvt_f16_f32_e32 v61, v206 + v_accvgpr_write_b32 a17, v61 + v_cvt_f16_f32_e32 v61, v205 + v_accvgpr_write_b32 a18, v61 + v_cvt_f16_f32_e32 v61, v204 + v_accvgpr_write_b32 a19, v61 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v116, v3 + v_cvt_f16_f32_e32 v117, v4 + v_cvt_f16_f32_e32 v118, v5 + v_cvt_f16_f32_e32 v119, v6 + v_cvt_f16_f32_e32 v120, v7 + v_cvt_f16_f32_e32 v121, v8 + v_cvt_f16_f32_e32 v122, v9 + v_cvt_f16_f32_e32 v123, v10 + v_cvt_f16_f32_e32 v124, v11 + v_cvt_f16_f32_e32 v125, v12 + v_cvt_f16_f32_e32 v126, v13 + v_cvt_f16_f32_e32 v127, v14 + v_cvt_f16_f32_e32 v128, v15 + v_cvt_f16_f32_e32 v129, v16 + v_cvt_f16_f32_e32 v130, v17 + v_cvt_f16_f32_e32 v193, v115 + v_cvt_f16_f32_e32 v194, v114 + v_cvt_f16_f32_e32 v195, v113 + v_cvt_f16_f32_e32 v196, v112 + v_cvt_f16_f32_e32 v197, v111 + v_cvt_f16_f32_e32 v198, v110 + v_cvt_f16_f32_e32 v199, v109 + v_cvt_f16_f32_e32 v200, v50 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v50, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v114, v185 + v_cvt_f16_f32_e32 v115, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v24 + v_cvt_f16_f32_e32 v13, v23 + v_cvt_f16_f32_e32 v14, v22 + v_cvt_f16_f32_e32 v15, v21 + v_cvt_f16_f32_e32 v16, v20 + v_cvt_f16_f32_e32 v17, v19 + v_cvt_f16_f32_e32 v51, v41 + v_cvt_f16_f32_e32 v52, v40 + v_cvt_f16_f32_e32 v53, v39 + v_cvt_f16_f32_e32 v54, v38 + v_cvt_f16_f32_e32 v55, v37 + v_cvt_f16_f32_e32 v56, v36 + v_cvt_f16_f32_e32 v57, v35 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_cvt_f16_f32_e32 v25, v25 + v_lshlrev_b32_e32 v21, 1, v226 + v_lshlrev_b32_e32 v20, 1, v229 + v_lshrrev_b32_e32 v19, 1, v225 + s_cbranch_scc1 .LBB23_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB23_14 +.LBB23_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEESB_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB23_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v22, s5, v18 + v_lshl_or_b32 v22, v22, 7, v21 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v22, v20, s2 + ds_write_b16 v22, v252 + ds_write_b16 v22, v253 offset:128 + ds_write_b16 v22, v254 offset:256 + ds_write_b16 v22, v255 offset:384 + ds_write_b16 v22, v1 offset:1024 + ds_write_b16 v22, v34 offset:1152 + ds_write_b16 v22, v0 offset:1280 + ds_write_b16 v22, v245 offset:1408 + ds_write_b16 v22, v246 offset:2048 + ds_write_b16 v22, v247 offset:2176 + ds_write_b16 v22, v248 offset:2304 + ds_write_b16 v22, v249 offset:2432 + ds_write_b16 v22, v250 offset:3072 + ds_write_b16 v22, v251 offset:3200 + ds_write_b16 v22, v133 offset:3328 + ds_write_b16 v22, v134 offset:3456 + ds_write_b16 v22, v135 offset:8192 + ds_write_b16 v22, v230 offset:8320 + ds_write_b16 v22, v231 offset:8448 + ds_write_b16 v22, v232 offset:8576 + ds_write_b16 v22, v233 offset:9216 + ds_write_b16 v22, v234 offset:9344 + ds_write_b16 v22, v235 offset:9472 + ds_write_b16 v22, v236 offset:9600 + ds_write_b16 v22, v237 offset:10240 + ds_write_b16 v22, v238 offset:10368 + ds_write_b16 v22, v239 offset:10496 + ds_write_b16 v22, v240 offset:10624 + ds_write_b16 v22, v241 offset:11264 + ds_write_b16 v22, v242 offset:11392 + ds_write_b16 v22, v243 offset:11520 + ds_write_b16 v22, v244 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v23, 60, v19 + v_add_u32_e32 v24, s2, v23 + v_and_b32_e32 v31, 56, v228 + v_lshlrev_b32_e32 v23, 7, v24 + v_lshl_or_b32 v23, v31, 1, v23 + v_add_u32_e32 v32, s20, v24 + v_or_b32_e32 v24, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v32, s16 + v_add_u32_e32 v33, v31, v24 + v_lshlrev_b32_e32 v35, 1, v33 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v35, s[0:3], 12 offen + v_add_u32_e32 v33, s16, v33 + v_lshlrev_b32_e32 v35, 1, v33 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v35, s[0:3], 12 offen + v_add_u32_e32 v33, s16, v33 + v_lshlrev_b32_e32 v35, 1, v33 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v35, s[0:3], 12 offen + v_add_lshl_u32 v33, v33, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v33, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v108 + ds_write_b16 v22, v107 offset:128 + ds_write_b16 v22, v106 offset:256 + ds_write_b16 v22, v105 offset:384 + ds_write_b16 v22, v104 offset:1024 + ds_write_b16 v22, v103 offset:1152 + ds_write_b16 v22, v102 offset:1280 + ds_write_b16 v22, v101 offset:1408 + ds_write_b16 v22, v100 offset:2048 + ds_write_b16 v22, v99 offset:2176 + ds_write_b16 v22, v98 offset:2304 + ds_write_b16 v22, v97 offset:2432 + ds_write_b16 v22, v96 offset:3072 + ds_write_b16 v22, v95 offset:3200 + ds_write_b16 v22, v209 offset:3328 + ds_write_b16 v22, v210 offset:3456 + ds_write_b16 v22, v211 offset:8192 + ds_write_b16 v22, v212 offset:8320 + ds_write_b16 v22, v213 offset:8448 + ds_write_b16 v22, v214 offset:8576 + ds_write_b16 v22, v215 offset:9216 + ds_write_b16 v22, v216 offset:9344 + ds_write_b16 v22, v217 offset:9472 + ds_write_b16 v22, v218 offset:9600 + ds_write_b16 v22, v219 offset:10240 + ds_write_b16 v22, v220 offset:10368 + ds_write_b16 v22, v221 offset:10496 + ds_write_b16 v22, v222 offset:10624 + ds_write_b16 v22, v223 offset:11264 + ds_write_b16 v22, v224 offset:11392 + ds_write_b16 v22, v131 offset:11520 + ds_write_b16 v22, v132 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v33, 64, v24 + v_add_u32_e32 v35, v31, v33 + v_lshlrev_b32_e32 v40, 1, v35 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v40, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v40, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v40, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v40, s[0:3], 12 offen + v_add_u32_e32 v35, s16, v35 + v_lshlrev_b32_e32 v36, 1, v35 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v35, s16, v35 + v_lshlrev_b32_e32 v36, 1, v35 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v35, v35, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v35, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v163 + ds_write_b16 v22, v164 offset:128 + ds_write_b16 v22, v165 offset:256 + ds_write_b16 v22, v166 offset:384 + ds_write_b16 v22, v167 offset:1024 + ds_write_b16 v22, v168 offset:1152 + ds_write_b16 v22, v169 offset:1280 + ds_write_b16 v22, v170 offset:1408 + ds_write_b16 v22, v171 offset:2048 + ds_write_b16 v22, v172 offset:2176 + ds_write_b16 v22, v173 offset:2304 + ds_write_b16 v22, v174 offset:2432 + ds_write_b16 v22, v175 offset:3072 + ds_write_b16 v22, v176 offset:3200 + ds_write_b16 v22, v78 offset:3328 + ds_write_b16 v22, v77 offset:3456 + ds_write_b16 v22, v79 offset:8192 + ds_write_b16 v22, v80 offset:8320 + ds_write_b16 v22, v81 offset:8448 + ds_write_b16 v22, v82 offset:8576 + ds_write_b16 v22, v83 offset:9216 + ds_write_b16 v22, v84 offset:9344 + ds_write_b16 v22, v85 offset:9472 + ds_write_b16 v22, v86 offset:9600 + ds_write_b16 v22, v87 offset:10240 + ds_write_b16 v22, v88 offset:10368 + ds_write_b16 v22, v89 offset:10496 + ds_write_b16 v22, v90 offset:10624 + ds_write_b16 v22, v91 offset:11264 + ds_write_b16 v22, v92 offset:11392 + ds_write_b16 v22, v93 offset:11520 + ds_write_b16 v22, v94 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v35, 0x80, v24 + v_add_u32_e32 v40, v31, v35 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v41, s[0:3], 12 offen + v_add_u32_e32 v36, s16, v40 + v_lshlrev_b32_e32 v37, 1, v36 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v37, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v37, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v37, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v37, s[0:3], 12 offen + v_add_u32_e32 v36, s16, v36 + v_lshlrev_b32_e32 v37, 1, v36 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v37, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v37, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v37, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v37, s[0:3], 12 offen + v_add_lshl_u32 v36, v36, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v36, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v76 + ds_write_b16 v22, v75 offset:128 + ds_write_b16 v22, v74 offset:256 + ds_write_b16 v22, v73 offset:384 + ds_write_b16 v22, v72 offset:1024 + ds_write_b16 v22, v136 offset:1152 + ds_write_b16 v22, v137 offset:1280 + ds_write_b16 v22, v138 offset:1408 + ds_write_b16 v22, v139 offset:2048 + ds_write_b16 v22, v140 offset:2176 + ds_write_b16 v22, v141 offset:2304 + ds_write_b16 v22, v142 offset:2432 + ds_write_b16 v22, v143 offset:3072 + ds_write_b16 v22, v144 offset:3200 + ds_write_b16 v22, v145 offset:3328 + ds_write_b16 v22, v146 offset:3456 + ds_write_b16 v22, v147 offset:8192 + ds_write_b16 v22, v148 offset:8320 + ds_write_b16 v22, v149 offset:8448 + ds_write_b16 v22, v150 offset:8576 + ds_write_b16 v22, v151 offset:9216 + ds_write_b16 v22, v152 offset:9344 + ds_write_b16 v22, v153 offset:9472 + ds_write_b16 v22, v154 offset:9600 + ds_write_b16 v22, v155 offset:10240 + ds_write_b16 v22, v156 offset:10368 + ds_write_b16 v22, v157 offset:10496 + ds_write_b16 v22, v158 offset:10624 + ds_write_b16 v22, v159 offset:11264 + ds_write_b16 v22, v160 offset:11392 + ds_write_b16 v22, v161 offset:11520 + ds_write_b16 v22, v162 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v40, 0xc0, v24 + v_add_u32_e32 v31, v31, v40 + v_lshlrev_b32_e32 v41, 1, v31 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v41, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v36, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v36, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, a16 offset:128 + ds_write_b16 v22, a17 offset:256 + ds_write_b16 v22, a18 offset:384 + ds_write_b16 v22, a19 offset:1024 + ds_write_b16 v22, v71 offset:1152 + ds_write_b16 v22, v70 offset:1280 + ds_write_b16 v22, v69 offset:1408 + ds_write_b16 v22, v68 offset:2048 + ds_write_b16 v22, v67 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v116 offset:8320 + ds_write_b16 v22, v117 offset:8448 + ds_write_b16 v22, v118 offset:8576 + ds_write_b16 v22, v119 offset:9216 + ds_write_b16 v22, v120 offset:9344 + ds_write_b16 v22, v121 offset:9472 + ds_write_b16 v22, v122 offset:9600 + ds_write_b16 v22, v123 offset:10240 + ds_write_b16 v22, v124 offset:10368 + ds_write_b16 v22, v125 offset:10496 + ds_write_b16 v22, v126 offset:10624 + ds_write_b16 v22, v127 offset:11264 + ds_write_b16 v22, v128 offset:11392 + ds_write_b16 v22, v129 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v32 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v32, v31, v40 + v_lshlrev_b32_e32 v40, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v40, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v40, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v40, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v40, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v36, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v36, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v193 + ds_write_b16 v22, v194 offset:128 + ds_write_b16 v22, v195 offset:256 + ds_write_b16 v22, v196 offset:384 + ds_write_b16 v22, v197 offset:1024 + ds_write_b16 v22, v198 offset:1152 + ds_write_b16 v22, v199 offset:1280 + ds_write_b16 v22, v200 offset:1408 + ds_write_b16 v22, v201 offset:2048 + ds_write_b16 v22, v202 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v48 offset:3456 + ds_write_b16 v22, v49 offset:8192 + ds_write_b16 v22, v50 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v114 offset:9600 + ds_write_b16 v22, v115 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, v31, v35 + v_lshlrev_b32_e32 v35, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v35, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v35, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v35, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v35, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v35, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v51 offset:8192 + ds_write_b16 v22, v52 offset:8320 + ds_write_b16 v22, v53 offset:8448 + ds_write_b16 v22, v54 offset:8576 + ds_write_b16 v22, v55 offset:9216 + ds_write_b16 v22, v56 offset:9344 + ds_write_b16 v22, v57 offset:9472 + ds_write_b16 v22, v58 offset:9600 + ds_write_b16 v22, v59 offset:10240 + ds_write_b16 v22, v60 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, v31, v33 + v_lshlrev_b32_e32 v33, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3456 + v_accvgpr_read_b32 v32, a71 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8192 + v_accvgpr_read_b32 v32, a70 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8320 + v_accvgpr_read_b32 v32, a69 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8448 + v_accvgpr_read_b32 v32, a68 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8576 + v_accvgpr_read_b32 v32, a67 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9216 + v_accvgpr_read_b32 v32, a66 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9344 + v_accvgpr_read_b32 v32, a65 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9472 + v_accvgpr_read_b32 v32, a64 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9600 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10240 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10368 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10496 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10624 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11264 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11392 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11520 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11648 + v_add_u32_e32 v22, v31, v24 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v24, 1, v22 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v23, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v23, s[0:3], 12 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v22, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v22, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v22, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v22, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB23_12 +.LBB23_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v18, s5, v18 + s_barrier + v_lshl_or_b32 v18, v18, 7, v21 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v18, v20, s2 + ds_write_b16 v22, v252 + ds_write_b16 v22, v253 offset:128 + ds_write_b16 v22, v254 offset:256 + ds_write_b16 v22, v255 offset:384 + ds_write_b16 v22, v1 offset:1024 + ds_write_b16 v22, v34 offset:1152 + ds_write_b16 v22, v0 offset:1280 + ds_write_b16 v22, v245 offset:1408 + ds_write_b16 v22, v246 offset:2048 + ds_write_b16 v22, v247 offset:2176 + ds_write_b16 v22, v248 offset:2304 + ds_write_b16 v22, v249 offset:2432 + ds_write_b16 v22, v250 offset:3072 + ds_write_b16 v22, v251 offset:3200 + ds_write_b16 v22, v133 offset:3328 + ds_write_b16 v22, v134 offset:3456 + ds_write_b16 v22, v135 offset:8192 + ds_write_b16 v22, v230 offset:8320 + ds_write_b16 v22, v231 offset:8448 + ds_write_b16 v22, v232 offset:8576 + ds_write_b16 v22, v233 offset:9216 + ds_write_b16 v22, v234 offset:9344 + ds_write_b16 v22, v235 offset:9472 + ds_write_b16 v22, v236 offset:9600 + ds_write_b16 v22, v237 offset:10240 + ds_write_b16 v22, v238 offset:10368 + ds_write_b16 v22, v239 offset:10496 + ds_write_b16 v22, v240 offset:10624 + ds_write_b16 v22, v241 offset:11264 + ds_write_b16 v22, v242 offset:11392 + ds_write_b16 v22, v243 offset:11520 + ds_write_b16 v22, v244 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v228 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v19 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v23, v0, 1, v18 + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[184:187], v23 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v24, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v31, v0, v24 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v40, 1, v31 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v40, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v31 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[184:187], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v108 + ds_write_b16 v22, v107 offset:128 + ds_write_b16 v22, v106 offset:256 + ds_write_b16 v22, v105 offset:384 + ds_write_b16 v22, v104 offset:1024 + ds_write_b16 v22, v103 offset:1152 + ds_write_b16 v22, v102 offset:1280 + ds_write_b16 v22, v101 offset:1408 + ds_write_b16 v22, v100 offset:2048 + ds_write_b16 v22, v99 offset:2176 + ds_write_b16 v22, v98 offset:2304 + ds_write_b16 v22, v97 offset:2432 + ds_write_b16 v22, v96 offset:3072 + ds_write_b16 v22, v95 offset:3200 + ds_write_b16 v22, v209 offset:3328 + ds_write_b16 v22, v210 offset:3456 + ds_write_b16 v22, v211 offset:8192 + ds_write_b16 v22, v212 offset:8320 + ds_write_b16 v22, v213 offset:8448 + ds_write_b16 v22, v214 offset:8576 + ds_write_b16 v22, v215 offset:9216 + ds_write_b16 v22, v216 offset:9344 + ds_write_b16 v22, v217 offset:9472 + ds_write_b16 v22, v218 offset:9600 + ds_write_b16 v22, v219 offset:10240 + ds_write_b16 v22, v220 offset:10368 + ds_write_b16 v22, v221 offset:10496 + ds_write_b16 v22, v222 offset:10624 + ds_write_b16 v22, v223 offset:11264 + ds_write_b16 v22, v224 offset:11392 + ds_write_b16 v22, v131 offset:11520 + ds_write_b16 v22, v132 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[96:99], v23 offset:384 + v_or_b32_e32 v31, 64, v24 + v_add_u32_e32 v40, v0, v31 + v_lshlrev_b32_e32 v41, 1, v40 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v41, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v40 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[96:99], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v163 + ds_write_b16 v22, v164 offset:128 + ds_write_b16 v22, v165 offset:256 + ds_write_b16 v22, v166 offset:384 + ds_write_b16 v22, v167 offset:1024 + ds_write_b16 v22, v168 offset:1152 + ds_write_b16 v22, v169 offset:1280 + ds_write_b16 v22, v170 offset:1408 + ds_write_b16 v22, v171 offset:2048 + ds_write_b16 v22, v172 offset:2176 + ds_write_b16 v22, v173 offset:2304 + ds_write_b16 v22, v174 offset:2432 + ds_write_b16 v22, v175 offset:3072 + ds_write_b16 v22, v176 offset:3200 + ds_write_b16 v22, v78 offset:3328 + ds_write_b16 v22, v77 offset:3456 + ds_write_b16 v22, v79 offset:8192 + ds_write_b16 v22, v80 offset:8320 + ds_write_b16 v22, v81 offset:8448 + ds_write_b16 v22, v82 offset:8576 + ds_write_b16 v22, v83 offset:9216 + ds_write_b16 v22, v84 offset:9344 + ds_write_b16 v22, v85 offset:9472 + ds_write_b16 v22, v86 offset:9600 + ds_write_b16 v22, v87 offset:10240 + ds_write_b16 v22, v88 offset:10368 + ds_write_b16 v22, v89 offset:10496 + ds_write_b16 v22, v90 offset:10624 + ds_write_b16 v22, v91 offset:11264 + ds_write_b16 v22, v92 offset:11392 + ds_write_b16 v22, v93 offset:11520 + ds_write_b16 v22, v94 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[78:81], v23 offset:384 + v_or_b32_e32 v40, 0x80, v24 + v_add_u32_e32 v41, v0, v40 + v_lshlrev_b32_e32 v77, 1, v41 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v41 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v76 + ds_write_b16 v22, v75 offset:128 + ds_write_b16 v22, v74 offset:256 + ds_write_b16 v22, v73 offset:384 + ds_write_b16 v22, v72 offset:1024 + ds_write_b16 v22, v136 offset:1152 + ds_write_b16 v22, v137 offset:1280 + ds_write_b16 v22, v138 offset:1408 + ds_write_b16 v22, v139 offset:2048 + ds_write_b16 v22, v140 offset:2176 + ds_write_b16 v22, v141 offset:2304 + ds_write_b16 v22, v142 offset:2432 + ds_write_b16 v22, v143 offset:3072 + ds_write_b16 v22, v144 offset:3200 + ds_write_b16 v22, v145 offset:3328 + ds_write_b16 v22, v146 offset:3456 + ds_write_b16 v22, v147 offset:8192 + ds_write_b16 v22, v148 offset:8320 + ds_write_b16 v22, v149 offset:8448 + ds_write_b16 v22, v150 offset:8576 + ds_write_b16 v22, v151 offset:9216 + ds_write_b16 v22, v152 offset:9344 + ds_write_b16 v22, v153 offset:9472 + ds_write_b16 v22, v154 offset:9600 + ds_write_b16 v22, v155 offset:10240 + ds_write_b16 v22, v156 offset:10368 + ds_write_b16 v22, v157 offset:10496 + ds_write_b16 v22, v158 offset:10624 + ds_write_b16 v22, v159 offset:11264 + ds_write_b16 v22, v160 offset:11392 + ds_write_b16 v22, v161 offset:11520 + ds_write_b16 v22, v162 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[78:81], v23 offset:384 + v_or_b32_e32 v41, 0xc0, v24 + v_add_u32_e32 v0, v0, v41 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, a16 offset:128 + ds_write_b16 v22, a17 offset:256 + ds_write_b16 v22, a18 offset:384 + ds_write_b16 v22, a19 offset:1024 + ds_write_b16 v22, v71 offset:1152 + ds_write_b16 v22, v70 offset:1280 + ds_write_b16 v22, v69 offset:1408 + ds_write_b16 v22, v68 offset:2048 + ds_write_b16 v22, v67 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v116 offset:8320 + ds_write_b16 v22, v117 offset:8448 + ds_write_b16 v22, v118 offset:8576 + ds_write_b16 v22, v119 offset:9216 + ds_write_b16 v22, v120 offset:9344 + ds_write_b16 v22, v121 offset:9472 + ds_write_b16 v22, v122 offset:9600 + ds_write_b16 v22, v123 offset:10240 + ds_write_b16 v22, v124 offset:10368 + ds_write_b16 v22, v125 offset:10496 + ds_write_b16 v22, v126 offset:10624 + ds_write_b16 v22, v127 offset:11264 + ds_write_b16 v22, v128 offset:11392 + ds_write_b16 v22, v129 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[62:65], v23 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v41 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v193 + ds_write_b16 v22, v194 offset:128 + ds_write_b16 v22, v195 offset:256 + ds_write_b16 v22, v196 offset:384 + ds_write_b16 v22, v197 offset:1024 + ds_write_b16 v22, v198 offset:1152 + ds_write_b16 v22, v199 offset:1280 + ds_write_b16 v22, v200 offset:1408 + ds_write_b16 v22, v201 offset:2048 + ds_write_b16 v22, v202 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v48 offset:3456 + ds_write_b16 v22, v49 offset:8192 + ds_write_b16 v22, v50 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v114 offset:9600 + ds_write_b16 v22, v115 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[44:47], v23 offset:384 + v_add_u32_e32 v0, v61, v40 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[44:47], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v51 offset:8192 + ds_write_b16 v22, v52 offset:8320 + ds_write_b16 v22, v53 offset:8448 + ds_write_b16 v22, v54 offset:8576 + ds_write_b16 v22, v55 offset:9216 + ds_write_b16 v22, v56 offset:9344 + ds_write_b16 v22, v57 offset:9472 + ds_write_b16 v22, v58 offset:9600 + ds_write_b16 v22, v59 offset:10240 + ds_write_b16 v22, v60 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v61, v31 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a71 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a70 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a69 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a68 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a67 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a66 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v25, a65 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a64 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a55 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a54 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a53 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a52 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a51 + v_cvt_f16_f32_e32 v31, v31 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + v_accvgpr_read_b32 v33, a49 + v_cvt_f16_f32_e32 v33, v33 + v_accvgpr_read_b32 v34, a48 + v_cvt_f16_f32_e32 v34, v34 + ds_write_b16 v22, v0 + ds_write_b16 v22, v1 offset:128 + ds_write_b16 v22, v2 offset:256 + ds_write_b16 v22, v3 offset:384 + ds_write_b16 v22, v4 offset:1024 + ds_write_b16 v22, v5 offset:1152 + ds_write_b16 v22, v6 offset:1280 + ds_write_b16 v22, v7 offset:1408 + ds_write_b16 v22, v8 offset:2048 + ds_write_b16 v22, v9 offset:2176 + ds_write_b16 v22, v10 offset:2304 + ds_write_b16 v22, v11 offset:2432 + ds_write_b16 v22, v12 offset:3072 + ds_write_b16 v22, v13 offset:3200 + ds_write_b16 v22, v14 offset:3328 + ds_write_b16 v22, v15 offset:3456 + ds_write_b16 v22, v16 offset:8192 + ds_write_b16 v22, v17 offset:8320 + ds_write_b16 v22, v18 offset:8448 + ds_write_b16 v22, v19 offset:8576 + ds_write_b16 v22, v20 offset:9216 + ds_write_b16 v22, v21 offset:9344 + ds_write_b16 v22, v25 offset:9472 + ds_write_b16 v22, v26 offset:9600 + ds_write_b16 v22, v27 offset:10240 + ds_write_b16 v22, v28 offset:10368 + ds_write_b16 v22, v29 offset:10496 + ds_write_b16 v22, v30 offset:10624 + ds_write_b16 v22, v31 offset:11264 + ds_write_b16 v22, v32 offset:11392 + ds_write_b16 v22, v33 offset:11520 + ds_write_b16 v22, v34 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v61, v24 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end23: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end23-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 29 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDB8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 29728 +; TotalNumSgprs: 35 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB24_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB24_5 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v2, v6, s7 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[2:3], s[8:9], 0, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v0 +.LBB24_3: ; =>This Inner Loop Header: Depth=1 + global_load_ubyte v7, v[2:3], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_fp8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_fp8_sdwa v5, v5 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v7, v5 + s_cbranch_scc0 .LBB24_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB24_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB24_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end24: + .size _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end24-_ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDB8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 440 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s12, s10, s15 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s22, s3 + s_add_u32 s2, s2, s3 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v2, -1, 0 + s_cbranch_scc0 .LBB25_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v2 + s_lshr_b32 s19, s15, 2 + v_and_b32_e32 v25, 15, v225 + s_and_b32 s11, s19, 0x3ffffff0 + v_lshrrev_b32_e32 v0, 2, v225 + v_and_b32_e32 v1, 28, v0 + v_lshl_or_b32 v0, v25, 4, s20 + v_add_u32_e32 v28, s11, v1 + v_mad_u64_u32 v[0:1], s[24:25], v28, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[8:11], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[12:15], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[16:19], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[20:23], v0, s[8:11], 0 offen + s_mov_b32 s23, 0x3020504 + s_mov_b32 s26, 0x5010400 + s_mov_b32 s27, 0x5040100 + s_mov_b32 s28, 0x7060302 + s_mov_b32 s29, 0x7030602 + v_and_b32_e32 v1, 31, v225 + v_lshrrev_b32_e32 v29, 5, v225 + v_lshlrev_b32_e32 v0, 4, v225 + s_and_b32 s24, s15, 0xffffffc0 + v_and_b32_e32 v3, 0x7c, v225 + s_lshr_b32 s25, s15, 1 + v_lshlrev_b32_e32 v4, 3, v225 + s_mov_b32 s15, s11 + s_and_b32 s19, s19, 0x3fffffe0 + v_lshlrev_b32_e32 v30, 3, v29 + v_lshlrev_b32_e32 v6, 12, v29 + v_and_b32_e32 v24, 48, v0 + v_add_u32_e32 v31, s24, v3 + s_and_b32 s11, s25, 32 + v_and_or_b32 v5, v4, 8, v29 + v_or_b32_e32 v0, s19, v1 + v_lshl_or_b32 v32, v25, 7, v6 + v_add_u32_e32 v3, s21, v31 + v_or_b32_e32 v4, s11, v1 + v_lshrrev_b32_e32 v33, 4, v0 + v_mad_u64_u32 v[26:27], s[24:25], v3, s22, v[24:25] + v_lshrrev_b32_e32 v7, 1, v4 + v_bfe_u32 v4, v4, 1, 4 + v_xor_b32_e32 v27, v25, v33 + v_xor_b32_e32 v3, v4, v5 + v_lshlrev_b32_e32 v6, 7, v7 + v_add_u32_e32 v34, s22, v26 + buffer_load_dwordx4 v[38:41], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v34, s[12:15], 0 offen + v_add_u32_e32 v26, s22, v34 + v_add_u32_e32 v34, s22, v26 + buffer_load_dwordx4 v[46:49], v26, s[12:15], 0 offen + buffer_load_dwordx4 v[50:53], v34, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v8, v8, v8, s23 + v_perm_b32 v9, v9, v9, s23 + v_perm_b32 v10, v10, v10, s23 + v_perm_b32 v11, v11, v11, s23 + s_waitcnt vmcnt(6) + v_perm_b32 v12, v12, v12, s23 + v_perm_b32 v13, v13, v13, s23 + v_perm_b32 v14, v14, v14, s23 + v_perm_b32 v15, v15, v15, s23 + s_waitcnt vmcnt(5) + v_perm_b32 v16, v16, v16, s23 + v_perm_b32 v17, v17, v17, s23 + v_perm_b32 v18, v18, v18, s23 + v_perm_b32 v19, v19, v19, s23 + v_perm_b32 v26, v12, v8, s26 + v_perm_b32 v8, v12, v8, s29 + v_perm_b32 v12, v13, v9, s26 + v_perm_b32 v9, v13, v9, s29 + v_perm_b32 v13, v14, v10, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v20, v20, v20, s23 + v_perm_b32 v21, v21, v21, s23 + v_perm_b32 v22, v22, v22, s23 + v_perm_b32 v23, v23, v23, s23 + v_perm_b32 v34, v20, v16, s26 + v_perm_b32 v16, v20, v16, s29 + v_perm_b32 v20, v21, v17, s26 + v_perm_b32 v17, v21, v17, s29 + v_perm_b32 v21, v34, v26, s27 + v_perm_b32 v26, v34, v26, s28 + v_perm_b32 v34, v16, v8, s27 + v_perm_b32 v8, v16, v8, s28 + v_perm_b32 v16, v20, v12, s27 + v_perm_b32 v12, v20, v12, s28 + v_perm_b32 v20, v17, v9, s27 + v_perm_b32 v9, v17, v9, s28 + v_perm_b32 v17, v22, v18, s26 + v_perm_b32 v35, v17, v13, s27 + v_perm_b32 v13, v17, v13, s28 + v_perm_b32 v10, v14, v10, s29 + v_perm_b32 v14, v22, v18, s29 + v_perm_b32 v17, v14, v10, s27 + v_perm_b32 v10, v14, v10, s28 + v_perm_b32 v14, v15, v11, s26 + v_perm_b32 v18, v23, v19, s26 + v_perm_b32 v22, v18, v14, s27 + v_perm_b32 v14, v18, v14, s28 + v_perm_b32 v11, v15, v11, s29 + v_perm_b32 v15, v23, v19, s29 + v_perm_b32 v18, v15, v11, s27 + v_perm_b32 v11, v15, v11, s28 + v_lshrrev_b32_e32 v15, 1, v28 + v_and_b32_e32 v15, 16, v15 + v_xor_b32_e32 v19, v15, v1 + v_lshlrev_b32_e32 v23, 9, v28 + v_and_b32_e32 v23, 0x3000, v23 + v_lshlrev_b32_e32 v28, 6, v28 + s_movk_i32 s15, 0xf800 + v_and_b32_e32 v28, 0xfffff800, v28 + v_add_u32_e32 v23, v23, v28 + v_lshl_or_b32 v23, v19, 2, v23 + ds_write_b32 v23, v21 + v_or_b32_e32 v21, 1, v15 + v_xor_b32_e32 v21, v21, v1 + v_sub_u32_e32 v19, v21, v19 + v_lshl_add_u32 v19, v19, 2, v23 + ds_write_b32 v19, v26 offset:128 + v_or_b32_e32 v23, 2, v15 + v_xor_b32_e32 v23, v23, v1 + v_sub_u32_e32 v21, v23, v21 + v_mov_b32_e32 v26, 0x80 + v_lshl_add_u32 v21, v21, 2, v26 + v_or_b32_e32 v28, 3, v15 + v_xor_b32_e32 v28, v28, v1 + v_sub_u32_e32 v23, v28, v23 + v_lshl_add_u32 v23, v23, 2, v26 + v_add3_u32 v36, v19, v21, v23 + v_add3_u32 v19, v19, s18, v21 + ds_write_b32 v19, v34 + v_add_u32_e32 v19, v23, v19 + ds_write_b32 v19, v8 + v_or_b32_e32 v8, 4, v15 + v_xor_b32_e32 v8, v8, v1 + v_sub_u32_e32 v21, v8, v28 + v_lshl_add_u32 v21, v21, 2, v26 + v_or_b32_e32 v23, 5, v15 + v_xor_b32_e32 v23, v23, v1 + v_sub_u32_e32 v8, v23, v8 + v_lshl_add_u32 v8, v8, 2, v26 + v_add3_u32 v28, v36, v21, v8 + v_add_u32_e32 v19, v21, v19 + ds_write_b32 v19, v16 + v_add_u32_e32 v8, v8, v19 + ds_write_b32 v8, v12 + v_or_b32_e32 v12, 6, v15 + v_xor_b32_e32 v12, v12, v1 + v_sub_u32_e32 v16, v12, v23 + v_lshl_add_u32 v16, v16, 2, v26 + v_or_b32_e32 v19, 7, v15 + v_xor_b32_e32 v19, v19, v1 + v_sub_u32_e32 v12, v19, v12 + v_lshl_add_u32 v12, v12, 2, v26 + v_add3_u32 v21, v28, v16, v12 + v_add_u32_e32 v8, v16, v8 + ds_write_b32 v8, v20 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v9 + v_or_b32_e32 v9, 8, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v12, v9, v19 + v_lshl_add_u32 v12, v12, 2, v26 + v_or_b32_e32 v16, 9, v15 + v_xor_b32_e32 v16, v16, v1 + v_sub_u32_e32 v9, v16, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v19, v21, v12, v9 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v35 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v13 + v_or_b32_e32 v9, 10, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v12, v9, v16 + v_lshl_add_u32 v12, v12, 2, v26 + v_or_b32_e32 v13, 11, v15 + v_xor_b32_e32 v13, v13, v1 + v_sub_u32_e32 v9, v13, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v16, v19, v12, v9 + v_add_u32_e32 v8, v12, v8 + ds_write_b32 v8, v17 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v10 + v_or_b32_e32 v9, 12, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v10, v9, v13 + v_lshl_add_u32 v10, v10, 2, v26 + v_or_b32_e32 v12, 13, v15 + v_xor_b32_e32 v12, v12, v1 + v_sub_u32_e32 v9, v12, v9 + v_lshl_add_u32 v9, v9, 2, v26 + v_add3_u32 v13, v16, v10, v9 + v_add_u32_e32 v8, v10, v8 + ds_write_b32 v8, v22 + v_add_u32_e32 v8, v9, v8 + ds_write_b32 v8, v14 + v_or_b32_e32 v9, 14, v15 + v_xor_b32_e32 v9, v9, v1 + v_sub_u32_e32 v10, v9, v12 + v_lshlrev_b32_e32 v10, 2, v10 + v_or_b32_e32 v12, 15, v15 + v_xor_b32_e32 v1, v12, v1 + v_sub_u32_e32 v1, v1, v9 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v13, v10, v1 + v_add_u32_e32 v8, v8, v10 + ds_write_b32 v8, v18 offset:128 + ds_write_b32 v1, v11 offset:384 + v_lshrrev_b32_e32 v1, 3, v24 + v_ashrrev_i32_e32 v8, 1, v31 + v_ashrrev_i32_e32 v9, 31, v31 + v_lshrrev_b32_e32 v9, 28, v9 + v_add_u32_e32 v10, v8, v9 + v_and_b32_e32 v10, -16, v10 + v_sub_u32_e32 v10, v8, v10 + v_xor_b32_e32 v11, v10, v1 + v_lshlrev_b32_e32 v12, 6, v31 + v_lshl_add_u32 v11, v11, 3, v12 + s_waitcnt vmcnt(3) + ds_write_b64 v11, v[38:39] offset:16384 + v_or_b32_e32 v11, 1, v1 + v_xor_b32_e32 v10, v10, v11 + v_lshl_add_u32 v12, v10, 3, v12 + ds_write_b64 v12, v[40:41] offset:16384 + v_or_b32_e32 v13, 1, v31 + v_sub_u32_e32 v14, v1, v11 + v_lshrrev_b32_e32 v15, 31, v31 + v_add_u32_e32 v16, v13, v15 + v_ashrrev_i32_e32 v17, 1, v16 + v_sub_u32_e32 v18, v17, v8 + v_and_b32_e32 v19, 0x1ffffffe, v16 + v_sub_u32_e32 v13, v13, v19 + v_lshl_or_b32 v13, v13, 3, v11 + v_add_u32_e32 v19, v13, v14 + v_ashrrev_i32_e32 v16, 31, v16 + v_lshrrev_b32_e32 v16, 28, v16 + v_add_u32_e32 v16, v17, v16 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v16, v17, v16 + v_xor_b32_e32 v19, v19, v16 + v_sub_u32_e32 v19, v19, v10 + v_lshl_add_u32 v12, v18, 7, v12 + v_lshl_add_u32 v18, v19, 3, v12 + s_waitcnt vmcnt(2) + ds_write_b64 v18, v[42:43] offset:16384 + v_xor_b32_e32 v13, v13, v16 + v_sub_u32_e32 v10, v13, v10 + v_lshl_add_u32 v10, v10, 3, v12 + ds_write_b64 v10, v[44:45] offset:16384 + v_or_b32_e32 v8, 1, v8 + v_sub_u32_e32 v12, v8, v17 + v_add_u32_e32 v9, v8, v9 + v_and_b32_e32 v9, -16, v9 + v_sub_u32_e32 v9, v8, v9 + v_xor_b32_e32 v1, v9, v1 + v_sub_u32_e32 v13, v1, v13 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshlrev_b32_e32 v12, 7, v12 + v_add3_u32 v10, v13, v12, v10 + s_waitcnt vmcnt(1) + ds_write_b64 v10, v[46:47] offset:16384 + v_xor_b32_e32 v9, v9, v11 + v_sub_u32_e32 v1, v9, v1 + v_lshl_add_u32 v1, v1, 3, v10 + ds_write_b64 v1, v[48:49] offset:16384 + v_or_b32_e32 v10, 3, v31 + v_add_u32_e32 v12, v10, v15 + v_ashrrev_i32_e32 v13, 1, v12 + v_sub_u32_e32 v8, v13, v8 + v_and_b32_e32 v15, 0x1ffffffe, v12 + v_sub_u32_e32 v10, v10, v15 + v_lshl_or_b32 v10, v10, 3, v11 + v_add_u32_e32 v11, v10, v14 + v_ashrrev_i32_e32 v12, 31, v12 + v_lshrrev_b32_e32 v12, 28, v12 + v_add_u32_e32 v12, v13, v12 + v_and_b32_e32 v12, -16, v12 + v_sub_u32_e32 v12, v13, v12 + v_xor_b32_e32 v11, v11, v12 + v_sub_u32_e32 v9, v11, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_lshlrev_b32_e32 v8, 7, v8 + v_add3_u32 v1, v9, v8, v1 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[50:51] offset:16384 + v_xor_b32_e32 v8, v10, v12 + v_sub_u32_e32 v8, v8, v11 + v_lshl_add_u32 v1, v8, 3, v1 + ds_write_b64 v1, v[52:53] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v1, v27, 2, v32 + v_lshrrev_b16_e32 v9, 3, v30 + v_add_u32_e32 v10, 16, v33 + v_xor_b32_e32 v8, v25, v10 + v_sub_u32_e32 v11, v9, v29 + v_lshlrev_b32_e32 v11, 12, v11 + v_lshlrev_b32_e32 v12, 2, v8 + v_add3_u32 v11, v12, v32, v11 + v_add_u32_e32 v12, 16, v30 + v_lshrrev_b32_e32 v13, 5, v12 + v_lshrrev_b16_e32 v12, 3, v12 + v_and_b32_e32 v12, 3, v12 + v_sub_u16_e32 v14, v12, v9 + v_bfe_i32 v14, v14, 0, 16 + v_lshlrev_b32_e32 v15, 4, v13 + v_or_b32_e32 v16, v15, v25 + v_and_b32_e32 v16, 31, v16 + v_xor_b32_e32 v16, v16, v33 + v_sub_u32_e32 v8, v16, v8 + v_lshlrev_b32_e32 v17, 11, v13 + v_lshlrev_b32_e32 v8, 2, v8 + v_lshl_add_u32 v31, v14, 12, v17 + v_add3_u32 v14, v31, v11, v8 + v_add_u32_e32 v8, 20, v30 + v_lshrrev_b32_e32 v17, 5, v8 + v_sub_u32_e32 v13, v17, v13 + v_lshrrev_b16_e32 v8, 3, v8 + v_and_b32_e32 v8, 3, v8 + v_sub_u16_e32 v12, v8, v12 + v_bfe_i32 v12, v12, 0, 16 + v_lshlrev_b32_e32 v18, 4, v17 + v_or_b32_e32 v19, v18, v25 + v_and_b32_e32 v19, 31, v19 + v_xor_b32_e32 v19, v19, v10 + v_sub_u32_e32 v16, v19, v16 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v16, 2, v16 + v_lshl_add_u32 v32, v12, 12, v13 + v_add3_u32 v12, v16, v32, v14 + v_sub_u16_e32 v8, v9, v8 + v_bfe_i32 v8, v8, 0, 16 + v_or_b32_e32 v13, 16, v25 + v_xor_b32_e32 v16, v13, v33 + v_sub_u32_e32 v19, v16, v19 + v_lshlrev_b32_e32 v17, 11, v17 + v_xor_b32_e32 v17, 0x800, v17 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_add_u32 v34, v8, 12, v17 + v_add3_u32 v17, v19, v34, v12 + v_xor_b32_e32 v8, v13, v10 + v_sub_u32_e32 v13, v8, v16 + v_lshl_add_u32 v13, v13, 2, v17 + v_add_u32_e32 v16, 48, v30 + v_lshrrev_b32_e32 v19, 5, v16 + v_lshlrev_b32_e32 v20, 11, v19 + v_lshrrev_b16_e32 v16, 3, v16 + v_and_b32_e32 v16, 3, v16 + v_sub_u16_e32 v21, v16, v9 + v_lshlrev_b32_e32 v22, 4, v19 + v_or_b32_e32 v23, v22, v25 + v_and_b32_e32 v23, 31, v23 + v_xor_b32_e32 v23, v23, v33 + v_sub_u32_e32 v8, v23, v8 + v_lshlrev_b32_e32 v24, 2, v8 + v_mov_b32_e32 v26, 12 + v_lshlrev_b32_sdwa v8, v26, sext(v21) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v8, v20, v8, s15 + v_add3_u32 v20, v24, v8, v13 + v_add_u32_e32 v21, 52, v30 + v_lshrrev_b32_e32 v24, 5, v21 + v_sub_u32_e32 v19, v24, v19 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v16, v21, v16 + v_bfe_i32 v16, v16, 0, 16 + v_lshlrev_b32_e32 v27, 4, v24 + v_or_b32_e32 v25, v27, v25 + v_and_b32_e32 v30, 31, v25 + v_xor_b32_e32 v10, v30, v10 + v_sub_u32_e32 v23, v10, v23 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_add_u32 v33, v16, 12, v19 + v_add3_u32 v16, v23, v33, v20 + ds_read_b32 v52, v1 + ds_read_b32 v53, v11 + ds_read_b32 v72, v14 + ds_read_b32 v73, v12 + ds_read_b32 v74, v17 + ds_read_b32 v75, v13 + ds_read_b32 v76, v20 + ds_read_b32 v77, v16 + v_add_u32_e32 v1, 64, v0 + v_lshrrev_b32_e32 v1, 4, v1 + v_sub_u16_e32 v9, v9, v21 + v_sub_u32_e32 v11, v25, v27 + v_ashrrev_i32_e32 v12, 31, v11 + v_lshrrev_b32_e32 v12, 27, v12 + v_add_u32_e32 v12, v11, v12 + v_and_b32_e32 v12, 0xffffffe0, v12 + v_sub_u32_e32 v35, v11, v12 + v_xor_b32_e32 v12, v35, v1 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_lshlrev_b32_sdwa v9, v26, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v13, 11, v24 + v_sub_u32_e32 v9, v9, v13 + v_add3_u32 v10, v10, v9, v16 + v_add_u32_e32 v36, 16, v1 + v_xor_b32_e32 v13, v35, v36 + v_sub_u32_e32 v12, v13, v12 + v_lshl_add_u32 v12, v12, 2, v10 + v_add_u32_e32 v14, v11, v15 + v_ashrrev_i32_e32 v15, 31, v14 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v14, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v37, v14, v15 + v_xor_b32_e32 v14, v37, v1 + v_sub_u32_e32 v13, v14, v13 + v_lshl_add_u32 v13, v13, 2, v31 + v_add_u32_e32 v38, v13, v12 + v_add_u32_e32 v13, v11, v18 + v_ashrrev_i32_e32 v15, 31, v13 + v_lshrrev_b32_e32 v15, 27, v15 + v_add_u32_e32 v15, v13, v15 + v_and_b32_e32 v15, 0xffffffe0, v15 + v_sub_u32_e32 v39, v13, v15 + v_xor_b32_e32 v13, v39, v36 + v_sub_u32_e32 v14, v13, v14 + v_lshl_add_u32 v40, v14, 2, v32 + v_add_u32_e32 v14, v38, v40 + ds_read_b32 v62, v10 + ds_read_b32 v63, v12 + ds_read_b32 v78, v38 + ds_read_b32 v79, v14 + v_add_u32_e32 v10, 16, v11 + v_ashrrev_i32_e32 v12, 31, v10 + v_lshrrev_b32_e32 v12, 27, v12 + v_add_u32_e32 v12, v10, v12 + v_and_b32_e32 v12, 0xffffffe0, v12 + v_sub_u32_e32 v41, v10, v12 + v_xor_b32_e32 v10, v41, v1 + v_sub_u32_e32 v12, v10, v13 + v_lshl_add_u32 v42, v12, 2, v34 + v_add_u32_e32 v43, v14, v42 + v_xor_b32_e32 v44, v41, v36 + v_sub_u32_e32 v10, v44, v10 + v_lshlrev_b32_e32 v45, 2, v10 + v_add_u32_e32 v46, v43, v45 + v_add_u32_e32 v10, v11, v22 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshrrev_b32_e32 v11, 27, v11 + v_add_u32_e32 v11, v10, v11 + v_and_b32_e32 v11, 0xffffffe0, v11 + v_sub_u32_e32 v47, v10, v11 + v_xor_b32_e32 v1, v47, v1 + v_lshl_or_b32 v10, v3, 3, v6 + v_add_u32_e32 v16, 2, v5 + v_add_u32_e32 v11, -16, v7 + s_cmp_eq_u32 s11, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v7, v11, v7, vcc + v_xor_b32_e32 v11, v7, v16 + v_lshl_add_u32 v12, v11, 3, v6 + v_or_b32_e32 v17, 4, v5 + v_xor_b32_e32 v11, v7, v17 + v_lshl_add_u32 v14, v11, 3, v6 + ds_read_b64 v[10:11], v10 offset:16384 + ds_read_b64 v[12:13], v12 offset:16384 + ds_read_b64 v[14:15], v14 offset:16384 + v_add_u32_e32 v5, 6, v5 + v_xor_b32_e32 v7, v7, v5 + v_lshl_add_u32 v48, v7, 3, v6 + v_sub_u32_e32 v6, v3, v7 + v_lshl_add_u32 v20, v6, 3, v48 + v_xor_b32_e32 v6, v4, v16 + v_sub_u32_e32 v6, v6, v3 + v_lshlrev_b32_e32 v26, 3, v6 + v_add_u32_e32 v16, v20, v26 + v_xor_b32_e32 v6, v4, v17 + v_sub_u32_e32 v6, v6, v3 + v_lshlrev_b32_e32 v27, 3, v6 + v_add_u32_e32 v18, v20, v27 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[52:53], v[10:11], 0 + ds_read_b64 v[6:7], v20 offset:20480 + ds_read_b64 v[16:17], v16 offset:20480 + ds_read_b64 v[18:19], v18 offset:20480 + v_xor_b32_e32 v4, v4, v5 + v_sub_u32_e32 v5, v4, v3 + v_lshlrev_b32_e32 v49, 3, v5 + v_add_u32_e32 v50, v20, v49 + v_sub_u32_e32 v3, v3, v4 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[52:53], v[6:7], 0 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v24, v50, v3 + ds_read_b64 v[4:5], v24 offset:24576 + v_add_u32_e32 v20, v24, v26 + v_add_u32_e32 v22, v24, v27 + ds_read_b64 v[20:21], v20 offset:24576 + ds_read_b64 v[22:23], v22 offset:24576 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[52:53], v[4:5], 0 + v_add_u32_e32 v51, v24, v49 + v_add_u32_e32 v3, v51, v3 + ds_read_b64 v[24:25], v3 offset:28672 + v_add_u32_e32 v26, v3, v26 + v_add_u32_e32 v28, v3, v27 + ds_read_b64 v[26:27], v26 offset:28672 + ds_read_b64 v[28:29], v28 offset:28672 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[52:53], v[24:25], 0 + v_sub_u32_e32 v44, v1, v44 + v_lshl_add_u32 v44, v44, 2, v8 + v_add_u32_e32 v52, v46, v44 + v_xor_b32_e32 v36, v30, v36 + v_sub_u32_e32 v1, v36, v1 + v_lshl_add_u32 v53, v1, 2, v33 + v_add_u32_e32 v54, v52, v53 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[62:63], v[10:11], 0 + v_add_u32_e32 v1, 0x80, v0 + v_lshrrev_b32_e32 v1, 4, v1 + v_xor_b32_e32 v55, v35, v1 + v_sub_u32_e32 v36, v55, v36 + v_lshl_add_u32 v36, v36, 2, v9 + v_add_u32_e32 v56, v54, v36 + ds_read_b32 v80, v56 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[62:63], v[6:7], 0 + v_add_u32_e32 v57, 16, v1 + v_xor_b32_e32 v58, v35, v57 + v_sub_u32_e32 v55, v58, v55 + v_lshlrev_b32_e32 v55, 2, v55 + v_add_u32_e32 v56, v56, v55 + ds_read_b32 v81, v56 + v_xor_b32_e32 v59, v37, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[62:63], v[4:5], 0 + v_sub_u32_e32 v58, v59, v58 + v_lshl_add_u32 v58, v58, 2, v31 + v_add_u32_e32 v56, v56, v58 + v_xor_b32_e32 v60, v39, v57 + v_sub_u32_e32 v59, v60, v59 + v_lshl_add_u32 v59, v59, 2, v32 + v_add_u32_e32 v61, v56, v59 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[62:63], v[24:25], 0 + v_xor_b32_e32 v62, v41, v1 + v_sub_u32_e32 v60, v62, v60 + v_lshl_add_u32 v60, v60, 2, v34 + v_add_u32_e32 v63, v61, v60 + v_xor_b32_e32 v64, v41, v57 + v_sub_u32_e32 v62, v64, v62 + v_lshlrev_b32_e32 v62, 2, v62 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[80:81], v[10:11], 0 + v_add_u32_e32 v65, v63, v62 + v_xor_b32_e32 v1, v47, v1 + v_sub_u32_e32 v64, v1, v64 + v_lshl_add_u32 v64, v64, 2, v8 + v_add_u32_e32 v66, v65, v64 + v_xor_b32_e32 v57, v30, v57 + v_sub_u32_e32 v1, v57, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[80:81], v[6:7], 0 + v_lshl_add_u32 v67, v1, 2, v33 + v_add_u32_e32 v68, v66, v67 + v_add_u32_e32 v0, 0xc0, v0 + v_lshrrev_b32_e32 v69, 4, v0 + v_xor_b32_e32 v0, v35, v69 + v_sub_u32_e32 v1, v0, v57 + v_lshl_add_u32 v9, v1, 2, v9 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[80:81], v[4:5], 0 + v_add_u32_e32 v1, v68, v9 + ds_read_b32 v82, v1 + v_add_u32_e32 v57, 16, v69 + v_xor_b32_e32 v35, v35, v57 + v_sub_u32_e32 v0, v35, v0 + v_lshlrev_b32_e32 v70, 2, v0 + v_add_u32_e32 v0, v1, v70 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[80:81], v[24:25], 0 + ds_read_b32 v83, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[82:83], v[10:11], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[82:83], v[6:7], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[82:83], v[4:5], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[82:83], v[24:25], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[72:73], v[12:13], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[72:73], v[16:17], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[72:73], v[20:21], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[72:73], v[26:27], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[78:79], v[12:13], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[78:79], v[16:17], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[78:79], v[20:21], a[128:143] + ds_read_b32 v6, v56 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[78:79], v[26:27], a[112:127] + ds_read_b32 v7, v61 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[6:7], v[12:13], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[6:7], v[16:17], a[80:95] + v_xor_b32_e32 v1, v37, v69 + v_sub_u32_e32 v4, v1, v35 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[6:7], v[20:21], a[64:79] + v_lshl_add_u32 v24, v4, 2, v31 + v_add_u32_e32 v0, v0, v24 + ds_read_b32 v10, v0 + v_xor_b32_e32 v4, v39, v57 + v_sub_u32_e32 v1, v4, v1 + v_lshl_add_u32 v25, v1, 2, v32 + v_add_u32_e32 v0, v0, v25 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[6:7], v[26:27], a[48:63] + ds_read_b32 v11, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[10:11], v[12:13], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[10:11], v[16:17], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[10:11], v[20:21], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[10:11], v[26:27], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[74:75], v[14:15], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[74:75], v[18:19], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[74:75], v[22:23], a[192:207] + ds_read_b32 v6, v43 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[74:75], v[28:29], a[176:191] + ds_read_b32 v7, v46 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[6:7], v[14:15], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[6:7], v[18:19], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[6:7], v[22:23], a[128:143] + ds_read_b32 v10, v63 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[6:7], v[28:29], a[112:127] + ds_read_b32 v11, v65 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[10:11], v[14:15], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[10:11], v[18:19], a[80:95] + v_xor_b32_e32 v1, v41, v69 + v_sub_u32_e32 v4, v1, v4 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[10:11], v[22:23], a[64:79] + v_lshl_add_u32 v12, v4, 2, v34 + v_add_u32_e32 v0, v0, v12 + ds_read_b32 v4, v0 + v_xor_b32_e32 v13, v41, v57 + v_sub_u32_e32 v1, v13, v1 + v_lshlrev_b32_e32 v16, 2, v1 + v_add_u32_e32 v17, v0, v16 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[10:11], v[28:29], a[48:63] + ds_read_b32 v5, v17 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[4:5], v[14:15], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[4:5], v[18:19], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[4:5], v[22:23], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[4:5], v[28:29], a[240:255] + ds_read_b64 v[0:1], v48 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[76:77], v[0:1], a[224:239] + ds_read_b64 v[4:5], v50 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[76:77], v[4:5], a[208:223] + ds_read_b64 v[6:7], v51 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[76:77], v[6:7], a[192:207] + v_add_u32_e32 v3, v3, v49 + ds_read_b64 v[10:11], v3 offset:28672 + ds_read_b32 v14, v52 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[76:77], v[10:11], a[176:191] + ds_read_b32 v15, v54 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[14:15], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[14:15], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[14:15], v[6:7], a[128:143] + ds_read_b32 v18, v66 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[14:15], v[10:11], a[112:127] + ds_read_b32 v19, v68 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[18:19], v[0:1], a[96:111] + v_add3_u32 v3, v40, v38, v42 + v_add3_u32 v3, v45, v3, v44 + v_add3_u32 v3, v53, v3, v36 + v_add3_u32 v3, v3, v55, v58 + v_add3_u32 v3, v59, v3, v60 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[18:19], v[4:5], a[80:95] + v_add3_u32 v3, v62, v3, v64 + v_add3_u32 v3, v67, v3, v9 + v_add3_u32 v3, v3, v70, v24 + v_add3_u32 v3, v25, v3, v12 + v_xor_b32_e32 v9, v47, v69 + v_sub_u32_e32 v12, v9, v13 + v_lshl_add_u32 v8, v12, 2, v8 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[18:19], v[6:7], a[64:79] + v_add3_u32 v3, v16, v3, v8 + v_xor_b32_e32 v12, v30, v57 + v_sub_u32_e32 v9, v12, v9 + v_lshlrev_b32_e32 v9, 2, v9 + v_add3_u32 v3, v9, v33, v3 + ds_read_b32 v9, v3 + v_add_u32_e32 v3, v17, v8 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[18:19], v[10:11], a[48:63] + ds_read_b32 v8, v3 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[8:9], v[6:7], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[10:11], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB25_3 + s_branch .LBB25_10 +.LBB25_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr225 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB25_3: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v2 + v_and_b32_e32 v2, 15, v225 + s_lshr_b32 s23, s15, 2 + s_and_b32 s11, s23, 0x3ffffff0 + v_lshrrev_b32_e32 v1, 2, v225 + v_lshl_or_b32 v0, v2, 4, s20 + v_and_b32_e32 v83, 28, v1 + v_add_u32_e32 v1, s11, v83 + v_mad_u64_u32 v[18:19], s[18:19], v1, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v18 + buffer_load_dwordx4 v[14:17], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[22:25], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + s_mov_b32 s24, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s26, 0x5040100 + s_mov_b32 s27, 0x7060302 + s_mov_b32 s28, 0x7030602 + v_lshrrev_b32_e32 v8, 5, v225 + v_and_b32_e32 v84, 31, v225 + v_lshlrev_b32_e32 v0, 4, v225 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v85, 0x7c, v225 + s_lshr_b32 s19, s15, 1 + v_lshlrev_b32_e32 v3, 3, v225 + s_mov_b32 s15, s11 + s_and_b32 s23, s23, 0x3fffffe0 + v_lshlrev_b32_e32 v4, 12, v8 + v_lshlrev_b32_e32 v19, 3, v8 + v_and_b32_e32 v30, 48, v0 + v_add_u32_e32 v31, s18, v85 + v_and_or_b32 v0, s19, 32, v84 + v_and_or_b32 v32, v3, 8, v8 + v_or_b32_e32 v6, s23, v84 + v_lshl_or_b32 v9, v2, 7, v4 + v_add_u32_e32 v3, s21, v31 + v_lshrrev_b32_e32 v5, 1, v0 + v_bfe_u32 v4, v0, 1, 4 + v_lshrrev_b32_e32 v7, 4, v6 + v_mad_u64_u32 v[20:21], s[18:19], v3, s22, v[30:31] + v_xor_b32_e32 v3, v4, v32 + v_lshlrev_b32_e32 v5, 7, v5 + v_xor_b32_e32 v0, v2, v7 + v_add_u32_e32 v21, s22, v20 + buffer_load_dwordx4 v[36:39], v20, s[12:15], 0 offen + buffer_load_dwordx4 v[40:43], v21, s[12:15], 0 offen + v_add_u32_e32 v21, s22, v21 + v_add_u32_e32 v33, s22, v21 + buffer_load_dwordx4 v[44:47], v21, s[12:15], 0 offen + buffer_load_dwordx4 v[48:51], v33, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v10, v10, s24 + v_perm_b32 v11, v11, v11, s24 + v_perm_b32 v12, v12, v12, s24 + v_perm_b32 v13, v13, v13, s24 + s_waitcnt vmcnt(6) + v_perm_b32 v14, v14, v14, s24 + v_perm_b32 v15, v15, v15, s24 + v_perm_b32 v16, v16, v16, s24 + v_perm_b32 v17, v17, v17, s24 + s_waitcnt vmcnt(5) + v_perm_b32 v21, v22, v22, s24 + v_perm_b32 v22, v23, v23, s24 + v_perm_b32 v23, v24, v24, s24 + v_perm_b32 v24, v25, v25, s24 + v_perm_b32 v25, v14, v10, s25 + v_perm_b32 v10, v14, v10, s28 + v_perm_b32 v14, v15, v11, s25 + v_perm_b32 v11, v15, v11, s28 + v_perm_b32 v15, v16, v12, s25 + s_waitcnt vmcnt(4) + v_perm_b32 v26, v26, v26, s24 + v_perm_b32 v27, v27, v27, s24 + v_perm_b32 v28, v28, v28, s24 + v_perm_b32 v29, v29, v29, s24 + v_perm_b32 v33, v26, v21, s25 + v_perm_b32 v21, v26, v21, s28 + v_perm_b32 v26, v27, v22, s25 + v_perm_b32 v22, v27, v22, s28 + v_perm_b32 v27, v28, v23, s25 + v_perm_b32 v34, v33, v25, s26 + v_perm_b32 v25, v33, v25, s27 + v_perm_b32 v33, v21, v10, s26 + v_perm_b32 v10, v21, v10, s27 + v_perm_b32 v21, v26, v14, s26 + v_perm_b32 v14, v26, v14, s27 + v_perm_b32 v26, v22, v11, s26 + v_perm_b32 v11, v22, v11, s27 + v_perm_b32 v22, v27, v15, s26 + v_perm_b32 v15, v27, v15, s27 + v_perm_b32 v12, v16, v12, s28 + v_perm_b32 v16, v28, v23, s28 + v_perm_b32 v23, v16, v12, s26 + v_perm_b32 v12, v16, v12, s27 + v_perm_b32 v16, v17, v13, s25 + v_perm_b32 v27, v29, v24, s25 + v_perm_b32 v28, v27, v16, s26 + v_perm_b32 v16, v27, v16, s27 + v_perm_b32 v13, v17, v13, s28 + v_perm_b32 v17, v29, v24, s28 + v_perm_b32 v24, v17, v13, s26 + v_perm_b32 v13, v17, v13, s27 + v_lshrrev_b32_e32 v17, 1, v1 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v27, v17, v84 + v_lshlrev_b32_e32 v29, 9, v1 + v_and_b32_e32 v29, 0x3000, v29 + v_lshlrev_b32_e32 v1, 6, v1 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v1, 0xfffff800, v1 + v_add_u32_e32 v1, v29, v1 + v_lshl_or_b32 v1, v27, 2, v1 + ds_write_b32 v1, v34 + v_or_b32_e32 v29, 1, v17 + v_xor_b32_e32 v29, v29, v84 + v_sub_u32_e32 v27, v29, v27 + v_lshl_add_u32 v1, v27, 2, v1 + ds_write_b32 v1, v25 offset:128 + v_or_b32_e32 v25, 2, v17 + v_xor_b32_e32 v25, v25, v84 + v_sub_u32_e32 v27, v25, v29 + s_movk_i32 s19, 0x80 + v_mov_b32_e32 v29, 0x80 + v_lshl_add_u32 v27, v27, 2, v29 + v_or_b32_e32 v34, 3, v17 + v_xor_b32_e32 v34, v34, v84 + v_sub_u32_e32 v25, v34, v25 + v_lshl_add_u32 v25, v25, 2, v29 + v_add3_u32 v35, v1, v27, v25 + v_add3_u32 v1, v1, s19, v27 + ds_write_b32 v1, v33 + v_add_u32_e32 v1, v25, v1 + ds_write_b32 v1, v10 + v_or_b32_e32 v10, 4, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v25, v10, v34 + v_lshl_add_u32 v25, v25, 2, v29 + v_or_b32_e32 v27, 5, v17 + v_xor_b32_e32 v27, v27, v84 + v_sub_u32_e32 v10, v27, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v33, v35, v25, v10 + v_add_u32_e32 v1, v25, v1 + ds_write_b32 v1, v21 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v14 + v_or_b32_e32 v10, 6, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v14, v10, v27 + v_lshl_add_u32 v14, v14, 2, v29 + v_or_b32_e32 v21, 7, v17 + v_xor_b32_e32 v21, v21, v84 + v_sub_u32_e32 v10, v21, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v25, v33, v14, v10 + v_add_u32_e32 v1, v14, v1 + ds_write_b32 v1, v26 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v11 + v_or_b32_e32 v10, 8, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v21 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v14, 9, v17 + v_xor_b32_e32 v14, v14, v84 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v21, v25, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v22 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v15 + v_or_b32_e32 v10, 10, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v14, 11, v17 + v_xor_b32_e32 v14, v14, v84 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v15, v21, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v23 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v12 + v_or_b32_e32 v10, 12, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v29 + v_or_b32_e32 v12, 13, v17 + v_xor_b32_e32 v12, v12, v84 + v_sub_u32_e32 v10, v12, v10 + v_lshl_add_u32 v10, v10, 2, v29 + v_add3_u32 v14, v15, v11, v10 + v_add_u32_e32 v1, v11, v1 + ds_write_b32 v1, v28 + v_add_u32_e32 v1, v10, v1 + ds_write_b32 v1, v16 + v_or_b32_e32 v10, 14, v17 + v_xor_b32_e32 v10, v10, v84 + v_sub_u32_e32 v11, v10, v12 + v_lshlrev_b32_e32 v11, 2, v11 + v_or_b32_e32 v12, 15, v17 + v_xor_b32_e32 v12, v12, v84 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v14, v11, v10 + v_add_u32_e32 v1, v1, v11 + ds_write_b32 v1, v24 offset:128 + ds_write_b32 v10, v13 offset:384 + v_lshrrev_b32_e32 v86, 3, v30 + v_ashrrev_i32_e32 v1, 1, v31 + v_ashrrev_i32_e32 v10, 31, v31 + v_lshrrev_b32_e32 v10, 28, v10 + v_add_u32_e32 v11, v1, v10 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v1, v11 + v_xor_b32_e32 v12, v11, v86 + v_lshlrev_b32_e32 v13, 6, v31 + v_lshl_add_u32 v12, v12, 3, v13 + s_waitcnt vmcnt(3) + ds_write_b64 v12, v[36:37] offset:16384 + v_or_b32_e32 v87, 1, v86 + v_xor_b32_e32 v11, v11, v87 + v_lshl_add_u32 v12, v11, 3, v13 + ds_write_b64 v12, v[38:39] offset:16384 + v_or_b32_e32 v13, 1, v31 + v_sub_u32_e32 v88, v86, v87 + v_lshrrev_b32_e32 v14, 31, v31 + v_add_u32_e32 v15, v13, v14 + v_ashrrev_i32_e32 v16, 1, v15 + v_sub_u32_e32 v17, v16, v1 + v_and_b32_e32 v21, 0x1ffffffe, v15 + v_sub_u32_e32 v13, v13, v21 + v_lshl_or_b32 v13, v13, 3, v87 + v_add_u32_e32 v21, v13, v88 + v_ashrrev_i32_e32 v15, 31, v15 + v_lshrrev_b32_e32 v15, 28, v15 + v_add_u32_e32 v15, v16, v15 + v_and_b32_e32 v15, -16, v15 + v_sub_u32_e32 v15, v16, v15 + v_xor_b32_e32 v21, v21, v15 + v_sub_u32_e32 v21, v21, v11 + v_lshl_add_u32 v12, v17, 7, v12 + v_lshl_add_u32 v17, v21, 3, v12 + s_waitcnt vmcnt(2) + ds_write_b64 v17, v[40:41] offset:16384 + v_xor_b32_e32 v13, v13, v15 + v_sub_u32_e32 v11, v13, v11 + v_lshl_add_u32 v11, v11, 3, v12 + ds_write_b64 v11, v[42:43] offset:16384 + v_or_b32_e32 v1, 1, v1 + v_sub_u32_e32 v12, v1, v16 + v_add_u32_e32 v10, v1, v10 + v_and_b32_e32 v10, -16, v10 + v_sub_u32_e32 v10, v1, v10 + v_xor_b32_e32 v15, v10, v86 + v_sub_u32_e32 v13, v15, v13 + v_lshlrev_b32_e32 v13, 3, v13 + v_lshlrev_b32_e32 v12, 7, v12 + v_add3_u32 v11, v13, v12, v11 + s_waitcnt vmcnt(1) + ds_write_b64 v11, v[44:45] offset:16384 + v_xor_b32_e32 v10, v10, v87 + v_sub_u32_e32 v12, v10, v15 + v_lshl_add_u32 v11, v12, 3, v11 + ds_write_b64 v11, v[46:47] offset:16384 + v_or_b32_e32 v12, 3, v31 + v_add_u32_e32 v13, v12, v14 + v_ashrrev_i32_e32 v14, 1, v13 + v_sub_u32_e32 v1, v14, v1 + v_and_b32_e32 v15, 0x1ffffffe, v13 + v_sub_u32_e32 v12, v12, v15 + v_lshl_or_b32 v12, v12, 3, v87 + v_add_u32_e32 v15, v12, v88 + v_ashrrev_i32_e32 v13, 31, v13 + v_lshrrev_b32_e32 v13, 28, v13 + v_add_u32_e32 v13, v14, v13 + v_and_b32_e32 v13, -16, v13 + v_sub_u32_e32 v13, v14, v13 + v_xor_b32_e32 v14, v15, v13 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v1, v10, v1, v11 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[48:49] offset:16384 + v_xor_b32_e32 v10, v12, v13 + v_sub_u32_e32 v10, v10, v14 + v_lshl_add_u32 v1, v10, 3, v1 + ds_write_b64 v1, v[50:51] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v14, 3, v19 + v_add_u32_e32 v15, 16, v7 + v_add_u32_e32 v24, 16, v19 + v_add_u32_e32 v23, 20, v19 + v_or_b32_e32 v13, 16, v2 + v_add_u32_e32 v22, 36, v19 + v_add_u32_e32 v21, 48, v19 + v_add_u32_e32 v17, 52, v19 + v_add_u32_e32 v16, 64, v6 + v_add_u32_e32 v12, 2, v32 + v_add_u32_e32 v11, 4, v32 + v_add_u32_e32 v10, 6, v32 + s_cbranch_vccnz .LBB25_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit968.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v2, v15 + v_sub_u32_e32 v19, v14, v8 + v_lshlrev_b32_e32 v19, 12, v19 + v_lshlrev_b32_e32 v25, 2, v1 + v_add3_u32 v69, v25, v9, v19 + v_lshrrev_b32_e32 v19, 5, v24 + v_lshrrev_b16_e32 v25, 3, v24 + v_and_b32_e32 v25, 3, v25 + v_sub_u16_e32 v26, v25, v14 + v_bfe_i32 v26, v26, 0, 16 + v_lshl_or_b32 v27, v19, 4, v2 + v_xor_b32_e32 v28, v27, v7 + v_sub_u32_e32 v1, v28, v1 + v_lshlrev_b32_e32 v29, 11, v19 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_or_b32 v26, v26, 12, v29 + v_add3_u32 v41, v26, v69, v1 + v_lshrrev_b32_e32 v1, 5, v23 + v_sub_u32_e32 v19, v1, v19 + v_lshrrev_b16_e32 v29, 3, v23 + v_and_b32_e32 v29, 3, v29 + v_sub_u16_e32 v25, v29, v25 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v30, v1, 4, v2 + v_xor_b32_e32 v31, v30, v15 + v_sub_u32_e32 v28, v31, v28 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_add_u32 v25, v25, 12, v19 + v_add3_u32 v42, v28, v25, v41 + v_sub_u16_e32 v19, v14, v29 + v_bfe_i32 v19, v19, 0, 16 + v_xor_b32_e32 v28, v13, v7 + v_sub_u32_e32 v29, v28, v31 + v_lshlrev_b32_e32 v1, 11, v1 + v_xor_b32_e32 v1, 0x800, v1 + v_lshlrev_b32_e32 v29, 2, v29 + v_lshl_or_b32 v1, v19, 12, v1 + v_add3_u32 v36, v29, v1, v42 + v_lshrrev_b32_e32 v19, 5, v22 + v_lshlrev_b32_e32 v29, 11, v19 + v_lshrrev_b16_e32 v31, 3, v22 + v_and_b32_e32 v31, 3, v31 + v_sub_u16_e32 v32, v31, v14 + v_lshl_or_b32 v33, v19, 4, v2 + v_and_b32_e32 v33, 31, v33 + v_xor_b32_e32 v34, v33, v15 + v_sub_u32_e32 v28, v34, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_mov_b32_e32 v35, 12 + v_lshlrev_b32_sdwa v32, v35, sext(v32) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v29, v29, v32, s18 + v_add3_u32 v38, v28, v29, v36 + v_lshrrev_b32_e32 v28, 5, v21 + v_sub_u32_e32 v19, v28, v19 + v_lshrrev_b16_e32 v32, 3, v21 + v_and_b32_e32 v32, 3, v32 + v_sub_u16_e32 v31, v32, v31 + v_bfe_i32 v31, v31, 0, 16 + v_lshl_or_b32 v37, v28, 4, v2 + v_and_b32_e32 v45, 31, v37 + v_xor_b32_e32 v37, v45, v7 + v_sub_u32_e32 v34, v37, v34 + v_lshlrev_b32_e32 v19, 11, v19 + v_lshlrev_b32_e32 v34, 2, v34 + v_lshl_add_u32 v31, v31, 12, v19 + v_add3_u32 v19, v34, v31, v38 + v_lshrrev_b32_e32 v34, 5, v17 + v_sub_u32_e32 v28, v34, v28 + v_lshrrev_b16_e32 v39, 3, v17 + v_and_b32_e32 v39, 3, v39 + v_sub_u16_e32 v32, v39, v32 + v_bfe_i32 v32, v32, 0, 16 + v_lshl_or_b32 v40, v34, 4, v2 + v_and_b32_e32 v53, 31, v40 + v_xor_b32_e32 v40, v53, v15 + v_sub_u32_e32 v37, v40, v37 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v37, 2, v37 + v_lshl_add_u32 v28, v32, 12, v28 + v_add3_u32 v37, v37, v28, v19 + v_lshrrev_b32_e32 v32, 4, v16 + v_sub_u16_e32 v39, v14, v39 + v_xor_b32_e32 v43, v2, v32 + v_sub_u32_e32 v40, v43, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_lshlrev_b32_sdwa v35, v35, sext(v39) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v34, 11, v34 + v_sub_u32_e32 v34, v35, v34 + v_add3_u32 v72, v40, v34, v37 + v_add_u32_e32 v35, 16, v32 + v_xor_b32_e32 v39, v2, v35 + v_sub_u32_e32 v40, v39, v43 + v_lshl_add_u32 v73, v40, 2, v72 + v_xor_b32_e32 v40, v27, v32 + v_sub_u32_e32 v39, v40, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v49, v39, v26, v73 + v_xor_b32_e32 v39, v30, v35 + v_sub_u32_e32 v40, v39, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_add3_u32 v50, v40, v25, v49 + v_xor_b32_e32 v40, v13, v32 + v_sub_u32_e32 v39, v40, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v47, v39, v1, v50 + v_xor_b32_e32 v39, v33, v35 + v_sub_u32_e32 v40, v39, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_add3_u32 v48, v40, v29, v47 + v_xor_b32_e32 v32, v45, v32 + v_sub_u32_e32 v39, v32, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v39, v39, v31, v48 + v_xor_b32_e32 v35, v53, v35 + v_sub_u32_e32 v32, v35, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v40, v32, v28, v39 + v_add_u32_e32 v32, 0x80, v6 + v_lshrrev_b32_e32 v32, 4, v32 + v_xor_b32_e32 v43, v2, v32 + v_sub_u32_e32 v35, v43, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v74, v35, v34, v40 + v_add_u32_e32 v35, 16, v32 + v_xor_b32_e32 v44, v2, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshl_add_u32 v75, v43, 2, v74 + v_xor_b32_e32 v43, v27, v32 + v_sub_u32_e32 v44, v43, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v54, v44, v26, v75 + v_xor_b32_e32 v44, v30, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v55, v43, v25, v54 + v_xor_b32_e32 v43, v13, v32 + v_sub_u32_e32 v44, v43, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v51, v44, v1, v55 + v_xor_b32_e32 v44, v33, v35 + v_sub_u32_e32 v43, v44, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v52, v43, v29, v51 + v_xor_b32_e32 v32, v45, v32 + v_sub_u32_e32 v43, v32, v44 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v43, v43, v31, v52 + v_xor_b32_e32 v35, v53, v35 + v_sub_u32_e32 v32, v35, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v44, v32, v28, v43 + v_add_u32_e32 v32, 0xc0, v6 + v_lshrrev_b32_e32 v32, 4, v32 + v_xor_b32_e32 v46, v2, v32 + v_sub_u32_e32 v35, v46, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v76, v35, v34, v44 + v_add_u32_e32 v34, 16, v32 + v_xor_b32_e32 v35, v2, v34 + v_sub_u32_e32 v46, v35, v46 + v_lshl_add_u32 v77, v46, 2, v76 + v_xor_b32_e32 v27, v27, v32 + v_sub_u32_e32 v35, v27, v35 + v_lshlrev_b32_e32 v35, 2, v35 + v_add3_u32 v62, v35, v26, v77 + v_xor_b32_e32 v26, v30, v34 + v_sub_u32_e32 v27, v26, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v63, v27, v25, v62 + v_xor_b32_e32 v25, v13, v32 + v_sub_u32_e32 v26, v25, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v56, v26, v1, v63 + v_xor_b32_e32 v1, v33, v34 + v_sub_u32_e32 v25, v1, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v59, v25, v29, v56 + v_xor_b32_e32 v25, v45, v32 + v_sub_u32_e32 v1, v25, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v46, v1, v31, v59 + v_xor_b32_e32 v1, v53, v34 + v_sub_u32_e32 v1, v1, v25 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v45, v1, v28, v46 + v_xor_b32_e32 v1, v4, v12 + v_lshl_add_u32 v67, v1, 3, v5 + v_xor_b32_e32 v25, v4, v11 + v_lshl_add_u32 v61, v25, 3, v5 + v_xor_b32_e32 v26, v4, v10 + v_lshl_add_u32 v53, v26, 3, v5 + v_sub_u32_e32 v27, v3, v26 + v_mov_b32_e32 v28, 0x1000 + v_lshl_add_u32 v27, v27, 3, v28 + v_add_u32_e32 v80, v27, v53 + v_sub_u32_e32 v1, v1, v3 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v68, v80, v1 + v_sub_u32_e32 v25, v25, v3 + v_lshlrev_b32_e32 v25, 3, v25 + v_add_u32_e32 v64, v80, v25 + v_sub_u32_e32 v26, v26, v3 + v_lshlrev_b32_e32 v26, 3, v26 + v_add_u32_e32 v57, v80, v26 + v_add_u32_e32 v81, v57, v27 + v_add_u32_e32 v70, v81, v1 + v_add_u32_e32 v65, v81, v25 + v_add_u32_e32 v58, v81, v26 + v_add_u32_e32 v82, v58, v27 + v_add_u32_e32 v71, v82, v1 + v_add_u32_e32 v66, v82, v25 + v_add_u32_e32 v60, v82, v26 + s_mov_b64 s[2:3], 0 + s_branch .LBB25_6 +.LBB25_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr60 +.LBB25_6: ; %Flow98 + v_lshl_add_u32 v79, v0, 2, v9 + v_lshl_or_b32 v78, v3, 3, v5 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB25_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_xor_b32_e32 v0, v2, v15 + v_sub_u32_e32 v1, v14, v8 + v_lshlrev_b32_e32 v1, 12, v1 + v_lshlrev_b32_e32 v8, 2, v0 + v_add3_u32 v69, v8, v9, v1 + v_lshrrev_b32_e32 v1, 5, v24 + v_lshrrev_b16_e32 v8, 3, v24 + v_and_b32_e32 v8, 3, v8 + v_sub_u16_e32 v9, v8, v14 + v_bfe_i32 v9, v9, 0, 16 + v_lshl_or_b32 v24, v1, 4, v2 + v_xor_b32_e32 v19, v24, v7 + v_sub_u32_e32 v0, v19, v0 + v_lshlrev_b32_e32 v25, 11, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v9, v9, 12, v25 + v_add3_u32 v41, v9, v69, v0 + v_lshrrev_b32_e32 v0, 5, v23 + v_sub_u32_e32 v1, v0, v1 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v8, v23, v8 + v_bfe_i32 v8, v8, 0, 16 + v_lshl_or_b32 v25, v0, 4, v2 + v_xor_b32_e32 v26, v25, v15 + v_sub_u32_e32 v19, v26, v19 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_add_u32 v1, v8, 12, v1 + v_add3_u32 v42, v19, v1, v41 + v_sub_u16_e32 v8, v14, v23 + v_bfe_i32 v8, v8, 0, 16 + v_xor_b32_e32 v19, v13, v7 + v_sub_u32_e32 v23, v19, v26 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_or_b32 v0, v8, 12, v0 + v_add3_u32 v36, v23, v0, v42 + v_lshrrev_b32_e32 v8, 5, v22 + v_lshlrev_b32_e32 v23, 11, v8 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v26, v22, v14 + v_lshl_or_b32 v27, v8, 4, v2 + v_and_b32_e32 v27, 31, v27 + v_xor_b32_e32 v28, v27, v15 + v_sub_u32_e32 v19, v28, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_mov_b32_e32 v29, 12 + v_lshlrev_b32_sdwa v26, v29, sext(v26) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v23, v23, v26, s6 + v_add3_u32 v38, v19, v23, v36 + v_lshrrev_b32_e32 v26, 5, v21 + v_sub_u32_e32 v8, v26, v8 + v_lshrrev_b16_e32 v19, 3, v21 + v_and_b32_e32 v21, 3, v19 + v_sub_u16_e32 v19, v21, v22 + v_bfe_i32 v19, v19, 0, 16 + v_lshl_or_b32 v22, v26, 4, v2 + v_and_b32_e32 v22, 31, v22 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v28, v7, v28 + v_lshlrev_b32_e32 v8, 11, v8 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_add_u32 v8, v19, 12, v8 + v_add3_u32 v19, v28, v8, v38 + v_lshrrev_b32_e32 v28, 5, v17 + v_sub_u32_e32 v26, v28, v26 + v_lshrrev_b16_e32 v17, 3, v17 + v_and_b32_e32 v17, 3, v17 + v_sub_u16_e32 v21, v17, v21 + v_bfe_i32 v21, v21, 0, 16 + v_lshl_or_b32 v30, v28, 4, v2 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v26, 11, v26 + v_lshlrev_b32_e32 v7, 2, v7 + v_lshl_add_u32 v21, v21, 12, v26 + v_add3_u32 v37, v7, v21, v19 + v_lshrrev_b32_e32 v7, 4, v16 + v_sub_u16_e32 v14, v14, v17 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_lshlrev_b32_sdwa v14, v29, sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v17, 11, v28 + v_sub_u32_e32 v14, v14, v17 + v_add3_u32 v72, v15, v14, v37 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v73, v16, 2, v72 + v_xor_b32_e32 v16, v24, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v49, v17, v9, v73 + v_xor_b32_e32 v17, v25, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v50, v16, v1, v49 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v47, v17, v0, v50 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v48, v16, v23, v47 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v39, v16, v8, v48 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v40, v7, v21, v39 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v7, 0x80, v6 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v74, v15, v14, v40 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v75, v16, 2, v74 + v_xor_b32_e32 v16, v24, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v54, v17, v9, v75 + v_xor_b32_e32 v17, v25, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v55, v16, v1, v54 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v51, v17, v0, v55 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v52, v16, v23, v51 + v_xor_b32_e32 v7, v22, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v43, v16, v8, v52 + v_xor_b32_e32 v15, v30, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v44, v7, v21, v43 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 4, v6 + v_xor_b32_e32 v7, v2, v6 + v_sub_u32_e32 v15, v7, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v76, v15, v14, v44 + v_add_u32_e32 v14, 16, v6 + v_xor_b32_e32 v2, v2, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshl_add_u32 v77, v7, 2, v76 + v_xor_b32_e32 v7, v24, v6 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v62, v2, v9, v77 + v_xor_b32_e32 v2, v25, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v63, v7, v1, v62 + v_xor_b32_e32 v1, v13, v6 + v_sub_u32_e32 v2, v1, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v56, v2, v0, v63 + v_xor_b32_e32 v0, v27, v14 + v_sub_u32_e32 v1, v0, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v59, v1, v23, v56 + v_xor_b32_e32 v1, v22, v6 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v46, v0, v8, v59 + v_xor_b32_e32 v0, v30, v14 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v45, v0, v21, v46 + v_xor_b32_e32 v0, v4, v12 + v_lshl_add_u32 v67, v0, 3, v5 + v_xor_b32_e32 v1, v4, v11 + v_lshl_add_u32 v61, v1, 3, v5 + v_xor_b32_e32 v2, v4, v10 + v_lshl_add_u32 v53, v2, 3, v5 + v_sub_u32_e32 v4, v3, v2 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v5, 0x1000, v4 + v_add_u32_e32 v80, v5, v53 + v_add_u32_e32 v89, v4, v53 + v_sub_u32_e32 v0, v0, v3 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v68, v80, v0 + v_add_u32_e32 v90, v89, v0 + v_sub_u32_e32 v1, v1, v3 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v64, v80, v1 + v_add_u32_e32 v91, v89, v1 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v57, v80, v2 + v_add_u32_e32 v92, v89, v2 + v_add_u32_e32 v81, v57, v5 + v_add_u32_e32 v93, v92, v5 + v_add_u32_e32 v70, v81, v0 + v_add_u32_e32 v65, v81, v1 + v_add_u32_e32 v58, v81, v2 + v_add_u32_e32 v82, v58, v5 + v_add_u32_e32 v71, v82, v0 + v_add_u32_e32 v66, v82, v1 + v_add_u32_e32 v60, v82, v2 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_mov_b32_e32 v94, 0x80 +.LBB25_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v0, 64, v20 + v_add_u32_e32 v18, s2, v18 + buffer_load_dwordx4 v[100:103], v20, s[12:15], 0 offen offset:64 + v_add_u32_e32 v1, s7, v18 + v_add_u32_e32 v2, s22, v0 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + buffer_load_dwordx4 v[6:9], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[104:107], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[108:111], v2, s[12:15], 0 offen + v_add_u32_e32 v20, s22, v2 + buffer_load_dwordx4 v[14:17], v1, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v3, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[112:115], v20, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v35, v69 + ds_read_b32 v34, v79 + ds_read_b64 v[28:29], v78 offset:16384 + ds_read_b64 v[26:27], v89 offset:20480 + ds_read_b64 v[20:21], v90 offset:20480 + ds_read_b64 v[24:25], v93 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[34:35], v[28:29], a[64:79] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[34:35], v[26:27], a[80:95] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[34:35], v[24:25], a[96:111] + ds_read_b64 v[30:31], v81 offset:20480 + ds_read_b32 v96, v72 + ds_read_b64 v[32:33], v70 offset:20480 + ds_read_b64 v[22:23], v65 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[34:35], v[30:31], a[112:127] + ds_read_b32 v97, v73 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[96:97], v[28:29], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[96:97], v[26:27], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[96:97], v[24:25], a[160:175] + ds_read_b32 v34, v74 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[96:97], v[30:31], a[176:191] + ds_read_b32 v35, v75 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[34:35], v[28:29], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[34:35], v[26:27], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[34:35], v[24:25], a[224:239] + ds_read_b32 v96, v76 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[34:35], v[30:31], a[240:255] + ds_read_b32 v97, v77 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[96:97], v[28:29], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[96:97], v[26:27], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[96:97], v[24:25], a[0:15] + ds_read_b32 v34, v41 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[96:97], v[30:31], a[48:63] + ds_read_b32 v35, v42 + ds_read_b64 v[24:25], v67 offset:16384 + ds_read_b32 v96, v36 + ds_read_b32 v97, v38 + ds_read_b32 v122, v19 + ds_read_b32 v123, v37 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[34:35], v[24:25], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[34:35], v[20:21], a[80:95] + ds_read_b64 v[28:29], v68 offset:20480 + ds_read_b64 v[26:27], v64 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[34:35], v[28:29], a[96:111] + ds_read_b32 v30, v49 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[34:35], v[32:33], a[112:127] + ds_read_b32 v31, v50 + ds_read_b32 v34, v47 + ds_read_b32 v35, v48 + ds_read_b32 v120, v39 + ds_read_b32 v121, v40 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[30:31], v[24:25], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[30:31], v[20:21], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[30:31], v[28:29], a[160:175] + ds_read_b32 v98, v54 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[30:31], v[32:33], a[176:191] + ds_read_b32 v99, v55 + ds_read_b32 v126, v51 + ds_read_b32 v127, v52 + ds_read_b32 v118, v43 + ds_read_b32 v119, v44 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[98:99], v[24:25], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[98:99], v[20:21], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[98:99], v[28:29], a[224:239] + ds_read_b32 v30, v62 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[98:99], v[32:33], a[240:255] + ds_read_b32 v31, v63 + ds_read_b32 v124, v56 + ds_read_b32 v125, v59 + ds_read_b32 v116, v46 + ds_read_b32 v117, v45 + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[30:31], v[24:25], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[30:31], v[20:21], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[30:31], v[28:29], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[30:31], v[32:33], a[48:63] + ds_read_b64 v[30:31], v61 offset:16384 + ds_read_b64 v[24:25], v53 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[96:97], v[30:31], a[64:79] + ds_read_b64 v[28:29], v91 offset:20480 + ds_read_b64 v[32:33], v92 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[96:97], v[28:29], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[96:97], v[26:27], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[96:97], v[22:23], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[34:35], v[30:31], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[34:35], v[28:29], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[34:35], v[26:27], a[160:175] + s_add_i32 s26, s3, -1 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[34:35], v[22:23], a[176:191] + v_readfirstlane_b32 s27, v227 + s_lshr_b32 s28, s27, 2 + s_andn2_b32 s27, s27, 63 + s_and_b32 s28, s28, 0x3ffffff0 + v_add_u32_e32 v1, s27, v85 + v_mov_b32_e32 v20, v0 + v_add_u32_e32 v97, s28, v83 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[126:127], v[30:31], a[192:207] + v_ashrrev_i32_e32 v21, 1, v1 + v_ashrrev_i32_e32 v98, 31, v1 + v_lshlrev_b32_e32 v0, 6, v1 + v_or_b32_e32 v96, 1, v1 + v_lshrrev_b32_e32 v99, 31, v1 + v_or_b32_e32 v95, 3, v1 + s_cmp_gt_u32 s3, 2 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[126:127], v[28:29], a[208:223] + s_mov_b32 s3, s26 + ds_read_b64 v[34:35], v57 offset:20480 + ds_read_b64 v[128:129], v58 offset:20480 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v1, 1, v97 + v_lshlrev_b32_e32 v130, 9, v97 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[126:127], v[26:27], a[224:239] + v_lshlrev_b32_e32 v97, 6, v97 + v_lshrrev_b32_e32 v98, 28, v98 + v_add_u32_e32 v131, v96, v99 + v_or_b32_e32 v132, 1, v21 + v_add_u32_e32 v99, v95, v99 + v_and_b32_e32 v1, 16, v1 + v_and_b32_e32 v130, 0x3000, v130 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[126:127], v[22:23], a[240:255] + v_and_b32_e32 v97, 0xfffff800, v97 + v_add_u32_e32 v126, v21, v98 + v_ashrrev_i32_e32 v127, 1, v131 + v_and_b32_e32 v133, 0x1ffffffe, v131 + v_ashrrev_i32_e32 v131, 31, v131 + v_add_u32_e32 v98, v132, v98 + v_ashrrev_i32_e32 v134, 1, v99 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[124:125], v[30:31], a[16:31] + v_and_b32_e32 v30, 0x1ffffffe, v99 + v_ashrrev_i32_e32 v31, 31, v99 + v_xor_b32_e32 v99, v1, v84 + v_add_u32_e32 v97, v130, v97 + v_or_b32_e32 v130, 1, v1 + v_or_b32_e32 v135, 2, v1 + v_or_b32_e32 v136, 3, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[124:125], v[28:29], a[32:47] + v_or_b32_e32 v28, 4, v1 + v_or_b32_e32 v29, 5, v1 + v_or_b32_e32 v137, 6, v1 + v_or_b32_e32 v138, 7, v1 + v_or_b32_e32 v139, 8, v1 + v_or_b32_e32 v140, 9, v1 + v_or_b32_e32 v141, 10, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[124:125], v[26:27], a[0:15] + v_or_b32_e32 v26, 11, v1 + v_or_b32_e32 v27, 12, v1 + v_or_b32_e32 v142, 13, v1 + v_or_b32_e32 v143, 14, v1 + v_or_b32_e32 v1, 15, v1 + v_and_b32_e32 v126, -16, v126 + v_sub_u32_e32 v144, v127, v21 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[124:125], v[22:23], a[48:63] + v_sub_u32_e32 v22, v96, v133 + v_lshrrev_b32_e32 v23, 28, v131 + v_sub_u32_e32 v96, v132, v127 + v_and_b32_e32 v98, -16, v98 + v_sub_u32_e32 v124, v134, v132 + v_sub_u32_e32 v30, v95, v30 + v_lshrrev_b32_e32 v31, 28, v31 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[122:123], v[24:25], a[64:79] + v_lshl_or_b32 v95, v99, 2, v97 + v_xor_b32_e32 v97, v130, v84 + v_xor_b32_e32 v125, v135, v84 + v_xor_b32_e32 v130, v136, v84 + v_xor_b32_e32 v28, v28, v84 + v_xor_b32_e32 v29, v29, v84 + v_xor_b32_e32 v131, v137, v84 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[122:123], v[32:33], a[80:95] + v_xor_b32_e32 v133, v138, v84 + v_xor_b32_e32 v135, v139, v84 + v_xor_b32_e32 v136, v140, v84 + v_xor_b32_e32 v137, v141, v84 + v_xor_b32_e32 v26, v26, v84 + v_xor_b32_e32 v27, v27, v84 + v_xor_b32_e32 v138, v142, v84 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[122:123], v[34:35], a[96:111] + v_xor_b32_e32 v139, v143, v84 + v_xor_b32_e32 v1, v1, v84 + v_sub_u32_e32 v21, v21, v126 + v_lshl_or_b32 v22, v22, 3, v87 + v_add_u32_e32 v23, v127, v23 + v_sub_u32_e32 v98, v132, v98 + v_lshlrev_b32_e32 v96, 7, v96 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[122:123], v[128:129], a[112:127] + v_lshl_or_b32 v30, v30, 3, v87 + v_add_u32_e32 v31, v134, v31 + v_lshlrev_b32_e32 v122, 7, v124 + v_sub_u32_e32 v99, v97, v99 + v_sub_u32_e32 v97, v125, v97 + v_sub_u32_e32 v123, v130, v125 + v_sub_u32_e32 v124, v28, v130 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[120:121], v[24:25], a[128:143] + v_sub_u32_e32 v28, v29, v28 + v_sub_u32_e32 v29, v131, v29 + v_sub_u32_e32 v125, v133, v131 + v_sub_u32_e32 v126, v135, v133 + v_sub_u32_e32 v130, v136, v135 + v_sub_u32_e32 v131, v137, v136 + v_sub_u32_e32 v132, v26, v137 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[120:121], v[32:33], a[144:159] + v_sub_u32_e32 v26, v27, v26 + v_sub_u32_e32 v27, v138, v27 + v_sub_u32_e32 v133, v139, v138 + v_sub_u32_e32 v1, v1, v139 + v_xor_b32_e32 v135, v21, v86 + v_xor_b32_e32 v21, v21, v87 + v_add_u32_e32 v136, v22, v88 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[120:121], v[34:35], a[160:175] + v_and_b32_e32 v23, -16, v23 + v_xor_b32_e32 v137, v98, v86 + v_xor_b32_e32 v98, v98, v87 + v_add_u32_e32 v138, v30, v88 + v_and_b32_e32 v31, -16, v31 + v_lshl_add_u32 v99, v99, 2, v95 + v_lshl_add_u32 v97, v97, 2, v94 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[120:121], v[128:129], a[176:191] + v_lshl_add_u32 v120, v123, 2, v94 + v_lshl_add_u32 v121, v124, 2, v94 + v_lshl_add_u32 v28, v28, 2, v94 + v_lshl_add_u32 v29, v29, 2, v94 + v_lshl_add_u32 v123, v125, 2, v94 + v_lshl_add_u32 v124, v126, 2, v94 + v_lshl_add_u32 v125, v130, 2, v94 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[118:119], v[24:25], a[192:207] + v_lshl_add_u32 v126, v131, 2, v94 + v_lshl_add_u32 v130, v132, 2, v94 + v_lshl_add_u32 v26, v26, 2, v94 + v_lshl_add_u32 v27, v27, 2, v94 + v_lshlrev_b32_e32 v131, 2, v133 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_add_u32 v132, v135, 3, v0 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[118:119], v[32:33], a[208:223] + v_lshl_add_u32 v0, v21, 3, v0 + v_sub_u32_e32 v23, v127, v23 + v_sub_u32_e32 v127, v98, v137 + v_sub_u32_e32 v31, v134, v31 + v_add3_u32 v133, v99, v97, v120 + v_add3_u32 v97, v99, s6, v97 + v_xor_b32_e32 v134, v136, v23 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[118:119], v[34:35], a[224:239] + v_lshl_add_u32 v135, v144, 7, v0 + v_xor_b32_e32 v22, v22, v23 + v_xor_b32_e32 v23, v138, v31 + v_xor_b32_e32 v30, v30, v31 + v_add_u32_e32 v31, v120, v97 + v_add3_u32 v120, v133, v121, v28 + v_sub_u32_e32 v133, v134, v21 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[118:119], v[128:129], a[240:255] + v_sub_u32_e32 v21, v22, v21 + v_sub_u32_e32 v22, v137, v22 + v_sub_u32_e32 v98, v23, v98 + v_sub_u32_e32 v23, v30, v23 + v_add_u32_e32 v30, v121, v31 + v_add3_u32 v118, v120, v29, v123 + v_lshl_add_u32 v119, v133, 3, v135 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[116:117], v[24:25], a[16:31] + v_lshl_add_u32 v21, v21, 3, v135 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshlrev_b32_e32 v24, 3, v98 + v_add_u32_e32 v25, v28, v30 + v_add3_u32 v28, v118, v124, v125 + v_add3_u32 v22, v22, v96, v21 + v_add_u32_e32 v29, v29, v25 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[116:117], v[32:33], a[32:47] + v_add3_u32 v28, v28, v126, v130 + v_lshl_add_u32 v32, v127, 3, v22 + v_add_u32_e32 v33, v123, v29 + v_add3_u32 v28, v28, v26, v27 + v_add3_u32 v24, v24, v122, v32 + v_add_u32_e32 v96, v124, v33 + v_add3_u32 v1, v28, v131, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[116:117], v[34:35], a[0:15] + v_lshl_add_u32 v23, v23, 3, v24 + v_add_u32_e32 v28, v125, v96 + v_add_u32_e32 v34, v126, v28 + v_add_u32_e32 v35, v130, v34 + v_add_u32_e32 v26, v26, v35 + v_add_u32_e32 v27, v27, v26 + v_add_u32_e32 v98, v27, v131 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[116:117], v[128:129], a[48:63] + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + s_waitcnt vmcnt(5) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v14, v14, v14, s18 + v_perm_b32 v15, v15, v15, s18 + v_perm_b32 v16, v16, v16, s18 + v_perm_b32 v17, v17, v17, s18 + v_perm_b32 v116, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + s_waitcnt vmcnt(1) + v_perm_b32 v2, v2, v2, s18 + v_perm_b32 v3, v3, v3, s18 + v_perm_b32 v4, v4, v4, s18 + v_perm_b32 v5, v5, v5, s18 + v_perm_b32 v13, v2, v14, s19 + v_perm_b32 v2, v2, v14, s25 + v_perm_b32 v14, v3, v15, s19 + v_perm_b32 v3, v3, v15, s25 + v_perm_b32 v15, v4, v16, s19 + v_perm_b32 v4, v4, v16, s25 + v_perm_b32 v16, v5, v17, s19 + v_perm_b32 v5, v5, v17, s25 + v_perm_b32 v17, v13, v116, s23 + v_perm_b32 v13, v13, v116, s24 + v_perm_b32 v116, v2, v6, s23 + v_perm_b32 v2, v2, v6, s24 + v_perm_b32 v6, v14, v10, s23 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v3, v7, s23 + v_perm_b32 v3, v3, v7, s24 + v_perm_b32 v7, v15, v11, s23 + v_perm_b32 v11, v15, v11, s24 + v_perm_b32 v15, v4, v8, s23 + v_perm_b32 v4, v4, v8, s24 + v_perm_b32 v8, v16, v12, s23 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v5, v9, s23 + v_perm_b32 v5, v5, v9, s24 + ds_write_b32 v95, v17 + ds_write_b32 v99, v13 offset:128 + ds_write_b32 v97, v116 + ds_write_b32 v31, v2 + ds_write_b32 v30, v6 + ds_write_b32 v25, v10 + ds_write_b32 v29, v14 + ds_write_b32 v33, v3 + ds_write_b32 v96, v7 + ds_write_b32 v28, v11 + ds_write_b32 v34, v15 + ds_write_b32 v35, v4 + ds_write_b32 v26, v8 + ds_write_b32 v27, v12 + ds_write_b32 v98, v16 offset:128 + ds_write_b32 v1, v5 offset:384 + ds_write_b64 v132, v[100:101] offset:16384 + ds_write_b64 v0, v[102:103] offset:16384 + ds_write_b64 v119, v[104:105] offset:16384 + ds_write_b64 v21, v[106:107] offset:16384 + ds_write_b64 v22, v[108:109] offset:16384 + ds_write_b64 v32, v[110:111] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v24, v[112:113] offset:16384 + ds_write_b64 v23, v[114:115] offset:16384 + s_cbranch_scc1 .LBB25_8 +.LBB25_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESC_NSB_8RowMajorELi1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEENSL_IJNSM_IS1D_NSL_IJS1G_S1F_EEEEEEEESG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1O_T0_EE5valueEbE4typeE + v_accvgpr_read_b32 v20, a160 + v_accvgpr_read_b32 v21, a161 + v_accvgpr_read_b32 v22, a162 + v_accvgpr_read_b32 v23, a163 + v_accvgpr_read_b32 v24, a164 + v_accvgpr_read_b32 v25, a165 + v_accvgpr_read_b32 v26, a166 + v_accvgpr_read_b32 v27, a167 + v_accvgpr_read_b32 v28, a168 + v_accvgpr_read_b32 v29, a169 + v_accvgpr_read_b32 v30, a170 + v_accvgpr_read_b32 v31, a171 + v_accvgpr_read_b32 v32, a172 + v_accvgpr_read_b32 v33, a173 + v_accvgpr_read_b32 v34, a174 + v_accvgpr_read_b32 v35, a175 + v_accvgpr_read_b32 v84, a176 + v_accvgpr_read_b32 v85, a177 + v_accvgpr_read_b32 v86, a178 + v_accvgpr_read_b32 v87, a179 + v_accvgpr_read_b32 v88, a180 + v_accvgpr_read_b32 v89, a181 + v_accvgpr_read_b32 v90, a182 + v_accvgpr_read_b32 v91, a183 + v_accvgpr_read_b32 v92, a184 + v_accvgpr_read_b32 v93, a185 + v_accvgpr_read_b32 v94, a186 + v_accvgpr_read_b32 v95, a187 + v_accvgpr_read_b32 v96, a188 + v_accvgpr_read_b32 v97, a189 + v_accvgpr_read_b32 v98, a190 + v_accvgpr_read_b32 v99, a191 + v_accvgpr_read_b32 v100, a192 + v_accvgpr_read_b32 v101, a193 + v_accvgpr_read_b32 v102, a194 + v_accvgpr_read_b32 v103, a195 + v_accvgpr_read_b32 v104, a196 + v_accvgpr_read_b32 v105, a197 + v_accvgpr_read_b32 v106, a198 + v_accvgpr_read_b32 v107, a199 + v_accvgpr_read_b32 v108, a200 + v_accvgpr_read_b32 v109, a201 + v_accvgpr_read_b32 v110, a202 + v_accvgpr_read_b32 v111, a203 + v_accvgpr_read_b32 v112, a204 + v_accvgpr_read_b32 v113, a205 + v_accvgpr_read_b32 v114, a206 + v_accvgpr_read_b32 v115, a207 + v_accvgpr_read_b32 v116, a208 + v_accvgpr_read_b32 v117, a209 + v_accvgpr_read_b32 v118, a210 + v_accvgpr_read_b32 v119, a211 + v_accvgpr_read_b32 v120, a212 + v_accvgpr_read_b32 v121, a213 + v_accvgpr_read_b32 v122, a214 + v_accvgpr_read_b32 v123, a215 + v_accvgpr_read_b32 v124, a216 + v_accvgpr_read_b32 v125, a217 + v_accvgpr_read_b32 v126, a218 + v_accvgpr_read_b32 v127, a219 + v_accvgpr_read_b32 v128, a220 + v_accvgpr_read_b32 v129, a221 + v_accvgpr_read_b32 v130, a222 + v_accvgpr_read_b32 v131, a223 + v_accvgpr_read_b32 v132, a224 + v_accvgpr_read_b32 v133, a225 + v_accvgpr_read_b32 v134, a226 + v_accvgpr_read_b32 v135, a227 + v_accvgpr_read_b32 v136, a228 + v_accvgpr_read_b32 v137, a229 + v_accvgpr_read_b32 v138, a230 + v_accvgpr_read_b32 v139, a231 + v_accvgpr_read_b32 v140, a232 + v_accvgpr_read_b32 v141, a233 + v_accvgpr_read_b32 v142, a234 + v_accvgpr_read_b32 v143, a235 + v_accvgpr_read_b32 v144, a236 + v_accvgpr_read_b32 v145, a237 + v_accvgpr_read_b32 v146, a238 + v_accvgpr_read_b32 v147, a239 + v_accvgpr_read_b32 v148, a240 + v_accvgpr_read_b32 v149, a241 + v_accvgpr_read_b32 v150, a242 + v_accvgpr_read_b32 v151, a243 + v_accvgpr_read_b32 v152, a244 + v_accvgpr_read_b32 v153, a245 + v_accvgpr_read_b32 v154, a246 + v_accvgpr_read_b32 v155, a247 + v_accvgpr_read_b32 v156, a248 + v_accvgpr_read_b32 v157, a249 + v_accvgpr_read_b32 v158, a250 + v_accvgpr_read_b32 v159, a251 + v_accvgpr_read_b32 v160, a252 + v_accvgpr_read_b32 v161, a253 + v_accvgpr_read_b32 v162, a254 + v_accvgpr_read_b32 v163, a255 + v_accvgpr_read_b32 v164, a32 + v_accvgpr_read_b32 v165, a33 + v_accvgpr_read_b32 v166, a34 + v_accvgpr_read_b32 v167, a35 + v_accvgpr_read_b32 v168, a36 + v_accvgpr_read_b32 v169, a37 + v_accvgpr_read_b32 v170, a38 + v_accvgpr_read_b32 v171, a39 + v_accvgpr_read_b32 v172, a40 + v_accvgpr_read_b32 v173, a41 + v_accvgpr_read_b32 v174, a42 + v_accvgpr_read_b32 v175, a43 + v_accvgpr_read_b32 v176, a44 + v_accvgpr_read_b32 v177, a45 + v_accvgpr_read_b32 v178, a46 + v_accvgpr_read_b32 v179, a47 + v_accvgpr_mov_b32 a240, a48 + v_accvgpr_mov_b32 a241, a49 + v_accvgpr_mov_b32 a242, a50 + v_accvgpr_mov_b32 a243, a51 + v_accvgpr_mov_b32 a244, a52 + v_accvgpr_mov_b32 a245, a53 + v_accvgpr_mov_b32 a246, a54 + v_accvgpr_mov_b32 a247, a55 + v_accvgpr_mov_b32 a248, a56 + v_accvgpr_mov_b32 a249, a57 + v_accvgpr_mov_b32 a250, a58 + v_accvgpr_mov_b32 a251, a59 + v_accvgpr_mov_b32 a252, a60 + v_accvgpr_mov_b32 a253, a61 + v_accvgpr_mov_b32 a254, a62 + v_accvgpr_mov_b32 a255, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v8, v79 + ds_read_b32 v9, v69 + ds_read_b64 v[0:1], v78 offset:16384 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a224, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[8:9], v[0:1], a[224:239] + ds_read_b64 v[4:5], v80 offset:16384 + v_accvgpr_mov_b32 a223, a95 + v_accvgpr_mov_b32 a222, a94 + v_accvgpr_mov_b32 a221, a93 + v_accvgpr_mov_b32 a220, a92 + v_accvgpr_mov_b32 a219, a91 + v_accvgpr_mov_b32 a218, a90 + v_accvgpr_mov_b32 a217, a89 + v_accvgpr_mov_b32 a216, a88 + v_accvgpr_mov_b32 a215, a87 + v_accvgpr_mov_b32 a214, a86 + v_accvgpr_mov_b32 a213, a85 + v_accvgpr_mov_b32 a212, a84 + v_accvgpr_mov_b32 a211, a83 + v_accvgpr_mov_b32 a210, a82 + v_accvgpr_mov_b32 a209, a81 + v_accvgpr_mov_b32 a208, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[8:9], v[4:5], a[208:223] + ds_read_b64 v[6:7], v81 offset:16384 + v_accvgpr_mov_b32 a207, a111 + v_accvgpr_mov_b32 a206, a110 + v_accvgpr_mov_b32 a205, a109 + v_accvgpr_mov_b32 a204, a108 + v_accvgpr_mov_b32 a203, a107 + v_accvgpr_mov_b32 a202, a106 + v_accvgpr_mov_b32 a201, a105 + v_accvgpr_mov_b32 a200, a104 + v_accvgpr_mov_b32 a199, a103 + v_accvgpr_mov_b32 a198, a102 + v_accvgpr_mov_b32 a197, a101 + v_accvgpr_mov_b32 a196, a100 + v_accvgpr_mov_b32 a195, a99 + v_accvgpr_mov_b32 a194, a98 + v_accvgpr_mov_b32 a193, a97 + v_accvgpr_mov_b32 a192, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[8:9], v[6:7], a[192:207] + ds_read_b64 v[2:3], v82 offset:16384 + v_accvgpr_mov_b32 a191, a127 + v_accvgpr_mov_b32 a190, a126 + v_accvgpr_mov_b32 a189, a125 + v_accvgpr_mov_b32 a188, a124 + v_accvgpr_mov_b32 a187, a123 + v_accvgpr_mov_b32 a186, a122 + v_accvgpr_mov_b32 a185, a121 + v_accvgpr_mov_b32 a184, a120 + v_accvgpr_mov_b32 a183, a119 + v_accvgpr_mov_b32 a182, a118 + v_accvgpr_mov_b32 a181, a117 + v_accvgpr_mov_b32 a180, a116 + v_accvgpr_mov_b32 a179, a115 + v_accvgpr_mov_b32 a178, a114 + v_accvgpr_mov_b32 a177, a113 + v_accvgpr_mov_b32 a176, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[8:9], v[2:3], a[176:191] + ds_read_b32 v8, v72 + ds_read_b32 v9, v73 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[8:9], v[4:5], a[144:159] + v_accvgpr_write_b32 a143, v35 + v_accvgpr_write_b32 a142, v34 + v_accvgpr_write_b32 a141, v33 + v_accvgpr_write_b32 a140, v32 + v_accvgpr_write_b32 a139, v31 + v_accvgpr_write_b32 a138, v30 + v_accvgpr_write_b32 a137, v29 + v_accvgpr_write_b32 a136, v28 + v_accvgpr_write_b32 a135, v27 + v_accvgpr_write_b32 a134, v26 + v_accvgpr_write_b32 a133, v25 + v_accvgpr_write_b32 a132, v24 + v_accvgpr_write_b32 a131, v23 + v_accvgpr_write_b32 a130, v22 + v_accvgpr_write_b32 a129, v21 + v_accvgpr_write_b32 a128, v20 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[8:9], v[6:7], a[128:143] + v_accvgpr_write_b32 a127, v99 + v_accvgpr_write_b32 a126, v98 + v_accvgpr_write_b32 a125, v97 + v_accvgpr_write_b32 a124, v96 + v_accvgpr_write_b32 a123, v95 + v_accvgpr_write_b32 a122, v94 + v_accvgpr_write_b32 a121, v93 + v_accvgpr_write_b32 a120, v92 + v_accvgpr_write_b32 a119, v91 + v_accvgpr_write_b32 a118, v90 + v_accvgpr_write_b32 a117, v89 + v_accvgpr_write_b32 a116, v88 + v_accvgpr_write_b32 a115, v87 + v_accvgpr_write_b32 a114, v86 + v_accvgpr_write_b32 a113, v85 + v_accvgpr_write_b32 a112, v84 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[8:9], v[2:3], a[112:127] + ds_read_b32 v8, v74 + ds_read_b32 v9, v75 + v_accvgpr_write_b32 a96, v100 + v_accvgpr_write_b32 a97, v101 + v_accvgpr_write_b32 a98, v102 + v_accvgpr_write_b32 a99, v103 + v_accvgpr_write_b32 a100, v104 + v_accvgpr_write_b32 a101, v105 + v_accvgpr_write_b32 a102, v106 + v_accvgpr_write_b32 a103, v107 + v_accvgpr_write_b32 a104, v108 + v_accvgpr_write_b32 a105, v109 + v_accvgpr_write_b32 a106, v110 + v_accvgpr_write_b32 a107, v111 + v_accvgpr_write_b32 a108, v112 + v_accvgpr_write_b32 a109, v113 + v_accvgpr_write_b32 a110, v114 + v_accvgpr_write_b32 a111, v115 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[8:9], v[0:1], a[96:111] + v_accvgpr_write_b32 a80, v116 + v_accvgpr_write_b32 a81, v117 + v_accvgpr_write_b32 a82, v118 + v_accvgpr_write_b32 a83, v119 + v_accvgpr_write_b32 a84, v120 + v_accvgpr_write_b32 a85, v121 + v_accvgpr_write_b32 a86, v122 + v_accvgpr_write_b32 a87, v123 + v_accvgpr_write_b32 a88, v124 + v_accvgpr_write_b32 a89, v125 + v_accvgpr_write_b32 a90, v126 + v_accvgpr_write_b32 a91, v127 + v_accvgpr_write_b32 a92, v128 + v_accvgpr_write_b32 a93, v129 + v_accvgpr_write_b32 a94, v130 + v_accvgpr_write_b32 a95, v131 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[8:9], v[4:5], a[80:95] + v_accvgpr_write_b32 a64, v132 + v_accvgpr_write_b32 a65, v133 + v_accvgpr_write_b32 a66, v134 + v_accvgpr_write_b32 a67, v135 + v_accvgpr_write_b32 a68, v136 + v_accvgpr_write_b32 a69, v137 + v_accvgpr_write_b32 a70, v138 + v_accvgpr_write_b32 a71, v139 + v_accvgpr_write_b32 a72, v140 + v_accvgpr_write_b32 a73, v141 + v_accvgpr_write_b32 a74, v142 + v_accvgpr_write_b32 a75, v143 + v_accvgpr_write_b32 a76, v144 + v_accvgpr_write_b32 a77, v145 + v_accvgpr_write_b32 a78, v146 + v_accvgpr_write_b32 a79, v147 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[8:9], v[6:7], a[64:79] + v_accvgpr_write_b32 a48, v148 + v_accvgpr_write_b32 a49, v149 + v_accvgpr_write_b32 a50, v150 + v_accvgpr_write_b32 a51, v151 + v_accvgpr_write_b32 a52, v152 + v_accvgpr_write_b32 a53, v153 + v_accvgpr_write_b32 a54, v154 + v_accvgpr_write_b32 a55, v155 + v_accvgpr_write_b32 a56, v156 + v_accvgpr_write_b32 a57, v157 + v_accvgpr_write_b32 a58, v158 + v_accvgpr_write_b32 a59, v159 + v_accvgpr_write_b32 a60, v160 + v_accvgpr_write_b32 a61, v161 + v_accvgpr_write_b32 a62, v162 + v_accvgpr_write_b32 a63, v163 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[8:9], v[2:3], a[48:63] + ds_read_b32 v8, v76 + ds_read_b32 v9, v77 + v_accvgpr_mov_b32 a47, a31 + v_accvgpr_mov_b32 a46, a30 + v_accvgpr_mov_b32 a45, a29 + v_accvgpr_mov_b32 a44, a28 + v_accvgpr_mov_b32 a43, a27 + v_accvgpr_mov_b32 a42, a26 + v_accvgpr_mov_b32 a41, a25 + v_accvgpr_mov_b32 a40, a24 + v_accvgpr_mov_b32 a39, a23 + v_accvgpr_mov_b32 a38, a22 + v_accvgpr_mov_b32 a37, a21 + v_accvgpr_mov_b32 a36, a20 + v_accvgpr_mov_b32 a35, a19 + v_accvgpr_mov_b32 a34, a18 + v_accvgpr_mov_b32 a33, a17 + v_accvgpr_mov_b32 a32, a16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[0:1], a[32:47] + v_accvgpr_write_b32 a16, v164 + v_accvgpr_write_b32 a17, v165 + v_accvgpr_write_b32 a18, v166 + v_accvgpr_write_b32 a19, v167 + v_accvgpr_write_b32 a20, v168 + v_accvgpr_write_b32 a21, v169 + v_accvgpr_write_b32 a22, v170 + v_accvgpr_write_b32 a23, v171 + v_accvgpr_write_b32 a24, v172 + v_accvgpr_write_b32 a25, v173 + v_accvgpr_write_b32 a26, v174 + v_accvgpr_write_b32 a27, v175 + v_accvgpr_write_b32 a28, v176 + v_accvgpr_write_b32 a29, v177 + v_accvgpr_write_b32 a30, v178 + v_accvgpr_write_b32 a31, v179 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[8:9], v[6:7], a[0:15] + ds_read_b32 v10, v41 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[2:3], a[240:255] + ds_read_b32 v11, v42 + ds_read_b64 v[0:1], v67 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v70 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v71 offset:16384 + ds_read_b32 v8, v49 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v50 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v54 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v55 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v62 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v63 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[8:9], v[4:5], a[0:15] + ds_read_b32 v10, v36 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[6:7], a[240:255] + ds_read_b32 v11, v38 + ds_read_b64 v[0:1], v61 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v64 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v66 offset:16384 + ds_read_b32 v8, v47 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v48 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v51 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v52 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v56 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v59 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[8:9], v[4:5], a[0:15] + ds_read_b32 v10, v19 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[6:7], a[240:255] + ds_read_b32 v11, v37 + ds_read_b64 v[0:1], v53 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[10:11], v[0:1], a[224:239] + ds_read_b64 v[2:3], v57 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[10:11], v[2:3], a[208:223] + ds_read_b64 v[4:5], v58 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[10:11], v[4:5], a[192:207] + ds_read_b64 v[6:7], v60 offset:16384 + ds_read_b32 v8, v39 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[10:11], v[6:7], a[176:191] + ds_read_b32 v9, v40 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[8:9], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[8:9], v[2:3], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[8:9], v[4:5], a[128:143] + ds_read_b32 v10, v43 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[8:9], v[6:7], a[112:127] + ds_read_b32 v11, v44 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[10:11], v[0:1], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[10:11], v[2:3], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[10:11], v[4:5], a[64:79] + ds_read_b32 v8, v46 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b32 v9, v45 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[0:1], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[2:3], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[8:9], v[4:5], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[6:7], a[240:255] +.LBB25_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESC_NSB_8RowMajorELi1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEENSL_IJNSM_IS1D_NSL_IJS1G_S1F_EEEEEEEESG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1O_T0_EE5valueEbE4typeEL + v_accvgpr_read_b32 v143, a224 + v_accvgpr_read_b32 v142, a225 + v_accvgpr_read_b32 v141, a226 + v_accvgpr_read_b32 v140, a227 + v_accvgpr_read_b32 v139, a228 + v_accvgpr_read_b32 v18, a229 + v_accvgpr_read_b32 v0, a230 + v_accvgpr_read_b32 v138, a231 + v_accvgpr_read_b32 v137, a232 + v_accvgpr_read_b32 v136, a233 + v_accvgpr_read_b32 v135, a234 + v_accvgpr_read_b32 v134, a235 + v_accvgpr_read_b32 v133, a236 + v_accvgpr_read_b32 v132, a237 + v_accvgpr_read_b32 v131, a238 + v_accvgpr_read_b32 v130, a239 + v_accvgpr_read_b32 v107, a208 + v_accvgpr_read_b32 v106, a209 + v_accvgpr_read_b32 v105, a210 + v_accvgpr_read_b32 v104, a211 + v_accvgpr_read_b32 v103, a212 + v_accvgpr_read_b32 v102, a213 + v_accvgpr_read_b32 v101, a214 + v_accvgpr_read_b32 v100, a215 + v_accvgpr_read_b32 v99, a216 + v_accvgpr_read_b32 v98, a217 + v_accvgpr_read_b32 v97, a218 + v_accvgpr_read_b32 v96, a219 + v_accvgpr_read_b32 v95, a220 + v_accvgpr_read_b32 v94, a221 + v_accvgpr_read_b32 v93, a222 + v_accvgpr_read_b32 v92, a223 + v_accvgpr_read_b32 v91, a192 + v_accvgpr_read_b32 v90, a193 + v_accvgpr_read_b32 v89, a194 + v_accvgpr_read_b32 v88, a195 + v_accvgpr_read_b32 v87, a196 + v_accvgpr_read_b32 v86, a197 + v_accvgpr_read_b32 v85, a198 + v_accvgpr_read_b32 v84, a199 + v_accvgpr_read_b32 v83, a200 + v_accvgpr_read_b32 v82, a201 + v_accvgpr_read_b32 v81, a202 + v_accvgpr_read_b32 v80, a203 + v_accvgpr_read_b32 v79, a204 + v_accvgpr_read_b32 v78, a205 + v_accvgpr_read_b32 v77, a206 + v_accvgpr_read_b32 v76, a207 + v_accvgpr_read_b32 v75, a176 + v_accvgpr_read_b32 v74, a177 + v_accvgpr_read_b32 v73, a178 + v_accvgpr_read_b32 v72, a179 + v_accvgpr_read_b32 v71, a180 + v_accvgpr_read_b32 v70, a181 + v_accvgpr_read_b32 v69, a182 + v_accvgpr_read_b32 v68, a183 + v_accvgpr_read_b32 v67, a184 + v_accvgpr_read_b32 v66, a185 + v_accvgpr_read_b32 v65, a186 + v_accvgpr_read_b32 v64, a187 + v_accvgpr_read_b32 v63, a188 + v_accvgpr_read_b32 v62, a189 + v_accvgpr_read_b32 v61, a190 + v_accvgpr_read_b32 v20, a191 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v60, a80 + v_accvgpr_read_b32 v59, a81 + v_accvgpr_read_b32 v58, a82 + v_accvgpr_read_b32 v57, a83 + v_accvgpr_read_b32 v56, a84 + v_accvgpr_read_b32 v55, a85 + v_accvgpr_read_b32 v54, a86 + v_accvgpr_read_b32 v53, a87 + v_accvgpr_read_b32 v52, a88 + v_accvgpr_read_b32 v51, a89 + v_accvgpr_read_b32 v50, a90 + v_accvgpr_read_b32 v25, a91 + v_accvgpr_read_b32 v24, a92 + v_accvgpr_read_b32 v23, a93 + v_accvgpr_read_b32 v22, a94 + v_accvgpr_read_b32 v21, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v1, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s2, s4, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_u32 s2, s5, s3 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v19, 3, v225 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v209, v92 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v147 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v20, v205 + v_accvgpr_write_b32 a0, v20 + v_cvt_f16_f32_e32 v20, v204 + v_accvgpr_write_b32 a1, v20 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v20, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v1 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v201, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v225 + v_lshrrev_b32_e32 v1, 1, v225 + s_cbranch_scc1 .LBB25_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB25_14 +.LBB25_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB25_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_or_b32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v132 offset:3456 + ds_write_b16 v23, v133 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s20, v25 + v_or_b32_e32 v25, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v190, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v190, v31, v41 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v76 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 0x80, v25 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v72 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0xc0, v25 + v_add_u32_e32 v31, v31, v191 + v_lshlrev_b32_e32 v192, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v207 offset:128 + ds_write_b16 v23, v206 offset:256 + ds_write_b16 v23, a0 offset:384 + ds_write_b16 v23, a1 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v61 offset:2304 + ds_write_b16 v23, v62 offset:2432 + ds_write_b16 v23, v63 offset:3072 + ds_write_b16 v23, v64 offset:3200 + ds_write_b16 v23, v65 offset:3328 + ds_write_b16 v23, v66 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v115 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v191 + v_lshlrev_b32_e32 v191, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v114 + ds_write_b16 v23, v193 offset:128 + ds_write_b16 v23, v194 offset:256 + ds_write_b16 v23, v195 offset:384 + ds_write_b16 v23, v196 offset:1024 + ds_write_b16 v23, v197 offset:1152 + ds_write_b16 v23, v198 offset:1280 + ds_write_b16 v23, v199 offset:1408 + ds_write_b16 v23, v200 offset:2048 + ds_write_b16 v23, v201 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v43 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v108 offset:8320 + ds_write_b16 v23, v109 offset:8448 + ds_write_b16 v23, v110 offset:8576 + ds_write_b16 v23, v111 offset:9216 + ds_write_b16 v23, v112 offset:9344 + ds_write_b16 v23, v113 offset:9472 + ds_write_b16 v23, v185 offset:9600 + ds_write_b16 v23, v184 offset:10240 + ds_write_b16 v23, v183 offset:10368 + ds_write_b16 v23, v182 offset:10496 + ds_write_b16 v23, v181 offset:10624 + ds_write_b16 v23, v180 offset:11264 + ds_write_b16 v23, v179 offset:11392 + ds_write_b16 v23, v178 offset:11520 + ds_write_b16 v23, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v190 + v_lshlrev_b32_e32 v190, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v3 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB25_12 +.LBB25_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_or_b32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v132 offset:3456 + ds_write_b16 v31, v133 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v41, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v131, v0, v41 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v186, 1, v131 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v186, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v131 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v107 + ds_write_b16 v31, v106 offset:128 + ds_write_b16 v31, v105 offset:256 + ds_write_b16 v31, v104 offset:384 + ds_write_b16 v31, v103 offset:1024 + ds_write_b16 v31, v102 offset:1152 + ds_write_b16 v31, v101 offset:1280 + ds_write_b16 v31, v100 offset:1408 + ds_write_b16 v31, v99 offset:2048 + ds_write_b16 v31, v98 offset:2176 + ds_write_b16 v31, v97 offset:2304 + ds_write_b16 v31, v96 offset:2432 + ds_write_b16 v31, v95 offset:3072 + ds_write_b16 v31, v94 offset:3200 + ds_write_b16 v31, v93 offset:3328 + ds_write_b16 v31, v209 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v41 + v_add_u32_e32 v94, v0, v93 + v_lshlrev_b32_e32 v95, 1, v94 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v95, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v94 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v76 offset:3456 + ds_write_b16 v31, v77 offset:8192 + ds_write_b16 v31, v78 offset:8320 + ds_write_b16 v31, v79 offset:8448 + ds_write_b16 v31, v80 offset:8576 + ds_write_b16 v31, v81 offset:9216 + ds_write_b16 v31, v82 offset:9344 + ds_write_b16 v31, v83 offset:9472 + ds_write_b16 v31, v84 offset:9600 + ds_write_b16 v31, v85 offset:10240 + ds_write_b16 v31, v86 offset:10368 + ds_write_b16 v31, v87 offset:10496 + ds_write_b16 v31, v88 offset:10624 + ds_write_b16 v31, v89 offset:11264 + ds_write_b16 v31, v90 offset:11392 + ds_write_b16 v31, v91 offset:11520 + ds_write_b16 v31, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v76, 0x80, v41 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v75 + ds_write_b16 v31, v74 offset:128 + ds_write_b16 v31, v73 offset:256 + ds_write_b16 v31, v72 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v74, 0xc0, v41 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v208 + ds_write_b16 v31, v207 offset:128 + ds_write_b16 v31, v206 offset:256 + ds_write_b16 v31, a0 offset:384 + ds_write_b16 v31, a1 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v61 offset:2304 + ds_write_b16 v31, v62 offset:2432 + ds_write_b16 v31, v63 offset:3072 + ds_write_b16 v31, v64 offset:3200 + ds_write_b16 v31, v65 offset:3328 + ds_write_b16 v31, v66 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v115 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v114 + ds_write_b16 v31, v193 offset:128 + ds_write_b16 v31, v194 offset:256 + ds_write_b16 v31, v195 offset:384 + ds_write_b16 v31, v196 offset:1024 + ds_write_b16 v31, v197 offset:1152 + ds_write_b16 v31, v198 offset:1280 + ds_write_b16 v31, v199 offset:1408 + ds_write_b16 v31, v200 offset:2048 + ds_write_b16 v31, v201 offset:2176 + ds_write_b16 v31, v47 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v44 offset:3200 + ds_write_b16 v31, v43 offset:3328 + ds_write_b16 v31, v48 offset:3456 + ds_write_b16 v31, v49 offset:8192 + ds_write_b16 v31, v108 offset:8320 + ds_write_b16 v31, v109 offset:8448 + ds_write_b16 v31, v110 offset:8576 + ds_write_b16 v31, v111 offset:9216 + ds_write_b16 v31, v112 offset:9344 + ds_write_b16 v31, v113 offset:9472 + ds_write_b16 v31, v185 offset:9600 + ds_write_b16 v31, v184 offset:10240 + ds_write_b16 v31, v183 offset:10368 + ds_write_b16 v31, v182 offset:10496 + ds_write_b16 v31, v181 offset:10624 + ds_write_b16 v31, v180 offset:11264 + ds_write_b16 v31, v179 offset:11392 + ds_write_b16 v31, v178 offset:11520 + ds_write_b16 v31, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, v61, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v3 offset:128 + ds_write_b16 v31, v4 offset:256 + ds_write_b16 v31, v5 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v41 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end25: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end25-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 29528 +; TotalNumSgprs: 36 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB26_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB26_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v2, v0, s2 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v6 +.LBB26_3: ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_ubyte v7, v[2:3], off + v_lshl_add_u64 v[8:9], s[8:9], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_bf8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_bf8_sdwa v5, v5 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s7, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v5, v7 + s_cbranch_scc0 .LBB26_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB26_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB26_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end26: + .size _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end26-_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 440 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_mov_b32 s23, s7 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v0, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s24, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s24, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_mul_i32 s19, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s19, 31 + s_add_u32 s12, s10, s19 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_mul_i32 s2, s22, s2 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v225, -1, v0 + v_and_b32_e32 v37, 31, v225 + v_lshrrev_b32_e32 v5, 5, v225 + v_and_b32_e32 v4, 15, v225 + v_lshrrev_b32_e32 v1, 2, v225 + s_cbranch_scc0 .LBB27_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + s_lshr_b32 s28, s15, 2 + s_and_b32 s11, s28, 0x3ffffff0 + v_and_b32_e32 v2, 28, v1 + v_lshlrev_b32_e32 v14, 4, v4 + v_or_b32_e32 v0, s20, v14 + v_add_u32_e32 v16, s11, v2 + v_mad_u64_u32 v[2:3], s[24:25], v16, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[6:9], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[20:23], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[24:27], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v19, 3, v5 + v_lshlrev_b32_e32 v0, 12, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s19, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s26, 0x7030602 + v_lshl_or_b32 v3, v4, 7, v0 + v_or_b32_e32 v14, s21, v14 + s_lshr_b32 s29, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s28, 0x3fffffe0 + v_and_or_b32 v2, s29, 32, v37 + v_or_b32_e32 v0, s11, v37 + v_lshrrev_b32_e32 v2, 4, v2 + v_lshrrev_b32_e32 v36, 4, v0 + v_mad_u64_u32 v[14:15], s[28:29], v16, s22, v[14:15] + v_xor_b32_e32 v17, v2, v4 + v_xor_b32_e32 v15, v36, v4 + v_lshl_or_b32 v18, v17, 2, v3 + v_add_u32_e32 v38, s22, v14 + buffer_load_dwordx4 v[28:31], v14, s[12:15], 0 offen + buffer_load_dwordx4 v[32:35], v38, s[12:15], 0 offen + v_add_u32_e32 v14, s22, v38 + v_add_u32_e32 v46, s22, v14 + buffer_load_dwordx4 v[38:41], v14, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v46, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v6, v6, v6, s27 + v_perm_b32 v7, v7, v7, s27 + v_perm_b32 v8, v8, v8, s27 + v_perm_b32 v9, v9, v9, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s27 + v_perm_b32 v11, v11, v11, s27 + v_perm_b32 v12, v12, v12, s27 + v_perm_b32 v13, v13, v13, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v14, v20, v20, s27 + v_perm_b32 v20, v21, v21, s27 + v_perm_b32 v21, v22, v22, s27 + v_perm_b32 v22, v23, v23, s27 + v_perm_b32 v23, v10, v6, s25 + v_perm_b32 v6, v10, v6, s26 + v_perm_b32 v10, v11, v7, s25 + v_perm_b32 v7, v11, v7, s26 + v_perm_b32 v11, v12, v8, s25 + v_perm_b32 v8, v12, v8, s26 + v_perm_b32 v12, v13, v9, s25 + v_perm_b32 v9, v13, v9, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v13, v24, v24, s27 + v_perm_b32 v24, v25, v25, s27 + v_perm_b32 v25, v26, v26, s27 + v_perm_b32 v26, v27, v27, s27 + v_perm_b32 v27, v13, v14, s25 + v_perm_b32 v13, v13, v14, s26 + v_perm_b32 v14, v24, v20, s25 + v_perm_b32 v20, v24, v20, s26 + v_perm_b32 v24, v25, v21, s25 + v_perm_b32 v21, v25, v21, s26 + v_perm_b32 v25, v26, v22, s25 + v_perm_b32 v22, v26, v22, s26 + v_perm_b32 v26, v27, v23, s19 + v_perm_b32 v23, v27, v23, s24 + v_perm_b32 v27, v13, v6, s19 + v_perm_b32 v6, v13, v6, s24 + v_perm_b32 v13, v14, v10, s19 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v20, v7, s19 + v_perm_b32 v7, v20, v7, s24 + v_perm_b32 v20, v24, v11, s19 + v_perm_b32 v11, v24, v11, s24 + v_perm_b32 v24, v21, v8, s19 + v_perm_b32 v8, v21, v8, s24 + v_perm_b32 v21, v25, v12, s19 + v_perm_b32 v12, v25, v12, s24 + v_perm_b32 v25, v22, v9, s19 + v_perm_b32 v9, v22, v9, s24 + v_lshrrev_b32_e32 v22, 1, v16 + v_and_b32_e32 v22, 16, v22 + v_xor_b32_e32 v46, v22, v37 + v_lshlrev_b32_e32 v47, 9, v16 + v_and_b32_e32 v47, 0x3000, v47 + v_lshlrev_b32_e32 v16, 6, v16 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v16, 0xfffff800, v16 + v_add_u32_e32 v16, v47, v16 + v_lshl_or_b32 v16, v46, 2, v16 + ds_write_b32 v16, v26 + v_or_b32_e32 v26, 1, v22 + v_xor_b32_e32 v26, v26, v37 + v_sub_u32_e32 v46, v26, v46 + v_lshl_add_u32 v46, v46, 2, v16 + ds_write_b32 v46, v23 offset:128 + v_or_b32_e32 v23, 2, v22 + v_xor_b32_e32 v23, v23, v37 + v_sub_u32_e32 v26, v23, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v46, s18, v26 + ds_write_b32 v26, v27 offset:128 + v_or_b32_e32 v27, 3, v22 + v_xor_b32_e32 v27, v27, v37 + v_sub_u32_e32 v23, v27, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v26, s18, v23 + ds_write_b32 v23, v6 offset:128 + v_or_b32_e32 v6, 4, v22 + v_xor_b32_e32 v6, v6, v37 + v_sub_u32_e32 v27, v6, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v27, v23, s18, v27 + ds_write_b32 v27, v13 offset:128 + v_or_b32_e32 v13, 5, v22 + v_xor_b32_e32 v13, v13, v37 + v_sub_u32_e32 v6, v13, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v27, s18, v6 + ds_write_b32 v6, v10 offset:128 + v_or_b32_e32 v10, 6, v22 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v13, v10, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v6, s18, v13 + ds_write_b32 v13, v14 offset:128 + v_or_b32_e32 v14, 7, v22 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v13, s18, v10 + ds_write_b32 v10, v7 offset:128 + v_or_b32_e32 v7, 8, v22 + v_xor_b32_e32 v7, v7, v37 + v_sub_u32_e32 v14, v7, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v10, s18, v14 + ds_write_b32 v14, v20 offset:128 + v_or_b32_e32 v20, 9, v22 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v7, v20, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v7, v14, s18, v7 + ds_write_b32 v7, v11 offset:128 + v_or_b32_e32 v11, 10, v22 + v_xor_b32_e32 v11, v11, v37 + v_sub_u32_e32 v20, v11, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v7, s18, v20 + ds_write_b32 v20, v24 offset:128 + v_or_b32_e32 v24, 11, v22 + v_xor_b32_e32 v24, v24, v37 + v_sub_u32_e32 v11, v24, v11 + v_lshlrev_b32_e32 v11, 2, v11 + v_add3_u32 v11, v20, s18, v11 + ds_write_b32 v11, v8 offset:128 + v_or_b32_e32 v8, 12, v22 + v_xor_b32_e32 v8, v8, v37 + v_sub_u32_e32 v24, v8, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v11, s18, v24 + ds_write_b32 v24, v21 offset:128 + v_or_b32_e32 v21, 13, v22 + v_xor_b32_e32 v21, v21, v37 + v_sub_u32_e32 v8, v21, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v8, v24, s18, v8 + ds_write_b32 v8, v12 offset:128 + v_or_b32_e32 v12, 14, v22 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v21, v12, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v8, s18, v21 + ds_write_b32 v21, v25 offset:128 + v_or_b32_e32 v22, 15, v22 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v12, v22, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v21, s18, v12 + ds_write_b32 v12, v9 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v9, v28, v28, s27 + v_perm_b32 v22, v29, v29, s27 + v_perm_b32 v25, v30, v30, s27 + v_perm_b32 v28, v31, v31, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v29, v32, v32, s27 + v_perm_b32 v30, v33, v33, s27 + v_perm_b32 v31, v34, v34, s27 + v_perm_b32 v32, v35, v35, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v33, v38, v38, s27 + v_perm_b32 v34, v39, v39, s27 + v_perm_b32 v35, v40, v40, s27 + v_perm_b32 v38, v41, v41, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v39, v42, v42, s27 + v_perm_b32 v40, v43, v43, s27 + v_perm_b32 v41, v44, v44, s27 + v_perm_b32 v42, v45, v45, s27 + v_perm_b32 v43, v29, v9, s25 + v_perm_b32 v44, v39, v33, s25 + v_perm_b32 v45, v44, v43, s19 + v_perm_b32 v43, v44, v43, s24 + v_perm_b32 v9, v29, v9, s26 + v_perm_b32 v29, v39, v33, s26 + v_perm_b32 v33, v29, v9, s19 + v_perm_b32 v9, v29, v9, s24 + v_perm_b32 v29, v30, v22, s25 + v_perm_b32 v39, v40, v34, s25 + v_perm_b32 v44, v39, v29, s19 + v_perm_b32 v29, v39, v29, s24 + v_perm_b32 v22, v30, v22, s26 + v_perm_b32 v30, v40, v34, s26 + v_perm_b32 v34, v30, v22, s19 + v_perm_b32 v22, v30, v22, s24 + v_perm_b32 v30, v31, v25, s25 + v_perm_b32 v39, v41, v35, s25 + v_perm_b32 v40, v39, v30, s19 + v_perm_b32 v30, v39, v30, s24 + v_perm_b32 v25, v31, v25, s26 + v_perm_b32 v31, v41, v35, s26 + v_perm_b32 v35, v31, v25, s19 + v_perm_b32 v25, v31, v25, s24 + v_perm_b32 v31, v32, v28, s25 + v_perm_b32 v39, v42, v38, s25 + v_perm_b32 v41, v39, v31, s19 + v_perm_b32 v31, v39, v31, s24 + v_perm_b32 v28, v32, v28, s26 + v_perm_b32 v32, v42, v38, s26 + v_perm_b32 v38, v32, v28, s19 + v_perm_b32 v28, v32, v28, s24 + ds_write_b32 v16, v45 offset:16384 + ds_write_b32 v46, v43 offset:16512 + ds_write_b32 v26, v33 offset:16512 + ds_write_b32 v23, v9 offset:16512 + ds_write_b32 v27, v44 offset:16512 + ds_write_b32 v6, v29 offset:16512 + ds_write_b32 v13, v34 offset:16512 + ds_write_b32 v10, v22 offset:16512 + ds_write_b32 v14, v40 offset:16512 + ds_write_b32 v7, v30 offset:16512 + ds_write_b32 v20, v35 offset:16512 + ds_write_b32 v11, v25 offset:16512 + ds_write_b32 v24, v41 offset:16512 + ds_write_b32 v8, v31 offset:16512 + ds_write_b32 v21, v38 offset:16512 + ds_write_b32 v12, v28 offset:16512 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v20, v15, 2, v3 + v_lshrrev_b16_e32 v8, 3, v19 + v_add_u32_e32 v7, 16, v36 + v_xor_b32_e32 v6, v7, v4 + v_sub_u32_e32 v9, v8, v5 + v_lshlrev_b32_e32 v21, 12, v9 + v_lshlrev_b32_e32 v9, 2, v6 + v_add3_u32 v22, v21, v3, v9 + v_add_u32_e32 v3, 16, v19 + v_lshrrev_b32_e32 v9, 5, v3 + v_lshrrev_b16_e32 v3, 3, v3 + v_and_b32_e32 v3, 3, v3 + v_sub_u16_e32 v10, v3, v8 + v_bfe_i32 v10, v10, 0, 16 + v_lshlrev_b32_e32 v11, 4, v9 + v_or_b32_e32 v12, v11, v4 + v_and_b32_e32 v23, 31, v12 + v_xor_b32_e32 v12, v36, v23 + v_sub_u32_e32 v6, v12, v6 + v_lshlrev_b32_e32 v13, 11, v9 + v_lshlrev_b32_e32 v6, 2, v6 + v_lshl_or_b32 v14, v10, 12, v13 + v_add3_u32 v24, v6, v14, v22 + v_add_u32_e32 v6, 20, v19 + v_lshrrev_b32_e32 v10, 5, v6 + v_sub_u32_e32 v9, v10, v9 + v_lshrrev_b16_e32 v6, 3, v6 + v_and_b32_e32 v6, 3, v6 + v_sub_u16_e32 v3, v6, v3 + v_bfe_i32 v3, v3, 0, 16 + v_lshlrev_b32_e32 v16, 4, v10 + v_or_b32_e32 v13, v16, v4 + v_and_b32_e32 v25, 31, v13 + v_xor_b32_e32 v13, v7, v25 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v9, 11, v9 + v_lshlrev_b32_e32 v12, 2, v12 + v_lshl_add_u32 v15, v3, 12, v9 + v_add3_u32 v26, v12, v15, v24 + v_sub_u16_e32 v3, v8, v6 + v_bfe_i32 v3, v3, 0, 16 + v_or_b32_e32 v27, 16, v4 + v_xor_b32_e32 v6, v36, v27 + v_sub_u32_e32 v9, v6, v13 + v_lshlrev_b32_e32 v10, 11, v10 + v_xor_b32_e32 v10, 0x800, v10 + v_lshlrev_b32_e32 v12, 2, v9 + v_lshl_add_u32 v9, v3, 12, v10 + v_add3_u32 v28, v12, v9, v26 + v_xor_b32_e32 v3, v7, v27 + v_sub_u32_e32 v6, v3, v6 + v_lshl_add_u32 v29, v6, 2, v28 + v_add_u32_e32 v6, 48, v19 + v_lshrrev_b32_e32 v10, 5, v6 + v_lshlrev_b32_e32 v12, 11, v10 + v_lshrrev_b16_e32 v6, 3, v6 + v_and_b32_e32 v6, 3, v6 + v_sub_u16_e32 v13, v6, v8 + v_lshlrev_b32_e32 v30, 4, v10 + v_or_b32_e32 v31, v30, v4 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v32, v36, v31 + v_sub_u32_e32 v3, v32, v3 + v_lshlrev_b32_e32 v33, 2, v3 + v_mov_b32_e32 v34, 12 + v_lshlrev_b32_sdwa v3, v34, sext(v13) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v3, v12, v3, s11 + v_add3_u32 v33, v33, v3, v29 + v_add_u32_e32 v12, 52, v19 + v_lshrrev_b32_e32 v19, 5, v12 + v_sub_u32_e32 v10, v19, v10 + v_lshrrev_b16_e32 v12, 3, v12 + v_and_b32_e32 v12, 3, v12 + v_sub_u16_e32 v6, v12, v6 + v_bfe_i32 v13, v6, 0, 16 + v_lshlrev_b32_e32 v35, 4, v19 + v_or_b32_e32 v36, v35, v4 + v_and_b32_e32 v6, 31, v36 + v_xor_b32_e32 v38, v7, v6 + v_sub_u32_e32 v7, v38, v32 + v_lshlrev_b32_e32 v10, 11, v10 + v_lshlrev_b32_e32 v32, 2, v7 + v_lshl_add_u32 v7, v13, 12, v10 + v_add3_u32 v13, v32, v7, v33 + v_add_u32_e32 v10, 64, v0 + v_lshrrev_b32_e32 v32, 4, v10 + v_sub_u16_e32 v8, v8, v12 + v_sub_u32_e32 v12, v36, v35 + v_ashrrev_i32_e32 v10, 31, v12 + v_lshrrev_b32_e32 v10, 27, v10 + v_add_u32_e32 v10, v12, v10 + v_and_b32_e32 v10, 0xffffffe0, v10 + v_sub_u32_e32 v35, v12, v10 + v_xor_b32_e32 v10, v32, v35 + v_sub_u32_e32 v36, v10, v38 + v_lshlrev_b32_e32 v36, 2, v36 + v_lshlrev_b32_sdwa v8, v34, sext(v8) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v19, 11, v19 + v_sub_u32_e32 v34, v8, v19 + v_add3_u32 v19, v36, v34, v13 + v_add_u32_e32 v36, 16, v32 + v_xor_b32_e32 v8, v36, v35 + v_sub_u32_e32 v10, v8, v10 + v_lshl_add_u32 v10, v10, 2, v19 + v_add_u32_e32 v11, v12, v11 + v_ashrrev_i32_e32 v38, 31, v11 + v_lshrrev_b32_e32 v38, 27, v38 + v_add_u32_e32 v38, v11, v38 + v_and_b32_e32 v38, 0xffffffe0, v38 + v_sub_u32_e32 v38, v11, v38 + v_xor_b32_e32 v11, v32, v38 + v_sub_u32_e32 v8, v11, v8 + v_lshl_add_u32 v8, v8, 2, v14 + v_add_u32_e32 v8, v8, v10 + ds_read_b32 v70, v19 + ds_read_b32 v71, v10 + ds_read_b32 v78, v8 + v_add_u32_e32 v10, v12, v16 + v_ashrrev_i32_e32 v16, 31, v10 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v10, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v39, v10, v16 + v_xor_b32_e32 v19, v36, v39 + v_sub_u32_e32 v10, v19, v11 + v_lshl_add_u32 v10, v10, 2, v15 + v_add_u32_e32 v40, v8, v10 + v_add_u32_e32 v11, 16, v12 + v_ashrrev_i32_e32 v16, 31, v11 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v11, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v16, v11, v16 + v_xor_b32_e32 v41, v32, v16 + v_sub_u32_e32 v11, v41, v19 + v_lshl_add_u32 v11, v11, 2, v9 + v_add_u32_e32 v19, v40, v11 + v_xor_b32_e32 v42, v36, v16 + v_add_u32_e32 v12, v12, v30 + v_ashrrev_i32_e32 v30, 31, v12 + v_lshrrev_b32_e32 v30, 27, v30 + v_add_u32_e32 v30, v12, v30 + v_and_b32_e32 v30, 0xffffffe0, v30 + v_sub_u32_e32 v12, v12, v30 + ds_read_b32 v60, v20 + ds_read_b32 v61, v22 + ds_read_b32 v80, v24 + ds_read_b32 v81, v26 + ds_read_b32 v82, v28 + ds_read_b32 v83, v29 + ds_read_b32 v20, v33 + ds_read_b32 v84, v18 offset:16384 + v_or_b32_e32 v22, 16, v2 + v_xor_b32_e32 v24, v22, v4 + v_sub_u32_e32 v17, v24, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v18, v21, v17 + v_xor_b32_e32 v18, v2, v23 + v_sub_u32_e32 v21, v18, v24 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v21, v14, v17 + v_xor_b32_e32 v23, v22, v25 + v_sub_u32_e32 v18, v23, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v18, v15, v21 + v_xor_b32_e32 v24, v2, v27 + v_sub_u32_e32 v23, v24, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v23, v9, v18 + v_xor_b32_e32 v25, v22, v27 + v_sub_u32_e32 v24, v25, v24 + v_lshl_add_u32 v24, v24, 2, v23 + v_xor_b32_e32 v26, v2, v31 + v_sub_u32_e32 v25, v26, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v25, v3, v24 + v_xor_b32_e32 v22, v22, v6 + v_sub_u32_e32 v26, v22, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v26, v7, v25 + ds_read_b32 v85, v17 offset:16384 + ds_read_b32 v86, v21 offset:16384 + ds_read_b32 v87, v18 offset:16384 + ds_read_b32 v88, v23 offset:16384 + ds_read_b32 v89, v24 offset:16384 + ds_read_b32 v90, v25 offset:16384 + ds_read_b32 v91, v26 offset:16384 + v_or_b32_e32 v17, 4, v2 + v_xor_b32_e32 v18, v17, v35 + v_sub_u32_e32 v21, v18, v22 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v21, v34, v26 + v_or_b32_e32 v22, 20, v2 + v_xor_b32_e32 v23, v22, v35 + v_sub_u32_e32 v18, v23, v18 + v_lshl_add_u32 v18, v18, 2, v21 + ds_read_b32 v92, v21 offset:16384 + ds_read_b32 v93, v18 offset:16384 + v_xor_b32_e32 v21, v17, v38 + v_sub_u32_e32 v23, v21, v23 + v_lshl_add_u32 v23, v23, 2, v14 + v_add_u32_e32 v18, v23, v18 + v_xor_b32_e32 v23, v22, v39 + v_sub_u32_e32 v21, v23, v21 + v_lshl_add_u32 v24, v21, 2, v15 + v_add_u32_e32 v21, v18, v24 + v_xor_b32_e32 v25, v17, v16 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v23, v23, 2, v9 + v_add_u32_e32 v26, v21, v23 + v_xor_b32_e32 v27, v22, v16 + v_sub_u32_e32 v25, v27, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add_u32_e32 v28, v26, v25 + v_xor_b32_e32 v17, v17, v12 + v_sub_u32_e32 v27, v17, v27 + v_lshl_add_u32 v27, v27, 2, v3 + v_add_u32_e32 v29, v28, v27 + v_xor_b32_e32 v22, v22, v6 + v_sub_u32_e32 v17, v22, v17 + v_lshl_add_u32 v17, v17, 2, v7 + v_add_u32_e32 v30, v29, v17 + v_or_b32_e32 v31, 8, v2 + v_xor_b32_e32 v33, v31, v35 + v_sub_u32_e32 v22, v33, v22 + v_lshl_add_u32 v22, v22, 2, v34 + v_add_u32_e32 v43, v30, v22 + ds_read_b32 v94, v43 offset:16384 + v_or_b32_e32 v44, 24, v2 + v_xor_b32_e32 v45, v44, v35 + v_sub_u32_e32 v33, v45, v33 + v_lshlrev_b32_e32 v33, 2, v33 + v_add_u32_e32 v43, v43, v33 + ds_read_b32 v95, v43 offset:16384 + v_xor_b32_e32 v46, v31, v38 + v_sub_u32_e32 v45, v46, v45 + v_lshl_add_u32 v45, v45, 2, v14 + v_add_u32_e32 v43, v43, v45 + v_xor_b32_e32 v47, v44, v39 + v_sub_u32_e32 v46, v47, v46 + v_lshl_add_u32 v46, v46, 2, v15 + v_add_u32_e32 v48, v43, v46 + v_xor_b32_e32 v49, v31, v16 + v_sub_u32_e32 v47, v49, v47 + v_lshl_add_u32 v47, v47, 2, v9 + v_add_u32_e32 v50, v48, v47 + v_xor_b32_e32 v51, v44, v16 + v_sub_u32_e32 v49, v51, v49 + v_lshlrev_b32_e32 v49, 2, v49 + v_add_u32_e32 v52, v50, v49 + v_xor_b32_e32 v31, v31, v12 + v_sub_u32_e32 v51, v31, v51 + v_lshl_add_u32 v51, v51, 2, v3 + s_waitcnt lgkmcnt(10) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[60:61], v[84:85], 0 + v_add_u32_e32 v53, v52, v51 + v_xor_b32_e32 v44, v44, v6 + v_sub_u32_e32 v31, v44, v31 + v_lshl_add_u32 v31, v31, 2, v7 + v_add_u32_e32 v54, v53, v31 + v_or_b32_e32 v55, 12, v2 + v_xor_b32_e32 v56, v55, v35 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[60:61], v[92:93], 0 + v_sub_u32_e32 v44, v56, v44 + v_lshl_add_u32 v44, v44, 2, v34 + v_add_u32_e32 v57, v54, v44 + ds_read_b32 v96, v57 offset:16384 + v_or_b32_e32 v2, 28, v2 + v_xor_b32_e32 v58, v2, v35 + v_sub_u32_e32 v56, v58, v56 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[60:61], v[94:95], 0 + v_lshlrev_b32_e32 v56, 2, v56 + v_add_u32_e32 v57, v57, v56 + ds_read_b32 v97, v57 offset:16384 + v_sub_u32_e32 v41, v42, v41 + v_lshlrev_b32_e32 v41, 2, v41 + v_add_u32_e32 v59, v19, v41 + v_xor_b32_e32 v32, v32, v12 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[60:61], v[96:97], 0 + v_sub_u32_e32 v42, v32, v42 + v_lshl_add_u32 v42, v42, 2, v3 + v_add_u32_e32 v60, v59, v42 + v_xor_b32_e32 v36, v36, v6 + v_sub_u32_e32 v32, v36, v32 + v_lshl_add_u32 v32, v32, 2, v7 + v_add_u32_e32 v61, v60, v32 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[70:71], v[84:85], 0 + v_add_u32_e32 v62, 0x80, v0 + v_lshrrev_b32_e32 v62, 4, v62 + v_xor_b32_e32 v63, v62, v35 + v_sub_u32_e32 v36, v63, v36 + v_lshl_add_u32 v36, v36, 2, v34 + v_add_u32_e32 v64, v61, v36 + ds_read_b32 v98, v64 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[70:71], v[92:93], 0 + v_add_u32_e32 v65, 16, v62 + v_xor_b32_e32 v66, v65, v35 + v_sub_u32_e32 v63, v66, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add_u32_e32 v64, v64, v63 + ds_read_b32 v99, v64 + v_xor_b32_e32 v67, v62, v38 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[70:71], v[94:95], 0 + v_sub_u32_e32 v66, v67, v66 + v_lshl_add_u32 v66, v66, 2, v14 + v_add_u32_e32 v64, v64, v66 + v_xor_b32_e32 v68, v65, v39 + v_sub_u32_e32 v67, v68, v67 + v_lshl_add_u32 v67, v67, 2, v15 + v_add_u32_e32 v69, v64, v67 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[70:71], v[96:97], 0 + v_xor_b32_e32 v70, v62, v16 + v_sub_u32_e32 v68, v70, v68 + v_lshl_add_u32 v68, v68, 2, v9 + v_add_u32_e32 v71, v69, v68 + v_xor_b32_e32 v72, v65, v16 + v_sub_u32_e32 v70, v72, v70 + v_lshlrev_b32_e32 v70, 2, v70 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[98:99], v[84:85], 0 + v_add_u32_e32 v73, v71, v70 + v_xor_b32_e32 v62, v62, v12 + v_sub_u32_e32 v72, v62, v72 + v_lshl_add_u32 v72, v72, 2, v3 + v_add_u32_e32 v74, v73, v72 + v_xor_b32_e32 v65, v65, v6 + v_sub_u32_e32 v62, v65, v62 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[98:99], v[92:93], 0 + v_lshl_add_u32 v62, v62, 2, v7 + v_add_u32_e32 v75, v74, v62 + v_add_u32_e32 v0, 0xc0, v0 + v_lshrrev_b32_e32 v0, 4, v0 + v_xor_b32_e32 v76, v0, v35 + v_sub_u32_e32 v65, v76, v65 + v_lshl_add_u32 v34, v65, 2, v34 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[98:99], v[94:95], 0 + v_add_u32_e32 v65, v75, v34 + ds_read_b32 v100, v65 + v_add_u32_e32 v77, 16, v0 + v_xor_b32_e32 v35, v77, v35 + v_sub_u32_e32 v76, v35, v76 + v_lshlrev_b32_e32 v76, 2, v76 + v_add_u32_e32 v65, v65, v76 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[98:99], v[96:97], 0 + ds_read_b32 v101, v65 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[100:101], v[84:85], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[100:101], v[92:93], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[100:101], v[94:95], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[100:101], v[96:97], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[80:81], v[86:87], a[224:239] + ds_read_b32 v84, v18 offset:16384 + ds_read_b32 v85, v21 offset:16384 + ds_read_b32 v92, v43 offset:16384 + ds_read_b32 v93, v48 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[80:81], v[84:85], a[208:223] + v_xor_b32_e32 v21, v55, v38 + v_sub_u32_e32 v43, v21, v58 + v_lshl_add_u32 v43, v43, 2, v14 + v_add_u32_e32 v48, v57, v43 + ds_read_b32 v94, v48 offset:16384 + v_xor_b32_e32 v57, v2, v39 + v_sub_u32_e32 v21, v57, v21 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[80:81], v[92:93], a[192:207] + v_lshl_add_u32 v58, v21, 2, v15 + v_add_u32_e32 v21, v48, v58 + ds_read_b32 v95, v21 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[80:81], v[94:95], a[176:191] + ds_read_b32 v79, v40 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[78:79], v[86:87], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[78:79], v[84:85], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[78:79], v[92:93], a[128:143] + ds_read_b32 v80, v64 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[78:79], v[94:95], a[112:127] + ds_read_b32 v81, v69 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[80:81], v[86:87], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[80:81], v[84:85], a[80:95] + v_xor_b32_e32 v38, v0, v38 + v_sub_u32_e32 v35, v38, v35 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[80:81], v[92:93], a[64:79] + v_lshl_add_u32 v14, v35, 2, v14 + v_add_u32_e32 v35, v65, v14 + ds_read_b32 v64, v35 + v_xor_b32_e32 v39, v77, v39 + v_sub_u32_e32 v38, v39, v38 + v_lshl_add_u32 v15, v38, 2, v15 + v_add_u32_e32 v35, v35, v15 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[80:81], v[94:95], a[48:63] + ds_read_b32 v65, v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[64:65], v[86:87], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[64:65], v[84:85], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[64:65], v[92:93], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[64:65], v[94:95], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[82:83], v[88:89], a[224:239] + ds_read_b32 v64, v26 offset:16384 + ds_read_b32 v65, v28 offset:16384 + ds_read_b32 v78, v50 offset:16384 + ds_read_b32 v79, v52 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[82:83], v[64:65], a[208:223] + v_xor_b32_e32 v26, v55, v16 + v_sub_u32_e32 v28, v26, v57 + v_lshl_add_u32 v28, v28, 2, v9 + v_add_u32_e32 v21, v21, v28 + ds_read_b32 v80, v21 offset:16384 + v_xor_b32_e32 v38, v2, v16 + v_sub_u32_e32 v26, v38, v26 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[82:83], v[78:79], a[192:207] + v_lshlrev_b32_e32 v26, 2, v26 + v_add_u32_e32 v40, v21, v26 + ds_read_b32 v81, v40 offset:16384 + ds_read_b32 v84, v19 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[82:83], v[80:81], a[176:191] + ds_read_b32 v85, v59 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[84:85], v[88:89], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[84:85], v[64:65], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[84:85], v[78:79], a[128:143] + ds_read_b32 v82, v71 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[84:85], v[80:81], a[112:127] + ds_read_b32 v83, v73 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[82:83], v[88:89], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[82:83], v[64:65], a[80:95] + v_xor_b32_e32 v19, v0, v16 + v_sub_u32_e32 v21, v19, v39 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[82:83], v[78:79], a[64:79] + v_lshl_add_u32 v9, v21, 2, v9 + v_add_u32_e32 v21, v35, v9 + ds_read_b32 v84, v21 + v_xor_b32_e32 v16, v77, v16 + v_sub_u32_e32 v19, v16, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add_u32_e32 v35, v21, v19 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[82:83], v[80:81], a[48:63] + ds_read_b32 v85, v35 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[84:85], v[88:89], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[84:85], v[64:65], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[84:85], v[78:79], a[0:15] + ds_read_b32 v21, v13 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[84:85], v[80:81], a[240:255] + v_add3_u32 v13, v24, v18, v23 + v_add3_u32 v13, v25, v13, v27 + ds_read_b32 v24, v29 offset:16384 + ds_read_b32 v25, v30 offset:16384 + v_add3_u32 v13, v17, v13, v22 + v_add3_u32 v13, v13, v33, v45 + v_add3_u32 v13, v46, v13, v47 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[20:21], v[90:91], a[224:239] + v_add3_u32 v13, v49, v13, v51 + ds_read_b32 v22, v53 offset:16384 + ds_read_b32 v23, v54 offset:16384 + v_add3_u32 v13, v31, v13, v44 + v_add3_u32 v13, v13, v56, v43 + v_add3_u32 v13, v58, v13, v28 + v_xor_b32_e32 v17, v55, v12 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[20:21], v[24:25], a[208:223] + v_sub_u32_e32 v18, v17, v38 + v_lshl_add_u32 v18, v18, 2, v3 + v_add3_u32 v13, v26, v13, v18 + v_add_u32_e32 v18, v40, v18 + ds_read_b32 v26, v18 offset:16384 + v_xor_b32_e32 v2, v2, v6 + v_sub_u32_e32 v2, v2, v17 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[20:21], v[22:23], a[192:207] + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v2, v7, v13 + ds_read_b32 v27, v2 offset:16384 + ds_read_b32 v28, v60 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[20:21], v[26:27], a[176:191] + ds_read_b32 v29, v61 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[28:29], v[90:91], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[28:29], v[24:25], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[28:29], v[22:23], a[128:143] + ds_read_b32 v20, v74 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[28:29], v[26:27], a[112:127] + ds_read_b32 v21, v75 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[20:21], v[90:91], a[96:111] + v_add3_u32 v2, v10, v8, v11 + v_add3_u32 v2, v41, v2, v42 + v_add3_u32 v2, v32, v2, v36 + v_add3_u32 v2, v2, v63, v66 + v_add3_u32 v2, v67, v2, v68 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[20:21], v[24:25], a[80:95] + v_add3_u32 v2, v70, v2, v72 + v_add3_u32 v2, v62, v2, v34 + v_add3_u32 v2, v2, v76, v14 + v_add3_u32 v2, v15, v2, v9 + v_xor_b32_e32 v0, v0, v12 + v_sub_u32_e32 v8, v0, v16 + v_lshl_add_u32 v3, v8, 2, v3 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[20:21], v[22:23], a[64:79] + v_add3_u32 v2, v19, v2, v3 + v_xor_b32_e32 v6, v77, v6 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v0, v0, v7, v2 + ds_read_b32 v7, v0 + v_add_u32_e32 v0, v35, v3 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[20:21], v[26:27], a[48:63] + ds_read_b32 v6, v0 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[6:7], v[90:91], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[6:7], v[24:25], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[6:7], v[22:23], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[6:7], v[26:27], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB27_3 + s_branch .LBB27_10 +.LBB27_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB27_3: + v_readfirstlane_b32 s15, v227 + v_lshlrev_b32_e32 v2, 4, v4 + s_lshr_b32 s26, s15, 2 + v_mov_b32_e32 v0, s26 + v_and_b32_e32 v1, 0x3ffffffc, v1 + v_and_b32_e32 v0, 0x3ffffff0, v0 + v_add_u32_e32 v9, v0, v1 + v_or_b32_e32 v0, s20, v2 + v_mad_u64_u32 v[34:35], s[18:19], v9, s23, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[14:17], v34, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v34 + buffer_load_dwordx4 v[18:21], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[22:25], v0, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 12, v5 + v_lshlrev_b32_e32 v11, 3, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s24, 0x5010400 + s_mov_b32 s18, 0x5040100 + s_mov_b32 s19, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_lshl_or_b32 v13, v4, 7, v0 + v_or_b32_e32 v0, s21, v2 + s_lshr_b32 s28, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s29, s26, 0x3ffffff0 + s_and_b32 s26, s26, 0x3fffffe0 + v_and_or_b32 v2, s28, 32, v37 + v_or_b32_e32 v7, s26, v37 + v_add_u32_e32 v3, s29, v1 + v_lshrrev_b32_e32 v6, 4, v2 + v_lshrrev_b32_e32 v8, 4, v7 + v_mad_u64_u32 v[2:3], s[28:29], v3, s22, v[0:1] + v_xor_b32_e32 v3, v6, v4 + v_xor_b32_e32 v0, v8, v4 + v_lshl_or_b32 v56, v3, 2, v13 + v_add_u32_e32 v10, s22, v2 + buffer_load_dwordx4 v[30:33], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[38:41], v10, s[12:15], 0 offen + v_add_u32_e32 v10, s22, v10 + v_add_u32_e32 v12, s22, v10 + buffer_load_dwordx4 v[42:45], v10, s[12:15], 0 offen + buffer_load_dwordx4 v[46:49], v12, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v14, v14, s27 + v_perm_b32 v12, v15, v15, s27 + v_perm_b32 v14, v16, v16, s27 + v_perm_b32 v15, v17, v17, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v16, v18, v18, s27 + v_perm_b32 v17, v19, v19, s27 + v_perm_b32 v18, v20, v20, s27 + v_perm_b32 v19, v21, v21, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v20, v22, v22, s27 + v_perm_b32 v21, v23, v23, s27 + v_perm_b32 v22, v24, v24, s27 + v_perm_b32 v23, v25, v25, s27 + v_perm_b32 v24, v16, v10, s24 + v_perm_b32 v10, v16, v10, s25 + v_perm_b32 v16, v17, v12, s24 + v_perm_b32 v12, v17, v12, s25 + v_perm_b32 v17, v18, v14, s24 + v_perm_b32 v14, v18, v14, s25 + v_perm_b32 v18, v19, v15, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v25, v26, v26, s27 + v_perm_b32 v26, v27, v27, s27 + v_perm_b32 v27, v28, v28, s27 + v_perm_b32 v28, v29, v29, s27 + v_perm_b32 v29, v25, v20, s24 + v_perm_b32 v20, v25, v20, s25 + v_perm_b32 v25, v26, v21, s24 + v_perm_b32 v21, v26, v21, s25 + v_perm_b32 v26, v27, v22, s24 + v_perm_b32 v22, v27, v22, s25 + v_perm_b32 v27, v28, v23, s24 + v_perm_b32 v35, v29, v24, s18 + v_perm_b32 v24, v29, v24, s19 + v_perm_b32 v29, v20, v10, s18 + v_perm_b32 v10, v20, v10, s19 + v_perm_b32 v20, v25, v16, s18 + v_perm_b32 v16, v25, v16, s19 + v_perm_b32 v25, v21, v12, s18 + v_perm_b32 v12, v21, v12, s19 + v_perm_b32 v21, v26, v17, s18 + v_perm_b32 v17, v26, v17, s19 + v_perm_b32 v26, v22, v14, s18 + v_perm_b32 v14, v22, v14, s19 + v_perm_b32 v22, v27, v18, s18 + v_perm_b32 v18, v27, v18, s19 + v_perm_b32 v15, v19, v15, s25 + v_perm_b32 v19, v28, v23, s25 + v_perm_b32 v23, v19, v15, s18 + v_perm_b32 v15, v19, v15, s19 + v_lshrrev_b32_e32 v19, 1, v9 + v_and_b32_e32 v19, 16, v19 + v_xor_b32_e32 v27, v19, v37 + v_lshlrev_b32_e32 v28, 9, v9 + v_and_b32_e32 v28, 0x3000, v28 + v_lshlrev_b32_e32 v9, 6, v9 + s_movk_i32 s26, 0xf800 + v_and_b32_e32 v9, 0xfffff800, v9 + v_add_u32_e32 v9, v28, v9 + v_lshl_or_b32 v9, v27, 2, v9 + ds_write_b32 v9, v35 + v_or_b32_e32 v28, 1, v19 + v_xor_b32_e32 v28, v28, v37 + v_sub_u32_e32 v27, v28, v27 + v_lshl_add_u32 v27, v27, 2, v9 + ds_write_b32 v27, v24 offset:128 + v_or_b32_e32 v24, 2, v19 + v_xor_b32_e32 v24, v24, v37 + v_sub_u32_e32 v28, v24, v28 + v_lshlrev_b32_e32 v28, 2, v28 + s_movk_i32 s28, 0x80 + v_add3_u32 v28, v27, s28, v28 + ds_write_b32 v28, v29 offset:128 + v_or_b32_e32 v29, 3, v19 + v_xor_b32_e32 v29, v29, v37 + v_sub_u32_e32 v24, v29, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v28, s28, v24 + ds_write_b32 v24, v10 offset:128 + v_or_b32_e32 v10, 4, v19 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v29, v10, v29 + v_lshlrev_b32_e32 v29, 2, v29 + v_add3_u32 v29, v24, s28, v29 + ds_write_b32 v29, v20 offset:128 + v_or_b32_e32 v20, 5, v19 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v10, v20, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v29, s28, v10 + ds_write_b32 v10, v16 offset:128 + v_or_b32_e32 v16, 6, v19 + v_xor_b32_e32 v16, v16, v37 + v_sub_u32_e32 v20, v16, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v10, s28, v20 + ds_write_b32 v20, v25 offset:128 + v_or_b32_e32 v25, 7, v19 + v_xor_b32_e32 v25, v25, v37 + v_sub_u32_e32 v16, v25, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v20, s28, v16 + ds_write_b32 v16, v12 offset:128 + v_or_b32_e32 v12, 8, v19 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v25, v12, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v16, s28, v25 + ds_write_b32 v25, v21 offset:128 + v_or_b32_e32 v21, 9, v19 + v_xor_b32_e32 v21, v21, v37 + v_sub_u32_e32 v12, v21, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v25, s28, v12 + ds_write_b32 v12, v17 offset:128 + v_or_b32_e32 v17, 10, v19 + v_xor_b32_e32 v17, v17, v37 + v_sub_u32_e32 v21, v17, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v12, s28, v21 + ds_write_b32 v21, v26 offset:128 + v_or_b32_e32 v26, 11, v19 + v_xor_b32_e32 v26, v26, v37 + v_sub_u32_e32 v17, v26, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v21, s28, v17 + ds_write_b32 v17, v14 offset:128 + v_or_b32_e32 v14, 12, v19 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v26, v14, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v17, s28, v26 + ds_write_b32 v26, v22 offset:128 + v_or_b32_e32 v22, 13, v19 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v14, v22, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v26, s28, v14 + ds_write_b32 v14, v18 offset:128 + v_or_b32_e32 v18, 14, v19 + v_xor_b32_e32 v18, v18, v37 + v_sub_u32_e32 v22, v18, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v14, s28, v22 + ds_write_b32 v22, v23 offset:128 + v_or_b32_e32 v19, 15, v19 + v_xor_b32_e32 v19, v19, v37 + v_sub_u32_e32 v18, v19, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v22, s28, v18 + ds_write_b32 v18, v15 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v15, v30, v30, s27 + v_perm_b32 v19, v31, v31, s27 + v_perm_b32 v23, v32, v32, s27 + v_perm_b32 v30, v33, v33, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v31, v38, v38, s27 + v_perm_b32 v32, v39, v39, s27 + v_perm_b32 v33, v40, v40, s27 + v_perm_b32 v35, v41, v41, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v36, v42, v42, s27 + v_perm_b32 v38, v43, v43, s27 + v_perm_b32 v39, v44, v44, s27 + v_perm_b32 v40, v45, v45, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v41, v46, v46, s27 + v_perm_b32 v42, v47, v47, s27 + v_perm_b32 v43, v48, v48, s27 + v_perm_b32 v44, v49, v49, s27 + v_perm_b32 v45, v31, v15, s24 + v_perm_b32 v46, v41, v36, s24 + v_perm_b32 v47, v46, v45, s18 + v_perm_b32 v45, v46, v45, s19 + v_perm_b32 v15, v31, v15, s25 + v_perm_b32 v31, v41, v36, s25 + v_perm_b32 v36, v31, v15, s18 + v_perm_b32 v15, v31, v15, s19 + v_perm_b32 v31, v32, v19, s24 + v_perm_b32 v41, v42, v38, s24 + v_perm_b32 v46, v41, v31, s18 + v_perm_b32 v31, v41, v31, s19 + v_perm_b32 v19, v32, v19, s25 + v_perm_b32 v32, v42, v38, s25 + v_perm_b32 v38, v32, v19, s18 + v_perm_b32 v19, v32, v19, s19 + v_perm_b32 v32, v33, v23, s24 + v_perm_b32 v41, v43, v39, s24 + v_perm_b32 v42, v41, v32, s18 + v_perm_b32 v32, v41, v32, s19 + v_perm_b32 v23, v33, v23, s25 + v_perm_b32 v33, v43, v39, s25 + v_perm_b32 v39, v33, v23, s18 + v_perm_b32 v23, v33, v23, s19 + v_perm_b32 v33, v35, v30, s24 + v_perm_b32 v41, v44, v40, s24 + v_perm_b32 v43, v41, v33, s18 + v_perm_b32 v33, v41, v33, s19 + v_perm_b32 v30, v35, v30, s25 + v_perm_b32 v35, v44, v40, s25 + v_perm_b32 v40, v35, v30, s18 + v_perm_b32 v30, v35, v30, s19 + ds_write_b32 v9, v47 offset:16384 + ds_write_b32 v27, v45 offset:16512 + ds_write_b32 v28, v36 offset:16512 + ds_write_b32 v24, v15 offset:16512 + ds_write_b32 v29, v46 offset:16512 + ds_write_b32 v10, v31 offset:16512 + ds_write_b32 v20, v38 offset:16512 + ds_write_b32 v16, v19 offset:16512 + ds_write_b32 v25, v42 offset:16512 + ds_write_b32 v12, v32 offset:16512 + ds_write_b32 v21, v39 offset:16512 + ds_write_b32 v17, v23 offset:16512 + ds_write_b32 v26, v43 offset:16512 + ds_write_b32 v14, v33 offset:16512 + ds_write_b32 v22, v40 offset:16512 + ds_write_b32 v18, v30 offset:16512 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v18, 3, v11 + v_add_u32_e32 v19, 16, v8 + v_add_u32_e32 v25, 16, v11 + v_add_u32_e32 v24, 20, v11 + v_or_b32_e32 v10, 16, v4 + v_add_u32_e32 v23, 36, v11 + v_add_u32_e32 v22, 48, v11 + v_add_u32_e32 v21, 52, v11 + v_add_u32_e32 v20, 64, v7 + v_or_b32_e32 v17, 16, v6 + v_or_b32_e32 v16, 4, v6 + v_or_b32_e32 v15, 20, v6 + v_or_b32_e32 v14, 8, v6 + v_or_b32_e32 v12, 24, v6 + v_or_b32_e32 v11, 12, v6 + v_or_b32_e32 v9, 28, v6 + s_cbranch_vccnz .LBB27_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit1774.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v26, v19, v4 + v_sub_u32_e32 v27, v18, v5 + v_lshlrev_b32_e32 v27, 12, v27 + v_lshlrev_b32_e32 v28, 2, v26 + v_add3_u32 v78, v27, v13, v28 + v_lshrrev_b32_e32 v28, 5, v25 + v_lshrrev_b16_e32 v29, 3, v25 + v_and_b32_e32 v29, 3, v29 + v_sub_u16_e32 v30, v29, v18 + v_bfe_i32 v30, v30, 0, 16 + v_lshl_or_b32 v31, v28, 4, v4 + v_xor_b32_e32 v32, v8, v31 + v_sub_u32_e32 v26, v32, v26 + v_lshlrev_b32_e32 v33, 11, v28 + v_lshlrev_b32_e32 v26, 2, v26 + v_lshl_or_b32 v30, v30, 12, v33 + v_add3_u32 v44, v26, v30, v78 + v_lshrrev_b32_e32 v26, 5, v24 + v_sub_u32_e32 v28, v26, v28 + v_lshrrev_b16_e32 v33, 3, v24 + v_and_b32_e32 v33, 3, v33 + v_sub_u16_e32 v29, v33, v29 + v_bfe_i32 v29, v29, 0, 16 + v_lshl_or_b32 v35, v26, 4, v4 + v_xor_b32_e32 v36, v19, v35 + v_sub_u32_e32 v32, v36, v32 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v32, 2, v32 + v_lshl_add_u32 v28, v29, 12, v28 + v_add3_u32 v45, v32, v28, v44 + v_sub_u16_e32 v29, v18, v33 + v_bfe_i32 v29, v29, 0, 16 + v_xor_b32_e32 v32, v8, v10 + v_sub_u32_e32 v33, v32, v36 + v_lshlrev_b32_e32 v26, 11, v26 + v_xor_b32_e32 v26, 0x800, v26 + v_lshlrev_b32_e32 v33, 2, v33 + v_lshl_or_b32 v26, v29, 12, v26 + v_add3_u32 v40, v33, v26, v45 + v_lshrrev_b32_e32 v29, 5, v23 + v_lshlrev_b32_e32 v33, 11, v29 + v_lshrrev_b16_e32 v36, 3, v23 + v_and_b32_e32 v36, 3, v36 + v_sub_u16_e32 v38, v36, v18 + v_lshl_or_b32 v39, v29, 4, v4 + v_and_b32_e32 v75, 31, v39 + v_xor_b32_e32 v39, v19, v75 + v_sub_u32_e32 v32, v39, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_mov_b32_e32 v42, 12 + v_lshlrev_b32_sdwa v38, v42, sext(v38) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v33, v33, v38, s26 + v_add3_u32 v41, v32, v33, v40 + v_lshrrev_b32_e32 v32, 5, v22 + v_sub_u32_e32 v29, v32, v29 + v_lshrrev_b16_e32 v38, 3, v22 + v_and_b32_e32 v43, 3, v38 + v_sub_u16_e32 v36, v43, v36 + v_bfe_i32 v36, v36, 0, 16 + v_lshl_or_b32 v38, v32, 4, v4 + v_and_b32_e32 v76, 31, v38 + v_xor_b32_e32 v46, v8, v76 + v_sub_u32_e32 v38, v46, v39 + v_lshlrev_b32_e32 v29, 11, v29 + v_lshlrev_b32_e32 v38, 2, v38 + v_lshl_add_u32 v29, v36, 12, v29 + v_add3_u32 v38, v38, v29, v41 + v_lshrrev_b32_e32 v36, 5, v21 + v_sub_u32_e32 v32, v36, v32 + v_lshrrev_b16_e32 v39, 3, v21 + v_and_b32_e32 v47, 3, v39 + v_sub_u16_e32 v39, v47, v43 + v_bfe_i32 v39, v39, 0, 16 + v_lshl_or_b32 v43, v36, 4, v4 + v_and_b32_e32 v97, 31, v43 + v_xor_b32_e32 v43, v19, v97 + v_sub_u32_e32 v46, v43, v46 + v_lshlrev_b32_e32 v32, 11, v32 + v_lshlrev_b32_e32 v46, 2, v46 + v_lshl_add_u32 v32, v39, 12, v32 + v_add3_u32 v39, v46, v32, v38 + v_lshrrev_b32_e32 v46, 4, v20 + v_sub_u16_e32 v47, v18, v47 + v_xor_b32_e32 v48, v46, v4 + v_sub_u32_e32 v43, v48, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_lshlrev_b32_sdwa v42, v42, sext(v47) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v36, 11, v36 + v_sub_u32_e32 v36, v42, v36 + v_add3_u32 v88, v43, v36, v39 + v_add_u32_e32 v43, 16, v46 + v_xor_b32_e32 v42, v43, v4 + v_sub_u32_e32 v47, v42, v48 + v_lshl_add_u32 v89, v47, 2, v88 + v_xor_b32_e32 v47, v46, v31 + v_sub_u32_e32 v42, v47, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v53, v42, v30, v89 + v_xor_b32_e32 v42, v43, v35 + v_sub_u32_e32 v47, v42, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v55, v47, v28, v53 + v_xor_b32_e32 v47, v46, v10 + v_sub_u32_e32 v42, v47, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v48, v42, v26, v55 + v_xor_b32_e32 v42, v43, v75 + v_sub_u32_e32 v47, v42, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v49, v47, v33, v48 + v_xor_b32_e32 v46, v46, v76 + v_sub_u32_e32 v42, v46, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v42, v42, v29, v49 + v_xor_b32_e32 v47, v43, v97 + v_sub_u32_e32 v43, v47, v46 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v43, v43, v32, v42 + v_add_u32_e32 v46, 0x80, v7 + v_lshrrev_b32_e32 v46, 4, v46 + v_xor_b32_e32 v50, v46, v4 + v_sub_u32_e32 v47, v50, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v90, v47, v36, v43 + v_add_u32_e32 v47, 16, v46 + v_xor_b32_e32 v51, v47, v4 + v_sub_u32_e32 v50, v51, v50 + v_lshl_add_u32 v91, v50, 2, v90 + v_xor_b32_e32 v50, v46, v31 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v59, v51, v30, v91 + v_xor_b32_e32 v51, v47, v35 + v_sub_u32_e32 v50, v51, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v62, v50, v28, v59 + v_xor_b32_e32 v50, v46, v10 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v52, v51, v26, v62 + v_xor_b32_e32 v51, v47, v75 + v_sub_u32_e32 v50, v51, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v54, v50, v33, v52 + v_xor_b32_e32 v50, v46, v76 + v_sub_u32_e32 v46, v50, v51 + v_lshlrev_b32_e32 v46, 2, v46 + v_add3_u32 v46, v46, v29, v54 + v_xor_b32_e32 v51, v47, v97 + v_sub_u32_e32 v47, v51, v50 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v47, v47, v32, v46 + v_add_u32_e32 v50, 0xc0, v7 + v_lshrrev_b32_e32 v50, 4, v50 + v_xor_b32_e32 v57, v50, v4 + v_sub_u32_e32 v51, v57, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v92, v51, v36, v47 + v_add_u32_e32 v58, 16, v50 + v_xor_b32_e32 v51, v58, v4 + v_sub_u32_e32 v57, v51, v57 + v_lshl_add_u32 v93, v57, 2, v92 + v_xor_b32_e32 v57, v50, v31 + v_sub_u32_e32 v51, v57, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v64, v51, v30, v93 + v_xor_b32_e32 v51, v58, v35 + v_sub_u32_e32 v57, v51, v57 + v_lshlrev_b32_e32 v57, 2, v57 + v_add3_u32 v66, v57, v28, v64 + v_xor_b32_e32 v60, v50, v10 + v_sub_u32_e32 v51, v60, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v57, v51, v26, v66 + v_xor_b32_e32 v51, v58, v75 + v_sub_u32_e32 v60, v51, v60 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v60, v60, v33, v57 + v_xor_b32_e32 v50, v50, v76 + v_sub_u32_e32 v51, v50, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v51, v51, v29, v60 + v_xor_b32_e32 v58, v58, v97 + v_sub_u32_e32 v50, v58, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v50, v50, v32, v51 + v_xor_b32_e32 v58, v17, v4 + v_sub_u32_e32 v61, v58, v3 + v_lshlrev_b32_e32 v61, 2, v61 + v_add3_u32 v94, v56, v27, v61 + v_xor_b32_e32 v27, v6, v31 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v73, v58, v30, v94 + v_xor_b32_e32 v58, v17, v35 + v_sub_u32_e32 v27, v58, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v74, v27, v28, v73 + v_xor_b32_e32 v27, v6, v10 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v67, v58, v26, v74 + v_xor_b32_e32 v58, v17, v75 + v_sub_u32_e32 v27, v58, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v68, v27, v33, v67 + v_xor_b32_e32 v27, v6, v76 + v_sub_u32_e32 v58, v27, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v58, v58, v29, v68 + v_xor_b32_e32 v63, v17, v97 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v61, v27, v32, v58 + v_xor_b32_e32 v27, v16, v4 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v95, v63, v36, v61 + v_xor_b32_e32 v63, v15, v4 + v_sub_u32_e32 v27, v63, v27 + v_lshl_add_u32 v96, v27, 2, v95 + v_xor_b32_e32 v27, v16, v31 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v80, v63, v30, v96 + v_xor_b32_e32 v63, v15, v35 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v81, v27, v28, v80 + v_xor_b32_e32 v27, v16, v10 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v71, v63, v26, v81 + v_xor_b32_e32 v63, v15, v75 + v_sub_u32_e32 v27, v63, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v72, v27, v33, v71 + v_xor_b32_e32 v27, v16, v76 + v_sub_u32_e32 v63, v27, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v63, v63, v29, v72 + v_xor_b32_e32 v69, v15, v97 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v65, v27, v32, v63 + v_xor_b32_e32 v27, v14, v4 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v98, v69, v36, v65 + v_xor_b32_e32 v69, v12, v4 + v_sub_u32_e32 v27, v69, v27 + v_lshl_add_u32 v99, v27, 2, v98 + v_xor_b32_e32 v27, v14, v31 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v84, v69, v30, v99 + v_xor_b32_e32 v69, v12, v35 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v85, v27, v28, v84 + v_xor_b32_e32 v27, v14, v10 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v77, v69, v26, v85 + v_xor_b32_e32 v69, v12, v75 + v_sub_u32_e32 v27, v69, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v79, v27, v33, v77 + v_xor_b32_e32 v27, v14, v76 + v_sub_u32_e32 v69, v27, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v69, v69, v29, v79 + v_xor_b32_e32 v82, v12, v97 + v_sub_u32_e32 v27, v82, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v70, v27, v32, v69 + v_xor_b32_e32 v27, v11, v4 + v_sub_u32_e32 v82, v27, v82 + v_lshlrev_b32_e32 v82, 2, v82 + v_add3_u32 v100, v82, v36, v70 + v_xor_b32_e32 v36, v9, v4 + v_sub_u32_e32 v27, v36, v27 + v_lshl_add_u32 v101, v27, 2, v100 + v_xor_b32_e32 v27, v11, v31 + v_sub_u32_e32 v31, v27, v36 + v_lshlrev_b32_e32 v31, 2, v31 + v_add3_u32 v86, v31, v30, v101 + v_xor_b32_e32 v30, v9, v35 + v_sub_u32_e32 v27, v30, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v87, v27, v28, v86 + v_xor_b32_e32 v27, v11, v10 + v_sub_u32_e32 v28, v27, v30 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v82, v28, v26, v87 + v_xor_b32_e32 v26, v9, v75 + v_sub_u32_e32 v27, v26, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v83, v27, v33, v82 + v_xor_b32_e32 v27, v11, v76 + v_sub_u32_e32 v26, v27, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v75, v26, v29, v83 + v_xor_b32_e32 v26, v9, v97 + v_sub_u32_e32 v26, v26, v27 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v76, v26, v32, v75 + s_mov_b64 s[2:3], 0 + s_branch .LBB27_6 +.LBB27_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 +.LBB27_6: ; %Flow120 + v_lshl_add_u32 v97, v0, 2, v13 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_cbranch_vccnz .LBB27_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2753.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v35, v2 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s18, s6, 6 + s_lshl_b32 s2, s22, 6 + s_lshl_b32 s3, s23, 6 + v_xor_b32_e32 v0, v19, v4 + v_sub_u32_e32 v2, v18, v5 + v_lshlrev_b32_e32 v2, 12, v2 + v_lshlrev_b32_e32 v5, 2, v0 + v_add3_u32 v78, v2, v13, v5 + v_lshrrev_b32_e32 v5, 5, v25 + v_lshrrev_b16_e32 v13, 3, v25 + v_and_b32_e32 v13, 3, v13 + v_sub_u16_e32 v25, v13, v18 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v26, v5, 4, v4 + v_xor_b32_e32 v27, v8, v26 + v_sub_u32_e32 v0, v27, v0 + v_lshlrev_b32_e32 v28, 11, v5 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v25, v25, 12, v28 + v_add3_u32 v44, v0, v25, v78 + v_lshrrev_b32_e32 v0, 5, v24 + v_sub_u32_e32 v5, v0, v5 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v13, v24, v13 + v_bfe_i32 v13, v13, 0, 16 + v_lshl_or_b32 v28, v0, 4, v4 + v_xor_b32_e32 v29, v19, v28 + v_sub_u32_e32 v27, v29, v27 + v_lshlrev_b32_e32 v5, 11, v5 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_add_u32 v5, v13, 12, v5 + v_add3_u32 v45, v27, v5, v44 + v_sub_u16_e32 v13, v18, v24 + v_bfe_i32 v13, v13, 0, 16 + v_xor_b32_e32 v24, v8, v10 + v_sub_u32_e32 v27, v24, v29 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_or_b32 v0, v13, 12, v0 + v_add3_u32 v40, v27, v0, v45 + v_lshrrev_b32_e32 v13, 5, v23 + v_lshlrev_b32_e32 v27, 11, v13 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v29, v23, v18 + v_lshl_or_b32 v30, v13, 4, v4 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v31, v19, v30 + v_sub_u32_e32 v24, v31, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_mov_b32_e32 v32, 12 + v_lshlrev_b32_sdwa v29, v32, sext(v29) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v27, v27, v29, s6 + v_add3_u32 v41, v24, v27, v40 + v_lshrrev_b32_e32 v24, 5, v22 + v_sub_u32_e32 v13, v24, v13 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v23, v22, v23 + v_bfe_i32 v23, v23, 0, 16 + v_lshl_or_b32 v29, v24, 4, v4 + v_and_b32_e32 v29, 31, v29 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v31, v8, v31 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_add_u32 v13, v23, 12, v13 + v_add3_u32 v38, v31, v13, v41 + v_lshrrev_b32_e32 v23, 5, v21 + v_sub_u32_e32 v24, v23, v24 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v22, v21, v22 + v_bfe_i32 v22, v22, 0, 16 + v_lshl_or_b32 v31, v23, 4, v4 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v24, 11, v24 + v_lshlrev_b32_e32 v8, 2, v8 + v_lshl_add_u32 v22, v22, 12, v24 + v_add3_u32 v39, v8, v22, v38 + v_lshrrev_b32_e32 v8, 4, v20 + v_sub_u16_e32 v18, v18, v21 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshlrev_b32_sdwa v18, v32, sext(v18) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v21, 11, v23 + v_sub_u32_e32 v18, v18, v21 + v_add3_u32 v88, v19, v18, v39 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v89, v20, 2, v88 + v_xor_b32_e32 v20, v8, v26 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v53, v21, v25, v89 + v_xor_b32_e32 v21, v19, v28 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v55, v20, v5, v53 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v48, v21, v0, v55 + v_xor_b32_e32 v21, v19, v30 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v49, v20, v27, v48 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v42, v20, v13, v49 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v43, v8, v22, v42 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v8, 0x80, v7 + v_lshrrev_b32_e32 v8, 4, v8 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v90, v19, v18, v43 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v91, v20, 2, v90 + v_xor_b32_e32 v20, v8, v26 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v59, v21, v25, v91 + v_xor_b32_e32 v21, v19, v28 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v62, v20, v5, v59 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v52, v21, v0, v62 + v_xor_b32_e32 v21, v19, v30 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v54, v20, v27, v52 + v_xor_b32_e32 v8, v8, v29 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v46, v20, v13, v54 + v_xor_b32_e32 v19, v19, v31 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v47, v8, v22, v46 + v_add_u32_e32 v7, 0xc0, v7 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v8, v7, v4 + v_sub_u32_e32 v19, v8, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v92, v19, v18, v47 + v_add_u32_e32 v19, 16, v7 + v_xor_b32_e32 v20, v19, v4 + v_sub_u32_e32 v8, v20, v8 + v_lshl_add_u32 v93, v8, 2, v92 + v_xor_b32_e32 v8, v7, v26 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v64, v20, v25, v93 + v_xor_b32_e32 v20, v19, v28 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v66, v8, v5, v64 + v_xor_b32_e32 v8, v7, v10 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v57, v20, v0, v66 + v_xor_b32_e32 v20, v19, v30 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v60, v8, v27, v57 + v_xor_b32_e32 v7, v7, v29 + v_sub_u32_e32 v8, v7, v20 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v51, v8, v13, v60 + v_xor_b32_e32 v8, v19, v31 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v50, v7, v22, v51 + v_xor_b32_e32 v7, v17, v4 + v_sub_u32_e32 v3, v7, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v94, v56, v2, v3 + v_xor_b32_e32 v2, v6, v26 + v_sub_u32_e32 v3, v2, v7 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v73, v3, v25, v94 + v_xor_b32_e32 v3, v17, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v74, v2, v5, v73 + v_xor_b32_e32 v2, v6, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v67, v3, v0, v74 + v_xor_b32_e32 v3, v17, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v68, v2, v27, v67 + v_xor_b32_e32 v2, v6, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v58, v3, v13, v68 + v_xor_b32_e32 v3, v17, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v61, v2, v22, v58 + v_xor_b32_e32 v2, v16, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v95, v3, v18, v61 + v_xor_b32_e32 v3, v15, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v96, v2, 2, v95 + v_xor_b32_e32 v2, v16, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v80, v3, v25, v96 + v_xor_b32_e32 v3, v15, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v81, v2, v5, v80 + v_xor_b32_e32 v2, v16, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v71, v3, v0, v81 + v_xor_b32_e32 v3, v15, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v72, v2, v27, v71 + v_xor_b32_e32 v2, v16, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v63, v3, v13, v72 + v_xor_b32_e32 v3, v15, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v65, v2, v22, v63 + v_xor_b32_e32 v2, v14, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v98, v3, v18, v65 + v_xor_b32_e32 v3, v12, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v99, v2, 2, v98 + v_xor_b32_e32 v2, v14, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v84, v3, v25, v99 + v_xor_b32_e32 v3, v12, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v85, v2, v5, v84 + v_xor_b32_e32 v2, v14, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v77, v3, v0, v85 + v_xor_b32_e32 v3, v12, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v79, v2, v27, v77 + v_xor_b32_e32 v2, v14, v29 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v69, v3, v13, v79 + v_xor_b32_e32 v3, v12, v31 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v70, v2, v22, v69 + v_xor_b32_e32 v2, v11, v4 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v100, v3, v18, v70 + v_xor_b32_e32 v3, v9, v4 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v101, v2, 2, v100 + v_xor_b32_e32 v2, v11, v26 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v86, v3, v25, v101 + v_xor_b32_e32 v3, v9, v28 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v87, v2, v5, v86 + v_xor_b32_e32 v2, v11, v10 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v82, v3, v0, v87 + v_xor_b32_e32 v0, v9, v30 + v_sub_u32_e32 v2, v0, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v83, v2, v27, v82 + v_xor_b32_e32 v2, v11, v29 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v75, v0, v13, v83 + v_xor_b32_e32 v0, v9, v31 + v_sub_u32_e32 v0, v0, v2 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v76, v0, v22, v75 + s_add_i32 s18, s18, 1 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_mov_b32 s19, 0x3020504 + s_mov_b32 s23, 0x5010400 + s_mov_b32 s24, 0x5040100 + s_mov_b32 s25, 0x7060302 + s_mov_b32 s26, 0x7030602 +.LBB27_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2753.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v35, s2, v35 + v_add_u32_e32 v34, s3, v34 + buffer_load_dwordx4 v[26:29], v34, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v34 + buffer_load_dwordx4 v[18:21], v35, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v35 + v_add_u32_e32 v3, s7, v0 + buffer_load_dwordx4 v[22:25], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[30:33], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v3, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v3 + buffer_load_dwordx4 v[10:13], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[6:9], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v2, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v120, v88 + ds_read_b32 v122, v97 + ds_read_b32 v123, v78 + ds_read_b32 v110, v44 + ds_read_b32 v111, v45 + ds_read_b32 v106, v40 + ds_read_b32 v107, v41 + ds_read_b32 v104, v38 + ds_read_b32 v116, v56 offset:16384 + ds_read_b32 v118, v95 offset:16384 + ds_read_b32 v119, v96 offset:16384 + ds_read_b32 v112, v80 offset:16384 + ds_read_b32 v117, v94 offset:16384 + ds_read_b32 v114, v73 offset:16384 + ds_read_b32 v115, v74 offset:16384 + ds_read_b32 v108, v67 offset:16384 + ds_read_b32 v109, v68 offset:16384 + ds_read_b32 v102, v58 offset:16384 + ds_read_b32 v103, v61 offset:16384 + ds_read_b32 v125, v50 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[122:123], v[116:117], a[64:79] + ds_read_b32 v113, v81 offset:16384 + ds_read_b32 v126, v71 offset:16384 + ds_read_b32 v127, v72 offset:16384 + ds_read_b32 v128, v63 offset:16384 + ds_read_b32 v129, v65 offset:16384 + ds_read_b32 v130, v98 offset:16384 + ds_read_b32 v131, v99 offset:16384 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[122:123], v[118:119], a[80:95] + ds_read_b32 v132, v84 offset:16384 + ds_read_b32 v133, v85 offset:16384 + ds_read_b32 v134, v77 offset:16384 + ds_read_b32 v135, v79 offset:16384 + ds_read_b32 v136, v69 offset:16384 + ds_read_b32 v137, v70 offset:16384 + ds_read_b32 v138, v100 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[122:123], v[130:131], a[96:111] + ds_read_b32 v139, v101 offset:16384 + ds_read_b32 v140, v86 offset:16384 + ds_read_b32 v141, v87 offset:16384 + ds_read_b32 v142, v82 offset:16384 + ds_read_b32 v143, v83 offset:16384 + ds_read_b32 v144, v75 offset:16384 + ds_read_b32 v145, v76 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[122:123], v[138:139], a[112:127] + ds_read_b32 v121, v89 + ds_read_b32 v122, v53 + ds_read_b32 v123, v55 + ds_read_b32 v146, v48 + ds_read_b32 v147, v49 + ds_read_b32 v148, v42 + ds_read_b32 v105, v39 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[120:121], v[116:117], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[120:121], v[118:119], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[120:121], v[130:131], a[160:175] + ds_read_b32 v150, v90 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[120:121], v[138:139], a[176:191] + ds_read_b32 v151, v91 + ds_read_b32 v120, v59 + ds_read_b32 v121, v62 + ds_read_b32 v152, v52 + ds_read_b32 v153, v54 + ds_read_b32 v154, v46 + ds_read_b32 v149, v43 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[150:151], v[116:117], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[150:151], v[118:119], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[150:151], v[130:131], a[224:239] + ds_read_b32 v156, v92 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[150:151], v[138:139], a[240:255] + ds_read_b32 v157, v93 + ds_read_b32 v150, v64 + ds_read_b32 v151, v66 + ds_read_b32 v158, v57 + ds_read_b32 v159, v60 + ds_read_b32 v124, v51 + ds_read_b32 v155, v47 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[156:157], v[116:117], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[156:157], v[118:119], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[156:157], v[130:131], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[156:157], v[138:139], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[110:111], v[114:115], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[110:111], v[112:113], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[110:111], v[132:133], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[110:111], v[140:141], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[122:123], v[114:115], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[122:123], v[112:113], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[122:123], v[132:133], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[122:123], v[140:141], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[120:121], v[114:115], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[120:121], v[112:113], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[120:121], v[132:133], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[120:121], v[140:141], a[240:255] + s_waitcnt lgkmcnt(4) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[150:151], v[114:115], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[150:151], v[112:113], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[150:151], v[132:133], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[150:151], v[140:141], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[106:107], v[108:109], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[106:107], v[126:127], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[106:107], v[134:135], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[106:107], v[142:143], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[146:147], v[108:109], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[146:147], v[126:127], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[146:147], v[134:135], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[146:147], v[142:143], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[152:153], v[108:109], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[152:153], v[126:127], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[152:153], v[134:135], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[152:153], v[142:143], a[240:255] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[158:159], v[108:109], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[158:159], v[126:127], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[158:159], v[134:135], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[158:159], v[142:143], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[104:105], v[102:103], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[104:105], v[128:129], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[104:105], v[136:137], a[96:111] + v_readfirstlane_b32 s27, v227 + s_add_i32 s18, s18, -1 + s_lshr_b32 s27, s27, 2 + s_and_b32 s27, s27, 0x3ffffff0 + v_add_u32_e32 v0, s27, v1 + s_cmp_gt_u32 s18, 2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[104:105], v[144:145], a[112:127] + s_barrier + v_lshrrev_b32_e32 v36, 1, v0 + v_lshlrev_b32_e32 v104, 9, v0 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v36, 16, v36 + v_and_b32_e32 v104, 0x3000, v104 + v_and_b32_e32 v0, 0xfffff800, v0 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[148:149], v[102:103], a[128:143] + v_xor_b32_e32 v105, v36, v37 + v_add_u32_e32 v0, v104, v0 + v_or_b32_e32 v104, 1, v36 + v_or_b32_e32 v106, 2, v36 + v_or_b32_e32 v107, 3, v36 + v_or_b32_e32 v108, 4, v36 + v_or_b32_e32 v109, 5, v36 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[148:149], v[128:129], a[144:159] + v_or_b32_e32 v110, 6, v36 + v_or_b32_e32 v111, 7, v36 + v_or_b32_e32 v112, 8, v36 + v_or_b32_e32 v113, 9, v36 + v_or_b32_e32 v114, 10, v36 + v_or_b32_e32 v115, 11, v36 + v_or_b32_e32 v116, 12, v36 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[148:149], v[136:137], a[160:175] + v_or_b32_e32 v117, 13, v36 + v_or_b32_e32 v118, 14, v36 + v_or_b32_e32 v36, 15, v36 + v_lshl_or_b32 v0, v105, 2, v0 + v_xor_b32_e32 v104, v104, v37 + v_xor_b32_e32 v106, v106, v37 + v_xor_b32_e32 v107, v107, v37 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[148:149], v[144:145], a[176:191] + v_xor_b32_e32 v108, v108, v37 + v_xor_b32_e32 v109, v109, v37 + v_xor_b32_e32 v110, v110, v37 + v_xor_b32_e32 v111, v111, v37 + v_xor_b32_e32 v112, v112, v37 + v_xor_b32_e32 v113, v113, v37 + v_xor_b32_e32 v114, v114, v37 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[154:155], v[102:103], a[192:207] + v_xor_b32_e32 v115, v115, v37 + v_xor_b32_e32 v116, v116, v37 + v_xor_b32_e32 v117, v117, v37 + v_xor_b32_e32 v118, v118, v37 + v_xor_b32_e32 v36, v36, v37 + v_sub_u32_e32 v105, v104, v105 + v_sub_u32_e32 v104, v106, v104 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[154:155], v[128:129], a[208:223] + v_sub_u32_e32 v106, v107, v106 + v_sub_u32_e32 v107, v108, v107 + v_sub_u32_e32 v108, v109, v108 + v_sub_u32_e32 v109, v110, v109 + v_sub_u32_e32 v110, v111, v110 + v_sub_u32_e32 v111, v112, v111 + v_sub_u32_e32 v112, v113, v112 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[154:155], v[136:137], a[224:239] + v_sub_u32_e32 v113, v114, v113 + v_sub_u32_e32 v114, v115, v114 + v_sub_u32_e32 v115, v116, v115 + v_sub_u32_e32 v116, v117, v116 + v_sub_u32_e32 v117, v118, v117 + v_sub_u32_e32 v36, v36, v118 + v_lshl_add_u32 v105, v105, 2, v0 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[154:155], v[144:145], a[240:255] + v_lshlrev_b32_e32 v104, 2, v104 + v_lshlrev_b32_e32 v106, 2, v106 + v_lshlrev_b32_e32 v107, 2, v107 + v_lshlrev_b32_e32 v108, 2, v108 + v_lshlrev_b32_e32 v109, 2, v109 + v_lshlrev_b32_e32 v110, 2, v110 + v_lshlrev_b32_e32 v111, 2, v111 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[124:125], v[102:103], a[32:47] + v_lshlrev_b32_e32 v102, 2, v112 + v_lshlrev_b32_e32 v103, 2, v113 + v_lshlrev_b32_e32 v112, 2, v114 + v_lshlrev_b32_e32 v113, 2, v115 + v_lshlrev_b32_e32 v114, 2, v116 + v_lshlrev_b32_e32 v115, 2, v117 + v_lshlrev_b32_e32 v36, 2, v36 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[124:125], v[128:129], a[48:63] + v_add3_u32 v104, v105, s6, v104 + v_add3_u32 v106, v104, s6, v106 + v_add3_u32 v107, v106, s6, v107 + v_add3_u32 v108, v107, s6, v108 + v_add3_u32 v109, v108, s6, v109 + v_add3_u32 v110, v109, s6, v110 + v_add3_u32 v111, v110, s6, v111 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[124:125], v[136:137], a[0:15] + v_add3_u32 v102, v111, s6, v102 + v_add3_u32 v103, v102, s6, v103 + v_add3_u32 v112, v103, s6, v112 + v_add3_u32 v113, v112, s6, v113 + v_add3_u32 v114, v113, s6, v114 + v_add3_u32 v115, v114, s6, v115 + v_add3_u32 v36, v115, s6, v36 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[124:125], v[144:145], a[16:31] + s_waitcnt vmcnt(7) + v_perm_b32 v26, v26, v26, s19 + v_perm_b32 v27, v27, v27, s19 + v_perm_b32 v28, v28, v28, s19 + v_perm_b32 v29, v29, v29, s19 + s_waitcnt vmcnt(6) + v_perm_b32 v18, v18, v18, s19 + v_perm_b32 v19, v19, v19, s19 + v_perm_b32 v20, v20, v20, s19 + v_perm_b32 v21, v21, v21, s19 + s_waitcnt vmcnt(4) + v_perm_b32 v30, v30, v30, s19 + v_perm_b32 v31, v31, v31, s19 + v_perm_b32 v32, v32, v32, s19 + v_perm_b32 v33, v33, v33, s19 + v_perm_b32 v22, v22, v22, s19 + v_perm_b32 v23, v23, v23, s19 + v_perm_b32 v24, v24, v24, s19 + v_perm_b32 v25, v25, v25, s19 + s_waitcnt vmcnt(3) + v_perm_b32 v14, v14, v14, s19 + v_perm_b32 v15, v15, v15, s19 + v_perm_b32 v16, v16, v16, s19 + v_perm_b32 v17, v17, v17, s19 + v_perm_b32 v116, v30, v26, s23 + v_perm_b32 v26, v30, v26, s26 + v_perm_b32 v30, v31, v27, s23 + v_perm_b32 v27, v31, v27, s26 + v_perm_b32 v31, v32, v28, s23 + v_perm_b32 v28, v32, v28, s26 + v_perm_b32 v32, v33, v29, s23 + v_perm_b32 v29, v33, v29, s26 + s_waitcnt vmcnt(2) + v_perm_b32 v10, v10, v10, s19 + v_perm_b32 v11, v11, v11, s19 + v_perm_b32 v12, v12, v12, s19 + v_perm_b32 v13, v13, v13, s19 + v_perm_b32 v33, v22, v18, s23 + v_perm_b32 v18, v22, v18, s26 + v_perm_b32 v22, v23, v19, s23 + v_perm_b32 v19, v23, v19, s26 + v_perm_b32 v23, v24, v20, s23 + v_perm_b32 v20, v24, v20, s26 + v_perm_b32 v24, v25, v21, s23 + v_perm_b32 v21, v25, v21, s26 + s_waitcnt vmcnt(1) + v_perm_b32 v6, v6, v6, s19 + v_perm_b32 v7, v7, v7, s19 + v_perm_b32 v8, v8, v8, s19 + v_perm_b32 v9, v9, v9, s19 + s_waitcnt vmcnt(0) + v_perm_b32 v2, v2, v2, s19 + v_perm_b32 v3, v3, v3, s19 + v_perm_b32 v4, v4, v4, s19 + v_perm_b32 v5, v5, v5, s19 + v_perm_b32 v25, v6, v14, s23 + v_perm_b32 v6, v6, v14, s26 + v_perm_b32 v14, v7, v15, s23 + v_perm_b32 v7, v7, v15, s26 + v_perm_b32 v15, v8, v16, s23 + v_perm_b32 v8, v8, v16, s26 + v_perm_b32 v16, v9, v17, s23 + v_perm_b32 v9, v9, v17, s26 + v_perm_b32 v17, v2, v10, s23 + v_perm_b32 v2, v2, v10, s26 + v_perm_b32 v10, v3, v11, s23 + v_perm_b32 v3, v3, v11, s26 + v_perm_b32 v11, v4, v12, s23 + v_perm_b32 v4, v4, v12, s26 + v_perm_b32 v12, v5, v13, s23 + v_perm_b32 v5, v5, v13, s26 + v_perm_b32 v13, v25, v116, s24 + v_perm_b32 v25, v25, v116, s25 + v_perm_b32 v116, v6, v26, s24 + v_perm_b32 v6, v6, v26, s25 + v_perm_b32 v26, v14, v30, s24 + v_perm_b32 v14, v14, v30, s25 + v_perm_b32 v30, v7, v27, s24 + v_perm_b32 v7, v7, v27, s25 + v_perm_b32 v27, v15, v31, s24 + v_perm_b32 v15, v15, v31, s25 + v_perm_b32 v31, v8, v28, s24 + v_perm_b32 v8, v8, v28, s25 + v_perm_b32 v28, v16, v32, s24 + v_perm_b32 v16, v16, v32, s25 + v_perm_b32 v32, v9, v29, s24 + v_perm_b32 v9, v9, v29, s25 + v_perm_b32 v29, v17, v33, s24 + v_perm_b32 v17, v17, v33, s25 + v_perm_b32 v33, v2, v18, s24 + v_perm_b32 v2, v2, v18, s25 + v_perm_b32 v18, v10, v22, s24 + v_perm_b32 v10, v10, v22, s25 + v_perm_b32 v22, v3, v19, s24 + v_perm_b32 v3, v3, v19, s25 + v_perm_b32 v19, v11, v23, s24 + v_perm_b32 v11, v11, v23, s25 + v_perm_b32 v23, v4, v20, s24 + v_perm_b32 v4, v4, v20, s25 + v_perm_b32 v20, v12, v24, s24 + v_perm_b32 v12, v12, v24, s25 + v_perm_b32 v24, v5, v21, s24 + v_perm_b32 v5, v5, v21, s25 + ds_write_b32 v0, v13 + ds_write_b32 v105, v25 offset:128 + ds_write_b32 v104, v116 offset:128 + ds_write_b32 v106, v6 offset:128 + ds_write_b32 v107, v26 offset:128 + ds_write_b32 v108, v14 offset:128 + ds_write_b32 v109, v30 offset:128 + ds_write_b32 v110, v7 offset:128 + ds_write_b32 v111, v27 offset:128 + ds_write_b32 v102, v15 offset:128 + ds_write_b32 v103, v31 offset:128 + ds_write_b32 v112, v8 offset:128 + ds_write_b32 v113, v28 offset:128 + ds_write_b32 v114, v16 offset:128 + ds_write_b32 v115, v32 offset:128 + ds_write_b32 v36, v9 offset:128 + ds_write_b32 v0, v29 offset:16384 + ds_write_b32 v105, v17 offset:16512 + ds_write_b32 v104, v33 offset:16512 + ds_write_b32 v106, v2 offset:16512 + ds_write_b32 v107, v18 offset:16512 + ds_write_b32 v108, v10 offset:16512 + ds_write_b32 v109, v22 offset:16512 + ds_write_b32 v110, v3 offset:16512 + ds_write_b32 v111, v19 offset:16512 + ds_write_b32 v102, v11 offset:16512 + ds_write_b32 v103, v23 offset:16512 + ds_write_b32 v112, v4 offset:16512 + ds_write_b32 v113, v20 offset:16512 + ds_write_b32 v114, v12 offset:16512 + ds_write_b32 v115, v24 offset:16512 + ds_write_b32 v36, v5 offset:16512 + s_cbranch_scc1 .LBB27_8 +.LBB27_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSB_8RowMajorESD_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iP + v_accvgpr_read_b32 v0, a160 + v_accvgpr_read_b32 v1, a161 + v_accvgpr_read_b32 v2, a162 + v_accvgpr_read_b32 v3, a163 + v_accvgpr_read_b32 v4, a164 + v_accvgpr_read_b32 v5, a165 + v_accvgpr_read_b32 v6, a166 + v_accvgpr_read_b32 v7, a167 + v_accvgpr_read_b32 v8, a168 + v_accvgpr_read_b32 v9, a169 + v_accvgpr_read_b32 v10, a170 + v_accvgpr_read_b32 v11, a171 + v_accvgpr_read_b32 v12, a172 + v_accvgpr_read_b32 v13, a173 + v_accvgpr_read_b32 v14, a174 + v_accvgpr_read_b32 v15, a175 + v_accvgpr_read_b32 v16, a176 + v_accvgpr_read_b32 v17, a177 + v_accvgpr_read_b32 v18, a178 + v_accvgpr_read_b32 v19, a179 + v_accvgpr_read_b32 v20, a180 + v_accvgpr_read_b32 v21, a181 + v_accvgpr_read_b32 v22, a182 + v_accvgpr_read_b32 v23, a183 + v_accvgpr_read_b32 v24, a184 + v_accvgpr_read_b32 v25, a185 + v_accvgpr_read_b32 v26, a186 + v_accvgpr_read_b32 v27, a187 + v_accvgpr_read_b32 v28, a188 + v_accvgpr_read_b32 v29, a189 + v_accvgpr_read_b32 v30, a190 + v_accvgpr_read_b32 v31, a191 + v_accvgpr_read_b32 v102, a192 + v_accvgpr_read_b32 v103, a193 + v_accvgpr_read_b32 v104, a194 + v_accvgpr_read_b32 v105, a195 + v_accvgpr_read_b32 v106, a196 + v_accvgpr_read_b32 v107, a197 + v_accvgpr_read_b32 v108, a198 + v_accvgpr_read_b32 v109, a199 + v_accvgpr_read_b32 v110, a200 + v_accvgpr_read_b32 v111, a201 + v_accvgpr_read_b32 v112, a202 + v_accvgpr_read_b32 v113, a203 + v_accvgpr_read_b32 v114, a204 + v_accvgpr_read_b32 v115, a205 + v_accvgpr_read_b32 v116, a206 + v_accvgpr_read_b32 v117, a207 + v_accvgpr_read_b32 v118, a208 + v_accvgpr_read_b32 v119, a209 + v_accvgpr_read_b32 v120, a210 + v_accvgpr_read_b32 v121, a211 + v_accvgpr_read_b32 v122, a212 + v_accvgpr_read_b32 v123, a213 + v_accvgpr_read_b32 v124, a214 + v_accvgpr_read_b32 v125, a215 + v_accvgpr_read_b32 v126, a216 + v_accvgpr_read_b32 v127, a217 + v_accvgpr_read_b32 v128, a218 + v_accvgpr_read_b32 v129, a219 + v_accvgpr_read_b32 v130, a220 + v_accvgpr_read_b32 v131, a221 + v_accvgpr_read_b32 v132, a222 + v_accvgpr_read_b32 v133, a223 + v_accvgpr_read_b32 v134, a224 + v_accvgpr_read_b32 v135, a225 + v_accvgpr_read_b32 v136, a226 + v_accvgpr_read_b32 v137, a227 + v_accvgpr_read_b32 v138, a228 + v_accvgpr_read_b32 v139, a229 + v_accvgpr_read_b32 v140, a230 + v_accvgpr_read_b32 v141, a231 + v_accvgpr_read_b32 v142, a232 + v_accvgpr_read_b32 v143, a233 + v_accvgpr_read_b32 v144, a234 + v_accvgpr_read_b32 v145, a235 + v_accvgpr_read_b32 v146, a236 + v_accvgpr_read_b32 v147, a237 + v_accvgpr_read_b32 v148, a238 + v_accvgpr_read_b32 v149, a239 + v_accvgpr_read_b32 v150, a240 + v_accvgpr_read_b32 v151, a241 + v_accvgpr_read_b32 v152, a242 + v_accvgpr_read_b32 v153, a243 + v_accvgpr_read_b32 v154, a244 + v_accvgpr_read_b32 v155, a245 + v_accvgpr_read_b32 v156, a246 + v_accvgpr_read_b32 v157, a247 + v_accvgpr_read_b32 v158, a248 + v_accvgpr_read_b32 v159, a249 + v_accvgpr_read_b32 v160, a250 + v_accvgpr_read_b32 v161, a251 + v_accvgpr_read_b32 v162, a252 + v_accvgpr_read_b32 v163, a253 + v_accvgpr_read_b32 v164, a254 + v_accvgpr_read_b32 v165, a255 + v_accvgpr_read_b32 v166, a48 + v_accvgpr_read_b32 v167, a49 + v_accvgpr_read_b32 v168, a50 + v_accvgpr_read_b32 v169, a51 + v_accvgpr_read_b32 v170, a52 + v_accvgpr_read_b32 v171, a53 + v_accvgpr_read_b32 v172, a54 + v_accvgpr_read_b32 v173, a55 + v_accvgpr_read_b32 v174, a56 + v_accvgpr_read_b32 v175, a57 + v_accvgpr_read_b32 v176, a58 + v_accvgpr_read_b32 v177, a59 + v_accvgpr_read_b32 v178, a60 + v_accvgpr_read_b32 v179, a61 + v_accvgpr_read_b32 v180, a62 + v_accvgpr_read_b32 v181, a63 + v_accvgpr_mov_b32 a240, a16 + v_accvgpr_mov_b32 a241, a17 + v_accvgpr_mov_b32 a242, a18 + v_accvgpr_mov_b32 a243, a19 + v_accvgpr_mov_b32 a244, a20 + v_accvgpr_mov_b32 a245, a21 + v_accvgpr_mov_b32 a246, a22 + v_accvgpr_mov_b32 a247, a23 + v_accvgpr_mov_b32 a248, a24 + v_accvgpr_mov_b32 a249, a25 + v_accvgpr_mov_b32 a250, a26 + v_accvgpr_mov_b32 a251, a27 + v_accvgpr_mov_b32 a252, a28 + v_accvgpr_mov_b32 a253, a29 + v_accvgpr_mov_b32 a254, a30 + v_accvgpr_mov_b32 a255, a31 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v32, v97 + ds_read_b32 v33, v78 + ds_read_b32 v34, v56 offset:16384 + ds_read_b32 v35, v94 offset:16384 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a224, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[32:33], v[34:35], a[224:239] + ds_read_b32 v36, v95 offset:16384 + ds_read_b32 v37, v96 offset:16384 + v_accvgpr_mov_b32 a223, a95 + v_accvgpr_mov_b32 a222, a94 + v_accvgpr_mov_b32 a221, a93 + v_accvgpr_mov_b32 a220, a92 + v_accvgpr_mov_b32 a219, a91 + v_accvgpr_mov_b32 a218, a90 + v_accvgpr_mov_b32 a217, a89 + v_accvgpr_mov_b32 a216, a88 + v_accvgpr_mov_b32 a215, a87 + v_accvgpr_mov_b32 a214, a86 + v_accvgpr_mov_b32 a213, a85 + v_accvgpr_mov_b32 a212, a84 + v_accvgpr_mov_b32 a211, a83 + v_accvgpr_mov_b32 a210, a82 + v_accvgpr_mov_b32 a209, a81 + v_accvgpr_mov_b32 a208, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[32:33], v[36:37], a[208:223] + ds_read_b32 v94, v98 offset:16384 + ds_read_b32 v95, v99 offset:16384 + v_accvgpr_mov_b32 a207, a111 + v_accvgpr_mov_b32 a206, a110 + v_accvgpr_mov_b32 a205, a109 + v_accvgpr_mov_b32 a204, a108 + v_accvgpr_mov_b32 a203, a107 + v_accvgpr_mov_b32 a202, a106 + v_accvgpr_mov_b32 a201, a105 + v_accvgpr_mov_b32 a200, a104 + v_accvgpr_mov_b32 a199, a103 + v_accvgpr_mov_b32 a198, a102 + v_accvgpr_mov_b32 a197, a101 + v_accvgpr_mov_b32 a196, a100 + v_accvgpr_mov_b32 a195, a99 + v_accvgpr_mov_b32 a194, a98 + v_accvgpr_mov_b32 a193, a97 + v_accvgpr_mov_b32 a192, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[32:33], v[94:95], a[192:207] + ds_read_b32 v96, v100 offset:16384 + ds_read_b32 v97, v101 offset:16384 + v_accvgpr_mov_b32 a191, a127 + v_accvgpr_mov_b32 a190, a126 + v_accvgpr_mov_b32 a189, a125 + v_accvgpr_mov_b32 a188, a124 + v_accvgpr_mov_b32 a187, a123 + v_accvgpr_mov_b32 a186, a122 + v_accvgpr_mov_b32 a185, a121 + v_accvgpr_mov_b32 a184, a120 + v_accvgpr_mov_b32 a183, a119 + v_accvgpr_mov_b32 a182, a118 + v_accvgpr_mov_b32 a181, a117 + v_accvgpr_mov_b32 a180, a116 + v_accvgpr_mov_b32 a179, a115 + v_accvgpr_mov_b32 a178, a114 + v_accvgpr_mov_b32 a177, a113 + v_accvgpr_mov_b32 a176, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[32:33], v[96:97], a[176:191] + ds_read_b32 v32, v88 + ds_read_b32 v33, v89 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[32:33], v[34:35], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[32:33], v[36:37], a[144:159] + v_accvgpr_write_b32 a143, v15 + v_accvgpr_write_b32 a142, v14 + v_accvgpr_write_b32 a141, v13 + v_accvgpr_write_b32 a140, v12 + v_accvgpr_write_b32 a139, v11 + v_accvgpr_write_b32 a138, v10 + v_accvgpr_write_b32 a137, v9 + v_accvgpr_write_b32 a136, v8 + v_accvgpr_write_b32 a135, v7 + v_accvgpr_write_b32 a134, v6 + v_accvgpr_write_b32 a133, v5 + v_accvgpr_write_b32 a132, v4 + v_accvgpr_write_b32 a131, v3 + v_accvgpr_write_b32 a130, v2 + v_accvgpr_write_b32 a129, v1 + v_accvgpr_write_b32 a128, v0 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[32:33], v[94:95], a[128:143] + v_accvgpr_write_b32 a127, v31 + v_accvgpr_write_b32 a126, v30 + v_accvgpr_write_b32 a125, v29 + v_accvgpr_write_b32 a124, v28 + v_accvgpr_write_b32 a123, v27 + v_accvgpr_write_b32 a122, v26 + v_accvgpr_write_b32 a121, v25 + v_accvgpr_write_b32 a120, v24 + v_accvgpr_write_b32 a119, v23 + v_accvgpr_write_b32 a118, v22 + v_accvgpr_write_b32 a117, v21 + v_accvgpr_write_b32 a116, v20 + v_accvgpr_write_b32 a115, v19 + v_accvgpr_write_b32 a114, v18 + v_accvgpr_write_b32 a113, v17 + v_accvgpr_write_b32 a112, v16 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[32:33], v[96:97], a[112:127] + ds_read_b32 v0, v90 + ds_read_b32 v1, v91 + v_accvgpr_write_b32 a96, v102 + v_accvgpr_write_b32 a97, v103 + v_accvgpr_write_b32 a98, v104 + v_accvgpr_write_b32 a99, v105 + v_accvgpr_write_b32 a100, v106 + v_accvgpr_write_b32 a101, v107 + v_accvgpr_write_b32 a102, v108 + v_accvgpr_write_b32 a103, v109 + v_accvgpr_write_b32 a104, v110 + v_accvgpr_write_b32 a105, v111 + v_accvgpr_write_b32 a106, v112 + v_accvgpr_write_b32 a107, v113 + v_accvgpr_write_b32 a108, v114 + v_accvgpr_write_b32 a109, v115 + v_accvgpr_write_b32 a110, v116 + v_accvgpr_write_b32 a111, v117 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[34:35], a[96:111] + v_accvgpr_write_b32 a80, v118 + v_accvgpr_write_b32 a81, v119 + v_accvgpr_write_b32 a82, v120 + v_accvgpr_write_b32 a83, v121 + v_accvgpr_write_b32 a84, v122 + v_accvgpr_write_b32 a85, v123 + v_accvgpr_write_b32 a86, v124 + v_accvgpr_write_b32 a87, v125 + v_accvgpr_write_b32 a88, v126 + v_accvgpr_write_b32 a89, v127 + v_accvgpr_write_b32 a90, v128 + v_accvgpr_write_b32 a91, v129 + v_accvgpr_write_b32 a92, v130 + v_accvgpr_write_b32 a93, v131 + v_accvgpr_write_b32 a94, v132 + v_accvgpr_write_b32 a95, v133 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[36:37], a[80:95] + v_accvgpr_write_b32 a64, v134 + v_accvgpr_write_b32 a65, v135 + v_accvgpr_write_b32 a66, v136 + v_accvgpr_write_b32 a67, v137 + v_accvgpr_write_b32 a68, v138 + v_accvgpr_write_b32 a69, v139 + v_accvgpr_write_b32 a70, v140 + v_accvgpr_write_b32 a71, v141 + v_accvgpr_write_b32 a72, v142 + v_accvgpr_write_b32 a73, v143 + v_accvgpr_write_b32 a74, v144 + v_accvgpr_write_b32 a75, v145 + v_accvgpr_write_b32 a76, v146 + v_accvgpr_write_b32 a77, v147 + v_accvgpr_write_b32 a78, v148 + v_accvgpr_write_b32 a79, v149 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[94:95], a[64:79] + v_accvgpr_write_b32 a48, v150 + v_accvgpr_write_b32 a49, v151 + v_accvgpr_write_b32 a50, v152 + v_accvgpr_write_b32 a51, v153 + v_accvgpr_write_b32 a52, v154 + v_accvgpr_write_b32 a53, v155 + v_accvgpr_write_b32 a54, v156 + v_accvgpr_write_b32 a55, v157 + v_accvgpr_write_b32 a56, v158 + v_accvgpr_write_b32 a57, v159 + v_accvgpr_write_b32 a58, v160 + v_accvgpr_write_b32 a59, v161 + v_accvgpr_write_b32 a60, v162 + v_accvgpr_write_b32 a61, v163 + v_accvgpr_write_b32 a62, v164 + v_accvgpr_write_b32 a63, v165 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[96:97], a[48:63] + ds_read_b32 v0, v92 + ds_read_b32 v1, v93 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[34:35], a[32:47] + v_accvgpr_write_b32 a16, v166 + v_accvgpr_write_b32 a17, v167 + v_accvgpr_write_b32 a18, v168 + v_accvgpr_write_b32 a19, v169 + v_accvgpr_write_b32 a20, v170 + v_accvgpr_write_b32 a21, v171 + v_accvgpr_write_b32 a22, v172 + v_accvgpr_write_b32 a23, v173 + v_accvgpr_write_b32 a24, v174 + v_accvgpr_write_b32 a25, v175 + v_accvgpr_write_b32 a26, v176 + v_accvgpr_write_b32 a27, v177 + v_accvgpr_write_b32 a28, v178 + v_accvgpr_write_b32 a29, v179 + v_accvgpr_write_b32 a30, v180 + v_accvgpr_write_b32 a31, v181 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[36:37], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[94:95], a[0:15] + ds_read_b32 v2, v44 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[96:97], a[240:255] + ds_read_b32 v3, v45 + ds_read_b32 v0, v73 offset:16384 + ds_read_b32 v1, v74 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[2:3], v[0:1], a[224:239] + ds_read_b32 v4, v80 offset:16384 + ds_read_b32 v5, v81 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[2:3], v[4:5], a[208:223] + ds_read_b32 v6, v84 offset:16384 + ds_read_b32 v7, v85 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[2:3], v[6:7], a[192:207] + ds_read_b32 v8, v86 offset:16384 + ds_read_b32 v9, v87 offset:16384 + ds_read_b32 v10, v53 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[2:3], v[8:9], a[176:191] + ds_read_b32 v11, v55 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[10:11], v[0:1], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v2, v59 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v3, v62 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[2:3], v[0:1], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[2:3], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[2:3], v[6:7], a[64:79] + ds_read_b32 v10, v64 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v11, v66 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[10:11], v[0:1], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[10:11], v[6:7], a[0:15] + ds_read_b32 v0, v40 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v1, v41 + ds_read_b32 v2, v67 offset:16384 + ds_read_b32 v3, v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[2:3], a[224:239] + ds_read_b32 v4, v71 offset:16384 + ds_read_b32 v5, v72 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[4:5], a[208:223] + ds_read_b32 v6, v77 offset:16384 + ds_read_b32 v7, v79 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[6:7], a[192:207] + ds_read_b32 v8, v82 offset:16384 + ds_read_b32 v9, v83 offset:16384 + ds_read_b32 v10, v48 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b32 v11, v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v0, v52 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v1, v54 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b32 v10, v57 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b32 v11, v60 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[10:11], v[2:3], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[10:11], v[6:7], a[0:15] + ds_read_b32 v0, v38 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v1, v39 + ds_read_b32 v2, v58 offset:16384 + ds_read_b32 v3, v61 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[2:3], a[224:239] + ds_read_b32 v4, v63 offset:16384 + ds_read_b32 v5, v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[4:5], a[208:223] + ds_read_b32 v6, v69 offset:16384 + ds_read_b32 v7, v70 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[6:7], a[192:207] + ds_read_b32 v8, v75 offset:16384 + ds_read_b32 v9, v76 offset:16384 + ds_read_b32 v10, v42 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b32 v11, v43 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[10:11], v[2:3], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[10:11], v[6:7], a[128:143] + ds_read_b32 v0, v46 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[10:11], v[8:9], a[112:127] + ds_read_b32 v1, v47 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b32 v10, v51 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b32 v11, v50 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[10:11], v[2:3], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[10:11], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[10:11], v[6:7], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[10:11], v[8:9], a[240:255] +.LBB27_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSB_8RowMajorESD_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iPv + v_accvgpr_read_b32 v143, a224 + v_accvgpr_read_b32 v142, a225 + v_accvgpr_read_b32 v141, a226 + v_accvgpr_read_b32 v140, a227 + v_accvgpr_read_b32 v139, a228 + v_accvgpr_read_b32 v36, a229 + v_accvgpr_read_b32 v1, a230 + v_accvgpr_read_b32 v138, a231 + v_accvgpr_read_b32 v137, a232 + v_accvgpr_read_b32 v136, a233 + v_accvgpr_read_b32 v135, a234 + v_accvgpr_read_b32 v134, a235 + v_accvgpr_read_b32 v133, a236 + v_accvgpr_read_b32 v132, a237 + v_accvgpr_read_b32 v131, a238 + v_accvgpr_read_b32 v130, a239 + v_accvgpr_read_b32 v106, a208 + v_accvgpr_read_b32 v105, a209 + v_accvgpr_read_b32 v104, a210 + v_accvgpr_read_b32 v103, a211 + v_accvgpr_read_b32 v102, a212 + v_accvgpr_read_b32 v101, a213 + v_accvgpr_read_b32 v100, a214 + v_accvgpr_read_b32 v99, a215 + v_accvgpr_read_b32 v98, a216 + v_accvgpr_read_b32 v97, a217 + v_accvgpr_read_b32 v96, a218 + v_accvgpr_read_b32 v95, a219 + v_accvgpr_read_b32 v94, a220 + v_accvgpr_read_b32 v93, a221 + v_accvgpr_read_b32 v92, a222 + v_accvgpr_read_b32 v91, a223 + v_accvgpr_read_b32 v90, a192 + v_accvgpr_read_b32 v89, a193 + v_accvgpr_read_b32 v88, a194 + v_accvgpr_read_b32 v87, a195 + v_accvgpr_read_b32 v86, a196 + v_accvgpr_read_b32 v85, a197 + v_accvgpr_read_b32 v84, a198 + v_accvgpr_read_b32 v83, a199 + v_accvgpr_read_b32 v82, a200 + v_accvgpr_read_b32 v81, a201 + v_accvgpr_read_b32 v80, a202 + v_accvgpr_read_b32 v79, a203 + v_accvgpr_read_b32 v78, a204 + v_accvgpr_read_b32 v77, a205 + v_accvgpr_read_b32 v76, a206 + v_accvgpr_read_b32 v75, a207 + v_accvgpr_read_b32 v74, a176 + v_accvgpr_read_b32 v73, a177 + v_accvgpr_read_b32 v72, a178 + v_accvgpr_read_b32 v71, a179 + v_accvgpr_read_b32 v70, a180 + v_accvgpr_read_b32 v69, a181 + v_accvgpr_read_b32 v68, a182 + v_accvgpr_read_b32 v67, a183 + v_accvgpr_read_b32 v66, a184 + v_accvgpr_read_b32 v65, a185 + v_accvgpr_read_b32 v64, a186 + v_accvgpr_read_b32 v63, a187 + v_accvgpr_read_b32 v62, a188 + v_accvgpr_read_b32 v61, a189 + v_accvgpr_read_b32 v60, a190 + v_accvgpr_read_b32 v18, a191 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v59, a80 + v_accvgpr_read_b32 v58, a81 + v_accvgpr_read_b32 v57, a82 + v_accvgpr_read_b32 v56, a83 + v_accvgpr_read_b32 v55, a84 + v_accvgpr_read_b32 v54, a85 + v_accvgpr_read_b32 v53, a86 + v_accvgpr_read_b32 v52, a87 + v_accvgpr_read_b32 v51, a88 + v_accvgpr_read_b32 v50, a89 + v_accvgpr_read_b32 v24, a90 + v_accvgpr_read_b32 v23, a91 + v_accvgpr_read_b32 v22, a92 + v_accvgpr_read_b32 v21, a93 + v_accvgpr_read_b32 v20, a94 + v_accvgpr_read_b32 v19, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v107, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v35, a21 + v_accvgpr_read_b32 v34, a22 + v_accvgpr_read_b32 v33, a23 + v_accvgpr_read_b32 v32, a24 + v_accvgpr_read_b32 v31, a25 + v_accvgpr_read_b32 v30, a26 + v_accvgpr_read_b32 v29, a27 + v_accvgpr_read_b32 v28, a28 + v_accvgpr_read_b32 v27, a29 + v_accvgpr_read_b32 v26, a30 + v_accvgpr_read_b32 v25, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s3, s4, s16 + s_mul_hi_u32 s4, 0, s16 + s_add_i32 s4, s4, s3 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v0, 3, v225 + v_and_b32_e32 v0, 12, v0 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v36, v36 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v92, v92 + v_cvt_f16_f32_e32 v209, v91 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v90 + v_cvt_f16_f32_e32 v163, v89 + v_cvt_f16_f32_e32 v164, v88 + v_cvt_f16_f32_e32 v165, v87 + v_cvt_f16_f32_e32 v166, v86 + v_cvt_f16_f32_e32 v167, v85 + v_cvt_f16_f32_e32 v168, v84 + v_cvt_f16_f32_e32 v169, v83 + v_cvt_f16_f32_e32 v170, v82 + v_cvt_f16_f32_e32 v171, v81 + v_cvt_f16_f32_e32 v172, v80 + v_cvt_f16_f32_e32 v173, v79 + v_cvt_f16_f32_e32 v174, v78 + v_cvt_f16_f32_e32 v175, v77 + v_cvt_f16_f32_e32 v176, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v76, v160 + v_cvt_f16_f32_e32 v77, v159 + v_cvt_f16_f32_e32 v78, v158 + v_cvt_f16_f32_e32 v79, v157 + v_cvt_f16_f32_e32 v80, v156 + v_cvt_f16_f32_e32 v81, v155 + v_cvt_f16_f32_e32 v82, v154 + v_cvt_f16_f32_e32 v83, v153 + v_cvt_f16_f32_e32 v84, v152 + v_cvt_f16_f32_e32 v85, v151 + v_cvt_f16_f32_e32 v86, v150 + v_cvt_f16_f32_e32 v87, v149 + v_cvt_f16_f32_e32 v88, v148 + v_cvt_f16_f32_e32 v89, v147 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v71, v71 + v_cvt_f16_f32_e32 v134, v70 + v_cvt_f16_f32_e32 v135, v69 + v_cvt_f16_f32_e32 v136, v68 + v_cvt_f16_f32_e32 v137, v67 + v_cvt_f16_f32_e32 v138, v66 + v_cvt_f16_f32_e32 v139, v65 + v_cvt_f16_f32_e32 v140, v64 + v_cvt_f16_f32_e32 v141, v63 + v_cvt_f16_f32_e32 v142, v62 + v_cvt_f16_f32_e32 v143, v61 + v_cvt_f16_f32_e32 v144, v60 + v_cvt_f16_f32_e32 v145, v18 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v18, v205 + v_accvgpr_write_b32 a0, v18 + v_cvt_f16_f32_e32 v18, v204 + v_accvgpr_write_b32 a1, v18 + v_cvt_f16_f32_e32 v70, v203 + v_cvt_f16_f32_e32 v69, v202 + v_cvt_f16_f32_e32 v68, v201 + v_cvt_f16_f32_e32 v67, v200 + v_cvt_f16_f32_e32 v60, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v18, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v107 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v48, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v49, v42 + v_cvt_f16_f32_e32 v107, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v59 + v_cvt_f16_f32_e32 v3, v58 + v_cvt_f16_f32_e32 v4, v57 + v_cvt_f16_f32_e32 v5, v56 + v_cvt_f16_f32_e32 v6, v55 + v_cvt_f16_f32_e32 v7, v54 + v_cvt_f16_f32_e32 v8, v53 + v_cvt_f16_f32_e32 v9, v52 + v_cvt_f16_f32_e32 v10, v51 + v_cvt_f16_f32_e32 v11, v50 + v_cvt_f16_f32_e32 v12, v24 + v_cvt_f16_f32_e32 v13, v23 + v_cvt_f16_f32_e32 v14, v22 + v_cvt_f16_f32_e32 v15, v21 + v_cvt_f16_f32_e32 v16, v20 + v_cvt_f16_f32_e32 v17, v19 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v35 + v_cvt_f16_f32_e32 v56, v34 + v_cvt_f16_f32_e32 v57, v33 + v_cvt_f16_f32_e32 v58, v32 + v_cvt_f16_f32_e32 v59, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_cvt_f16_f32_e32 v25, v25 + v_lshlrev_b32_e32 v21, 1, v228 + v_lshlrev_b32_e32 v20, 3, v225 + v_lshrrev_b32_e32 v19, 1, v225 + s_cbranch_scc1 .LBB27_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB27_14 +.LBB27_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB27_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v22, s5, v0 + v_lshl_or_b32 v22, v22, 7, v18 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v22, v21, s2 + ds_write_b16 v22, v251 + ds_write_b16 v22, v252 offset:128 + ds_write_b16 v22, v253 offset:256 + ds_write_b16 v22, v254 offset:384 + ds_write_b16 v22, v255 offset:1024 + ds_write_b16 v22, v36 offset:1152 + ds_write_b16 v22, v1 offset:1280 + ds_write_b16 v22, v244 offset:1408 + ds_write_b16 v22, v245 offset:2048 + ds_write_b16 v22, v246 offset:2176 + ds_write_b16 v22, v247 offset:2304 + ds_write_b16 v22, v248 offset:2432 + ds_write_b16 v22, v249 offset:3072 + ds_write_b16 v22, v250 offset:3200 + ds_write_b16 v22, v131 offset:3328 + ds_write_b16 v22, v132 offset:3456 + ds_write_b16 v22, v133 offset:8192 + ds_write_b16 v22, v229 offset:8320 + ds_write_b16 v22, v230 offset:8448 + ds_write_b16 v22, v231 offset:8576 + ds_write_b16 v22, v232 offset:9216 + ds_write_b16 v22, v233 offset:9344 + ds_write_b16 v22, v234 offset:9472 + ds_write_b16 v22, v235 offset:9600 + ds_write_b16 v22, v236 offset:10240 + ds_write_b16 v22, v237 offset:10368 + ds_write_b16 v22, v238 offset:10496 + ds_write_b16 v22, v239 offset:10624 + ds_write_b16 v22, v240 offset:11264 + ds_write_b16 v22, v241 offset:11392 + ds_write_b16 v22, v242 offset:11520 + ds_write_b16 v22, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v23, 60, v19 + v_add_u32_e32 v24, s2, v23 + v_and_b32_e32 v31, 56, v20 + v_lshlrev_b32_e32 v23, 7, v24 + v_lshl_or_b32 v23, v31, 1, v23 + v_add_u32_e32 v37, s20, v24 + v_or_b32_e32 v24, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v37, s16 + v_add_u32_e32 v190, v31, v24 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v106 + ds_write_b16 v22, v105 offset:128 + ds_write_b16 v22, v104 offset:256 + ds_write_b16 v22, v103 offset:384 + ds_write_b16 v22, v102 offset:1024 + ds_write_b16 v22, v101 offset:1152 + ds_write_b16 v22, v100 offset:1280 + ds_write_b16 v22, v99 offset:1408 + ds_write_b16 v22, v98 offset:2048 + ds_write_b16 v22, v97 offset:2176 + ds_write_b16 v22, v96 offset:2304 + ds_write_b16 v22, v95 offset:2432 + ds_write_b16 v22, v94 offset:3072 + ds_write_b16 v22, v93 offset:3200 + ds_write_b16 v22, v92 offset:3328 + ds_write_b16 v22, v209 offset:3456 + ds_write_b16 v22, v210 offset:8192 + ds_write_b16 v22, v211 offset:8320 + ds_write_b16 v22, v212 offset:8448 + ds_write_b16 v22, v213 offset:8576 + ds_write_b16 v22, v214 offset:9216 + ds_write_b16 v22, v215 offset:9344 + ds_write_b16 v22, v216 offset:9472 + ds_write_b16 v22, v217 offset:9600 + ds_write_b16 v22, v218 offset:10240 + ds_write_b16 v22, v219 offset:10368 + ds_write_b16 v22, v220 offset:10496 + ds_write_b16 v22, v221 offset:10624 + ds_write_b16 v22, v222 offset:11264 + ds_write_b16 v22, v223 offset:11392 + ds_write_b16 v22, v224 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 64, v24 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v162 + ds_write_b16 v22, v163 offset:128 + ds_write_b16 v22, v164 offset:256 + ds_write_b16 v22, v165 offset:384 + ds_write_b16 v22, v166 offset:1024 + ds_write_b16 v22, v167 offset:1152 + ds_write_b16 v22, v168 offset:1280 + ds_write_b16 v22, v169 offset:1408 + ds_write_b16 v22, v170 offset:2048 + ds_write_b16 v22, v171 offset:2176 + ds_write_b16 v22, v172 offset:2304 + ds_write_b16 v22, v173 offset:2432 + ds_write_b16 v22, v174 offset:3072 + ds_write_b16 v22, v175 offset:3200 + ds_write_b16 v22, v176 offset:3328 + ds_write_b16 v22, v75 offset:3456 + ds_write_b16 v22, v76 offset:8192 + ds_write_b16 v22, v77 offset:8320 + ds_write_b16 v22, v78 offset:8448 + ds_write_b16 v22, v79 offset:8576 + ds_write_b16 v22, v80 offset:9216 + ds_write_b16 v22, v81 offset:9344 + ds_write_b16 v22, v82 offset:9472 + ds_write_b16 v22, v83 offset:9600 + ds_write_b16 v22, v84 offset:10240 + ds_write_b16 v22, v85 offset:10368 + ds_write_b16 v22, v86 offset:10496 + ds_write_b16 v22, v87 offset:10624 + ds_write_b16 v22, v88 offset:11264 + ds_write_b16 v22, v89 offset:11392 + ds_write_b16 v22, v90 offset:11520 + ds_write_b16 v22, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0x80, v24 + v_add_u32_e32 v192, v31, v191 + v_lshlrev_b32_e32 v201, 1, v192 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v201, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v201, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v201, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v201, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v192 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v74 + ds_write_b16 v22, v73 offset:128 + ds_write_b16 v22, v72 offset:256 + ds_write_b16 v22, v71 offset:384 + ds_write_b16 v22, v134 offset:1024 + ds_write_b16 v22, v135 offset:1152 + ds_write_b16 v22, v136 offset:1280 + ds_write_b16 v22, v137 offset:1408 + ds_write_b16 v22, v138 offset:2048 + ds_write_b16 v22, v139 offset:2176 + ds_write_b16 v22, v140 offset:2304 + ds_write_b16 v22, v141 offset:2432 + ds_write_b16 v22, v142 offset:3072 + ds_write_b16 v22, v143 offset:3200 + ds_write_b16 v22, v144 offset:3328 + ds_write_b16 v22, v145 offset:3456 + ds_write_b16 v22, v146 offset:8192 + ds_write_b16 v22, v147 offset:8320 + ds_write_b16 v22, v148 offset:8448 + ds_write_b16 v22, v149 offset:8576 + ds_write_b16 v22, v150 offset:9216 + ds_write_b16 v22, v151 offset:9344 + ds_write_b16 v22, v152 offset:9472 + ds_write_b16 v22, v153 offset:9600 + ds_write_b16 v22, v154 offset:10240 + ds_write_b16 v22, v155 offset:10368 + ds_write_b16 v22, v156 offset:10496 + ds_write_b16 v22, v157 offset:10624 + ds_write_b16 v22, v158 offset:11264 + ds_write_b16 v22, v159 offset:11392 + ds_write_b16 v22, v160 offset:11520 + ds_write_b16 v22, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v192, 0xc0, v24 + v_add_u32_e32 v31, v31, v192 + v_lshlrev_b32_e32 v201, 1, v31 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v201, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v201, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v201, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v201, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, v207 offset:128 + ds_write_b16 v22, v206 offset:256 + ds_write_b16 v22, a0 offset:384 + ds_write_b16 v22, a1 offset:1024 + ds_write_b16 v22, v70 offset:1152 + ds_write_b16 v22, v69 offset:1280 + ds_write_b16 v22, v68 offset:1408 + ds_write_b16 v22, v67 offset:2048 + ds_write_b16 v22, v60 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v115 offset:8320 + ds_write_b16 v22, v116 offset:8448 + ds_write_b16 v22, v117 offset:8576 + ds_write_b16 v22, v118 offset:9216 + ds_write_b16 v22, v119 offset:9344 + ds_write_b16 v22, v120 offset:9472 + ds_write_b16 v22, v121 offset:9600 + ds_write_b16 v22, v122 offset:10240 + ds_write_b16 v22, v123 offset:10368 + ds_write_b16 v22, v124 offset:10496 + ds_write_b16 v22, v125 offset:10624 + ds_write_b16 v22, v126 offset:11264 + ds_write_b16 v22, v127 offset:11392 + ds_write_b16 v22, v128 offset:11520 + ds_write_b16 v22, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v37 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v37, v31, v192 + v_lshlrev_b32_e32 v192, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v114 + ds_write_b16 v22, v193 offset:128 + ds_write_b16 v22, v194 offset:256 + ds_write_b16 v22, v195 offset:384 + ds_write_b16 v22, v196 offset:1024 + ds_write_b16 v22, v197 offset:1152 + ds_write_b16 v22, v198 offset:1280 + ds_write_b16 v22, v199 offset:1408 + ds_write_b16 v22, v200 offset:2048 + ds_write_b16 v22, v48 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v49 offset:3456 + ds_write_b16 v22, v107 offset:8192 + ds_write_b16 v22, v108 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v185 offset:9600 + ds_write_b16 v22, v184 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v37, v31, v191 + v_lshlrev_b32_e32 v191, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v50 offset:8192 + ds_write_b16 v22, v51 offset:8320 + ds_write_b16 v22, v52 offset:8448 + ds_write_b16 v22, v53 offset:8576 + ds_write_b16 v22, v54 offset:9216 + ds_write_b16 v22, v55 offset:9344 + ds_write_b16 v22, v56 offset:9472 + ds_write_b16 v22, v57 offset:9600 + ds_write_b16 v22, v58 offset:10240 + ds_write_b16 v22, v59 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v37, v31, v190 + v_lshlrev_b32_e32 v190, 1, v37 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v37 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11648 + v_add_u32_e32 v22, v31, v24 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v24, 1, v22 + ds_read_b128 v[32:35], v23 + ds_read_b128 v[38:41], v23 offset:128 + ds_read_b128 v[186:189], v23 offset:256 + ds_read_b128 v[202:205], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v24, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v38, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v39, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v40, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v41, v23, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v23, s[0:3], 12 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v22, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v22, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v22, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v22, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB27_12 +.LBB27_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v0, s5, v0 + s_barrier + v_lshl_or_b32 v0, v0, 7, v18 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v0, v21, s2 + ds_write_b16 v22, v251 + ds_write_b16 v22, v252 offset:128 + ds_write_b16 v22, v253 offset:256 + ds_write_b16 v22, v254 offset:384 + ds_write_b16 v22, v255 offset:1024 + ds_write_b16 v22, v36 offset:1152 + ds_write_b16 v22, v1 offset:1280 + ds_write_b16 v22, v244 offset:1408 + ds_write_b16 v22, v245 offset:2048 + ds_write_b16 v22, v246 offset:2176 + ds_write_b16 v22, v247 offset:2304 + ds_write_b16 v22, v248 offset:2432 + ds_write_b16 v22, v249 offset:3072 + ds_write_b16 v22, v250 offset:3200 + ds_write_b16 v22, v131 offset:3328 + ds_write_b16 v22, v132 offset:3456 + ds_write_b16 v22, v133 offset:8192 + ds_write_b16 v22, v229 offset:8320 + ds_write_b16 v22, v230 offset:8448 + ds_write_b16 v22, v231 offset:8576 + ds_write_b16 v22, v232 offset:9216 + ds_write_b16 v22, v233 offset:9344 + ds_write_b16 v22, v234 offset:9472 + ds_write_b16 v22, v235 offset:9600 + ds_write_b16 v22, v236 offset:10240 + ds_write_b16 v22, v237 offset:10368 + ds_write_b16 v22, v238 offset:10496 + ds_write_b16 v22, v239 offset:10624 + ds_write_b16 v22, v240 offset:11264 + ds_write_b16 v22, v241 offset:11392 + ds_write_b16 v22, v242 offset:11520 + ds_write_b16 v22, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v20 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v19 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v23, v0, 1, v18 + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[186:189], v23 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v24, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v31, v0, v24 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v40, 1, v31 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v40, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v31 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[186:189], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v106 + ds_write_b16 v22, v105 offset:128 + ds_write_b16 v22, v104 offset:256 + ds_write_b16 v22, v103 offset:384 + ds_write_b16 v22, v102 offset:1024 + ds_write_b16 v22, v101 offset:1152 + ds_write_b16 v22, v100 offset:1280 + ds_write_b16 v22, v99 offset:1408 + ds_write_b16 v22, v98 offset:2048 + ds_write_b16 v22, v97 offset:2176 + ds_write_b16 v22, v96 offset:2304 + ds_write_b16 v22, v95 offset:2432 + ds_write_b16 v22, v94 offset:3072 + ds_write_b16 v22, v93 offset:3200 + ds_write_b16 v22, v92 offset:3328 + ds_write_b16 v22, v209 offset:3456 + ds_write_b16 v22, v210 offset:8192 + ds_write_b16 v22, v211 offset:8320 + ds_write_b16 v22, v212 offset:8448 + ds_write_b16 v22, v213 offset:8576 + ds_write_b16 v22, v214 offset:9216 + ds_write_b16 v22, v215 offset:9344 + ds_write_b16 v22, v216 offset:9472 + ds_write_b16 v22, v217 offset:9600 + ds_write_b16 v22, v218 offset:10240 + ds_write_b16 v22, v219 offset:10368 + ds_write_b16 v22, v220 offset:10496 + ds_write_b16 v22, v221 offset:10624 + ds_write_b16 v22, v222 offset:11264 + ds_write_b16 v22, v223 offset:11392 + ds_write_b16 v22, v224 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[92:95], v23 offset:384 + v_or_b32_e32 v31, 64, v24 + v_add_u32_e32 v40, v0, v31 + v_lshlrev_b32_e32 v41, 1, v40 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v41, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v40 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[92:95], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v162 + ds_write_b16 v22, v163 offset:128 + ds_write_b16 v22, v164 offset:256 + ds_write_b16 v22, v165 offset:384 + ds_write_b16 v22, v166 offset:1024 + ds_write_b16 v22, v167 offset:1152 + ds_write_b16 v22, v168 offset:1280 + ds_write_b16 v22, v169 offset:1408 + ds_write_b16 v22, v170 offset:2048 + ds_write_b16 v22, v171 offset:2176 + ds_write_b16 v22, v172 offset:2304 + ds_write_b16 v22, v173 offset:2432 + ds_write_b16 v22, v174 offset:3072 + ds_write_b16 v22, v175 offset:3200 + ds_write_b16 v22, v176 offset:3328 + ds_write_b16 v22, v75 offset:3456 + ds_write_b16 v22, v76 offset:8192 + ds_write_b16 v22, v77 offset:8320 + ds_write_b16 v22, v78 offset:8448 + ds_write_b16 v22, v79 offset:8576 + ds_write_b16 v22, v80 offset:9216 + ds_write_b16 v22, v81 offset:9344 + ds_write_b16 v22, v82 offset:9472 + ds_write_b16 v22, v83 offset:9600 + ds_write_b16 v22, v84 offset:10240 + ds_write_b16 v22, v85 offset:10368 + ds_write_b16 v22, v86 offset:10496 + ds_write_b16 v22, v87 offset:10624 + ds_write_b16 v22, v88 offset:11264 + ds_write_b16 v22, v89 offset:11392 + ds_write_b16 v22, v90 offset:11520 + ds_write_b16 v22, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[76:79], v23 offset:384 + v_or_b32_e32 v40, 0x80, v24 + v_add_u32_e32 v41, v0, v40 + v_lshlrev_b32_e32 v75, 1, v41 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v41 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[76:79], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v74 + ds_write_b16 v22, v73 offset:128 + ds_write_b16 v22, v72 offset:256 + ds_write_b16 v22, v71 offset:384 + ds_write_b16 v22, v134 offset:1024 + ds_write_b16 v22, v135 offset:1152 + ds_write_b16 v22, v136 offset:1280 + ds_write_b16 v22, v137 offset:1408 + ds_write_b16 v22, v138 offset:2048 + ds_write_b16 v22, v139 offset:2176 + ds_write_b16 v22, v140 offset:2304 + ds_write_b16 v22, v141 offset:2432 + ds_write_b16 v22, v142 offset:3072 + ds_write_b16 v22, v143 offset:3200 + ds_write_b16 v22, v144 offset:3328 + ds_write_b16 v22, v145 offset:3456 + ds_write_b16 v22, v146 offset:8192 + ds_write_b16 v22, v147 offset:8320 + ds_write_b16 v22, v148 offset:8448 + ds_write_b16 v22, v149 offset:8576 + ds_write_b16 v22, v150 offset:9216 + ds_write_b16 v22, v151 offset:9344 + ds_write_b16 v22, v152 offset:9472 + ds_write_b16 v22, v153 offset:9600 + ds_write_b16 v22, v154 offset:10240 + ds_write_b16 v22, v155 offset:10368 + ds_write_b16 v22, v156 offset:10496 + ds_write_b16 v22, v157 offset:10624 + ds_write_b16 v22, v158 offset:11264 + ds_write_b16 v22, v159 offset:11392 + ds_write_b16 v22, v160 offset:11520 + ds_write_b16 v22, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[76:79], v23 offset:384 + v_or_b32_e32 v41, 0xc0, v24 + v_add_u32_e32 v0, v0, v41 + v_lshlrev_b32_e32 v73, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v73, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[76:79], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, v207 offset:128 + ds_write_b16 v22, v206 offset:256 + ds_write_b16 v22, a0 offset:384 + ds_write_b16 v22, a1 offset:1024 + ds_write_b16 v22, v70 offset:1152 + ds_write_b16 v22, v69 offset:1280 + ds_write_b16 v22, v68 offset:1408 + ds_write_b16 v22, v67 offset:2048 + ds_write_b16 v22, v60 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v115 offset:8320 + ds_write_b16 v22, v116 offset:8448 + ds_write_b16 v22, v117 offset:8576 + ds_write_b16 v22, v118 offset:9216 + ds_write_b16 v22, v119 offset:9344 + ds_write_b16 v22, v120 offset:9472 + ds_write_b16 v22, v121 offset:9600 + ds_write_b16 v22, v122 offset:10240 + ds_write_b16 v22, v123 offset:10368 + ds_write_b16 v22, v124 offset:10496 + ds_write_b16 v22, v125 offset:10624 + ds_write_b16 v22, v126 offset:11264 + ds_write_b16 v22, v127 offset:11392 + ds_write_b16 v22, v128 offset:11520 + ds_write_b16 v22, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[60:63], v23 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v64, v0, s16 + v_add_u32_e32 v0, v64, v41 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[60:63], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v114 + ds_write_b16 v22, v193 offset:128 + ds_write_b16 v22, v194 offset:256 + ds_write_b16 v22, v195 offset:384 + ds_write_b16 v22, v196 offset:1024 + ds_write_b16 v22, v197 offset:1152 + ds_write_b16 v22, v198 offset:1280 + ds_write_b16 v22, v199 offset:1408 + ds_write_b16 v22, v200 offset:2048 + ds_write_b16 v22, v48 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v49 offset:3456 + ds_write_b16 v22, v107 offset:8192 + ds_write_b16 v22, v108 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v185 offset:9600 + ds_write_b16 v22, v184 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[44:47], v23 offset:384 + v_add_u32_e32 v0, v64, v40 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[44:47], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v50 offset:8192 + ds_write_b16 v22, v51 offset:8320 + ds_write_b16 v22, v52 offset:8448 + ds_write_b16 v22, v53 offset:8576 + ds_write_b16 v22, v54 offset:9216 + ds_write_b16 v22, v55 offset:9344 + ds_write_b16 v22, v56 offset:9472 + ds_write_b16 v22, v57 offset:9600 + ds_write_b16 v22, v58 offset:10240 + ds_write_b16 v22, v59 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v64, v31 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v25, a49 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a48 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a39 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a38 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a37 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a36 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a35 + v_cvt_f16_f32_e32 v31, v31 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + v_accvgpr_read_b32 v33, a33 + v_cvt_f16_f32_e32 v33, v33 + v_accvgpr_read_b32 v34, a32 + v_cvt_f16_f32_e32 v34, v34 + ds_write_b16 v22, v0 + ds_write_b16 v22, v1 offset:128 + ds_write_b16 v22, v2 offset:256 + ds_write_b16 v22, v3 offset:384 + ds_write_b16 v22, v4 offset:1024 + ds_write_b16 v22, v5 offset:1152 + ds_write_b16 v22, v6 offset:1280 + ds_write_b16 v22, v7 offset:1408 + ds_write_b16 v22, v8 offset:2048 + ds_write_b16 v22, v9 offset:2176 + ds_write_b16 v22, v10 offset:2304 + ds_write_b16 v22, v11 offset:2432 + ds_write_b16 v22, v12 offset:3072 + ds_write_b16 v22, v13 offset:3200 + ds_write_b16 v22, v14 offset:3328 + ds_write_b16 v22, v15 offset:3456 + ds_write_b16 v22, v16 offset:8192 + ds_write_b16 v22, v17 offset:8320 + ds_write_b16 v22, v18 offset:8448 + ds_write_b16 v22, v19 offset:8576 + ds_write_b16 v22, v20 offset:9216 + ds_write_b16 v22, v21 offset:9344 + ds_write_b16 v22, v25 offset:9472 + ds_write_b16 v22, v26 offset:9600 + ds_write_b16 v22, v27 offset:10240 + ds_write_b16 v22, v28 offset:10368 + ds_write_b16 v22, v29 offset:10496 + ds_write_b16 v22, v30 offset:10624 + ds_write_b16 v22, v31 offset:11264 + ds_write_b16 v22, v32 offset:11392 + ds_write_b16 v22, v33 offset:11520 + ds_write_b16 v22, v34 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v64, v24 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end27: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end27-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSF_8RowMajorESH_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 31436 +; TotalNumSgprs: 36 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB28_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB28_5 +; %bb.2: ; %.lr.ph.preheader + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v2, v6 + v_mov_b32_e32 v4, v0 +.LBB28_3: ; %.lr.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[8:9], s[8:9], 0, v[2:3] + global_load_ubyte v3, v[8:9], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_waitcnt vmcnt(1) + v_cvt_f32_bf8_sdwa v3, v3 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_bf8_sdwa v5, v5 src0_sel:BYTE_0 + s_add_i32 s6, s6, -1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v3, v5 + v_add_u32_e32 v2, s7, v2 + s_cbranch_scc0 .LBB28_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB28_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB28_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end28: + .size _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii, .Lfunc_end28-_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm11ColumnMajorENS3_8RowMajorES5_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 432 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_waitcnt lgkmcnt(0) + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v0, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s23, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s18, s18, s15 + s_sub_i32 s6, s6, s18 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s3, s3, 1 + s_add_u32 s10, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s22, s2 + s_add_u32 s14, s2, s3 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[18:19], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[18:19] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v4, -1, 0 + s_cbranch_scc0 .LBB29_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v4 + v_lshlrev_b32_e32 v0, 4, v225 + v_and_b32_e32 v0, 48, v0 + v_and_b32_e32 v1, 0x7c, v225 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v5, s11, v1 + v_add_u32_e32 v1, s20, v5 + v_mad_u64_u32 v[2:3], s[18:19], v1, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[24:27], v2, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v2 + buffer_load_dwordx4 v[30:33], v1, s[8:11], 0 offen + v_and_b32_e32 v2, 31, v225 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[34:37], v3, s[8:11], 0 offen + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v1, 3, v225 + v_lshrrev_b32_e32 v6, 5, v225 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s23, s18, 0x3fffffe0 + v_and_or_b32 v54, v1, 8, v6 + s_and_b32 s18, s19, 32 + v_or_b32_e32 v55, s23, v2 + v_add_u32_e32 v1, s21, v5 + v_or_b32_e32 v2, s18, v2 + v_lshrrev_b32_e32 v6, 3, v0 + v_ashrrev_i32_e32 v7, 1, v5 + v_ashrrev_i32_e32 v8, 31, v5 + v_lshlrev_b32_e32 v9, 6, v5 + v_or_b32_e32 v10, 1, v5 + v_lshrrev_b32_e32 v11, 31, v5 + v_lshrrev_b32_e32 v12, 1, v55 + v_bfe_u32 v13, v55, 1, 4 + v_mad_u64_u32 v[0:1], s[24:25], v1, s22, v[0:1] + v_add_u32_e32 v1, s7, v3 + buffer_load_dwordx4 v[38:41], v1, s[8:11], 0 offen + v_lshrrev_b32_e32 v14, 1, v2 + v_bfe_u32 v20, v2, 1, 4 + v_lshrrev_b32_e32 v1, 28, v8 + v_or_b32_e32 v2, 1, v6 + buffer_load_dwordx4 v[42:45], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[46:49], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[50:53], v0, s[12:15], 0 offen + v_add_u32_e32 v0, s22, v0 + buffer_load_dwordx4 v[56:59], v0, s[12:15], 0 offen + v_add_u32_e32 v0, v10, v11 + v_or_b32_e32 v3, 1, v7 + v_xor_b32_e32 v8, v13, v54 + v_lshlrev_b32_e32 v15, 7, v12 + v_xor_b32_e32 v28, v20, v54 + v_lshlrev_b32_e32 v16, 7, v14 + v_add_u32_e32 v17, v7, v1 + v_sub_u32_e32 v18, v6, v2 + v_ashrrev_i32_e32 v19, 1, v0 + v_and_b32_e32 v21, 0x1ffffffe, v0 + v_ashrrev_i32_e32 v0, 31, v0 + v_and_b32_e32 v17, -16, v17 + v_sub_u32_e32 v22, v19, v7 + v_sub_u32_e32 v10, v10, v21 + v_lshrrev_b32_e32 v0, 28, v0 + v_sub_u32_e32 v7, v7, v17 + v_lshl_or_b32 v10, v10, 3, v2 + v_add_u32_e32 v0, v19, v0 + v_xor_b32_e32 v17, v7, v6 + v_xor_b32_e32 v7, v7, v2 + v_add_u32_e32 v21, v10, v18 + v_and_b32_e32 v0, -16, v0 + v_lshl_add_u32 v17, v17, 3, v9 + v_lshl_add_u32 v9, v7, 3, v9 + v_sub_u32_e32 v0, v19, v0 + v_xor_b32_e32 v21, v21, v0 + v_lshl_add_u32 v22, v22, 7, v9 + v_xor_b32_e32 v0, v10, v0 + v_sub_u32_e32 v10, v21, v7 + v_sub_u32_e32 v7, v0, v7 + v_lshl_add_u32 v10, v10, 3, v22 + v_lshl_add_u32 v7, v7, 3, v22 + s_waitcnt vmcnt(7) + ds_write_b64 v17, v[24:25] + ds_write_b64 v9, v[26:27] + s_waitcnt vmcnt(6) + ds_write_b64 v10, v[30:31] + ds_write_b64 v7, v[32:33] + v_sub_u32_e32 v19, v3, v19 + v_add_u32_e32 v1, v3, v1 + v_and_b32_e32 v1, -16, v1 + v_sub_u32_e32 v1, v3, v1 + v_xor_b32_e32 v6, v1, v6 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v19, 7, v19 + v_add3_u32 v0, v0, v19, v7 + s_waitcnt vmcnt(5) + ds_write_b64 v0, v[34:35] + v_xor_b32_e32 v1, v1, v2 + v_sub_u32_e32 v6, v1, v6 + v_lshl_add_u32 v6, v6, 3, v0 + ds_write_b64 v6, v[36:37] + v_or_b32_e32 v5, 3, v5 + v_add_u32_e32 v11, v5, v11 + v_ashrrev_i32_e32 v19, 1, v11 + v_sub_u32_e32 v3, v19, v3 + v_and_b32_e32 v21, 0x1ffffffe, v11 + v_sub_u32_e32 v5, v5, v21 + v_lshl_or_b32 v2, v5, 3, v2 + v_add_u32_e32 v5, v2, v18 + v_ashrrev_i32_e32 v11, 31, v11 + v_lshrrev_b32_e32 v11, 28, v11 + v_add_u32_e32 v11, v19, v11 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v19, v11 + v_xor_b32_e32 v5, v5, v11 + v_sub_u32_e32 v1, v5, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v3, 7, v3 + v_add3_u32 v1, v1, v3, v6 + s_waitcnt vmcnt(4) + ds_write_b64 v1, v[38:39] + v_xor_b32_e32 v2, v2, v11 + v_sub_u32_e32 v2, v2, v5 + v_lshl_add_u32 v2, v2, 3, v1 + ds_write_b64 v2, v[40:41] + s_waitcnt vmcnt(3) + ds_write_b64 v17, v[42:43] offset:16384 + ds_write_b64 v9, v[44:45] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v10, v[46:47] offset:16384 + ds_write_b64 v7, v[48:49] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v0, v[50:51] offset:16384 + ds_write_b64 v6, v[52:53] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v1, v[56:57] offset:16384 + ds_write_b64 v2, v[58:59] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v0, v8, 3, v15 + v_add_u32_e32 v5, 2, v54 + v_xor_b32_e32 v1, v5, v13 + v_lshl_add_u32 v2, v1, 3, v15 + v_or_b32_e32 v56, 4, v54 + v_xor_b32_e32 v1, v56, v13 + v_lshl_add_u32 v3, v1, 3, v15 + v_add_u32_e32 v57, 6, v54 + v_xor_b32_e32 v44, v57, v13 + v_lshl_add_u32 v10, v44, 3, v15 + ds_read_b64 v[0:1], v0 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[8:9], v3 + ds_read_b64 v[2:3], v10 + v_add_u32_e32 v11, 64, v55 + v_lshrrev_b32_e32 v48, 1, v11 + v_sub_u32_e32 v12, v48, v12 + v_bfe_u32 v45, v11, 1, 4 + v_xor_b32_e32 v11, v45, v54 + v_sub_u32_e32 v11, v11, v44 + v_lshl_add_u32 v46, v12, 7, v10 + v_lshl_add_u32 v10, v11, 3, v46 + ds_read_b64 v[10:11], v10 + v_xor_b32_e32 v12, v45, v5 + v_sub_u32_e32 v12, v12, v44 + v_lshl_add_u32 v47, v12, 3, v46 + v_xor_b32_e32 v12, v45, v56 + v_sub_u32_e32 v12, v12, v44 + v_lshl_add_u32 v49, v12, 3, v46 + v_lshl_or_b32 v12, v28, 3, v16 + v_add_u32_e32 v13, -16, v14 + s_cmp_eq_u32 s18, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v13, v13, v14, vcc + v_xor_b32_e32 v14, v13, v5 + v_lshl_add_u32 v14, v14, 3, v16 + v_xor_b32_e32 v15, v13, v56 + v_lshl_add_u32 v17, v15, 3, v16 + v_xor_b32_e32 v21, v13, v57 + v_lshl_add_u32 v22, v21, 3, v16 + ds_read_b64 v[12:13], v12 offset:16384 + ds_read_b64 v[14:15], v14 offset:16384 + ds_read_b64 v[16:17], v17 offset:16384 + ds_read_b64 v[18:19], v22 offset:16384 + v_sub_u32_e32 v21, v28, v21 + v_lshl_add_u32 v21, v21, 3, v22 + v_xor_b32_e32 v22, v20, v5 + v_sub_u32_e32 v22, v22, v28 + v_lshlrev_b32_e32 v38, 3, v22 + v_add_u32_e32 v22, v21, v38 + v_xor_b32_e32 v23, v20, v56 + v_sub_u32_e32 v23, v23, v28 + v_lshlrev_b32_e32 v39, 3, v23 + v_add_u32_e32 v24, v21, v39 + v_xor_b32_e32 v29, v20, v57 + v_sub_u32_e32 v20, v29, v28 + v_lshlrev_b32_e32 v40, 3, v20 + v_add_u32_e32 v30, v21, v40 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[12:13], 0 + ds_read_b64 v[20:21], v21 offset:20480 + ds_read_b64 v[22:23], v22 offset:20480 + ds_read_b64 v[24:25], v24 offset:20480 + ds_read_b64 v[26:27], v30 offset:20480 + v_sub_u32_e32 v28, v28, v29 + v_lshlrev_b32_e32 v36, 3, v28 + v_add_u32_e32 v28, v30, v36 + v_add_u32_e32 v30, v28, v38 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[20:21], 0 + v_add_u32_e32 v32, v28, v39 + v_add_u32_e32 v37, v28, v40 + ds_read_b64 v[28:29], v28 offset:24576 + ds_read_b64 v[30:31], v30 offset:24576 + ds_read_b64 v[32:33], v32 offset:24576 + ds_read_b64 v[34:35], v37 offset:24576 + v_add_u32_e32 v41, v37, v36 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[28:29], 0 + ds_read_b64 v[36:37], v41 offset:28672 + v_add_u32_e32 v38, v41, v38 + v_add_u32_e32 v42, v41, v39 + v_add_u32_e32 v43, v41, v40 + ds_read_b64 v[38:39], v38 offset:28672 + ds_read_b64 v[40:41], v42 offset:28672 + ds_read_b64 v[42:43], v43 offset:28672 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[36:37], 0 + v_xor_b32_e32 v50, v45, v57 + v_sub_u32_e32 v0, v50, v44 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v58, v0, v46 + ds_read_b64 v[0:1], v47 + ds_read_b64 v[44:45], v49 + ds_read_b64 v[46:47], v58 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[10:11], v[12:13], 0 + v_add_u32_e32 v49, 0x80, v55 + v_lshrrev_b32_e32 v59, 1, v49 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[10:11], v[20:21], 0 + v_sub_u32_e32 v48, v59, v48 + v_bfe_u32 v51, v49, 1, 4 + v_xor_b32_e32 v52, v51, v54 + v_sub_u32_e32 v49, v52, v50 + v_lshlrev_b32_e32 v48, 7, v48 + v_lshl_add_u32 v60, v49, 3, v48 + v_add_u32_e32 v50, v58, v60 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[10:11], v[28:29], 0 + ds_read_b64 v[48:49], v50 + v_xor_b32_e32 v53, v51, v5 + v_sub_u32_e32 v53, v53, v52 + v_lshl_add_u32 v53, v53, 3, v50 + v_xor_b32_e32 v61, v51, v56 + v_sub_u32_e32 v61, v61, v52 + v_lshl_add_u32 v61, v61, 3, v50 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[10:11], v[36:37], 0 + v_xor_b32_e32 v62, v51, v57 + v_sub_u32_e32 v10, v62, v52 + v_lshlrev_b32_e32 v63, 3, v10 + v_add_u32_e32 v52, v50, v63 + ds_read_b64 v[10:11], v53 + ds_read_b64 v[50:51], v61 + ds_read_b64 v[52:53], v52 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[48:49], v[12:13], 0 + v_add3_u32 v58, v60, v58, v63 + v_add_u32_e32 v55, 0xc0, v55 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[48:49], v[20:21], 0 + v_lshrrev_b32_e32 v60, 1, v55 + v_sub_u32_e32 v59, v60, v59 + v_bfe_u32 v60, v55, 1, 4 + v_xor_b32_e32 v61, v60, v54 + v_sub_u32_e32 v54, v61, v62 + v_lshlrev_b32_e32 v54, 3, v54 + v_lshlrev_b32_e32 v55, 7, v59 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[48:49], v[28:29], 0 + v_add3_u32 v58, v54, v55, v58 + ds_read_b64 v[54:55], v58 + v_xor_b32_e32 v5, v60, v5 + v_sub_u32_e32 v5, v5, v61 + v_lshl_add_u32 v5, v5, 3, v58 + v_xor_b32_e32 v56, v60, v56 + v_sub_u32_e32 v56, v56, v61 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[48:49], v[36:37], 0 + v_lshl_add_u32 v56, v56, 3, v58 + v_xor_b32_e32 v48, v60, v57 + v_sub_u32_e32 v48, v48, v61 + v_lshl_add_u32 v58, v48, 3, v58 + ds_read_b64 v[48:49], v5 + ds_read_b64 v[56:57], v56 + ds_read_b64 v[58:59], v58 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[54:55], v[12:13], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[54:55], v[20:21], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[54:55], v[28:29], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[54:55], v[36:37], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[6:7], v[14:15], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[6:7], v[22:23], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[6:7], v[30:31], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[6:7], v[38:39], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[14:15], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[22:23], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[30:31], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[38:39], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[10:11], v[14:15], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[10:11], v[22:23], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[10:11], v[30:31], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[10:11], v[38:39], a[48:63] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[48:49], v[14:15], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[48:49], v[22:23], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[48:49], v[30:31], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[48:49], v[38:39], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[8:9], v[16:17], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[8:9], v[24:25], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[8:9], v[32:33], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[8:9], v[40:41], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[44:45], v[16:17], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[44:45], v[24:25], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[44:45], v[32:33], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[44:45], v[40:41], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[50:51], v[16:17], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[50:51], v[24:25], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[50:51], v[32:33], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[50:51], v[40:41], a[48:63] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[56:57], v[16:17], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[56:57], v[24:25], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[56:57], v[32:33], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[56:57], v[40:41], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[2:3], v[18:19], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[2:3], v[26:27], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[2:3], v[34:35], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[2:3], v[42:43], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[46:47], v[18:19], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[46:47], v[26:27], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[46:47], v[34:35], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[46:47], v[42:43], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[52:53], v[18:19], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[52:53], v[26:27], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[52:53], v[34:35], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[52:53], v[42:43], a[48:63] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[58:59], v[18:19], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[58:59], v[26:27], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[58:59], v[34:35], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[58:59], v[42:43], a[176:191] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB29_3 + s_branch .LBB29_10 +.LBB29_2: + ; implicit-def: $agpr15 + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr207 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr255 + ; implicit-def: $agpr176_agpr177_agpr178_agpr179_agpr180_agpr181_agpr182_agpr183_agpr184_agpr185_agpr186_agpr187_agpr188_agpr189_agpr190_agpr191 + ; implicit-def: $vgpr225 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB29_3: + s_mov_b32 s11, s7 + v_readfirstlane_b32 s15, v227 + v_mbcnt_hi_u32_b32 v225, -1, v4 + v_lshlrev_b32_e32 v0, 4, v225 + v_and_b32_e32 v4, 48, v0 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v54, 0x7c, v225 + v_add_u32_e32 v1, s18, v54 + v_add_u32_e32 v0, s20, v1 + v_mad_u64_u32 v[2:3], s[18:19], v0, s11, v[4:5] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[24:27], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[28:31], v0, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v0 + buffer_load_dwordx4 v[32:35], v3, s[8:11], 0 offen + v_lshrrev_b32_e32 v0, 5, v225 + v_and_b32_e32 v5, 31, v225 + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v6, 3, v225 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s18, s18, 0x3fffffe0 + v_and_or_b32 v7, v6, 8, v0 + v_and_or_b32 v0, s19, 32, v5 + v_or_b32_e32 v8, s18, v5 + v_add_u32_e32 v5, s21, v1 + v_lshrrev_b32_e32 v9, 1, v0 + v_bfe_u32 v6, v0, 1, 4 + v_lshrrev_b32_e32 v55, 3, v4 + v_ashrrev_i32_e32 v12, 1, v1 + v_ashrrev_i32_e32 v11, 31, v1 + v_lshlrev_b32_e32 v13, 6, v1 + v_or_b32_e32 v14, 1, v1 + v_lshrrev_b32_e32 v15, 31, v1 + v_lshrrev_b32_e32 v0, 1, v8 + v_bfe_u32 v10, v8, 1, 4 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[36:39], v3, s[8:11], 0 offen + v_mad_u64_u32 v[4:5], s[18:19], v5, s22, v[4:5] + v_xor_b32_e32 v5, v6, v7 + v_lshlrev_b32_e32 v9, 7, v9 + buffer_load_dwordx4 v[40:43], v4, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v4 + buffer_load_dwordx4 v[44:47], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[48:51], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[58:61], v3, s[12:15], 0 offen + v_lshrrev_b32_e32 v16, 28, v11 + v_or_b32_e32 v56, 1, v55 + v_add_u32_e32 v17, v14, v15 + v_or_b32_e32 v18, 1, v12 + v_xor_b32_e32 v3, v10, v7 + v_lshlrev_b32_e32 v11, 7, v0 + v_add_u32_e32 v19, v12, v16 + v_sub_u32_e32 v57, v55, v56 + v_ashrrev_i32_e32 v20, 1, v17 + v_and_b32_e32 v21, 0x1ffffffe, v17 + v_ashrrev_i32_e32 v17, 31, v17 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v22, v20, v12 + v_sub_u32_e32 v14, v14, v21 + v_lshrrev_b32_e32 v17, 28, v17 + v_sub_u32_e32 v12, v12, v19 + v_lshl_or_b32 v14, v14, 3, v56 + v_add_u32_e32 v17, v20, v17 + v_xor_b32_e32 v19, v12, v55 + v_xor_b32_e32 v12, v12, v56 + v_add_u32_e32 v21, v14, v57 + v_and_b32_e32 v17, -16, v17 + v_lshl_add_u32 v19, v19, 3, v13 + v_lshl_add_u32 v13, v12, 3, v13 + v_sub_u32_e32 v17, v20, v17 + v_xor_b32_e32 v21, v21, v17 + v_lshl_add_u32 v22, v22, 7, v13 + v_xor_b32_e32 v14, v14, v17 + v_sub_u32_e32 v17, v21, v12 + v_sub_u32_e32 v12, v14, v12 + v_lshl_add_u32 v17, v17, 3, v22 + v_lshl_add_u32 v12, v12, 3, v22 + s_waitcnt vmcnt(7) + ds_write_b64 v19, v[24:25] + ds_write_b64 v13, v[26:27] + s_waitcnt vmcnt(6) + ds_write_b64 v17, v[28:29] + ds_write_b64 v12, v[30:31] + v_sub_u32_e32 v20, v18, v20 + v_add_u32_e32 v16, v18, v16 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v16, v18, v16 + v_xor_b32_e32 v21, v16, v55 + v_sub_u32_e32 v14, v21, v14 + v_lshlrev_b32_e32 v14, 3, v14 + v_lshlrev_b32_e32 v20, 7, v20 + v_add3_u32 v14, v14, v20, v12 + s_waitcnt vmcnt(5) + ds_write_b64 v14, v[32:33] + v_xor_b32_e32 v16, v16, v56 + v_sub_u32_e32 v20, v16, v21 + v_lshl_add_u32 v20, v20, 3, v14 + ds_write_b64 v20, v[34:35] + v_or_b32_e32 v1, 3, v1 + v_add_u32_e32 v15, v1, v15 + v_ashrrev_i32_e32 v21, 1, v15 + v_sub_u32_e32 v18, v21, v18 + v_and_b32_e32 v22, 0x1ffffffe, v15 + v_sub_u32_e32 v1, v1, v22 + v_lshl_or_b32 v1, v1, 3, v56 + v_add_u32_e32 v22, v1, v57 + v_ashrrev_i32_e32 v15, 31, v15 + v_lshrrev_b32_e32 v15, 28, v15 + v_add_u32_e32 v15, v21, v15 + v_and_b32_e32 v15, -16, v15 + v_sub_u32_e32 v15, v21, v15 + v_xor_b32_e32 v21, v22, v15 + v_sub_u32_e32 v16, v21, v16 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshlrev_b32_e32 v18, 7, v18 + v_add3_u32 v16, v16, v18, v20 + s_waitcnt vmcnt(4) + ds_write_b64 v16, v[36:37] + v_xor_b32_e32 v1, v1, v15 + v_sub_u32_e32 v1, v1, v21 + v_lshl_add_u32 v1, v1, 3, v16 + ds_write_b64 v1, v[38:39] + s_waitcnt vmcnt(3) + ds_write_b64 v19, v[40:41] offset:16384 + ds_write_b64 v13, v[42:43] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v17, v[44:45] offset:16384 + ds_write_b64 v12, v[46:47] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v14, v[48:49] offset:16384 + ds_write_b64 v20, v[50:51] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v16, v[58:59] offset:16384 + ds_write_b64 v1, v[60:61] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v14, 2, v7 + v_add_u32_e32 v13, 4, v7 + v_add_u32_e32 v12, 6, v7 + v_add_u32_e32 v15, 64, v8 + s_cbranch_vccnz .LBB29_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit993.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v14, v10 + v_lshl_add_u32 v29, v1, 3, v11 + v_xor_b32_e32 v1, v13, v10 + v_lshl_add_u32 v26, v1, 3, v11 + v_xor_b32_e32 v1, v12, v10 + v_lshl_add_u32 v25, v1, 3, v11 + v_lshrrev_b32_e32 v16, 1, v15 + v_sub_u32_e32 v17, v16, v0 + v_bfe_u32 v18, v15, 1, 4 + v_xor_b32_e32 v19, v18, v7 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v17, v17, 7, v25 + v_lshl_add_u32 v46, v19, 3, v17 + v_xor_b32_e32 v19, v18, v14 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v30, v19, 3, v17 + v_xor_b32_e32 v19, v18, v13 + v_sub_u32_e32 v19, v19, v1 + v_lshl_add_u32 v27, v19, 3, v17 + v_xor_b32_e32 v18, v18, v12 + v_sub_u32_e32 v1, v18, v1 + v_lshl_add_u32 v22, v1, 3, v17 + v_add_u32_e32 v1, 0x80, v8 + v_lshrrev_b32_e32 v17, 1, v1 + v_sub_u32_e32 v16, v17, v16 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v19, v1, v7 + v_sub_u32_e32 v18, v19, v18 + v_lshlrev_b32_e32 v18, 3, v18 + v_lshlrev_b32_e32 v16, 7, v16 + v_add3_u32 v47, v18, v16, v22 + v_xor_b32_e32 v16, v1, v14 + v_sub_u32_e32 v16, v16, v19 + v_lshl_add_u32 v36, v16, 3, v47 + v_xor_b32_e32 v16, v1, v13 + v_sub_u32_e32 v16, v16, v19 + v_lshl_add_u32 v28, v16, 3, v47 + v_xor_b32_e32 v1, v1, v12 + v_sub_u32_e32 v16, v1, v19 + v_lshl_add_u32 v23, v16, 3, v47 + v_add_u32_e32 v16, 0xc0, v8 + v_lshrrev_b32_e32 v18, 1, v16 + v_sub_u32_e32 v17, v18, v17 + v_bfe_u32 v16, v16, 1, 4 + v_xor_b32_e32 v18, v16, v7 + v_sub_u32_e32 v1, v18, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v17, 7, v17 + v_add3_u32 v48, v1, v17, v23 + v_xor_b32_e32 v1, v16, v14 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v39, v1, 3, v48 + v_xor_b32_e32 v1, v16, v13 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v31, v1, 3, v48 + v_xor_b32_e32 v1, v16, v12 + v_sub_u32_e32 v1, v1, v18 + v_lshl_add_u32 v24, v1, 3, v48 + v_xor_b32_e32 v1, v6, v14 + v_lshl_add_u32 v42, v1, 3, v9 + v_xor_b32_e32 v16, v6, v13 + v_lshl_add_u32 v37, v16, 3, v9 + v_xor_b32_e32 v17, v6, v12 + v_lshl_add_u32 v34, v17, 3, v9 + v_sub_u32_e32 v18, v5, v17 + v_mov_b32_e32 v19, 0x1000 + v_lshl_add_u32 v18, v18, 3, v19 + v_add_u32_e32 v49, v18, v34 + v_sub_u32_e32 v1, v1, v5 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v43, v49, v1 + v_sub_u32_e32 v16, v16, v5 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v38, v49, v16 + v_sub_u32_e32 v17, v17, v5 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v32, v49, v17 + v_add_u32_e32 v50, v32, v18 + v_add_u32_e32 v44, v50, v1 + v_add_u32_e32 v40, v50, v16 + v_add_u32_e32 v33, v50, v17 + v_add_u32_e32 v51, v33, v18 + v_add_u32_e32 v45, v51, v1 + v_add_u32_e32 v41, v51, v16 + v_add_u32_e32 v35, v51, v17 + s_mov_b64 s[2:3], 0 + s_branch .LBB29_6 +.LBB29_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr29 + ; implicit-def: $vgpr26 + ; implicit-def: $vgpr25 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr30 + ; implicit-def: $vgpr27 + ; implicit-def: $vgpr22 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr28 + ; implicit-def: $vgpr23 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr31 + ; implicit-def: $vgpr24 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr34 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr32 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr33 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr35 +.LBB29_6: ; %Flow80 + v_lshl_or_b32 v53, v3, 3, v11 + v_lshl_or_b32 v52, v5, 3, v9 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB29_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v3, v4 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v1, v14, v10 + v_lshl_add_u32 v29, v1, 3, v11 + v_xor_b32_e32 v1, v13, v10 + v_lshl_add_u32 v26, v1, 3, v11 + v_xor_b32_e32 v1, v12, v10 + v_lshl_add_u32 v25, v1, 3, v11 + v_lshrrev_b32_e32 v4, 1, v15 + v_sub_u32_e32 v0, v4, v0 + v_bfe_u32 v10, v15, 1, 4 + v_xor_b32_e32 v11, v10, v7 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v0, v0, 7, v25 + v_lshl_add_u32 v46, v11, 3, v0 + v_xor_b32_e32 v11, v10, v14 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v30, v11, 3, v0 + v_xor_b32_e32 v11, v10, v13 + v_sub_u32_e32 v11, v11, v1 + v_lshl_add_u32 v27, v11, 3, v0 + v_xor_b32_e32 v10, v10, v12 + v_sub_u32_e32 v1, v10, v1 + v_lshl_add_u32 v22, v1, 3, v0 + v_add_u32_e32 v0, 0x80, v8 + v_lshrrev_b32_e32 v1, 1, v0 + v_sub_u32_e32 v4, v1, v4 + v_bfe_u32 v0, v0, 1, 4 + v_xor_b32_e32 v11, v0, v7 + v_sub_u32_e32 v10, v11, v10 + v_lshlrev_b32_e32 v10, 3, v10 + v_lshlrev_b32_e32 v4, 7, v4 + v_add3_u32 v47, v10, v4, v22 + v_xor_b32_e32 v4, v0, v14 + v_sub_u32_e32 v4, v4, v11 + v_lshl_add_u32 v36, v4, 3, v47 + v_xor_b32_e32 v4, v0, v13 + v_sub_u32_e32 v4, v4, v11 + v_lshl_add_u32 v28, v4, 3, v47 + v_xor_b32_e32 v0, v0, v12 + v_sub_u32_e32 v4, v0, v11 + v_lshl_add_u32 v23, v4, 3, v47 + v_add_u32_e32 v4, 0xc0, v8 + v_lshrrev_b32_e32 v8, 1, v4 + v_sub_u32_e32 v1, v8, v1 + v_bfe_u32 v4, v4, 1, 4 + v_xor_b32_e32 v7, v4, v7 + v_sub_u32_e32 v0, v7, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v48, v0, v1, v23 + v_xor_b32_e32 v0, v4, v14 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v39, v0, 3, v48 + v_xor_b32_e32 v0, v4, v13 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v31, v0, 3, v48 + v_xor_b32_e32 v0, v4, v12 + v_sub_u32_e32 v0, v0, v7 + v_lshl_add_u32 v24, v0, 3, v48 + v_xor_b32_e32 v0, v6, v14 + v_lshl_add_u32 v42, v0, 3, v9 + v_xor_b32_e32 v1, v6, v13 + v_lshl_add_u32 v37, v1, 3, v9 + v_xor_b32_e32 v4, v6, v12 + v_lshl_add_u32 v34, v4, 3, v9 + v_sub_u32_e32 v6, v5, v4 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_u32_e32 v7, 0x1000, v6 + v_add_u32_e32 v49, v7, v34 + v_add_u32_e32 v58, v6, v34 + v_sub_u32_e32 v0, v0, v5 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v43, v49, v0 + v_add_u32_e32 v59, v58, v0 + v_sub_u32_e32 v1, v1, v5 + v_lshlrev_b32_e32 v1, 3, v1 + v_add_u32_e32 v38, v49, v1 + v_add_u32_e32 v60, v58, v1 + v_sub_u32_e32 v4, v4, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v32, v49, v4 + v_add_u32_e32 v61, v58, v4 + v_add_u32_e32 v50, v32, v7 + v_add_u32_e32 v62, v61, v7 + v_add_u32_e32 v44, v50, v0 + v_add_u32_e32 v40, v50, v1 + v_add_u32_e32 v33, v50, v4 + v_add_u32_e32 v51, v33, v7 + v_add_u32_e32 v45, v51, v0 + v_add_u32_e32 v41, v51, v1 + v_add_u32_e32 v35, v51, v4 + s_add_i32 s2, s2, 1 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 +.LBB29_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v5, 64, v3 + v_add_u32_e32 v4, 64, v2 + buffer_load_dwordx4 v[64:67], v2, s[8:11], 0 offen offset:64 + buffer_load_dwordx4 v[68:71], v3, s[12:15], 0 offen offset:64 + v_add_u32_e32 v0, s7, v4 + v_add_u32_e32 v1, s22, v5 + v_add_u32_e32 v2, s7, v0 + buffer_load_dwordx4 v[72:75], v1, s[12:15], 0 offen + v_add_u32_e32 v1, s22, v1 + buffer_load_dwordx4 v[88:91], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[84:87], v2, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + buffer_load_dwordx4 v[76:79], v1, s[12:15], 0 offen + v_add_u32_e32 v1, s22, v1 + buffer_load_dwordx4 v[92:95], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[80:83], v1, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[0:1], v53 + ds_read_b64 v[8:9], v52 offset:16384 + ds_read_b64 v[20:21], v58 offset:20480 + ds_read_b64 v[10:11], v59 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[8:9], a[64:79] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[20:21], a[80:95] + ds_read_b64 v[96:97], v62 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[96:97], a[96:111] + ds_read_b64 v[98:99], v50 offset:20480 + ds_read_b64 v[12:13], v44 offset:20480 + ds_read_b64 v[2:3], v40 offset:20480 + ds_read_b64 v[6:7], v33 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[98:99], a[112:127] + ds_read_b64 v[0:1], v46 + ds_read_b64 v[14:15], v30 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[8:9], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[20:21], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[96:97], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[98:99], a[176:191] + ds_read_b64 v[0:1], v47 + ds_read_b64 v[16:17], v36 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[8:9], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[20:21], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[96:97], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[98:99], a[240:255] + ds_read_b64 v[0:1], v48 + ds_read_b64 v[18:19], v39 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[8:9], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[20:21], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[96:97], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[98:99], a[48:63] + ds_read_b64 v[0:1], v29 + ds_read_b64 v[20:21], v42 offset:16384 + ds_read_b64 v[96:97], v37 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[20:21], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[10:11], a[80:95] + ds_read_b64 v[98:99], v43 offset:20480 + ds_read_b64 v[100:101], v38 offset:20480 + ds_read_b64 v[8:9], v32 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[98:99], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[12:13], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[14:15], v[20:21], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[14:15], v[10:11], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[14:15], v[98:99], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[14:15], v[12:13], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[16:17], v[20:21], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[16:17], v[10:11], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[16:17], v[98:99], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[16:17], v[12:13], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[18:19], v[20:21], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[18:19], v[10:11], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[18:19], v[98:99], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[18:19], v[12:13], a[48:63] + ds_read_b64 v[0:1], v26 + ds_read_b64 v[20:21], v25 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[96:97], a[64:79] + ds_read_b64 v[18:19], v60 offset:20480 + ds_read_b64 v[10:11], v61 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[18:19], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[100:101], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[2:3], a[112:127] + ds_read_b64 v[0:1], v27 + ds_read_b64 v[12:13], v22 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[96:97], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[18:19], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[100:101], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[2:3], a[176:191] + ds_read_b64 v[0:1], v28 + ds_read_b64 v[14:15], v23 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[96:97], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[18:19], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[100:101], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[0:1], v31 + ds_read_b64 v[16:17], v24 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[96:97], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[18:19], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[100:101], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[2:3], a[48:63] + ds_read_b64 v[18:19], v34 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[20:21], v[18:19], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[20:21], v[10:11], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[20:21], v[8:9], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[20:21], v[6:7], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[12:13], v[18:19], a[128:143] + v_readfirstlane_b32 s3, v227 + s_add_i32 s2, s2, -1 + s_andn2_b32 s3, s3, 63 + v_add_u32_e32 v0, s3, v54 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[12:13], v[10:11], a[144:159] + s_cmp_gt_u32 s2, 2 + v_ashrrev_i32_e32 v1, 1, v0 + v_ashrrev_i32_e32 v2, 31, v0 + v_lshlrev_b32_e32 v20, 6, v0 + v_or_b32_e32 v21, 1, v0 + v_lshrrev_b32_e32 v3, 31, v0 + v_or_b32_e32 v0, 3, v0 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[12:13], v[8:9], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v63, 28, v2 + v_add_u32_e32 v96, v21, v3 + v_or_b32_e32 v97, 1, v1 + v_add_u32_e32 v98, v0, v3 + v_mov_b64_e32 v[2:3], v[4:5] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[12:13], v[6:7], a[176:191] + v_add_u32_e32 v4, v1, v63 + v_ashrrev_i32_e32 v5, 1, v96 + v_and_b32_e32 v12, 0x1ffffffe, v96 + v_ashrrev_i32_e32 v13, 31, v96 + v_add_u32_e32 v63, v97, v63 + v_ashrrev_i32_e32 v96, 1, v98 + v_and_b32_e32 v99, 0x1ffffffe, v98 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[14:15], v[18:19], a[192:207] + v_ashrrev_i32_e32 v98, 31, v98 + v_and_b32_e32 v4, -16, v4 + v_sub_u32_e32 v100, v5, v1 + v_sub_u32_e32 v12, v21, v12 + v_lshrrev_b32_e32 v13, 28, v13 + v_sub_u32_e32 v21, v97, v5 + v_and_b32_e32 v63, -16, v63 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[14:15], v[10:11], a[208:223] + v_sub_u32_e32 v101, v96, v97 + v_sub_u32_e32 v0, v0, v99 + v_lshrrev_b32_e32 v98, 28, v98 + v_sub_u32_e32 v1, v1, v4 + v_lshl_or_b32 v4, v12, 3, v56 + v_add_u32_e32 v12, v5, v13 + v_sub_u32_e32 v13, v97, v63 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[14:15], v[8:9], a[224:239] + v_lshlrev_b32_e32 v21, 7, v21 + v_lshl_or_b32 v0, v0, 3, v56 + v_add_u32_e32 v63, v96, v98 + v_lshlrev_b32_e32 v97, 7, v101 + v_xor_b32_e32 v98, v1, v55 + v_xor_b32_e32 v1, v1, v56 + v_add_u32_e32 v99, v4, v57 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[14:15], v[6:7], a[240:255] + v_and_b32_e32 v12, -16, v12 + v_xor_b32_e32 v14, v13, v55 + v_xor_b32_e32 v13, v13, v56 + v_add_u32_e32 v15, v0, v57 + v_and_b32_e32 v63, -16, v63 + v_lshl_add_u32 v98, v98, 3, v20 + v_lshl_add_u32 v20, v1, 3, v20 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[16:17], v[18:19], a[16:31] + v_sub_u32_e32 v5, v5, v12 + v_sub_u32_e32 v12, v13, v14 + v_sub_u32_e32 v18, v96, v63 + v_xor_b32_e32 v19, v99, v5 + v_lshl_add_u32 v63, v100, 7, v20 + v_xor_b32_e32 v4, v4, v5 + v_xor_b32_e32 v5, v15, v18 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[16:17], v[10:11], a[32:47] + v_xor_b32_e32 v0, v0, v18 + v_sub_u32_e32 v10, v19, v1 + v_sub_u32_e32 v1, v4, v1 + v_sub_u32_e32 v4, v14, v4 + v_sub_u32_e32 v11, v5, v13 + v_sub_u32_e32 v0, v0, v5 + v_lshl_add_u32 v5, v10, 3, v63 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[16:17], v[8:9], a[0:15] + v_lshl_add_u32 v1, v1, 3, v63 + v_lshlrev_b32_e32 v4, 3, v4 + v_lshlrev_b32_e32 v8, 3, v11 + v_add3_u32 v4, v4, v21, v1 + v_lshl_add_u32 v9, v12, 3, v4 + v_add3_u32 v8, v8, v97, v9 + v_lshl_add_u32 v0, v0, 3, v8 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[16:17], v[6:7], a[48:63] + s_waitcnt vmcnt(7) + ds_write_b64 v98, v[64:65] + ds_write_b64 v20, v[66:67] + s_waitcnt vmcnt(4) + ds_write_b64 v5, v[88:89] + ds_write_b64 v1, v[90:91] + s_waitcnt vmcnt(3) + ds_write_b64 v4, v[84:85] + ds_write_b64 v9, v[86:87] + s_waitcnt vmcnt(1) + ds_write_b64 v8, v[92:93] + ds_write_b64 v0, v[94:95] + ds_write_b64 v98, v[68:69] offset:16384 + ds_write_b64 v20, v[70:71] offset:16384 + ds_write_b64 v5, v[72:73] offset:16384 + ds_write_b64 v1, v[74:75] offset:16384 + ds_write_b64 v4, v[76:77] offset:16384 + ds_write_b64 v9, v[78:79] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v8, v[80:81] offset:16384 + ds_write_b64 v0, v[82:83] offset:16384 + s_cbranch_scc1 .LBB29_8 +.LBB29_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iP + v_accvgpr_read_b32 v0, a160 + v_accvgpr_read_b32 v1, a161 + v_accvgpr_read_b32 v2, a162 + v_accvgpr_read_b32 v3, a163 + v_accvgpr_read_b32 v4, a164 + v_accvgpr_read_b32 v5, a165 + v_accvgpr_read_b32 v6, a166 + v_accvgpr_read_b32 v7, a167 + v_accvgpr_read_b32 v8, a168 + v_accvgpr_read_b32 v9, a169 + v_accvgpr_read_b32 v10, a170 + v_accvgpr_read_b32 v11, a171 + v_accvgpr_read_b32 v12, a172 + v_accvgpr_read_b32 v13, a173 + v_accvgpr_read_b32 v14, a174 + v_accvgpr_read_b32 v15, a175 + v_accvgpr_read_b32 v54, a192 + v_accvgpr_read_b32 v55, a193 + v_accvgpr_read_b32 v56, a194 + v_accvgpr_read_b32 v57, a195 + v_accvgpr_read_b32 v58, a196 + v_accvgpr_read_b32 v59, a197 + v_accvgpr_read_b32 v60, a198 + v_accvgpr_read_b32 v61, a199 + v_accvgpr_read_b32 v62, a200 + v_accvgpr_read_b32 v63, a201 + v_accvgpr_read_b32 v64, a202 + v_accvgpr_read_b32 v65, a203 + v_accvgpr_read_b32 v66, a204 + v_accvgpr_read_b32 v67, a205 + v_accvgpr_read_b32 v68, a206 + v_accvgpr_read_b32 v69, a207 + v_accvgpr_read_b32 v70, a208 + v_accvgpr_read_b32 v71, a209 + v_accvgpr_read_b32 v72, a210 + v_accvgpr_read_b32 v73, a211 + v_accvgpr_read_b32 v74, a212 + v_accvgpr_read_b32 v75, a213 + v_accvgpr_read_b32 v76, a214 + v_accvgpr_read_b32 v77, a215 + v_accvgpr_read_b32 v78, a216 + v_accvgpr_read_b32 v79, a217 + v_accvgpr_read_b32 v80, a218 + v_accvgpr_read_b32 v81, a219 + v_accvgpr_read_b32 v82, a220 + v_accvgpr_read_b32 v83, a221 + v_accvgpr_read_b32 v84, a222 + v_accvgpr_read_b32 v85, a223 + v_accvgpr_read_b32 v86, a224 + v_accvgpr_read_b32 v87, a225 + v_accvgpr_read_b32 v88, a226 + v_accvgpr_read_b32 v89, a227 + v_accvgpr_read_b32 v90, a228 + v_accvgpr_read_b32 v91, a229 + v_accvgpr_read_b32 v92, a230 + v_accvgpr_read_b32 v93, a231 + v_accvgpr_read_b32 v94, a232 + v_accvgpr_read_b32 v95, a233 + v_accvgpr_read_b32 v96, a234 + v_accvgpr_read_b32 v97, a235 + v_accvgpr_read_b32 v98, a236 + v_accvgpr_read_b32 v99, a237 + v_accvgpr_read_b32 v100, a238 + v_accvgpr_read_b32 v101, a239 + v_accvgpr_read_b32 v102, a240 + v_accvgpr_read_b32 v103, a241 + v_accvgpr_read_b32 v104, a242 + v_accvgpr_read_b32 v105, a243 + v_accvgpr_read_b32 v106, a244 + v_accvgpr_read_b32 v107, a245 + v_accvgpr_read_b32 v108, a246 + v_accvgpr_read_b32 v109, a247 + v_accvgpr_read_b32 v110, a248 + v_accvgpr_read_b32 v111, a249 + v_accvgpr_read_b32 v112, a250 + v_accvgpr_read_b32 v113, a251 + v_accvgpr_read_b32 v114, a252 + v_accvgpr_read_b32 v115, a253 + v_accvgpr_read_b32 v116, a254 + v_accvgpr_read_b32 v117, a255 + v_accvgpr_read_b32 v118, a32 + v_accvgpr_read_b32 v119, a33 + v_accvgpr_read_b32 v120, a34 + v_accvgpr_read_b32 v121, a35 + v_accvgpr_read_b32 v122, a36 + v_accvgpr_read_b32 v123, a37 + v_accvgpr_read_b32 v124, a38 + v_accvgpr_read_b32 v125, a39 + v_accvgpr_read_b32 v126, a40 + v_accvgpr_read_b32 v127, a41 + v_accvgpr_read_b32 v128, a42 + v_accvgpr_read_b32 v129, a43 + v_accvgpr_read_b32 v130, a44 + v_accvgpr_read_b32 v131, a45 + v_accvgpr_read_b32 v132, a46 + v_accvgpr_read_b32 v133, a47 + v_accvgpr_read_b32 v134, a48 + v_accvgpr_read_b32 v135, a49 + v_accvgpr_read_b32 v136, a50 + v_accvgpr_read_b32 v137, a51 + v_accvgpr_read_b32 v138, a52 + v_accvgpr_read_b32 v139, a53 + v_accvgpr_read_b32 v140, a54 + v_accvgpr_read_b32 v141, a55 + v_accvgpr_read_b32 v142, a56 + v_accvgpr_read_b32 v143, a57 + v_accvgpr_read_b32 v144, a58 + v_accvgpr_read_b32 v145, a59 + v_accvgpr_read_b32 v146, a60 + v_accvgpr_read_b32 v147, a61 + v_accvgpr_read_b32 v148, a62 + v_accvgpr_read_b32 v149, a63 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[16:17], v53 + ds_read_b64 v[18:19], v52 offset:16384 + v_accvgpr_mov_b32 a255, a79 + v_accvgpr_mov_b32 a254, a78 + v_accvgpr_mov_b32 a253, a77 + v_accvgpr_mov_b32 a252, a76 + v_accvgpr_mov_b32 a251, a75 + v_accvgpr_mov_b32 a250, a74 + v_accvgpr_mov_b32 a249, a73 + v_accvgpr_mov_b32 a248, a72 + v_accvgpr_mov_b32 a247, a71 + v_accvgpr_mov_b32 a246, a70 + v_accvgpr_mov_b32 a245, a69 + v_accvgpr_mov_b32 a244, a68 + v_accvgpr_mov_b32 a243, a67 + v_accvgpr_mov_b32 a242, a66 + v_accvgpr_mov_b32 a241, a65 + v_accvgpr_mov_b32 a240, a64 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[16:17], v[18:19], a[240:255] + ds_read_b64 v[20:21], v49 offset:16384 + v_accvgpr_mov_b32 a239, a95 + v_accvgpr_mov_b32 a238, a94 + v_accvgpr_mov_b32 a237, a93 + v_accvgpr_mov_b32 a236, a92 + v_accvgpr_mov_b32 a235, a91 + v_accvgpr_mov_b32 a234, a90 + v_accvgpr_mov_b32 a233, a89 + v_accvgpr_mov_b32 a232, a88 + v_accvgpr_mov_b32 a231, a87 + v_accvgpr_mov_b32 a230, a86 + v_accvgpr_mov_b32 a229, a85 + v_accvgpr_mov_b32 a228, a84 + v_accvgpr_mov_b32 a227, a83 + v_accvgpr_mov_b32 a226, a82 + v_accvgpr_mov_b32 a225, a81 + v_accvgpr_mov_b32 a224, a80 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[16:17], v[20:21], a[224:239] + ds_read_b64 v[52:53], v50 offset:16384 + v_accvgpr_mov_b32 a223, a111 + v_accvgpr_mov_b32 a222, a110 + v_accvgpr_mov_b32 a221, a109 + v_accvgpr_mov_b32 a220, a108 + v_accvgpr_mov_b32 a219, a107 + v_accvgpr_mov_b32 a218, a106 + v_accvgpr_mov_b32 a217, a105 + v_accvgpr_mov_b32 a216, a104 + v_accvgpr_mov_b32 a215, a103 + v_accvgpr_mov_b32 a214, a102 + v_accvgpr_mov_b32 a213, a101 + v_accvgpr_mov_b32 a212, a100 + v_accvgpr_mov_b32 a211, a99 + v_accvgpr_mov_b32 a210, a98 + v_accvgpr_mov_b32 a209, a97 + v_accvgpr_mov_b32 a208, a96 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[16:17], v[52:53], a[208:223] + ds_read_b64 v[50:51], v51 offset:16384 + v_accvgpr_mov_b32 a207, a127 + v_accvgpr_mov_b32 a206, a126 + v_accvgpr_mov_b32 a205, a125 + v_accvgpr_mov_b32 a204, a124 + v_accvgpr_mov_b32 a203, a123 + v_accvgpr_mov_b32 a202, a122 + v_accvgpr_mov_b32 a201, a121 + v_accvgpr_mov_b32 a200, a120 + v_accvgpr_mov_b32 a199, a119 + v_accvgpr_mov_b32 a198, a118 + v_accvgpr_mov_b32 a197, a117 + v_accvgpr_mov_b32 a196, a116 + v_accvgpr_mov_b32 a195, a115 + v_accvgpr_mov_b32 a194, a114 + v_accvgpr_mov_b32 a193, a113 + v_accvgpr_mov_b32 a192, a112 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[16:17], v[50:51], a[192:207] + ds_read_b64 v[16:17], v46 + v_accvgpr_mov_b32 a175, a143 + v_accvgpr_mov_b32 a174, a142 + v_accvgpr_mov_b32 a173, a141 + v_accvgpr_mov_b32 a172, a140 + v_accvgpr_mov_b32 a171, a139 + v_accvgpr_mov_b32 a170, a138 + v_accvgpr_mov_b32 a169, a137 + v_accvgpr_mov_b32 a168, a136 + v_accvgpr_mov_b32 a167, a135 + v_accvgpr_mov_b32 a166, a134 + v_accvgpr_mov_b32 a165, a133 + v_accvgpr_mov_b32 a164, a132 + v_accvgpr_mov_b32 a163, a131 + v_accvgpr_mov_b32 a162, a130 + v_accvgpr_mov_b32 a161, a129 + v_accvgpr_mov_b32 a160, a128 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[16:17], v[18:19], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[16:17], v[20:21], a[144:159] + v_accvgpr_write_b32 a143, v15 + v_accvgpr_write_b32 a142, v14 + v_accvgpr_write_b32 a141, v13 + v_accvgpr_write_b32 a140, v12 + v_accvgpr_write_b32 a139, v11 + v_accvgpr_write_b32 a138, v10 + v_accvgpr_write_b32 a137, v9 + v_accvgpr_write_b32 a136, v8 + v_accvgpr_write_b32 a135, v7 + v_accvgpr_write_b32 a134, v6 + v_accvgpr_write_b32 a133, v5 + v_accvgpr_write_b32 a132, v4 + v_accvgpr_write_b32 a131, v3 + v_accvgpr_write_b32 a130, v2 + v_accvgpr_write_b32 a129, v1 + v_accvgpr_write_b32 a128, v0 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[16:17], v[52:53], a[128:143] + v_accvgpr_mov_b32 a112, a176 + v_accvgpr_mov_b32 a113, a177 + v_accvgpr_mov_b32 a114, a178 + v_accvgpr_mov_b32 a115, a179 + v_accvgpr_mov_b32 a116, a180 + v_accvgpr_mov_b32 a117, a181 + v_accvgpr_mov_b32 a118, a182 + v_accvgpr_mov_b32 a119, a183 + v_accvgpr_mov_b32 a120, a184 + v_accvgpr_mov_b32 a121, a185 + v_accvgpr_mov_b32 a122, a186 + v_accvgpr_mov_b32 a123, a187 + v_accvgpr_mov_b32 a124, a188 + v_accvgpr_mov_b32 a125, a189 + v_accvgpr_mov_b32 a126, a190 + v_accvgpr_mov_b32 a127, a191 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[16:17], v[50:51], a[112:127] + ds_read_b64 v[0:1], v47 + v_accvgpr_write_b32 a111, v69 + v_accvgpr_write_b32 a110, v68 + v_accvgpr_write_b32 a109, v67 + v_accvgpr_write_b32 a108, v66 + v_accvgpr_write_b32 a107, v65 + v_accvgpr_write_b32 a106, v64 + v_accvgpr_write_b32 a105, v63 + v_accvgpr_write_b32 a104, v62 + v_accvgpr_write_b32 a103, v61 + v_accvgpr_write_b32 a102, v60 + v_accvgpr_write_b32 a101, v59 + v_accvgpr_write_b32 a100, v58 + v_accvgpr_write_b32 a99, v57 + v_accvgpr_write_b32 a98, v56 + v_accvgpr_write_b32 a97, v55 + v_accvgpr_write_b32 a96, v54 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[18:19], a[96:111] + v_accvgpr_write_b32 a95, v85 + v_accvgpr_write_b32 a94, v84 + v_accvgpr_write_b32 a93, v83 + v_accvgpr_write_b32 a92, v82 + v_accvgpr_write_b32 a91, v81 + v_accvgpr_write_b32 a90, v80 + v_accvgpr_write_b32 a89, v79 + v_accvgpr_write_b32 a88, v78 + v_accvgpr_write_b32 a87, v77 + v_accvgpr_write_b32 a86, v76 + v_accvgpr_write_b32 a85, v75 + v_accvgpr_write_b32 a84, v74 + v_accvgpr_write_b32 a83, v73 + v_accvgpr_write_b32 a82, v72 + v_accvgpr_write_b32 a81, v71 + v_accvgpr_write_b32 a80, v70 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[20:21], a[80:95] + v_accvgpr_write_b32 a64, v86 + v_accvgpr_write_b32 a65, v87 + v_accvgpr_write_b32 a66, v88 + v_accvgpr_write_b32 a67, v89 + v_accvgpr_write_b32 a68, v90 + v_accvgpr_write_b32 a69, v91 + v_accvgpr_write_b32 a70, v92 + v_accvgpr_write_b32 a71, v93 + v_accvgpr_write_b32 a72, v94 + v_accvgpr_write_b32 a73, v95 + v_accvgpr_write_b32 a74, v96 + v_accvgpr_write_b32 a75, v97 + v_accvgpr_write_b32 a76, v98 + v_accvgpr_write_b32 a77, v99 + v_accvgpr_write_b32 a78, v100 + v_accvgpr_write_b32 a79, v101 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[52:53], a[64:79] + v_accvgpr_write_b32 a48, v102 + v_accvgpr_write_b32 a49, v103 + v_accvgpr_write_b32 a50, v104 + v_accvgpr_write_b32 a51, v105 + v_accvgpr_write_b32 a52, v106 + v_accvgpr_write_b32 a53, v107 + v_accvgpr_write_b32 a54, v108 + v_accvgpr_write_b32 a55, v109 + v_accvgpr_write_b32 a56, v110 + v_accvgpr_write_b32 a57, v111 + v_accvgpr_write_b32 a58, v112 + v_accvgpr_write_b32 a59, v113 + v_accvgpr_write_b32 a60, v114 + v_accvgpr_write_b32 a61, v115 + v_accvgpr_write_b32 a62, v116 + v_accvgpr_write_b32 a63, v117 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[50:51], a[48:63] + ds_read_b64 v[0:1], v48 + v_accvgpr_mov_b32 a47, a31 + v_accvgpr_mov_b32 a46, a30 + v_accvgpr_mov_b32 a45, a29 + v_accvgpr_mov_b32 a44, a28 + v_accvgpr_mov_b32 a43, a27 + v_accvgpr_mov_b32 a42, a26 + v_accvgpr_mov_b32 a41, a25 + v_accvgpr_mov_b32 a40, a24 + v_accvgpr_mov_b32 a39, a23 + v_accvgpr_mov_b32 a38, a22 + v_accvgpr_mov_b32 a37, a21 + v_accvgpr_mov_b32 a36, a20 + v_accvgpr_mov_b32 a35, a19 + v_accvgpr_mov_b32 a34, a18 + v_accvgpr_mov_b32 a33, a17 + v_accvgpr_mov_b32 a32, a16 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[18:19], a[32:47] + v_accvgpr_write_b32 a16, v118 + v_accvgpr_write_b32 a17, v119 + v_accvgpr_write_b32 a18, v120 + v_accvgpr_write_b32 a19, v121 + v_accvgpr_write_b32 a20, v122 + v_accvgpr_write_b32 a21, v123 + v_accvgpr_write_b32 a22, v124 + v_accvgpr_write_b32 a23, v125 + v_accvgpr_write_b32 a24, v126 + v_accvgpr_write_b32 a25, v127 + v_accvgpr_write_b32 a26, v128 + v_accvgpr_write_b32 a27, v129 + v_accvgpr_write_b32 a28, v130 + v_accvgpr_write_b32 a29, v131 + v_accvgpr_write_b32 a30, v132 + v_accvgpr_write_b32 a31, v133 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[20:21], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[52:53], a[0:15] + v_accvgpr_write_b32 a191, v149 + v_accvgpr_write_b32 a190, v148 + v_accvgpr_write_b32 a189, v147 + v_accvgpr_write_b32 a188, v146 + v_accvgpr_write_b32 a187, v145 + v_accvgpr_write_b32 a186, v144 + v_accvgpr_write_b32 a185, v143 + v_accvgpr_write_b32 a184, v142 + v_accvgpr_write_b32 a183, v141 + v_accvgpr_write_b32 a182, v140 + v_accvgpr_write_b32 a181, v139 + v_accvgpr_write_b32 a180, v138 + v_accvgpr_write_b32 a179, v137 + v_accvgpr_write_b32 a178, v136 + v_accvgpr_write_b32 a177, v135 + v_accvgpr_write_b32 a176, v134 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[50:51], a[176:191] + ds_read_b64 v[0:1], v29 + ds_read_b64 v[2:3], v42 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v43 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v44 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v45 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v30 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v36 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v39 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b64 v[0:1], v26 + ds_read_b64 v[2:3], v37 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v38 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v40 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v41 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v27 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v28 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v31 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[8:9], a[176:191] + ds_read_b64 v[0:1], v25 + ds_read_b64 v[2:3], v34 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[2:3], a[240:255] + ds_read_b64 v[4:5], v32 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[4:5], a[224:239] + ds_read_b64 v[6:7], v33 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[8:9], v35 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[8:9], a[192:207] + ds_read_b64 v[0:1], v22 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[2:3], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[4:5], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[6:7], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[8:9], a[112:127] + ds_read_b64 v[0:1], v23 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[2:3], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[4:5], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[8:9], a[48:63] + ds_read_b64 v[0:1], v24 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[2:3], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[4:5], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[6:7], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[8:9], a[176:191] +.LBB29_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEES2_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEES1J_SG_SG_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1L_T0_EE5valueEbE4typeELPb0EEEDaRKS1M_RKT1_RKS1N_RKT2_iPv + v_accvgpr_read_b32 v143, a240 + v_accvgpr_read_b32 v142, a241 + v_accvgpr_read_b32 v141, a242 + v_accvgpr_read_b32 v140, a243 + v_accvgpr_read_b32 v139, a244 + v_accvgpr_read_b32 v18, a245 + v_accvgpr_read_b32 v0, a246 + v_accvgpr_read_b32 v138, a247 + v_accvgpr_read_b32 v137, a248 + v_accvgpr_read_b32 v136, a249 + v_accvgpr_read_b32 v135, a250 + v_accvgpr_read_b32 v134, a251 + v_accvgpr_read_b32 v133, a252 + v_accvgpr_read_b32 v132, a253 + v_accvgpr_read_b32 v131, a254 + v_accvgpr_read_b32 v130, a255 + v_accvgpr_read_b32 v107, a224 + v_accvgpr_read_b32 v106, a225 + v_accvgpr_read_b32 v105, a226 + v_accvgpr_read_b32 v104, a227 + v_accvgpr_read_b32 v103, a228 + v_accvgpr_read_b32 v102, a229 + v_accvgpr_read_b32 v101, a230 + v_accvgpr_read_b32 v100, a231 + v_accvgpr_read_b32 v99, a232 + v_accvgpr_read_b32 v98, a233 + v_accvgpr_read_b32 v97, a234 + v_accvgpr_read_b32 v96, a235 + v_accvgpr_read_b32 v95, a236 + v_accvgpr_read_b32 v94, a237 + v_accvgpr_read_b32 v93, a238 + v_accvgpr_read_b32 v92, a239 + v_accvgpr_read_b32 v91, a208 + v_accvgpr_read_b32 v90, a209 + v_accvgpr_read_b32 v89, a210 + v_accvgpr_read_b32 v88, a211 + v_accvgpr_read_b32 v87, a212 + v_accvgpr_read_b32 v86, a213 + v_accvgpr_read_b32 v85, a214 + v_accvgpr_read_b32 v84, a215 + v_accvgpr_read_b32 v83, a216 + v_accvgpr_read_b32 v82, a217 + v_accvgpr_read_b32 v81, a218 + v_accvgpr_read_b32 v80, a219 + v_accvgpr_read_b32 v79, a220 + v_accvgpr_read_b32 v78, a221 + v_accvgpr_read_b32 v77, a222 + v_accvgpr_read_b32 v76, a223 + v_accvgpr_read_b32 v75, a192 + v_accvgpr_read_b32 v74, a193 + v_accvgpr_read_b32 v73, a194 + v_accvgpr_read_b32 v72, a195 + v_accvgpr_read_b32 v71, a196 + v_accvgpr_read_b32 v70, a197 + v_accvgpr_read_b32 v69, a198 + v_accvgpr_read_b32 v68, a199 + v_accvgpr_read_b32 v67, a200 + v_accvgpr_read_b32 v66, a201 + v_accvgpr_read_b32 v65, a202 + v_accvgpr_read_b32 v64, a203 + v_accvgpr_read_b32 v63, a204 + v_accvgpr_read_b32 v62, a205 + v_accvgpr_read_b32 v61, a206 + v_accvgpr_read_b32 v20, a207 + v_accvgpr_read_b32 v224, a160 + v_accvgpr_read_b32 v223, a161 + v_accvgpr_read_b32 v222, a162 + v_accvgpr_read_b32 v221, a163 + v_accvgpr_read_b32 v220, a164 + v_accvgpr_read_b32 v219, a165 + v_accvgpr_read_b32 v218, a166 + v_accvgpr_read_b32 v217, a167 + v_accvgpr_read_b32 v216, a168 + v_accvgpr_read_b32 v215, a169 + v_accvgpr_read_b32 v214, a170 + v_accvgpr_read_b32 v213, a171 + v_accvgpr_read_b32 v212, a172 + v_accvgpr_read_b32 v211, a173 + v_accvgpr_read_b32 v210, a174 + v_accvgpr_read_b32 v209, a175 + v_accvgpr_read_b32 v176, a144 + v_accvgpr_read_b32 v175, a145 + v_accvgpr_read_b32 v174, a146 + v_accvgpr_read_b32 v173, a147 + v_accvgpr_read_b32 v172, a148 + v_accvgpr_read_b32 v171, a149 + v_accvgpr_read_b32 v170, a150 + v_accvgpr_read_b32 v169, a151 + v_accvgpr_read_b32 v168, a152 + v_accvgpr_read_b32 v167, a153 + v_accvgpr_read_b32 v166, a154 + v_accvgpr_read_b32 v165, a155 + v_accvgpr_read_b32 v164, a156 + v_accvgpr_read_b32 v163, a157 + v_accvgpr_read_b32 v162, a158 + v_accvgpr_read_b32 v161, a159 + v_accvgpr_read_b32 v160, a128 + v_accvgpr_read_b32 v159, a129 + v_accvgpr_read_b32 v158, a130 + v_accvgpr_read_b32 v157, a131 + v_accvgpr_read_b32 v156, a132 + v_accvgpr_read_b32 v155, a133 + v_accvgpr_read_b32 v154, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v152, a136 + v_accvgpr_read_b32 v151, a137 + v_accvgpr_read_b32 v150, a138 + v_accvgpr_read_b32 v149, a139 + v_accvgpr_read_b32 v148, a140 + v_accvgpr_read_b32 v147, a141 + v_accvgpr_read_b32 v145, a142 + v_accvgpr_read_b32 v144, a143 + v_accvgpr_read_b32 v146, a112 + v_accvgpr_read_b32 v129, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v127, a115 + v_accvgpr_read_b32 v126, a116 + v_accvgpr_read_b32 v125, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v123, a119 + v_accvgpr_read_b32 v122, a120 + v_accvgpr_read_b32 v121, a121 + v_accvgpr_read_b32 v120, a122 + v_accvgpr_read_b32 v119, a123 + v_accvgpr_read_b32 v118, a124 + v_accvgpr_read_b32 v117, a125 + v_accvgpr_read_b32 v116, a126 + v_accvgpr_read_b32 v115, a127 + v_accvgpr_mov_b32 a119, a96 + v_accvgpr_mov_b32 a118, a97 + v_accvgpr_mov_b32 a117, a98 + v_accvgpr_mov_b32 a116, a99 + v_accvgpr_mov_b32 a115, a100 + v_accvgpr_mov_b32 a114, a101 + v_accvgpr_mov_b32 a113, a102 + v_accvgpr_mov_b32 a112, a103 + v_accvgpr_mov_b32 a103, a104 + v_accvgpr_mov_b32 a102, a105 + v_accvgpr_mov_b32 a101, a106 + v_accvgpr_mov_b32 a100, a107 + v_accvgpr_mov_b32 a99, a108 + v_accvgpr_mov_b32 a98, a109 + v_accvgpr_mov_b32 a97, a110 + v_accvgpr_mov_b32 a96, a111 + v_accvgpr_read_b32 v60, a80 + v_accvgpr_read_b32 v59, a81 + v_accvgpr_read_b32 v58, a82 + v_accvgpr_read_b32 v57, a83 + v_accvgpr_read_b32 v56, a84 + v_accvgpr_read_b32 v55, a85 + v_accvgpr_read_b32 v54, a86 + v_accvgpr_read_b32 v53, a87 + v_accvgpr_read_b32 v52, a88 + v_accvgpr_read_b32 v51, a89 + v_accvgpr_read_b32 v50, a90 + v_accvgpr_read_b32 v25, a91 + v_accvgpr_read_b32 v24, a92 + v_accvgpr_read_b32 v23, a93 + v_accvgpr_read_b32 v22, a94 + v_accvgpr_read_b32 v21, a95 + v_accvgpr_read_b32 v114, a64 + v_accvgpr_read_b32 v113, a65 + v_accvgpr_read_b32 v112, a66 + v_accvgpr_read_b32 v111, a67 + v_accvgpr_read_b32 v110, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v108, a70 + v_accvgpr_read_b32 v1, a71 + v_accvgpr_read_b32 v49, a72 + v_accvgpr_read_b32 v48, a73 + v_accvgpr_read_b32 v47, a74 + v_accvgpr_read_b32 v46, a75 + v_accvgpr_read_b32 v45, a76 + v_accvgpr_read_b32 v44, a77 + v_accvgpr_read_b32 v43, a78 + v_accvgpr_read_b32 v42, a79 + v_accvgpr_read_b32 v208, a48 + v_accvgpr_read_b32 v207, a49 + v_accvgpr_read_b32 v206, a50 + v_accvgpr_read_b32 v205, a51 + v_accvgpr_read_b32 v204, a52 + v_accvgpr_read_b32 v203, a53 + v_accvgpr_read_b32 v202, a54 + v_accvgpr_read_b32 v201, a55 + v_accvgpr_read_b32 v200, a56 + v_accvgpr_read_b32 v199, a57 + v_accvgpr_read_b32 v198, a58 + v_accvgpr_read_b32 v197, a59 + v_accvgpr_read_b32 v196, a60 + v_accvgpr_read_b32 v195, a61 + v_accvgpr_read_b32 v194, a62 + v_accvgpr_read_b32 v193, a63 + v_accvgpr_mov_b32 a55, a32 + v_accvgpr_mov_b32 a54, a33 + v_accvgpr_mov_b32 a53, a34 + v_accvgpr_mov_b32 a52, a35 + v_accvgpr_mov_b32 a51, a36 + v_accvgpr_mov_b32 a50, a37 + v_accvgpr_mov_b32 a49, a38 + v_accvgpr_mov_b32 a48, a39 + v_accvgpr_mov_b32 a39, a40 + v_accvgpr_mov_b32 a38, a41 + v_accvgpr_mov_b32 a37, a42 + v_accvgpr_mov_b32 a36, a43 + v_accvgpr_mov_b32 a35, a44 + v_accvgpr_mov_b32 a34, a45 + v_accvgpr_mov_b32 a33, a46 + v_accvgpr_mov_b32 a32, a47 + v_accvgpr_read_b32 v41, a16 + v_accvgpr_read_b32 v40, a17 + v_accvgpr_read_b32 v39, a18 + v_accvgpr_read_b32 v38, a19 + v_accvgpr_read_b32 v37, a20 + v_accvgpr_read_b32 v36, a21 + v_accvgpr_read_b32 v35, a22 + v_accvgpr_read_b32 v34, a23 + v_accvgpr_read_b32 v33, a24 + v_accvgpr_read_b32 v32, a25 + v_accvgpr_read_b32 v31, a26 + v_accvgpr_read_b32 v30, a27 + v_accvgpr_read_b32 v29, a28 + v_accvgpr_read_b32 v28, a29 + v_accvgpr_read_b32 v27, a30 + v_accvgpr_read_b32 v26, a31 + v_accvgpr_read_b32 v192, a0 + v_accvgpr_read_b32 v191, a1 + v_accvgpr_read_b32 v190, a2 + v_accvgpr_read_b32 v189, a3 + v_accvgpr_read_b32 v188, a4 + v_accvgpr_read_b32 v187, a5 + v_accvgpr_read_b32 v186, a6 + v_accvgpr_read_b32 v185, a7 + v_accvgpr_read_b32 v184, a8 + v_accvgpr_read_b32 v183, a9 + v_accvgpr_read_b32 v182, a10 + v_accvgpr_read_b32 v181, a11 + v_accvgpr_read_b32 v180, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v178, a14 + v_accvgpr_read_b32 v177, a15 + v_accvgpr_read_b32 v2, a176 + v_accvgpr_read_b32 v3, a177 + v_accvgpr_read_b32 v4, a178 + v_accvgpr_read_b32 v5, a179 + v_accvgpr_read_b32 v6, a180 + v_accvgpr_read_b32 v7, a181 + v_accvgpr_read_b32 v8, a182 + v_accvgpr_read_b32 v9, a183 + v_accvgpr_read_b32 v10, a184 + v_accvgpr_read_b32 v11, a185 + v_accvgpr_read_b32 v12, a186 + v_accvgpr_read_b32 v13, a187 + v_accvgpr_read_b32 v14, a188 + v_accvgpr_read_b32 v15, a189 + v_accvgpr_read_b32 v16, a190 + v_accvgpr_read_b32 v17, a191 + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s5, s4 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v228, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v19, 3, v225 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v132, v130 + v_cvt_f16_f32_e32 v133, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v209, v92 + v_cvt_f16_f32_e32 v210, v176 + v_cvt_f16_f32_e32 v211, v175 + v_cvt_f16_f32_e32 v212, v174 + v_cvt_f16_f32_e32 v213, v173 + v_cvt_f16_f32_e32 v214, v172 + v_cvt_f16_f32_e32 v215, v171 + v_cvt_f16_f32_e32 v216, v170 + v_cvt_f16_f32_e32 v217, v169 + v_cvt_f16_f32_e32 v218, v168 + v_cvt_f16_f32_e32 v219, v167 + v_cvt_f16_f32_e32 v220, v166 + v_cvt_f16_f32_e32 v221, v165 + v_cvt_f16_f32_e32 v222, v164 + v_cvt_f16_f32_e32 v223, v163 + v_cvt_f16_f32_e32 v224, v162 + v_cvt_f16_f32_e32 v130, v161 + v_cvt_f16_f32_e32 v162, v91 + v_cvt_f16_f32_e32 v163, v90 + v_cvt_f16_f32_e32 v164, v89 + v_cvt_f16_f32_e32 v165, v88 + v_cvt_f16_f32_e32 v166, v87 + v_cvt_f16_f32_e32 v167, v86 + v_cvt_f16_f32_e32 v168, v85 + v_cvt_f16_f32_e32 v169, v84 + v_cvt_f16_f32_e32 v170, v83 + v_cvt_f16_f32_e32 v171, v82 + v_cvt_f16_f32_e32 v172, v81 + v_cvt_f16_f32_e32 v173, v80 + v_cvt_f16_f32_e32 v174, v79 + v_cvt_f16_f32_e32 v175, v78 + v_cvt_f16_f32_e32 v176, v77 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v77, v160 + v_cvt_f16_f32_e32 v78, v159 + v_cvt_f16_f32_e32 v79, v158 + v_cvt_f16_f32_e32 v80, v157 + v_cvt_f16_f32_e32 v81, v156 + v_cvt_f16_f32_e32 v82, v155 + v_cvt_f16_f32_e32 v83, v154 + v_cvt_f16_f32_e32 v84, v153 + v_cvt_f16_f32_e32 v85, v152 + v_cvt_f16_f32_e32 v86, v151 + v_cvt_f16_f32_e32 v87, v150 + v_cvt_f16_f32_e32 v88, v149 + v_cvt_f16_f32_e32 v89, v148 + v_cvt_f16_f32_e32 v90, v147 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v129 + v_cvt_f16_f32_e32 v148, v128 + v_cvt_f16_f32_e32 v149, v127 + v_cvt_f16_f32_e32 v150, v126 + v_cvt_f16_f32_e32 v151, v125 + v_cvt_f16_f32_e32 v152, v124 + v_cvt_f16_f32_e32 v153, v123 + v_cvt_f16_f32_e32 v154, v122 + v_cvt_f16_f32_e32 v155, v121 + v_cvt_f16_f32_e32 v156, v120 + v_cvt_f16_f32_e32 v157, v119 + v_cvt_f16_f32_e32 v158, v118 + v_cvt_f16_f32_e32 v159, v117 + v_cvt_f16_f32_e32 v160, v116 + v_cvt_f16_f32_e32 v161, v115 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v207, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v20, v205 + v_accvgpr_write_b32 a0, v20 + v_cvt_f16_f32_e32 v20, v204 + v_accvgpr_write_b32 a1, v20 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v115, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v20, 1, v226 + v_cvt_f16_f32_e32 v114, v114 + v_cvt_f16_f32_e32 v193, v113 + v_cvt_f16_f32_e32 v194, v112 + v_cvt_f16_f32_e32 v195, v111 + v_cvt_f16_f32_e32 v196, v110 + v_cvt_f16_f32_e32 v197, v109 + v_cvt_f16_f32_e32 v198, v108 + v_cvt_f16_f32_e32 v199, v1 + v_cvt_f16_f32_e32 v200, v49 + v_cvt_f16_f32_e32 v201, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v108, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v228 + v_lshlrev_b32_e32 v21, 3, v225 + v_lshrrev_b32_e32 v1, 1, v225 + s_cbranch_scc1 .LBB29_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB29_14 +.LBB29_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEESB_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB29_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_or_b32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v132 offset:3456 + ds_write_b16 v23, v133 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s20, v25 + v_or_b32_e32 v25, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v190, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v107 + ds_write_b16 v23, v106 offset:128 + ds_write_b16 v23, v105 offset:256 + ds_write_b16 v23, v104 offset:384 + ds_write_b16 v23, v103 offset:1024 + ds_write_b16 v23, v102 offset:1152 + ds_write_b16 v23, v101 offset:1280 + ds_write_b16 v23, v100 offset:1408 + ds_write_b16 v23, v99 offset:2048 + ds_write_b16 v23, v98 offset:2176 + ds_write_b16 v23, v97 offset:2304 + ds_write_b16 v23, v96 offset:2432 + ds_write_b16 v23, v95 offset:3072 + ds_write_b16 v23, v94 offset:3200 + ds_write_b16 v23, v93 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v190, v31, v41 + v_lshlrev_b32_e32 v191, 1, v190 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v190 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v76 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v190, 0x80, v25 + v_add_u32_e32 v191, v31, v190 + v_lshlrev_b32_e32 v192, 1, v191 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v191 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v75 + ds_write_b16 v23, v74 offset:128 + ds_write_b16 v23, v73 offset:256 + ds_write_b16 v23, v72 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v191, 0xc0, v25 + v_add_u32_e32 v31, v31, v191 + v_lshlrev_b32_e32 v192, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v207 offset:128 + ds_write_b16 v23, v206 offset:256 + ds_write_b16 v23, a0 offset:384 + ds_write_b16 v23, a1 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v61 offset:2304 + ds_write_b16 v23, v62 offset:2432 + ds_write_b16 v23, v63 offset:3072 + ds_write_b16 v23, v64 offset:3200 + ds_write_b16 v23, v65 offset:3328 + ds_write_b16 v23, v66 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v115 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v191 + v_lshlrev_b32_e32 v191, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v191, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v191, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v191, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v191, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v114 + ds_write_b16 v23, v193 offset:128 + ds_write_b16 v23, v194 offset:256 + ds_write_b16 v23, v195 offset:384 + ds_write_b16 v23, v196 offset:1024 + ds_write_b16 v23, v197 offset:1152 + ds_write_b16 v23, v198 offset:1280 + ds_write_b16 v23, v199 offset:1408 + ds_write_b16 v23, v200 offset:2048 + ds_write_b16 v23, v201 offset:2176 + ds_write_b16 v23, v47 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v43 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v108 offset:8320 + ds_write_b16 v23, v109 offset:8448 + ds_write_b16 v23, v110 offset:8576 + ds_write_b16 v23, v111 offset:9216 + ds_write_b16 v23, v112 offset:9344 + ds_write_b16 v23, v113 offset:9472 + ds_write_b16 v23, v185 offset:9600 + ds_write_b16 v23, v184 offset:10240 + ds_write_b16 v23, v183 offset:10368 + ds_write_b16 v23, v182 offset:10496 + ds_write_b16 v23, v181 offset:10624 + ds_write_b16 v23, v180 offset:11264 + ds_write_b16 v23, v179 offset:11392 + ds_write_b16 v23, v178 offset:11520 + ds_write_b16 v23, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v190 + v_lshlrev_b32_e32 v190, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v190, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v190, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v190, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v190, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v3 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a119 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a118 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a117 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a116 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a115 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a114 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a113 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a112 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a103 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a102 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a101 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a100 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a99 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a98 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a97 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a96 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a39 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a38 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a37 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a36 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a35 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a34 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a33 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[202:205], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v202, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v203, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB29_12 +.LBB29_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_or_b32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v132 offset:3456 + ds_write_b16 v31, v133 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v41, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v131, v0, v41 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v186, 1, v131 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v186, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v131 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v107 + ds_write_b16 v31, v106 offset:128 + ds_write_b16 v31, v105 offset:256 + ds_write_b16 v31, v104 offset:384 + ds_write_b16 v31, v103 offset:1024 + ds_write_b16 v31, v102 offset:1152 + ds_write_b16 v31, v101 offset:1280 + ds_write_b16 v31, v100 offset:1408 + ds_write_b16 v31, v99 offset:2048 + ds_write_b16 v31, v98 offset:2176 + ds_write_b16 v31, v97 offset:2304 + ds_write_b16 v31, v96 offset:2432 + ds_write_b16 v31, v95 offset:3072 + ds_write_b16 v31, v94 offset:3200 + ds_write_b16 v31, v93 offset:3328 + ds_write_b16 v31, v209 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v41 + v_add_u32_e32 v94, v0, v93 + v_lshlrev_b32_e32 v95, 1, v94 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v95, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v94 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v76 offset:3456 + ds_write_b16 v31, v77 offset:8192 + ds_write_b16 v31, v78 offset:8320 + ds_write_b16 v31, v79 offset:8448 + ds_write_b16 v31, v80 offset:8576 + ds_write_b16 v31, v81 offset:9216 + ds_write_b16 v31, v82 offset:9344 + ds_write_b16 v31, v83 offset:9472 + ds_write_b16 v31, v84 offset:9600 + ds_write_b16 v31, v85 offset:10240 + ds_write_b16 v31, v86 offset:10368 + ds_write_b16 v31, v87 offset:10496 + ds_write_b16 v31, v88 offset:10624 + ds_write_b16 v31, v89 offset:11264 + ds_write_b16 v31, v90 offset:11392 + ds_write_b16 v31, v91 offset:11520 + ds_write_b16 v31, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v76, 0x80, v41 + v_add_u32_e32 v77, v0, v76 + v_lshlrev_b32_e32 v78, 1, v77 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v77 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v75 + ds_write_b16 v31, v74 offset:128 + ds_write_b16 v31, v73 offset:256 + ds_write_b16 v31, v72 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v74, 0xc0, v41 + v_add_u32_e32 v0, v0, v74 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v208 + ds_write_b16 v31, v207 offset:128 + ds_write_b16 v31, v206 offset:256 + ds_write_b16 v31, a0 offset:384 + ds_write_b16 v31, a1 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v61 offset:2304 + ds_write_b16 v31, v62 offset:2432 + ds_write_b16 v31, v63 offset:3072 + ds_write_b16 v31, v64 offset:3200 + ds_write_b16 v31, v65 offset:3328 + ds_write_b16 v31, v66 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v115 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v74 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v114 + ds_write_b16 v31, v193 offset:128 + ds_write_b16 v31, v194 offset:256 + ds_write_b16 v31, v195 offset:384 + ds_write_b16 v31, v196 offset:1024 + ds_write_b16 v31, v197 offset:1152 + ds_write_b16 v31, v198 offset:1280 + ds_write_b16 v31, v199 offset:1408 + ds_write_b16 v31, v200 offset:2048 + ds_write_b16 v31, v201 offset:2176 + ds_write_b16 v31, v47 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v44 offset:3200 + ds_write_b16 v31, v43 offset:3328 + ds_write_b16 v31, v48 offset:3456 + ds_write_b16 v31, v49 offset:8192 + ds_write_b16 v31, v108 offset:8320 + ds_write_b16 v31, v109 offset:8448 + ds_write_b16 v31, v110 offset:8576 + ds_write_b16 v31, v111 offset:9216 + ds_write_b16 v31, v112 offset:9344 + ds_write_b16 v31, v113 offset:9472 + ds_write_b16 v31, v185 offset:9600 + ds_write_b16 v31, v184 offset:10240 + ds_write_b16 v31, v183 offset:10368 + ds_write_b16 v31, v182 offset:10496 + ds_write_b16 v31, v181 offset:10624 + ds_write_b16 v31, v180 offset:11264 + ds_write_b16 v31, v179 offset:11392 + ds_write_b16 v31, v178 offset:11520 + ds_write_b16 v31, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v0, v61, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v3 offset:128 + ds_write_b16 v31, v4 offset:256 + ds_write_b16 v31, v5 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a119 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a118 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a117 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a116 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a115 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a114 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a113 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a112 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a103 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a102 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a101 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a100 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a99 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a98 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a97 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a96 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a55 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a54 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a53 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a52 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a51 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a50 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a49 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a48 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a39 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a38 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a37 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a36 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a35 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a34 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a33 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a32 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v61, v41 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end29: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end29-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 26 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEESC_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 24024 +; TotalNumSgprs: 32 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB30_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB30_5 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v4, v6, s7 + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v2, v0, s2 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[4:5], s[8:9], 0, v[4:5] + v_mov_b32_e32 v1, 0 +.LBB30_3: ; =>This Inner Loop Header: Depth=1 + global_load_ubyte v7, v[4:5], off + global_load_ubyte v8, v[2:3], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_bf8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_bf8_sdwa v8, v8 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_lshl_add_u64 v[4:5], v[4:5], 0, 1 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v7, v8 + s_cbranch_scc0 .LBB30_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB30_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB30_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 9 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end30: + .size _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end30-_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 9 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 448 +; TotalNumSgprs: 20 +; NumVgprs: 9 +; NumAgprs: 0 +; TotalNumVgprs: 9 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 9 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v227, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v0 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s8, s8, s15 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s10, s2, 1 + s_mul_i32 s2, s22, s3 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v0 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v0, -1, 0 + v_mbcnt_hi_u32_b32 v225, -1, v0 + v_and_b32_e32 v35, 31, v225 + v_lshlrev_b32_e32 v228, 3, v225 + v_lshrrev_b32_e32 v9, 5, v225 + v_lshlrev_b32_e32 v11, 4, v225 + v_lshrrev_b32_e32 v10, 2, v225 + v_and_b32_e32 v8, 15, v225 + s_cbranch_scc0 .LBB31_2 +; %bb.1: + v_readfirstlane_b32 s15, v227 + v_and_b32_e32 v2, 48, v11 + v_and_b32_e32 v0, 0x7c, v225 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v13, s11, v0 + v_add_u32_e32 v0, s20, v13 + v_mad_u64_u32 v[0:1], s[24:25], v0, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[48:51], v0, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v0 + buffer_load_dwordx4 v[52:55], v1, s[8:11], 0 offen + v_and_or_b32 v0, v228, 8, v9 + v_lshlrev_b32_e32 v26, 3, v9 + v_add_u32_e32 v3, s7, v1 + buffer_load_dwordx4 v[56:59], v3, s[8:11], 0 offen + v_and_b32_e32 v5, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v1, 12, v9 + s_lshr_b32 s19, s15, 2 + s_lshr_b32 s23, s15, 1 + v_lshl_or_b32 v22, v8, 7, v1 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v27, 3, v2 + s_and_b32 s24, s19, 0x3fffffe0 + s_and_b32 s19, s19, 0x3ffffff0 + v_and_or_b32 v2, s23, 32, v35 + v_or_b32_e32 v28, 1, v27 + v_or_b32_e32 v1, s24, v35 + v_add_u32_e32 v29, s19, v5 + v_lshrrev_b32_e32 v12, 4, v2 + v_ashrrev_i32_e32 v30, 1, v13 + v_ashrrev_i32_e32 v14, 31, v13 + v_lshlrev_b32_e32 v31, 6, v13 + v_or_b32_e32 v32, 1, v13 + v_sub_u32_e32 v33, v27, v28 + v_lshrrev_b32_e32 v34, 31, v13 + v_add_u32_e32 v2, s7, v3 + buffer_load_dwordx4 v[60:63], v2, s[8:11], 0 offen + v_lshrrev_b32_e32 v36, 1, v1 + v_bfe_u32 v37, v1, 1, 4 + v_mad_u64_u32 v[6:7], s[24:25], v29, s22, v[4:5] + v_xor_b32_e32 v38, v12, v8 + buffer_load_dwordx4 v[2:5], v6, s[12:15], 0 offen + v_lshrrev_b32_e32 v7, 28, v14 + v_add_u32_e32 v39, v32, v34 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[14:17], v6, s[12:15], 0 offen + v_or_b32_e32 v40, 1, v30 + v_xor_b32_e32 v41, v37, v0 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[18:21], v6, s[12:15], 0 offen + v_lshlrev_b32_e32 v42, 7, v36 + v_lshl_or_b32 v43, v38, 2, v22 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[22:25], v6, s[12:15], 0 offen + v_add_u32_e32 v6, v30, v7 + v_ashrrev_i32_e32 v44, 1, v39 + v_and_b32_e32 v45, 0x1ffffffe, v39 + v_ashrrev_i32_e32 v39, 31, v39 + v_and_b32_e32 v6, -16, v6 + v_sub_u32_e32 v46, v44, v30 + v_sub_u32_e32 v32, v32, v45 + v_lshrrev_b32_e32 v39, 28, v39 + v_sub_u32_e32 v45, v40, v44 + v_sub_u32_e32 v6, v30, v6 + v_lshl_or_b32 v30, v32, 3, v28 + v_add_u32_e32 v32, v44, v39 + v_xor_b32_e32 v39, v6, v27 + v_xor_b32_e32 v6, v6, v28 + v_add_u32_e32 v47, v30, v33 + v_and_b32_e32 v32, -16, v32 + v_lshl_add_u32 v39, v39, 3, v31 + v_lshl_add_u32 v31, v6, 3, v31 + v_sub_u32_e32 v32, v44, v32 + v_xor_b32_e32 v44, v47, v32 + v_lshl_add_u32 v46, v46, 7, v31 + v_xor_b32_e32 v30, v30, v32 + v_sub_u32_e32 v32, v44, v6 + v_sub_u32_e32 v6, v30, v6 + v_lshl_add_u32 v32, v32, 3, v46 + v_lshl_add_u32 v6, v6, 3, v46 + s_waitcnt vmcnt(7) + ds_write_b64 v39, v[48:49] + ds_write_b64 v31, v[50:51] + s_waitcnt vmcnt(6) + ds_write_b64 v32, v[52:53] + ds_write_b64 v6, v[54:55] + v_add_u32_e32 v7, v40, v7 + v_and_b32_e32 v7, -16, v7 + v_sub_u32_e32 v7, v40, v7 + v_xor_b32_e32 v27, v7, v27 + v_sub_u32_e32 v30, v27, v30 + v_lshlrev_b32_e32 v30, 3, v30 + v_lshlrev_b32_e32 v31, 7, v45 + v_add3_u32 v6, v30, v31, v6 + s_waitcnt vmcnt(5) + ds_write_b64 v6, v[56:57] + v_xor_b32_e32 v7, v7, v28 + v_sub_u32_e32 v27, v7, v27 + v_lshl_add_u32 v6, v27, 3, v6 + ds_write_b64 v6, v[58:59] + v_or_b32_e32 v13, 3, v13 + v_add_u32_e32 v27, v13, v34 + v_ashrrev_i32_e32 v30, 1, v27 + v_sub_u32_e32 v31, v30, v40 + v_and_b32_e32 v32, 0x1ffffffe, v27 + v_sub_u32_e32 v13, v13, v32 + v_lshl_or_b32 v13, v13, 3, v28 + v_add_u32_e32 v28, v13, v33 + v_ashrrev_i32_e32 v27, 31, v27 + v_lshrrev_b32_e32 v27, 28, v27 + v_add_u32_e32 v27, v30, v27 + v_and_b32_e32 v27, -16, v27 + v_sub_u32_e32 v27, v30, v27 + v_xor_b32_e32 v28, v28, v27 + v_sub_u32_e32 v7, v28, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v30, 7, v31 + v_add3_u32 v6, v7, v30, v6 + s_waitcnt vmcnt(4) + ds_write_b64 v6, v[60:61] + v_xor_b32_e32 v7, v13, v27 + v_sub_u32_e32 v7, v7, v28 + v_lshl_add_u32 v6, v7, 3, v6 + ds_write_b64 v6, v[62:63] + s_mov_b32 s11, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v2, v2, v2, s11 + v_perm_b32 v3, v3, v3, s11 + v_perm_b32 v4, v4, v4, s11 + v_perm_b32 v5, v5, v5, s11 + s_waitcnt vmcnt(2) + v_perm_b32 v6, v14, v14, s11 + v_perm_b32 v7, v15, v15, s11 + v_perm_b32 v13, v16, v16, s11 + v_perm_b32 v14, v17, v17, s11 + s_waitcnt vmcnt(1) + v_perm_b32 v15, v18, v18, s11 + v_perm_b32 v16, v19, v19, s11 + v_perm_b32 v17, v20, v20, s11 + v_perm_b32 v18, v21, v21, s11 + s_waitcnt vmcnt(0) + v_perm_b32 v19, v22, v22, s11 + v_perm_b32 v20, v23, v23, s11 + v_perm_b32 v21, v24, v24, s11 + v_perm_b32 v22, v25, v25, s11 + s_mov_b32 s11, 0x5010400 + v_perm_b32 v23, v6, v2, s11 + v_perm_b32 v24, v19, v15, s11 + s_mov_b32 s15, 0x5040100 + v_perm_b32 v25, v24, v23, s15 + s_mov_b32 s19, 0x7060302 + v_perm_b32 v23, v24, v23, s19 + s_mov_b32 s23, 0x7030602 + v_perm_b32 v2, v6, v2, s23 + v_perm_b32 v6, v19, v15, s23 + v_perm_b32 v15, v6, v2, s15 + v_perm_b32 v2, v6, v2, s19 + v_perm_b32 v6, v7, v3, s11 + v_perm_b32 v19, v20, v16, s11 + v_perm_b32 v24, v19, v6, s15 + v_perm_b32 v6, v19, v6, s19 + v_perm_b32 v3, v7, v3, s23 + v_perm_b32 v7, v20, v16, s23 + v_perm_b32 v16, v7, v3, s15 + v_perm_b32 v3, v7, v3, s19 + v_perm_b32 v7, v13, v4, s11 + v_perm_b32 v19, v21, v17, s11 + v_perm_b32 v20, v19, v7, s15 + v_perm_b32 v7, v19, v7, s19 + v_perm_b32 v4, v13, v4, s23 + v_perm_b32 v13, v21, v17, s23 + v_perm_b32 v17, v13, v4, s15 + v_perm_b32 v4, v13, v4, s19 + v_perm_b32 v13, v14, v5, s11 + v_perm_b32 v19, v22, v18, s11 + v_perm_b32 v21, v19, v13, s15 + v_perm_b32 v13, v19, v13, s19 + v_perm_b32 v5, v14, v5, s23 + v_perm_b32 v14, v22, v18, s23 + v_perm_b32 v18, v14, v5, s15 + v_perm_b32 v5, v14, v5, s19 + v_lshrrev_b32_e32 v14, 1, v29 + v_and_b32_e32 v14, 16, v14 + v_xor_b32_e32 v19, v14, v35 + v_lshlrev_b32_e32 v22, 9, v29 + v_and_b32_e32 v22, 0x3000, v22 + v_lshlrev_b32_e32 v27, 6, v29 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v27, 0xfffff800, v27 + v_add_u32_e32 v22, v22, v27 + v_lshl_or_b32 v22, v19, 2, v22 + ds_write_b32 v22, v25 offset:16384 + v_or_b32_e32 v25, 1, v14 + v_xor_b32_e32 v25, v25, v35 + v_sub_u32_e32 v19, v25, v19 + v_lshl_add_u32 v19, v19, 2, v22 + v_or_b32_e32 v22, 2, v14 + v_xor_b32_e32 v22, v22, v35 + v_sub_u32_e32 v25, v22, v25 + v_lshl_add_u32 v25, v25, 2, v19 + ds_write_b32 v19, v23 offset:16512 + v_or_b32_e32 v19, 3, v14 + v_xor_b32_e32 v19, v19, v35 + v_sub_u32_e32 v22, v19, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v25, s18, v22 + ds_write_b32 v25, v15 offset:16640 + v_or_b32_e32 v15, 4, v14 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v19, v15, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v19, v22, s18, v19 + ds_write_b32 v22, v2 offset:16640 + v_or_b32_e32 v2, 5, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v15, v2, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v19, s18, v15 + ds_write_b32 v19, v24 offset:16640 + v_or_b32_e32 v19, 6, v14 + v_xor_b32_e32 v19, v19, v35 + v_sub_u32_e32 v2, v19, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v15, s18, v2 + ds_write_b32 v15, v6 offset:16640 + v_or_b32_e32 v6, 7, v14 + v_xor_b32_e32 v6, v6, v35 + v_sub_u32_e32 v15, v6, v19 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v2, s18, v15 + ds_write_b32 v2, v16 offset:16640 + v_or_b32_e32 v2, 8, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v15, s18, v6 + ds_write_b32 v15, v3 offset:16640 + v_or_b32_e32 v3, 9, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v20 offset:16640 + v_or_b32_e32 v6, 10, v14 + v_xor_b32_e32 v6, v6, v35 + v_sub_u32_e32 v3, v6, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v7 offset:16640 + v_or_b32_e32 v2, 11, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v3, s18, v6 + ds_write_b32 v3, v17 offset:16640 + v_or_b32_e32 v3, 12, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v4 offset:16640 + v_or_b32_e32 v4, 13, v14 + v_xor_b32_e32 v4, v4, v35 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v21 offset:16640 + v_or_b32_e32 v2, 14, v14 + v_xor_b32_e32 v2, v2, v35 + v_sub_u32_e32 v4, v2, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v4, v3, s18, v4 + ds_write_b32 v3, v13 offset:16640 + v_or_b32_e32 v3, 15, v14 + v_xor_b32_e32 v3, v3, v35 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v2, v2, 2, v4 + ds_write_b32 v4, v18 offset:16640 + ds_write_b32 v2, v5 offset:16768 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v2, v41, 3, v42 + v_add_u32_e32 v15, 2, v0 + v_xor_b32_e32 v3, v37, v15 + v_lshl_or_b32 v3, v3, 3, v42 + v_or_b32_e32 v24, 4, v0 + v_xor_b32_e32 v4, v37, v24 + v_lshl_or_b32 v16, v4, 3, v42 + v_add_u32_e32 v13, 6, v0 + v_xor_b32_e32 v20, v37, v13 + v_lshl_add_u32 v14, v20, 3, v42 + v_add_u32_e32 v4, 64, v1 + v_lshrrev_b32_e32 v21, 1, v4 + v_sub_u32_e32 v17, v21, v36 + v_bfe_u32 v22, v4, 1, 4 + v_xor_b32_e32 v4, v22, v0 + v_sub_u32_e32 v18, v4, v20 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[4:5], v3 + ds_read_b64 v[2:3], v16 + ds_read_b32 v74, v43 offset:16384 + v_lshrrev_b16_e32 v16, 3, v26 + v_or_b32_e32 v19, 16, v12 + v_xor_b32_e32 v23, v19, v8 + v_sub_u32_e32 v25, v23, v38 + v_lshlrev_b32_e32 v25, 2, v25 + v_sub_u32_e32 v27, v16, v9 + v_lshlrev_b32_e32 v27, 12, v27 + v_add3_u32 v25, v43, v27, v25 + v_add_u32_e32 v27, 16, v26 + v_lshrrev_b32_e32 v28, 5, v27 + v_lshrrev_b16_e32 v27, 3, v27 + v_and_b32_e32 v27, 3, v27 + v_sub_u16_e32 v29, v27, v16 + v_bfe_i32 v29, v29, 0, 16 + v_lshlrev_b32_e32 v30, 4, v28 + v_or_b32_e32 v31, v30, v8 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v31, v12, v31 + v_sub_u32_e32 v23, v31, v23 + v_lshlrev_b32_e32 v32, 11, v28 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshl_or_b32 v29, v29, 12, v32 + v_add3_u32 v23, v23, v29, v25 + v_add_u32_e32 v32, 20, v26 + v_lshrrev_b32_e32 v33, 5, v32 + v_sub_u32_e32 v28, v33, v28 + v_lshrrev_b16_e32 v32, 3, v32 + v_and_b32_e32 v32, 3, v32 + v_sub_u16_e32 v27, v32, v27 + v_bfe_i32 v27, v27, 0, 16 + v_lshlrev_b32_e32 v34, 4, v33 + v_or_b32_e32 v36, v34, v8 + v_and_b32_e32 v36, 31, v36 + v_xor_b32_e32 v36, v19, v36 + v_sub_u32_e32 v31, v36, v31 + v_lshlrev_b32_e32 v28, 11, v28 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_add_u32 v27, v27, 12, v28 + v_add3_u32 v28, v31, v27, v23 + v_sub_u16_e32 v31, v16, v32 + v_bfe_i32 v31, v31, 0, 16 + v_or_b32_e32 v32, 16, v8 + v_xor_b32_e32 v37, v12, v32 + v_sub_u32_e32 v36, v37, v36 + v_lshlrev_b32_e32 v33, 11, v33 + v_xor_b32_e32 v33, 0x800, v33 + v_lshlrev_b32_e32 v36, 2, v36 + v_lshl_add_u32 v31, v31, 12, v33 + v_add3_u32 v33, v36, v31, v28 + v_xor_b32_e32 v32, v19, v32 + v_sub_u32_e32 v36, v32, v37 + v_lshl_add_u32 v36, v36, 2, v33 + v_add_u32_e32 v37, 48, v26 + v_lshrrev_b32_e32 v38, 5, v37 + v_lshlrev_b32_e32 v39, 11, v38 + v_lshrrev_b16_e32 v37, 3, v37 + v_and_b32_e32 v37, 3, v37 + v_sub_u16_e32 v40, v37, v16 + v_lshlrev_b32_e32 v41, 4, v38 + v_or_b32_e32 v42, v41, v8 + v_and_b32_e32 v42, 31, v42 + v_xor_b32_e32 v42, v12, v42 + v_sub_u32_e32 v32, v42, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_mov_b32_e32 v43, 12 + v_lshlrev_b32_sdwa v40, v43, sext(v40) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v39, v39, v40, s11 + v_add3_u32 v32, v32, v39, v36 + v_add_u32_e32 v26, 52, v26 + v_lshrrev_b32_e32 v40, 5, v26 + v_sub_u32_e32 v38, v40, v38 + v_lshrrev_b16_e32 v26, 3, v26 + v_and_b32_e32 v26, 3, v26 + v_sub_u16_e32 v37, v26, v37 + v_bfe_i32 v37, v37, 0, 16 + v_lshlrev_b32_e32 v44, 4, v40 + v_or_b32_e32 v45, v44, v8 + v_and_b32_e32 v46, 31, v45 + v_xor_b32_e32 v19, v19, v46 + v_sub_u32_e32 v42, v19, v42 + v_lshlrev_b32_e32 v38, 11, v38 + v_lshlrev_b32_e32 v42, 2, v42 + v_lshl_add_u32 v37, v37, 12, v38 + v_add3_u32 v38, v42, v37, v32 + ds_read_b32 v75, v25 offset:16384 + ds_read_b32 v76, v23 offset:16384 + ds_read_b32 v77, v28 offset:16384 + ds_read_b32 v78, v33 offset:16384 + ds_read_b32 v79, v36 offset:16384 + ds_read_b32 v80, v32 offset:16384 + ds_read_b32 v81, v38 offset:16384 + v_or_b32_e32 v23, 4, v12 + v_sub_u16_e32 v16, v16, v26 + v_sub_u32_e32 v25, v45, v44 + v_ashrrev_i32_e32 v26, 31, v25 + v_lshrrev_b32_e32 v26, 27, v26 + v_add_u32_e32 v26, v25, v26 + v_and_b32_e32 v26, 0xffffffe0, v26 + v_sub_u32_e32 v26, v25, v26 + v_xor_b32_e32 v28, v23, v26 + v_sub_u32_e32 v19, v28, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshlrev_b32_sdwa v16, v43, sext(v16) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v32, 11, v40 + v_sub_u32_e32 v16, v16, v32 + v_add3_u32 v19, v19, v16, v38 + v_or_b32_e32 v32, 20, v12 + v_xor_b32_e32 v33, v32, v26 + v_sub_u32_e32 v28, v33, v28 + v_lshl_add_u32 v28, v28, 2, v19 + ds_read_b32 v82, v19 offset:16384 + ds_read_b32 v83, v28 offset:16384 + v_add_u32_e32 v19, v25, v30 + v_ashrrev_i32_e32 v30, 31, v19 + v_lshrrev_b32_e32 v30, 27, v30 + v_add_u32_e32 v30, v19, v30 + v_and_b32_e32 v30, 0xffffffe0, v30 + v_sub_u32_e32 v30, v19, v30 + v_xor_b32_e32 v19, v23, v30 + v_sub_u32_e32 v33, v19, v33 + v_lshl_add_u32 v33, v33, 2, v29 + v_add_u32_e32 v28, v33, v28 + v_add_u32_e32 v33, v25, v34 + v_ashrrev_i32_e32 v34, 31, v33 + v_lshrrev_b32_e32 v34, 27, v34 + v_add_u32_e32 v34, v33, v34 + v_and_b32_e32 v34, 0xffffffe0, v34 + v_sub_u32_e32 v33, v33, v34 + v_xor_b32_e32 v34, v32, v33 + v_sub_u32_e32 v19, v34, v19 + v_lshl_add_u32 v36, v19, 2, v27 + v_add_u32_e32 v38, v28, v36 + v_add_u32_e32 v19, 16, v25 + v_ashrrev_i32_e32 v40, 31, v19 + v_lshrrev_b32_e32 v40, 27, v40 + v_add_u32_e32 v40, v19, v40 + v_and_b32_e32 v40, 0xffffffe0, v40 + v_sub_u32_e32 v40, v19, v40 + v_xor_b32_e32 v19, v23, v40 + v_sub_u32_e32 v34, v19, v34 + v_lshl_add_u32 v34, v34, 2, v31 + v_add_u32_e32 v42, v38, v34 + v_xor_b32_e32 v43, v32, v40 + v_sub_u32_e32 v19, v43, v19 + v_lshlrev_b32_e32 v44, 2, v19 + v_add_u32_e32 v45, v42, v44 + v_add_u32_e32 v19, v25, v41 + v_ashrrev_i32_e32 v25, 31, v19 + v_lshrrev_b32_e32 v25, 27, v25 + v_add_u32_e32 v25, v19, v25 + v_and_b32_e32 v25, 0xffffffe0, v25 + v_sub_u32_e32 v41, v19, v25 + v_xor_b32_e32 v19, v23, v41 + v_sub_u32_e32 v23, v19, v43 + v_lshl_add_u32 v43, v23, 2, v39 + v_add_u32_e32 v47, v45, v43 + v_xor_b32_e32 v23, v32, v46 + v_sub_u32_e32 v19, v23, v19 + v_lshl_add_u32 v32, v19, 2, v37 + v_add_u32_e32 v48, v47, v32 + v_or_b32_e32 v19, 8, v12 + v_xor_b32_e32 v25, v19, v26 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v49, v23, 2, v16 + v_add_u32_e32 v23, v48, v49 + ds_read_b32 v84, v23 offset:16384 + v_or_b32_e32 v50, 24, v12 + v_xor_b32_e32 v51, v50, v26 + v_sub_u32_e32 v25, v51, v25 + v_lshlrev_b32_e32 v52, 2, v25 + v_add_u32_e32 v23, v23, v52 + ds_read_b32 v85, v23 offset:16384 + v_xor_b32_e32 v25, v19, v30 + v_sub_u32_e32 v51, v25, v51 + v_lshl_add_u32 v51, v51, 2, v29 + v_add_u32_e32 v53, v23, v51 + v_xor_b32_e32 v23, v50, v33 + v_sub_u32_e32 v25, v23, v25 + v_lshl_add_u32 v54, v25, 2, v27 + v_add_u32_e32 v55, v53, v54 + v_xor_b32_e32 v25, v19, v40 + v_sub_u32_e32 v23, v25, v23 + v_lshl_add_u32 v56, v23, 2, v31 + v_add_u32_e32 v57, v55, v56 + v_xor_b32_e32 v23, v50, v40 + v_sub_u32_e32 v25, v23, v25 + v_lshlrev_b32_e32 v58, 2, v25 + v_add_u32_e32 v59, v57, v58 + v_xor_b32_e32 v19, v19, v41 + v_sub_u32_e32 v23, v19, v23 + v_lshl_add_u32 v60, v23, 2, v39 + s_waitcnt lgkmcnt(10) + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[6:7], v[74:75], 0 + v_add_u32_e32 v61, v59, v60 + v_xor_b32_e32 v23, v50, v46 + v_sub_u32_e32 v19, v23, v19 + v_lshl_add_u32 v50, v19, 2, v37 + v_add_u32_e32 v62, v61, v50 + v_or_b32_e32 v63, 12, v12 + v_xor_b32_e32 v19, v63, v26 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[6:7], v[82:83], 0 + v_sub_u32_e32 v23, v19, v23 + v_lshl_add_u32 v64, v23, 2, v16 + v_add_u32_e32 v16, v62, v64 + ds_read_b32 v86, v16 offset:16384 + v_or_b32_e32 v12, 28, v12 + v_xor_b32_e32 v26, v12, v26 + v_sub_u32_e32 v19, v26, v19 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[6:7], v[84:85], 0 + v_lshlrev_b32_e32 v65, 2, v19 + v_add_u32_e32 v66, v16, v65 + ds_read_b32 v87, v66 offset:16384 + v_lshl_add_u32 v23, v17, 7, v14 + v_lshl_add_u32 v16, v18, 3, v23 + ds_read_b64 v[16:17], v16 + v_xor_b32_e32 v18, v22, v15 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[6:7], v[86:87], 0 + v_sub_u32_e32 v6, v18, v20 + v_lshl_add_u32 v6, v6, 3, v23 + v_xor_b32_e32 v7, v22, v24 + v_sub_u32_e32 v7, v7, v20 + v_lshl_add_u32 v18, v7, 3, v23 + ds_read_b64 v[6:7], v6 + ds_read_b64 v[18:19], v18 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[16:17], v[74:75], 0 + v_xor_b32_e32 v22, v22, v13 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[16:17], v[82:83], 0 + v_sub_u32_e32 v20, v22, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_add_u32_e32 v67, v20, v23 + v_add_u32_e32 v20, 0x80, v1 + v_lshrrev_b32_e32 v25, 1, v20 + v_sub_u32_e32 v21, v25, v21 + v_bfe_u32 v68, v20, 1, 4 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[16:17], v[84:85], 0 + v_xor_b32_e32 v69, v68, v0 + v_sub_u32_e32 v20, v69, v22 + v_lshlrev_b32_e32 v21, 7, v21 + v_lshl_add_u32 v70, v20, 3, v21 + v_add_u32_e32 v71, v67, v70 + ds_read_b64 v[20:21], v71 + v_xor_b32_e32 v22, v68, v15 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[16:17], v[86:87], 0 + v_sub_u32_e32 v16, v22, v69 + v_lshl_add_u32 v16, v16, 3, v71 + v_xor_b32_e32 v17, v68, v24 + v_sub_u32_e32 v17, v17, v69 + v_lshl_add_u32 v22, v17, 3, v71 + ds_read_b64 v[16:17], v16 + ds_read_b64 v[22:23], v22 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[20:21], v[74:75], 0 + v_xor_b32_e32 v68, v68, v13 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[20:21], v[82:83], 0 + v_sub_u32_e32 v69, v68, v69 + v_lshlrev_b32_e32 v69, 3, v69 + v_add3_u32 v70, v70, v67, v69 + v_add_u32_e32 v1, 0xc0, v1 + v_lshrrev_b32_e32 v72, 1, v1 + v_sub_u32_e32 v25, v72, v25 + v_bfe_u32 v72, v1, 1, 4 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[20:21], v[84:85], 0 + v_xor_b32_e32 v73, v72, v0 + v_sub_u32_e32 v0, v73, v68 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v1, 7, v25 + v_add3_u32 v68, v0, v1, v70 + ds_read_b64 v[0:1], v68 + v_xor_b32_e32 v15, v72, v15 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[20:21], v[86:87], 0 + v_sub_u32_e32 v15, v15, v73 + v_lshl_add_u32 v15, v15, 3, v68 + v_xor_b32_e32 v20, v72, v24 + v_sub_u32_e32 v20, v20, v73 + v_lshl_add_u32 v24, v20, 3, v68 + ds_read_b64 v[20:21], v15 + ds_read_b64 v[24:25], v24 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[74:75], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[82:83], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[84:85], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[86:87], 0 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[4:5], v[76:77], a[0:15] + ds_read_b32 v74, v28 offset:16384 + ds_read_b32 v75, v38 offset:16384 + ds_read_b32 v82, v53 offset:16384 + ds_read_b32 v83, v55 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[4:5], v[74:75], a[240:255] + v_xor_b32_e32 v0, v63, v30 + v_sub_u32_e32 v1, v0, v26 + v_lshl_add_u32 v15, v1, 2, v29 + v_add_u32_e32 v1, v66, v15 + ds_read_b32 v84, v1 offset:16384 + v_xor_b32_e32 v26, v12, v33 + v_sub_u32_e32 v0, v26, v0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[4:5], v[82:83], a[224:239] + v_lshl_add_u32 v27, v0, 2, v27 + v_add_u32_e32 v0, v1, v27 + ds_read_b32 v85, v0 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[4:5], v[84:85], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[6:7], v[76:77], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[6:7], v[74:75], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[6:7], v[82:83], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[6:7], v[84:85], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[16:17], v[76:77], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[16:17], v[74:75], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[16:17], v[82:83], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[16:17], v[84:85], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[20:21], v[76:77], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[20:21], v[74:75], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[20:21], v[82:83], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[20:21], v[84:85], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[2:3], v[78:79], a[0:15] + ds_read_b32 v16, v42 offset:16384 + ds_read_b32 v17, v45 offset:16384 + ds_read_b32 v20, v57 offset:16384 + ds_read_b32 v21, v59 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[2:3], v[16:17], a[240:255] + v_xor_b32_e32 v1, v63, v40 + v_sub_u32_e32 v4, v1, v26 + v_lshl_add_u32 v4, v4, 2, v31 + v_add_u32_e32 v0, v0, v4 + ds_read_b32 v30, v0 offset:16384 + v_xor_b32_e32 v5, v12, v40 + v_sub_u32_e32 v1, v5, v1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[2:3], v[20:21], a[224:239] + v_lshlrev_b32_e32 v6, 2, v1 + v_add_u32_e32 v7, v0, v6 + ds_read_b32 v31, v7 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[2:3], v[30:31], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[18:19], v[78:79], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[18:19], v[16:17], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[18:19], v[20:21], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[18:19], v[30:31], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[22:23], v[78:79], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[22:23], v[16:17], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[22:23], v[20:21], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[22:23], v[30:31], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[24:25], v[78:79], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[24:25], v[16:17], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[24:25], v[20:21], a[16:31] + ds_read_b64 v[0:1], v14 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[24:25], v[30:31], a[192:207] + v_add3_u32 v2, v36, v28, v34 + v_add3_u32 v2, v44, v2, v43 + ds_read_b32 v16, v47 offset:16384 + ds_read_b32 v17, v48 offset:16384 + v_add3_u32 v2, v32, v2, v49 + v_add3_u32 v2, v2, v52, v51 + v_add3_u32 v2, v54, v2, v56 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[0:1], v[80:81], a[0:15] + v_add3_u32 v2, v58, v2, v60 + ds_read_b32 v18, v61 offset:16384 + ds_read_b32 v19, v62 offset:16384 + v_add3_u32 v2, v50, v2, v64 + v_add3_u32 v2, v2, v65, v15 + v_add3_u32 v2, v27, v2, v4 + v_xor_b32_e32 v3, v63, v41 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[0:1], v[16:17], a[240:255] + v_sub_u32_e32 v4, v3, v5 + v_lshl_add_u32 v4, v4, 2, v39 + v_add3_u32 v2, v6, v2, v4 + v_add_u32_e32 v4, v7, v4 + ds_read_b32 v6, v4 offset:16384 + v_xor_b32_e32 v4, v12, v46 + v_sub_u32_e32 v3, v4, v3 + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[0:1], v[18:19], a[224:239] + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v2, v3, v37, v2 + ds_read_b32 v7, v2 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[0:1], v[6:7], a[208:223] + ds_read_b64 v[0:1], v67 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[0:1], v[80:81], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[0:1], v[16:17], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[0:1], v[18:19], a[144:159] + v_add_u32_e32 v2, v71, v69 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[0:1], v[6:7], a[128:143] + ds_read_b64 v[0:1], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[0:1], v[80:81], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[0:1], v[16:17], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[0:1], v[18:19], a[80:95] + v_xor_b32_e32 v2, v72, v13 + v_sub_u32_e32 v2, v2, v73 + v_lshl_add_u32 v2, v2, 3, v68 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[0:1], v[6:7], a[64:79] + ds_read_b64 v[0:1], v2 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[0:1], v[80:81], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[0:1], v[16:17], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[0:1], v[18:19], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[0:1], v[6:7], a[192:207] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB31_3 + s_branch .LBB31_10 +.LBB31_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr79 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr159 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr223 + ; implicit-def: $agpr239 + ; implicit-def: $agpr255 + ; implicit-def: $agpr15 + ; implicit-def: $agpr192_agpr193_agpr194_agpr195_agpr196_agpr197_agpr198_agpr199_agpr200_agpr201_agpr202_agpr203_agpr204_agpr205_agpr206_agpr207 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB31_3: + v_readfirstlane_b32 s15, v227 + v_and_b32_e32 v0, 48, v11 + s_and_b32 s11, s15, 0xffffffc0 + v_and_b32_e32 v83, 0x7c, v225 + v_add_u32_e32 v1, s11, v83 + v_add_u32_e32 v2, s20, v1 + v_mad_u64_u32 v[20:21], s[18:19], v2, s7, v[0:1] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[44:47], v20, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v20 + buffer_load_dwordx4 v[52:55], v2, s[8:11], 0 offen + v_and_or_b32 v3, v228, 8, v9 + v_lshlrev_b32_e32 v11, 3, v9 + v_add_u32_e32 v6, s7, v2 + buffer_load_dwordx4 v[56:59], v6, s[8:11], 0 offen + v_and_b32_e32 v84, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v2, 12, v9 + s_lshr_b32 s18, s15, 2 + s_lshr_b32 s19, s15, 1 + v_lshl_or_b32 v16, v8, 7, v2 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v85, 3, v0 + s_and_b32 s23, s18, 0x3fffffe0 + s_and_b32 s18, s18, 0x3ffffff0 + v_and_or_b32 v0, s19, 32, v35 + v_or_b32_e32 v86, 1, v85 + v_or_b32_e32 v5, s23, v35 + v_add_u32_e32 v17, s18, v84 + v_lshrrev_b32_e32 v2, 4, v0 + v_ashrrev_i32_e32 v21, 1, v1 + v_ashrrev_i32_e32 v0, 31, v1 + v_lshlrev_b32_e32 v34, 6, v1 + v_or_b32_e32 v36, 1, v1 + v_sub_u32_e32 v87, v85, v86 + v_lshrrev_b32_e32 v37, 31, v1 + v_add_u32_e32 v6, s7, v6 + buffer_load_dwordx4 v[60:63], v6, s[8:11], 0 offen + v_lshrrev_b32_e32 v6, 1, v5 + v_bfe_u32 v7, v5, 1, 4 + v_mad_u64_u32 v[18:19], s[18:19], v17, s22, v[4:5] + v_xor_b32_e32 v4, v2, v8 + buffer_load_dwordx4 v[12:15], v18, s[12:15], 0 offen + v_lshrrev_b32_e32 v19, 28, v0 + v_add_u32_e32 v38, v36, v37 + v_add_u32_e32 v10, s22, v18 + buffer_load_dwordx4 v[22:25], v10, s[12:15], 0 offen + v_or_b32_e32 v39, 1, v21 + v_xor_b32_e32 v0, v7, v3 + v_add_u32_e32 v30, s22, v10 + buffer_load_dwordx4 v[26:29], v30, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 7, v6 + v_lshl_or_b32 v50, v4, 2, v16 + v_add_u32_e32 v16, s22, v30 + buffer_load_dwordx4 v[30:33], v16, s[12:15], 0 offen + v_add_u32_e32 v16, v21, v19 + v_ashrrev_i32_e32 v40, 1, v38 + v_and_b32_e32 v41, 0x1ffffffe, v38 + v_ashrrev_i32_e32 v38, 31, v38 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v42, v40, v21 + v_sub_u32_e32 v36, v36, v41 + v_lshrrev_b32_e32 v38, 28, v38 + v_sub_u32_e32 v41, v39, v40 + v_sub_u32_e32 v16, v21, v16 + v_lshl_or_b32 v21, v36, 3, v86 + v_add_u32_e32 v36, v40, v38 + v_xor_b32_e32 v38, v16, v85 + v_xor_b32_e32 v16, v16, v86 + v_add_u32_e32 v43, v21, v87 + v_and_b32_e32 v36, -16, v36 + v_lshl_add_u32 v38, v38, 3, v34 + v_lshl_add_u32 v34, v16, 3, v34 + v_sub_u32_e32 v36, v40, v36 + v_xor_b32_e32 v40, v43, v36 + v_lshl_add_u32 v42, v42, 7, v34 + v_xor_b32_e32 v21, v21, v36 + v_sub_u32_e32 v36, v40, v16 + v_sub_u32_e32 v16, v21, v16 + v_lshl_add_u32 v36, v36, 3, v42 + v_lshl_add_u32 v16, v16, 3, v42 + s_waitcnt vmcnt(7) + ds_write_b64 v38, v[44:45] + ds_write_b64 v34, v[46:47] + s_waitcnt vmcnt(6) + ds_write_b64 v36, v[52:53] + ds_write_b64 v16, v[54:55] + v_add_u32_e32 v19, v39, v19 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v19, v39, v19 + v_xor_b32_e32 v34, v19, v85 + v_sub_u32_e32 v21, v34, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_lshlrev_b32_e32 v36, 7, v41 + v_add3_u32 v16, v21, v36, v16 + s_waitcnt vmcnt(5) + ds_write_b64 v16, v[56:57] + v_xor_b32_e32 v19, v19, v86 + v_sub_u32_e32 v21, v19, v34 + v_lshl_add_u32 v16, v21, 3, v16 + ds_write_b64 v16, v[58:59] + v_or_b32_e32 v1, 3, v1 + v_add_u32_e32 v21, v1, v37 + v_ashrrev_i32_e32 v34, 1, v21 + v_sub_u32_e32 v36, v34, v39 + v_and_b32_e32 v37, 0x1ffffffe, v21 + v_sub_u32_e32 v1, v1, v37 + v_lshl_or_b32 v1, v1, 3, v86 + v_add_u32_e32 v37, v1, v87 + v_ashrrev_i32_e32 v21, 31, v21 + v_lshrrev_b32_e32 v21, 28, v21 + v_add_u32_e32 v21, v34, v21 + v_and_b32_e32 v21, -16, v21 + v_sub_u32_e32 v21, v34, v21 + v_xor_b32_e32 v34, v37, v21 + v_sub_u32_e32 v19, v34, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshlrev_b32_e32 v36, 7, v36 + v_add3_u32 v16, v19, v36, v16 + s_waitcnt vmcnt(4) + ds_write_b64 v16, v[60:61] + v_xor_b32_e32 v1, v1, v21 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v1, v1, 3, v16 + ds_write_b64 v1, v[62:63] + s_mov_b32 s18, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v1, v12, v12, s18 + v_perm_b32 v12, v13, v13, s18 + v_perm_b32 v13, v14, v14, s18 + v_perm_b32 v14, v15, v15, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v15, v22, v22, s18 + v_perm_b32 v16, v23, v23, s18 + v_perm_b32 v19, v24, v24, s18 + v_perm_b32 v21, v25, v25, s18 + s_waitcnt vmcnt(1) + v_perm_b32 v22, v26, v26, s18 + v_perm_b32 v23, v27, v27, s18 + v_perm_b32 v24, v28, v28, s18 + v_perm_b32 v25, v29, v29, s18 + s_waitcnt vmcnt(0) + v_perm_b32 v26, v30, v30, s18 + v_perm_b32 v27, v31, v31, s18 + v_perm_b32 v28, v32, v32, s18 + v_perm_b32 v29, v33, v33, s18 + s_mov_b32 s18, 0x5010400 + v_perm_b32 v30, v15, v1, s18 + v_perm_b32 v31, v26, v22, s18 + s_mov_b32 s19, 0x5040100 + v_perm_b32 v32, v31, v30, s19 + s_mov_b32 s23, 0x7060302 + v_perm_b32 v30, v31, v30, s23 + s_mov_b32 s24, 0x7030602 + v_perm_b32 v1, v15, v1, s24 + v_perm_b32 v15, v26, v22, s24 + v_perm_b32 v22, v15, v1, s19 + v_perm_b32 v1, v15, v1, s23 + v_perm_b32 v15, v16, v12, s18 + v_perm_b32 v26, v27, v23, s18 + v_perm_b32 v31, v26, v15, s19 + v_perm_b32 v15, v26, v15, s23 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v27, v23, s24 + v_perm_b32 v23, v16, v12, s19 + v_perm_b32 v12, v16, v12, s23 + v_perm_b32 v16, v19, v13, s18 + v_perm_b32 v26, v28, v24, s18 + v_perm_b32 v27, v26, v16, s19 + v_perm_b32 v16, v26, v16, s23 + v_perm_b32 v13, v19, v13, s24 + v_perm_b32 v19, v28, v24, s24 + v_perm_b32 v24, v19, v13, s19 + v_perm_b32 v13, v19, v13, s23 + v_perm_b32 v19, v21, v14, s18 + v_perm_b32 v26, v29, v25, s18 + v_perm_b32 v28, v26, v19, s19 + v_perm_b32 v19, v26, v19, s23 + v_perm_b32 v14, v21, v14, s24 + v_perm_b32 v21, v29, v25, s24 + v_perm_b32 v25, v21, v14, s19 + v_perm_b32 v14, v21, v14, s23 + v_lshrrev_b32_e32 v21, 1, v17 + v_and_b32_e32 v21, 16, v21 + v_xor_b32_e32 v26, v21, v35 + v_lshlrev_b32_e32 v29, 9, v17 + v_and_b32_e32 v29, 0x3000, v29 + v_lshlrev_b32_e32 v17, 6, v17 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v17, 0xfffff800, v17 + v_add_u32_e32 v17, v29, v17 + v_lshl_or_b32 v17, v26, 2, v17 + ds_write_b32 v17, v32 offset:16384 + v_or_b32_e32 v29, 1, v21 + v_xor_b32_e32 v29, v29, v35 + v_sub_u32_e32 v26, v29, v26 + v_lshl_add_u32 v17, v26, 2, v17 + v_or_b32_e32 v26, 2, v21 + v_xor_b32_e32 v26, v26, v35 + v_sub_u32_e32 v29, v26, v29 + v_lshl_add_u32 v29, v29, 2, v17 + ds_write_b32 v17, v30 offset:16512 + v_or_b32_e32 v17, 3, v21 + v_xor_b32_e32 v17, v17, v35 + v_sub_u32_e32 v26, v17, v26 + v_lshlrev_b32_e32 v26, 2, v26 + s_movk_i32 s19, 0x80 + v_add3_u32 v26, v29, s19, v26 + ds_write_b32 v29, v22 offset:16640 + v_or_b32_e32 v22, 4, v21 + v_xor_b32_e32 v22, v22, v35 + v_sub_u32_e32 v17, v22, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v26, s19, v17 + ds_write_b32 v26, v1 offset:16640 + v_or_b32_e32 v1, 5, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v22, v1, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v17, s19, v22 + ds_write_b32 v17, v31 offset:16640 + v_or_b32_e32 v17, 6, v21 + v_xor_b32_e32 v17, v17, v35 + v_sub_u32_e32 v1, v17, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v22, s19, v1 + ds_write_b32 v22, v15 offset:16640 + v_or_b32_e32 v15, 7, v21 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v17, v15, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v1, s19, v17 + ds_write_b32 v1, v23 offset:16640 + v_or_b32_e32 v1, 8, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v15, v1, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v17, s19, v15 + ds_write_b32 v17, v12 offset:16640 + v_or_b32_e32 v12, 9, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v15, s19, v1 + ds_write_b32 v15, v27 offset:16640 + v_or_b32_e32 v15, 10, v21 + v_xor_b32_e32 v15, v15, v35 + v_sub_u32_e32 v12, v15, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v1, s19, v12 + ds_write_b32 v1, v16 offset:16640 + v_or_b32_e32 v1, 11, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v15, v1, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v12, s19, v15 + ds_write_b32 v12, v24 offset:16640 + v_or_b32_e32 v12, 12, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v1, v15, s19, v1 + ds_write_b32 v15, v13 offset:16640 + v_or_b32_e32 v13, 13, v21 + v_xor_b32_e32 v13, v13, v35 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v1, s19, v12 + ds_write_b32 v1, v28 offset:16640 + v_or_b32_e32 v1, 14, v21 + v_xor_b32_e32 v1, v1, v35 + v_sub_u32_e32 v13, v1, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v12, s19, v13 + ds_write_b32 v12, v19 offset:16640 + v_or_b32_e32 v12, 15, v21 + v_xor_b32_e32 v12, v12, v35 + v_sub_u32_e32 v1, v12, v1 + v_lshl_add_u32 v1, v1, 2, v13 + ds_write_b32 v13, v25 offset:16640 + ds_write_b32 v1, v14 offset:16768 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v30, 2, v3 + v_add_u32_e32 v29, 4, v3 + v_add_u32_e32 v28, 6, v3 + v_add_u32_e32 v31, 64, v5 + v_lshrrev_b16_e32 v21, 3, v11 + v_or_b32_e32 v22, 16, v2 + v_add_u32_e32 v27, 16, v11 + v_add_u32_e32 v26, 20, v11 + v_or_b32_e32 v12, 16, v8 + v_add_u32_e32 v25, 36, v11 + v_add_u32_e32 v24, 48, v11 + v_add_u32_e32 v23, 52, v11 + v_or_b32_e32 v17, 4, v2 + v_or_b32_e32 v16, 20, v2 + v_or_b32_e32 v15, 8, v2 + v_or_b32_e32 v14, 24, v2 + v_or_b32_e32 v13, 12, v2 + v_or_b32_e32 v11, 28, v2 + s_cbranch_vccnz .LBB31_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit967.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v1, v7, v30 + v_lshl_add_u32 v49, v1, 3, v10 + v_xor_b32_e32 v1, v7, v29 + v_lshl_add_u32 v47, v1, 3, v10 + v_xor_b32_e32 v1, v7, v28 + v_lshl_add_u32 v19, v1, 3, v10 + v_lshrrev_b32_e32 v32, 1, v31 + v_sub_u32_e32 v33, v32, v6 + v_bfe_u32 v34, v31, 1, 4 + v_xor_b32_e32 v36, v34, v3 + v_sub_u32_e32 v36, v36, v1 + v_lshl_add_u32 v33, v33, 7, v19 + v_lshl_add_u32 v36, v36, 3, v33 + v_xor_b32_e32 v37, v34, v30 + v_sub_u32_e32 v37, v37, v1 + v_lshl_add_u32 v37, v37, 3, v33 + v_xor_b32_e32 v38, v34, v29 + v_sub_u32_e32 v38, v38, v1 + v_lshl_add_u32 v39, v38, 3, v33 + v_xor_b32_e32 v34, v34, v28 + v_sub_u32_e32 v1, v34, v1 + v_lshl_add_u32 v38, v1, 3, v33 + v_add_u32_e32 v1, 0x80, v5 + v_lshrrev_b32_e32 v33, 1, v1 + v_sub_u32_e32 v32, v33, v32 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v42, v1, v3 + v_sub_u32_e32 v34, v42, v34 + v_lshlrev_b32_e32 v34, 3, v34 + v_lshlrev_b32_e32 v32, 7, v32 + v_add3_u32 v40, v34, v32, v38 + v_xor_b32_e32 v32, v1, v30 + v_sub_u32_e32 v32, v32, v42 + v_lshl_add_u32 v41, v32, 3, v40 + v_xor_b32_e32 v32, v1, v29 + v_sub_u32_e32 v32, v32, v42 + v_lshl_add_u32 v43, v32, 3, v40 + v_xor_b32_e32 v1, v1, v28 + v_sub_u32_e32 v32, v1, v42 + v_lshl_add_u32 v42, v32, 3, v40 + v_add_u32_e32 v32, 0xc0, v5 + v_lshrrev_b32_e32 v34, 1, v32 + v_sub_u32_e32 v33, v34, v33 + v_bfe_u32 v32, v32, 1, 4 + v_xor_b32_e32 v34, v32, v3 + v_sub_u32_e32 v1, v34, v1 + v_lshlrev_b32_e32 v1, 3, v1 + v_lshlrev_b32_e32 v33, 7, v33 + v_add3_u32 v44, v1, v33, v42 + v_xor_b32_e32 v1, v32, v30 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v45, v1, 3, v44 + v_xor_b32_e32 v1, v32, v29 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v46, v1, 3, v44 + v_xor_b32_e32 v1, v32, v28 + v_sub_u32_e32 v1, v1, v34 + v_lshl_add_u32 v48, v1, 3, v44 + v_xor_b32_e32 v1, v22, v8 + v_sub_u32_e32 v32, v1, v4 + v_lshlrev_b32_e32 v32, 2, v32 + v_sub_u32_e32 v33, v21, v9 + v_lshlrev_b32_e32 v33, 12, v33 + v_add3_u32 v51, v50, v33, v32 + v_lshrrev_b32_e32 v32, 5, v27 + v_lshrrev_b16_e32 v33, 3, v27 + v_and_b32_e32 v33, 3, v33 + v_sub_u16_e32 v34, v33, v21 + v_bfe_i32 v34, v34, 0, 16 + v_lshl_or_b32 v76, v32, 4, v8 + v_xor_b32_e32 v53, v2, v76 + v_sub_u32_e32 v1, v53, v1 + v_lshlrev_b32_e32 v52, 11, v32 + v_lshlrev_b32_e32 v1, 2, v1 + v_lshl_or_b32 v34, v34, 12, v52 + v_add3_u32 v52, v1, v34, v51 + v_lshrrev_b32_e32 v1, 5, v26 + v_sub_u32_e32 v32, v1, v32 + v_lshrrev_b16_e32 v54, 3, v26 + v_and_b32_e32 v54, 3, v54 + v_sub_u16_e32 v33, v54, v33 + v_bfe_i32 v33, v33, 0, 16 + v_lshl_or_b32 v77, v1, 4, v8 + v_xor_b32_e32 v55, v22, v77 + v_sub_u32_e32 v53, v55, v53 + v_lshlrev_b32_e32 v32, 11, v32 + v_lshlrev_b32_e32 v53, 2, v53 + v_lshl_add_u32 v32, v33, 12, v32 + v_add3_u32 v53, v53, v32, v52 + v_sub_u16_e32 v33, v21, v54 + v_bfe_i32 v33, v33, 0, 16 + v_xor_b32_e32 v56, v2, v12 + v_sub_u32_e32 v54, v56, v55 + v_lshlrev_b32_e32 v1, 11, v1 + v_xor_b32_e32 v1, 0x800, v1 + v_lshlrev_b32_e32 v54, 2, v54 + v_lshl_or_b32 v1, v33, 12, v1 + v_add3_u32 v54, v54, v1, v53 + v_lshrrev_b32_e32 v33, 5, v25 + v_lshlrev_b32_e32 v55, 11, v33 + v_lshrrev_b16_e32 v57, 3, v25 + v_and_b32_e32 v57, 3, v57 + v_sub_u16_e32 v58, v57, v21 + v_lshl_or_b32 v59, v33, 4, v8 + v_and_b32_e32 v79, 31, v59 + v_xor_b32_e32 v60, v22, v79 + v_sub_u32_e32 v56, v60, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_mov_b32_e32 v62, 12 + v_lshlrev_b32_sdwa v58, v62, sext(v58) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v80, v55, v58, s18 + v_add3_u32 v59, v56, v80, v54 + v_lshrrev_b32_e32 v56, 5, v24 + v_sub_u32_e32 v33, v56, v33 + v_lshrrev_b16_e32 v55, 3, v24 + v_and_b32_e32 v58, 3, v55 + v_sub_u16_e32 v55, v58, v57 + v_bfe_i32 v55, v55, 0, 16 + v_lshl_or_b32 v57, v56, 4, v8 + v_and_b32_e32 v81, 31, v57 + v_xor_b32_e32 v57, v2, v81 + v_sub_u32_e32 v60, v57, v60 + v_lshlrev_b32_e32 v33, 11, v33 + v_lshlrev_b32_e32 v60, 2, v60 + v_lshl_add_u32 v33, v55, 12, v33 + v_add3_u32 v55, v60, v33, v59 + v_lshrrev_b32_e32 v60, 5, v23 + v_sub_u32_e32 v56, v60, v56 + v_lshrrev_b16_e32 v61, 3, v23 + v_and_b32_e32 v63, 3, v61 + v_sub_u16_e32 v58, v63, v58 + v_bfe_i32 v58, v58, 0, 16 + v_lshl_or_b32 v61, v60, 4, v8 + v_and_b32_e32 v82, 31, v61 + v_xor_b32_e32 v64, v22, v82 + v_sub_u32_e32 v57, v64, v57 + v_lshlrev_b32_e32 v56, 11, v56 + v_lshlrev_b32_e32 v57, 2, v57 + v_lshl_add_u32 v88, v58, 12, v56 + v_add3_u32 v61, v57, v88, v55 + v_sub_u16_e32 v56, v21, v63 + v_xor_b32_e32 v57, v17, v8 + v_sub_u32_e32 v58, v57, v64 + v_lshlrev_b32_e32 v58, 2, v58 + v_lshlrev_b32_sdwa v56, v62, sext(v56) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v60, 11, v60 + v_sub_u32_e32 v74, v56, v60 + v_add3_u32 v56, v58, v74, v61 + v_xor_b32_e32 v58, v16, v8 + v_sub_u32_e32 v57, v58, v57 + v_lshl_add_u32 v57, v57, 2, v56 + v_xor_b32_e32 v60, v17, v76 + v_sub_u32_e32 v58, v60, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v58, v58, v34, v57 + v_xor_b32_e32 v62, v16, v77 + v_sub_u32_e32 v60, v62, v60 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v60, v60, v32, v58 + v_xor_b32_e32 v63, v17, v12 + v_sub_u32_e32 v62, v63, v62 + v_lshlrev_b32_e32 v62, 2, v62 + v_add3_u32 v62, v62, v1, v60 + v_xor_b32_e32 v64, v16, v79 + v_sub_u32_e32 v63, v64, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v63, v63, v80, v62 + v_xor_b32_e32 v65, v17, v81 + v_sub_u32_e32 v64, v65, v64 + v_lshlrev_b32_e32 v64, 2, v64 + v_add3_u32 v64, v64, v33, v63 + v_xor_b32_e32 v66, v16, v82 + v_sub_u32_e32 v65, v66, v65 + v_lshlrev_b32_e32 v65, 2, v65 + v_add3_u32 v65, v65, v88, v64 + v_xor_b32_e32 v67, v15, v8 + v_sub_u32_e32 v66, v67, v66 + v_lshlrev_b32_e32 v66, 2, v66 + v_add3_u32 v66, v66, v74, v65 + v_xor_b32_e32 v68, v14, v8 + v_sub_u32_e32 v67, v68, v67 + v_lshl_add_u32 v67, v67, 2, v66 + v_xor_b32_e32 v69, v15, v76 + v_sub_u32_e32 v68, v69, v68 + v_lshlrev_b32_e32 v68, 2, v68 + v_add3_u32 v68, v68, v34, v67 + v_xor_b32_e32 v70, v14, v77 + v_sub_u32_e32 v69, v70, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v69, v69, v32, v68 + v_xor_b32_e32 v71, v15, v12 + v_sub_u32_e32 v70, v71, v70 + v_lshlrev_b32_e32 v70, 2, v70 + v_add3_u32 v70, v70, v1, v69 + v_xor_b32_e32 v72, v14, v79 + v_sub_u32_e32 v71, v72, v71 + v_lshlrev_b32_e32 v71, 2, v71 + v_add3_u32 v71, v71, v80, v70 + v_xor_b32_e32 v73, v15, v81 + v_sub_u32_e32 v72, v73, v72 + v_lshlrev_b32_e32 v72, 2, v72 + v_add3_u32 v72, v72, v33, v71 + v_xor_b32_e32 v75, v14, v82 + v_sub_u32_e32 v73, v75, v73 + v_lshlrev_b32_e32 v73, 2, v73 + v_add3_u32 v73, v73, v88, v72 + v_xor_b32_e32 v78, v13, v8 + v_sub_u32_e32 v75, v78, v75 + v_lshlrev_b32_e32 v75, 2, v75 + v_add3_u32 v74, v75, v74, v73 + v_xor_b32_e32 v89, v11, v8 + v_sub_u32_e32 v75, v89, v78 + v_lshl_add_u32 v75, v75, 2, v74 + v_xor_b32_e32 v78, v13, v76 + v_sub_u32_e32 v76, v78, v89 + v_lshlrev_b32_e32 v76, 2, v76 + v_add3_u32 v76, v76, v34, v75 + v_xor_b32_e32 v34, v11, v77 + v_sub_u32_e32 v77, v34, v78 + v_lshlrev_b32_e32 v77, 2, v77 + v_add3_u32 v77, v77, v32, v76 + v_xor_b32_e32 v32, v13, v12 + v_sub_u32_e32 v34, v32, v34 + v_lshlrev_b32_e32 v34, 2, v34 + v_add3_u32 v78, v34, v1, v77 + v_xor_b32_e32 v1, v11, v79 + v_sub_u32_e32 v32, v1, v32 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v79, v32, v80, v78 + v_xor_b32_e32 v32, v13, v81 + v_sub_u32_e32 v1, v32, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v80, v1, v33, v79 + v_xor_b32_e32 v1, v11, v82 + v_sub_u32_e32 v1, v1, v32 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v81, v1, v88, v80 + s_mov_b64 s[2:3], 0 + s_branch .LBB31_6 +.LBB31_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 +.LBB31_6: ; %Flow116 + v_lshl_or_b32 v82, v0, 3, v10 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_cbranch_vccnz .LBB31_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s22, 6 + v_xor_b32_e32 v0, v7, v30 + v_lshl_add_u32 v49, v0, 3, v10 + v_xor_b32_e32 v0, v7, v29 + v_lshl_add_u32 v47, v0, 3, v10 + v_xor_b32_e32 v0, v7, v28 + v_lshl_add_u32 v19, v0, 3, v10 + v_lshrrev_b32_e32 v1, 1, v31 + v_sub_u32_e32 v6, v1, v6 + v_bfe_u32 v7, v31, 1, 4 + v_xor_b32_e32 v10, v7, v3 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v6, v6, 7, v19 + v_lshl_add_u32 v36, v10, 3, v6 + v_xor_b32_e32 v10, v7, v30 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v37, v10, 3, v6 + v_xor_b32_e32 v10, v7, v29 + v_sub_u32_e32 v10, v10, v0 + v_lshl_add_u32 v39, v10, 3, v6 + v_xor_b32_e32 v7, v7, v28 + v_sub_u32_e32 v0, v7, v0 + v_lshl_add_u32 v38, v0, 3, v6 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v0, 0x80, v5 + v_lshrrev_b32_e32 v6, 1, v0 + v_sub_u32_e32 v1, v6, v1 + v_bfe_u32 v0, v0, 1, 4 + v_xor_b32_e32 v10, v0, v3 + v_sub_u32_e32 v7, v10, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v1, 7, v1 + v_add3_u32 v40, v7, v1, v38 + v_xor_b32_e32 v1, v0, v30 + v_sub_u32_e32 v1, v1, v10 + v_lshl_add_u32 v41, v1, 3, v40 + v_xor_b32_e32 v1, v0, v29 + v_sub_u32_e32 v1, v1, v10 + v_lshl_add_u32 v43, v1, 3, v40 + v_xor_b32_e32 v0, v0, v28 + v_sub_u32_e32 v1, v0, v10 + v_lshl_add_u32 v42, v1, 3, v40 + v_add_u32_e32 v1, 0xc0, v5 + v_lshrrev_b32_e32 v5, 1, v1 + v_sub_u32_e32 v5, v5, v6 + v_bfe_u32 v1, v1, 1, 4 + v_xor_b32_e32 v3, v1, v3 + v_sub_u32_e32 v0, v3, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_lshlrev_b32_e32 v5, 7, v5 + v_add3_u32 v44, v0, v5, v42 + v_xor_b32_e32 v0, v1, v30 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v45, v0, 3, v44 + v_xor_b32_e32 v0, v1, v29 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v46, v0, 3, v44 + v_xor_b32_e32 v0, v1, v28 + v_sub_u32_e32 v0, v0, v3 + v_lshl_add_u32 v48, v0, 3, v44 + v_xor_b32_e32 v0, v22, v8 + v_sub_u32_e32 v1, v0, v4 + v_lshlrev_b32_e32 v1, 2, v1 + v_sub_u32_e32 v3, v21, v9 + v_lshlrev_b32_e32 v3, 12, v3 + v_add3_u32 v51, v50, v3, v1 + v_lshrrev_b32_e32 v1, 5, v27 + v_lshrrev_b16_e32 v3, 3, v27 + v_and_b32_e32 v3, 3, v3 + v_sub_u16_e32 v4, v3, v21 + v_bfe_i32 v4, v4, 0, 16 + v_lshl_or_b32 v5, v1, 4, v8 + v_xor_b32_e32 v6, v2, v5 + v_sub_u32_e32 v0, v6, v0 + v_lshlrev_b32_e32 v7, 11, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_lshl_or_b32 v4, v4, 12, v7 + v_add3_u32 v52, v0, v4, v51 + v_lshrrev_b32_e32 v0, 5, v26 + v_sub_u32_e32 v1, v0, v1 + v_lshrrev_b16_e32 v7, 3, v26 + v_and_b32_e32 v7, 3, v7 + v_sub_u16_e32 v3, v7, v3 + v_bfe_i32 v3, v3, 0, 16 + v_lshl_or_b32 v9, v0, 4, v8 + v_xor_b32_e32 v10, v22, v9 + v_sub_u32_e32 v6, v10, v6 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v6, 2, v6 + v_lshl_add_u32 v1, v3, 12, v1 + v_add3_u32 v53, v6, v1, v52 + v_sub_u16_e32 v3, v21, v7 + v_bfe_i32 v3, v3, 0, 16 + v_xor_b32_e32 v6, v2, v12 + v_sub_u32_e32 v7, v6, v10 + v_lshlrev_b32_e32 v0, 11, v0 + v_xor_b32_e32 v0, 0x800, v0 + v_lshlrev_b32_e32 v7, 2, v7 + v_lshl_or_b32 v0, v3, 12, v0 + v_add3_u32 v54, v7, v0, v53 + v_lshrrev_b32_e32 v3, 5, v25 + v_lshlrev_b32_e32 v7, 11, v3 + v_lshrrev_b16_e32 v10, 3, v25 + v_and_b32_e32 v10, 3, v10 + v_sub_u16_e32 v25, v10, v21 + v_lshl_or_b32 v26, v3, 4, v8 + v_and_b32_e32 v26, 31, v26 + v_xor_b32_e32 v27, v22, v26 + v_sub_u32_e32 v6, v27, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_mov_b32_e32 v28, 12 + v_lshlrev_b32_sdwa v25, v28, sext(v25) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v7, v7, v25, s18 + v_add3_u32 v59, v6, v7, v54 + v_lshrrev_b32_e32 v6, 5, v24 + v_sub_u32_e32 v3, v6, v3 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v10, v24, v10 + v_bfe_i32 v10, v10, 0, 16 + v_lshl_or_b32 v25, v6, 4, v8 + v_and_b32_e32 v25, 31, v25 + v_xor_b32_e32 v2, v2, v25 + v_sub_u32_e32 v27, v2, v27 + v_lshlrev_b32_e32 v3, 11, v3 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_add_u32 v3, v10, 12, v3 + v_add3_u32 v55, v27, v3, v59 + v_lshrrev_b32_e32 v10, 5, v23 + v_sub_u32_e32 v6, v10, v6 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v24, v23, v24 + v_bfe_i32 v24, v24, 0, 16 + v_lshl_or_b32 v27, v10, 4, v8 + v_and_b32_e32 v27, 31, v27 + v_xor_b32_e32 v22, v22, v27 + v_sub_u32_e32 v2, v22, v2 + v_lshlrev_b32_e32 v6, 11, v6 + v_lshlrev_b32_e32 v2, 2, v2 + v_lshl_add_u32 v6, v24, 12, v6 + v_add3_u32 v61, v2, v6, v55 + v_sub_u16_e32 v2, v21, v23 + v_xor_b32_e32 v21, v17, v8 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_lshlrev_b32_sdwa v2, v28, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v10, 11, v10 + v_sub_u32_e32 v2, v2, v10 + v_add3_u32 v56, v22, v2, v61 + v_xor_b32_e32 v10, v16, v8 + v_sub_u32_e32 v21, v10, v21 + v_lshl_add_u32 v57, v21, 2, v56 + v_xor_b32_e32 v21, v17, v5 + v_sub_u32_e32 v10, v21, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v58, v10, v4, v57 + v_xor_b32_e32 v10, v16, v9 + v_sub_u32_e32 v21, v10, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v60, v21, v1, v58 + v_xor_b32_e32 v21, v17, v12 + v_sub_u32_e32 v10, v21, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v62, v10, v0, v60 + v_xor_b32_e32 v10, v16, v26 + v_sub_u32_e32 v21, v10, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v63, v21, v7, v62 + v_xor_b32_e32 v17, v17, v25 + v_sub_u32_e32 v10, v17, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v64, v10, v3, v63 + v_xor_b32_e32 v10, v16, v27 + v_sub_u32_e32 v16, v10, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v65, v16, v6, v64 + v_xor_b32_e32 v16, v15, v8 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v66, v10, v2, v65 + v_xor_b32_e32 v10, v14, v8 + v_sub_u32_e32 v16, v10, v16 + v_lshl_add_u32 v67, v16, 2, v66 + v_xor_b32_e32 v16, v15, v5 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v68, v10, v4, v67 + v_xor_b32_e32 v10, v14, v9 + v_sub_u32_e32 v16, v10, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v69, v16, v1, v68 + v_xor_b32_e32 v16, v15, v12 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v70, v10, v0, v69 + v_xor_b32_e32 v10, v14, v26 + v_sub_u32_e32 v16, v10, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v71, v16, v7, v70 + v_xor_b32_e32 v15, v15, v25 + v_sub_u32_e32 v10, v15, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v72, v10, v3, v71 + v_xor_b32_e32 v10, v14, v27 + v_sub_u32_e32 v14, v10, v15 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v73, v14, v6, v72 + v_xor_b32_e32 v14, v13, v8 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v74, v10, v2, v73 + v_xor_b32_e32 v2, v11, v8 + v_sub_u32_e32 v8, v2, v14 + v_lshl_add_u32 v75, v8, 2, v74 + v_xor_b32_e32 v5, v13, v5 + v_sub_u32_e32 v2, v5, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v76, v2, v4, v75 + v_xor_b32_e32 v2, v11, v9 + v_sub_u32_e32 v4, v2, v5 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v77, v4, v1, v76 + v_xor_b32_e32 v1, v13, v12 + v_sub_u32_e32 v2, v1, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v78, v2, v0, v77 + v_xor_b32_e32 v0, v11, v26 + v_sub_u32_e32 v1, v0, v1 + v_lshlrev_b32_e32 v1, 2, v1 + v_add3_u32 v79, v1, v7, v78 + v_xor_b32_e32 v1, v13, v25 + v_sub_u32_e32 v0, v1, v0 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v80, v0, v3, v79 + v_xor_b32_e32 v0, v11, v27 + v_sub_u32_e32 v0, v0, v1 + v_lshlrev_b32_e32 v0, 2, v0 + v_add3_u32 v81, v0, v6, v80 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 +.LBB31_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v18, s2, v18 + v_add_u32_e32 v0, 64, v20 + buffer_load_dwordx4 v[92:95], v20, s[8:11], 0 offen offset:64 + v_add_u32_e32 v1, s7, v0 + buffer_load_dwordx4 v[2:5], v18, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v18 + buffer_load_dwordx4 v[100:103], v1, s[8:11], 0 offen + v_add_u32_e32 v1, s7, v1 + buffer_load_dwordx4 v[14:17], v6, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v6 + v_add_u32_e32 v7, s7, v1 + buffer_load_dwordx4 v[10:13], v6, s[12:15], 0 offen + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[104:107], v1, s[8:11], 0 offen + buffer_load_dwordx4 v[96:99], v7, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[6:9], v6, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[22:23], v82 + ds_read_b64 v[20:21], v47 + ds_read_b32 v90, v50 offset:16384 + ds_read_b32 v91, v51 offset:16384 + ds_read_b32 v124, v52 offset:16384 + ds_read_b32 v125, v53 offset:16384 + ds_read_b32 v116, v54 offset:16384 + ds_read_b32 v117, v59 offset:16384 + ds_read_b32 v108, v55 offset:16384 + ds_read_b32 v109, v61 offset:16384 + ds_read_b32 v126, v56 offset:16384 + ds_read_b32 v127, v57 offset:16384 + ds_read_b32 v128, v58 offset:16384 + s_waitcnt lgkmcnt(9) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[22:23], v[90:91], a[64:79] + ds_read_b32 v129, v60 offset:16384 + ds_read_b32 v118, v62 offset:16384 + ds_read_b32 v119, v63 offset:16384 + ds_read_b32 v110, v64 offset:16384 + ds_read_b32 v111, v65 offset:16384 + ds_read_b32 v130, v66 offset:16384 + ds_read_b32 v131, v67 offset:16384 + s_waitcnt lgkmcnt(8) + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[22:23], v[126:127], a[80:95] + ds_read_b32 v132, v68 offset:16384 + ds_read_b32 v133, v69 offset:16384 + ds_read_b32 v120, v70 offset:16384 + ds_read_b32 v121, v71 offset:16384 + ds_read_b32 v112, v72 offset:16384 + ds_read_b32 v113, v73 offset:16384 + ds_read_b32 v134, v74 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[22:23], v[130:131], a[96:111] + ds_read_b32 v135, v75 offset:16384 + ds_read_b32 v136, v76 offset:16384 + ds_read_b32 v137, v77 offset:16384 + ds_read_b32 v122, v78 offset:16384 + ds_read_b32 v123, v79 offset:16384 + ds_read_b32 v114, v80 offset:16384 + ds_read_b32 v115, v81 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[22:23], v[134:135], a[112:127] + ds_read_b64 v[22:23], v36 + ds_read_b64 v[28:29], v37 + ds_read_b64 v[26:27], v39 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[22:23], v[90:91], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[22:23], v[126:127], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[22:23], v[130:131], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[22:23], v[134:135], a[176:191] + ds_read_b64 v[22:23], v40 + ds_read_b64 v[30:31], v41 + ds_read_b64 v[24:25], v43 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[22:23], v[90:91], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[22:23], v[126:127], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[22:23], v[130:131], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[22:23], v[134:135], a[240:255] + ds_read_b64 v[88:89], v44 + ds_read_b64 v[32:33], v45 + ds_read_b64 v[22:23], v46 + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[88:89], v[90:91], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[88:89], v[126:127], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[88:89], v[130:131], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[88:89], v[134:135], a[48:63] + ds_read_b64 v[88:89], v49 + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[88:89], v[124:125], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[88:89], v[128:129], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[88:89], v[132:133], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[88:89], v[136:137], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[28:29], v[124:125], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[28:29], v[128:129], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[28:29], v[132:133], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[28:29], v[136:137], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[30:31], v[124:125], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[30:31], v[128:129], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[30:31], v[132:133], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[30:31], v[136:137], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[32:33], v[124:125], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[32:33], v[128:129], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[32:33], v[132:133], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[32:33], v[136:137], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[20:21], v[116:117], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[20:21], v[118:119], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[20:21], v[120:121], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[20:21], v[122:123], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[26:27], v[116:117], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[26:27], v[118:119], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[26:27], v[120:121], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[26:27], v[122:123], a[176:191] + s_add_i32 s26, s3, -1 + v_readfirstlane_b32 s27, v227 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[24:25], v[116:117], a[192:207] + s_and_b32 s28, s27, 0xffffffc0 + s_lshr_b32 s27, s27, 2 + v_add_u32_e32 v21, s28, v83 + s_and_b32 s27, s27, 0x3ffffff0 + v_mov_b32_e32 v20, v0 + v_ashrrev_i32_e32 v1, 1, v21 + v_ashrrev_i32_e32 v89, 31, v21 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[24:25], v[118:119], a[208:223] + v_lshlrev_b32_e32 v0, 6, v21 + v_or_b32_e32 v34, 1, v21 + v_lshrrev_b32_e32 v90, 31, v21 + v_or_b32_e32 v21, 3, v21 + v_add_u32_e32 v88, s27, v84 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s26 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[24:25], v[120:121], a[224:239] + ds_read_b64 v[30:31], v19 + ds_read_b64 v[28:29], v38 + ds_read_b64 v[26:27], v42 + ds_read_b64 v[32:33], v48 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v89, 28, v89 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[24:25], v[122:123], a[240:255] + v_add_u32_e32 v24, v34, v90 + v_or_b32_e32 v25, 1, v1 + v_add_u32_e32 v90, v21, v90 + v_lshrrev_b32_e32 v91, 1, v88 + v_lshlrev_b32_e32 v124, 9, v88 + v_lshlrev_b32_e32 v88, 6, v88 + v_add_u32_e32 v125, v1, v89 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[22:23], v[116:117], a[16:31] + v_ashrrev_i32_e32 v116, 1, v24 + v_and_b32_e32 v117, 0x1ffffffe, v24 + v_ashrrev_i32_e32 v24, 31, v24 + v_add_u32_e32 v89, v25, v89 + v_ashrrev_i32_e32 v126, 1, v90 + v_and_b32_e32 v127, 0x1ffffffe, v90 + v_ashrrev_i32_e32 v90, 31, v90 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[22:23], v[118:119], a[32:47] + v_and_b32_e32 v91, 16, v91 + v_and_b32_e32 v118, 0x3000, v124 + v_and_b32_e32 v88, 0xfffff800, v88 + v_and_b32_e32 v119, -16, v125 + v_sub_u32_e32 v124, v116, v1 + v_sub_u32_e32 v34, v34, v117 + v_lshrrev_b32_e32 v24, 28, v24 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[22:23], v[120:121], a[0:15] + v_sub_u32_e32 v117, v25, v116 + v_and_b32_e32 v89, -16, v89 + v_sub_u32_e32 v120, v126, v25 + v_sub_u32_e32 v21, v21, v127 + v_lshrrev_b32_e32 v90, 28, v90 + v_xor_b32_e32 v121, v91, v35 + v_add_u32_e32 v88, v118, v88 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[22:23], v[122:123], a[48:63] + v_or_b32_e32 v22, 1, v91 + v_or_b32_e32 v23, 2, v91 + v_or_b32_e32 v118, 3, v91 + v_or_b32_e32 v122, 4, v91 + v_or_b32_e32 v123, 5, v91 + v_or_b32_e32 v125, 6, v91 + v_or_b32_e32 v127, 7, v91 + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[30:31], v[108:109], a[64:79] + v_or_b32_e32 v128, 8, v91 + v_or_b32_e32 v129, 9, v91 + v_or_b32_e32 v130, 10, v91 + v_or_b32_e32 v131, 11, v91 + v_or_b32_e32 v132, 12, v91 + v_or_b32_e32 v133, 13, v91 + v_or_b32_e32 v134, 14, v91 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[30:31], v[110:111], a[80:95] + v_or_b32_e32 v91, 15, v91 + v_sub_u32_e32 v1, v1, v119 + v_lshl_or_b32 v34, v34, 3, v86 + v_add_u32_e32 v24, v116, v24 + v_sub_u32_e32 v25, v25, v89 + v_lshlrev_b32_e32 v89, 7, v117 + v_lshl_or_b32 v21, v21, 3, v86 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[30:31], v[112:113], a[96:111] + v_add_u32_e32 v90, v126, v90 + v_lshlrev_b32_e32 v117, 7, v120 + v_lshl_or_b32 v88, v121, 2, v88 + v_xor_b32_e32 v22, v22, v35 + v_xor_b32_e32 v23, v23, v35 + v_xor_b32_e32 v118, v118, v35 + v_xor_b32_e32 v119, v122, v35 + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[30:31], v[114:115], a[112:127] + v_xor_b32_e32 v30, v123, v35 + v_xor_b32_e32 v31, v125, v35 + v_xor_b32_e32 v120, v127, v35 + v_xor_b32_e32 v122, v128, v35 + v_xor_b32_e32 v123, v129, v35 + v_xor_b32_e32 v125, v130, v35 + v_xor_b32_e32 v127, v131, v35 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[28:29], v[108:109], a[128:143] + v_xor_b32_e32 v128, v132, v35 + v_xor_b32_e32 v129, v133, v35 + v_xor_b32_e32 v130, v134, v35 + v_xor_b32_e32 v91, v91, v35 + v_xor_b32_e32 v131, v1, v85 + v_xor_b32_e32 v1, v1, v86 + v_add_u32_e32 v132, v34, v87 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[28:29], v[110:111], a[144:159] + v_and_b32_e32 v24, -16, v24 + v_xor_b32_e32 v133, v25, v85 + v_xor_b32_e32 v25, v25, v86 + v_add_u32_e32 v134, v21, v87 + v_and_b32_e32 v90, -16, v90 + v_sub_u32_e32 v121, v22, v121 + v_sub_u32_e32 v22, v23, v22 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[28:29], v[112:113], a[160:175] + v_sub_u32_e32 v23, v118, v23 + v_sub_u32_e32 v118, v119, v118 + v_sub_u32_e32 v119, v30, v119 + v_sub_u32_e32 v30, v31, v30 + v_sub_u32_e32 v31, v120, v31 + v_sub_u32_e32 v120, v122, v120 + v_sub_u32_e32 v122, v123, v122 + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[28:29], v[114:115], a[176:191] + v_sub_u32_e32 v28, v125, v123 + v_sub_u32_e32 v29, v127, v125 + v_sub_u32_e32 v123, v128, v127 + v_sub_u32_e32 v125, v129, v128 + v_sub_u32_e32 v127, v130, v129 + v_sub_u32_e32 v91, v91, v130 + v_lshl_add_u32 v128, v131, 3, v0 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[26:27], v[108:109], a[192:207] + v_lshl_add_u32 v0, v1, 3, v0 + v_sub_u32_e32 v24, v116, v24 + v_sub_u32_e32 v116, v25, v133 + v_sub_u32_e32 v90, v126, v90 + v_lshl_add_u32 v121, v121, 2, v88 + v_lshlrev_b32_e32 v23, 2, v23 + v_lshlrev_b32_e32 v118, 2, v118 + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[26:27], v[110:111], a[208:223] + v_lshlrev_b32_e32 v119, 2, v119 + v_lshlrev_b32_e32 v30, 2, v30 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshlrev_b32_e32 v120, 2, v120 + v_lshlrev_b32_e32 v122, 2, v122 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshlrev_b32_e32 v29, 2, v29 + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[26:27], v[112:113], a[224:239] + v_lshlrev_b32_e32 v123, 2, v123 + v_lshlrev_b32_e32 v125, 2, v125 + v_lshlrev_b32_e32 v126, 2, v127 + v_xor_b32_e32 v127, v132, v24 + v_lshl_add_u32 v124, v124, 7, v0 + v_xor_b32_e32 v24, v34, v24 + v_xor_b32_e32 v34, v134, v90 + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[26:27], v[114:115], a[240:255] + v_xor_b32_e32 v21, v21, v90 + v_lshl_add_u32 v22, v22, 2, v121 + v_sub_u32_e32 v26, v127, v1 + v_sub_u32_e32 v1, v24, v1 + v_sub_u32_e32 v24, v133, v24 + v_sub_u32_e32 v25, v34, v25 + v_sub_u32_e32 v21, v21, v34 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[32:33], v[108:109], a[16:31] + v_add3_u32 v23, v22, s6, v23 + v_lshl_add_u32 v26, v26, 3, v124 + v_lshl_add_u32 v1, v1, 3, v124 + v_lshlrev_b32_e32 v24, 3, v24 + v_lshlrev_b32_e32 v25, 3, v25 + v_add3_u32 v27, v23, s6, v118 + v_add3_u32 v24, v24, v89, v1 + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[32:33], v[110:111], a[32:47] + v_add3_u32 v34, v27, s6, v119 + v_lshl_add_u32 v89, v116, 3, v24 + v_add3_u32 v30, v34, s6, v30 + v_add3_u32 v25, v25, v117, v89 + v_add3_u32 v31, v30, s6, v31 + v_lshl_add_u32 v21, v21, 3, v25 + v_add3_u32 v90, v31, s6, v120 + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[32:33], v[112:113], a[0:15] + v_add3_u32 v108, v90, s6, v122 + v_add3_u32 v28, v108, s6, v28 + v_add3_u32 v29, v28, s6, v29 + v_add3_u32 v109, v29, s6, v123 + v_add3_u32 v110, v109, s6, v125 + v_add3_u32 v111, v110, s6, v126 + v_lshl_add_u32 v91, v91, 2, v111 + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[32:33], v[114:115], a[48:63] + s_waitcnt vmcnt(7) + ds_write_b64 v128, v[92:93] + ds_write_b64 v0, v[94:95] + s_waitcnt vmcnt(6) + v_perm_b32 v0, v2, v2, s18 + v_perm_b32 v2, v3, v3, s18 + v_perm_b32 v3, v4, v4, s18 + v_perm_b32 v4, v5, v5, s18 + s_waitcnt vmcnt(5) + ds_write_b64 v26, v[100:101] + ds_write_b64 v1, v[102:103] + s_waitcnt vmcnt(4) + v_perm_b32 v1, v14, v14, s18 + v_perm_b32 v5, v15, v15, s18 + v_perm_b32 v14, v16, v16, s18 + v_perm_b32 v15, v17, v17, s18 + s_waitcnt vmcnt(2) + ds_write_b64 v24, v[104:105] + ds_write_b64 v89, v[106:107] + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + v_perm_b32 v16, v1, v0, s19 + v_perm_b32 v0, v1, v0, s25 + v_perm_b32 v1, v5, v2, s19 + v_perm_b32 v2, v5, v2, s25 + v_perm_b32 v5, v14, v3, s19 + v_perm_b32 v3, v14, v3, s25 + v_perm_b32 v14, v15, v4, s19 + v_perm_b32 v4, v15, v4, s25 + s_waitcnt vmcnt(1) + ds_write_b64 v25, v[96:97] + ds_write_b64 v21, v[98:99] + s_waitcnt vmcnt(0) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + v_perm_b32 v15, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + v_perm_b32 v13, v15, v16, s23 + v_perm_b32 v15, v15, v16, s24 + v_perm_b32 v16, v6, v0, s23 + v_perm_b32 v0, v6, v0, s24 + v_perm_b32 v6, v10, v1, s23 + v_perm_b32 v1, v10, v1, s24 + v_perm_b32 v10, v7, v2, s23 + v_perm_b32 v2, v7, v2, s24 + v_perm_b32 v7, v11, v5, s23 + v_perm_b32 v5, v11, v5, s24 + v_perm_b32 v11, v8, v3, s23 + v_perm_b32 v3, v8, v3, s24 + v_perm_b32 v8, v12, v14, s23 + v_perm_b32 v12, v12, v14, s24 + v_perm_b32 v14, v9, v4, s23 + v_perm_b32 v4, v9, v4, s24 + ds_write_b32 v88, v13 offset:16384 + ds_write_b32 v121, v15 offset:16512 + ds_write_b32 v22, v16 offset:16640 + ds_write_b32 v23, v0 offset:16640 + ds_write_b32 v27, v6 offset:16640 + ds_write_b32 v34, v1 offset:16640 + ds_write_b32 v30, v10 offset:16640 + ds_write_b32 v31, v2 offset:16640 + ds_write_b32 v90, v7 offset:16640 + ds_write_b32 v108, v5 offset:16640 + ds_write_b32 v28, v11 offset:16640 + ds_write_b32 v29, v3 offset:16640 + ds_write_b32 v109, v8 offset:16640 + ds_write_b32 v110, v12 offset:16640 + ds_write_b32 v111, v14 offset:16640 + ds_write_b32 v91, v4 offset:16768 + s_cbranch_scc1 .LBB31_8 +.LBB31_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESC_SC_Li1EEES2_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSK_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDaRKS1O_ + v_accvgpr_read_b32 v0, a64 + v_accvgpr_read_b32 v1, a65 + v_accvgpr_read_b32 v2, a66 + v_accvgpr_read_b32 v3, a67 + v_accvgpr_read_b32 v4, a68 + v_accvgpr_read_b32 v5, a69 + v_accvgpr_read_b32 v6, a70 + v_accvgpr_read_b32 v7, a71 + v_accvgpr_read_b32 v8, a72 + v_accvgpr_read_b32 v9, a73 + v_accvgpr_read_b32 v10, a74 + v_accvgpr_read_b32 v11, a75 + v_accvgpr_read_b32 v12, a76 + v_accvgpr_read_b32 v13, a77 + v_accvgpr_read_b32 v14, a78 + v_accvgpr_read_b32 v15, a79 + v_accvgpr_read_b32 v20, a160 + v_accvgpr_read_b32 v21, a161 + v_accvgpr_read_b32 v22, a162 + v_accvgpr_read_b32 v23, a163 + v_accvgpr_read_b32 v24, a164 + v_accvgpr_read_b32 v25, a165 + v_accvgpr_read_b32 v26, a166 + v_accvgpr_read_b32 v27, a167 + v_accvgpr_read_b32 v28, a168 + v_accvgpr_read_b32 v29, a169 + v_accvgpr_read_b32 v30, a170 + v_accvgpr_read_b32 v31, a171 + v_accvgpr_read_b32 v32, a172 + v_accvgpr_read_b32 v33, a173 + v_accvgpr_read_b32 v34, a174 + v_accvgpr_read_b32 v35, a175 + v_accvgpr_read_b32 v84, a176 + v_accvgpr_read_b32 v85, a177 + v_accvgpr_read_b32 v86, a178 + v_accvgpr_read_b32 v87, a179 + v_accvgpr_read_b32 v88, a180 + v_accvgpr_read_b32 v89, a181 + v_accvgpr_read_b32 v90, a182 + v_accvgpr_read_b32 v91, a183 + v_accvgpr_read_b32 v92, a184 + v_accvgpr_read_b32 v93, a185 + v_accvgpr_read_b32 v94, a186 + v_accvgpr_read_b32 v95, a187 + v_accvgpr_read_b32 v96, a188 + v_accvgpr_read_b32 v97, a189 + v_accvgpr_read_b32 v98, a190 + v_accvgpr_read_b32 v99, a191 + v_accvgpr_read_b32 v100, a208 + v_accvgpr_read_b32 v101, a209 + v_accvgpr_read_b32 v102, a210 + v_accvgpr_read_b32 v103, a211 + v_accvgpr_read_b32 v104, a212 + v_accvgpr_read_b32 v105, a213 + v_accvgpr_read_b32 v106, a214 + v_accvgpr_read_b32 v107, a215 + v_accvgpr_read_b32 v108, a216 + v_accvgpr_read_b32 v109, a217 + v_accvgpr_read_b32 v110, a218 + v_accvgpr_read_b32 v111, a219 + v_accvgpr_read_b32 v112, a220 + v_accvgpr_read_b32 v113, a221 + v_accvgpr_read_b32 v114, a222 + v_accvgpr_read_b32 v115, a223 + v_accvgpr_read_b32 v116, a224 + v_accvgpr_read_b32 v117, a225 + v_accvgpr_read_b32 v118, a226 + v_accvgpr_read_b32 v119, a227 + v_accvgpr_read_b32 v120, a228 + v_accvgpr_read_b32 v121, a229 + v_accvgpr_read_b32 v122, a230 + v_accvgpr_read_b32 v123, a231 + v_accvgpr_read_b32 v124, a232 + v_accvgpr_read_b32 v125, a233 + v_accvgpr_read_b32 v126, a234 + v_accvgpr_read_b32 v127, a235 + v_accvgpr_read_b32 v128, a236 + v_accvgpr_read_b32 v129, a237 + v_accvgpr_read_b32 v130, a238 + v_accvgpr_read_b32 v131, a239 + v_accvgpr_mov_b32 a64, a240 + v_accvgpr_mov_b32 a65, a241 + v_accvgpr_mov_b32 a66, a242 + v_accvgpr_mov_b32 a67, a243 + v_accvgpr_mov_b32 a68, a244 + v_accvgpr_mov_b32 a69, a245 + v_accvgpr_mov_b32 a70, a246 + v_accvgpr_mov_b32 a71, a247 + v_accvgpr_mov_b32 a72, a248 + v_accvgpr_mov_b32 a73, a249 + v_accvgpr_mov_b32 a74, a250 + v_accvgpr_mov_b32 a75, a251 + v_accvgpr_mov_b32 a76, a252 + v_accvgpr_mov_b32 a77, a253 + v_accvgpr_mov_b32 a78, a254 + v_accvgpr_mov_b32 a79, a255 + v_accvgpr_read_b32 v132, a0 + v_accvgpr_read_b32 v133, a1 + v_accvgpr_read_b32 v134, a2 + v_accvgpr_read_b32 v135, a3 + v_accvgpr_read_b32 v136, a4 + v_accvgpr_read_b32 v137, a5 + v_accvgpr_read_b32 v138, a6 + v_accvgpr_read_b32 v139, a7 + v_accvgpr_read_b32 v140, a8 + v_accvgpr_read_b32 v141, a9 + v_accvgpr_read_b32 v142, a10 + v_accvgpr_read_b32 v143, a11 + v_accvgpr_read_b32 v144, a12 + v_accvgpr_read_b32 v145, a13 + v_accvgpr_read_b32 v146, a14 + v_accvgpr_read_b32 v147, a15 + v_accvgpr_read_b32 v148, a48 + v_accvgpr_read_b32 v149, a49 + v_accvgpr_read_b32 v150, a50 + v_accvgpr_read_b32 v151, a51 + v_accvgpr_read_b32 v152, a52 + v_accvgpr_read_b32 v153, a53 + v_accvgpr_read_b32 v154, a54 + v_accvgpr_read_b32 v155, a55 + v_accvgpr_read_b32 v156, a56 + v_accvgpr_read_b32 v157, a57 + v_accvgpr_read_b32 v158, a58 + v_accvgpr_read_b32 v159, a59 + v_accvgpr_read_b32 v160, a60 + v_accvgpr_read_b32 v161, a61 + v_accvgpr_read_b32 v162, a62 + v_accvgpr_read_b32 v163, a63 + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_write_b32 a0, v0 + v_accvgpr_write_b32 a1, v1 + v_accvgpr_write_b32 a2, v2 + v_accvgpr_write_b32 a3, v3 + v_accvgpr_write_b32 a4, v4 + v_accvgpr_write_b32 a5, v5 + v_accvgpr_write_b32 a6, v6 + v_accvgpr_write_b32 a7, v7 + v_accvgpr_write_b32 a8, v8 + v_accvgpr_write_b32 a9, v9 + v_accvgpr_write_b32 a10, v10 + v_accvgpr_write_b32 a11, v11 + v_accvgpr_write_b32 a12, v12 + v_accvgpr_write_b32 a13, v13 + v_accvgpr_write_b32 a14, v14 + v_accvgpr_write_b32 a15, v15 + ds_read_b64 v[2:3], v82 + ds_read_b32 v0, v50 offset:16384 + ds_read_b64 v[4:5], v49 + ds_read_b64 v[6:7], v47 + ds_read_b32 v1, v51 offset:16384 + ds_read_b32 v50, v52 offset:16384 + ds_read_b32 v51, v53 offset:16384 + ds_read_b32 v52, v54 offset:16384 + ds_read_b32 v53, v59 offset:16384 + ds_read_b32 v54, v55 offset:16384 + ds_read_b32 v55, v61 offset:16384 + ds_read_b64 v[8:9], v48 + s_waitcnt lgkmcnt(7) + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[2:3], v[0:1], a[0:15] + v_accvgpr_mov_b32 a255, a95 + v_accvgpr_mov_b32 a254, a94 + v_accvgpr_mov_b32 a253, a93 + v_accvgpr_mov_b32 a252, a92 + v_accvgpr_mov_b32 a251, a91 + v_accvgpr_mov_b32 a250, a90 + v_accvgpr_mov_b32 a249, a89 + v_accvgpr_mov_b32 a248, a88 + v_accvgpr_mov_b32 a247, a87 + v_accvgpr_mov_b32 a246, a86 + v_accvgpr_mov_b32 a245, a85 + v_accvgpr_mov_b32 a244, a84 + v_accvgpr_mov_b32 a243, a83 + v_accvgpr_mov_b32 a242, a82 + v_accvgpr_mov_b32 a241, a81 + v_accvgpr_mov_b32 a240, a80 + ds_read_b32 v48, v56 offset:16384 + ds_read_b32 v49, v57 offset:16384 + ds_read_b32 v56, v58 offset:16384 + ds_read_b32 v57, v60 offset:16384 + ds_read_b32 v58, v62 offset:16384 + ds_read_b32 v59, v63 offset:16384 + ds_read_b32 v60, v64 offset:16384 + ds_read_b32 v61, v65 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[2:3], v[48:49], a[240:255] + v_accvgpr_mov_b32 a239, a111 + v_accvgpr_mov_b32 a238, a110 + v_accvgpr_mov_b32 a237, a109 + v_accvgpr_mov_b32 a236, a108 + v_accvgpr_mov_b32 a235, a107 + v_accvgpr_mov_b32 a234, a106 + v_accvgpr_mov_b32 a233, a105 + v_accvgpr_mov_b32 a232, a104 + v_accvgpr_mov_b32 a231, a103 + v_accvgpr_mov_b32 a230, a102 + v_accvgpr_mov_b32 a229, a101 + v_accvgpr_mov_b32 a228, a100 + v_accvgpr_mov_b32 a227, a99 + v_accvgpr_mov_b32 a226, a98 + v_accvgpr_mov_b32 a225, a97 + v_accvgpr_mov_b32 a224, a96 + ds_read_b32 v62, v66 offset:16384 + ds_read_b32 v63, v67 offset:16384 + ds_read_b32 v64, v68 offset:16384 + ds_read_b32 v65, v69 offset:16384 + ds_read_b32 v66, v70 offset:16384 + ds_read_b32 v67, v71 offset:16384 + ds_read_b32 v68, v72 offset:16384 + ds_read_b32 v69, v73 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[2:3], v[62:63], a[224:239] + v_accvgpr_mov_b32 a223, a127 + v_accvgpr_mov_b32 a222, a126 + v_accvgpr_mov_b32 a221, a125 + v_accvgpr_mov_b32 a220, a124 + v_accvgpr_mov_b32 a219, a123 + v_accvgpr_mov_b32 a218, a122 + v_accvgpr_mov_b32 a217, a121 + v_accvgpr_mov_b32 a216, a120 + v_accvgpr_mov_b32 a215, a119 + v_accvgpr_mov_b32 a214, a118 + v_accvgpr_mov_b32 a213, a117 + v_accvgpr_mov_b32 a212, a116 + v_accvgpr_mov_b32 a211, a115 + v_accvgpr_mov_b32 a210, a114 + v_accvgpr_mov_b32 a209, a113 + v_accvgpr_mov_b32 a208, a112 + ds_read_b32 v70, v74 offset:16384 + ds_read_b32 v71, v75 offset:16384 + ds_read_b32 v72, v76 offset:16384 + ds_read_b32 v73, v77 offset:16384 + ds_read_b32 v74, v78 offset:16384 + ds_read_b32 v75, v79 offset:16384 + ds_read_b32 v76, v80 offset:16384 + ds_read_b32 v77, v81 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[2:3], v[70:71], a[208:223] + ds_read_b64 v[2:3], v36 + v_accvgpr_mov_b32 a191, a143 + v_accvgpr_mov_b32 a190, a142 + v_accvgpr_mov_b32 a189, a141 + v_accvgpr_mov_b32 a188, a140 + v_accvgpr_mov_b32 a187, a139 + v_accvgpr_mov_b32 a186, a138 + v_accvgpr_mov_b32 a185, a137 + v_accvgpr_mov_b32 a184, a136 + v_accvgpr_mov_b32 a183, a135 + v_accvgpr_mov_b32 a182, a134 + v_accvgpr_mov_b32 a181, a133 + v_accvgpr_mov_b32 a180, a132 + v_accvgpr_mov_b32 a179, a131 + v_accvgpr_mov_b32 a178, a130 + v_accvgpr_mov_b32 a177, a129 + v_accvgpr_mov_b32 a176, a128 + ds_read_b64 v[10:11], v37 + ds_read_b64 v[12:13], v39 + ds_read_b64 v[14:15], v19 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[2:3], v[0:1], a[176:191] + v_accvgpr_mov_b32 a175, a159 + v_accvgpr_mov_b32 a174, a158 + v_accvgpr_mov_b32 a173, a157 + v_accvgpr_mov_b32 a172, a156 + v_accvgpr_mov_b32 a171, a155 + v_accvgpr_mov_b32 a170, a154 + v_accvgpr_mov_b32 a169, a153 + v_accvgpr_mov_b32 a168, a152 + v_accvgpr_mov_b32 a167, a151 + v_accvgpr_mov_b32 a166, a150 + v_accvgpr_mov_b32 a165, a149 + v_accvgpr_mov_b32 a164, a148 + v_accvgpr_mov_b32 a163, a147 + v_accvgpr_mov_b32 a162, a146 + v_accvgpr_mov_b32 a161, a145 + v_accvgpr_mov_b32 a160, a144 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[2:3], v[48:49], a[160:175] + v_accvgpr_write_b32 a159, v35 + v_accvgpr_write_b32 a158, v34 + v_accvgpr_write_b32 a157, v33 + v_accvgpr_write_b32 a156, v32 + v_accvgpr_write_b32 a155, v31 + v_accvgpr_write_b32 a154, v30 + v_accvgpr_write_b32 a153, v29 + v_accvgpr_write_b32 a152, v28 + v_accvgpr_write_b32 a151, v27 + v_accvgpr_write_b32 a150, v26 + v_accvgpr_write_b32 a149, v25 + v_accvgpr_write_b32 a148, v24 + v_accvgpr_write_b32 a147, v23 + v_accvgpr_write_b32 a146, v22 + v_accvgpr_write_b32 a145, v21 + v_accvgpr_write_b32 a144, v20 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[2:3], v[62:63], a[144:159] + v_accvgpr_write_b32 a143, v99 + v_accvgpr_write_b32 a142, v98 + v_accvgpr_write_b32 a141, v97 + v_accvgpr_write_b32 a140, v96 + v_accvgpr_write_b32 a139, v95 + v_accvgpr_write_b32 a138, v94 + v_accvgpr_write_b32 a137, v93 + v_accvgpr_write_b32 a136, v92 + v_accvgpr_write_b32 a135, v91 + v_accvgpr_write_b32 a134, v90 + v_accvgpr_write_b32 a133, v89 + v_accvgpr_write_b32 a132, v88 + v_accvgpr_write_b32 a131, v87 + v_accvgpr_write_b32 a130, v86 + v_accvgpr_write_b32 a129, v85 + v_accvgpr_write_b32 a128, v84 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[2:3], v[70:71], a[128:143] + ds_read_b64 v[2:3], v40 + v_accvgpr_mov_b32 a112, a192 + v_accvgpr_mov_b32 a113, a193 + v_accvgpr_mov_b32 a114, a194 + v_accvgpr_mov_b32 a115, a195 + v_accvgpr_mov_b32 a116, a196 + v_accvgpr_mov_b32 a117, a197 + v_accvgpr_mov_b32 a118, a198 + v_accvgpr_mov_b32 a119, a199 + v_accvgpr_mov_b32 a120, a200 + v_accvgpr_mov_b32 a121, a201 + v_accvgpr_mov_b32 a122, a202 + v_accvgpr_mov_b32 a123, a203 + v_accvgpr_mov_b32 a124, a204 + v_accvgpr_mov_b32 a125, a205 + v_accvgpr_mov_b32 a126, a206 + v_accvgpr_mov_b32 a127, a207 + ds_read_b64 v[16:17], v41 + ds_read_b64 v[18:19], v43 + ds_read_b64 v[20:21], v38 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[2:3], v[0:1], a[112:127] + v_accvgpr_write_b32 a96, v100 + v_accvgpr_write_b32 a97, v101 + v_accvgpr_write_b32 a98, v102 + v_accvgpr_write_b32 a99, v103 + v_accvgpr_write_b32 a100, v104 + v_accvgpr_write_b32 a101, v105 + v_accvgpr_write_b32 a102, v106 + v_accvgpr_write_b32 a103, v107 + v_accvgpr_write_b32 a104, v108 + v_accvgpr_write_b32 a105, v109 + v_accvgpr_write_b32 a106, v110 + v_accvgpr_write_b32 a107, v111 + v_accvgpr_write_b32 a108, v112 + v_accvgpr_write_b32 a109, v113 + v_accvgpr_write_b32 a110, v114 + v_accvgpr_write_b32 a111, v115 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[2:3], v[48:49], a[96:111] + v_accvgpr_write_b32 a80, v116 + v_accvgpr_write_b32 a81, v117 + v_accvgpr_write_b32 a82, v118 + v_accvgpr_write_b32 a83, v119 + v_accvgpr_write_b32 a84, v120 + v_accvgpr_write_b32 a85, v121 + v_accvgpr_write_b32 a86, v122 + v_accvgpr_write_b32 a87, v123 + v_accvgpr_write_b32 a88, v124 + v_accvgpr_write_b32 a89, v125 + v_accvgpr_write_b32 a90, v126 + v_accvgpr_write_b32 a91, v127 + v_accvgpr_write_b32 a92, v128 + v_accvgpr_write_b32 a93, v129 + v_accvgpr_write_b32 a94, v130 + v_accvgpr_write_b32 a95, v131 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[2:3], v[62:63], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[2:3], v[70:71], a[64:79] + ds_read_b64 v[2:3], v44 + v_accvgpr_mov_b32 a63, a31 + v_accvgpr_mov_b32 a62, a30 + v_accvgpr_mov_b32 a61, a29 + v_accvgpr_mov_b32 a60, a28 + v_accvgpr_mov_b32 a59, a27 + v_accvgpr_mov_b32 a58, a26 + v_accvgpr_mov_b32 a57, a25 + v_accvgpr_mov_b32 a56, a24 + v_accvgpr_mov_b32 a55, a23 + v_accvgpr_mov_b32 a54, a22 + v_accvgpr_mov_b32 a53, a21 + v_accvgpr_mov_b32 a52, a20 + v_accvgpr_mov_b32 a51, a19 + v_accvgpr_mov_b32 a50, a18 + v_accvgpr_mov_b32 a49, a17 + v_accvgpr_mov_b32 a48, a16 + ds_read_b64 v[22:23], v45 + ds_read_b64 v[24:25], v46 + ds_read_b64 v[26:27], v42 + s_waitcnt lgkmcnt(3) + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[2:3], v[0:1], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[2:3], v[48:49], a[32:47] + v_accvgpr_write_b32 a16, v132 + v_accvgpr_write_b32 a17, v133 + v_accvgpr_write_b32 a18, v134 + v_accvgpr_write_b32 a19, v135 + v_accvgpr_write_b32 a20, v136 + v_accvgpr_write_b32 a21, v137 + v_accvgpr_write_b32 a22, v138 + v_accvgpr_write_b32 a23, v139 + v_accvgpr_write_b32 a24, v140 + v_accvgpr_write_b32 a25, v141 + v_accvgpr_write_b32 a26, v142 + v_accvgpr_write_b32 a27, v143 + v_accvgpr_write_b32 a28, v144 + v_accvgpr_write_b32 a29, v145 + v_accvgpr_write_b32 a30, v146 + v_accvgpr_write_b32 a31, v147 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[2:3], v[62:63], a[16:31] + v_accvgpr_write_b32 a207, v163 + v_accvgpr_write_b32 a206, v162 + v_accvgpr_write_b32 a205, v161 + v_accvgpr_write_b32 a204, v160 + v_accvgpr_write_b32 a203, v159 + v_accvgpr_write_b32 a202, v158 + v_accvgpr_write_b32 a201, v157 + v_accvgpr_write_b32 a200, v156 + v_accvgpr_write_b32 a199, v155 + v_accvgpr_write_b32 a198, v154 + v_accvgpr_write_b32 a197, v153 + v_accvgpr_write_b32 a196, v152 + v_accvgpr_write_b32 a195, v151 + v_accvgpr_write_b32 a194, v150 + v_accvgpr_write_b32 a193, v149 + v_accvgpr_write_b32 a192, v148 + s_nop 1 + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[2:3], v[70:71], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[4:5], v[50:51], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[4:5], v[56:57], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[4:5], v[64:65], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[4:5], v[72:73], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[10:11], v[50:51], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[10:11], v[56:57], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[10:11], v[64:65], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[10:11], v[72:73], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[16:17], v[50:51], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[16:17], v[56:57], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[16:17], v[64:65], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[16:17], v[72:73], a[64:79] + s_waitcnt lgkmcnt(2) + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[22:23], v[50:51], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[22:23], v[56:57], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[22:23], v[64:65], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[22:23], v[72:73], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[6:7], v[52:53], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[6:7], v[58:59], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[6:7], v[66:67], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[6:7], v[74:75], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[12:13], v[52:53], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[12:13], v[58:59], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[12:13], v[66:67], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[12:13], v[74:75], a[128:143] + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[18:19], v[52:53], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[18:19], v[58:59], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[18:19], v[66:67], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[18:19], v[74:75], a[64:79] + s_waitcnt lgkmcnt(1) + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[24:25], v[52:53], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[24:25], v[58:59], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[24:25], v[66:67], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[24:25], v[74:75], a[192:207] + v_mfma_f32_32x32x16_bf8_bf8 a[0:15], v[14:15], v[54:55], a[0:15] + v_mfma_f32_32x32x16_bf8_bf8 a[240:255], v[14:15], v[60:61], a[240:255] + v_mfma_f32_32x32x16_bf8_bf8 a[224:239], v[14:15], v[68:69], a[224:239] + v_mfma_f32_32x32x16_bf8_bf8 a[208:223], v[14:15], v[76:77], a[208:223] + v_mfma_f32_32x32x16_bf8_bf8 a[176:191], v[20:21], v[54:55], a[176:191] + v_mfma_f32_32x32x16_bf8_bf8 a[160:175], v[20:21], v[60:61], a[160:175] + v_mfma_f32_32x32x16_bf8_bf8 a[144:159], v[20:21], v[68:69], a[144:159] + v_mfma_f32_32x32x16_bf8_bf8 a[128:143], v[20:21], v[76:77], a[128:143] + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x16_bf8_bf8 a[112:127], v[26:27], v[54:55], a[112:127] + v_mfma_f32_32x32x16_bf8_bf8 a[96:111], v[26:27], v[60:61], a[96:111] + v_mfma_f32_32x32x16_bf8_bf8 a[80:95], v[26:27], v[68:69], a[80:95] + v_mfma_f32_32x32x16_bf8_bf8 a[64:79], v[26:27], v[76:77], a[64:79] + v_mfma_f32_32x32x16_bf8_bf8 a[48:63], v[8:9], v[54:55], a[48:63] + v_mfma_f32_32x32x16_bf8_bf8 a[32:47], v[8:9], v[60:61], a[32:47] + v_mfma_f32_32x32x16_bf8_bf8 a[16:31], v[8:9], v[68:69], a[16:31] + v_mfma_f32_32x32x16_bf8_bf8 a[192:207], v[8:9], v[76:77], a[192:207] +.LBB31_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_S2_fNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESC_SC_Li1EEES2_NS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKS2_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSK_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi16ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDaRKS1O_R + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v1, a4 + v_accvgpr_read_b32 v34, a5 + v_accvgpr_read_b32 v0, a6 + v_accvgpr_read_b32 v139, a7 + v_accvgpr_read_b32 v138, a8 + v_accvgpr_read_b32 v137, a9 + v_accvgpr_read_b32 v136, a10 + v_accvgpr_read_b32 v135, a11 + v_accvgpr_read_b32 v134, a12 + v_accvgpr_read_b32 v133, a13 + v_accvgpr_read_b32 v132, a14 + v_accvgpr_read_b32 v131, a15 + v_accvgpr_read_b32 v108, a240 + v_accvgpr_read_b32 v107, a241 + v_accvgpr_read_b32 v106, a242 + v_accvgpr_read_b32 v105, a243 + v_accvgpr_read_b32 v104, a244 + v_accvgpr_read_b32 v103, a245 + v_accvgpr_read_b32 v102, a246 + v_accvgpr_read_b32 v101, a247 + v_accvgpr_read_b32 v100, a248 + v_accvgpr_read_b32 v99, a249 + v_accvgpr_read_b32 v98, a250 + v_accvgpr_read_b32 v97, a251 + v_accvgpr_read_b32 v96, a252 + v_accvgpr_read_b32 v95, a253 + v_accvgpr_read_b32 v94, a254 + v_accvgpr_read_b32 v93, a255 + v_accvgpr_read_b32 v92, a224 + v_accvgpr_read_b32 v91, a225 + v_accvgpr_read_b32 v90, a226 + v_accvgpr_read_b32 v89, a227 + v_accvgpr_read_b32 v88, a228 + v_accvgpr_read_b32 v87, a229 + v_accvgpr_read_b32 v86, a230 + v_accvgpr_read_b32 v85, a231 + v_accvgpr_read_b32 v84, a232 + v_accvgpr_read_b32 v83, a233 + v_accvgpr_read_b32 v82, a234 + v_accvgpr_read_b32 v81, a235 + v_accvgpr_read_b32 v80, a236 + v_accvgpr_read_b32 v79, a237 + v_accvgpr_read_b32 v78, a238 + v_accvgpr_read_b32 v77, a239 + v_accvgpr_read_b32 v76, a208 + v_accvgpr_read_b32 v75, a209 + v_accvgpr_read_b32 v74, a210 + v_accvgpr_read_b32 v73, a211 + v_accvgpr_read_b32 v72, a212 + v_accvgpr_read_b32 v71, a213 + v_accvgpr_read_b32 v70, a214 + v_accvgpr_read_b32 v69, a215 + v_accvgpr_read_b32 v68, a216 + v_accvgpr_read_b32 v67, a217 + v_accvgpr_read_b32 v66, a218 + v_accvgpr_read_b32 v65, a219 + v_accvgpr_read_b32 v64, a220 + v_accvgpr_read_b32 v63, a221 + v_accvgpr_read_b32 v62, a222 + v_accvgpr_read_b32 v61, a223 + v_accvgpr_read_b32 v224, a176 + v_accvgpr_read_b32 v223, a177 + v_accvgpr_read_b32 v222, a178 + v_accvgpr_read_b32 v221, a179 + v_accvgpr_read_b32 v220, a180 + v_accvgpr_read_b32 v219, a181 + v_accvgpr_read_b32 v218, a182 + v_accvgpr_read_b32 v217, a183 + v_accvgpr_read_b32 v216, a184 + v_accvgpr_read_b32 v215, a185 + v_accvgpr_read_b32 v214, a186 + v_accvgpr_read_b32 v213, a187 + v_accvgpr_read_b32 v212, a188 + v_accvgpr_read_b32 v211, a189 + v_accvgpr_read_b32 v210, a190 + v_accvgpr_read_b32 v209, a191 + v_accvgpr_read_b32 v176, a160 + v_accvgpr_read_b32 v175, a161 + v_accvgpr_read_b32 v174, a162 + v_accvgpr_read_b32 v173, a163 + v_accvgpr_read_b32 v172, a164 + v_accvgpr_read_b32 v171, a165 + v_accvgpr_read_b32 v170, a166 + v_accvgpr_read_b32 v169, a167 + v_accvgpr_read_b32 v168, a168 + v_accvgpr_read_b32 v167, a169 + v_accvgpr_read_b32 v166, a170 + v_accvgpr_read_b32 v165, a171 + v_accvgpr_read_b32 v164, a172 + v_accvgpr_read_b32 v163, a173 + v_accvgpr_read_b32 v162, a174 + v_accvgpr_read_b32 v161, a175 + v_accvgpr_read_b32 v160, a144 + v_accvgpr_read_b32 v159, a145 + v_accvgpr_read_b32 v158, a146 + v_accvgpr_read_b32 v157, a147 + v_accvgpr_read_b32 v156, a148 + v_accvgpr_read_b32 v155, a149 + v_accvgpr_read_b32 v154, a150 + v_accvgpr_read_b32 v153, a151 + v_accvgpr_read_b32 v152, a152 + v_accvgpr_read_b32 v151, a153 + v_accvgpr_read_b32 v150, a154 + v_accvgpr_read_b32 v149, a155 + v_accvgpr_read_b32 v148, a156 + v_accvgpr_read_b32 v146, a157 + v_accvgpr_read_b32 v145, a158 + v_accvgpr_read_b32 v144, a159 + v_accvgpr_read_b32 v147, a128 + v_accvgpr_read_b32 v130, a129 + v_accvgpr_read_b32 v129, a130 + v_accvgpr_read_b32 v128, a131 + v_accvgpr_read_b32 v127, a132 + v_accvgpr_read_b32 v126, a133 + v_accvgpr_read_b32 v125, a134 + v_accvgpr_read_b32 v124, a135 + v_accvgpr_read_b32 v123, a136 + v_accvgpr_read_b32 v122, a137 + v_accvgpr_read_b32 v121, a138 + v_accvgpr_read_b32 v120, a139 + v_accvgpr_read_b32 v119, a140 + v_accvgpr_read_b32 v118, a141 + v_accvgpr_read_b32 v117, a142 + v_accvgpr_read_b32 v116, a143 + v_accvgpr_mov_b32 a15, a112 + v_accvgpr_mov_b32 a14, a113 + v_accvgpr_mov_b32 a13, a114 + v_accvgpr_mov_b32 a12, a115 + v_accvgpr_mov_b32 a11, a116 + v_accvgpr_mov_b32 a10, a117 + v_accvgpr_mov_b32 a9, a118 + v_accvgpr_mov_b32 a8, a119 + v_accvgpr_mov_b32 a7, a120 + v_accvgpr_mov_b32 a6, a121 + v_accvgpr_mov_b32 a5, a122 + v_accvgpr_mov_b32 a4, a123 + v_accvgpr_mov_b32 a3, a124 + v_accvgpr_mov_b32 a2, a125 + v_accvgpr_mov_b32 a1, a126 + v_accvgpr_mov_b32 a0, a127 + v_accvgpr_read_b32 v60, a96 + v_accvgpr_read_b32 v59, a97 + v_accvgpr_read_b32 v58, a98 + v_accvgpr_read_b32 v57, a99 + v_accvgpr_read_b32 v56, a100 + v_accvgpr_read_b32 v55, a101 + v_accvgpr_read_b32 v54, a102 + v_accvgpr_read_b32 v53, a103 + v_accvgpr_read_b32 v52, a104 + v_accvgpr_read_b32 v51, a105 + v_accvgpr_read_b32 v24, a106 + v_accvgpr_read_b32 v23, a107 + v_accvgpr_read_b32 v22, a108 + v_accvgpr_read_b32 v21, a109 + v_accvgpr_read_b32 v20, a110 + v_accvgpr_read_b32 v19, a111 + v_accvgpr_read_b32 v115, a80 + v_accvgpr_read_b32 v114, a81 + v_accvgpr_read_b32 v113, a82 + v_accvgpr_read_b32 v112, a83 + v_accvgpr_read_b32 v111, a84 + v_accvgpr_read_b32 v110, a85 + v_accvgpr_read_b32 v109, a86 + v_accvgpr_read_b32 v50, a87 + v_accvgpr_read_b32 v49, a88 + v_accvgpr_read_b32 v48, a89 + v_accvgpr_read_b32 v47, a90 + v_accvgpr_read_b32 v46, a91 + v_accvgpr_read_b32 v45, a92 + v_accvgpr_read_b32 v44, a93 + v_accvgpr_read_b32 v43, a94 + v_accvgpr_read_b32 v42, a95 + v_accvgpr_read_b32 v208, a64 + v_accvgpr_read_b32 v207, a65 + v_accvgpr_read_b32 v206, a66 + v_accvgpr_read_b32 v205, a67 + v_accvgpr_read_b32 v204, a68 + v_accvgpr_read_b32 v203, a69 + v_accvgpr_read_b32 v202, a70 + v_accvgpr_read_b32 v201, a71 + v_accvgpr_read_b32 v200, a72 + v_accvgpr_read_b32 v199, a73 + v_accvgpr_read_b32 v198, a74 + v_accvgpr_read_b32 v197, a75 + v_accvgpr_read_b32 v196, a76 + v_accvgpr_read_b32 v195, a77 + v_accvgpr_read_b32 v194, a78 + v_accvgpr_read_b32 v193, a79 + v_accvgpr_mov_b32 a71, a48 + v_accvgpr_mov_b32 a70, a49 + v_accvgpr_mov_b32 a69, a50 + v_accvgpr_mov_b32 a68, a51 + v_accvgpr_mov_b32 a67, a52 + v_accvgpr_mov_b32 a66, a53 + v_accvgpr_mov_b32 a65, a54 + v_accvgpr_mov_b32 a64, a55 + v_accvgpr_mov_b32 a55, a56 + v_accvgpr_mov_b32 a54, a57 + v_accvgpr_mov_b32 a53, a58 + v_accvgpr_mov_b32 a52, a59 + v_accvgpr_mov_b32 a51, a60 + v_accvgpr_mov_b32 a50, a61 + v_accvgpr_mov_b32 a49, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v41, a32 + v_accvgpr_read_b32 v40, a33 + v_accvgpr_read_b32 v39, a34 + v_accvgpr_read_b32 v38, a35 + v_accvgpr_read_b32 v37, a36 + v_accvgpr_read_b32 v36, a37 + v_accvgpr_read_b32 v35, a38 + v_accvgpr_read_b32 v33, a39 + v_accvgpr_read_b32 v32, a40 + v_accvgpr_read_b32 v31, a41 + v_accvgpr_read_b32 v30, a42 + v_accvgpr_read_b32 v29, a43 + v_accvgpr_read_b32 v28, a44 + v_accvgpr_read_b32 v27, a45 + v_accvgpr_read_b32 v26, a46 + v_accvgpr_read_b32 v25, a47 + v_accvgpr_read_b32 v192, a16 + v_accvgpr_read_b32 v191, a17 + v_accvgpr_read_b32 v190, a18 + v_accvgpr_read_b32 v189, a19 + v_accvgpr_read_b32 v188, a20 + v_accvgpr_read_b32 v187, a21 + v_accvgpr_read_b32 v186, a22 + v_accvgpr_read_b32 v185, a23 + v_accvgpr_read_b32 v184, a24 + v_accvgpr_read_b32 v183, a25 + v_accvgpr_read_b32 v182, a26 + v_accvgpr_read_b32 v181, a27 + v_accvgpr_read_b32 v180, a28 + v_accvgpr_read_b32 v179, a29 + v_accvgpr_read_b32 v178, a30 + v_accvgpr_read_b32 v177, a31 + v_accvgpr_read_b32 v2, a192 + v_accvgpr_read_b32 v3, a193 + v_accvgpr_read_b32 v4, a194 + v_accvgpr_read_b32 v5, a195 + v_accvgpr_read_b32 v6, a196 + v_accvgpr_read_b32 v7, a197 + v_accvgpr_read_b32 v8, a198 + v_accvgpr_read_b32 v9, a199 + v_accvgpr_read_b32 v10, a200 + v_accvgpr_read_b32 v11, a201 + v_accvgpr_read_b32 v12, a202 + v_accvgpr_read_b32 v13, a203 + v_accvgpr_read_b32 v14, a204 + v_accvgpr_read_b32 v15, a205 + v_accvgpr_read_b32 v16, a206 + v_accvgpr_read_b32 v17, a207 + s_add_i32 s2, s5, 0x7fffffff + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v229, 24, v225 + v_and_b32_e32 v226, 7, v225 + v_lshrrev_b32_e32 v18, 3, v225 + v_and_b32_e32 v18, 12, v18 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v252, v143 + v_cvt_f16_f32_e32 v253, v142 + v_cvt_f16_f32_e32 v254, v141 + v_cvt_f16_f32_e32 v255, v140 + v_cvt_f16_f32_e32 v1, v1 + v_cvt_f16_f32_e32 v34, v34 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v245, v139 + v_cvt_f16_f32_e32 v246, v138 + v_cvt_f16_f32_e32 v247, v137 + v_cvt_f16_f32_e32 v248, v136 + v_cvt_f16_f32_e32 v249, v135 + v_cvt_f16_f32_e32 v250, v134 + v_cvt_f16_f32_e32 v251, v133 + v_cvt_f16_f32_e32 v133, v132 + v_cvt_f16_f32_e32 v134, v131 + v_cvt_f16_f32_e32 v135, v224 + v_cvt_f16_f32_e32 v230, v223 + v_cvt_f16_f32_e32 v231, v222 + v_cvt_f16_f32_e32 v232, v221 + v_cvt_f16_f32_e32 v233, v220 + v_cvt_f16_f32_e32 v234, v219 + v_cvt_f16_f32_e32 v235, v218 + v_cvt_f16_f32_e32 v236, v217 + v_cvt_f16_f32_e32 v237, v216 + v_cvt_f16_f32_e32 v238, v215 + v_cvt_f16_f32_e32 v239, v214 + v_cvt_f16_f32_e32 v240, v213 + v_cvt_f16_f32_e32 v241, v212 + v_cvt_f16_f32_e32 v242, v211 + v_cvt_f16_f32_e32 v243, v210 + v_cvt_f16_f32_e32 v244, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v108, v108 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v209, v94 + v_cvt_f16_f32_e32 v210, v93 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v131, v162 + v_cvt_f16_f32_e32 v132, v161 + v_cvt_f16_f32_e32 v163, v92 + v_cvt_f16_f32_e32 v164, v91 + v_cvt_f16_f32_e32 v165, v90 + v_cvt_f16_f32_e32 v166, v89 + v_cvt_f16_f32_e32 v167, v88 + v_cvt_f16_f32_e32 v168, v87 + v_cvt_f16_f32_e32 v169, v86 + v_cvt_f16_f32_e32 v170, v85 + v_cvt_f16_f32_e32 v171, v84 + v_cvt_f16_f32_e32 v172, v83 + v_cvt_f16_f32_e32 v173, v82 + v_cvt_f16_f32_e32 v174, v81 + v_cvt_f16_f32_e32 v175, v80 + v_cvt_f16_f32_e32 v176, v79 + v_cvt_f16_f32_e32 v78, v78 + v_cvt_f16_f32_e32 v77, v77 + v_cvt_f16_f32_e32 v79, v160 + v_cvt_f16_f32_e32 v80, v159 + v_cvt_f16_f32_e32 v81, v158 + v_cvt_f16_f32_e32 v82, v157 + v_cvt_f16_f32_e32 v83, v156 + v_cvt_f16_f32_e32 v84, v155 + v_cvt_f16_f32_e32 v85, v154 + v_cvt_f16_f32_e32 v86, v153 + v_cvt_f16_f32_e32 v87, v152 + v_cvt_f16_f32_e32 v88, v151 + v_cvt_f16_f32_e32 v89, v150 + v_cvt_f16_f32_e32 v90, v149 + v_cvt_f16_f32_e32 v91, v148 + v_cvt_f16_f32_e32 v92, v146 + v_cvt_f16_f32_e32 v93, v145 + v_cvt_f16_f32_e32 v94, v144 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v74, v74 + v_cvt_f16_f32_e32 v73, v73 + v_cvt_f16_f32_e32 v72, v72 + v_cvt_f16_f32_e32 v136, v71 + v_cvt_f16_f32_e32 v137, v70 + v_cvt_f16_f32_e32 v138, v69 + v_cvt_f16_f32_e32 v139, v68 + v_cvt_f16_f32_e32 v140, v67 + v_cvt_f16_f32_e32 v141, v66 + v_cvt_f16_f32_e32 v142, v65 + v_cvt_f16_f32_e32 v143, v64 + v_cvt_f16_f32_e32 v144, v63 + v_cvt_f16_f32_e32 v145, v62 + v_cvt_f16_f32_e32 v146, v61 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v130 + v_cvt_f16_f32_e32 v149, v129 + v_cvt_f16_f32_e32 v150, v128 + v_cvt_f16_f32_e32 v151, v127 + v_cvt_f16_f32_e32 v152, v126 + v_cvt_f16_f32_e32 v153, v125 + v_cvt_f16_f32_e32 v154, v124 + v_cvt_f16_f32_e32 v155, v123 + v_cvt_f16_f32_e32 v156, v122 + v_cvt_f16_f32_e32 v157, v121 + v_cvt_f16_f32_e32 v158, v120 + v_cvt_f16_f32_e32 v159, v119 + v_cvt_f16_f32_e32 v160, v118 + v_cvt_f16_f32_e32 v161, v117 + v_cvt_f16_f32_e32 v162, v116 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v61, v207 + v_accvgpr_write_b32 a16, v61 + v_cvt_f16_f32_e32 v61, v206 + v_accvgpr_write_b32 a17, v61 + v_cvt_f16_f32_e32 v61, v205 + v_accvgpr_write_b32 a18, v61 + v_cvt_f16_f32_e32 v61, v204 + v_accvgpr_write_b32 a19, v61 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v61, v198 + v_cvt_f16_f32_e32 v62, v197 + v_cvt_f16_f32_e32 v63, v196 + v_cvt_f16_f32_e32 v64, v195 + v_cvt_f16_f32_e32 v65, v194 + v_cvt_f16_f32_e32 v66, v193 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v116, v3 + v_cvt_f16_f32_e32 v117, v4 + v_cvt_f16_f32_e32 v118, v5 + v_cvt_f16_f32_e32 v119, v6 + v_cvt_f16_f32_e32 v120, v7 + v_cvt_f16_f32_e32 v121, v8 + v_cvt_f16_f32_e32 v122, v9 + v_cvt_f16_f32_e32 v123, v10 + v_cvt_f16_f32_e32 v124, v11 + v_cvt_f16_f32_e32 v125, v12 + v_cvt_f16_f32_e32 v126, v13 + v_cvt_f16_f32_e32 v127, v14 + v_cvt_f16_f32_e32 v128, v15 + v_cvt_f16_f32_e32 v129, v16 + v_cvt_f16_f32_e32 v130, v17 + v_cvt_f16_f32_e32 v193, v115 + v_cvt_f16_f32_e32 v194, v114 + v_cvt_f16_f32_e32 v195, v113 + v_cvt_f16_f32_e32 v196, v112 + v_cvt_f16_f32_e32 v197, v111 + v_cvt_f16_f32_e32 v198, v110 + v_cvt_f16_f32_e32 v199, v109 + v_cvt_f16_f32_e32 v200, v50 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v47, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v43, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v192 + v_cvt_f16_f32_e32 v50, v191 + v_cvt_f16_f32_e32 v109, v190 + v_cvt_f16_f32_e32 v110, v189 + v_cvt_f16_f32_e32 v111, v188 + v_cvt_f16_f32_e32 v112, v187 + v_cvt_f16_f32_e32 v113, v186 + v_cvt_f16_f32_e32 v114, v185 + v_cvt_f16_f32_e32 v115, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v177, v177 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v3, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v24 + v_cvt_f16_f32_e32 v13, v23 + v_cvt_f16_f32_e32 v14, v22 + v_cvt_f16_f32_e32 v15, v21 + v_cvt_f16_f32_e32 v16, v20 + v_cvt_f16_f32_e32 v17, v19 + v_cvt_f16_f32_e32 v51, v41 + v_cvt_f16_f32_e32 v52, v40 + v_cvt_f16_f32_e32 v53, v39 + v_cvt_f16_f32_e32 v54, v38 + v_cvt_f16_f32_e32 v55, v37 + v_cvt_f16_f32_e32 v56, v36 + v_cvt_f16_f32_e32 v57, v35 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_cvt_f16_f32_e32 v25, v25 + v_lshlrev_b32_e32 v21, 1, v226 + v_lshlrev_b32_e32 v20, 1, v229 + v_lshrrev_b32_e32 v19, 1, v225 + s_cbranch_scc1 .LBB31_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB31_14 +.LBB31_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SB_fS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEESB_NS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISB_SB_NS_5tupleIJEEEfDF16_SP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB31_13: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_or_b32_e32 v22, s5, v18 + v_lshl_or_b32 v22, v22, 7, v21 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v22, v20, s2 + ds_write_b16 v22, v252 + ds_write_b16 v22, v253 offset:128 + ds_write_b16 v22, v254 offset:256 + ds_write_b16 v22, v255 offset:384 + ds_write_b16 v22, v1 offset:1024 + ds_write_b16 v22, v34 offset:1152 + ds_write_b16 v22, v0 offset:1280 + ds_write_b16 v22, v245 offset:1408 + ds_write_b16 v22, v246 offset:2048 + ds_write_b16 v22, v247 offset:2176 + ds_write_b16 v22, v248 offset:2304 + ds_write_b16 v22, v249 offset:2432 + ds_write_b16 v22, v250 offset:3072 + ds_write_b16 v22, v251 offset:3200 + ds_write_b16 v22, v133 offset:3328 + ds_write_b16 v22, v134 offset:3456 + ds_write_b16 v22, v135 offset:8192 + ds_write_b16 v22, v230 offset:8320 + ds_write_b16 v22, v231 offset:8448 + ds_write_b16 v22, v232 offset:8576 + ds_write_b16 v22, v233 offset:9216 + ds_write_b16 v22, v234 offset:9344 + ds_write_b16 v22, v235 offset:9472 + ds_write_b16 v22, v236 offset:9600 + ds_write_b16 v22, v237 offset:10240 + ds_write_b16 v22, v238 offset:10368 + ds_write_b16 v22, v239 offset:10496 + ds_write_b16 v22, v240 offset:10624 + ds_write_b16 v22, v241 offset:11264 + ds_write_b16 v22, v242 offset:11392 + ds_write_b16 v22, v243 offset:11520 + ds_write_b16 v22, v244 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v23, 60, v19 + v_add_u32_e32 v24, s2, v23 + v_and_b32_e32 v31, 56, v228 + v_lshlrev_b32_e32 v23, 7, v24 + v_lshl_or_b32 v23, v31, 1, v23 + v_add_u32_e32 v32, s20, v24 + v_or_b32_e32 v24, s21, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v32, s16 + v_add_u32_e32 v33, v31, v24 + v_lshlrev_b32_e32 v35, 1, v33 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v35, s[0:3], 12 offen + v_add_u32_e32 v33, s16, v33 + v_lshlrev_b32_e32 v35, 1, v33 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v35, s[0:3], 12 offen + v_add_u32_e32 v33, s16, v33 + v_lshlrev_b32_e32 v35, 1, v33 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v35, s[0:3], 12 offen + v_add_lshl_u32 v33, v33, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v33, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v108 + ds_write_b16 v22, v107 offset:128 + ds_write_b16 v22, v106 offset:256 + ds_write_b16 v22, v105 offset:384 + ds_write_b16 v22, v104 offset:1024 + ds_write_b16 v22, v103 offset:1152 + ds_write_b16 v22, v102 offset:1280 + ds_write_b16 v22, v101 offset:1408 + ds_write_b16 v22, v100 offset:2048 + ds_write_b16 v22, v99 offset:2176 + ds_write_b16 v22, v98 offset:2304 + ds_write_b16 v22, v97 offset:2432 + ds_write_b16 v22, v96 offset:3072 + ds_write_b16 v22, v95 offset:3200 + ds_write_b16 v22, v209 offset:3328 + ds_write_b16 v22, v210 offset:3456 + ds_write_b16 v22, v211 offset:8192 + ds_write_b16 v22, v212 offset:8320 + ds_write_b16 v22, v213 offset:8448 + ds_write_b16 v22, v214 offset:8576 + ds_write_b16 v22, v215 offset:9216 + ds_write_b16 v22, v216 offset:9344 + ds_write_b16 v22, v217 offset:9472 + ds_write_b16 v22, v218 offset:9600 + ds_write_b16 v22, v219 offset:10240 + ds_write_b16 v22, v220 offset:10368 + ds_write_b16 v22, v221 offset:10496 + ds_write_b16 v22, v222 offset:10624 + ds_write_b16 v22, v223 offset:11264 + ds_write_b16 v22, v224 offset:11392 + ds_write_b16 v22, v131 offset:11520 + ds_write_b16 v22, v132 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v33, 64, v24 + v_add_u32_e32 v35, v31, v33 + v_lshlrev_b32_e32 v40, 1, v35 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v40, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v40, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v40, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v40, s[0:3], 12 offen + v_add_u32_e32 v35, s16, v35 + v_lshlrev_b32_e32 v36, 1, v35 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v35, s16, v35 + v_lshlrev_b32_e32 v36, 1, v35 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v35, v35, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v35, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v163 + ds_write_b16 v22, v164 offset:128 + ds_write_b16 v22, v165 offset:256 + ds_write_b16 v22, v166 offset:384 + ds_write_b16 v22, v167 offset:1024 + ds_write_b16 v22, v168 offset:1152 + ds_write_b16 v22, v169 offset:1280 + ds_write_b16 v22, v170 offset:1408 + ds_write_b16 v22, v171 offset:2048 + ds_write_b16 v22, v172 offset:2176 + ds_write_b16 v22, v173 offset:2304 + ds_write_b16 v22, v174 offset:2432 + ds_write_b16 v22, v175 offset:3072 + ds_write_b16 v22, v176 offset:3200 + ds_write_b16 v22, v78 offset:3328 + ds_write_b16 v22, v77 offset:3456 + ds_write_b16 v22, v79 offset:8192 + ds_write_b16 v22, v80 offset:8320 + ds_write_b16 v22, v81 offset:8448 + ds_write_b16 v22, v82 offset:8576 + ds_write_b16 v22, v83 offset:9216 + ds_write_b16 v22, v84 offset:9344 + ds_write_b16 v22, v85 offset:9472 + ds_write_b16 v22, v86 offset:9600 + ds_write_b16 v22, v87 offset:10240 + ds_write_b16 v22, v88 offset:10368 + ds_write_b16 v22, v89 offset:10496 + ds_write_b16 v22, v90 offset:10624 + ds_write_b16 v22, v91 offset:11264 + ds_write_b16 v22, v92 offset:11392 + ds_write_b16 v22, v93 offset:11520 + ds_write_b16 v22, v94 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v35, 0x80, v24 + v_add_u32_e32 v40, v31, v35 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v41, s[0:3], 12 offen + v_add_u32_e32 v36, s16, v40 + v_lshlrev_b32_e32 v37, 1, v36 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v37, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v37, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v37, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v37, s[0:3], 12 offen + v_add_u32_e32 v36, s16, v36 + v_lshlrev_b32_e32 v37, 1, v36 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v37, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v37, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v37, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v37, s[0:3], 12 offen + v_add_lshl_u32 v36, v36, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v36, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v76 + ds_write_b16 v22, v75 offset:128 + ds_write_b16 v22, v74 offset:256 + ds_write_b16 v22, v73 offset:384 + ds_write_b16 v22, v72 offset:1024 + ds_write_b16 v22, v136 offset:1152 + ds_write_b16 v22, v137 offset:1280 + ds_write_b16 v22, v138 offset:1408 + ds_write_b16 v22, v139 offset:2048 + ds_write_b16 v22, v140 offset:2176 + ds_write_b16 v22, v141 offset:2304 + ds_write_b16 v22, v142 offset:2432 + ds_write_b16 v22, v143 offset:3072 + ds_write_b16 v22, v144 offset:3200 + ds_write_b16 v22, v145 offset:3328 + ds_write_b16 v22, v146 offset:3456 + ds_write_b16 v22, v147 offset:8192 + ds_write_b16 v22, v148 offset:8320 + ds_write_b16 v22, v149 offset:8448 + ds_write_b16 v22, v150 offset:8576 + ds_write_b16 v22, v151 offset:9216 + ds_write_b16 v22, v152 offset:9344 + ds_write_b16 v22, v153 offset:9472 + ds_write_b16 v22, v154 offset:9600 + ds_write_b16 v22, v155 offset:10240 + ds_write_b16 v22, v156 offset:10368 + ds_write_b16 v22, v157 offset:10496 + ds_write_b16 v22, v158 offset:10624 + ds_write_b16 v22, v159 offset:11264 + ds_write_b16 v22, v160 offset:11392 + ds_write_b16 v22, v161 offset:11520 + ds_write_b16 v22, v162 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v40, 0xc0, v24 + v_add_u32_e32 v31, v31, v40 + v_lshlrev_b32_e32 v41, 1, v31 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v41, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v36, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v36, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, a16 offset:128 + ds_write_b16 v22, a17 offset:256 + ds_write_b16 v22, a18 offset:384 + ds_write_b16 v22, a19 offset:1024 + ds_write_b16 v22, v71 offset:1152 + ds_write_b16 v22, v70 offset:1280 + ds_write_b16 v22, v69 offset:1408 + ds_write_b16 v22, v68 offset:2048 + ds_write_b16 v22, v67 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v116 offset:8320 + ds_write_b16 v22, v117 offset:8448 + ds_write_b16 v22, v118 offset:8576 + ds_write_b16 v22, v119 offset:9216 + ds_write_b16 v22, v120 offset:9344 + ds_write_b16 v22, v121 offset:9472 + ds_write_b16 v22, v122 offset:9600 + ds_write_b16 v22, v123 offset:10240 + ds_write_b16 v22, v124 offset:10368 + ds_write_b16 v22, v125 offset:10496 + ds_write_b16 v22, v126 offset:10624 + ds_write_b16 v22, v127 offset:11264 + ds_write_b16 v22, v128 offset:11392 + ds_write_b16 v22, v129 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v32 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v32, v31, v40 + v_lshlrev_b32_e32 v40, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v40, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v40, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v40, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v40, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v36, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v36, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v36, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v36, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v36, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v36, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v36, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v193 + ds_write_b16 v22, v194 offset:128 + ds_write_b16 v22, v195 offset:256 + ds_write_b16 v22, v196 offset:384 + ds_write_b16 v22, v197 offset:1024 + ds_write_b16 v22, v198 offset:1152 + ds_write_b16 v22, v199 offset:1280 + ds_write_b16 v22, v200 offset:1408 + ds_write_b16 v22, v201 offset:2048 + ds_write_b16 v22, v202 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v48 offset:3456 + ds_write_b16 v22, v49 offset:8192 + ds_write_b16 v22, v50 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v114 offset:9600 + ds_write_b16 v22, v115 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, v31, v35 + v_lshlrev_b32_e32 v35, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v35, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v35, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v35, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v35, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v35, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v35, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v35, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v35, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v51 offset:8192 + ds_write_b16 v22, v52 offset:8320 + ds_write_b16 v22, v53 offset:8448 + ds_write_b16 v22, v54 offset:8576 + ds_write_b16 v22, v55 offset:9216 + ds_write_b16 v22, v56 offset:9344 + ds_write_b16 v22, v57 offset:9472 + ds_write_b16 v22, v58 offset:9600 + ds_write_b16 v22, v59 offset:10240 + ds_write_b16 v22, v60 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v32, v31, v33 + v_lshlrev_b32_e32 v33, 1, v32 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:3456 + v_accvgpr_read_b32 v32, a71 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8192 + v_accvgpr_read_b32 v32, a70 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8320 + v_accvgpr_read_b32 v32, a69 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8448 + v_accvgpr_read_b32 v32, a68 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:8576 + v_accvgpr_read_b32 v32, a67 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9216 + v_accvgpr_read_b32 v32, a66 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9344 + v_accvgpr_read_b32 v32, a65 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9472 + v_accvgpr_read_b32 v32, a64 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:9600 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10240 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10368 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10496 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:10624 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11264 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11392 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11520 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v22, v32 offset:11648 + v_add_u32_e32 v22, v31, v24 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v24, 1, v22 + ds_read_b128 v[36:39], v23 + ds_read_b128 v[184:187], v23 offset:128 + ds_read_b128 v[188:191], v23 offset:256 + ds_read_b128 v[204:207], v23 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v184, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v185, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v186, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v187, v23, s[0:3], 12 offen + v_add_u32_e32 v22, s16, v22 + v_lshlrev_b32_e32 v23, 1, v22 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v23, s[0:3], 12 offen + v_add_lshl_u32 v22, v22, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v22, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v22, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v22, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v22, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB31_12 +.LBB31_14: + v_readfirstlane_b32 s2, v227 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_or_b32_e32 v18, s5, v18 + s_barrier + v_lshl_or_b32 v18, v18, 7, v21 + s_and_b32 s2, s2, 64 + v_add3_u32 v22, v18, v20, s2 + ds_write_b16 v22, v252 + ds_write_b16 v22, v253 offset:128 + ds_write_b16 v22, v254 offset:256 + ds_write_b16 v22, v255 offset:384 + ds_write_b16 v22, v1 offset:1024 + ds_write_b16 v22, v34 offset:1152 + ds_write_b16 v22, v0 offset:1280 + ds_write_b16 v22, v245 offset:1408 + ds_write_b16 v22, v246 offset:2048 + ds_write_b16 v22, v247 offset:2176 + ds_write_b16 v22, v248 offset:2304 + ds_write_b16 v22, v249 offset:2432 + ds_write_b16 v22, v250 offset:3072 + ds_write_b16 v22, v251 offset:3200 + ds_write_b16 v22, v133 offset:3328 + ds_write_b16 v22, v134 offset:3456 + ds_write_b16 v22, v135 offset:8192 + ds_write_b16 v22, v230 offset:8320 + ds_write_b16 v22, v231 offset:8448 + ds_write_b16 v22, v232 offset:8576 + ds_write_b16 v22, v233 offset:9216 + ds_write_b16 v22, v234 offset:9344 + ds_write_b16 v22, v235 offset:9472 + ds_write_b16 v22, v236 offset:9600 + ds_write_b16 v22, v237 offset:10240 + ds_write_b16 v22, v238 offset:10368 + ds_write_b16 v22, v239 offset:10496 + ds_write_b16 v22, v240 offset:10624 + ds_write_b16 v22, v241 offset:11264 + ds_write_b16 v22, v242 offset:11392 + ds_write_b16 v22, v243 offset:11520 + ds_write_b16 v22, v244 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v228 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 60, v19 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v23, v0, 1, v18 + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[184:187], v23 offset:384 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v24, s21, v0 + v_mul_lo_u32 v0, v1, s16 + v_add_u32_e32 v31, v0, v24 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v40, 1, v31 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v40, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v31 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[184:187], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v108 + ds_write_b16 v22, v107 offset:128 + ds_write_b16 v22, v106 offset:256 + ds_write_b16 v22, v105 offset:384 + ds_write_b16 v22, v104 offset:1024 + ds_write_b16 v22, v103 offset:1152 + ds_write_b16 v22, v102 offset:1280 + ds_write_b16 v22, v101 offset:1408 + ds_write_b16 v22, v100 offset:2048 + ds_write_b16 v22, v99 offset:2176 + ds_write_b16 v22, v98 offset:2304 + ds_write_b16 v22, v97 offset:2432 + ds_write_b16 v22, v96 offset:3072 + ds_write_b16 v22, v95 offset:3200 + ds_write_b16 v22, v209 offset:3328 + ds_write_b16 v22, v210 offset:3456 + ds_write_b16 v22, v211 offset:8192 + ds_write_b16 v22, v212 offset:8320 + ds_write_b16 v22, v213 offset:8448 + ds_write_b16 v22, v214 offset:8576 + ds_write_b16 v22, v215 offset:9216 + ds_write_b16 v22, v216 offset:9344 + ds_write_b16 v22, v217 offset:9472 + ds_write_b16 v22, v218 offset:9600 + ds_write_b16 v22, v219 offset:10240 + ds_write_b16 v22, v220 offset:10368 + ds_write_b16 v22, v221 offset:10496 + ds_write_b16 v22, v222 offset:10624 + ds_write_b16 v22, v223 offset:11264 + ds_write_b16 v22, v224 offset:11392 + ds_write_b16 v22, v131 offset:11520 + ds_write_b16 v22, v132 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[96:99], v23 offset:384 + v_or_b32_e32 v31, 64, v24 + v_add_u32_e32 v40, v0, v31 + v_lshlrev_b32_e32 v41, 1, v40 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v41, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v40 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[96:99], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v163 + ds_write_b16 v22, v164 offset:128 + ds_write_b16 v22, v165 offset:256 + ds_write_b16 v22, v166 offset:384 + ds_write_b16 v22, v167 offset:1024 + ds_write_b16 v22, v168 offset:1152 + ds_write_b16 v22, v169 offset:1280 + ds_write_b16 v22, v170 offset:1408 + ds_write_b16 v22, v171 offset:2048 + ds_write_b16 v22, v172 offset:2176 + ds_write_b16 v22, v173 offset:2304 + ds_write_b16 v22, v174 offset:2432 + ds_write_b16 v22, v175 offset:3072 + ds_write_b16 v22, v176 offset:3200 + ds_write_b16 v22, v78 offset:3328 + ds_write_b16 v22, v77 offset:3456 + ds_write_b16 v22, v79 offset:8192 + ds_write_b16 v22, v80 offset:8320 + ds_write_b16 v22, v81 offset:8448 + ds_write_b16 v22, v82 offset:8576 + ds_write_b16 v22, v83 offset:9216 + ds_write_b16 v22, v84 offset:9344 + ds_write_b16 v22, v85 offset:9472 + ds_write_b16 v22, v86 offset:9600 + ds_write_b16 v22, v87 offset:10240 + ds_write_b16 v22, v88 offset:10368 + ds_write_b16 v22, v89 offset:10496 + ds_write_b16 v22, v90 offset:10624 + ds_write_b16 v22, v91 offset:11264 + ds_write_b16 v22, v92 offset:11392 + ds_write_b16 v22, v93 offset:11520 + ds_write_b16 v22, v94 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[78:81], v23 offset:384 + v_or_b32_e32 v40, 0x80, v24 + v_add_u32_e32 v41, v0, v40 + v_lshlrev_b32_e32 v77, 1, v41 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v77, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v18, s16, v41 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v19, s[0:3], 0 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 1, v18 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v19, s[0:3], 0 offen + v_add_lshl_u32 v18, v18, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v18, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v76 + ds_write_b16 v22, v75 offset:128 + ds_write_b16 v22, v74 offset:256 + ds_write_b16 v22, v73 offset:384 + ds_write_b16 v22, v72 offset:1024 + ds_write_b16 v22, v136 offset:1152 + ds_write_b16 v22, v137 offset:1280 + ds_write_b16 v22, v138 offset:1408 + ds_write_b16 v22, v139 offset:2048 + ds_write_b16 v22, v140 offset:2176 + ds_write_b16 v22, v141 offset:2304 + ds_write_b16 v22, v142 offset:2432 + ds_write_b16 v22, v143 offset:3072 + ds_write_b16 v22, v144 offset:3200 + ds_write_b16 v22, v145 offset:3328 + ds_write_b16 v22, v146 offset:3456 + ds_write_b16 v22, v147 offset:8192 + ds_write_b16 v22, v148 offset:8320 + ds_write_b16 v22, v149 offset:8448 + ds_write_b16 v22, v150 offset:8576 + ds_write_b16 v22, v151 offset:9216 + ds_write_b16 v22, v152 offset:9344 + ds_write_b16 v22, v153 offset:9472 + ds_write_b16 v22, v154 offset:9600 + ds_write_b16 v22, v155 offset:10240 + ds_write_b16 v22, v156 offset:10368 + ds_write_b16 v22, v157 offset:10496 + ds_write_b16 v22, v158 offset:10624 + ds_write_b16 v22, v159 offset:11264 + ds_write_b16 v22, v160 offset:11392 + ds_write_b16 v22, v161 offset:11520 + ds_write_b16 v22, v162 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[78:81], v23 offset:384 + v_or_b32_e32 v41, 0xc0, v24 + v_add_u32_e32 v0, v0, v41 + v_lshlrev_b32_e32 v75, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v75, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v18, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v18, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v208 + ds_write_b16 v22, a16 offset:128 + ds_write_b16 v22, a17 offset:256 + ds_write_b16 v22, a18 offset:384 + ds_write_b16 v22, a19 offset:1024 + ds_write_b16 v22, v71 offset:1152 + ds_write_b16 v22, v70 offset:1280 + ds_write_b16 v22, v69 offset:1408 + ds_write_b16 v22, v68 offset:2048 + ds_write_b16 v22, v67 offset:2176 + ds_write_b16 v22, v61 offset:2304 + ds_write_b16 v22, v62 offset:2432 + ds_write_b16 v22, v63 offset:3072 + ds_write_b16 v22, v64 offset:3200 + ds_write_b16 v22, v65 offset:3328 + ds_write_b16 v22, v66 offset:3456 + ds_write_b16 v22, v2 offset:8192 + ds_write_b16 v22, v116 offset:8320 + ds_write_b16 v22, v117 offset:8448 + ds_write_b16 v22, v118 offset:8576 + ds_write_b16 v22, v119 offset:9216 + ds_write_b16 v22, v120 offset:9344 + ds_write_b16 v22, v121 offset:9472 + ds_write_b16 v22, v122 offset:9600 + ds_write_b16 v22, v123 offset:10240 + ds_write_b16 v22, v124 offset:10368 + ds_write_b16 v22, v125 offset:10496 + ds_write_b16 v22, v126 offset:10624 + ds_write_b16 v22, v127 offset:11264 + ds_write_b16 v22, v128 offset:11392 + ds_write_b16 v22, v129 offset:11520 + ds_write_b16 v22, v130 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[62:65], v23 offset:384 + v_add_u32_e32 v0, 0x80, v1 + v_mul_lo_u32 v61, v0, s16 + v_add_u32_e32 v0, v61, v41 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v193 + ds_write_b16 v22, v194 offset:128 + ds_write_b16 v22, v195 offset:256 + ds_write_b16 v22, v196 offset:384 + ds_write_b16 v22, v197 offset:1024 + ds_write_b16 v22, v198 offset:1152 + ds_write_b16 v22, v199 offset:1280 + ds_write_b16 v22, v200 offset:1408 + ds_write_b16 v22, v201 offset:2048 + ds_write_b16 v22, v202 offset:2176 + ds_write_b16 v22, v47 offset:2304 + ds_write_b16 v22, v46 offset:2432 + ds_write_b16 v22, v45 offset:3072 + ds_write_b16 v22, v44 offset:3200 + ds_write_b16 v22, v43 offset:3328 + ds_write_b16 v22, v48 offset:3456 + ds_write_b16 v22, v49 offset:8192 + ds_write_b16 v22, v50 offset:8320 + ds_write_b16 v22, v109 offset:8448 + ds_write_b16 v22, v110 offset:8576 + ds_write_b16 v22, v111 offset:9216 + ds_write_b16 v22, v112 offset:9344 + ds_write_b16 v22, v113 offset:9472 + ds_write_b16 v22, v114 offset:9600 + ds_write_b16 v22, v115 offset:10240 + ds_write_b16 v22, v183 offset:10368 + ds_write_b16 v22, v182 offset:10496 + ds_write_b16 v22, v181 offset:10624 + ds_write_b16 v22, v180 offset:11264 + ds_write_b16 v22, v179 offset:11392 + ds_write_b16 v22, v178 offset:11520 + ds_write_b16 v22, v177 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v23 + ds_read_b128 v[32:35], v23 offset:128 + ds_read_b128 v[36:39], v23 offset:256 + ds_read_b128 v[44:47], v23 offset:384 + v_add_u32_e32 v0, v61, v40 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[44:47], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v22, v42 + ds_write_b16 v22, v3 offset:128 + ds_write_b16 v22, v4 offset:256 + ds_write_b16 v22, v5 offset:384 + ds_write_b16 v22, v6 offset:1024 + ds_write_b16 v22, v7 offset:1152 + ds_write_b16 v22, v8 offset:1280 + ds_write_b16 v22, v9 offset:1408 + ds_write_b16 v22, v10 offset:2048 + ds_write_b16 v22, v11 offset:2176 + ds_write_b16 v22, v12 offset:2304 + ds_write_b16 v22, v13 offset:2432 + ds_write_b16 v22, v14 offset:3072 + ds_write_b16 v22, v15 offset:3200 + ds_write_b16 v22, v16 offset:3328 + ds_write_b16 v22, v17 offset:3456 + ds_write_b16 v22, v51 offset:8192 + ds_write_b16 v22, v52 offset:8320 + ds_write_b16 v22, v53 offset:8448 + ds_write_b16 v22, v54 offset:8576 + ds_write_b16 v22, v55 offset:9216 + ds_write_b16 v22, v56 offset:9344 + ds_write_b16 v22, v57 offset:9472 + ds_write_b16 v22, v58 offset:9600 + ds_write_b16 v22, v59 offset:10240 + ds_write_b16 v22, v60 offset:10368 + ds_write_b16 v22, v30 offset:10496 + ds_write_b16 v22, v29 offset:10624 + ds_write_b16 v22, v28 offset:11264 + ds_write_b16 v22, v27 offset:11392 + ds_write_b16 v22, v26 offset:11520 + ds_write_b16 v22, v25 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v61, v31 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a71 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a70 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a69 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a68 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a67 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a66 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v25, a65 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a64 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a55 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a54 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a53 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a52 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v31, a51 + v_cvt_f16_f32_e32 v31, v31 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + v_accvgpr_read_b32 v33, a49 + v_cvt_f16_f32_e32 v33, v33 + v_accvgpr_read_b32 v34, a48 + v_cvt_f16_f32_e32 v34, v34 + ds_write_b16 v22, v0 + ds_write_b16 v22, v1 offset:128 + ds_write_b16 v22, v2 offset:256 + ds_write_b16 v22, v3 offset:384 + ds_write_b16 v22, v4 offset:1024 + ds_write_b16 v22, v5 offset:1152 + ds_write_b16 v22, v6 offset:1280 + ds_write_b16 v22, v7 offset:1408 + ds_write_b16 v22, v8 offset:2048 + ds_write_b16 v22, v9 offset:2176 + ds_write_b16 v22, v10 offset:2304 + ds_write_b16 v22, v11 offset:2432 + ds_write_b16 v22, v12 offset:3072 + ds_write_b16 v22, v13 offset:3200 + ds_write_b16 v22, v14 offset:3328 + ds_write_b16 v22, v15 offset:3456 + ds_write_b16 v22, v16 offset:8192 + ds_write_b16 v22, v17 offset:8320 + ds_write_b16 v22, v18 offset:8448 + ds_write_b16 v22, v19 offset:8576 + ds_write_b16 v22, v20 offset:9216 + ds_write_b16 v22, v21 offset:9344 + ds_write_b16 v22, v25 offset:9472 + ds_write_b16 v22, v26 offset:9600 + ds_write_b16 v22, v27 offset:10240 + ds_write_b16 v22, v28 offset:10368 + ds_write_b16 v22, v29 offset:10496 + ds_write_b16 v22, v30 offset:10624 + ds_write_b16 v22, v31 offset:11264 + ds_write_b16 v22, v32 offset:11392 + ds_write_b16 v22, v33 offset:11520 + ds_write_b16 v22, v34 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v23 + ds_read_b128 v[4:7], v23 offset:128 + ds_read_b128 v[8:11], v23 offset:256 + ds_read_b128 v[12:15], v23 offset:384 + v_add_u32_e32 v16, v61, v24 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 32768 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end31: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end31-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 29 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDU8_SC_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESG_SG_Li1EEESC_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemISC_SC_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 29728 +; TotalNumSgprs: 35 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 32768 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v6, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v6 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB32_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v6, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB32_5 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v2, v6, s7 + v_ashrrev_i32_e32 v3, 31, v2 + s_waitcnt lgkmcnt(0) + v_lshl_add_u64 v[2:3], s[8:9], 0, v[2:3] + v_mov_b32_e32 v1, 0 + v_mov_b32_e32 v4, v0 +.LBB32_3: ; =>This Inner Loop Header: Depth=1 + global_load_ubyte v7, v[2:3], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[4:5] + global_load_ubyte v5, v[8:9], off + s_add_i32 s6, s6, -1 + s_waitcnt vmcnt(1) + v_cvt_f32_bf8_sdwa v7, v7 src0_sel:BYTE_0 + s_waitcnt vmcnt(0) + v_cvt_f32_bf8_sdwa v5, v5 src0_sel:BYTE_0 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s6, 0 + v_fmac_f32_e32 v1, v7, v5 + s_cbranch_scc0 .LBB32_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v1 +.LBB32_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v6, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB32_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end32: + .size _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end32-_ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDU8_S1_fDF16_NS_13tensor_layout4gemm8RowMajorES4_S4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 440 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v1, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v1 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s12, s10, s15 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s22, s3 + s_add_u32 s2, s2, s3 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v1 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v2, -1, 0 + s_cbranch_scc0 .LBB33_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + v_mbcnt_hi_u32_b32 v1, -1, v2 + s_lshr_b32 s19, s15, 2 + v_and_b32_e32 v27, 15, v1 + s_and_b32 s11, s19, 0x3ffffff0 + v_lshrrev_b32_e32 v3, 2, v1 + v_and_b32_e32 v3, 28, v3 + v_lshl_or_b32 v4, v27, 4, s20 + v_add_u32_e32 v9, s11, v3 + v_mad_u64_u32 v[4:5], s[24:25], v9, s7, v[4:5] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[10:13], v4, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v4 + buffer_load_dwordx4 v[14:17], v3, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[18:21], v3, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[22:25], v3, s[8:11], 0 offen + s_mov_b32 s23, 0x3020504 + s_mov_b32 s26, 0x5010400 + s_mov_b32 s27, 0x5040100 + s_mov_b32 s28, 0x7060302 + s_mov_b32 s29, 0x7030602 + v_and_b32_e32 v30, 31, v1 + v_lshrrev_b32_e32 v31, 5, v1 + v_lshlrev_b32_e32 v3, 4, v1 + s_and_b32 s24, s15, 0xffffffc0 + v_and_b32_e32 v4, 0x7c, v1 + s_lshr_b32 s25, s15, 1 + v_lshlrev_b32_e32 v5, 3, v1 + s_mov_b32 s15, s11 + s_and_b32 s19, s19, 0x3fffffe0 + v_lshlrev_b32_e32 v32, 3, v31 + v_lshlrev_b32_e32 v7, 12, v31 + v_and_b32_e32 v26, 48, v3 + v_add_u32_e32 v33, s24, v4 + s_and_b32 s11, s25, 32 + v_and_or_b32 v6, v5, 8, v31 + v_or_b32_e32 v3, s19, v30 + v_lshl_or_b32 v34, v27, 7, v7 + v_add_u32_e32 v4, s21, v33 + v_or_b32_e32 v5, s11, v30 + v_lshrrev_b32_e32 v35, 4, v3 + v_mad_u64_u32 v[28:29], s[24:25], v4, s22, v[26:27] + v_lshrrev_b32_e32 v8, 1, v5 + v_bfe_u32 v5, v5, 1, 4 + v_xor_b32_e32 v29, v27, v35 + v_xor_b32_e32 v4, v5, v6 + v_lshlrev_b32_e32 v7, 7, v8 + v_add_u32_e32 v36, s22, v28 + buffer_load_dwordx4 v[40:43], v28, s[12:15], 0 offen + buffer_load_dwordx4 v[44:47], v36, s[12:15], 0 offen + v_add_u32_e32 v28, s22, v36 + v_add_u32_e32 v36, s22, v28 + buffer_load_dwordx4 v[48:51], v28, s[12:15], 0 offen + buffer_load_dwordx4 v[52:55], v36, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v10, v10, s23 + v_perm_b32 v11, v11, v11, s23 + v_perm_b32 v12, v12, v12, s23 + v_perm_b32 v13, v13, v13, s23 + s_waitcnt vmcnt(6) + v_perm_b32 v14, v14, v14, s23 + v_perm_b32 v15, v15, v15, s23 + v_perm_b32 v16, v16, v16, s23 + v_perm_b32 v17, v17, v17, s23 + s_waitcnt vmcnt(5) + v_perm_b32 v18, v18, v18, s23 + v_perm_b32 v19, v19, v19, s23 + v_perm_b32 v20, v20, v20, s23 + v_perm_b32 v21, v21, v21, s23 + v_perm_b32 v28, v14, v10, s26 + v_perm_b32 v10, v14, v10, s29 + v_perm_b32 v14, v15, v11, s26 + v_perm_b32 v11, v15, v11, s29 + v_perm_b32 v15, v16, v12, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v22, v22, v22, s23 + v_perm_b32 v23, v23, v23, s23 + v_perm_b32 v24, v24, v24, s23 + v_perm_b32 v25, v25, v25, s23 + v_perm_b32 v36, v22, v18, s26 + v_perm_b32 v18, v22, v18, s29 + v_perm_b32 v22, v23, v19, s26 + v_perm_b32 v19, v23, v19, s29 + v_perm_b32 v23, v36, v28, s27 + v_perm_b32 v28, v36, v28, s28 + v_perm_b32 v36, v18, v10, s27 + v_perm_b32 v10, v18, v10, s28 + v_perm_b32 v18, v22, v14, s27 + v_perm_b32 v14, v22, v14, s28 + v_perm_b32 v22, v19, v11, s27 + v_perm_b32 v11, v19, v11, s28 + v_perm_b32 v19, v24, v20, s26 + v_perm_b32 v37, v19, v15, s27 + v_perm_b32 v15, v19, v15, s28 + v_perm_b32 v12, v16, v12, s29 + v_perm_b32 v16, v24, v20, s29 + v_perm_b32 v19, v16, v12, s27 + v_perm_b32 v12, v16, v12, s28 + v_perm_b32 v16, v17, v13, s26 + v_perm_b32 v20, v25, v21, s26 + v_perm_b32 v24, v20, v16, s27 + v_perm_b32 v16, v20, v16, s28 + v_perm_b32 v13, v17, v13, s29 + v_perm_b32 v17, v25, v21, s29 + v_perm_b32 v20, v17, v13, s27 + v_perm_b32 v13, v17, v13, s28 + v_lshrrev_b32_e32 v17, 1, v9 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v21, v17, v30 + v_lshlrev_b32_e32 v25, 9, v9 + v_and_b32_e32 v25, 0x3000, v25 + v_lshlrev_b32_e32 v9, 6, v9 + s_movk_i32 s15, 0xf800 + v_and_b32_e32 v9, 0xfffff800, v9 + v_add_u32_e32 v9, v25, v9 + v_lshl_or_b32 v9, v21, 2, v9 + ds_write_b32 v9, v23 + v_or_b32_e32 v23, 1, v17 + v_xor_b32_e32 v23, v23, v30 + v_sub_u32_e32 v21, v23, v21 + v_lshl_add_u32 v9, v21, 2, v9 + ds_write_b32 v9, v28 offset:128 + v_or_b32_e32 v21, 2, v17 + v_xor_b32_e32 v21, v21, v30 + v_sub_u32_e32 v23, v21, v23 + v_mov_b32_e32 v25, 0x80 + v_lshl_add_u32 v23, v23, 2, v25 + v_or_b32_e32 v28, 3, v17 + v_xor_b32_e32 v28, v28, v30 + v_sub_u32_e32 v21, v28, v21 + v_lshl_add_u32 v21, v21, 2, v25 + v_add3_u32 v38, v9, v23, v21 + v_add3_u32 v9, v9, s18, v23 + ds_write_b32 v9, v36 + v_add_u32_e32 v9, v21, v9 + ds_write_b32 v9, v10 + v_or_b32_e32 v10, 4, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v21, v10, v28 + v_lshl_add_u32 v21, v21, 2, v25 + v_or_b32_e32 v23, 5, v17 + v_xor_b32_e32 v23, v23, v30 + v_sub_u32_e32 v10, v23, v10 + v_lshl_add_u32 v10, v10, 2, v25 + v_add3_u32 v28, v38, v21, v10 + v_add_u32_e32 v9, v21, v9 + ds_write_b32 v9, v18 + v_add_u32_e32 v9, v10, v9 + ds_write_b32 v9, v14 + v_or_b32_e32 v10, 6, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v14, v10, v23 + v_lshl_add_u32 v14, v14, 2, v25 + v_or_b32_e32 v18, 7, v17 + v_xor_b32_e32 v18, v18, v30 + v_sub_u32_e32 v10, v18, v10 + v_lshl_add_u32 v10, v10, 2, v25 + v_add3_u32 v21, v28, v14, v10 + v_add_u32_e32 v9, v14, v9 + ds_write_b32 v9, v22 + v_add_u32_e32 v9, v10, v9 + ds_write_b32 v9, v11 + v_or_b32_e32 v10, 8, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v11, v10, v18 + v_lshl_add_u32 v11, v11, 2, v25 + v_or_b32_e32 v14, 9, v17 + v_xor_b32_e32 v14, v14, v30 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v25 + v_add3_u32 v18, v21, v11, v10 + v_add_u32_e32 v9, v11, v9 + ds_write_b32 v9, v37 + v_add_u32_e32 v9, v10, v9 + ds_write_b32 v9, v15 + v_or_b32_e32 v10, 10, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v25 + v_or_b32_e32 v14, 11, v17 + v_xor_b32_e32 v14, v14, v30 + v_sub_u32_e32 v10, v14, v10 + v_lshl_add_u32 v10, v10, 2, v25 + v_add3_u32 v15, v18, v11, v10 + v_add_u32_e32 v9, v11, v9 + ds_write_b32 v9, v19 + v_add_u32_e32 v9, v10, v9 + ds_write_b32 v9, v12 + v_or_b32_e32 v10, 12, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v11, v10, v14 + v_lshl_add_u32 v11, v11, 2, v25 + v_or_b32_e32 v12, 13, v17 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v10, v12, v10 + v_lshl_add_u32 v10, v10, 2, v25 + v_add3_u32 v14, v15, v11, v10 + v_add_u32_e32 v9, v11, v9 + ds_write_b32 v9, v24 + v_add_u32_e32 v9, v10, v9 + ds_write_b32 v9, v16 + v_or_b32_e32 v10, 14, v17 + v_xor_b32_e32 v10, v10, v30 + v_sub_u32_e32 v11, v10, v12 + v_lshlrev_b32_e32 v11, 2, v11 + v_or_b32_e32 v12, 15, v17 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v14, v11, v10 + v_add_u32_e32 v9, v9, v11 + ds_write_b32 v9, v20 offset:128 + ds_write_b32 v10, v13 offset:384 + v_lshrrev_b32_e32 v9, 3, v26 + v_ashrrev_i32_e32 v10, 1, v33 + v_ashrrev_i32_e32 v11, 31, v33 + v_lshrrev_b32_e32 v11, 28, v11 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -16, v12 + v_sub_u32_e32 v12, v10, v12 + v_xor_b32_e32 v13, v12, v9 + v_lshlrev_b32_e32 v14, 6, v33 + v_lshl_add_u32 v13, v13, 3, v14 + s_waitcnt vmcnt(3) + ds_write_b64 v13, v[40:41] offset:16384 + v_or_b32_e32 v13, 1, v9 + v_xor_b32_e32 v12, v12, v13 + v_lshl_add_u32 v14, v12, 3, v14 + ds_write_b64 v14, v[42:43] offset:16384 + v_or_b32_e32 v15, 1, v33 + v_sub_u32_e32 v16, v9, v13 + v_lshrrev_b32_e32 v17, 31, v33 + v_add_u32_e32 v18, v15, v17 + v_ashrrev_i32_e32 v19, 1, v18 + v_sub_u32_e32 v20, v19, v10 + v_and_b32_e32 v21, 0x1ffffffe, v18 + v_sub_u32_e32 v15, v15, v21 + v_lshl_or_b32 v15, v15, 3, v13 + v_add_u32_e32 v21, v15, v16 + v_ashrrev_i32_e32 v18, 31, v18 + v_lshrrev_b32_e32 v18, 28, v18 + v_add_u32_e32 v18, v19, v18 + v_and_b32_e32 v18, -16, v18 + v_sub_u32_e32 v18, v19, v18 + v_xor_b32_e32 v21, v21, v18 + v_sub_u32_e32 v21, v21, v12 + v_lshl_add_u32 v14, v20, 7, v14 + v_lshl_add_u32 v20, v21, 3, v14 + s_waitcnt vmcnt(2) + ds_write_b64 v20, v[44:45] offset:16384 + v_xor_b32_e32 v15, v15, v18 + v_sub_u32_e32 v12, v15, v12 + v_lshl_add_u32 v12, v12, 3, v14 + ds_write_b64 v12, v[46:47] offset:16384 + v_or_b32_e32 v10, 1, v10 + v_sub_u32_e32 v14, v10, v19 + v_add_u32_e32 v11, v10, v11 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v10, v11 + v_xor_b32_e32 v9, v11, v9 + v_sub_u32_e32 v15, v9, v15 + v_lshlrev_b32_e32 v15, 3, v15 + v_lshlrev_b32_e32 v14, 7, v14 + v_add3_u32 v12, v15, v14, v12 + s_waitcnt vmcnt(1) + ds_write_b64 v12, v[48:49] offset:16384 + v_xor_b32_e32 v11, v11, v13 + v_sub_u32_e32 v9, v11, v9 + v_lshl_add_u32 v9, v9, 3, v12 + ds_write_b64 v9, v[50:51] offset:16384 + v_or_b32_e32 v12, 3, v33 + v_add_u32_e32 v14, v12, v17 + v_ashrrev_i32_e32 v15, 1, v14 + v_sub_u32_e32 v10, v15, v10 + v_and_b32_e32 v17, 0x1ffffffe, v14 + v_sub_u32_e32 v12, v12, v17 + v_lshl_or_b32 v12, v12, 3, v13 + v_add_u32_e32 v13, v12, v16 + v_ashrrev_i32_e32 v14, 31, v14 + v_lshrrev_b32_e32 v14, 28, v14 + v_add_u32_e32 v14, v15, v14 + v_and_b32_e32 v14, -16, v14 + v_sub_u32_e32 v14, v15, v14 + v_xor_b32_e32 v13, v13, v14 + v_sub_u32_e32 v11, v13, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_lshlrev_b32_e32 v10, 7, v10 + v_add3_u32 v9, v11, v10, v9 + s_waitcnt vmcnt(0) + ds_write_b64 v9, v[52:53] offset:16384 + v_xor_b32_e32 v10, v12, v14 + v_sub_u32_e32 v10, v10, v13 + v_lshl_add_u32 v9, v10, 3, v9 + ds_write_b64 v9, v[54:55] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v10, v29, 2, v34 + v_lshrrev_b16_e32 v11, 3, v32 + v_add_u32_e32 v12, 16, v35 + v_xor_b32_e32 v9, v27, v12 + v_sub_u32_e32 v13, v11, v31 + v_lshlrev_b32_e32 v13, 12, v13 + v_lshlrev_b32_e32 v14, 2, v9 + v_add3_u32 v13, v14, v34, v13 + v_add_u32_e32 v14, 16, v32 + v_lshrrev_b32_e32 v15, 5, v14 + v_lshrrev_b16_e32 v14, 3, v14 + v_and_b32_e32 v14, 3, v14 + v_sub_u16_e32 v16, v14, v11 + v_bfe_i32 v16, v16, 0, 16 + v_lshlrev_b32_e32 v17, 4, v15 + v_or_b32_e32 v18, v17, v27 + v_and_b32_e32 v18, 31, v18 + v_xor_b32_e32 v18, v18, v35 + v_sub_u32_e32 v9, v18, v9 + v_lshlrev_b32_e32 v19, 11, v15 + v_lshlrev_b32_e32 v9, 2, v9 + v_lshl_add_u32 v30, v16, 12, v19 + v_add3_u32 v16, v30, v13, v9 + v_add_u32_e32 v9, 20, v32 + v_lshrrev_b32_e32 v19, 5, v9 + v_sub_u32_e32 v15, v19, v15 + v_lshrrev_b16_e32 v9, 3, v9 + v_and_b32_e32 v9, 3, v9 + v_sub_u16_e32 v14, v9, v14 + v_bfe_i32 v14, v14, 0, 16 + v_lshlrev_b32_e32 v20, 4, v19 + v_or_b32_e32 v21, v20, v27 + v_and_b32_e32 v21, 31, v21 + v_xor_b32_e32 v21, v21, v12 + v_sub_u32_e32 v18, v21, v18 + v_lshlrev_b32_e32 v15, 11, v15 + v_lshlrev_b32_e32 v18, 2, v18 + v_lshl_add_u32 v31, v14, 12, v15 + v_add3_u32 v14, v18, v31, v16 + v_sub_u16_e32 v9, v11, v9 + v_bfe_i32 v9, v9, 0, 16 + v_or_b32_e32 v15, 16, v27 + v_xor_b32_e32 v18, v15, v35 + v_sub_u32_e32 v21, v18, v21 + v_lshlrev_b32_e32 v19, 11, v19 + v_xor_b32_e32 v19, 0x800, v19 + v_lshlrev_b32_e32 v21, 2, v21 + v_lshl_add_u32 v33, v9, 12, v19 + v_add3_u32 v19, v21, v33, v14 + v_xor_b32_e32 v9, v15, v12 + v_sub_u32_e32 v15, v9, v18 + v_lshl_add_u32 v15, v15, 2, v19 + v_add_u32_e32 v18, 48, v32 + v_lshrrev_b32_e32 v21, 5, v18 + v_lshlrev_b32_e32 v22, 11, v21 + v_lshrrev_b16_e32 v18, 3, v18 + v_and_b32_e32 v18, 3, v18 + v_sub_u16_e32 v23, v18, v11 + v_lshlrev_b32_e32 v24, 4, v21 + v_or_b32_e32 v25, v24, v27 + v_and_b32_e32 v25, 31, v25 + v_xor_b32_e32 v25, v25, v35 + v_sub_u32_e32 v9, v25, v9 + v_lshlrev_b32_e32 v26, 2, v9 + v_mov_b32_e32 v28, 12 + v_lshlrev_b32_sdwa v9, v28, sext(v23) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v9, v22, v9, s15 + v_add3_u32 v22, v26, v9, v15 + v_add_u32_e32 v23, 52, v32 + v_lshrrev_b32_e32 v26, 5, v23 + v_sub_u32_e32 v21, v26, v21 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v18, v23, v18 + v_bfe_i32 v18, v18, 0, 16 + v_lshlrev_b32_e32 v29, 4, v26 + v_or_b32_e32 v27, v29, v27 + v_and_b32_e32 v32, 31, v27 + v_xor_b32_e32 v12, v32, v12 + v_sub_u32_e32 v25, v12, v25 + v_lshlrev_b32_e32 v21, 11, v21 + v_lshlrev_b32_e32 v25, 2, v25 + v_lshl_add_u32 v34, v18, 12, v21 + v_add3_u32 v18, v25, v34, v22 + ds_read_b32 v54, v10 + ds_read_b32 v55, v13 + ds_read_b32 v72, v16 + ds_read_b32 v73, v14 + ds_read_b32 v74, v19 + ds_read_b32 v75, v15 + ds_read_b32 v76, v22 + ds_read_b32 v77, v18 + v_add_u32_e32 v10, 64, v3 + v_lshrrev_b32_e32 v10, 4, v10 + v_sub_u16_e32 v11, v11, v23 + v_sub_u32_e32 v13, v27, v29 + v_ashrrev_i32_e32 v14, 31, v13 + v_lshrrev_b32_e32 v14, 27, v14 + v_add_u32_e32 v14, v13, v14 + v_and_b32_e32 v14, 0xffffffe0, v14 + v_sub_u32_e32 v35, v13, v14 + v_xor_b32_e32 v14, v35, v10 + v_sub_u32_e32 v12, v14, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_lshlrev_b32_sdwa v11, v28, sext(v11) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v15, 11, v26 + v_sub_u32_e32 v36, v11, v15 + v_add3_u32 v11, v12, v36, v18 + v_add_u32_e32 v37, 16, v10 + v_xor_b32_e32 v12, v35, v37 + v_sub_u32_e32 v14, v12, v14 + v_lshl_add_u32 v14, v14, 2, v11 + v_add_u32_e32 v15, v13, v17 + v_ashrrev_i32_e32 v16, 31, v15 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v15, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v38, v15, v16 + v_xor_b32_e32 v15, v38, v10 + v_sub_u32_e32 v12, v15, v12 + v_lshl_add_u32 v12, v12, 2, v30 + v_add_u32_e32 v39, v12, v14 + v_add_u32_e32 v12, v13, v20 + v_ashrrev_i32_e32 v16, 31, v12 + v_lshrrev_b32_e32 v16, 27, v16 + v_add_u32_e32 v16, v12, v16 + v_and_b32_e32 v16, 0xffffffe0, v16 + v_sub_u32_e32 v40, v12, v16 + v_xor_b32_e32 v12, v40, v37 + v_sub_u32_e32 v15, v12, v15 + v_lshl_add_u32 v41, v15, 2, v31 + v_add_u32_e32 v15, v39, v41 + ds_read_b32 v64, v11 + ds_read_b32 v65, v14 + ds_read_b32 v78, v39 + ds_read_b32 v79, v15 + v_add_u32_e32 v11, 16, v13 + v_ashrrev_i32_e32 v14, 31, v11 + v_lshrrev_b32_e32 v14, 27, v14 + v_add_u32_e32 v14, v11, v14 + v_and_b32_e32 v14, 0xffffffe0, v14 + v_sub_u32_e32 v42, v11, v14 + v_xor_b32_e32 v11, v42, v10 + v_sub_u32_e32 v12, v11, v12 + v_lshl_add_u32 v43, v12, 2, v33 + v_add_u32_e32 v44, v15, v43 + v_xor_b32_e32 v45, v42, v37 + v_sub_u32_e32 v11, v45, v11 + v_lshlrev_b32_e32 v46, 2, v11 + v_add_u32_e32 v47, v44, v46 + v_add_u32_e32 v11, v13, v24 + v_ashrrev_i32_e32 v12, 31, v11 + v_lshrrev_b32_e32 v12, 27, v12 + v_add_u32_e32 v12, v11, v12 + v_and_b32_e32 v12, 0xffffffe0, v12 + v_sub_u32_e32 v48, v11, v12 + v_xor_b32_e32 v49, v48, v10 + v_lshl_or_b32 v10, v4, 3, v7 + v_add_u32_e32 v16, 2, v6 + v_add_u32_e32 v11, -16, v8 + s_cmp_eq_u32 s11, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v8, v11, v8, vcc + v_xor_b32_e32 v11, v8, v16 + v_lshl_add_u32 v12, v11, 3, v7 + v_or_b32_e32 v17, 4, v6 + v_xor_b32_e32 v11, v8, v17 + v_lshl_add_u32 v14, v11, 3, v7 + ds_read_b64 v[10:11], v10 offset:16384 + ds_read_b64 v[12:13], v12 offset:16384 + ds_read_b64 v[14:15], v14 offset:16384 + v_add_u32_e32 v20, 6, v6 + v_xor_b32_e32 v6, v8, v20 + v_lshl_add_u32 v8, v6, 3, v7 + v_sub_u32_e32 v6, v4, v6 + v_lshl_add_u32 v21, v6, 3, v8 + v_xor_b32_e32 v6, v5, v16 + v_sub_u32_e32 v6, v6, v4 + v_lshlrev_b32_e32 v26, 3, v6 + v_add_u32_e32 v16, v21, v26 + v_xor_b32_e32 v6, v5, v17 + v_sub_u32_e32 v6, v6, v4 + v_lshlrev_b32_e32 v27, 3, v6 + v_add_u32_e32 v18, v21, v27 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[176:191], v[54:55], v[10:11], 0 + ds_read_b64 v[6:7], v21 offset:20480 + ds_read_b64 v[16:17], v16 offset:20480 + ds_read_b64 v[18:19], v18 offset:20480 + v_xor_b32_e32 v5, v5, v20 + v_sub_u32_e32 v20, v5, v4 + v_lshlrev_b32_e32 v50, 3, v20 + v_add_u32_e32 v51, v21, v50 + v_sub_u32_e32 v4, v4, v5 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[54:55], v[6:7], 0 + v_lshlrev_b32_e32 v24, 3, v4 + v_add_u32_e32 v25, v51, v24 + ds_read_b64 v[4:5], v25 offset:24576 + v_add_u32_e32 v20, v25, v26 + v_add_u32_e32 v22, v25, v27 + ds_read_b64 v[20:21], v20 offset:24576 + ds_read_b64 v[22:23], v22 offset:24576 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[48:63], v[54:55], v[4:5], 0 + v_add_u32_e32 v52, v25, v50 + v_add_u32_e32 v53, v52, v24 + ds_read_b64 v[24:25], v53 offset:28672 + v_add_u32_e32 v26, v53, v26 + v_add_u32_e32 v28, v53, v27 + ds_read_b64 v[26:27], v26 offset:28672 + ds_read_b64 v[28:29], v28 offset:28672 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[0:15], v[54:55], v[24:25], 0 + v_sub_u32_e32 v45, v49, v45 + v_lshl_add_u32 v45, v45, 2, v9 + v_add_u32_e32 v54, v47, v45 + v_xor_b32_e32 v37, v32, v37 + v_sub_u32_e32 v49, v37, v49 + v_lshl_add_u32 v49, v49, 2, v34 + v_add_u32_e32 v55, v54, v49 + v_mfma_i32_32x32x16_i8 a[192:207], v[64:65], v[10:11], 0 + v_add_u32_e32 v56, 0x80, v3 + v_lshrrev_b32_e32 v56, 4, v56 + v_xor_b32_e32 v57, v35, v56 + v_sub_u32_e32 v37, v57, v37 + v_lshl_add_u32 v37, v37, 2, v36 + v_add_u32_e32 v58, v55, v37 + ds_read_b32 v80, v58 + v_mfma_i32_32x32x16_i8 a[128:143], v[64:65], v[6:7], 0 + v_add_u32_e32 v59, 16, v56 + v_xor_b32_e32 v60, v35, v59 + v_sub_u32_e32 v57, v60, v57 + v_lshlrev_b32_e32 v57, 2, v57 + v_add_u32_e32 v58, v58, v57 + ds_read_b32 v81, v58 + v_xor_b32_e32 v61, v38, v56 + v_mfma_i32_32x32x16_i8 a[64:79], v[64:65], v[4:5], 0 + v_sub_u32_e32 v60, v61, v60 + v_lshl_add_u32 v60, v60, 2, v30 + v_add_u32_e32 v58, v58, v60 + v_xor_b32_e32 v62, v40, v59 + v_sub_u32_e32 v61, v62, v61 + v_lshl_add_u32 v61, v61, 2, v31 + v_add_u32_e32 v63, v58, v61 + v_mfma_i32_32x32x16_i8 a[16:31], v[64:65], v[24:25], 0 + v_xor_b32_e32 v64, v42, v56 + v_sub_u32_e32 v62, v64, v62 + v_lshl_add_u32 v62, v62, 2, v33 + v_add_u32_e32 v65, v63, v62 + v_xor_b32_e32 v66, v42, v59 + v_sub_u32_e32 v64, v66, v64 + v_lshlrev_b32_e32 v64, 2, v64 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[80:81], v[10:11], 0 + v_add_u32_e32 v67, v65, v64 + v_xor_b32_e32 v56, v48, v56 + v_sub_u32_e32 v66, v56, v66 + v_lshl_add_u32 v66, v66, 2, v9 + v_add_u32_e32 v68, v67, v66 + v_xor_b32_e32 v59, v32, v59 + v_sub_u32_e32 v56, v59, v56 + v_mfma_i32_32x32x16_i8 a[144:159], v[80:81], v[6:7], 0 + v_lshl_add_u32 v56, v56, 2, v34 + v_add_u32_e32 v69, v68, v56 + v_add_u32_e32 v3, 0xc0, v3 + v_lshrrev_b32_e32 v3, 4, v3 + v_xor_b32_e32 v70, v35, v3 + v_sub_u32_e32 v59, v70, v59 + v_lshl_add_u32 v36, v59, 2, v36 + v_mfma_i32_32x32x16_i8 a[80:95], v[80:81], v[4:5], 0 + v_add_u32_e32 v59, v69, v36 + ds_read_b32 v82, v59 + v_add_u32_e32 v71, 16, v3 + v_xor_b32_e32 v35, v35, v71 + v_sub_u32_e32 v70, v35, v70 + v_lshlrev_b32_e32 v70, 2, v70 + v_add_u32_e32 v59, v59, v70 + v_mfma_i32_32x32x16_i8 a[32:47], v[80:81], v[24:25], 0 + ds_read_b32 v83, v59 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[82:83], v[10:11], 0 + v_mfma_i32_32x32x16_i8 a[160:175], v[82:83], v[6:7], 0 + v_mfma_i32_32x32x16_i8 a[96:111], v[82:83], v[4:5], 0 + v_mfma_i32_32x32x16_i8 a[240:255], v[82:83], v[24:25], 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[72:73], v[12:13], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[72:73], v[16:17], a[112:127] + v_mfma_i32_32x32x16_i8 a[48:63], v[72:73], v[20:21], a[48:63] + v_mfma_i32_32x32x16_i8 a[0:15], v[72:73], v[26:27], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[78:79], v[12:13], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[78:79], v[16:17], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[78:79], v[20:21], a[64:79] + ds_read_b32 v10, v58 + v_mfma_i32_32x32x16_i8 a[16:31], v[78:79], v[26:27], a[16:31] + ds_read_b32 v11, v63 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[10:11], v[12:13], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[10:11], v[16:17], a[144:159] + v_xor_b32_e32 v4, v38, v3 + v_sub_u32_e32 v5, v4, v35 + v_mfma_i32_32x32x16_i8 a[80:95], v[10:11], v[20:21], a[80:95] + v_lshl_add_u32 v24, v5, 2, v30 + v_add_u32_e32 v5, v59, v24 + ds_read_b32 v30, v5 + v_xor_b32_e32 v6, v40, v71 + v_sub_u32_e32 v4, v6, v4 + v_lshl_add_u32 v25, v4, 2, v31 + v_add_u32_e32 v4, v5, v25 + v_mfma_i32_32x32x16_i8 a[32:47], v[10:11], v[26:27], a[32:47] + ds_read_b32 v31, v4 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[30:31], v[12:13], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[30:31], v[16:17], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[30:31], v[20:21], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[30:31], v[26:27], a[240:255] + v_mfma_i32_32x32x16_i8 a[176:191], v[74:75], v[14:15], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[74:75], v[18:19], a[112:127] + v_mfma_i32_32x32x16_i8 a[48:63], v[74:75], v[22:23], a[48:63] + ds_read_b32 v10, v44 + v_mfma_i32_32x32x16_i8 a[0:15], v[74:75], v[28:29], a[0:15] + ds_read_b32 v11, v47 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[14:15], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[18:19], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[22:23], a[64:79] + ds_read_b32 v12, v65 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[28:29], a[16:31] + ds_read_b32 v13, v67 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[12:13], v[14:15], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[12:13], v[18:19], a[144:159] + v_xor_b32_e32 v5, v42, v3 + v_sub_u32_e32 v6, v5, v6 + v_mfma_i32_32x32x16_i8 a[80:95], v[12:13], v[22:23], a[80:95] + v_lshl_add_u32 v16, v6, 2, v33 + v_add_u32_e32 v4, v4, v16 + ds_read_b32 v6, v4 + v_xor_b32_e32 v17, v42, v71 + v_sub_u32_e32 v5, v17, v5 + v_lshlrev_b32_e32 v20, 2, v5 + v_add_u32_e32 v21, v4, v20 + v_mfma_i32_32x32x16_i8 a[32:47], v[12:13], v[28:29], a[32:47] + ds_read_b32 v7, v21 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[6:7], v[14:15], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[6:7], v[18:19], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[6:7], v[22:23], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[6:7], v[28:29], a[240:255] + ds_read_b64 v[4:5], v8 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[76:77], v[4:5], a[176:191] + ds_read_b64 v[6:7], v51 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[76:77], v[6:7], a[112:127] + ds_read_b64 v[10:11], v52 offset:24576 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[76:77], v[10:11], a[48:63] + v_add_u32_e32 v8, v53, v50 + ds_read_b64 v[12:13], v8 offset:28672 + ds_read_b32 v14, v54 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[76:77], v[12:13], a[0:15] + ds_read_b32 v15, v55 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[14:15], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[14:15], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[14:15], v[10:11], a[64:79] + ds_read_b32 v18, v68 + v_mfma_i32_32x32x16_i8 a[16:31], v[14:15], v[12:13], a[16:31] + ds_read_b32 v19, v69 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[18:19], v[4:5], a[208:223] + v_add3_u32 v8, v41, v39, v43 + v_add3_u32 v8, v46, v8, v45 + v_add3_u32 v8, v49, v8, v37 + v_add3_u32 v8, v8, v57, v60 + v_add3_u32 v8, v61, v8, v62 + v_mfma_i32_32x32x16_i8 a[144:159], v[18:19], v[6:7], a[144:159] + v_add3_u32 v8, v64, v8, v66 + v_add3_u32 v8, v56, v8, v36 + v_add3_u32 v8, v8, v70, v24 + v_add3_u32 v8, v25, v8, v16 + v_xor_b32_e32 v3, v48, v3 + v_sub_u32_e32 v14, v3, v17 + v_lshl_add_u32 v9, v14, 2, v9 + v_mfma_i32_32x32x16_i8 a[80:95], v[18:19], v[10:11], a[80:95] + v_add3_u32 v8, v20, v8, v9 + v_xor_b32_e32 v14, v32, v71 + v_sub_u32_e32 v3, v14, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v3, v34, v8 + ds_read_b32 v15, v3 + v_add_u32_e32 v3, v21, v9 + v_mfma_i32_32x32x16_i8 a[32:47], v[18:19], v[12:13], a[32:47] + ds_read_b32 v14, v3 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[14:15], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[14:15], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[14:15], v[10:11], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[14:15], v[12:13], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB33_3 + s_branch .LBB33_10 +.LBB33_2: + ; implicit-def: $agpr111 + ; implicit-def: $agpr175 + ; implicit-def: $agpr239 + ; implicit-def: $agpr47 + ; implicit-def: $agpr95 + ; implicit-def: $agpr159 + ; implicit-def: $agpr223 + ; implicit-def: $agpr31 + ; implicit-def: $agpr79 + ; implicit-def: $agpr143 + ; implicit-def: $agpr207 + ; implicit-def: $agpr15 + ; implicit-def: $agpr63 + ; implicit-def: $agpr127 + ; implicit-def: $agpr191 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr1 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB33_3: + v_readfirstlane_b32 s15, v0 + v_mbcnt_hi_u32_b32 v1, -1, v2 + v_and_b32_e32 v2, 15, v1 + s_lshr_b32 s23, s15, 2 + s_and_b32 s11, s23, 0x3ffffff0 + v_lshrrev_b32_e32 v3, 2, v1 + v_lshl_or_b32 v4, v2, 4, s20 + v_and_b32_e32 v81, 28, v3 + v_add_u32_e32 v23, s11, v81 + v_mad_u64_u32 v[18:19], s[18:19], v23, s7, v[4:5] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v18 + buffer_load_dwordx4 v[14:17], v3, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[26:29], v3, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[30:33], v3, s[8:11], 0 offen + s_mov_b32 s24, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s26, 0x5040100 + s_mov_b32 s27, 0x7060302 + s_mov_b32 s28, 0x7030602 + v_lshrrev_b32_e32 v8, 5, v1 + v_and_b32_e32 v82, 31, v1 + v_lshlrev_b32_e32 v3, 4, v1 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v83, 0x7c, v1 + s_lshr_b32 s19, s15, 1 + v_lshlrev_b32_e32 v4, 3, v1 + s_mov_b32 s15, s11 + s_and_b32 s23, s23, 0x3fffffe0 + v_lshlrev_b32_e32 v5, 12, v8 + v_lshlrev_b32_e32 v19, 3, v8 + v_and_b32_e32 v22, 48, v3 + v_add_u32_e32 v24, s18, v83 + v_and_or_b32 v3, s19, 32, v82 + v_and_or_b32 v34, v4, 8, v8 + v_or_b32_e32 v6, s23, v82 + v_lshl_or_b32 v9, v2, 7, v5 + v_add_u32_e32 v5, s21, v24 + v_lshrrev_b32_e32 v25, 1, v3 + v_bfe_u32 v4, v3, 1, 4 + v_lshrrev_b32_e32 v7, 4, v6 + v_mad_u64_u32 v[20:21], s[18:19], v5, s22, v[22:23] + v_xor_b32_e32 v3, v4, v34 + v_lshlrev_b32_e32 v5, 7, v25 + v_xor_b32_e32 v25, v2, v7 + v_add_u32_e32 v21, s22, v20 + buffer_load_dwordx4 v[38:41], v20, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v21, s[12:15], 0 offen + v_add_u32_e32 v21, s22, v21 + v_add_u32_e32 v35, s22, v21 + buffer_load_dwordx4 v[46:49], v21, s[12:15], 0 offen + buffer_load_dwordx4 v[50:53], v35, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v10, v10, s24 + v_perm_b32 v11, v11, v11, s24 + v_perm_b32 v12, v12, v12, s24 + v_perm_b32 v13, v13, v13, s24 + s_waitcnt vmcnt(6) + v_perm_b32 v14, v14, v14, s24 + v_perm_b32 v15, v15, v15, s24 + v_perm_b32 v16, v16, v16, s24 + v_perm_b32 v17, v17, v17, s24 + s_waitcnt vmcnt(5) + v_perm_b32 v21, v26, v26, s24 + v_perm_b32 v26, v27, v27, s24 + v_perm_b32 v27, v28, v28, s24 + v_perm_b32 v28, v29, v29, s24 + v_perm_b32 v29, v14, v10, s25 + v_perm_b32 v10, v14, v10, s28 + v_perm_b32 v14, v15, v11, s25 + v_perm_b32 v11, v15, v11, s28 + v_perm_b32 v15, v16, v12, s25 + s_waitcnt vmcnt(4) + v_perm_b32 v30, v30, v30, s24 + v_perm_b32 v31, v31, v31, s24 + v_perm_b32 v32, v32, v32, s24 + v_perm_b32 v33, v33, v33, s24 + v_perm_b32 v35, v30, v21, s25 + v_perm_b32 v21, v30, v21, s28 + v_perm_b32 v30, v31, v26, s25 + v_perm_b32 v26, v31, v26, s28 + v_perm_b32 v31, v32, v27, s25 + v_perm_b32 v36, v35, v29, s26 + v_perm_b32 v29, v35, v29, s27 + v_perm_b32 v35, v21, v10, s26 + v_perm_b32 v10, v21, v10, s27 + v_perm_b32 v21, v30, v14, s26 + v_perm_b32 v14, v30, v14, s27 + v_perm_b32 v30, v26, v11, s26 + v_perm_b32 v11, v26, v11, s27 + v_perm_b32 v26, v31, v15, s26 + v_perm_b32 v15, v31, v15, s27 + v_perm_b32 v12, v16, v12, s28 + v_perm_b32 v16, v32, v27, s28 + v_perm_b32 v27, v16, v12, s26 + v_perm_b32 v12, v16, v12, s27 + v_perm_b32 v16, v17, v13, s25 + v_perm_b32 v31, v33, v28, s25 + v_perm_b32 v32, v31, v16, s26 + v_perm_b32 v16, v31, v16, s27 + v_perm_b32 v13, v17, v13, s28 + v_perm_b32 v17, v33, v28, s28 + v_perm_b32 v28, v17, v13, s26 + v_perm_b32 v13, v17, v13, s27 + v_lshrrev_b32_e32 v17, 1, v23 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v31, v17, v82 + v_lshlrev_b32_e32 v33, 9, v23 + v_and_b32_e32 v33, 0x3000, v33 + v_lshlrev_b32_e32 v23, 6, v23 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v23, 0xfffff800, v23 + v_add_u32_e32 v23, v33, v23 + v_lshl_or_b32 v23, v31, 2, v23 + ds_write_b32 v23, v36 + v_or_b32_e32 v33, 1, v17 + v_xor_b32_e32 v33, v33, v82 + v_sub_u32_e32 v31, v33, v31 + v_lshl_add_u32 v23, v31, 2, v23 + ds_write_b32 v23, v29 offset:128 + v_or_b32_e32 v29, 2, v17 + v_xor_b32_e32 v29, v29, v82 + v_sub_u32_e32 v31, v29, v33 + s_movk_i32 s19, 0x80 + v_mov_b32_e32 v33, 0x80 + v_lshl_add_u32 v31, v31, 2, v33 + v_or_b32_e32 v36, 3, v17 + v_xor_b32_e32 v36, v36, v82 + v_sub_u32_e32 v29, v36, v29 + v_lshl_add_u32 v29, v29, 2, v33 + v_add3_u32 v37, v23, v31, v29 + v_add3_u32 v23, v23, s19, v31 + ds_write_b32 v23, v35 + v_add_u32_e32 v23, v29, v23 + ds_write_b32 v23, v10 + v_or_b32_e32 v10, 4, v17 + v_xor_b32_e32 v10, v10, v82 + v_sub_u32_e32 v29, v10, v36 + v_lshl_add_u32 v29, v29, 2, v33 + v_or_b32_e32 v31, 5, v17 + v_xor_b32_e32 v31, v31, v82 + v_sub_u32_e32 v10, v31, v10 + v_lshl_add_u32 v10, v10, 2, v33 + v_add3_u32 v35, v37, v29, v10 + v_add_u32_e32 v23, v29, v23 + ds_write_b32 v23, v21 + v_add_u32_e32 v10, v10, v23 + ds_write_b32 v10, v14 + v_or_b32_e32 v14, 6, v17 + v_xor_b32_e32 v14, v14, v82 + v_sub_u32_e32 v21, v14, v31 + v_lshl_add_u32 v21, v21, 2, v33 + v_or_b32_e32 v23, 7, v17 + v_xor_b32_e32 v23, v23, v82 + v_sub_u32_e32 v14, v23, v14 + v_lshl_add_u32 v14, v14, 2, v33 + v_add3_u32 v29, v35, v21, v14 + v_add_u32_e32 v10, v21, v10 + ds_write_b32 v10, v30 + v_add_u32_e32 v10, v14, v10 + ds_write_b32 v10, v11 + v_or_b32_e32 v11, 8, v17 + v_xor_b32_e32 v11, v11, v82 + v_sub_u32_e32 v14, v11, v23 + v_lshl_add_u32 v14, v14, 2, v33 + v_or_b32_e32 v21, 9, v17 + v_xor_b32_e32 v21, v21, v82 + v_sub_u32_e32 v11, v21, v11 + v_lshl_add_u32 v11, v11, 2, v33 + v_add3_u32 v23, v29, v14, v11 + v_add_u32_e32 v10, v14, v10 + ds_write_b32 v10, v26 + v_add_u32_e32 v10, v11, v10 + ds_write_b32 v10, v15 + v_or_b32_e32 v11, 10, v17 + v_xor_b32_e32 v11, v11, v82 + v_sub_u32_e32 v14, v11, v21 + v_lshl_add_u32 v14, v14, 2, v33 + v_or_b32_e32 v15, 11, v17 + v_xor_b32_e32 v15, v15, v82 + v_sub_u32_e32 v11, v15, v11 + v_lshl_add_u32 v11, v11, 2, v33 + v_add3_u32 v21, v23, v14, v11 + v_add_u32_e32 v10, v14, v10 + ds_write_b32 v10, v27 + v_add_u32_e32 v10, v11, v10 + ds_write_b32 v10, v12 + v_or_b32_e32 v11, 12, v17 + v_xor_b32_e32 v11, v11, v82 + v_sub_u32_e32 v12, v11, v15 + v_lshl_add_u32 v12, v12, 2, v33 + v_or_b32_e32 v14, 13, v17 + v_xor_b32_e32 v14, v14, v82 + v_sub_u32_e32 v11, v14, v11 + v_lshl_add_u32 v11, v11, 2, v33 + v_add3_u32 v15, v21, v12, v11 + v_add_u32_e32 v10, v12, v10 + ds_write_b32 v10, v32 + v_add_u32_e32 v10, v11, v10 + ds_write_b32 v10, v16 + v_or_b32_e32 v11, 14, v17 + v_xor_b32_e32 v11, v11, v82 + v_sub_u32_e32 v12, v11, v14 + v_lshlrev_b32_e32 v12, 2, v12 + v_or_b32_e32 v14, 15, v17 + v_xor_b32_e32 v14, v14, v82 + v_sub_u32_e32 v11, v14, v11 + v_lshlrev_b32_e32 v11, 2, v11 + v_add3_u32 v11, v15, v12, v11 + v_add_u32_e32 v10, v10, v12 + ds_write_b32 v10, v28 offset:128 + ds_write_b32 v11, v13 offset:384 + v_lshrrev_b32_e32 v84, 3, v22 + v_ashrrev_i32_e32 v10, 1, v24 + v_ashrrev_i32_e32 v11, 31, v24 + v_lshrrev_b32_e32 v11, 28, v11 + v_add_u32_e32 v12, v10, v11 + v_and_b32_e32 v12, -16, v12 + v_sub_u32_e32 v12, v10, v12 + v_xor_b32_e32 v13, v12, v84 + v_lshlrev_b32_e32 v14, 6, v24 + v_lshl_add_u32 v13, v13, 3, v14 + s_waitcnt vmcnt(3) + ds_write_b64 v13, v[38:39] offset:16384 + v_or_b32_e32 v85, 1, v84 + v_xor_b32_e32 v12, v12, v85 + v_lshl_add_u32 v13, v12, 3, v14 + ds_write_b64 v13, v[40:41] offset:16384 + v_or_b32_e32 v14, 1, v24 + v_sub_u32_e32 v86, v84, v85 + v_lshrrev_b32_e32 v15, 31, v24 + v_add_u32_e32 v16, v14, v15 + v_ashrrev_i32_e32 v17, 1, v16 + v_sub_u32_e32 v21, v17, v10 + v_and_b32_e32 v22, 0x1ffffffe, v16 + v_sub_u32_e32 v14, v14, v22 + v_lshl_or_b32 v14, v14, 3, v85 + v_add_u32_e32 v22, v14, v86 + v_ashrrev_i32_e32 v16, 31, v16 + v_lshrrev_b32_e32 v16, 28, v16 + v_add_u32_e32 v16, v17, v16 + v_and_b32_e32 v16, -16, v16 + v_sub_u32_e32 v16, v17, v16 + v_xor_b32_e32 v22, v22, v16 + v_sub_u32_e32 v22, v22, v12 + v_lshl_add_u32 v13, v21, 7, v13 + v_lshl_add_u32 v21, v22, 3, v13 + s_waitcnt vmcnt(2) + ds_write_b64 v21, v[42:43] offset:16384 + v_xor_b32_e32 v14, v14, v16 + v_sub_u32_e32 v12, v14, v12 + v_lshl_add_u32 v12, v12, 3, v13 + ds_write_b64 v12, v[44:45] offset:16384 + v_or_b32_e32 v10, 1, v10 + v_sub_u32_e32 v13, v10, v17 + v_add_u32_e32 v11, v10, v11 + v_and_b32_e32 v11, -16, v11 + v_sub_u32_e32 v11, v10, v11 + v_xor_b32_e32 v16, v11, v84 + v_sub_u32_e32 v14, v16, v14 + v_lshlrev_b32_e32 v14, 3, v14 + v_lshlrev_b32_e32 v13, 7, v13 + v_add3_u32 v12, v14, v13, v12 + s_waitcnt vmcnt(1) + ds_write_b64 v12, v[46:47] offset:16384 + v_xor_b32_e32 v11, v11, v85 + v_sub_u32_e32 v13, v11, v16 + v_lshl_add_u32 v12, v13, 3, v12 + ds_write_b64 v12, v[48:49] offset:16384 + v_or_b32_e32 v13, 3, v24 + v_add_u32_e32 v14, v13, v15 + v_ashrrev_i32_e32 v15, 1, v14 + v_sub_u32_e32 v10, v15, v10 + v_and_b32_e32 v16, 0x1ffffffe, v14 + v_sub_u32_e32 v13, v13, v16 + v_lshl_or_b32 v13, v13, 3, v85 + v_add_u32_e32 v16, v13, v86 + v_ashrrev_i32_e32 v14, 31, v14 + v_lshrrev_b32_e32 v14, 28, v14 + v_add_u32_e32 v14, v15, v14 + v_and_b32_e32 v14, -16, v14 + v_sub_u32_e32 v14, v15, v14 + v_xor_b32_e32 v15, v16, v14 + v_sub_u32_e32 v11, v15, v11 + v_lshlrev_b32_e32 v11, 3, v11 + v_lshlrev_b32_e32 v10, 7, v10 + v_add3_u32 v10, v11, v10, v12 + s_waitcnt vmcnt(0) + ds_write_b64 v10, v[50:51] offset:16384 + v_xor_b32_e32 v11, v13, v14 + v_sub_u32_e32 v11, v11, v15 + v_lshl_add_u32 v10, v11, 3, v10 + ds_write_b64 v10, v[52:53] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v14, 3, v19 + v_add_u32_e32 v15, 16, v7 + v_add_u32_e32 v24, 16, v19 + v_add_u32_e32 v23, 20, v19 + v_or_b32_e32 v13, 16, v2 + v_add_u32_e32 v22, 36, v19 + v_add_u32_e32 v21, 48, v19 + v_add_u32_e32 v17, 52, v19 + v_add_u32_e32 v16, 64, v6 + v_add_u32_e32 v12, 2, v34 + v_add_u32_e32 v11, 4, v34 + v_add_u32_e32 v10, 6, v34 + s_cbranch_vccnz .LBB33_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit968.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v19, v2, v15 + v_sub_u32_e32 v26, v14, v8 + v_lshlrev_b32_e32 v26, 12, v26 + v_lshlrev_b32_e32 v27, 2, v19 + v_add3_u32 v64, v27, v9, v26 + v_lshrrev_b32_e32 v26, 5, v24 + v_lshrrev_b16_e32 v27, 3, v24 + v_and_b32_e32 v27, 3, v27 + v_sub_u16_e32 v28, v27, v14 + v_bfe_i32 v28, v28, 0, 16 + v_lshl_or_b32 v29, v26, 4, v2 + v_xor_b32_e32 v30, v29, v7 + v_sub_u32_e32 v19, v30, v19 + v_lshlrev_b32_e32 v31, 11, v26 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_or_b32 v28, v28, 12, v31 + v_add3_u32 v35, v28, v64, v19 + v_lshrrev_b32_e32 v19, 5, v23 + v_sub_u32_e32 v26, v19, v26 + v_lshrrev_b16_e32 v31, 3, v23 + v_and_b32_e32 v31, 3, v31 + v_sub_u16_e32 v27, v31, v27 + v_bfe_i32 v27, v27, 0, 16 + v_lshl_or_b32 v32, v19, 4, v2 + v_xor_b32_e32 v33, v32, v15 + v_sub_u32_e32 v30, v33, v30 + v_lshlrev_b32_e32 v26, 11, v26 + v_lshlrev_b32_e32 v30, 2, v30 + v_lshl_add_u32 v26, v27, 12, v26 + v_add3_u32 v37, v30, v26, v35 + v_sub_u16_e32 v27, v14, v31 + v_bfe_i32 v27, v27, 0, 16 + v_xor_b32_e32 v30, v13, v7 + v_sub_u32_e32 v31, v30, v33 + v_lshlrev_b32_e32 v19, 11, v19 + v_xor_b32_e32 v19, 0x800, v19 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_or_b32 v27, v27, 12, v19 + v_add3_u32 v19, v31, v27, v37 + v_lshrrev_b32_e32 v31, 5, v22 + v_lshlrev_b32_e32 v33, 11, v31 + v_lshrrev_b16_e32 v34, 3, v22 + v_and_b32_e32 v34, 3, v34 + v_sub_u16_e32 v36, v34, v14 + v_lshl_or_b32 v38, v31, 4, v2 + v_and_b32_e32 v49, 31, v38 + v_xor_b32_e32 v38, v49, v15 + v_sub_u32_e32 v30, v38, v30 + v_lshlrev_b32_e32 v30, 2, v30 + v_mov_b32_e32 v39, 12 + v_lshlrev_b32_sdwa v36, v39, sext(v36) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v33, v33, v36, s18 + v_add3_u32 v36, v30, v33, v19 + v_lshrrev_b32_e32 v30, 5, v21 + v_sub_u32_e32 v31, v30, v31 + v_lshrrev_b16_e32 v40, 3, v21 + v_and_b32_e32 v40, 3, v40 + v_sub_u16_e32 v34, v40, v34 + v_bfe_i32 v34, v34, 0, 16 + v_lshl_or_b32 v41, v30, 4, v2 + v_and_b32_e32 v51, 31, v41 + v_xor_b32_e32 v41, v51, v7 + v_sub_u32_e32 v38, v41, v38 + v_lshlrev_b32_e32 v31, 11, v31 + v_lshlrev_b32_e32 v38, 2, v38 + v_lshl_add_u32 v31, v34, 12, v31 + v_add3_u32 v34, v38, v31, v36 + v_lshrrev_b32_e32 v42, 5, v17 + v_sub_u32_e32 v30, v42, v30 + v_lshrrev_b16_e32 v38, 3, v17 + v_and_b32_e32 v43, 3, v38 + v_sub_u16_e32 v38, v43, v40 + v_bfe_i32 v38, v38, 0, 16 + v_lshl_or_b32 v40, v42, 4, v2 + v_and_b32_e32 v55, 31, v40 + v_xor_b32_e32 v40, v55, v15 + v_sub_u32_e32 v41, v40, v41 + v_lshlrev_b32_e32 v30, 11, v30 + v_lshlrev_b32_e32 v41, 2, v41 + v_lshl_add_u32 v30, v38, 12, v30 + v_add3_u32 v38, v41, v30, v34 + v_lshrrev_b32_e32 v45, 4, v16 + v_sub_u16_e32 v41, v14, v43 + v_xor_b32_e32 v43, v2, v45 + v_sub_u32_e32 v40, v43, v40 + v_lshlrev_b32_e32 v40, 2, v40 + v_lshlrev_b32_sdwa v39, v39, sext(v41) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v41, 11, v42 + v_sub_u32_e32 v53, v39, v41 + v_add3_u32 v71, v40, v53, v38 + v_add_u32_e32 v40, 16, v45 + v_xor_b32_e32 v39, v2, v40 + v_sub_u32_e32 v41, v39, v43 + v_lshl_add_u32 v74, v41, 2, v71 + v_xor_b32_e32 v41, v29, v45 + v_sub_u32_e32 v39, v41, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v44, v39, v28, v74 + v_xor_b32_e32 v39, v32, v40 + v_sub_u32_e32 v41, v39, v41 + v_lshlrev_b32_e32 v41, 2, v41 + v_add3_u32 v46, v41, v26, v44 + v_xor_b32_e32 v42, v13, v45 + v_sub_u32_e32 v39, v42, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v41, v39, v27, v46 + v_xor_b32_e32 v39, v49, v40 + v_sub_u32_e32 v42, v39, v42 + v_lshlrev_b32_e32 v42, 2, v42 + v_add3_u32 v42, v42, v33, v41 + v_xor_b32_e32 v43, v51, v45 + v_sub_u32_e32 v39, v43, v39 + v_lshlrev_b32_e32 v39, 2, v39 + v_add3_u32 v39, v39, v31, v42 + v_xor_b32_e32 v45, v55, v40 + v_sub_u32_e32 v40, v45, v43 + v_lshlrev_b32_e32 v40, 2, v40 + v_add3_u32 v40, v40, v30, v39 + v_add_u32_e32 v43, 0x80, v6 + v_lshrrev_b32_e32 v43, 4, v43 + v_xor_b32_e32 v47, v2, v43 + v_sub_u32_e32 v45, v47, v45 + v_lshlrev_b32_e32 v45, 2, v45 + v_add3_u32 v70, v45, v53, v40 + v_add_u32_e32 v45, 16, v43 + v_xor_b32_e32 v48, v2, v45 + v_sub_u32_e32 v47, v48, v47 + v_lshl_add_u32 v72, v47, 2, v70 + v_xor_b32_e32 v47, v29, v43 + v_sub_u32_e32 v48, v47, v48 + v_lshlrev_b32_e32 v48, 2, v48 + v_add3_u32 v50, v48, v28, v72 + v_xor_b32_e32 v48, v32, v45 + v_sub_u32_e32 v47, v48, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v52, v47, v26, v50 + v_xor_b32_e32 v54, v13, v43 + v_sub_u32_e32 v47, v54, v48 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v47, v47, v27, v52 + v_xor_b32_e32 v56, v49, v45 + v_sub_u32_e32 v48, v56, v54 + v_lshlrev_b32_e32 v48, 2, v48 + v_add3_u32 v48, v48, v33, v47 + v_xor_b32_e32 v54, v51, v43 + v_sub_u32_e32 v43, v54, v56 + v_lshlrev_b32_e32 v43, 2, v43 + v_add3_u32 v43, v43, v31, v48 + v_xor_b32_e32 v56, v55, v45 + v_sub_u32_e32 v45, v56, v54 + v_lshlrev_b32_e32 v45, 2, v45 + v_add3_u32 v45, v45, v30, v43 + v_add_u32_e32 v54, 0xc0, v6 + v_lshrrev_b32_e32 v58, 4, v54 + v_xor_b32_e32 v54, v2, v58 + v_sub_u32_e32 v56, v54, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v67, v56, v53, v45 + v_add_u32_e32 v59, 16, v58 + v_xor_b32_e32 v53, v2, v59 + v_sub_u32_e32 v54, v53, v54 + v_lshl_add_u32 v69, v54, 2, v67 + v_xor_b32_e32 v29, v29, v58 + v_sub_u32_e32 v53, v29, v53 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v56, v53, v28, v69 + v_xor_b32_e32 v28, v32, v59 + v_sub_u32_e32 v29, v28, v29 + v_lshlrev_b32_e32 v29, 2, v29 + v_add3_u32 v57, v29, v26, v56 + v_xor_b32_e32 v26, v13, v58 + v_sub_u32_e32 v28, v26, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v53, v28, v27, v57 + v_xor_b32_e32 v27, v49, v59 + v_sub_u32_e32 v26, v27, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v54, v26, v33, v53 + v_xor_b32_e32 v26, v51, v58 + v_sub_u32_e32 v27, v26, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v49, v27, v31, v54 + v_xor_b32_e32 v27, v55, v59 + v_sub_u32_e32 v26, v27, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v51, v26, v30, v49 + v_xor_b32_e32 v26, v4, v12 + v_lshl_add_u32 v65, v26, 3, v5 + v_xor_b32_e32 v27, v4, v11 + v_lshl_add_u32 v60, v27, 3, v5 + v_xor_b32_e32 v28, v4, v10 + v_lshl_add_u32 v55, v28, 3, v5 + v_sub_u32_e32 v29, v3, v28 + v_mov_b32_e32 v30, 0x1000 + v_lshl_add_u32 v29, v29, 3, v30 + v_add_u32_e32 v79, v29, v55 + v_sub_u32_e32 v26, v26, v3 + v_lshlrev_b32_e32 v26, 3, v26 + v_add_u32_e32 v68, v79, v26 + v_sub_u32_e32 v27, v27, v3 + v_lshlrev_b32_e32 v27, 3, v27 + v_add_u32_e32 v62, v79, v27 + v_sub_u32_e32 v28, v28, v3 + v_lshlrev_b32_e32 v28, 3, v28 + v_add_u32_e32 v58, v79, v28 + v_add_u32_e32 v80, v58, v29 + v_add_u32_e32 v73, v80, v26 + v_add_u32_e32 v63, v80, v27 + v_add_u32_e32 v59, v80, v28 + v_add_u32_e32 v78, v59, v29 + v_add_u32_e32 v75, v78, v26 + v_add_u32_e32 v66, v78, v27 + v_add_u32_e32 v61, v78, v28 + s_mov_b64 s[2:3], 0 + s_branch .LBB33_6 +.LBB33_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr35 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr34 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr61 +.LBB33_6: ; %Flow98 + v_lshl_add_u32 v77, v25, 2, v9 + v_lshl_or_b32 v76, v3, 3, v5 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_cbranch_vccnz .LBB33_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_xor_b32_e32 v19, v2, v15 + v_sub_u32_e32 v8, v14, v8 + v_lshlrev_b32_e32 v8, 12, v8 + v_lshlrev_b32_e32 v25, 2, v19 + v_add3_u32 v64, v25, v9, v8 + v_lshrrev_b32_e32 v8, 5, v24 + v_lshrrev_b16_e32 v9, 3, v24 + v_and_b32_e32 v9, 3, v9 + v_sub_u16_e32 v24, v9, v14 + v_bfe_i32 v24, v24, 0, 16 + v_lshl_or_b32 v25, v8, 4, v2 + v_xor_b32_e32 v26, v25, v7 + v_sub_u32_e32 v19, v26, v19 + v_lshlrev_b32_e32 v27, 11, v8 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshl_or_b32 v24, v24, 12, v27 + v_add3_u32 v35, v24, v64, v19 + v_lshrrev_b32_e32 v19, 5, v23 + v_sub_u32_e32 v8, v19, v8 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v9, v23, v9 + v_bfe_i32 v9, v9, 0, 16 + v_lshl_or_b32 v27, v19, 4, v2 + v_xor_b32_e32 v28, v27, v15 + v_sub_u32_e32 v26, v28, v26 + v_lshlrev_b32_e32 v8, 11, v8 + v_lshlrev_b32_e32 v26, 2, v26 + v_lshl_add_u32 v8, v9, 12, v8 + v_add3_u32 v37, v26, v8, v35 + v_sub_u16_e32 v9, v14, v23 + v_bfe_i32 v9, v9, 0, 16 + v_xor_b32_e32 v23, v13, v7 + v_sub_u32_e32 v26, v23, v28 + v_lshlrev_b32_e32 v19, 11, v19 + v_xor_b32_e32 v19, 0x800, v19 + v_lshlrev_b32_e32 v26, 2, v26 + v_lshl_or_b32 v9, v9, 12, v19 + v_add3_u32 v19, v26, v9, v37 + v_lshrrev_b32_e32 v26, 5, v22 + v_lshlrev_b32_e32 v28, 11, v26 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v29, v22, v14 + v_lshl_or_b32 v30, v26, 4, v2 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v31, v30, v15 + v_sub_u32_e32 v23, v31, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_mov_b32_e32 v32, 12 + v_lshlrev_b32_sdwa v29, v32, sext(v29) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v28, v28, v29, s6 + v_add3_u32 v36, v23, v28, v19 + v_lshrrev_b32_e32 v23, 5, v21 + v_sub_u32_e32 v26, v23, v26 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v22, v21, v22 + v_bfe_i32 v22, v22, 0, 16 + v_lshl_or_b32 v29, v23, 4, v2 + v_and_b32_e32 v29, 31, v29 + v_xor_b32_e32 v7, v29, v7 + v_sub_u32_e32 v31, v7, v31 + v_lshlrev_b32_e32 v26, 11, v26 + v_lshlrev_b32_e32 v31, 2, v31 + v_lshl_add_u32 v22, v22, 12, v26 + v_add3_u32 v34, v31, v22, v36 + v_lshrrev_b32_e32 v26, 5, v17 + v_sub_u32_e32 v23, v26, v23 + v_lshrrev_b16_e32 v17, 3, v17 + v_and_b32_e32 v17, 3, v17 + v_sub_u16_e32 v21, v17, v21 + v_bfe_i32 v21, v21, 0, 16 + v_lshl_or_b32 v31, v26, 4, v2 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v15, v31, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v23, 11, v23 + v_lshlrev_b32_e32 v7, 2, v7 + v_lshl_add_u32 v21, v21, 12, v23 + v_add3_u32 v38, v7, v21, v34 + v_lshrrev_b32_e32 v7, 4, v16 + v_sub_u16_e32 v14, v14, v17 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_lshlrev_b32_sdwa v14, v32, sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v17, 11, v26 + v_sub_u32_e32 v14, v14, v17 + v_add3_u32 v71, v15, v14, v38 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v74, v16, 2, v71 + v_xor_b32_e32 v16, v25, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v44, v17, v24, v74 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v46, v16, v8, v44 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v41, v17, v9, v46 + v_xor_b32_e32 v17, v30, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v42, v16, v28, v41 + v_xor_b32_e32 v7, v29, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v39, v16, v22, v42 + v_xor_b32_e32 v15, v31, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v40, v7, v21, v39 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v7, 0x80, v6 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v16, v2, v7 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v70, v15, v14, v40 + v_add_u32_e32 v15, 16, v7 + v_xor_b32_e32 v17, v2, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshl_add_u32 v72, v16, 2, v70 + v_xor_b32_e32 v16, v25, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v50, v17, v24, v72 + v_xor_b32_e32 v17, v27, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v52, v16, v8, v50 + v_xor_b32_e32 v16, v13, v7 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v47, v17, v9, v52 + v_xor_b32_e32 v17, v30, v15 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v48, v16, v28, v47 + v_xor_b32_e32 v7, v29, v7 + v_sub_u32_e32 v16, v7, v17 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v43, v16, v22, v48 + v_xor_b32_e32 v15, v31, v15 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v45, v7, v21, v43 + v_add_u32_e32 v6, 0xc0, v6 + v_lshrrev_b32_e32 v6, 4, v6 + v_xor_b32_e32 v7, v2, v6 + v_sub_u32_e32 v15, v7, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v67, v15, v14, v45 + v_add_u32_e32 v14, 16, v6 + v_xor_b32_e32 v2, v2, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshl_add_u32 v69, v7, 2, v67 + v_xor_b32_e32 v7, v25, v6 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v56, v2, v24, v69 + v_xor_b32_e32 v2, v27, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v57, v7, v8, v56 + v_xor_b32_e32 v7, v13, v6 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v53, v2, v9, v57 + v_xor_b32_e32 v2, v30, v14 + v_sub_u32_e32 v7, v2, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v54, v7, v28, v53 + v_xor_b32_e32 v6, v29, v6 + v_sub_u32_e32 v2, v6, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v49, v2, v22, v54 + v_xor_b32_e32 v2, v31, v14 + v_sub_u32_e32 v2, v2, v6 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v51, v2, v21, v49 + v_xor_b32_e32 v2, v4, v12 + v_lshl_add_u32 v65, v2, 3, v5 + v_xor_b32_e32 v6, v4, v11 + v_lshl_add_u32 v60, v6, 3, v5 + v_xor_b32_e32 v4, v4, v10 + v_lshl_add_u32 v55, v4, 3, v5 + v_sub_u32_e32 v5, v3, v4 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v7, 0x1000, v5 + v_add_u32_e32 v79, v7, v55 + v_add_u32_e32 v87, v5, v55 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v68, v79, v2 + v_add_u32_e32 v88, v87, v2 + v_sub_u32_e32 v5, v6, v3 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v62, v79, v5 + v_add_u32_e32 v89, v87, v5 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v58, v79, v3 + v_add_u32_e32 v90, v87, v3 + v_add_u32_e32 v80, v58, v7 + v_add_u32_e32 v91, v90, v7 + v_add_u32_e32 v73, v80, v2 + v_add_u32_e32 v63, v80, v5 + v_add_u32_e32 v59, v80, v3 + v_add_u32_e32 v78, v59, v7 + v_add_u32_e32 v75, v78, v2 + v_add_u32_e32 v66, v78, v5 + v_add_u32_e32 v61, v78, v3 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_mov_b32_e32 v92, 0x80 +.LBB33_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1478.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v93, 64, v20 + v_add_u32_e32 v18, s2, v18 + buffer_load_dwordx4 v[94:97], v20, s[12:15], 0 offen offset:64 + v_add_u32_e32 v2, s7, v18 + v_add_u32_e32 v3, s22, v93 + buffer_load_dwordx4 v[10:13], v18, s[8:11], 0 offen + buffer_load_dwordx4 v[6:9], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[98:101], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + v_add_u32_e32 v4, s7, v2 + buffer_load_dwordx4 v[102:105], v3, s[12:15], 0 offen + v_add_u32_e32 v20, s22, v3 + buffer_load_dwordx4 v[14:17], v2, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v4, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[106:109], v20, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v111, v64 + ds_read_b32 v110, v77 + ds_read_b64 v[28:29], v76 offset:16384 + ds_read_b64 v[26:27], v87 offset:20480 + ds_read_b64 v[20:21], v88 offset:20480 + ds_read_b64 v[24:25], v91 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[0:15], v[110:111], v[28:29], a[0:15] + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[80:95], v[110:111], v[26:27], a[80:95] + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[96:111], v[110:111], v[24:25], a[96:111] + ds_read_b64 v[32:33], v80 offset:20480 + ds_read_b32 v112, v71 + ds_read_b64 v[30:31], v73 offset:20480 + ds_read_b64 v[22:23], v63 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[112:127], v[110:111], v[32:33], a[112:127] + ds_read_b32 v113, v74 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[128:143], v[112:113], v[28:29], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[112:113], v[26:27], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[112:113], v[24:25], a[160:175] + ds_read_b32 v110, v70 + v_mfma_i32_32x32x16_i8 a[176:191], v[112:113], v[32:33], a[176:191] + ds_read_b32 v111, v72 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[110:111], v[28:29], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[110:111], v[26:27], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[110:111], v[24:25], a[224:239] + ds_read_b32 v112, v67 + v_mfma_i32_32x32x16_i8 a[240:255], v[110:111], v[32:33], a[240:255] + ds_read_b32 v113, v69 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[64:79], v[112:113], v[28:29], a[64:79] + v_mfma_i32_32x32x16_i8 a[48:63], v[112:113], v[26:27], a[48:63] + v_mfma_i32_32x32x16_i8 a[32:47], v[112:113], v[24:25], a[32:47] + ds_read_b32 v110, v35 + v_mfma_i32_32x32x16_i8 a[16:31], v[112:113], v[32:33], a[16:31] + ds_read_b32 v111, v37 + ds_read_b64 v[24:25], v65 offset:16384 + ds_read_b32 v118, v19 + ds_read_b32 v119, v36 + ds_read_b32 v116, v34 + ds_read_b32 v117, v38 + s_waitcnt lgkmcnt(4) + v_mfma_i32_32x32x16_i8 a[0:15], v[110:111], v[24:25], a[0:15] + v_mfma_i32_32x32x16_i8 a[80:95], v[110:111], v[20:21], a[80:95] + ds_read_b64 v[26:27], v68 offset:20480 + ds_read_b64 v[28:29], v62 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[96:111], v[110:111], v[26:27], a[96:111] + ds_read_b32 v32, v44 + v_mfma_i32_32x32x16_i8 a[112:127], v[110:111], v[30:31], a[112:127] + ds_read_b32 v33, v46 + ds_read_b32 v120, v41 + ds_read_b32 v121, v42 + ds_read_b32 v114, v39 + ds_read_b32 v115, v40 + s_waitcnt lgkmcnt(4) + v_mfma_i32_32x32x16_i8 a[128:143], v[32:33], v[24:25], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[32:33], v[20:21], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[32:33], v[26:27], a[160:175] + ds_read_b32 v110, v50 + v_mfma_i32_32x32x16_i8 a[176:191], v[32:33], v[30:31], a[176:191] + ds_read_b32 v111, v52 + ds_read_b32 v132, v47 + ds_read_b32 v133, v48 + ds_read_b32 v112, v43 + ds_read_b32 v113, v45 + s_waitcnt lgkmcnt(4) + v_mfma_i32_32x32x16_i8 a[192:207], v[110:111], v[24:25], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[110:111], v[20:21], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[110:111], v[26:27], a[224:239] + ds_read_b32 v32, v56 + v_mfma_i32_32x32x16_i8 a[240:255], v[110:111], v[30:31], a[240:255] + ds_read_b32 v33, v57 + ds_read_b32 v146, v53 + ds_read_b32 v147, v54 + ds_read_b32 v110, v49 + ds_read_b32 v111, v51 + s_waitcnt lgkmcnt(4) + v_mfma_i32_32x32x16_i8 a[64:79], v[32:33], v[24:25], a[64:79] + v_mfma_i32_32x32x16_i8 a[48:63], v[32:33], v[20:21], a[48:63] + v_mfma_i32_32x32x16_i8 a[32:47], v[32:33], v[26:27], a[32:47] + v_mfma_i32_32x32x16_i8 a[16:31], v[32:33], v[30:31], a[16:31] + ds_read_b64 v[32:33], v60 offset:16384 + ds_read_b64 v[26:27], v55 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[118:119], v[32:33], a[0:15] + ds_read_b64 v[30:31], v89 offset:20480 + ds_read_b64 v[24:25], v90 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[80:95], v[118:119], v[30:31], a[80:95] + v_mfma_i32_32x32x16_i8 a[96:111], v[118:119], v[28:29], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[118:119], v[22:23], a[112:127] + v_mfma_i32_32x32x16_i8 a[128:143], v[120:121], v[32:33], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[120:121], v[30:31], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[120:121], v[28:29], a[160:175] + s_add_i32 s26, s3, -1 + v_mfma_i32_32x32x16_i8 a[176:191], v[120:121], v[22:23], a[176:191] + v_readfirstlane_b32 s27, v0 + s_lshr_b32 s28, s27, 2 + s_andn2_b32 s27, s27, 63 + s_and_b32 s28, s28, 0x3ffffff0 + v_add_u32_e32 v21, s27, v83 + v_mov_b32_e32 v20, v93 + v_add_u32_e32 v93, s28, v81 + v_mfma_i32_32x32x16_i8 a[192:207], v[132:133], v[32:33], a[192:207] + v_ashrrev_i32_e32 v122, 1, v21 + v_ashrrev_i32_e32 v123, 31, v21 + v_lshlrev_b32_e32 v124, 6, v21 + v_or_b32_e32 v125, 1, v21 + v_lshrrev_b32_e32 v126, 31, v21 + v_or_b32_e32 v21, 3, v21 + s_cmp_gt_u32 s3, 2 + v_mfma_i32_32x32x16_i8 a[208:223], v[132:133], v[30:31], a[208:223] + s_mov_b32 s3, s26 + ds_read_b64 v[118:119], v58 offset:20480 + ds_read_b64 v[120:121], v59 offset:20480 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v127, 1, v93 + v_lshlrev_b32_e32 v128, 9, v93 + v_mfma_i32_32x32x16_i8 a[224:239], v[132:133], v[28:29], a[224:239] + v_lshlrev_b32_e32 v93, 6, v93 + v_lshrrev_b32_e32 v123, 28, v123 + v_add_u32_e32 v129, v125, v126 + v_or_b32_e32 v130, 1, v122 + v_add_u32_e32 v126, v21, v126 + v_and_b32_e32 v127, 16, v127 + v_and_b32_e32 v128, 0x3000, v128 + v_mfma_i32_32x32x16_i8 a[240:255], v[132:133], v[22:23], a[240:255] + v_and_b32_e32 v93, 0xfffff800, v93 + v_add_u32_e32 v131, v122, v123 + v_ashrrev_i32_e32 v132, 1, v129 + v_and_b32_e32 v133, 0x1ffffffe, v129 + v_ashrrev_i32_e32 v129, 31, v129 + v_add_u32_e32 v123, v130, v123 + v_ashrrev_i32_e32 v134, 1, v126 + v_mfma_i32_32x32x16_i8 a[64:79], v[146:147], v[32:33], a[64:79] + v_and_b32_e32 v32, 0x1ffffffe, v126 + v_ashrrev_i32_e32 v33, 31, v126 + v_xor_b32_e32 v126, v127, v82 + v_add_u32_e32 v93, v128, v93 + v_or_b32_e32 v128, 1, v127 + v_or_b32_e32 v135, 2, v127 + v_or_b32_e32 v136, 3, v127 + v_mfma_i32_32x32x16_i8 a[48:63], v[146:147], v[30:31], a[48:63] + v_or_b32_e32 v30, 4, v127 + v_or_b32_e32 v31, 5, v127 + v_or_b32_e32 v137, 6, v127 + v_or_b32_e32 v138, 7, v127 + v_or_b32_e32 v139, 8, v127 + v_or_b32_e32 v140, 9, v127 + v_or_b32_e32 v141, 10, v127 + v_mfma_i32_32x32x16_i8 a[32:47], v[146:147], v[28:29], a[32:47] + v_or_b32_e32 v28, 11, v127 + v_or_b32_e32 v29, 12, v127 + v_or_b32_e32 v142, 13, v127 + v_or_b32_e32 v143, 14, v127 + v_or_b32_e32 v127, 15, v127 + v_and_b32_e32 v131, -16, v131 + v_sub_u32_e32 v144, v132, v122 + v_mfma_i32_32x32x16_i8 a[16:31], v[146:147], v[22:23], a[16:31] + v_sub_u32_e32 v22, v125, v133 + v_lshrrev_b32_e32 v23, 28, v129 + v_sub_u32_e32 v125, v130, v132 + v_and_b32_e32 v123, -16, v123 + v_sub_u32_e32 v129, v134, v130 + v_sub_u32_e32 v21, v21, v32 + v_lshrrev_b32_e32 v32, 28, v33 + v_mfma_i32_32x32x16_i8 a[0:15], v[116:117], v[26:27], a[0:15] + v_lshl_or_b32 v33, v126, 2, v93 + v_xor_b32_e32 v93, v128, v82 + v_xor_b32_e32 v128, v135, v82 + v_xor_b32_e32 v133, v136, v82 + v_xor_b32_e32 v30, v30, v82 + v_xor_b32_e32 v31, v31, v82 + v_xor_b32_e32 v135, v137, v82 + v_mfma_i32_32x32x16_i8 a[80:95], v[116:117], v[24:25], a[80:95] + v_xor_b32_e32 v136, v138, v82 + v_xor_b32_e32 v137, v139, v82 + v_xor_b32_e32 v138, v140, v82 + v_xor_b32_e32 v139, v141, v82 + v_xor_b32_e32 v28, v28, v82 + v_xor_b32_e32 v29, v29, v82 + v_xor_b32_e32 v140, v142, v82 + v_mfma_i32_32x32x16_i8 a[96:111], v[116:117], v[118:119], a[96:111] + v_xor_b32_e32 v141, v143, v82 + v_xor_b32_e32 v127, v127, v82 + v_sub_u32_e32 v122, v122, v131 + v_lshl_or_b32 v22, v22, 3, v85 + v_add_u32_e32 v23, v132, v23 + v_sub_u32_e32 v123, v130, v123 + v_lshlrev_b32_e32 v125, 7, v125 + v_mfma_i32_32x32x16_i8 a[112:127], v[116:117], v[120:121], a[112:127] + v_lshl_or_b32 v21, v21, 3, v85 + v_add_u32_e32 v32, v134, v32 + v_lshlrev_b32_e32 v116, 7, v129 + v_sub_u32_e32 v117, v93, v126 + v_sub_u32_e32 v93, v128, v93 + v_sub_u32_e32 v126, v133, v128 + v_sub_u32_e32 v128, v30, v133 + v_mfma_i32_32x32x16_i8 a[128:143], v[114:115], v[26:27], a[128:143] + v_sub_u32_e32 v30, v31, v30 + v_sub_u32_e32 v31, v135, v31 + v_sub_u32_e32 v129, v136, v135 + v_sub_u32_e32 v130, v137, v136 + v_sub_u32_e32 v131, v138, v137 + v_sub_u32_e32 v133, v139, v138 + v_sub_u32_e32 v135, v28, v139 + v_mfma_i32_32x32x16_i8 a[144:159], v[114:115], v[24:25], a[144:159] + v_sub_u32_e32 v28, v29, v28 + v_sub_u32_e32 v29, v140, v29 + v_sub_u32_e32 v136, v141, v140 + v_sub_u32_e32 v127, v127, v141 + v_xor_b32_e32 v137, v122, v84 + v_xor_b32_e32 v122, v122, v85 + v_add_u32_e32 v138, v22, v86 + v_mfma_i32_32x32x16_i8 a[160:175], v[114:115], v[118:119], a[160:175] + v_and_b32_e32 v23, -16, v23 + v_xor_b32_e32 v139, v123, v84 + v_xor_b32_e32 v123, v123, v85 + v_add_u32_e32 v140, v21, v86 + v_and_b32_e32 v32, -16, v32 + v_lshl_add_u32 v117, v117, 2, v33 + v_lshl_add_u32 v93, v93, 2, v92 + v_mfma_i32_32x32x16_i8 a[176:191], v[114:115], v[120:121], a[176:191] + v_lshl_add_u32 v114, v126, 2, v92 + v_lshl_add_u32 v115, v128, 2, v92 + v_lshl_add_u32 v30, v30, 2, v92 + v_lshl_add_u32 v31, v31, 2, v92 + v_lshl_add_u32 v126, v129, 2, v92 + v_lshl_add_u32 v128, v130, 2, v92 + v_lshl_add_u32 v129, v131, 2, v92 + v_mfma_i32_32x32x16_i8 a[192:207], v[112:113], v[26:27], a[192:207] + v_lshl_add_u32 v130, v133, 2, v92 + v_lshl_add_u32 v131, v135, 2, v92 + v_lshl_add_u32 v28, v28, 2, v92 + v_lshl_add_u32 v29, v29, 2, v92 + v_lshlrev_b32_e32 v133, 2, v136 + v_lshlrev_b32_e32 v127, 2, v127 + v_lshl_add_u32 v135, v137, 3, v124 + v_mfma_i32_32x32x16_i8 a[208:223], v[112:113], v[24:25], a[208:223] + v_lshl_add_u32 v124, v122, 3, v124 + v_sub_u32_e32 v23, v132, v23 + v_sub_u32_e32 v132, v123, v139 + v_sub_u32_e32 v32, v134, v32 + v_add3_u32 v134, v117, v93, v114 + v_add3_u32 v93, v117, s6, v93 + v_xor_b32_e32 v136, v138, v23 + v_mfma_i32_32x32x16_i8 a[224:239], v[112:113], v[118:119], a[224:239] + v_lshl_add_u32 v137, v144, 7, v124 + v_xor_b32_e32 v22, v22, v23 + v_xor_b32_e32 v23, v140, v32 + v_xor_b32_e32 v21, v21, v32 + v_add_u32_e32 v32, v114, v93 + v_add3_u32 v114, v134, v115, v30 + v_sub_u32_e32 v134, v136, v122 + v_mfma_i32_32x32x16_i8 a[240:255], v[112:113], v[120:121], a[240:255] + v_sub_u32_e32 v112, v22, v122 + v_sub_u32_e32 v22, v139, v22 + v_sub_u32_e32 v113, v23, v123 + v_sub_u32_e32 v21, v21, v23 + v_add_u32_e32 v23, v115, v32 + v_add3_u32 v114, v114, v31, v126 + v_lshl_add_u32 v115, v134, 3, v137 + v_mfma_i32_32x32x16_i8 a[64:79], v[110:111], v[26:27], a[64:79] + v_lshl_add_u32 v26, v112, 3, v137 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshlrev_b32_e32 v27, 3, v113 + v_add_u32_e32 v30, v30, v23 + v_add3_u32 v112, v114, v128, v129 + v_add3_u32 v22, v22, v125, v26 + v_add_u32_e32 v31, v31, v30 + v_mfma_i32_32x32x16_i8 a[48:63], v[110:111], v[24:25], a[48:63] + v_add3_u32 v24, v112, v130, v131 + v_lshl_add_u32 v25, v132, 3, v22 + v_add_u32_e32 v112, v126, v31 + v_add3_u32 v24, v24, v28, v29 + v_add3_u32 v27, v27, v116, v25 + v_add_u32_e32 v113, v128, v112 + v_add3_u32 v24, v24, v133, v127 + v_mfma_i32_32x32x16_i8 a[32:47], v[110:111], v[118:119], a[32:47] + v_lshl_add_u32 v21, v21, 3, v27 + v_add_u32_e32 v114, v129, v113 + v_add_u32_e32 v116, v130, v114 + v_add_u32_e32 v118, v131, v116 + v_add_u32_e32 v28, v28, v118 + v_add_u32_e32 v29, v29, v28 + v_add_u32_e32 v119, v29, v133 + v_mfma_i32_32x32x16_i8 a[16:31], v[110:111], v[120:121], a[16:31] + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + s_waitcnt vmcnt(5) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v14, v14, v14, s18 + v_perm_b32 v15, v15, v15, s18 + v_perm_b32 v16, v16, v16, s18 + v_perm_b32 v17, v17, v17, s18 + v_perm_b32 v110, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + s_waitcnt vmcnt(1) + v_perm_b32 v2, v2, v2, s18 + v_perm_b32 v3, v3, v3, s18 + v_perm_b32 v4, v4, v4, s18 + v_perm_b32 v5, v5, v5, s18 + v_perm_b32 v13, v2, v14, s19 + v_perm_b32 v2, v2, v14, s25 + v_perm_b32 v14, v3, v15, s19 + v_perm_b32 v3, v3, v15, s25 + v_perm_b32 v15, v4, v16, s19 + v_perm_b32 v4, v4, v16, s25 + v_perm_b32 v16, v5, v17, s19 + v_perm_b32 v5, v5, v17, s25 + v_perm_b32 v17, v13, v110, s23 + v_perm_b32 v13, v13, v110, s24 + v_perm_b32 v110, v2, v6, s23 + v_perm_b32 v2, v2, v6, s24 + v_perm_b32 v6, v14, v10, s23 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v3, v7, s23 + v_perm_b32 v3, v3, v7, s24 + v_perm_b32 v7, v15, v11, s23 + v_perm_b32 v11, v15, v11, s24 + v_perm_b32 v15, v4, v8, s23 + v_perm_b32 v4, v4, v8, s24 + v_perm_b32 v8, v16, v12, s23 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v5, v9, s23 + v_perm_b32 v5, v5, v9, s24 + ds_write_b32 v33, v17 + ds_write_b32 v117, v13 offset:128 + ds_write_b32 v93, v110 + ds_write_b32 v32, v2 + ds_write_b32 v23, v6 + ds_write_b32 v30, v10 + ds_write_b32 v31, v14 + ds_write_b32 v112, v3 + ds_write_b32 v113, v7 + ds_write_b32 v114, v11 + ds_write_b32 v116, v15 + ds_write_b32 v118, v4 + ds_write_b32 v28, v8 + ds_write_b32 v29, v12 + ds_write_b32 v119, v16 offset:128 + ds_write_b32 v24, v5 offset:384 + ds_write_b64 v135, v[94:95] offset:16384 + ds_write_b64 v124, v[96:97] offset:16384 + ds_write_b64 v115, v[98:99] offset:16384 + ds_write_b64 v26, v[100:101] offset:16384 + ds_write_b64 v22, v[102:103] offset:16384 + ds_write_b64 v25, v[104:105] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v27, v[106:107] offset:16384 + ds_write_b64 v21, v[108:109] offset:16384 + s_cbranch_scc1 .LBB33_8 +.LBB33_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDa + v_accvgpr_read_b32 v194, a0 + v_accvgpr_read_b32 v195, a1 + v_accvgpr_read_b32 v196, a2 + v_accvgpr_read_b32 v197, a3 + v_accvgpr_read_b32 v198, a4 + v_accvgpr_read_b32 v199, a5 + v_accvgpr_read_b32 v200, a6 + v_accvgpr_read_b32 v201, a7 + v_accvgpr_read_b32 v202, a8 + v_accvgpr_read_b32 v203, a9 + v_accvgpr_read_b32 v204, a10 + v_accvgpr_read_b32 v205, a11 + v_accvgpr_read_b32 v206, a12 + v_accvgpr_read_b32 v207, a13 + v_accvgpr_read_b32 v208, a14 + v_accvgpr_read_b32 v209, a15 + v_accvgpr_read_b32 v178, a80 + v_accvgpr_read_b32 v179, a81 + v_accvgpr_read_b32 v180, a82 + v_accvgpr_read_b32 v181, a83 + v_accvgpr_read_b32 v182, a84 + v_accvgpr_read_b32 v183, a85 + v_accvgpr_read_b32 v184, a86 + v_accvgpr_read_b32 v185, a87 + v_accvgpr_read_b32 v186, a88 + v_accvgpr_read_b32 v187, a89 + v_accvgpr_read_b32 v188, a90 + v_accvgpr_read_b32 v189, a91 + v_accvgpr_read_b32 v190, a92 + v_accvgpr_read_b32 v191, a93 + v_accvgpr_read_b32 v192, a94 + v_accvgpr_read_b32 v193, a95 + v_accvgpr_read_b32 v162, a96 + v_accvgpr_read_b32 v163, a97 + v_accvgpr_read_b32 v164, a98 + v_accvgpr_read_b32 v165, a99 + v_accvgpr_read_b32 v166, a100 + v_accvgpr_read_b32 v167, a101 + v_accvgpr_read_b32 v168, a102 + v_accvgpr_read_b32 v169, a103 + v_accvgpr_read_b32 v170, a104 + v_accvgpr_read_b32 v171, a105 + v_accvgpr_read_b32 v172, a106 + v_accvgpr_read_b32 v173, a107 + v_accvgpr_read_b32 v174, a108 + v_accvgpr_read_b32 v175, a109 + v_accvgpr_read_b32 v176, a110 + v_accvgpr_read_b32 v177, a111 + v_accvgpr_mov_b32 a0, a112 + v_accvgpr_mov_b32 a1, a113 + v_accvgpr_mov_b32 a2, a114 + v_accvgpr_mov_b32 a3, a115 + v_accvgpr_mov_b32 a4, a116 + v_accvgpr_mov_b32 a5, a117 + v_accvgpr_mov_b32 a6, a118 + v_accvgpr_mov_b32 a7, a119 + v_accvgpr_mov_b32 a8, a120 + v_accvgpr_mov_b32 a9, a121 + v_accvgpr_mov_b32 a10, a122 + v_accvgpr_mov_b32 a11, a123 + v_accvgpr_mov_b32 a12, a124 + v_accvgpr_mov_b32 a13, a125 + v_accvgpr_mov_b32 a14, a126 + v_accvgpr_mov_b32 a15, a127 + v_accvgpr_read_b32 v146, a128 + v_accvgpr_read_b32 v147, a129 + v_accvgpr_read_b32 v148, a130 + v_accvgpr_read_b32 v149, a131 + v_accvgpr_read_b32 v150, a132 + v_accvgpr_read_b32 v151, a133 + v_accvgpr_read_b32 v152, a134 + v_accvgpr_read_b32 v153, a135 + v_accvgpr_read_b32 v154, a136 + v_accvgpr_read_b32 v155, a137 + v_accvgpr_read_b32 v156, a138 + v_accvgpr_read_b32 v157, a139 + v_accvgpr_read_b32 v158, a140 + v_accvgpr_read_b32 v159, a141 + v_accvgpr_read_b32 v160, a142 + v_accvgpr_read_b32 v161, a143 + v_accvgpr_mov_b32 a128, a144 + v_accvgpr_mov_b32 a129, a145 + v_accvgpr_mov_b32 a130, a146 + v_accvgpr_mov_b32 a131, a147 + v_accvgpr_mov_b32 a132, a148 + v_accvgpr_mov_b32 a133, a149 + v_accvgpr_mov_b32 a134, a150 + v_accvgpr_mov_b32 a135, a151 + v_accvgpr_mov_b32 a136, a152 + v_accvgpr_mov_b32 a137, a153 + v_accvgpr_mov_b32 a138, a154 + v_accvgpr_mov_b32 a139, a155 + v_accvgpr_mov_b32 a140, a156 + v_accvgpr_mov_b32 a141, a157 + v_accvgpr_mov_b32 a142, a158 + v_accvgpr_mov_b32 a143, a159 + v_accvgpr_read_b32 v130, a160 + v_accvgpr_read_b32 v131, a161 + v_accvgpr_read_b32 v132, a162 + v_accvgpr_read_b32 v133, a163 + v_accvgpr_read_b32 v134, a164 + v_accvgpr_read_b32 v135, a165 + v_accvgpr_read_b32 v136, a166 + v_accvgpr_read_b32 v137, a167 + v_accvgpr_read_b32 v138, a168 + v_accvgpr_read_b32 v139, a169 + v_accvgpr_read_b32 v140, a170 + v_accvgpr_read_b32 v141, a171 + v_accvgpr_read_b32 v142, a172 + v_accvgpr_read_b32 v143, a173 + v_accvgpr_read_b32 v144, a174 + v_accvgpr_read_b32 v145, a175 + v_accvgpr_read_b32 v114, a176 + v_accvgpr_read_b32 v115, a177 + v_accvgpr_read_b32 v116, a178 + v_accvgpr_read_b32 v117, a179 + v_accvgpr_read_b32 v118, a180 + v_accvgpr_read_b32 v119, a181 + v_accvgpr_read_b32 v120, a182 + v_accvgpr_read_b32 v121, a183 + v_accvgpr_read_b32 v122, a184 + v_accvgpr_read_b32 v123, a185 + v_accvgpr_read_b32 v124, a186 + v_accvgpr_read_b32 v125, a187 + v_accvgpr_read_b32 v126, a188 + v_accvgpr_read_b32 v127, a189 + v_accvgpr_read_b32 v128, a190 + v_accvgpr_read_b32 v129, a191 + v_accvgpr_read_b32 v98, a192 + v_accvgpr_read_b32 v99, a193 + v_accvgpr_read_b32 v100, a194 + v_accvgpr_read_b32 v101, a195 + v_accvgpr_read_b32 v102, a196 + v_accvgpr_read_b32 v103, a197 + v_accvgpr_read_b32 v104, a198 + v_accvgpr_read_b32 v105, a199 + v_accvgpr_read_b32 v106, a200 + v_accvgpr_read_b32 v107, a201 + v_accvgpr_read_b32 v108, a202 + v_accvgpr_read_b32 v109, a203 + v_accvgpr_read_b32 v110, a204 + v_accvgpr_read_b32 v111, a205 + v_accvgpr_read_b32 v112, a206 + v_accvgpr_read_b32 v113, a207 + v_accvgpr_mov_b32 a144, a208 + v_accvgpr_mov_b32 a145, a209 + v_accvgpr_mov_b32 a146, a210 + v_accvgpr_mov_b32 a147, a211 + v_accvgpr_mov_b32 a148, a212 + v_accvgpr_mov_b32 a149, a213 + v_accvgpr_mov_b32 a150, a214 + v_accvgpr_mov_b32 a151, a215 + v_accvgpr_mov_b32 a152, a216 + v_accvgpr_mov_b32 a153, a217 + v_accvgpr_mov_b32 a154, a218 + v_accvgpr_mov_b32 a155, a219 + v_accvgpr_mov_b32 a156, a220 + v_accvgpr_mov_b32 a157, a221 + v_accvgpr_mov_b32 a158, a222 + v_accvgpr_mov_b32 a159, a223 + v_accvgpr_mov_b32 a80, a224 + v_accvgpr_mov_b32 a81, a225 + v_accvgpr_mov_b32 a82, a226 + v_accvgpr_mov_b32 a83, a227 + v_accvgpr_mov_b32 a84, a228 + v_accvgpr_mov_b32 a85, a229 + v_accvgpr_mov_b32 a86, a230 + v_accvgpr_mov_b32 a87, a231 + v_accvgpr_mov_b32 a88, a232 + v_accvgpr_mov_b32 a89, a233 + v_accvgpr_mov_b32 a90, a234 + v_accvgpr_mov_b32 a91, a235 + v_accvgpr_mov_b32 a92, a236 + v_accvgpr_mov_b32 a93, a237 + v_accvgpr_mov_b32 a94, a238 + v_accvgpr_mov_b32 a95, a239 + v_accvgpr_read_b32 v82, a240 + v_accvgpr_read_b32 v83, a241 + v_accvgpr_read_b32 v84, a242 + v_accvgpr_read_b32 v85, a243 + v_accvgpr_read_b32 v86, a244 + v_accvgpr_read_b32 v87, a245 + v_accvgpr_read_b32 v88, a246 + v_accvgpr_read_b32 v89, a247 + v_accvgpr_read_b32 v90, a248 + v_accvgpr_read_b32 v91, a249 + v_accvgpr_read_b32 v92, a250 + v_accvgpr_read_b32 v93, a251 + v_accvgpr_read_b32 v94, a252 + v_accvgpr_read_b32 v95, a253 + v_accvgpr_read_b32 v96, a254 + v_accvgpr_read_b32 v97, a255 + v_accvgpr_mov_b32 a224, a64 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a160, a48 + v_accvgpr_mov_b32 a161, a49 + v_accvgpr_mov_b32 a162, a50 + v_accvgpr_mov_b32 a163, a51 + v_accvgpr_mov_b32 a164, a52 + v_accvgpr_mov_b32 a165, a53 + v_accvgpr_mov_b32 a166, a54 + v_accvgpr_mov_b32 a167, a55 + v_accvgpr_mov_b32 a168, a56 + v_accvgpr_mov_b32 a169, a57 + v_accvgpr_mov_b32 a170, a58 + v_accvgpr_mov_b32 a171, a59 + v_accvgpr_mov_b32 a172, a60 + v_accvgpr_mov_b32 a173, a61 + v_accvgpr_mov_b32 a174, a62 + v_accvgpr_mov_b32 a175, a63 + v_accvgpr_mov_b32 a96, a32 + v_accvgpr_mov_b32 a97, a33 + v_accvgpr_mov_b32 a98, a34 + v_accvgpr_mov_b32 a99, a35 + v_accvgpr_mov_b32 a100, a36 + v_accvgpr_mov_b32 a101, a37 + v_accvgpr_mov_b32 a102, a38 + v_accvgpr_mov_b32 a103, a39 + v_accvgpr_mov_b32 a104, a40 + v_accvgpr_mov_b32 a105, a41 + v_accvgpr_mov_b32 a106, a42 + v_accvgpr_mov_b32 a107, a43 + v_accvgpr_mov_b32 a108, a44 + v_accvgpr_mov_b32 a109, a45 + v_accvgpr_mov_b32 a110, a46 + v_accvgpr_mov_b32 a111, a47 + v_accvgpr_mov_b32 a240, a16 + v_accvgpr_mov_b32 a241, a17 + v_accvgpr_mov_b32 a242, a18 + v_accvgpr_mov_b32 a243, a19 + v_accvgpr_mov_b32 a244, a20 + v_accvgpr_mov_b32 a245, a21 + v_accvgpr_mov_b32 a246, a22 + v_accvgpr_mov_b32 a247, a23 + v_accvgpr_mov_b32 a248, a24 + v_accvgpr_mov_b32 a249, a25 + v_accvgpr_mov_b32 a250, a26 + v_accvgpr_mov_b32 a251, a27 + v_accvgpr_mov_b32 a252, a28 + v_accvgpr_mov_b32 a253, a29 + v_accvgpr_mov_b32 a254, a30 + v_accvgpr_mov_b32 a255, a31 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v10, v77 + ds_read_b32 v11, v64 + ds_read_b64 v[2:3], v76 offset:16384 + v_accvgpr_write_b32 a176, v194 + v_accvgpr_write_b32 a177, v195 + v_accvgpr_write_b32 a178, v196 + v_accvgpr_write_b32 a179, v197 + v_accvgpr_write_b32 a180, v198 + v_accvgpr_write_b32 a181, v199 + v_accvgpr_write_b32 a182, v200 + v_accvgpr_write_b32 a183, v201 + v_accvgpr_write_b32 a184, v202 + v_accvgpr_write_b32 a185, v203 + v_accvgpr_write_b32 a186, v204 + v_accvgpr_write_b32 a187, v205 + v_accvgpr_write_b32 a188, v206 + v_accvgpr_write_b32 a189, v207 + v_accvgpr_write_b32 a190, v208 + v_accvgpr_write_b32 a191, v209 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[10:11], v[2:3], a[176:191] + ds_read_b64 v[4:5], v79 offset:16384 + v_accvgpr_write_b32 a112, v178 + v_accvgpr_write_b32 a113, v179 + v_accvgpr_write_b32 a114, v180 + v_accvgpr_write_b32 a115, v181 + v_accvgpr_write_b32 a116, v182 + v_accvgpr_write_b32 a117, v183 + v_accvgpr_write_b32 a118, v184 + v_accvgpr_write_b32 a119, v185 + v_accvgpr_write_b32 a120, v186 + v_accvgpr_write_b32 a121, v187 + v_accvgpr_write_b32 a122, v188 + v_accvgpr_write_b32 a123, v189 + v_accvgpr_write_b32 a124, v190 + v_accvgpr_write_b32 a125, v191 + v_accvgpr_write_b32 a126, v192 + v_accvgpr_write_b32 a127, v193 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[112:127], v[10:11], v[4:5], a[112:127] + ds_read_b64 v[6:7], v80 offset:16384 + v_accvgpr_write_b32 a48, v162 + v_accvgpr_write_b32 a49, v163 + v_accvgpr_write_b32 a50, v164 + v_accvgpr_write_b32 a51, v165 + v_accvgpr_write_b32 a52, v166 + v_accvgpr_write_b32 a53, v167 + v_accvgpr_write_b32 a54, v168 + v_accvgpr_write_b32 a55, v169 + v_accvgpr_write_b32 a56, v170 + v_accvgpr_write_b32 a57, v171 + v_accvgpr_write_b32 a58, v172 + v_accvgpr_write_b32 a59, v173 + v_accvgpr_write_b32 a60, v174 + v_accvgpr_write_b32 a61, v175 + v_accvgpr_write_b32 a62, v176 + v_accvgpr_write_b32 a63, v177 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[48:63], v[10:11], v[6:7], a[48:63] + ds_read_b64 v[8:9], v78 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[10:11], v[8:9], a[0:15] + ds_read_b32 v10, v71 + ds_read_b32 v11, v74 + v_accvgpr_write_b32 a207, v161 + v_accvgpr_write_b32 a206, v160 + v_accvgpr_write_b32 a205, v159 + v_accvgpr_write_b32 a204, v158 + v_accvgpr_write_b32 a203, v157 + v_accvgpr_write_b32 a202, v156 + v_accvgpr_write_b32 a201, v155 + v_accvgpr_write_b32 a200, v154 + v_accvgpr_write_b32 a199, v153 + v_accvgpr_write_b32 a198, v152 + v_accvgpr_write_b32 a197, v151 + v_accvgpr_write_b32 a196, v150 + v_accvgpr_write_b32 a195, v149 + v_accvgpr_write_b32 a194, v148 + v_accvgpr_write_b32 a193, v147 + v_accvgpr_write_b32 a192, v146 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[4:5], a[128:143] + v_accvgpr_write_b32 a64, v130 + v_accvgpr_write_b32 a65, v131 + v_accvgpr_write_b32 a66, v132 + v_accvgpr_write_b32 a67, v133 + v_accvgpr_write_b32 a68, v134 + v_accvgpr_write_b32 a69, v135 + v_accvgpr_write_b32 a70, v136 + v_accvgpr_write_b32 a71, v137 + v_accvgpr_write_b32 a72, v138 + v_accvgpr_write_b32 a73, v139 + v_accvgpr_write_b32 a74, v140 + v_accvgpr_write_b32 a75, v141 + v_accvgpr_write_b32 a76, v142 + v_accvgpr_write_b32 a77, v143 + v_accvgpr_write_b32 a78, v144 + v_accvgpr_write_b32 a79, v145 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[6:7], a[64:79] + v_accvgpr_write_b32 a16, v114 + v_accvgpr_write_b32 a17, v115 + v_accvgpr_write_b32 a18, v116 + v_accvgpr_write_b32 a19, v117 + v_accvgpr_write_b32 a20, v118 + v_accvgpr_write_b32 a21, v119 + v_accvgpr_write_b32 a22, v120 + v_accvgpr_write_b32 a23, v121 + v_accvgpr_write_b32 a24, v122 + v_accvgpr_write_b32 a25, v123 + v_accvgpr_write_b32 a26, v124 + v_accvgpr_write_b32 a27, v125 + v_accvgpr_write_b32 a28, v126 + v_accvgpr_write_b32 a29, v127 + v_accvgpr_write_b32 a30, v128 + v_accvgpr_write_b32 a31, v129 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[8:9], a[16:31] + ds_read_b32 v10, v70 + ds_read_b32 v11, v72 + v_accvgpr_write_b32 a223, v113 + v_accvgpr_write_b32 a222, v112 + v_accvgpr_write_b32 a221, v111 + v_accvgpr_write_b32 a220, v110 + v_accvgpr_write_b32 a219, v109 + v_accvgpr_write_b32 a218, v108 + v_accvgpr_write_b32 a217, v107 + v_accvgpr_write_b32 a216, v106 + v_accvgpr_write_b32 a215, v105 + v_accvgpr_write_b32 a214, v104 + v_accvgpr_write_b32 a213, v103 + v_accvgpr_write_b32 a212, v102 + v_accvgpr_write_b32 a211, v101 + v_accvgpr_write_b32 a210, v100 + v_accvgpr_write_b32 a209, v99 + v_accvgpr_write_b32 a208, v98 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[208:223], v[10:11], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[10:11], v[6:7], a[80:95] + v_accvgpr_write_b32 a32, v82 + v_accvgpr_write_b32 a33, v83 + v_accvgpr_write_b32 a34, v84 + v_accvgpr_write_b32 a35, v85 + v_accvgpr_write_b32 a36, v86 + v_accvgpr_write_b32 a37, v87 + v_accvgpr_write_b32 a38, v88 + v_accvgpr_write_b32 a39, v89 + v_accvgpr_write_b32 a40, v90 + v_accvgpr_write_b32 a41, v91 + v_accvgpr_write_b32 a42, v92 + v_accvgpr_write_b32 a43, v93 + v_accvgpr_write_b32 a44, v94 + v_accvgpr_write_b32 a45, v95 + v_accvgpr_write_b32 a46, v96 + v_accvgpr_write_b32 a47, v97 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[32:47], v[10:11], v[8:9], a[32:47] + ds_read_b32 v10, v67 + ds_read_b32 v11, v69 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[10:11], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[10:11], v[4:5], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[6:7], a[96:111] + ds_read_b32 v12, v35 + v_mfma_i32_32x32x16_i8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v13, v37 + ds_read_b64 v[2:3], v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[2:3], a[176:191] + ds_read_b64 v[4:5], v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[4:5], a[112:127] + ds_read_b64 v[6:7], v73 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[12:13], v[6:7], a[48:63] + ds_read_b64 v[8:9], v75 offset:16384 + ds_read_b32 v10, v44 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[12:13], v[8:9], a[0:15] + ds_read_b32 v11, v46 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[4:5], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[6:7], a[64:79] + ds_read_b32 v12, v50 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[8:9], a[16:31] + ds_read_b32 v13, v52 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[12:13], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[12:13], v[4:5], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[12:13], v[6:7], a[80:95] + ds_read_b32 v10, v56 + v_mfma_i32_32x32x16_i8 a[32:47], v[12:13], v[8:9], a[32:47] + ds_read_b32 v11, v57 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[10:11], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[10:11], v[4:5], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[6:7], a[96:111] + ds_read_b32 v12, v19 + v_mfma_i32_32x32x16_i8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v13, v36 + ds_read_b64 v[2:3], v60 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[2:3], a[176:191] + ds_read_b64 v[4:5], v62 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[4:5], a[112:127] + ds_read_b64 v[6:7], v63 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[12:13], v[6:7], a[48:63] + ds_read_b64 v[8:9], v66 offset:16384 + ds_read_b32 v10, v41 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[12:13], v[8:9], a[0:15] + ds_read_b32 v11, v42 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[4:5], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[6:7], a[64:79] + ds_read_b32 v12, v47 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[8:9], a[16:31] + ds_read_b32 v13, v48 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[12:13], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[12:13], v[4:5], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[12:13], v[6:7], a[80:95] + ds_read_b32 v10, v53 + v_mfma_i32_32x32x16_i8 a[32:47], v[12:13], v[8:9], a[32:47] + ds_read_b32 v11, v54 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[10:11], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[10:11], v[4:5], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[6:7], a[96:111] + ds_read_b32 v12, v34 + v_mfma_i32_32x32x16_i8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b32 v13, v38 + ds_read_b64 v[2:3], v55 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[2:3], a[176:191] + ds_read_b64 v[4:5], v58 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[4:5], a[112:127] + ds_read_b64 v[6:7], v59 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[12:13], v[6:7], a[48:63] + ds_read_b64 v[8:9], v61 offset:16384 + ds_read_b32 v10, v39 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[12:13], v[8:9], a[0:15] + ds_read_b32 v11, v40 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[4:5], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[6:7], a[64:79] + ds_read_b32 v12, v43 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[8:9], a[16:31] + ds_read_b32 v13, v45 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[12:13], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[12:13], v[4:5], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[12:13], v[6:7], a[80:95] + ds_read_b32 v10, v49 + v_mfma_i32_32x32x16_i8 a[32:47], v[12:13], v[8:9], a[32:47] + ds_read_b32 v11, v51 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[10:11], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[10:11], v[4:5], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[6:7], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[10:11], v[8:9], a[240:255] +.LBB33_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESB_NSA_8RowMajorELi1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEENSK_IJNSL_IS1C_NSK_IJS1F_S1E_EEEEEEEESF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1N_T0_EE5valueEbE4typeELPb0EEEDaR + s_nop 10 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s2, s4, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_u32 s2, s5, s3 + s_add_u32 s4, s2, 2.0 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v18, 28, v1 + v_and_b32_e32 v19, 3, v1 + v_lshrrev_b32_e32 v20, 3, v1 + v_and_b32_e32 v22, 0x1ffffffc, v20 + s_waitcnt lgkmcnt(0) + s_mov_b64 s[2:3], -1 + v_lshlrev_b32_e32 v23, 2, v19 + v_lshlrev_b32_e32 v21, 2, v18 + v_lshlrev_b32_e32 v20, 2, v1 + v_and_b32_e32 v1, -16, v1 + s_cbranch_scc1 .LBB33_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB33_14 +.LBB33_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESE_NSD_8RowMajorELi1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB33_13: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_add_u32_e32 v18, s3, v22 + s_barrier + v_lshl_or_b32 v18, v18, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v24, v18, v21, s3 + ds_write_b32 v24, a176 + ds_write_b32 v24, a177 offset:256 + ds_write_b32 v24, a178 offset:512 + ds_write_b32 v24, a179 offset:768 + ds_write_b32 v24, a180 offset:2048 + ds_write_b32 v24, a181 offset:2304 + ds_write_b32 v24, a182 offset:2560 + ds_write_b32 v24, a183 offset:2816 + ds_write_b32 v24, a184 offset:4096 + ds_write_b32 v24, a185 offset:4352 + ds_write_b32 v24, a186 offset:4608 + ds_write_b32 v24, a187 offset:4864 + ds_write_b32 v24, a188 offset:6144 + ds_write_b32 v24, a189 offset:6400 + ds_write_b32 v24, a190 offset:6656 + ds_write_b32 v24, a191 offset:6912 + ds_write_b32 v24, a192 offset:16384 + ds_write_b32 v24, a193 offset:16640 + ds_write_b32 v24, a194 offset:16896 + ds_write_b32 v24, a195 offset:17152 + ds_write_b32 v24, a196 offset:18432 + ds_write_b32 v24, a197 offset:18688 + ds_write_b32 v24, a198 offset:18944 + ds_write_b32 v24, a199 offset:19200 + ds_write_b32 v24, a200 offset:20480 + ds_write_b32 v24, a201 offset:20736 + ds_write_b32 v24, a202 offset:20992 + ds_write_b32 v24, a203 offset:21248 + ds_write_b32 v24, a204 offset:22528 + ds_write_b32 v24, a205 offset:22784 + ds_write_b32 v24, a206 offset:23040 + ds_write_b32 v24, a207 offset:23296 + ds_write_b32 v24, a208 offset:32768 + ds_write_b32 v24, a209 offset:33024 + ds_write_b32 v24, a210 offset:33280 + ds_write_b32 v24, a211 offset:33536 + ds_write_b32 v24, a212 offset:34816 + ds_write_b32 v24, a213 offset:35072 + ds_write_b32 v24, a214 offset:35328 + ds_write_b32 v24, a215 offset:35584 + ds_write_b32 v24, a216 offset:36864 + ds_write_b32 v24, a217 offset:37120 + ds_write_b32 v24, a218 offset:37376 + ds_write_b32 v24, a219 offset:37632 + ds_write_b32 v24, a220 offset:38912 + ds_write_b32 v24, a221 offset:39168 + ds_write_b32 v24, a222 offset:39424 + ds_write_b32 v24, a223 offset:39680 + ds_write_b32 v24, a224 offset:49152 + ds_write_b32 v24, a225 offset:49408 + ds_write_b32 v24, a226 offset:49664 + ds_write_b32 v24, a227 offset:49920 + ds_write_b32 v24, a228 offset:51200 + ds_write_b32 v24, a229 offset:51456 + ds_write_b32 v24, a230 offset:51712 + ds_write_b32 v24, a231 offset:51968 + ds_write_b32 v24, a232 offset:53248 + ds_write_b32 v24, a233 offset:53504 + ds_write_b32 v24, a234 offset:53760 + ds_write_b32 v24, a235 offset:54016 + ds_write_b32 v24, a236 offset:55296 + ds_write_b32 v24, a237 offset:55552 + ds_write_b32 v24, a238 offset:55808 + ds_write_b32 v24, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v18, 60, v20 + s_andn2_b32 s2, s2, 63 + v_add_u32_e32 v19, s2, v1 + v_lshlrev_b32_e32 v25, 8, v19 + v_lshl_or_b32 v25, v18, 2, v25 + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, s20, v19 + v_or_b32_e32 v18, s21, v18 + v_mad_u64_u32 v[18:19], s[2:3], v19, s16, v[18:19] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v18 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a112 + ds_write_b32 v24, a113 offset:256 + ds_write_b32 v24, a114 offset:512 + ds_write_b32 v24, a115 offset:768 + ds_write_b32 v24, a116 offset:2048 + ds_write_b32 v24, a117 offset:2304 + ds_write_b32 v24, a118 offset:2560 + ds_write_b32 v24, a119 offset:2816 + ds_write_b32 v24, a120 offset:4096 + ds_write_b32 v24, a121 offset:4352 + ds_write_b32 v24, a122 offset:4608 + ds_write_b32 v24, a123 offset:4864 + ds_write_b32 v24, a124 offset:6144 + ds_write_b32 v24, a125 offset:6400 + ds_write_b32 v24, a126 offset:6656 + ds_write_b32 v24, a127 offset:6912 + ds_write_b32 v24, a128 offset:16384 + ds_write_b32 v24, a129 offset:16640 + ds_write_b32 v24, a130 offset:16896 + ds_write_b32 v24, a131 offset:17152 + ds_write_b32 v24, a132 offset:18432 + ds_write_b32 v24, a133 offset:18688 + ds_write_b32 v24, a134 offset:18944 + ds_write_b32 v24, a135 offset:19200 + ds_write_b32 v24, a136 offset:20480 + ds_write_b32 v24, a137 offset:20736 + ds_write_b32 v24, a138 offset:20992 + ds_write_b32 v24, a139 offset:21248 + ds_write_b32 v24, a140 offset:22528 + ds_write_b32 v24, a141 offset:22784 + ds_write_b32 v24, a142 offset:23040 + ds_write_b32 v24, a143 offset:23296 + ds_write_b32 v24, a144 offset:32768 + ds_write_b32 v24, a145 offset:33024 + ds_write_b32 v24, a146 offset:33280 + ds_write_b32 v24, a147 offset:33536 + ds_write_b32 v24, a148 offset:34816 + ds_write_b32 v24, a149 offset:35072 + ds_write_b32 v24, a150 offset:35328 + ds_write_b32 v24, a151 offset:35584 + ds_write_b32 v24, a152 offset:36864 + ds_write_b32 v24, a153 offset:37120 + ds_write_b32 v24, a154 offset:37376 + ds_write_b32 v24, a155 offset:37632 + ds_write_b32 v24, a156 offset:38912 + ds_write_b32 v24, a157 offset:39168 + ds_write_b32 v24, a158 offset:39424 + ds_write_b32 v24, a159 offset:39680 + ds_write_b32 v24, a160 offset:49152 + ds_write_b32 v24, a161 offset:49408 + ds_write_b32 v24, a162 offset:49664 + ds_write_b32 v24, a163 offset:49920 + ds_write_b32 v24, a164 offset:51200 + ds_write_b32 v24, a165 offset:51456 + ds_write_b32 v24, a166 offset:51712 + ds_write_b32 v24, a167 offset:51968 + ds_write_b32 v24, a168 offset:53248 + ds_write_b32 v24, a169 offset:53504 + ds_write_b32 v24, a170 offset:53760 + ds_write_b32 v24, a171 offset:54016 + ds_write_b32 v24, a172 offset:55296 + ds_write_b32 v24, a173 offset:55552 + ds_write_b32 v24, a174 offset:55808 + ds_write_b32 v24, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 64, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a48 + ds_write_b32 v24, a49 offset:256 + ds_write_b32 v24, a50 offset:512 + ds_write_b32 v24, a51 offset:768 + ds_write_b32 v24, a52 offset:2048 + ds_write_b32 v24, a53 offset:2304 + ds_write_b32 v24, a54 offset:2560 + ds_write_b32 v24, a55 offset:2816 + ds_write_b32 v24, a56 offset:4096 + ds_write_b32 v24, a57 offset:4352 + ds_write_b32 v24, a58 offset:4608 + ds_write_b32 v24, a59 offset:4864 + ds_write_b32 v24, a60 offset:6144 + ds_write_b32 v24, a61 offset:6400 + ds_write_b32 v24, a62 offset:6656 + ds_write_b32 v24, a63 offset:6912 + ds_write_b32 v24, a64 offset:16384 + ds_write_b32 v24, a65 offset:16640 + ds_write_b32 v24, a66 offset:16896 + ds_write_b32 v24, a67 offset:17152 + ds_write_b32 v24, a68 offset:18432 + ds_write_b32 v24, a69 offset:18688 + ds_write_b32 v24, a70 offset:18944 + ds_write_b32 v24, a71 offset:19200 + ds_write_b32 v24, a72 offset:20480 + ds_write_b32 v24, a73 offset:20736 + ds_write_b32 v24, a74 offset:20992 + ds_write_b32 v24, a75 offset:21248 + ds_write_b32 v24, a76 offset:22528 + ds_write_b32 v24, a77 offset:22784 + ds_write_b32 v24, a78 offset:23040 + ds_write_b32 v24, a79 offset:23296 + ds_write_b32 v24, a80 offset:32768 + ds_write_b32 v24, a81 offset:33024 + ds_write_b32 v24, a82 offset:33280 + ds_write_b32 v24, a83 offset:33536 + ds_write_b32 v24, a84 offset:34816 + ds_write_b32 v24, a85 offset:35072 + ds_write_b32 v24, a86 offset:35328 + ds_write_b32 v24, a87 offset:35584 + ds_write_b32 v24, a88 offset:36864 + ds_write_b32 v24, a89 offset:37120 + ds_write_b32 v24, a90 offset:37376 + ds_write_b32 v24, a91 offset:37632 + ds_write_b32 v24, a92 offset:38912 + ds_write_b32 v24, a93 offset:39168 + ds_write_b32 v24, a94 offset:39424 + ds_write_b32 v24, a95 offset:39680 + ds_write_b32 v24, a96 offset:49152 + ds_write_b32 v24, a97 offset:49408 + ds_write_b32 v24, a98 offset:49664 + ds_write_b32 v24, a99 offset:49920 + ds_write_b32 v24, a100 offset:51200 + ds_write_b32 v24, a101 offset:51456 + ds_write_b32 v24, a102 offset:51712 + ds_write_b32 v24, a103 offset:51968 + ds_write_b32 v24, a104 offset:53248 + ds_write_b32 v24, a105 offset:53504 + ds_write_b32 v24, a106 offset:53760 + ds_write_b32 v24, a107 offset:54016 + ds_write_b32 v24, a108 offset:55296 + ds_write_b32 v24, a109 offset:55552 + ds_write_b32 v24, a110 offset:55808 + ds_write_b32 v24, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 0x80, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a0 + ds_write_b32 v24, a1 offset:256 + ds_write_b32 v24, a2 offset:512 + ds_write_b32 v24, a3 offset:768 + ds_write_b32 v24, a4 offset:2048 + ds_write_b32 v24, a5 offset:2304 + ds_write_b32 v24, a6 offset:2560 + ds_write_b32 v24, a7 offset:2816 + ds_write_b32 v24, a8 offset:4096 + ds_write_b32 v24, a9 offset:4352 + ds_write_b32 v24, a10 offset:4608 + ds_write_b32 v24, a11 offset:4864 + ds_write_b32 v24, a12 offset:6144 + ds_write_b32 v24, a13 offset:6400 + ds_write_b32 v24, a14 offset:6656 + ds_write_b32 v24, a15 offset:6912 + ds_write_b32 v24, a16 offset:16384 + ds_write_b32 v24, a17 offset:16640 + ds_write_b32 v24, a18 offset:16896 + ds_write_b32 v24, a19 offset:17152 + ds_write_b32 v24, a20 offset:18432 + ds_write_b32 v24, a21 offset:18688 + ds_write_b32 v24, a22 offset:18944 + ds_write_b32 v24, a23 offset:19200 + ds_write_b32 v24, a24 offset:20480 + ds_write_b32 v24, a25 offset:20736 + ds_write_b32 v24, a26 offset:20992 + ds_write_b32 v24, a27 offset:21248 + ds_write_b32 v24, a28 offset:22528 + ds_write_b32 v24, a29 offset:22784 + ds_write_b32 v24, a30 offset:23040 + ds_write_b32 v24, a31 offset:23296 + ds_write_b32 v24, a32 offset:32768 + ds_write_b32 v24, a33 offset:33024 + ds_write_b32 v24, a34 offset:33280 + ds_write_b32 v24, a35 offset:33536 + ds_write_b32 v24, a36 offset:34816 + ds_write_b32 v24, a37 offset:35072 + ds_write_b32 v24, a38 offset:35328 + ds_write_b32 v24, a39 offset:35584 + ds_write_b32 v24, a40 offset:36864 + ds_write_b32 v24, a41 offset:37120 + ds_write_b32 v24, a42 offset:37376 + ds_write_b32 v24, a43 offset:37632 + ds_write_b32 v24, a44 offset:38912 + ds_write_b32 v24, a45 offset:39168 + ds_write_b32 v24, a46 offset:39424 + ds_write_b32 v24, a47 offset:39680 + ds_write2st64_b32 v24, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v24, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v24, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v24, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v24, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v24, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v24, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v24, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v18, 0xc0, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + buffer_atomic_add v30, v19, s[0:3], 0 offen + buffer_atomic_add v31, v19, s[0:3], 4 offen + buffer_atomic_add v32, v19, s[0:3], 8 offen + buffer_atomic_add v33, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v19, s[0:3], 0 offen + buffer_atomic_add v35, v19, s[0:3], 4 offen + buffer_atomic_add v36, v19, s[0:3], 8 offen + buffer_atomic_add v37, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v19, s[0:3], 0 offen + buffer_atomic_add v39, v19, s[0:3], 4 offen + buffer_atomic_add v40, v19, s[0:3], 8 offen + buffer_atomic_add v41, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v19, s[0:3], 0 offen + buffer_atomic_add v43, v19, s[0:3], 4 offen + buffer_atomic_add v44, v19, s[0:3], 8 offen + buffer_atomic_add v45, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v19, s[0:3], 0 offen + buffer_atomic_add v47, v19, s[0:3], 4 offen + buffer_atomic_add v48, v19, s[0:3], 8 offen + buffer_atomic_add v49, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v19, s[0:3], 0 offen + buffer_atomic_add v51, v19, s[0:3], 4 offen + buffer_atomic_add v52, v19, s[0:3], 8 offen + buffer_atomic_add v53, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v19, s[0:3], 0 offen + buffer_atomic_add v55, v19, s[0:3], 4 offen + buffer_atomic_add v56, v19, s[0:3], 8 offen + buffer_atomic_add v57, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v19, s[0:3], 0 offen + buffer_atomic_add v59, v19, s[0:3], 4 offen + buffer_atomic_add v60, v19, s[0:3], 8 offen + buffer_atomic_add v61, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v19, s[0:3], 0 offen + buffer_atomic_add v63, v19, s[0:3], 4 offen + buffer_atomic_add v64, v19, s[0:3], 8 offen + buffer_atomic_add v65, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v19, s[0:3], 0 offen + buffer_atomic_add v67, v19, s[0:3], 4 offen + buffer_atomic_add v68, v19, s[0:3], 8 offen + buffer_atomic_add v69, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v19, s[0:3], 0 offen + buffer_atomic_add v71, v19, s[0:3], 4 offen + buffer_atomic_add v72, v19, s[0:3], 8 offen + buffer_atomic_add v73, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v19, s[0:3], 0 offen + buffer_atomic_add v75, v19, s[0:3], 4 offen + buffer_atomic_add v76, v19, s[0:3], 8 offen + buffer_atomic_add v77, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v19, s[0:3], 0 offen + buffer_atomic_add v79, v19, s[0:3], 4 offen + buffer_atomic_add v80, v19, s[0:3], 8 offen + buffer_atomic_add v81, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v19, s[0:3], 0 offen + buffer_atomic_add v83, v19, s[0:3], 4 offen + buffer_atomic_add v84, v19, s[0:3], 8 offen + buffer_atomic_add v85, v19, s[0:3], 12 offen + v_add_lshl_u32 v18, v18, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v18, s[0:3], 0 offen + buffer_atomic_add v87, v18, s[0:3], 4 offen + buffer_atomic_add v88, v18, s[0:3], 8 offen + buffer_atomic_add v89, v18, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB33_12 +.LBB33_14: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_add_u32_e32 v0, s3, v22 + s_barrier + v_lshl_or_b32 v0, v0, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v82, v0, v21, s3 + ds_write_b32 v82, a176 + ds_write_b32 v82, a177 offset:256 + ds_write_b32 v82, a178 offset:512 + ds_write_b32 v82, a179 offset:768 + ds_write_b32 v82, a180 offset:2048 + ds_write_b32 v82, a181 offset:2304 + ds_write_b32 v82, a182 offset:2560 + ds_write_b32 v82, a183 offset:2816 + ds_write_b32 v82, a184 offset:4096 + ds_write_b32 v82, a185 offset:4352 + ds_write_b32 v82, a186 offset:4608 + ds_write_b32 v82, a187 offset:4864 + ds_write_b32 v82, a188 offset:6144 + ds_write_b32 v82, a189 offset:6400 + ds_write_b32 v82, a190 offset:6656 + ds_write_b32 v82, a191 offset:6912 + ds_write_b32 v82, a192 offset:16384 + ds_write_b32 v82, a193 offset:16640 + ds_write_b32 v82, a194 offset:16896 + ds_write_b32 v82, a195 offset:17152 + ds_write_b32 v82, a196 offset:18432 + ds_write_b32 v82, a197 offset:18688 + ds_write_b32 v82, a198 offset:18944 + ds_write_b32 v82, a199 offset:19200 + ds_write_b32 v82, a200 offset:20480 + ds_write_b32 v82, a201 offset:20736 + ds_write_b32 v82, a202 offset:20992 + ds_write_b32 v82, a203 offset:21248 + ds_write_b32 v82, a204 offset:22528 + ds_write_b32 v82, a205 offset:22784 + ds_write_b32 v82, a206 offset:23040 + ds_write_b32 v82, a207 offset:23296 + ds_write_b32 v82, a208 offset:32768 + ds_write_b32 v82, a209 offset:33024 + ds_write_b32 v82, a210 offset:33280 + ds_write_b32 v82, a211 offset:33536 + ds_write_b32 v82, a212 offset:34816 + ds_write_b32 v82, a213 offset:35072 + ds_write_b32 v82, a214 offset:35328 + ds_write_b32 v82, a215 offset:35584 + ds_write_b32 v82, a216 offset:36864 + ds_write_b32 v82, a217 offset:37120 + ds_write_b32 v82, a218 offset:37376 + ds_write_b32 v82, a219 offset:37632 + ds_write_b32 v82, a220 offset:38912 + ds_write_b32 v82, a221 offset:39168 + ds_write_b32 v82, a222 offset:39424 + ds_write_b32 v82, a223 offset:39680 + ds_write_b32 v82, a224 offset:49152 + ds_write_b32 v82, a225 offset:49408 + ds_write_b32 v82, a226 offset:49664 + ds_write_b32 v82, a227 offset:49920 + ds_write_b32 v82, a228 offset:51200 + ds_write_b32 v82, a229 offset:51456 + ds_write_b32 v82, a230 offset:51712 + ds_write_b32 v82, a231 offset:51968 + ds_write_b32 v82, a232 offset:53248 + ds_write_b32 v82, a233 offset:53504 + ds_write_b32 v82, a234 offset:53760 + ds_write_b32 v82, a235 offset:54016 + ds_write_b32 v82, a236 offset:55296 + ds_write_b32 v82, a237 offset:55552 + ds_write_b32 v82, a238 offset:55808 + ds_write_b32 v82, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 60, v20 + s_andn2_b32 s2, s2, 63 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 8, v1 + v_lshl_or_b32 v83, v0, 2, v18 + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v0, s21, v0 + v_mad_u64_u32 v[0:1], s[2:3], v1, s16, v[0:1] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a112 + ds_write_b32 v82, a113 offset:256 + ds_write_b32 v82, a114 offset:512 + ds_write_b32 v82, a115 offset:768 + ds_write_b32 v82, a116 offset:2048 + ds_write_b32 v82, a117 offset:2304 + ds_write_b32 v82, a118 offset:2560 + ds_write_b32 v82, a119 offset:2816 + ds_write_b32 v82, a120 offset:4096 + ds_write_b32 v82, a121 offset:4352 + ds_write_b32 v82, a122 offset:4608 + ds_write_b32 v82, a123 offset:4864 + ds_write_b32 v82, a124 offset:6144 + ds_write_b32 v82, a125 offset:6400 + ds_write_b32 v82, a126 offset:6656 + ds_write_b32 v82, a127 offset:6912 + ds_write_b32 v82, a128 offset:16384 + ds_write_b32 v82, a129 offset:16640 + ds_write_b32 v82, a130 offset:16896 + ds_write_b32 v82, a131 offset:17152 + ds_write_b32 v82, a132 offset:18432 + ds_write_b32 v82, a133 offset:18688 + ds_write_b32 v82, a134 offset:18944 + ds_write_b32 v82, a135 offset:19200 + ds_write_b32 v82, a136 offset:20480 + ds_write_b32 v82, a137 offset:20736 + ds_write_b32 v82, a138 offset:20992 + ds_write_b32 v82, a139 offset:21248 + ds_write_b32 v82, a140 offset:22528 + ds_write_b32 v82, a141 offset:22784 + ds_write_b32 v82, a142 offset:23040 + ds_write_b32 v82, a143 offset:23296 + ds_write_b32 v82, a144 offset:32768 + ds_write_b32 v82, a145 offset:33024 + ds_write_b32 v82, a146 offset:33280 + ds_write_b32 v82, a147 offset:33536 + ds_write_b32 v82, a148 offset:34816 + ds_write_b32 v82, a149 offset:35072 + ds_write_b32 v82, a150 offset:35328 + ds_write_b32 v82, a151 offset:35584 + ds_write_b32 v82, a152 offset:36864 + ds_write_b32 v82, a153 offset:37120 + ds_write_b32 v82, a154 offset:37376 + ds_write_b32 v82, a155 offset:37632 + ds_write_b32 v82, a156 offset:38912 + ds_write_b32 v82, a157 offset:39168 + ds_write_b32 v82, a158 offset:39424 + ds_write_b32 v82, a159 offset:39680 + ds_write_b32 v82, a160 offset:49152 + ds_write_b32 v82, a161 offset:49408 + ds_write_b32 v82, a162 offset:49664 + ds_write_b32 v82, a163 offset:49920 + ds_write_b32 v82, a164 offset:51200 + ds_write_b32 v82, a165 offset:51456 + ds_write_b32 v82, a166 offset:51712 + ds_write_b32 v82, a167 offset:51968 + ds_write_b32 v82, a168 offset:53248 + ds_write_b32 v82, a169 offset:53504 + ds_write_b32 v82, a170 offset:53760 + ds_write_b32 v82, a171 offset:54016 + ds_write_b32 v82, a172 offset:55296 + ds_write_b32 v82, a173 offset:55552 + ds_write_b32 v82, a174 offset:55808 + ds_write_b32 v82, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 64, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a48 + ds_write_b32 v82, a49 offset:256 + ds_write_b32 v82, a50 offset:512 + ds_write_b32 v82, a51 offset:768 + ds_write_b32 v82, a52 offset:2048 + ds_write_b32 v82, a53 offset:2304 + ds_write_b32 v82, a54 offset:2560 + ds_write_b32 v82, a55 offset:2816 + ds_write_b32 v82, a56 offset:4096 + ds_write_b32 v82, a57 offset:4352 + ds_write_b32 v82, a58 offset:4608 + ds_write_b32 v82, a59 offset:4864 + ds_write_b32 v82, a60 offset:6144 + ds_write_b32 v82, a61 offset:6400 + ds_write_b32 v82, a62 offset:6656 + ds_write_b32 v82, a63 offset:6912 + ds_write_b32 v82, a64 offset:16384 + ds_write_b32 v82, a65 offset:16640 + ds_write_b32 v82, a66 offset:16896 + ds_write_b32 v82, a67 offset:17152 + ds_write_b32 v82, a68 offset:18432 + ds_write_b32 v82, a69 offset:18688 + ds_write_b32 v82, a70 offset:18944 + ds_write_b32 v82, a71 offset:19200 + ds_write_b32 v82, a72 offset:20480 + ds_write_b32 v82, a73 offset:20736 + ds_write_b32 v82, a74 offset:20992 + ds_write_b32 v82, a75 offset:21248 + ds_write_b32 v82, a76 offset:22528 + ds_write_b32 v82, a77 offset:22784 + ds_write_b32 v82, a78 offset:23040 + ds_write_b32 v82, a79 offset:23296 + ds_write_b32 v82, a80 offset:32768 + ds_write_b32 v82, a81 offset:33024 + ds_write_b32 v82, a82 offset:33280 + ds_write_b32 v82, a83 offset:33536 + ds_write_b32 v82, a84 offset:34816 + ds_write_b32 v82, a85 offset:35072 + ds_write_b32 v82, a86 offset:35328 + ds_write_b32 v82, a87 offset:35584 + ds_write_b32 v82, a88 offset:36864 + ds_write_b32 v82, a89 offset:37120 + ds_write_b32 v82, a90 offset:37376 + ds_write_b32 v82, a91 offset:37632 + ds_write_b32 v82, a92 offset:38912 + ds_write_b32 v82, a93 offset:39168 + ds_write_b32 v82, a94 offset:39424 + ds_write_b32 v82, a95 offset:39680 + ds_write_b32 v82, a96 offset:49152 + ds_write_b32 v82, a97 offset:49408 + ds_write_b32 v82, a98 offset:49664 + ds_write_b32 v82, a99 offset:49920 + ds_write_b32 v82, a100 offset:51200 + ds_write_b32 v82, a101 offset:51456 + ds_write_b32 v82, a102 offset:51712 + ds_write_b32 v82, a103 offset:51968 + ds_write_b32 v82, a104 offset:53248 + ds_write_b32 v82, a105 offset:53504 + ds_write_b32 v82, a106 offset:53760 + ds_write_b32 v82, a107 offset:54016 + ds_write_b32 v82, a108 offset:55296 + ds_write_b32 v82, a109 offset:55552 + ds_write_b32 v82, a110 offset:55808 + ds_write_b32 v82, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 0x80, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a0 + ds_write_b32 v82, a1 offset:256 + ds_write_b32 v82, a2 offset:512 + ds_write_b32 v82, a3 offset:768 + ds_write_b32 v82, a4 offset:2048 + ds_write_b32 v82, a5 offset:2304 + ds_write_b32 v82, a6 offset:2560 + ds_write_b32 v82, a7 offset:2816 + ds_write_b32 v82, a8 offset:4096 + ds_write_b32 v82, a9 offset:4352 + ds_write_b32 v82, a10 offset:4608 + ds_write_b32 v82, a11 offset:4864 + ds_write_b32 v82, a12 offset:6144 + ds_write_b32 v82, a13 offset:6400 + ds_write_b32 v82, a14 offset:6656 + ds_write_b32 v82, a15 offset:6912 + ds_write_b32 v82, a16 offset:16384 + ds_write_b32 v82, a17 offset:16640 + ds_write_b32 v82, a18 offset:16896 + ds_write_b32 v82, a19 offset:17152 + ds_write_b32 v82, a20 offset:18432 + ds_write_b32 v82, a21 offset:18688 + ds_write_b32 v82, a22 offset:18944 + ds_write_b32 v82, a23 offset:19200 + ds_write_b32 v82, a24 offset:20480 + ds_write_b32 v82, a25 offset:20736 + ds_write_b32 v82, a26 offset:20992 + ds_write_b32 v82, a27 offset:21248 + ds_write_b32 v82, a28 offset:22528 + ds_write_b32 v82, a29 offset:22784 + ds_write_b32 v82, a30 offset:23040 + ds_write_b32 v82, a31 offset:23296 + ds_write_b32 v82, a32 offset:32768 + ds_write_b32 v82, a33 offset:33024 + ds_write_b32 v82, a34 offset:33280 + ds_write_b32 v82, a35 offset:33536 + ds_write_b32 v82, a36 offset:34816 + ds_write_b32 v82, a37 offset:35072 + ds_write_b32 v82, a38 offset:35328 + ds_write_b32 v82, a39 offset:35584 + ds_write_b32 v82, a40 offset:36864 + ds_write_b32 v82, a41 offset:37120 + ds_write_b32 v82, a42 offset:37376 + ds_write_b32 v82, a43 offset:37632 + ds_write_b32 v82, a44 offset:38912 + ds_write_b32 v82, a45 offset:39168 + ds_write_b32 v82, a46 offset:39424 + ds_write_b32 v82, a47 offset:39680 + ds_write2st64_b32 v82, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v82, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v82, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v82, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v82, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v82, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v82, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v82, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[2:5], v83 + ds_read_b128 v[6:9], v83 offset:256 + ds_read_b128 v[10:13], v83 offset:512 + ds_read_b128 v[14:17], v83 offset:768 + ds_read_b128 v[18:21], v83 offset:1024 + ds_read_b128 v[22:25], v83 offset:1280 + ds_read_b128 v[26:29], v83 offset:1536 + ds_read_b128 v[30:33], v83 offset:1792 + ds_read_b128 v[34:37], v83 offset:2048 + ds_read_b128 v[38:41], v83 offset:2304 + ds_read_b128 v[42:45], v83 offset:2560 + ds_read_b128 v[46:49], v83 offset:2816 + ds_read_b128 v[50:53], v83 offset:3072 + ds_read_b128 v[54:57], v83 offset:3328 + ds_read_b128 v[58:61], v83 offset:3584 + ds_read_b128 v[62:65], v83 offset:3840 + v_add_u32_e32 v0, 0xc0, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[2:5], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + buffer_store_dwordx4 v[6:9], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[10:13], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[14:17], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[26:29], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[30:33], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[34:37], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[38:41], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[42:45], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[46:49], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[50:53], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[54:57], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[58:61], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 468 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 212 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end33: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end33-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 210 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 28540 +; TotalNumSgprs: 36 +; NumVgprs: 210 +; NumAgprs: 256 +; TotalNumVgprs: 468 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 58 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 468 +; AccumOffset: 212 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 52 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v6, 0 + global_load_ushort v1, v6, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v2, s3 + v_rcp_iflag_f32_e32 v2, v2 + s_nop 0 + v_mul_f32_e32 v2, 0x4f7ffffe, v2 + v_cvt_u32_f32_e32 v2, v2 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v3, s8, v2 + v_mul_hi_u32 v3, v2, v3 + v_add_u32_e32 v2, v2, v3 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v1, s2, v1 + v_add_u32_e32 v0, v1, v0 + v_xor_b32_e32 v1, s5, v0 + v_sub_u32_e32 v3, 0, v0 + v_ashrrev_i32_e32 v4, 31, v1 + v_max_i32_e32 v1, v0, v3 + v_mul_hi_u32 v2, v1, v2 + v_mul_lo_u32 v3, v2, s3 + v_add_u32_e32 v5, 1, v2 + v_sub_u32_e32 v1, v1, v3 + v_cmp_le_u32_e32 vcc, s3, v1 + s_nop 1 + v_cndmask_b32_e32 v2, v2, v5, vcc + v_subrev_u32_e32 v3, s3, v1 + v_cndmask_b32_e32 v1, v1, v3, vcc + v_add_u32_e32 v3, 1, v2 + v_cmp_le_u32_e32 vcc, s3, v1 + s_nop 1 + v_cndmask_b32_e32 v1, v2, v3, vcc + v_xor_b32_e32 v5, v1, v4 + v_sub_u32_e32 v1, v5, v4 + v_cmp_gt_i32_e32 vcc, s4, v1 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB34_10 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v1, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB34_9 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v2, v0, s2 + s_cmp_eq_u32 s6, 1 + s_cselect_b64 s[0:1], -1, 0 + s_cmp_lg_u32 s7, 1 + s_cselect_b64 s[4:5], -1, 0 + s_or_b64 s[0:1], s[0:1], s[4:5] + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB34_6 +; %bb.3: ; %vector.ph + s_and_b32 s2, s6, 0x7ffffffe + s_mov_b32 s0, 0 + v_mov_b32_e32 v3, 0 + v_mov_b32_e32 v6, 0 +.LBB34_4: ; %vector.body + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v8, s0, v1 + v_add_u32_e32 v10, s0, v2 + v_ashrrev_i32_e32 v9, 31, v8 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshl_add_u64 v[8:9], s[8:9], 0, v[8:9] + v_lshl_add_u64 v[10:11], s[10:11], 0, v[10:11] + global_load_ushort v7, v[8:9], off + global_load_ushort v12, v[10:11], off + s_add_i32 s0, s0, 2 + s_cmp_lg_u32 s0, s2 + s_waitcnt vmcnt(1) + v_lshrrev_b16_e32 v8, 8, v7 + v_bfe_i32 v7, v7, 0, 8 + s_waitcnt vmcnt(0) + v_lshrrev_b16_e32 v9, 8, v12 + v_bfe_i32 v10, v12, 0, 8 + v_bfe_i32 v8, v8, 0, 8 + v_bfe_i32 v9, v9, 0, 8 + v_mad_i32_i24 v3, v10, v7, v3 + v_mad_i32_i24 v6, v9, v8, v6 + s_cbranch_scc1 .LBB34_4 +; %bb.5: ; %middle.block + v_add_u32_e32 v6, v3, v6 + s_cmp_lg_u32 s6, s2 + s_cselect_b64 s[0:1], -1, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB34_7 + s_branch .LBB34_9 +.LBB34_6: + s_mov_b32 s2, 0 + v_mov_b32_e32 v6, 0 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB34_9 +.LBB34_7: ; %scalar.ph.preheader + s_sub_i32 s0, s6, s2 + v_ashrrev_i32_e32 v3, 31, v2 + s_add_u32 s4, s10, s2 + s_addc_u32 s5, s11, 0 + v_lshl_add_u64 v[2:3], s[4:5], 0, v[2:3] + s_mul_i32 s1, s2, s7 + v_add_u32_e32 v5, s1, v5 + v_sub_u32_e32 v4, v5, v4 +.LBB34_8: ; %scalar.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + global_load_sbyte v7, v[2:3], off + v_lshl_add_u64 v[8:9], s[8:9], 0, v[4:5] + global_load_sbyte v5, v[8:9], off + s_add_i32 s0, s0, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s7, v4 + s_cmp_eq_u32 s0, 0 + s_waitcnt vmcnt(0) + v_mad_i32_i24 v6, v7, v5, v6 + s_cbranch_scc0 .LBB34_8 +.LBB34_9: ; %._crit_edge + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[0:1], s[0:1], v1, s3, v[0:1] + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] + global_store_dword v[0:1], v6, off +.LBB34_10: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 13 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 16 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end34: + .size _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end34-_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 13 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorES3_NS2_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 648 +; TotalNumSgprs: 20 +; NumVgprs: 13 +; NumAgprs: 0 +; TotalNumVgprs: 13 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 13 +; AccumOffset: 16 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 3 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_mov_b32 s23, s7 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v1, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v1 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s24, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s24, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s7 + s_mul_i32 s19, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s19, 31 + s_add_u32 s12, s10, s19 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s10, s3, 1 + s_mul_i32 s2, s22, s2 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v1 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v36, -1, v1 + v_and_b32_e32 v37, 31, v36 + v_lshrrev_b32_e32 v5, 5, v36 + v_and_b32_e32 v4, 15, v36 + v_lshrrev_b32_e32 v1, 2, v36 + s_cbranch_scc0 .LBB35_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + s_lshr_b32 s28, s15, 2 + s_and_b32 s11, s28, 0x3ffffff0 + v_and_b32_e32 v3, 28, v1 + v_lshlrev_b32_e32 v18, 4, v4 + v_or_b32_e32 v2, s20, v18 + v_add_u32_e32 v42, s11, v3 + v_mad_u64_u32 v[2:3], s[24:25], v42, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[6:9], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[10:13], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[14:17], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[20:23], v2, s[8:11], 0 offen + v_lshlrev_b32_e32 v43, 3, v5 + v_lshlrev_b32_e32 v2, 12, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s25, 0x5010400 + s_mov_b32 s19, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s26, 0x7030602 + v_lshl_or_b32 v44, v4, 7, v2 + v_or_b32_e32 v18, s21, v18 + s_lshr_b32 s29, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s11, s28, 0x3fffffe0 + v_and_or_b32 v3, s29, 32, v37 + v_or_b32_e32 v2, s11, v37 + v_lshrrev_b32_e32 v3, 4, v3 + v_lshrrev_b32_e32 v45, 4, v2 + v_mad_u64_u32 v[32:33], s[28:29], v42, s22, v[18:19] + v_xor_b32_e32 v18, v3, v4 + v_xor_b32_e32 v46, v45, v4 + v_lshl_or_b32 v19, v18, 2, v44 + v_add_u32_e32 v33, s22, v32 + buffer_load_dwordx4 v[24:27], v32, s[12:15], 0 offen + buffer_load_dwordx4 v[28:31], v33, s[12:15], 0 offen + v_add_u32_e32 v47, s22, v33 + v_add_u32_e32 v48, s22, v47 + buffer_load_dwordx4 v[32:35], v47, s[12:15], 0 offen + buffer_load_dwordx4 v[38:41], v48, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v6, v6, v6, s27 + v_perm_b32 v7, v7, v7, s27 + v_perm_b32 v8, v8, v8, s27 + v_perm_b32 v9, v9, v9, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v10, v10, v10, s27 + v_perm_b32 v11, v11, v11, s27 + v_perm_b32 v12, v12, v12, s27 + v_perm_b32 v13, v13, v13, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v14, v14, v14, s27 + v_perm_b32 v15, v15, v15, s27 + v_perm_b32 v16, v16, v16, s27 + v_perm_b32 v17, v17, v17, s27 + v_perm_b32 v47, v10, v6, s25 + v_perm_b32 v6, v10, v6, s26 + v_perm_b32 v10, v11, v7, s25 + v_perm_b32 v7, v11, v7, s26 + v_perm_b32 v11, v12, v8, s25 + v_perm_b32 v8, v12, v8, s26 + v_perm_b32 v12, v13, v9, s25 + v_perm_b32 v9, v13, v9, s26 + s_waitcnt vmcnt(4) + v_perm_b32 v13, v20, v20, s27 + v_perm_b32 v20, v21, v21, s27 + v_perm_b32 v21, v22, v22, s27 + v_perm_b32 v22, v23, v23, s27 + v_perm_b32 v23, v13, v14, s25 + v_perm_b32 v13, v13, v14, s26 + v_perm_b32 v14, v20, v15, s25 + v_perm_b32 v15, v20, v15, s26 + v_perm_b32 v20, v21, v16, s25 + v_perm_b32 v16, v21, v16, s26 + v_perm_b32 v21, v22, v17, s25 + v_perm_b32 v17, v22, v17, s26 + v_perm_b32 v22, v23, v47, s19 + v_perm_b32 v23, v23, v47, s24 + v_perm_b32 v47, v13, v6, s19 + v_perm_b32 v6, v13, v6, s24 + v_perm_b32 v13, v14, v10, s19 + v_perm_b32 v10, v14, v10, s24 + v_perm_b32 v14, v15, v7, s19 + v_perm_b32 v7, v15, v7, s24 + v_perm_b32 v15, v20, v11, s19 + v_perm_b32 v11, v20, v11, s24 + v_perm_b32 v20, v16, v8, s19 + v_perm_b32 v8, v16, v8, s24 + v_perm_b32 v16, v21, v12, s19 + v_perm_b32 v12, v21, v12, s24 + v_perm_b32 v21, v17, v9, s19 + v_perm_b32 v9, v17, v9, s24 + v_lshrrev_b32_e32 v17, 1, v42 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v48, v17, v37 + v_lshlrev_b32_e32 v49, 9, v42 + v_and_b32_e32 v49, 0x3000, v49 + v_lshlrev_b32_e32 v42, 6, v42 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v42, 0xfffff800, v42 + v_add_u32_e32 v42, v49, v42 + v_lshl_or_b32 v42, v48, 2, v42 + ds_write_b32 v42, v22 + v_or_b32_e32 v22, 1, v17 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v48, v22, v48 + v_lshl_add_u32 v48, v48, 2, v42 + ds_write_b32 v48, v23 offset:128 + v_or_b32_e32 v23, 2, v17 + v_xor_b32_e32 v23, v23, v37 + v_sub_u32_e32 v22, v23, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v48, s18, v22 + ds_write_b32 v22, v47 offset:128 + v_or_b32_e32 v47, 3, v17 + v_xor_b32_e32 v47, v47, v37 + v_sub_u32_e32 v23, v47, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v22, s18, v23 + ds_write_b32 v23, v6 offset:128 + v_or_b32_e32 v6, 4, v17 + v_xor_b32_e32 v6, v6, v37 + v_sub_u32_e32 v47, v6, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v47, v23, s18, v47 + ds_write_b32 v47, v13 offset:128 + v_or_b32_e32 v13, 5, v17 + v_xor_b32_e32 v13, v13, v37 + v_sub_u32_e32 v6, v13, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v47, s18, v6 + ds_write_b32 v6, v10 offset:128 + v_or_b32_e32 v10, 6, v17 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v13, v10, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v6, s18, v13 + ds_write_b32 v13, v14 offset:128 + v_or_b32_e32 v14, 7, v17 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v10, v14, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v13, s18, v10 + ds_write_b32 v10, v7 offset:128 + v_or_b32_e32 v7, 8, v17 + v_xor_b32_e32 v7, v7, v37 + v_sub_u32_e32 v14, v7, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v10, s18, v14 + ds_write_b32 v14, v15 offset:128 + v_or_b32_e32 v15, 9, v17 + v_xor_b32_e32 v15, v15, v37 + v_sub_u32_e32 v7, v15, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v7, v14, s18, v7 + ds_write_b32 v7, v11 offset:128 + v_or_b32_e32 v11, 10, v17 + v_xor_b32_e32 v11, v11, v37 + v_sub_u32_e32 v15, v11, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v15, v7, s18, v15 + ds_write_b32 v15, v20 offset:128 + v_or_b32_e32 v20, 11, v17 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v11, v20, v11 + v_lshlrev_b32_e32 v11, 2, v11 + v_add3_u32 v11, v15, s18, v11 + ds_write_b32 v11, v8 offset:128 + v_or_b32_e32 v8, 12, v17 + v_xor_b32_e32 v8, v8, v37 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v11, s18, v20 + ds_write_b32 v20, v16 offset:128 + v_or_b32_e32 v16, 13, v17 + v_xor_b32_e32 v16, v16, v37 + v_sub_u32_e32 v8, v16, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v8, v20, s18, v8 + ds_write_b32 v8, v12 offset:128 + v_or_b32_e32 v12, 14, v17 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v16, v12, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v8, s18, v16 + ds_write_b32 v16, v21 offset:128 + v_or_b32_e32 v17, 15, v17 + v_xor_b32_e32 v17, v17, v37 + v_sub_u32_e32 v12, v17, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v16, s18, v12 + ds_write_b32 v12, v9 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v9, v24, v24, s27 + v_perm_b32 v17, v25, v25, s27 + v_perm_b32 v21, v26, v26, s27 + v_perm_b32 v24, v27, v27, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v25, v28, v28, s27 + v_perm_b32 v26, v29, v29, s27 + v_perm_b32 v27, v30, v30, s27 + v_perm_b32 v28, v31, v31, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v29, v32, v32, s27 + v_perm_b32 v30, v33, v33, s27 + v_perm_b32 v31, v34, v34, s27 + v_perm_b32 v32, v35, v35, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v33, v38, v38, s27 + v_perm_b32 v34, v39, v39, s27 + v_perm_b32 v35, v40, v40, s27 + v_perm_b32 v38, v41, v41, s27 + v_perm_b32 v39, v25, v9, s25 + v_perm_b32 v40, v33, v29, s25 + v_perm_b32 v41, v40, v39, s19 + v_perm_b32 v39, v40, v39, s24 + v_perm_b32 v9, v25, v9, s26 + v_perm_b32 v25, v33, v29, s26 + v_perm_b32 v29, v25, v9, s19 + v_perm_b32 v9, v25, v9, s24 + v_perm_b32 v25, v26, v17, s25 + v_perm_b32 v33, v34, v30, s25 + v_perm_b32 v40, v33, v25, s19 + v_perm_b32 v25, v33, v25, s24 + v_perm_b32 v17, v26, v17, s26 + v_perm_b32 v26, v34, v30, s26 + v_perm_b32 v30, v26, v17, s19 + v_perm_b32 v17, v26, v17, s24 + v_perm_b32 v26, v27, v21, s25 + v_perm_b32 v33, v35, v31, s25 + v_perm_b32 v34, v33, v26, s19 + v_perm_b32 v26, v33, v26, s24 + v_perm_b32 v21, v27, v21, s26 + v_perm_b32 v27, v35, v31, s26 + v_perm_b32 v31, v27, v21, s19 + v_perm_b32 v21, v27, v21, s24 + v_perm_b32 v27, v28, v24, s25 + v_perm_b32 v33, v38, v32, s25 + v_perm_b32 v35, v33, v27, s19 + v_perm_b32 v27, v33, v27, s24 + v_perm_b32 v24, v28, v24, s26 + v_perm_b32 v28, v38, v32, s26 + v_perm_b32 v32, v28, v24, s19 + v_perm_b32 v24, v28, v24, s24 + ds_write_b32 v42, v41 offset:16384 + ds_write_b32 v48, v39 offset:16512 + ds_write_b32 v22, v29 offset:16512 + ds_write_b32 v23, v9 offset:16512 + ds_write_b32 v47, v40 offset:16512 + ds_write_b32 v6, v25 offset:16512 + ds_write_b32 v13, v30 offset:16512 + ds_write_b32 v10, v17 offset:16512 + ds_write_b32 v14, v34 offset:16512 + ds_write_b32 v7, v26 offset:16512 + ds_write_b32 v15, v31 offset:16512 + ds_write_b32 v11, v21 offset:16512 + ds_write_b32 v20, v35 offset:16512 + ds_write_b32 v8, v27 offset:16512 + ds_write_b32 v16, v32 offset:16512 + ds_write_b32 v12, v24 offset:16512 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_add_u32 v21, v46, 2, v44 + v_lshrrev_b16_e32 v9, 3, v43 + v_add_u32_e32 v8, 16, v45 + v_xor_b32_e32 v6, v8, v4 + v_sub_u32_e32 v7, v9, v5 + v_lshlrev_b32_e32 v23, 12, v7 + v_lshlrev_b32_e32 v7, 2, v6 + v_add3_u32 v22, v23, v44, v7 + v_add_u32_e32 v7, 16, v43 + v_lshrrev_b32_e32 v10, 5, v7 + v_lshrrev_b16_e32 v7, 3, v7 + v_and_b32_e32 v7, 3, v7 + v_sub_u16_e32 v11, v7, v9 + v_bfe_i32 v11, v11, 0, 16 + v_lshlrev_b32_e32 v12, 4, v10 + v_or_b32_e32 v13, v12, v4 + v_and_b32_e32 v24, 31, v13 + v_xor_b32_e32 v13, v45, v24 + v_sub_u32_e32 v6, v13, v6 + v_lshlrev_b32_e32 v14, 11, v10 + v_lshlrev_b32_e32 v6, 2, v6 + v_lshl_or_b32 v15, v11, 12, v14 + v_add3_u32 v25, v6, v15, v22 + v_add_u32_e32 v6, 20, v43 + v_lshrrev_b32_e32 v11, 5, v6 + v_sub_u32_e32 v10, v11, v10 + v_lshrrev_b16_e32 v6, 3, v6 + v_and_b32_e32 v6, 3, v6 + v_sub_u16_e32 v7, v6, v7 + v_bfe_i32 v7, v7, 0, 16 + v_lshlrev_b32_e32 v17, 4, v11 + v_or_b32_e32 v14, v17, v4 + v_and_b32_e32 v26, 31, v14 + v_xor_b32_e32 v14, v8, v26 + v_sub_u32_e32 v13, v14, v13 + v_lshlrev_b32_e32 v10, 11, v10 + v_lshlrev_b32_e32 v13, 2, v13 + v_lshl_add_u32 v16, v7, 12, v10 + v_add3_u32 v27, v13, v16, v25 + v_sub_u16_e32 v6, v9, v6 + v_bfe_i32 v6, v6, 0, 16 + v_or_b32_e32 v28, 16, v4 + v_xor_b32_e32 v7, v45, v28 + v_sub_u32_e32 v10, v7, v14 + v_lshlrev_b32_e32 v11, 11, v11 + v_xor_b32_e32 v11, 0x800, v11 + v_lshlrev_b32_e32 v13, 2, v10 + v_lshl_add_u32 v10, v6, 12, v11 + v_add3_u32 v29, v13, v10, v27 + v_xor_b32_e32 v6, v8, v28 + v_sub_u32_e32 v7, v6, v7 + v_lshl_add_u32 v30, v7, 2, v29 + v_add_u32_e32 v7, 48, v43 + v_lshrrev_b32_e32 v11, 5, v7 + v_lshlrev_b32_e32 v13, 11, v11 + v_lshrrev_b16_e32 v7, 3, v7 + v_and_b32_e32 v7, 3, v7 + v_sub_u16_e32 v14, v7, v9 + v_lshlrev_b32_e32 v31, 4, v11 + v_or_b32_e32 v20, v31, v4 + v_and_b32_e32 v32, 31, v20 + v_xor_b32_e32 v20, v45, v32 + v_sub_u32_e32 v6, v20, v6 + v_lshlrev_b32_e32 v33, 2, v6 + v_mov_b32_e32 v34, 12 + v_lshlrev_b32_sdwa v6, v34, sext(v14) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v6, v13, v6, s11 + v_add3_u32 v33, v33, v6, v30 + v_add_u32_e32 v13, 52, v43 + v_lshrrev_b32_e32 v35, 5, v13 + v_sub_u32_e32 v11, v35, v11 + v_lshrrev_b16_e32 v13, 3, v13 + v_and_b32_e32 v13, 3, v13 + v_sub_u16_e32 v7, v13, v7 + v_bfe_i32 v14, v7, 0, 16 + v_lshlrev_b32_e32 v38, 4, v35 + v_or_b32_e32 v39, v38, v4 + v_and_b32_e32 v7, 31, v39 + v_xor_b32_e32 v40, v8, v7 + v_sub_u32_e32 v8, v40, v20 + v_lshlrev_b32_e32 v11, 11, v11 + v_lshlrev_b32_e32 v20, 2, v8 + v_lshl_add_u32 v8, v14, 12, v11 + v_add3_u32 v14, v20, v8, v33 + v_add_u32_e32 v11, 64, v2 + v_lshrrev_b32_e32 v41, 4, v11 + v_sub_u16_e32 v9, v9, v13 + v_sub_u32_e32 v13, v39, v38 + v_ashrrev_i32_e32 v11, 31, v13 + v_lshrrev_b32_e32 v11, 27, v11 + v_add_u32_e32 v11, v13, v11 + v_and_b32_e32 v11, 0xffffffe0, v11 + v_sub_u32_e32 v38, v13, v11 + v_xor_b32_e32 v11, v41, v38 + v_sub_u32_e32 v20, v11, v40 + v_lshlrev_b32_e32 v20, 2, v20 + v_lshlrev_b32_sdwa v9, v34, sext(v9) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v34, 11, v35 + v_sub_u32_e32 v34, v9, v34 + v_add3_u32 v20, v20, v34, v14 + v_add_u32_e32 v35, 16, v41 + v_xor_b32_e32 v9, v35, v38 + v_sub_u32_e32 v11, v9, v11 + v_lshl_add_u32 v11, v11, 2, v20 + v_add_u32_e32 v12, v13, v12 + v_ashrrev_i32_e32 v39, 31, v12 + v_lshrrev_b32_e32 v39, 27, v39 + v_add_u32_e32 v39, v12, v39 + v_and_b32_e32 v39, 0xffffffe0, v39 + v_sub_u32_e32 v39, v12, v39 + v_xor_b32_e32 v12, v41, v39 + v_sub_u32_e32 v9, v12, v9 + v_lshl_add_u32 v9, v9, 2, v15 + v_add_u32_e32 v9, v9, v11 + ds_read_b32 v72, v20 + ds_read_b32 v73, v11 + ds_read_b32 v80, v9 + v_add_u32_e32 v11, v13, v17 + v_ashrrev_i32_e32 v17, 31, v11 + v_lshrrev_b32_e32 v17, 27, v17 + v_add_u32_e32 v17, v11, v17 + v_and_b32_e32 v17, 0xffffffe0, v17 + v_sub_u32_e32 v40, v11, v17 + v_xor_b32_e32 v20, v35, v40 + v_sub_u32_e32 v11, v20, v12 + v_lshl_add_u32 v11, v11, 2, v16 + v_add_u32_e32 v42, v9, v11 + v_add_u32_e32 v12, 16, v13 + v_ashrrev_i32_e32 v17, 31, v12 + v_lshrrev_b32_e32 v17, 27, v17 + v_add_u32_e32 v17, v12, v17 + v_and_b32_e32 v17, 0xffffffe0, v17 + v_sub_u32_e32 v17, v12, v17 + v_xor_b32_e32 v43, v41, v17 + v_sub_u32_e32 v12, v43, v20 + v_lshl_add_u32 v12, v12, 2, v10 + v_add_u32_e32 v20, v42, v12 + v_xor_b32_e32 v44, v35, v17 + v_add_u32_e32 v13, v13, v31 + v_ashrrev_i32_e32 v31, 31, v13 + v_lshrrev_b32_e32 v31, 27, v31 + v_add_u32_e32 v31, v13, v31 + v_and_b32_e32 v31, 0xffffffe0, v31 + v_sub_u32_e32 v13, v13, v31 + ds_read_b32 v62, v21 + ds_read_b32 v63, v22 + ds_read_b32 v82, v25 + ds_read_b32 v83, v27 + ds_read_b32 v84, v29 + ds_read_b32 v85, v30 + ds_read_b32 v22, v33 + ds_read_b32 v86, v19 offset:16384 + v_or_b32_e32 v21, 16, v3 + v_xor_b32_e32 v25, v21, v4 + v_sub_u32_e32 v18, v25, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v19, v23, v18 + v_xor_b32_e32 v19, v3, v24 + v_sub_u32_e32 v23, v19, v25 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v23, v15, v18 + v_xor_b32_e32 v24, v21, v26 + v_sub_u32_e32 v19, v24, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v19, v19, v16, v23 + v_xor_b32_e32 v25, v3, v28 + v_sub_u32_e32 v24, v25, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v24, v10, v19 + v_xor_b32_e32 v26, v21, v28 + v_sub_u32_e32 v25, v26, v25 + v_lshl_add_u32 v25, v25, 2, v24 + v_xor_b32_e32 v27, v3, v32 + v_sub_u32_e32 v26, v27, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add3_u32 v26, v26, v6, v25 + v_xor_b32_e32 v21, v21, v7 + v_sub_u32_e32 v27, v21, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v27, v27, v8, v26 + ds_read_b32 v87, v18 offset:16384 + ds_read_b32 v88, v23 offset:16384 + ds_read_b32 v89, v19 offset:16384 + ds_read_b32 v90, v24 offset:16384 + ds_read_b32 v91, v25 offset:16384 + ds_read_b32 v92, v26 offset:16384 + ds_read_b32 v93, v27 offset:16384 + v_or_b32_e32 v18, 4, v3 + v_xor_b32_e32 v19, v18, v38 + v_sub_u32_e32 v21, v19, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v21, v34, v27 + v_or_b32_e32 v23, 20, v3 + v_xor_b32_e32 v24, v23, v38 + v_sub_u32_e32 v19, v24, v19 + v_lshl_add_u32 v19, v19, 2, v21 + ds_read_b32 v94, v21 offset:16384 + ds_read_b32 v95, v19 offset:16384 + v_xor_b32_e32 v21, v18, v39 + v_sub_u32_e32 v24, v21, v24 + v_lshl_add_u32 v24, v24, 2, v15 + v_add_u32_e32 v19, v24, v19 + v_xor_b32_e32 v24, v23, v40 + v_sub_u32_e32 v21, v24, v21 + v_lshl_add_u32 v21, v21, 2, v16 + v_add_u32_e32 v25, v19, v21 + v_xor_b32_e32 v26, v18, v17 + v_sub_u32_e32 v24, v26, v24 + v_lshl_add_u32 v24, v24, 2, v10 + v_add_u32_e32 v27, v25, v24 + v_xor_b32_e32 v28, v23, v17 + v_sub_u32_e32 v26, v28, v26 + v_lshlrev_b32_e32 v26, 2, v26 + v_add_u32_e32 v29, v27, v26 + v_xor_b32_e32 v18, v18, v13 + v_sub_u32_e32 v28, v18, v28 + v_lshl_add_u32 v28, v28, 2, v6 + v_add_u32_e32 v30, v29, v28 + v_xor_b32_e32 v23, v23, v7 + v_sub_u32_e32 v18, v23, v18 + v_lshl_add_u32 v18, v18, 2, v8 + v_add_u32_e32 v31, v30, v18 + v_or_b32_e32 v32, 8, v3 + v_xor_b32_e32 v33, v32, v38 + v_sub_u32_e32 v23, v33, v23 + v_lshl_add_u32 v45, v23, 2, v34 + v_add_u32_e32 v23, v31, v45 + ds_read_b32 v96, v23 offset:16384 + v_or_b32_e32 v46, 24, v3 + v_xor_b32_e32 v47, v46, v38 + v_sub_u32_e32 v33, v47, v33 + v_lshlrev_b32_e32 v33, 2, v33 + v_add_u32_e32 v23, v23, v33 + ds_read_b32 v97, v23 offset:16384 + v_xor_b32_e32 v48, v32, v39 + v_sub_u32_e32 v47, v48, v47 + v_lshl_add_u32 v47, v47, 2, v15 + v_add_u32_e32 v23, v23, v47 + v_xor_b32_e32 v49, v46, v40 + v_sub_u32_e32 v48, v49, v48 + v_lshl_add_u32 v48, v48, 2, v16 + v_add_u32_e32 v50, v23, v48 + v_xor_b32_e32 v51, v32, v17 + v_sub_u32_e32 v49, v51, v49 + v_lshl_add_u32 v49, v49, 2, v10 + v_add_u32_e32 v52, v50, v49 + v_xor_b32_e32 v53, v46, v17 + v_sub_u32_e32 v51, v53, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add_u32_e32 v54, v52, v51 + v_xor_b32_e32 v32, v32, v13 + v_sub_u32_e32 v53, v32, v53 + v_lshl_add_u32 v53, v53, 2, v6 + s_waitcnt lgkmcnt(10) + v_mfma_i32_32x32x16_i8 a[160:175], v[62:63], v[86:87], 0 + v_add_u32_e32 v55, v54, v53 + v_xor_b32_e32 v46, v46, v7 + v_sub_u32_e32 v32, v46, v32 + v_lshl_add_u32 v32, v32, 2, v8 + v_add_u32_e32 v56, v55, v32 + v_or_b32_e32 v57, 12, v3 + v_xor_b32_e32 v58, v57, v38 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[96:111], v[62:63], v[94:95], 0 + v_sub_u32_e32 v46, v58, v46 + v_lshl_add_u32 v46, v46, 2, v34 + v_add_u32_e32 v59, v56, v46 + ds_read_b32 v98, v59 offset:16384 + v_or_b32_e32 v3, 28, v3 + v_xor_b32_e32 v60, v3, v38 + v_sub_u32_e32 v58, v60, v58 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[62:63], v[96:97], 0 + v_lshlrev_b32_e32 v58, 2, v58 + v_add_u32_e32 v59, v59, v58 + ds_read_b32 v99, v59 offset:16384 + v_sub_u32_e32 v43, v44, v43 + v_lshlrev_b32_e32 v43, 2, v43 + v_add_u32_e32 v61, v20, v43 + v_xor_b32_e32 v41, v41, v13 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[62:63], v[98:99], 0 + v_sub_u32_e32 v44, v41, v44 + v_lshl_add_u32 v44, v44, 2, v6 + v_add_u32_e32 v62, v61, v44 + v_xor_b32_e32 v35, v35, v7 + v_sub_u32_e32 v41, v35, v41 + v_lshl_add_u32 v41, v41, 2, v8 + v_add_u32_e32 v63, v62, v41 + v_mfma_i32_32x32x16_i8 a[192:207], v[72:73], v[86:87], 0 + v_add_u32_e32 v64, 0x80, v2 + v_lshrrev_b32_e32 v64, 4, v64 + v_xor_b32_e32 v65, v64, v38 + v_sub_u32_e32 v35, v65, v35 + v_lshl_add_u32 v35, v35, 2, v34 + v_add_u32_e32 v66, v63, v35 + ds_read_b32 v100, v66 + v_mfma_i32_32x32x16_i8 a[128:143], v[72:73], v[94:95], 0 + v_add_u32_e32 v67, 16, v64 + v_xor_b32_e32 v68, v67, v38 + v_sub_u32_e32 v65, v68, v65 + v_lshlrev_b32_e32 v65, 2, v65 + v_add_u32_e32 v66, v66, v65 + ds_read_b32 v101, v66 + v_xor_b32_e32 v69, v64, v39 + v_mfma_i32_32x32x16_i8 a[64:79], v[72:73], v[96:97], 0 + v_sub_u32_e32 v68, v69, v68 + v_lshl_add_u32 v68, v68, 2, v15 + v_add_u32_e32 v66, v66, v68 + v_xor_b32_e32 v70, v67, v40 + v_sub_u32_e32 v69, v70, v69 + v_lshl_add_u32 v69, v69, 2, v16 + v_add_u32_e32 v71, v66, v69 + v_mfma_i32_32x32x16_i8 a[16:31], v[72:73], v[98:99], 0 + v_xor_b32_e32 v72, v64, v17 + v_sub_u32_e32 v70, v72, v70 + v_lshl_add_u32 v70, v70, 2, v10 + v_add_u32_e32 v73, v71, v70 + v_xor_b32_e32 v74, v67, v17 + v_sub_u32_e32 v72, v74, v72 + v_lshlrev_b32_e32 v72, 2, v72 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[100:101], v[86:87], 0 + v_add_u32_e32 v75, v73, v72 + v_xor_b32_e32 v64, v64, v13 + v_sub_u32_e32 v74, v64, v74 + v_lshl_add_u32 v74, v74, 2, v6 + v_add_u32_e32 v76, v75, v74 + v_xor_b32_e32 v67, v67, v7 + v_sub_u32_e32 v64, v67, v64 + v_mfma_i32_32x32x16_i8 a[144:159], v[100:101], v[94:95], 0 + v_lshl_add_u32 v64, v64, 2, v8 + v_add_u32_e32 v77, v76, v64 + v_add_u32_e32 v2, 0xc0, v2 + v_lshrrev_b32_e32 v2, 4, v2 + v_xor_b32_e32 v78, v2, v38 + v_sub_u32_e32 v67, v78, v67 + v_lshl_add_u32 v34, v67, 2, v34 + v_mfma_i32_32x32x16_i8 a[80:95], v[100:101], v[96:97], 0 + v_add_u32_e32 v67, v77, v34 + ds_read_b32 v102, v67 + v_add_u32_e32 v79, 16, v2 + v_xor_b32_e32 v38, v79, v38 + v_sub_u32_e32 v78, v38, v78 + v_lshlrev_b32_e32 v78, 2, v78 + v_add_u32_e32 v67, v67, v78 + v_mfma_i32_32x32x16_i8 a[32:47], v[100:101], v[98:99], 0 + ds_read_b32 v103, v67 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[102:103], v[86:87], 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[102:103], v[94:95], 0 + v_mfma_i32_32x32x16_i8 a[112:127], v[102:103], v[96:97], 0 + v_mfma_i32_32x32x16_i8 a[240:255], v[102:103], v[98:99], 0 + v_mfma_i32_32x32x16_i8 a[160:175], v[82:83], v[88:89], a[160:175] + ds_read_b32 v86, v19 offset:16384 + ds_read_b32 v87, v25 offset:16384 + ds_read_b32 v94, v23 offset:16384 + ds_read_b32 v95, v50 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[96:111], v[82:83], v[86:87], a[96:111] + v_xor_b32_e32 v23, v57, v39 + v_sub_u32_e32 v25, v23, v60 + v_lshl_add_u32 v25, v25, 2, v15 + v_add_u32_e32 v50, v59, v25 + ds_read_b32 v96, v50 offset:16384 + v_xor_b32_e32 v59, v3, v40 + v_sub_u32_e32 v23, v59, v23 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[82:83], v[94:95], a[48:63] + v_lshl_add_u32 v60, v23, 2, v16 + v_add_u32_e32 v23, v50, v60 + ds_read_b32 v97, v23 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[82:83], v[96:97], a[0:15] + ds_read_b32 v81, v42 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[80:81], v[88:89], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[80:81], v[86:87], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[80:81], v[94:95], a[64:79] + ds_read_b32 v82, v66 + v_mfma_i32_32x32x16_i8 a[16:31], v[80:81], v[96:97], a[16:31] + ds_read_b32 v83, v71 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[82:83], v[88:89], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[82:83], v[86:87], a[144:159] + v_xor_b32_e32 v39, v2, v39 + v_sub_u32_e32 v38, v39, v38 + v_mfma_i32_32x32x16_i8 a[80:95], v[82:83], v[94:95], a[80:95] + v_lshl_add_u32 v15, v38, 2, v15 + v_add_u32_e32 v38, v67, v15 + ds_read_b32 v66, v38 + v_xor_b32_e32 v40, v79, v40 + v_sub_u32_e32 v39, v40, v39 + v_lshl_add_u32 v16, v39, 2, v16 + v_add_u32_e32 v38, v38, v16 + v_mfma_i32_32x32x16_i8 a[32:47], v[82:83], v[96:97], a[32:47] + ds_read_b32 v67, v38 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[66:67], v[88:89], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[66:67], v[86:87], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[66:67], v[94:95], a[112:127] + v_mfma_i32_32x32x16_i8 a[240:255], v[66:67], v[96:97], a[240:255] + v_mfma_i32_32x32x16_i8 a[160:175], v[84:85], v[90:91], a[160:175] + ds_read_b32 v66, v27 offset:16384 + ds_read_b32 v67, v29 offset:16384 + ds_read_b32 v80, v52 offset:16384 + ds_read_b32 v81, v54 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[96:111], v[84:85], v[66:67], a[96:111] + v_xor_b32_e32 v27, v57, v17 + v_sub_u32_e32 v29, v27, v59 + v_lshl_add_u32 v29, v29, 2, v10 + v_add_u32_e32 v23, v23, v29 + ds_read_b32 v82, v23 offset:16384 + v_xor_b32_e32 v39, v3, v17 + v_sub_u32_e32 v27, v39, v27 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[84:85], v[80:81], a[48:63] + v_lshlrev_b32_e32 v27, 2, v27 + v_add_u32_e32 v42, v23, v27 + ds_read_b32 v83, v42 offset:16384 + ds_read_b32 v86, v20 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[84:85], v[82:83], a[0:15] + ds_read_b32 v87, v61 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[86:87], v[90:91], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[86:87], v[66:67], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[86:87], v[80:81], a[64:79] + ds_read_b32 v84, v73 + v_mfma_i32_32x32x16_i8 a[16:31], v[86:87], v[82:83], a[16:31] + ds_read_b32 v85, v75 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[84:85], v[90:91], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[84:85], v[66:67], a[144:159] + v_xor_b32_e32 v20, v2, v17 + v_sub_u32_e32 v23, v20, v40 + v_mfma_i32_32x32x16_i8 a[80:95], v[84:85], v[80:81], a[80:95] + v_lshl_add_u32 v10, v23, 2, v10 + v_add_u32_e32 v23, v38, v10 + ds_read_b32 v86, v23 + v_xor_b32_e32 v17, v79, v17 + v_sub_u32_e32 v20, v17, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add_u32_e32 v38, v23, v20 + v_mfma_i32_32x32x16_i8 a[32:47], v[84:85], v[82:83], a[32:47] + ds_read_b32 v87, v38 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[86:87], v[90:91], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[86:87], v[66:67], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[86:87], v[80:81], a[112:127] + ds_read_b32 v23, v14 + v_mfma_i32_32x32x16_i8 a[240:255], v[86:87], v[82:83], a[240:255] + v_add3_u32 v14, v21, v19, v24 + v_add3_u32 v14, v26, v14, v28 + ds_read_b32 v30, v30 offset:16384 + ds_read_b32 v31, v31 offset:16384 + v_add3_u32 v14, v18, v14, v45 + v_add3_u32 v14, v14, v33, v47 + v_add3_u32 v14, v48, v14, v49 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[160:175], v[22:23], v[92:93], a[160:175] + v_add3_u32 v14, v51, v14, v53 + ds_read_b32 v48, v55 offset:16384 + ds_read_b32 v49, v56 offset:16384 + v_add3_u32 v14, v32, v14, v46 + v_add3_u32 v14, v14, v58, v25 + v_add3_u32 v14, v60, v14, v29 + v_xor_b32_e32 v18, v57, v13 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[96:111], v[22:23], v[30:31], a[96:111] + v_sub_u32_e32 v19, v18, v39 + v_lshl_add_u32 v19, v19, 2, v6 + v_add3_u32 v14, v27, v14, v19 + v_add_u32_e32 v19, v42, v19 + ds_read_b32 v24, v19 offset:16384 + v_xor_b32_e32 v3, v3, v7 + v_sub_u32_e32 v3, v3, v18 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[22:23], v[48:49], a[48:63] + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v3, v8, v14 + ds_read_b32 v25, v3 offset:16384 + ds_read_b32 v18, v62 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[22:23], v[24:25], a[0:15] + ds_read_b32 v19, v63 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[18:19], v[92:93], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[18:19], v[30:31], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[18:19], v[48:49], a[64:79] + ds_read_b32 v22, v76 + v_mfma_i32_32x32x16_i8 a[16:31], v[18:19], v[24:25], a[16:31] + ds_read_b32 v23, v77 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[22:23], v[92:93], a[208:223] + v_add3_u32 v3, v11, v9, v12 + v_add3_u32 v3, v43, v3, v44 + v_add3_u32 v3, v41, v3, v35 + v_add3_u32 v3, v3, v65, v68 + v_add3_u32 v3, v69, v3, v70 + v_mfma_i32_32x32x16_i8 a[144:159], v[22:23], v[30:31], a[144:159] + v_add3_u32 v3, v72, v3, v74 + v_add3_u32 v3, v64, v3, v34 + v_add3_u32 v3, v3, v78, v15 + v_add3_u32 v3, v16, v3, v10 + v_xor_b32_e32 v2, v2, v13 + v_sub_u32_e32 v9, v2, v17 + v_lshl_add_u32 v6, v9, 2, v6 + v_mfma_i32_32x32x16_i8 a[80:95], v[22:23], v[48:49], a[80:95] + v_add3_u32 v3, v20, v3, v6 + v_xor_b32_e32 v7, v79, v7 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v2, v8, v3 + ds_read_b32 v3, v2 + v_add_u32_e32 v2, v38, v6 + v_mfma_i32_32x32x16_i8 a[32:47], v[22:23], v[24:25], a[32:47] + ds_read_b32 v2, v2 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[92:93], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[30:31], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[48:49], a[112:127] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[24:25], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB35_3 + s_branch .LBB35_10 +.LBB35_2: + ; implicit-def: $agpr127 + ; implicit-def: $agpr191 + ; implicit-def: $agpr239 + ; implicit-def: $agpr47 + ; implicit-def: $agpr95 + ; implicit-def: $agpr159 + ; implicit-def: $agpr223 + ; implicit-def: $agpr31 + ; implicit-def: $agpr79 + ; implicit-def: $agpr143 + ; implicit-def: $agpr207 + ; implicit-def: $agpr15 + ; implicit-def: $agpr63 + ; implicit-def: $agpr111 + ; implicit-def: $agpr175 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB35_3: + v_readfirstlane_b32 s15, v0 + v_lshlrev_b32_e32 v3, 4, v4 + s_lshr_b32 s26, s15, 2 + v_mov_b32_e32 v2, s26 + v_and_b32_e32 v1, 0x3ffffffc, v1 + v_and_b32_e32 v2, 0x3ffffff0, v2 + v_add_u32_e32 v9, v2, v1 + v_or_b32_e32 v2, s20, v3 + v_mad_u64_u32 v[34:35], s[18:19], v9, s23, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[14:17], v34, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v34 + buffer_load_dwordx4 v[18:21], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[22:25], v2, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[28:31], v2, s[8:11], 0 offen + v_lshlrev_b32_e32 v2, 12, v5 + v_lshlrev_b32_e32 v11, 3, v5 + s_mov_b32 s27, 0x3020504 + s_mov_b32 s24, 0x5010400 + s_mov_b32 s18, 0x5040100 + s_mov_b32 s19, 0x7060302 + s_mov_b32 s25, 0x7030602 + v_lshl_or_b32 v13, v4, 7, v2 + v_or_b32_e32 v2, s21, v3 + s_lshr_b32 s28, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s29, s26, 0x3ffffff0 + s_and_b32 s26, s26, 0x3fffffe0 + v_and_or_b32 v3, s28, 32, v37 + v_or_b32_e32 v7, s26, v37 + v_add_u32_e32 v10, s29, v1 + v_lshrrev_b32_e32 v6, 4, v3 + v_lshrrev_b32_e32 v8, 4, v7 + v_mad_u64_u32 v[2:3], s[28:29], v10, s22, v[2:3] + v_xor_b32_e32 v3, v6, v4 + v_xor_b32_e32 v26, v8, v4 + v_lshl_or_b32 v46, v3, 2, v13 + v_add_u32_e32 v10, s22, v2 + buffer_load_dwordx4 v[38:41], v2, s[12:15], 0 offen + buffer_load_dwordx4 v[42:45], v10, s[12:15], 0 offen + v_add_u32_e32 v10, s22, v10 + v_add_u32_e32 v12, s22, v10 + buffer_load_dwordx4 v[48:51], v10, s[12:15], 0 offen + buffer_load_dwordx4 v[52:55], v12, s[12:15], 0 offen + s_waitcnt vmcnt(7) + v_perm_b32 v10, v14, v14, s27 + v_perm_b32 v12, v15, v15, s27 + v_perm_b32 v14, v16, v16, s27 + v_perm_b32 v15, v17, v17, s27 + s_waitcnt vmcnt(6) + v_perm_b32 v16, v18, v18, s27 + v_perm_b32 v17, v19, v19, s27 + v_perm_b32 v18, v20, v20, s27 + v_perm_b32 v19, v21, v21, s27 + s_waitcnt vmcnt(5) + v_perm_b32 v20, v22, v22, s27 + v_perm_b32 v21, v23, v23, s27 + v_perm_b32 v22, v24, v24, s27 + v_perm_b32 v23, v25, v25, s27 + v_perm_b32 v24, v16, v10, s24 + v_perm_b32 v10, v16, v10, s25 + v_perm_b32 v16, v17, v12, s24 + v_perm_b32 v12, v17, v12, s25 + v_perm_b32 v17, v18, v14, s24 + v_perm_b32 v14, v18, v14, s25 + v_perm_b32 v18, v19, v15, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v25, v28, v28, s27 + v_perm_b32 v27, v29, v29, s27 + v_perm_b32 v28, v30, v30, s27 + v_perm_b32 v29, v31, v31, s27 + v_perm_b32 v30, v25, v20, s24 + v_perm_b32 v20, v25, v20, s25 + v_perm_b32 v25, v27, v21, s24 + v_perm_b32 v21, v27, v21, s25 + v_perm_b32 v27, v28, v22, s24 + v_perm_b32 v22, v28, v22, s25 + v_perm_b32 v28, v29, v23, s24 + v_perm_b32 v31, v30, v24, s18 + v_perm_b32 v24, v30, v24, s19 + v_perm_b32 v30, v20, v10, s18 + v_perm_b32 v10, v20, v10, s19 + v_perm_b32 v20, v25, v16, s18 + v_perm_b32 v16, v25, v16, s19 + v_perm_b32 v25, v21, v12, s18 + v_perm_b32 v12, v21, v12, s19 + v_perm_b32 v21, v27, v17, s18 + v_perm_b32 v17, v27, v17, s19 + v_perm_b32 v27, v22, v14, s18 + v_perm_b32 v14, v22, v14, s19 + v_perm_b32 v22, v28, v18, s18 + v_perm_b32 v18, v28, v18, s19 + v_perm_b32 v15, v19, v15, s25 + v_perm_b32 v19, v29, v23, s25 + v_perm_b32 v23, v19, v15, s18 + v_perm_b32 v15, v19, v15, s19 + v_lshrrev_b32_e32 v19, 1, v9 + v_and_b32_e32 v19, 16, v19 + v_xor_b32_e32 v28, v19, v37 + v_lshlrev_b32_e32 v29, 9, v9 + v_and_b32_e32 v29, 0x3000, v29 + v_lshlrev_b32_e32 v9, 6, v9 + s_movk_i32 s26, 0xf800 + v_and_b32_e32 v9, 0xfffff800, v9 + v_add_u32_e32 v9, v29, v9 + v_lshl_or_b32 v9, v28, 2, v9 + ds_write_b32 v9, v31 + v_or_b32_e32 v29, 1, v19 + v_xor_b32_e32 v29, v29, v37 + v_sub_u32_e32 v28, v29, v28 + v_lshl_add_u32 v28, v28, 2, v9 + ds_write_b32 v28, v24 offset:128 + v_or_b32_e32 v24, 2, v19 + v_xor_b32_e32 v24, v24, v37 + v_sub_u32_e32 v29, v24, v29 + v_lshlrev_b32_e32 v29, 2, v29 + s_movk_i32 s28, 0x80 + v_add3_u32 v29, v28, s28, v29 + ds_write_b32 v29, v30 offset:128 + v_or_b32_e32 v30, 3, v19 + v_xor_b32_e32 v30, v30, v37 + v_sub_u32_e32 v24, v30, v24 + v_lshlrev_b32_e32 v24, 2, v24 + v_add3_u32 v24, v29, s28, v24 + ds_write_b32 v24, v10 offset:128 + v_or_b32_e32 v10, 4, v19 + v_xor_b32_e32 v10, v10, v37 + v_sub_u32_e32 v30, v10, v30 + v_lshlrev_b32_e32 v30, 2, v30 + v_add3_u32 v30, v24, s28, v30 + ds_write_b32 v30, v20 offset:128 + v_or_b32_e32 v20, 5, v19 + v_xor_b32_e32 v20, v20, v37 + v_sub_u32_e32 v10, v20, v10 + v_lshlrev_b32_e32 v10, 2, v10 + v_add3_u32 v10, v30, s28, v10 + ds_write_b32 v10, v16 offset:128 + v_or_b32_e32 v16, 6, v19 + v_xor_b32_e32 v16, v16, v37 + v_sub_u32_e32 v20, v16, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v20, v10, s28, v20 + ds_write_b32 v20, v25 offset:128 + v_or_b32_e32 v25, 7, v19 + v_xor_b32_e32 v25, v25, v37 + v_sub_u32_e32 v16, v25, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v20, s28, v16 + ds_write_b32 v16, v12 offset:128 + v_or_b32_e32 v12, 8, v19 + v_xor_b32_e32 v12, v12, v37 + v_sub_u32_e32 v25, v12, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v16, s28, v25 + ds_write_b32 v25, v21 offset:128 + v_or_b32_e32 v21, 9, v19 + v_xor_b32_e32 v21, v21, v37 + v_sub_u32_e32 v12, v21, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v25, s28, v12 + ds_write_b32 v12, v17 offset:128 + v_or_b32_e32 v17, 10, v19 + v_xor_b32_e32 v17, v17, v37 + v_sub_u32_e32 v21, v17, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v12, s28, v21 + ds_write_b32 v21, v27 offset:128 + v_or_b32_e32 v27, 11, v19 + v_xor_b32_e32 v27, v27, v37 + v_sub_u32_e32 v17, v27, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v17, v21, s28, v17 + ds_write_b32 v17, v14 offset:128 + v_or_b32_e32 v14, 12, v19 + v_xor_b32_e32 v14, v14, v37 + v_sub_u32_e32 v27, v14, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v27, v17, s28, v27 + ds_write_b32 v27, v22 offset:128 + v_or_b32_e32 v22, 13, v19 + v_xor_b32_e32 v22, v22, v37 + v_sub_u32_e32 v14, v22, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v27, s28, v14 + ds_write_b32 v14, v18 offset:128 + v_or_b32_e32 v18, 14, v19 + v_xor_b32_e32 v18, v18, v37 + v_sub_u32_e32 v22, v18, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v14, s28, v22 + ds_write_b32 v22, v23 offset:128 + v_or_b32_e32 v19, 15, v19 + v_xor_b32_e32 v19, v19, v37 + v_sub_u32_e32 v18, v19, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v22, s28, v18 + ds_write_b32 v18, v15 offset:128 + s_waitcnt vmcnt(3) + v_perm_b32 v15, v38, v38, s27 + v_perm_b32 v19, v39, v39, s27 + v_perm_b32 v23, v40, v40, s27 + v_perm_b32 v31, v41, v41, s27 + s_waitcnt vmcnt(2) + v_perm_b32 v32, v42, v42, s27 + v_perm_b32 v33, v43, v43, s27 + v_perm_b32 v35, v44, v44, s27 + v_perm_b32 v38, v45, v45, s27 + s_waitcnt vmcnt(1) + v_perm_b32 v39, v48, v48, s27 + v_perm_b32 v40, v49, v49, s27 + v_perm_b32 v41, v50, v50, s27 + v_perm_b32 v42, v51, v51, s27 + s_waitcnt vmcnt(0) + v_perm_b32 v43, v52, v52, s27 + v_perm_b32 v44, v53, v53, s27 + v_perm_b32 v45, v54, v54, s27 + v_perm_b32 v47, v55, v55, s27 + v_perm_b32 v48, v32, v15, s24 + v_perm_b32 v49, v43, v39, s24 + v_perm_b32 v50, v49, v48, s18 + v_perm_b32 v48, v49, v48, s19 + v_perm_b32 v15, v32, v15, s25 + v_perm_b32 v32, v43, v39, s25 + v_perm_b32 v39, v32, v15, s18 + v_perm_b32 v15, v32, v15, s19 + v_perm_b32 v32, v33, v19, s24 + v_perm_b32 v43, v44, v40, s24 + v_perm_b32 v49, v43, v32, s18 + v_perm_b32 v32, v43, v32, s19 + v_perm_b32 v19, v33, v19, s25 + v_perm_b32 v33, v44, v40, s25 + v_perm_b32 v40, v33, v19, s18 + v_perm_b32 v19, v33, v19, s19 + v_perm_b32 v33, v35, v23, s24 + v_perm_b32 v43, v45, v41, s24 + v_perm_b32 v44, v43, v33, s18 + v_perm_b32 v33, v43, v33, s19 + v_perm_b32 v23, v35, v23, s25 + v_perm_b32 v35, v45, v41, s25 + v_perm_b32 v41, v35, v23, s18 + v_perm_b32 v23, v35, v23, s19 + v_perm_b32 v35, v38, v31, s24 + v_perm_b32 v43, v47, v42, s24 + v_perm_b32 v45, v43, v35, s18 + v_perm_b32 v35, v43, v35, s19 + v_perm_b32 v31, v38, v31, s25 + v_perm_b32 v38, v47, v42, s25 + v_perm_b32 v42, v38, v31, s18 + v_perm_b32 v31, v38, v31, s19 + ds_write_b32 v9, v50 offset:16384 + ds_write_b32 v28, v48 offset:16512 + ds_write_b32 v29, v39 offset:16512 + ds_write_b32 v24, v15 offset:16512 + ds_write_b32 v30, v49 offset:16512 + ds_write_b32 v10, v32 offset:16512 + ds_write_b32 v20, v40 offset:16512 + ds_write_b32 v16, v19 offset:16512 + ds_write_b32 v25, v44 offset:16512 + ds_write_b32 v12, v33 offset:16512 + ds_write_b32 v21, v41 offset:16512 + ds_write_b32 v17, v23 offset:16512 + ds_write_b32 v27, v45 offset:16512 + ds_write_b32 v14, v35 offset:16512 + ds_write_b32 v22, v42 offset:16512 + ds_write_b32 v18, v31 offset:16512 + s_andn2_b64 vcc, exec, s[2:3] + v_lshrrev_b16_e32 v18, 3, v11 + v_add_u32_e32 v19, 16, v8 + v_add_u32_e32 v25, 16, v11 + v_add_u32_e32 v24, 20, v11 + v_or_b32_e32 v10, 16, v4 + v_add_u32_e32 v23, 36, v11 + v_add_u32_e32 v22, 48, v11 + v_add_u32_e32 v21, 52, v11 + v_add_u32_e32 v20, 64, v7 + v_or_b32_e32 v17, 16, v6 + v_or_b32_e32 v16, 4, v6 + v_or_b32_e32 v15, 20, v6 + v_or_b32_e32 v14, 8, v6 + v_or_b32_e32 v12, 24, v6 + v_or_b32_e32 v11, 12, v6 + v_or_b32_e32 v9, 28, v6 + s_cbranch_vccnz .LBB35_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit1774.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v27, v19, v4 + v_sub_u32_e32 v28, v18, v5 + v_lshlrev_b32_e32 v28, 12, v28 + v_lshlrev_b32_e32 v29, 2, v27 + v_add3_u32 v75, v28, v13, v29 + v_lshrrev_b32_e32 v29, 5, v25 + v_lshrrev_b16_e32 v30, 3, v25 + v_and_b32_e32 v30, 3, v30 + v_sub_u16_e32 v31, v30, v18 + v_bfe_i32 v31, v31, 0, 16 + v_lshl_or_b32 v32, v29, 4, v4 + v_xor_b32_e32 v33, v8, v32 + v_sub_u32_e32 v27, v33, v27 + v_lshlrev_b32_e32 v35, 11, v29 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshl_or_b32 v31, v31, 12, v35 + v_add3_u32 v42, v27, v31, v75 + v_lshrrev_b32_e32 v27, 5, v24 + v_sub_u32_e32 v29, v27, v29 + v_lshrrev_b16_e32 v35, 3, v24 + v_and_b32_e32 v35, 3, v35 + v_sub_u16_e32 v30, v35, v30 + v_bfe_i32 v30, v30, 0, 16 + v_lshl_or_b32 v86, v27, 4, v4 + v_xor_b32_e32 v38, v19, v86 + v_sub_u32_e32 v33, v38, v33 + v_lshlrev_b32_e32 v29, 11, v29 + v_lshlrev_b32_e32 v33, 2, v33 + v_lshl_add_u32 v29, v30, 12, v29 + v_add3_u32 v43, v33, v29, v42 + v_sub_u16_e32 v30, v18, v35 + v_bfe_i32 v30, v30, 0, 16 + v_xor_b32_e32 v33, v8, v10 + v_sub_u32_e32 v35, v33, v38 + v_lshlrev_b32_e32 v27, 11, v27 + v_xor_b32_e32 v27, 0x800, v27 + v_lshlrev_b32_e32 v35, 2, v35 + v_lshl_or_b32 v27, v30, 12, v27 + v_add3_u32 v39, v35, v27, v43 + v_lshrrev_b32_e32 v30, 5, v23 + v_lshlrev_b32_e32 v35, 11, v30 + v_lshrrev_b16_e32 v38, 3, v23 + v_and_b32_e32 v38, 3, v38 + v_sub_u16_e32 v40, v38, v18 + v_lshl_or_b32 v41, v30, 4, v4 + v_and_b32_e32 v87, 31, v41 + v_xor_b32_e32 v44, v19, v87 + v_sub_u32_e32 v33, v44, v33 + v_lshlrev_b32_e32 v33, 2, v33 + v_mov_b32_e32 v45, 12 + v_lshlrev_b32_sdwa v40, v45, sext(v40) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v35, v35, v40, s26 + v_add3_u32 v41, v33, v35, v39 + v_lshrrev_b32_e32 v33, 5, v22 + v_sub_u32_e32 v30, v33, v30 + v_lshrrev_b16_e32 v40, 3, v22 + v_and_b32_e32 v40, 3, v40 + v_sub_u16_e32 v38, v40, v38 + v_bfe_i32 v38, v38, 0, 16 + v_lshl_or_b32 v47, v33, 4, v4 + v_and_b32_e32 v101, 31, v47 + v_xor_b32_e32 v47, v8, v101 + v_sub_u32_e32 v44, v47, v44 + v_lshlrev_b32_e32 v30, 11, v30 + v_lshlrev_b32_e32 v44, 2, v44 + v_lshl_add_u32 v30, v38, 12, v30 + v_add3_u32 v38, v44, v30, v41 + v_lshrrev_b32_e32 v44, 5, v21 + v_sub_u32_e32 v33, v44, v33 + v_lshrrev_b16_e32 v48, 3, v21 + v_and_b32_e32 v48, 3, v48 + v_sub_u16_e32 v40, v48, v40 + v_bfe_i32 v40, v40, 0, 16 + v_lshl_or_b32 v49, v44, 4, v4 + v_and_b32_e32 v102, 31, v49 + v_xor_b32_e32 v49, v19, v102 + v_sub_u32_e32 v47, v49, v47 + v_lshlrev_b32_e32 v33, 11, v33 + v_lshlrev_b32_e32 v47, 2, v47 + v_lshl_add_u32 v33, v40, 12, v33 + v_add3_u32 v40, v47, v33, v38 + v_lshrrev_b32_e32 v50, 4, v20 + v_sub_u16_e32 v47, v18, v48 + v_xor_b32_e32 v48, v50, v4 + v_sub_u32_e32 v49, v48, v49 + v_lshlrev_b32_e32 v49, 2, v49 + v_lshlrev_b32_sdwa v45, v45, sext(v47) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v44, 11, v44 + v_sub_u32_e32 v90, v45, v44 + v_add3_u32 v76, v49, v90, v40 + v_add_u32_e32 v45, 16, v50 + v_xor_b32_e32 v44, v45, v4 + v_sub_u32_e32 v47, v44, v48 + v_lshl_add_u32 v79, v47, 2, v76 + v_xor_b32_e32 v47, v50, v32 + v_sub_u32_e32 v44, v47, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v51, v44, v31, v79 + v_xor_b32_e32 v44, v45, v86 + v_sub_u32_e32 v47, v44, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_add3_u32 v52, v47, v29, v51 + v_xor_b32_e32 v48, v50, v10 + v_sub_u32_e32 v44, v48, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v47, v44, v27, v52 + v_xor_b32_e32 v44, v45, v87 + v_sub_u32_e32 v48, v44, v48 + v_lshlrev_b32_e32 v48, 2, v48 + v_add3_u32 v48, v48, v35, v47 + v_xor_b32_e32 v49, v50, v101 + v_sub_u32_e32 v44, v49, v44 + v_lshlrev_b32_e32 v44, 2, v44 + v_add3_u32 v44, v44, v30, v48 + v_xor_b32_e32 v50, v45, v102 + v_sub_u32_e32 v45, v50, v49 + v_lshlrev_b32_e32 v45, 2, v45 + v_add3_u32 v45, v45, v33, v44 + v_add_u32_e32 v49, 0x80, v7 + v_lshrrev_b32_e32 v49, 4, v49 + v_xor_b32_e32 v53, v49, v4 + v_sub_u32_e32 v50, v53, v50 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v73, v50, v90, v45 + v_add_u32_e32 v50, 16, v49 + v_xor_b32_e32 v54, v50, v4 + v_sub_u32_e32 v53, v54, v53 + v_lshl_add_u32 v77, v53, 2, v73 + v_xor_b32_e32 v53, v49, v32 + v_sub_u32_e32 v54, v53, v54 + v_lshlrev_b32_e32 v54, 2, v54 + v_add3_u32 v57, v54, v31, v77 + v_xor_b32_e32 v54, v50, v86 + v_sub_u32_e32 v53, v54, v53 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v58, v53, v29, v57 + v_xor_b32_e32 v55, v49, v10 + v_sub_u32_e32 v53, v55, v54 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v53, v53, v27, v58 + v_xor_b32_e32 v56, v50, v87 + v_sub_u32_e32 v54, v56, v55 + v_lshlrev_b32_e32 v54, 2, v54 + v_add3_u32 v54, v54, v35, v53 + v_xor_b32_e32 v55, v49, v101 + v_sub_u32_e32 v49, v55, v56 + v_lshlrev_b32_e32 v49, 2, v49 + v_add3_u32 v49, v49, v30, v54 + v_xor_b32_e32 v56, v50, v102 + v_sub_u32_e32 v50, v56, v55 + v_lshlrev_b32_e32 v50, 2, v50 + v_add3_u32 v50, v50, v33, v49 + v_add_u32_e32 v55, 0xc0, v7 + v_lshrrev_b32_e32 v55, 4, v55 + v_xor_b32_e32 v59, v55, v4 + v_sub_u32_e32 v56, v59, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v70, v56, v90, v50 + v_add_u32_e32 v56, 16, v55 + v_xor_b32_e32 v60, v56, v4 + v_sub_u32_e32 v59, v60, v59 + v_lshl_add_u32 v72, v59, 2, v70 + v_xor_b32_e32 v59, v55, v32 + v_sub_u32_e32 v60, v59, v60 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v61, v60, v31, v72 + v_xor_b32_e32 v60, v56, v86 + v_sub_u32_e32 v59, v60, v59 + v_lshlrev_b32_e32 v59, 2, v59 + v_add3_u32 v62, v59, v29, v61 + v_xor_b32_e32 v63, v55, v10 + v_sub_u32_e32 v59, v63, v60 + v_lshlrev_b32_e32 v59, 2, v59 + v_add3_u32 v59, v59, v27, v62 + v_xor_b32_e32 v64, v56, v87 + v_sub_u32_e32 v60, v64, v63 + v_lshlrev_b32_e32 v60, 2, v60 + v_add3_u32 v60, v60, v35, v59 + v_xor_b32_e32 v63, v55, v101 + v_sub_u32_e32 v55, v63, v64 + v_lshlrev_b32_e32 v55, 2, v55 + v_add3_u32 v55, v55, v30, v60 + v_xor_b32_e32 v56, v56, v102 + v_sub_u32_e32 v56, v56, v63 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v56, v56, v33, v55 + v_xor_b32_e32 v63, v17, v4 + v_sub_u32_e32 v64, v63, v3 + v_lshlrev_b32_e32 v64, 2, v64 + v_add3_u32 v94, v46, v28, v64 + v_xor_b32_e32 v28, v6, v32 + v_sub_u32_e32 v63, v28, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v69, v63, v31, v94 + v_xor_b32_e32 v63, v17, v86 + v_sub_u32_e32 v28, v63, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v71, v28, v29, v69 + v_xor_b32_e32 v28, v6, v10 + v_sub_u32_e32 v63, v28, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v65, v63, v27, v71 + v_xor_b32_e32 v63, v17, v87 + v_sub_u32_e32 v28, v63, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v66, v28, v35, v65 + v_xor_b32_e32 v28, v6, v101 + v_sub_u32_e32 v63, v28, v63 + v_lshlrev_b32_e32 v63, 2, v63 + v_add3_u32 v63, v63, v30, v66 + v_xor_b32_e32 v67, v17, v102 + v_sub_u32_e32 v28, v67, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v64, v28, v33, v63 + v_xor_b32_e32 v28, v16, v4 + v_sub_u32_e32 v67, v28, v67 + v_lshlrev_b32_e32 v67, 2, v67 + v_add3_u32 v95, v67, v90, v64 + v_xor_b32_e32 v67, v15, v4 + v_sub_u32_e32 v28, v67, v28 + v_lshl_add_u32 v96, v28, 2, v95 + v_xor_b32_e32 v28, v16, v32 + v_sub_u32_e32 v67, v28, v67 + v_lshlrev_b32_e32 v67, 2, v67 + v_add3_u32 v82, v67, v31, v96 + v_xor_b32_e32 v67, v15, v86 + v_sub_u32_e32 v28, v67, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v83, v28, v29, v82 + v_xor_b32_e32 v28, v16, v10 + v_sub_u32_e32 v67, v28, v67 + v_lshlrev_b32_e32 v67, 2, v67 + v_add3_u32 v74, v67, v27, v83 + v_xor_b32_e32 v67, v15, v87 + v_sub_u32_e32 v28, v67, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v78, v28, v35, v74 + v_xor_b32_e32 v28, v16, v101 + v_sub_u32_e32 v67, v28, v67 + v_lshlrev_b32_e32 v67, 2, v67 + v_add3_u32 v67, v67, v30, v78 + v_xor_b32_e32 v80, v15, v102 + v_sub_u32_e32 v28, v80, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v68, v28, v33, v67 + v_xor_b32_e32 v28, v14, v4 + v_sub_u32_e32 v80, v28, v80 + v_lshlrev_b32_e32 v80, 2, v80 + v_add3_u32 v97, v80, v90, v68 + v_xor_b32_e32 v80, v12, v4 + v_sub_u32_e32 v28, v80, v28 + v_lshl_add_u32 v98, v28, 2, v97 + v_xor_b32_e32 v28, v14, v32 + v_sub_u32_e32 v80, v28, v80 + v_lshlrev_b32_e32 v80, 2, v80 + v_add3_u32 v88, v80, v31, v98 + v_xor_b32_e32 v80, v12, v86 + v_sub_u32_e32 v28, v80, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v89, v28, v29, v88 + v_xor_b32_e32 v28, v14, v10 + v_sub_u32_e32 v80, v28, v80 + v_lshlrev_b32_e32 v80, 2, v80 + v_add3_u32 v84, v80, v27, v89 + v_xor_b32_e32 v80, v12, v87 + v_sub_u32_e32 v28, v80, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v85, v28, v35, v84 + v_xor_b32_e32 v28, v14, v101 + v_sub_u32_e32 v80, v28, v80 + v_lshlrev_b32_e32 v80, 2, v80 + v_add3_u32 v80, v80, v30, v85 + v_xor_b32_e32 v91, v12, v102 + v_sub_u32_e32 v28, v91, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v81, v28, v33, v80 + v_xor_b32_e32 v28, v11, v4 + v_sub_u32_e32 v91, v28, v91 + v_lshlrev_b32_e32 v91, 2, v91 + v_add3_u32 v99, v91, v90, v81 + v_xor_b32_e32 v90, v9, v4 + v_sub_u32_e32 v28, v90, v28 + v_lshl_add_u32 v100, v28, 2, v99 + v_xor_b32_e32 v28, v11, v32 + v_sub_u32_e32 v32, v28, v90 + v_lshlrev_b32_e32 v32, 2, v32 + v_add3_u32 v92, v32, v31, v100 + v_xor_b32_e32 v31, v9, v86 + v_sub_u32_e32 v28, v31, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v93, v28, v29, v92 + v_xor_b32_e32 v28, v11, v10 + v_sub_u32_e32 v29, v28, v31 + v_lshlrev_b32_e32 v29, 2, v29 + v_add3_u32 v90, v29, v27, v93 + v_xor_b32_e32 v27, v9, v87 + v_sub_u32_e32 v28, v27, v28 + v_lshlrev_b32_e32 v28, 2, v28 + v_add3_u32 v91, v28, v35, v90 + v_xor_b32_e32 v28, v11, v101 + v_sub_u32_e32 v27, v28, v27 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v86, v27, v30, v91 + v_xor_b32_e32 v27, v9, v102 + v_sub_u32_e32 v27, v27, v28 + v_lshlrev_b32_e32 v27, 2, v27 + v_add3_u32 v87, v27, v33, v86 + s_mov_b64 s[2:3], 0 + s_branch .LBB35_6 +.LBB35_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr64 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr92 + ; implicit-def: $vgpr93 + ; implicit-def: $vgpr90 + ; implicit-def: $vgpr91 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr87 +.LBB35_6: ; %Flow120 + v_lshl_add_u32 v101, v26, 2, v13 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + s_cbranch_vccnz .LBB35_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2769.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v35, v2 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s18, s6, 6 + s_lshl_b32 s2, s22, 6 + s_lshl_b32 s3, s23, 6 + v_xor_b32_e32 v2, v19, v4 + v_sub_u32_e32 v5, v18, v5 + v_lshlrev_b32_e32 v5, 12, v5 + v_lshlrev_b32_e32 v26, 2, v2 + v_add3_u32 v75, v5, v13, v26 + v_lshrrev_b32_e32 v13, 5, v25 + v_lshrrev_b16_e32 v25, 3, v25 + v_and_b32_e32 v25, 3, v25 + v_sub_u16_e32 v26, v25, v18 + v_bfe_i32 v26, v26, 0, 16 + v_lshl_or_b32 v27, v13, 4, v4 + v_xor_b32_e32 v28, v8, v27 + v_sub_u32_e32 v2, v28, v2 + v_lshlrev_b32_e32 v29, 11, v13 + v_lshlrev_b32_e32 v2, 2, v2 + v_lshl_or_b32 v26, v26, 12, v29 + v_add3_u32 v42, v2, v26, v75 + v_lshrrev_b32_e32 v2, 5, v24 + v_sub_u32_e32 v13, v2, v13 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v25, v24, v25 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v29, v2, 4, v4 + v_xor_b32_e32 v30, v19, v29 + v_sub_u32_e32 v28, v30, v28 + v_lshlrev_b32_e32 v13, 11, v13 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_add_u32 v13, v25, 12, v13 + v_add3_u32 v43, v28, v13, v42 + v_sub_u16_e32 v24, v18, v24 + v_bfe_i32 v24, v24, 0, 16 + v_xor_b32_e32 v25, v8, v10 + v_sub_u32_e32 v28, v25, v30 + v_lshlrev_b32_e32 v2, 11, v2 + v_xor_b32_e32 v2, 0x800, v2 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshl_or_b32 v2, v24, 12, v2 + v_add3_u32 v39, v28, v2, v43 + v_lshrrev_b32_e32 v24, 5, v23 + v_lshlrev_b32_e32 v28, 11, v24 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v30, v23, v18 + v_lshl_or_b32 v31, v24, 4, v4 + v_and_b32_e32 v31, 31, v31 + v_xor_b32_e32 v32, v19, v31 + v_sub_u32_e32 v25, v32, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_mov_b32_e32 v33, 12 + v_lshlrev_b32_sdwa v30, v33, sext(v30) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + s_movk_i32 s6, 0xf800 + v_add3_u32 v28, v28, v30, s6 + v_add3_u32 v41, v25, v28, v39 + v_lshrrev_b32_e32 v25, 5, v22 + v_sub_u32_e32 v24, v25, v24 + v_lshrrev_b16_e32 v22, 3, v22 + v_and_b32_e32 v22, 3, v22 + v_sub_u16_e32 v23, v22, v23 + v_bfe_i32 v23, v23, 0, 16 + v_lshl_or_b32 v30, v25, 4, v4 + v_and_b32_e32 v30, 31, v30 + v_xor_b32_e32 v8, v8, v30 + v_sub_u32_e32 v32, v8, v32 + v_lshlrev_b32_e32 v24, 11, v24 + v_lshlrev_b32_e32 v32, 2, v32 + v_lshl_add_u32 v23, v23, 12, v24 + v_add3_u32 v38, v32, v23, v41 + v_lshrrev_b32_e32 v24, 5, v21 + v_sub_u32_e32 v25, v24, v25 + v_lshrrev_b16_e32 v21, 3, v21 + v_and_b32_e32 v21, 3, v21 + v_sub_u16_e32 v22, v21, v22 + v_bfe_i32 v22, v22, 0, 16 + v_lshl_or_b32 v32, v24, 4, v4 + v_and_b32_e32 v32, 31, v32 + v_xor_b32_e32 v19, v19, v32 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v25, 11, v25 + v_lshlrev_b32_e32 v8, 2, v8 + v_lshl_add_u32 v22, v22, 12, v25 + v_add3_u32 v40, v8, v22, v38 + v_lshrrev_b32_e32 v8, 4, v20 + v_sub_u16_e32 v18, v18, v21 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_lshlrev_b32_sdwa v18, v33, sext(v18) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v21, 11, v24 + v_sub_u32_e32 v18, v18, v21 + v_add3_u32 v76, v19, v18, v40 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v79, v20, 2, v76 + v_xor_b32_e32 v20, v8, v27 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v51, v21, v26, v79 + v_xor_b32_e32 v21, v19, v29 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v52, v20, v13, v51 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v47, v21, v2, v52 + v_xor_b32_e32 v21, v19, v31 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v48, v20, v28, v47 + v_xor_b32_e32 v8, v8, v30 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v44, v20, v23, v48 + v_xor_b32_e32 v19, v19, v32 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v45, v8, v22, v44 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v8, 0x80, v7 + v_lshrrev_b32_e32 v8, 4, v8 + v_xor_b32_e32 v20, v8, v4 + v_sub_u32_e32 v19, v20, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v73, v19, v18, v45 + v_add_u32_e32 v19, 16, v8 + v_xor_b32_e32 v21, v19, v4 + v_sub_u32_e32 v20, v21, v20 + v_lshl_add_u32 v77, v20, 2, v73 + v_xor_b32_e32 v20, v8, v27 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v57, v21, v26, v77 + v_xor_b32_e32 v21, v19, v29 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v58, v20, v13, v57 + v_xor_b32_e32 v20, v8, v10 + v_sub_u32_e32 v21, v20, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v53, v21, v2, v58 + v_xor_b32_e32 v21, v19, v31 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v54, v20, v28, v53 + v_xor_b32_e32 v8, v8, v30 + v_sub_u32_e32 v20, v8, v21 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v49, v20, v23, v54 + v_xor_b32_e32 v19, v19, v32 + v_sub_u32_e32 v8, v19, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v50, v8, v22, v49 + v_add_u32_e32 v7, 0xc0, v7 + v_lshrrev_b32_e32 v7, 4, v7 + v_xor_b32_e32 v8, v7, v4 + v_sub_u32_e32 v19, v8, v19 + v_lshlrev_b32_e32 v19, 2, v19 + v_add3_u32 v70, v19, v18, v50 + v_add_u32_e32 v19, 16, v7 + v_xor_b32_e32 v20, v19, v4 + v_sub_u32_e32 v8, v20, v8 + v_lshl_add_u32 v72, v8, 2, v70 + v_xor_b32_e32 v8, v7, v27 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v61, v20, v26, v72 + v_xor_b32_e32 v20, v19, v29 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v62, v8, v13, v61 + v_xor_b32_e32 v8, v7, v10 + v_sub_u32_e32 v20, v8, v20 + v_lshlrev_b32_e32 v20, 2, v20 + v_add3_u32 v59, v20, v2, v62 + v_xor_b32_e32 v20, v19, v31 + v_sub_u32_e32 v8, v20, v8 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v60, v8, v28, v59 + v_xor_b32_e32 v7, v7, v30 + v_sub_u32_e32 v8, v7, v20 + v_lshlrev_b32_e32 v8, 2, v8 + v_add3_u32 v55, v8, v23, v60 + v_xor_b32_e32 v8, v19, v32 + v_sub_u32_e32 v7, v8, v7 + v_lshlrev_b32_e32 v7, 2, v7 + v_add3_u32 v56, v7, v22, v55 + v_xor_b32_e32 v7, v17, v4 + v_sub_u32_e32 v3, v7, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v94, v46, v5, v3 + v_xor_b32_e32 v3, v6, v27 + v_sub_u32_e32 v5, v3, v7 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v69, v5, v26, v94 + v_xor_b32_e32 v5, v17, v29 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v71, v3, v13, v69 + v_xor_b32_e32 v3, v6, v10 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v65, v5, v2, v71 + v_xor_b32_e32 v5, v17, v31 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v66, v3, v28, v65 + v_xor_b32_e32 v3, v6, v30 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v63, v5, v23, v66 + v_xor_b32_e32 v5, v17, v32 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v64, v3, v22, v63 + v_xor_b32_e32 v3, v16, v4 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v95, v5, v18, v64 + v_xor_b32_e32 v5, v15, v4 + v_sub_u32_e32 v3, v5, v3 + v_lshl_add_u32 v96, v3, 2, v95 + v_xor_b32_e32 v3, v16, v27 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v82, v5, v26, v96 + v_xor_b32_e32 v5, v15, v29 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v83, v3, v13, v82 + v_xor_b32_e32 v3, v16, v10 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v74, v5, v2, v83 + v_xor_b32_e32 v5, v15, v31 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v78, v3, v28, v74 + v_xor_b32_e32 v3, v16, v30 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v67, v5, v23, v78 + v_xor_b32_e32 v5, v15, v32 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v68, v3, v22, v67 + v_xor_b32_e32 v3, v14, v4 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v97, v5, v18, v68 + v_xor_b32_e32 v5, v12, v4 + v_sub_u32_e32 v3, v5, v3 + v_lshl_add_u32 v98, v3, 2, v97 + v_xor_b32_e32 v3, v14, v27 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v88, v5, v26, v98 + v_xor_b32_e32 v5, v12, v29 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v89, v3, v13, v88 + v_xor_b32_e32 v3, v14, v10 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v84, v5, v2, v89 + v_xor_b32_e32 v5, v12, v31 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v85, v3, v28, v84 + v_xor_b32_e32 v3, v14, v30 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v80, v5, v23, v85 + v_xor_b32_e32 v5, v12, v32 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v81, v3, v22, v80 + v_xor_b32_e32 v3, v11, v4 + v_sub_u32_e32 v5, v3, v5 + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v99, v5, v18, v81 + v_xor_b32_e32 v4, v9, v4 + v_sub_u32_e32 v3, v4, v3 + v_lshl_add_u32 v100, v3, 2, v99 + v_xor_b32_e32 v3, v11, v27 + v_sub_u32_e32 v4, v3, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v92, v4, v26, v100 + v_xor_b32_e32 v4, v9, v29 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v93, v3, v13, v92 + v_xor_b32_e32 v3, v11, v10 + v_sub_u32_e32 v4, v3, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v90, v4, v2, v93 + v_xor_b32_e32 v2, v9, v31 + v_sub_u32_e32 v3, v2, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v91, v3, v28, v90 + v_xor_b32_e32 v3, v11, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v86, v2, v23, v91 + v_xor_b32_e32 v2, v9, v32 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v87, v2, v22, v86 + s_add_i32 s18, s18, 1 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + s_mov_b32 s19, 0x3020504 + s_mov_b32 s23, 0x5010400 + s_mov_b32 s24, 0x5040100 + s_mov_b32 s25, 0x7060302 + s_mov_b32 s26, 0x7030602 +.LBB35_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i2769.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v35, s2, v35 + v_add_u32_e32 v34, s3, v34 + buffer_load_dwordx4 v[26:29], v34, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v34 + buffer_load_dwordx4 v[18:21], v35, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v35 + v_add_u32_e32 v4, s7, v2 + buffer_load_dwordx4 v[22:25], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[30:33], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v4, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v4 + buffer_load_dwordx4 v[10:13], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[6:9], v2, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v124, v76 + ds_read_b32 v112, v101 + ds_read_b32 v113, v75 + ds_read_b32 v136, v42 + ds_read_b32 v137, v43 + ds_read_b32 v122, v39 + ds_read_b32 v123, v41 + ds_read_b32 v110, v38 + ds_read_b32 v148, v46 offset:16384 + ds_read_b32 v149, v94 offset:16384 + ds_read_b32 v128, v69 offset:16384 + ds_read_b32 v129, v71 offset:16384 + ds_read_b32 v114, v65 offset:16384 + ds_read_b32 v115, v66 offset:16384 + ds_read_b32 v102, v63 offset:16384 + ds_read_b32 v103, v64 offset:16384 + ds_read_b32 v146, v95 offset:16384 + ds_read_b32 v147, v96 offset:16384 + ds_read_b32 v130, v82 offset:16384 + s_waitcnt lgkmcnt(9) + v_mfma_i32_32x32x16_i8 a[0:15], v[112:113], v[148:149], a[0:15] + ds_read_b32 v131, v83 offset:16384 + ds_read_b32 v116, v74 offset:16384 + ds_read_b32 v117, v78 offset:16384 + ds_read_b32 v104, v67 offset:16384 + ds_read_b32 v105, v68 offset:16384 + ds_read_b32 v144, v97 offset:16384 + ds_read_b32 v145, v98 offset:16384 + s_waitcnt lgkmcnt(8) + v_mfma_i32_32x32x16_i8 a[16:31], v[112:113], v[146:147], a[16:31] + ds_read_b32 v132, v88 offset:16384 + ds_read_b32 v133, v89 offset:16384 + ds_read_b32 v118, v84 offset:16384 + ds_read_b32 v119, v85 offset:16384 + ds_read_b32 v106, v80 offset:16384 + ds_read_b32 v107, v81 offset:16384 + ds_read_b32 v142, v99 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_i32_32x32x16_i8 a[32:47], v[112:113], v[144:145], a[32:47] + ds_read_b32 v143, v100 offset:16384 + ds_read_b32 v134, v92 offset:16384 + ds_read_b32 v135, v93 offset:16384 + ds_read_b32 v120, v90 offset:16384 + ds_read_b32 v121, v91 offset:16384 + ds_read_b32 v108, v86 offset:16384 + ds_read_b32 v109, v87 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_i32_32x32x16_i8 a[48:63], v[112:113], v[142:143], a[48:63] + ds_read_b32 v125, v79 + ds_read_b32 v138, v51 + ds_read_b32 v139, v52 + ds_read_b32 v126, v47 + ds_read_b32 v127, v48 + ds_read_b32 v112, v44 + s_waitcnt lgkmcnt(5) + v_mfma_i32_32x32x16_i8 a[64:79], v[124:125], v[148:149], a[64:79] + v_mfma_i32_32x32x16_i8 a[144:159], v[124:125], v[146:147], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[124:125], v[144:145], a[160:175] + ds_read_b32 v140, v73 + v_mfma_i32_32x32x16_i8 a[176:191], v[124:125], v[142:143], a[176:191] + ds_read_b32 v141, v77 + ds_read_b32 v150, v57 + ds_read_b32 v151, v58 + ds_read_b32 v152, v53 + ds_read_b32 v153, v54 + ds_read_b32 v124, v49 + s_waitcnt lgkmcnt(5) + v_mfma_i32_32x32x16_i8 a[192:207], v[140:141], v[148:149], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[140:141], v[146:147], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[140:141], v[144:145], a[224:239] + ds_read_b32 v154, v70 + v_mfma_i32_32x32x16_i8 a[240:255], v[140:141], v[142:143], a[240:255] + ds_read_b32 v155, v72 + ds_read_b32 v156, v61 + ds_read_b32 v157, v62 + ds_read_b32 v158, v59 + ds_read_b32 v159, v60 + ds_read_b32 v140, v55 + s_waitcnt lgkmcnt(5) + v_mfma_i32_32x32x16_i8 a[128:143], v[154:155], v[148:149], a[128:143] + v_mfma_i32_32x32x16_i8 a[112:127], v[154:155], v[146:147], a[112:127] + v_mfma_i32_32x32x16_i8 a[96:111], v[154:155], v[144:145], a[96:111] + v_mfma_i32_32x32x16_i8 a[80:95], v[154:155], v[142:143], a[80:95] + v_mfma_i32_32x32x16_i8 a[0:15], v[136:137], v[128:129], a[0:15] + v_mfma_i32_32x32x16_i8 a[16:31], v[136:137], v[130:131], a[16:31] + v_mfma_i32_32x32x16_i8 a[32:47], v[136:137], v[132:133], a[32:47] + v_mfma_i32_32x32x16_i8 a[48:63], v[136:137], v[134:135], a[48:63] + v_mfma_i32_32x32x16_i8 a[64:79], v[138:139], v[128:129], a[64:79] + v_mfma_i32_32x32x16_i8 a[144:159], v[138:139], v[130:131], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[138:139], v[132:133], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[138:139], v[134:135], a[176:191] + v_mfma_i32_32x32x16_i8 a[192:207], v[150:151], v[128:129], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[150:151], v[130:131], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[150:151], v[132:133], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[150:151], v[134:135], a[240:255] + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[128:143], v[156:157], v[128:129], a[128:143] + v_mfma_i32_32x32x16_i8 a[112:127], v[156:157], v[130:131], a[112:127] + v_mfma_i32_32x32x16_i8 a[96:111], v[156:157], v[132:133], a[96:111] + v_mfma_i32_32x32x16_i8 a[80:95], v[156:157], v[134:135], a[80:95] + v_mfma_i32_32x32x16_i8 a[0:15], v[122:123], v[114:115], a[0:15] + v_mfma_i32_32x32x16_i8 a[16:31], v[122:123], v[116:117], a[16:31] + v_mfma_i32_32x32x16_i8 a[32:47], v[122:123], v[118:119], a[32:47] + v_mfma_i32_32x32x16_i8 a[48:63], v[122:123], v[120:121], a[48:63] + v_mfma_i32_32x32x16_i8 a[64:79], v[126:127], v[114:115], a[64:79] + v_mfma_i32_32x32x16_i8 a[144:159], v[126:127], v[116:117], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[126:127], v[118:119], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[126:127], v[120:121], a[176:191] + v_mfma_i32_32x32x16_i8 a[192:207], v[152:153], v[114:115], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[152:153], v[116:117], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[152:153], v[118:119], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[152:153], v[120:121], a[240:255] + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[128:143], v[158:159], v[114:115], a[128:143] + v_mfma_i32_32x32x16_i8 a[112:127], v[158:159], v[116:117], a[112:127] + v_mfma_i32_32x32x16_i8 a[96:111], v[158:159], v[118:119], a[96:111] + v_mfma_i32_32x32x16_i8 a[80:95], v[158:159], v[120:121], a[80:95] + ds_read_b32 v111, v40 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[110:111], v[102:103], a[0:15] + v_mfma_i32_32x32x16_i8 a[16:31], v[110:111], v[104:105], a[16:31] + v_readfirstlane_b32 s27, v0 + s_add_i32 s18, s18, -1 + s_lshr_b32 s27, s27, 2 + v_mfma_i32_32x32x16_i8 a[32:47], v[110:111], v[106:107], a[32:47] + s_and_b32 s27, s27, 0x3ffffff0 + v_add_u32_e32 v114, s27, v1 + s_cmp_gt_u32 s18, 2 + ds_read_b32 v113, v45 + ds_read_b32 v125, v50 + ds_read_b32 v141, v56 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[110:111], v[108:109], a[48:63] + s_barrier + v_lshrrev_b32_e32 v110, 1, v114 + v_lshlrev_b32_e32 v111, 9, v114 + v_lshlrev_b32_e32 v114, 6, v114 + v_and_b32_e32 v110, 16, v110 + v_and_b32_e32 v111, 0x3000, v111 + v_and_b32_e32 v114, 0xfffff800, v114 + v_mfma_i32_32x32x16_i8 a[64:79], v[112:113], v[102:103], a[64:79] + v_xor_b32_e32 v115, v110, v37 + v_add_u32_e32 v111, v111, v114 + v_or_b32_e32 v114, 1, v110 + v_or_b32_e32 v116, 2, v110 + v_or_b32_e32 v117, 3, v110 + v_or_b32_e32 v118, 4, v110 + v_or_b32_e32 v119, 5, v110 + v_mfma_i32_32x32x16_i8 a[144:159], v[112:113], v[104:105], a[144:159] + v_or_b32_e32 v120, 6, v110 + v_or_b32_e32 v121, 7, v110 + v_or_b32_e32 v122, 8, v110 + v_or_b32_e32 v123, 9, v110 + v_or_b32_e32 v126, 10, v110 + v_or_b32_e32 v127, 11, v110 + v_or_b32_e32 v128, 12, v110 + v_mfma_i32_32x32x16_i8 a[160:175], v[112:113], v[106:107], a[160:175] + v_or_b32_e32 v129, 13, v110 + v_or_b32_e32 v130, 14, v110 + v_or_b32_e32 v110, 15, v110 + v_lshl_or_b32 v111, v115, 2, v111 + v_xor_b32_e32 v114, v114, v37 + v_xor_b32_e32 v116, v116, v37 + v_xor_b32_e32 v117, v117, v37 + v_mfma_i32_32x32x16_i8 a[176:191], v[112:113], v[108:109], a[176:191] + v_xor_b32_e32 v112, v118, v37 + v_xor_b32_e32 v113, v119, v37 + v_xor_b32_e32 v118, v120, v37 + v_xor_b32_e32 v119, v121, v37 + v_xor_b32_e32 v120, v122, v37 + v_xor_b32_e32 v121, v123, v37 + v_xor_b32_e32 v122, v126, v37 + v_mfma_i32_32x32x16_i8 a[192:207], v[124:125], v[102:103], a[192:207] + v_xor_b32_e32 v123, v127, v37 + v_xor_b32_e32 v126, v128, v37 + v_xor_b32_e32 v127, v129, v37 + v_xor_b32_e32 v128, v130, v37 + v_xor_b32_e32 v110, v110, v37 + v_sub_u32_e32 v115, v114, v115 + v_sub_u32_e32 v114, v116, v114 + v_mfma_i32_32x32x16_i8 a[208:223], v[124:125], v[104:105], a[208:223] + v_sub_u32_e32 v116, v117, v116 + v_sub_u32_e32 v117, v112, v117 + v_sub_u32_e32 v112, v113, v112 + v_sub_u32_e32 v113, v118, v113 + v_sub_u32_e32 v118, v119, v118 + v_sub_u32_e32 v119, v120, v119 + v_sub_u32_e32 v120, v121, v120 + v_mfma_i32_32x32x16_i8 a[224:239], v[124:125], v[106:107], a[224:239] + v_sub_u32_e32 v121, v122, v121 + v_sub_u32_e32 v122, v123, v122 + v_sub_u32_e32 v123, v126, v123 + v_sub_u32_e32 v126, v127, v126 + v_sub_u32_e32 v127, v128, v127 + v_sub_u32_e32 v110, v110, v128 + v_lshl_add_u32 v115, v115, 2, v111 + v_mfma_i32_32x32x16_i8 a[240:255], v[124:125], v[108:109], a[240:255] + v_lshlrev_b32_e32 v114, 2, v114 + v_lshlrev_b32_e32 v116, 2, v116 + v_lshlrev_b32_e32 v117, 2, v117 + v_lshlrev_b32_e32 v112, 2, v112 + v_lshlrev_b32_e32 v113, 2, v113 + v_lshlrev_b32_e32 v118, 2, v118 + v_lshlrev_b32_e32 v119, 2, v119 + v_mfma_i32_32x32x16_i8 a[128:143], v[140:141], v[102:103], a[128:143] + v_lshlrev_b32_e32 v102, 2, v120 + v_lshlrev_b32_e32 v103, 2, v121 + v_lshlrev_b32_e32 v120, 2, v122 + v_lshlrev_b32_e32 v121, 2, v123 + v_lshlrev_b32_e32 v122, 2, v126 + v_lshlrev_b32_e32 v123, 2, v127 + v_lshlrev_b32_e32 v110, 2, v110 + v_mfma_i32_32x32x16_i8 a[112:127], v[140:141], v[104:105], a[112:127] + v_add3_u32 v104, v115, s6, v114 + v_add3_u32 v105, v104, s6, v116 + v_add3_u32 v114, v105, s6, v117 + v_add3_u32 v112, v114, s6, v112 + v_add3_u32 v113, v112, s6, v113 + v_add3_u32 v116, v113, s6, v118 + v_add3_u32 v117, v116, s6, v119 + v_mfma_i32_32x32x16_i8 a[96:111], v[140:141], v[106:107], a[96:111] + v_add3_u32 v102, v117, s6, v102 + v_add3_u32 v103, v102, s6, v103 + v_add3_u32 v106, v103, s6, v120 + v_add3_u32 v107, v106, s6, v121 + v_add3_u32 v118, v107, s6, v122 + v_add3_u32 v119, v118, s6, v123 + v_add3_u32 v110, v119, s6, v110 + v_mfma_i32_32x32x16_i8 a[80:95], v[140:141], v[108:109], a[80:95] + s_waitcnt vmcnt(7) + v_perm_b32 v26, v26, v26, s19 + v_perm_b32 v27, v27, v27, s19 + v_perm_b32 v28, v28, v28, s19 + v_perm_b32 v29, v29, v29, s19 + s_waitcnt vmcnt(6) + v_perm_b32 v18, v18, v18, s19 + v_perm_b32 v19, v19, v19, s19 + v_perm_b32 v20, v20, v20, s19 + v_perm_b32 v21, v21, v21, s19 + s_waitcnt vmcnt(4) + v_perm_b32 v30, v30, v30, s19 + v_perm_b32 v31, v31, v31, s19 + v_perm_b32 v32, v32, v32, s19 + v_perm_b32 v33, v33, v33, s19 + v_perm_b32 v22, v22, v22, s19 + v_perm_b32 v23, v23, v23, s19 + v_perm_b32 v24, v24, v24, s19 + v_perm_b32 v25, v25, v25, s19 + s_waitcnt vmcnt(3) + v_perm_b32 v14, v14, v14, s19 + v_perm_b32 v15, v15, v15, s19 + v_perm_b32 v16, v16, v16, s19 + v_perm_b32 v17, v17, v17, s19 + v_perm_b32 v108, v30, v26, s23 + v_perm_b32 v26, v30, v26, s26 + v_perm_b32 v30, v31, v27, s23 + v_perm_b32 v27, v31, v27, s26 + v_perm_b32 v31, v32, v28, s23 + v_perm_b32 v28, v32, v28, s26 + v_perm_b32 v32, v33, v29, s23 + v_perm_b32 v29, v33, v29, s26 + s_waitcnt vmcnt(2) + v_perm_b32 v10, v10, v10, s19 + v_perm_b32 v11, v11, v11, s19 + v_perm_b32 v12, v12, v12, s19 + v_perm_b32 v13, v13, v13, s19 + v_perm_b32 v33, v22, v18, s23 + v_perm_b32 v18, v22, v18, s26 + v_perm_b32 v22, v23, v19, s23 + v_perm_b32 v19, v23, v19, s26 + v_perm_b32 v23, v24, v20, s23 + v_perm_b32 v20, v24, v20, s26 + v_perm_b32 v24, v25, v21, s23 + v_perm_b32 v21, v25, v21, s26 + s_waitcnt vmcnt(1) + v_perm_b32 v6, v6, v6, s19 + v_perm_b32 v7, v7, v7, s19 + v_perm_b32 v8, v8, v8, s19 + v_perm_b32 v9, v9, v9, s19 + s_waitcnt vmcnt(0) + v_perm_b32 v2, v2, v2, s19 + v_perm_b32 v3, v3, v3, s19 + v_perm_b32 v4, v4, v4, s19 + v_perm_b32 v5, v5, v5, s19 + v_perm_b32 v25, v6, v14, s23 + v_perm_b32 v6, v6, v14, s26 + v_perm_b32 v14, v7, v15, s23 + v_perm_b32 v7, v7, v15, s26 + v_perm_b32 v15, v8, v16, s23 + v_perm_b32 v8, v8, v16, s26 + v_perm_b32 v16, v9, v17, s23 + v_perm_b32 v9, v9, v17, s26 + v_perm_b32 v17, v2, v10, s23 + v_perm_b32 v2, v2, v10, s26 + v_perm_b32 v10, v3, v11, s23 + v_perm_b32 v3, v3, v11, s26 + v_perm_b32 v11, v4, v12, s23 + v_perm_b32 v4, v4, v12, s26 + v_perm_b32 v12, v5, v13, s23 + v_perm_b32 v5, v5, v13, s26 + v_perm_b32 v13, v25, v108, s24 + v_perm_b32 v25, v25, v108, s25 + v_perm_b32 v108, v6, v26, s24 + v_perm_b32 v6, v6, v26, s25 + v_perm_b32 v26, v14, v30, s24 + v_perm_b32 v14, v14, v30, s25 + v_perm_b32 v30, v7, v27, s24 + v_perm_b32 v7, v7, v27, s25 + v_perm_b32 v27, v15, v31, s24 + v_perm_b32 v15, v15, v31, s25 + v_perm_b32 v31, v8, v28, s24 + v_perm_b32 v8, v8, v28, s25 + v_perm_b32 v28, v16, v32, s24 + v_perm_b32 v16, v16, v32, s25 + v_perm_b32 v32, v9, v29, s24 + v_perm_b32 v9, v9, v29, s25 + v_perm_b32 v29, v17, v33, s24 + v_perm_b32 v17, v17, v33, s25 + v_perm_b32 v33, v2, v18, s24 + v_perm_b32 v2, v2, v18, s25 + v_perm_b32 v18, v10, v22, s24 + v_perm_b32 v10, v10, v22, s25 + v_perm_b32 v22, v3, v19, s24 + v_perm_b32 v3, v3, v19, s25 + v_perm_b32 v19, v11, v23, s24 + v_perm_b32 v11, v11, v23, s25 + v_perm_b32 v23, v4, v20, s24 + v_perm_b32 v4, v4, v20, s25 + v_perm_b32 v20, v12, v24, s24 + v_perm_b32 v12, v12, v24, s25 + v_perm_b32 v24, v5, v21, s24 + v_perm_b32 v5, v5, v21, s25 + ds_write_b32 v111, v13 + ds_write_b32 v115, v25 offset:128 + ds_write_b32 v104, v108 offset:128 + ds_write_b32 v105, v6 offset:128 + ds_write_b32 v114, v26 offset:128 + ds_write_b32 v112, v14 offset:128 + ds_write_b32 v113, v30 offset:128 + ds_write_b32 v116, v7 offset:128 + ds_write_b32 v117, v27 offset:128 + ds_write_b32 v102, v15 offset:128 + ds_write_b32 v103, v31 offset:128 + ds_write_b32 v106, v8 offset:128 + ds_write_b32 v107, v28 offset:128 + ds_write_b32 v118, v16 offset:128 + ds_write_b32 v119, v32 offset:128 + ds_write_b32 v110, v9 offset:128 + ds_write_b32 v111, v29 offset:16384 + ds_write_b32 v115, v17 offset:16512 + ds_write_b32 v104, v33 offset:16512 + ds_write_b32 v105, v2 offset:16512 + ds_write_b32 v114, v18 offset:16512 + ds_write_b32 v112, v10 offset:16512 + ds_write_b32 v113, v22 offset:16512 + ds_write_b32 v116, v3 offset:16512 + ds_write_b32 v117, v19 offset:16512 + ds_write_b32 v102, v11 offset:16512 + ds_write_b32 v103, v23 offset:16512 + ds_write_b32 v106, v4 offset:16512 + ds_write_b32 v107, v20 offset:16512 + ds_write_b32 v118, v12 offset:16512 + ds_write_b32 v119, v24 offset:16512 + ds_write_b32 v110, v5 offset:16512 + s_cbranch_scc1 .LBB35_8 +.LBB35_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RKT2_iPvENKUlS1L + v_accvgpr_read_b32 v166, a0 + v_accvgpr_read_b32 v167, a1 + v_accvgpr_read_b32 v168, a2 + v_accvgpr_read_b32 v169, a3 + v_accvgpr_read_b32 v170, a4 + v_accvgpr_read_b32 v171, a5 + v_accvgpr_read_b32 v172, a6 + v_accvgpr_read_b32 v173, a7 + v_accvgpr_read_b32 v174, a8 + v_accvgpr_read_b32 v175, a9 + v_accvgpr_read_b32 v176, a10 + v_accvgpr_read_b32 v177, a11 + v_accvgpr_read_b32 v178, a12 + v_accvgpr_read_b32 v179, a13 + v_accvgpr_read_b32 v180, a14 + v_accvgpr_read_b32 v181, a15 + v_accvgpr_read_b32 v150, a16 + v_accvgpr_read_b32 v151, a17 + v_accvgpr_read_b32 v152, a18 + v_accvgpr_read_b32 v153, a19 + v_accvgpr_read_b32 v154, a20 + v_accvgpr_read_b32 v155, a21 + v_accvgpr_read_b32 v156, a22 + v_accvgpr_read_b32 v157, a23 + v_accvgpr_read_b32 v158, a24 + v_accvgpr_read_b32 v159, a25 + v_accvgpr_read_b32 v160, a26 + v_accvgpr_read_b32 v161, a27 + v_accvgpr_read_b32 v162, a28 + v_accvgpr_read_b32 v163, a29 + v_accvgpr_read_b32 v164, a30 + v_accvgpr_read_b32 v165, a31 + v_accvgpr_read_b32 v134, a32 + v_accvgpr_read_b32 v135, a33 + v_accvgpr_read_b32 v136, a34 + v_accvgpr_read_b32 v137, a35 + v_accvgpr_read_b32 v138, a36 + v_accvgpr_read_b32 v139, a37 + v_accvgpr_read_b32 v140, a38 + v_accvgpr_read_b32 v141, a39 + v_accvgpr_read_b32 v142, a40 + v_accvgpr_read_b32 v143, a41 + v_accvgpr_read_b32 v144, a42 + v_accvgpr_read_b32 v145, a43 + v_accvgpr_read_b32 v146, a44 + v_accvgpr_read_b32 v147, a45 + v_accvgpr_read_b32 v148, a46 + v_accvgpr_read_b32 v149, a47 + v_accvgpr_mov_b32 a0, a48 + v_accvgpr_mov_b32 a1, a49 + v_accvgpr_mov_b32 a2, a50 + v_accvgpr_mov_b32 a3, a51 + v_accvgpr_mov_b32 a4, a52 + v_accvgpr_mov_b32 a5, a53 + v_accvgpr_mov_b32 a6, a54 + v_accvgpr_mov_b32 a7, a55 + v_accvgpr_mov_b32 a8, a56 + v_accvgpr_mov_b32 a9, a57 + v_accvgpr_mov_b32 a10, a58 + v_accvgpr_mov_b32 a11, a59 + v_accvgpr_mov_b32 a12, a60 + v_accvgpr_mov_b32 a13, a61 + v_accvgpr_mov_b32 a14, a62 + v_accvgpr_mov_b32 a15, a63 + v_accvgpr_read_b32 v118, a64 + v_accvgpr_read_b32 v119, a65 + v_accvgpr_read_b32 v120, a66 + v_accvgpr_read_b32 v121, a67 + v_accvgpr_read_b32 v122, a68 + v_accvgpr_read_b32 v123, a69 + v_accvgpr_read_b32 v124, a70 + v_accvgpr_read_b32 v125, a71 + v_accvgpr_read_b32 v126, a72 + v_accvgpr_read_b32 v127, a73 + v_accvgpr_read_b32 v128, a74 + v_accvgpr_read_b32 v129, a75 + v_accvgpr_read_b32 v130, a76 + v_accvgpr_read_b32 v131, a77 + v_accvgpr_read_b32 v132, a78 + v_accvgpr_read_b32 v133, a79 + v_accvgpr_read_b32 v102, a144 + v_accvgpr_read_b32 v103, a145 + v_accvgpr_read_b32 v104, a146 + v_accvgpr_read_b32 v105, a147 + v_accvgpr_read_b32 v106, a148 + v_accvgpr_read_b32 v107, a149 + v_accvgpr_read_b32 v108, a150 + v_accvgpr_read_b32 v109, a151 + v_accvgpr_read_b32 v110, a152 + v_accvgpr_read_b32 v111, a153 + v_accvgpr_read_b32 v112, a154 + v_accvgpr_read_b32 v113, a155 + v_accvgpr_read_b32 v114, a156 + v_accvgpr_read_b32 v115, a157 + v_accvgpr_read_b32 v116, a158 + v_accvgpr_read_b32 v117, a159 + v_accvgpr_mov_b32 a64, a160 + v_accvgpr_mov_b32 a65, a161 + v_accvgpr_mov_b32 a66, a162 + v_accvgpr_mov_b32 a67, a163 + v_accvgpr_mov_b32 a68, a164 + v_accvgpr_mov_b32 a69, a165 + v_accvgpr_mov_b32 a70, a166 + v_accvgpr_mov_b32 a71, a167 + v_accvgpr_mov_b32 a72, a168 + v_accvgpr_mov_b32 a73, a169 + v_accvgpr_mov_b32 a74, a170 + v_accvgpr_mov_b32 a75, a171 + v_accvgpr_mov_b32 a76, a172 + v_accvgpr_mov_b32 a77, a173 + v_accvgpr_mov_b32 a78, a174 + v_accvgpr_mov_b32 a79, a175 + v_accvgpr_mov_b32 a16, a176 + v_accvgpr_mov_b32 a17, a177 + v_accvgpr_mov_b32 a18, a178 + v_accvgpr_mov_b32 a19, a179 + v_accvgpr_mov_b32 a20, a180 + v_accvgpr_mov_b32 a21, a181 + v_accvgpr_mov_b32 a22, a182 + v_accvgpr_mov_b32 a23, a183 + v_accvgpr_mov_b32 a24, a184 + v_accvgpr_mov_b32 a25, a185 + v_accvgpr_mov_b32 a26, a186 + v_accvgpr_mov_b32 a27, a187 + v_accvgpr_mov_b32 a28, a188 + v_accvgpr_mov_b32 a29, a189 + v_accvgpr_mov_b32 a30, a190 + v_accvgpr_mov_b32 a31, a191 + v_accvgpr_read_b32 v18, a192 + v_accvgpr_read_b32 v19, a193 + v_accvgpr_read_b32 v20, a194 + v_accvgpr_read_b32 v21, a195 + v_accvgpr_read_b32 v22, a196 + v_accvgpr_read_b32 v23, a197 + v_accvgpr_read_b32 v24, a198 + v_accvgpr_read_b32 v25, a199 + v_accvgpr_read_b32 v26, a200 + v_accvgpr_read_b32 v27, a201 + v_accvgpr_read_b32 v28, a202 + v_accvgpr_read_b32 v29, a203 + v_accvgpr_read_b32 v30, a204 + v_accvgpr_read_b32 v31, a205 + v_accvgpr_read_b32 v32, a206 + v_accvgpr_read_b32 v33, a207 + v_accvgpr_mov_b32 a144, a208 + v_accvgpr_mov_b32 a145, a209 + v_accvgpr_mov_b32 a146, a210 + v_accvgpr_mov_b32 a147, a211 + v_accvgpr_mov_b32 a148, a212 + v_accvgpr_mov_b32 a149, a213 + v_accvgpr_mov_b32 a150, a214 + v_accvgpr_mov_b32 a151, a215 + v_accvgpr_mov_b32 a152, a216 + v_accvgpr_mov_b32 a153, a217 + v_accvgpr_mov_b32 a154, a218 + v_accvgpr_mov_b32 a155, a219 + v_accvgpr_mov_b32 a156, a220 + v_accvgpr_mov_b32 a157, a221 + v_accvgpr_mov_b32 a158, a222 + v_accvgpr_mov_b32 a159, a223 + v_accvgpr_read_b32 v2, a224 + v_accvgpr_read_b32 v3, a225 + v_accvgpr_read_b32 v4, a226 + v_accvgpr_read_b32 v5, a227 + v_accvgpr_read_b32 v6, a228 + v_accvgpr_read_b32 v7, a229 + v_accvgpr_read_b32 v8, a230 + v_accvgpr_read_b32 v9, a231 + v_accvgpr_read_b32 v10, a232 + v_accvgpr_read_b32 v11, a233 + v_accvgpr_read_b32 v12, a234 + v_accvgpr_read_b32 v13, a235 + v_accvgpr_read_b32 v14, a236 + v_accvgpr_read_b32 v15, a237 + v_accvgpr_read_b32 v16, a238 + v_accvgpr_read_b32 v17, a239 + v_accvgpr_mov_b32 a32, a240 + v_accvgpr_mov_b32 a33, a241 + v_accvgpr_mov_b32 a34, a242 + v_accvgpr_mov_b32 a35, a243 + v_accvgpr_mov_b32 a36, a244 + v_accvgpr_mov_b32 a37, a245 + v_accvgpr_mov_b32 a38, a246 + v_accvgpr_mov_b32 a39, a247 + v_accvgpr_mov_b32 a40, a248 + v_accvgpr_mov_b32 a41, a249 + v_accvgpr_mov_b32 a42, a250 + v_accvgpr_mov_b32 a43, a251 + v_accvgpr_mov_b32 a44, a252 + v_accvgpr_mov_b32 a45, a253 + v_accvgpr_mov_b32 a46, a254 + v_accvgpr_mov_b32 a47, a255 + v_accvgpr_mov_b32 a224, a128 + v_accvgpr_mov_b32 a225, a129 + v_accvgpr_mov_b32 a226, a130 + v_accvgpr_mov_b32 a227, a131 + v_accvgpr_mov_b32 a228, a132 + v_accvgpr_mov_b32 a229, a133 + v_accvgpr_mov_b32 a230, a134 + v_accvgpr_mov_b32 a231, a135 + v_accvgpr_mov_b32 a232, a136 + v_accvgpr_mov_b32 a233, a137 + v_accvgpr_mov_b32 a234, a138 + v_accvgpr_mov_b32 a235, a139 + v_accvgpr_mov_b32 a236, a140 + v_accvgpr_mov_b32 a237, a141 + v_accvgpr_mov_b32 a238, a142 + v_accvgpr_mov_b32 a239, a143 + v_accvgpr_mov_b32 a176, a112 + v_accvgpr_mov_b32 a177, a113 + v_accvgpr_mov_b32 a178, a114 + v_accvgpr_mov_b32 a179, a115 + v_accvgpr_mov_b32 a180, a116 + v_accvgpr_mov_b32 a181, a117 + v_accvgpr_mov_b32 a182, a118 + v_accvgpr_mov_b32 a183, a119 + v_accvgpr_mov_b32 a184, a120 + v_accvgpr_mov_b32 a185, a121 + v_accvgpr_mov_b32 a186, a122 + v_accvgpr_mov_b32 a187, a123 + v_accvgpr_mov_b32 a188, a124 + v_accvgpr_mov_b32 a189, a125 + v_accvgpr_mov_b32 a190, a126 + v_accvgpr_mov_b32 a191, a127 + v_accvgpr_mov_b32 a112, a96 + v_accvgpr_mov_b32 a113, a97 + v_accvgpr_mov_b32 a114, a98 + v_accvgpr_mov_b32 a115, a99 + v_accvgpr_mov_b32 a116, a100 + v_accvgpr_mov_b32 a117, a101 + v_accvgpr_mov_b32 a118, a102 + v_accvgpr_mov_b32 a119, a103 + v_accvgpr_mov_b32 a120, a104 + v_accvgpr_mov_b32 a121, a105 + v_accvgpr_mov_b32 a122, a106 + v_accvgpr_mov_b32 a123, a107 + v_accvgpr_mov_b32 a124, a108 + v_accvgpr_mov_b32 a125, a109 + v_accvgpr_mov_b32 a126, a110 + v_accvgpr_mov_b32 a127, a111 + v_accvgpr_mov_b32 a240, a80 + v_accvgpr_mov_b32 a241, a81 + v_accvgpr_mov_b32 a242, a82 + v_accvgpr_mov_b32 a243, a83 + v_accvgpr_mov_b32 a244, a84 + v_accvgpr_mov_b32 a245, a85 + v_accvgpr_mov_b32 a246, a86 + v_accvgpr_mov_b32 a247, a87 + v_accvgpr_mov_b32 a248, a88 + v_accvgpr_mov_b32 a249, a89 + v_accvgpr_mov_b32 a250, a90 + v_accvgpr_mov_b32 a251, a91 + v_accvgpr_mov_b32 a252, a92 + v_accvgpr_mov_b32 a253, a93 + v_accvgpr_mov_b32 a254, a94 + v_accvgpr_mov_b32 a255, a95 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v34, v101 + ds_read_b32 v35, v75 + ds_read_b32 v182, v46 offset:16384 + ds_read_b32 v183, v94 offset:16384 + v_accvgpr_write_b32 a160, v166 + v_accvgpr_write_b32 a161, v167 + v_accvgpr_write_b32 a162, v168 + v_accvgpr_write_b32 a163, v169 + v_accvgpr_write_b32 a164, v170 + v_accvgpr_write_b32 a165, v171 + v_accvgpr_write_b32 a166, v172 + v_accvgpr_write_b32 a167, v173 + v_accvgpr_write_b32 a168, v174 + v_accvgpr_write_b32 a169, v175 + v_accvgpr_write_b32 a170, v176 + v_accvgpr_write_b32 a171, v177 + v_accvgpr_write_b32 a172, v178 + v_accvgpr_write_b32 a173, v179 + v_accvgpr_write_b32 a174, v180 + v_accvgpr_write_b32 a175, v181 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[160:175], v[34:35], v[182:183], a[160:175] + ds_read_b32 v94, v95 offset:16384 + ds_read_b32 v95, v96 offset:16384 + v_accvgpr_write_b32 a96, v150 + v_accvgpr_write_b32 a97, v151 + v_accvgpr_write_b32 a98, v152 + v_accvgpr_write_b32 a99, v153 + v_accvgpr_write_b32 a100, v154 + v_accvgpr_write_b32 a101, v155 + v_accvgpr_write_b32 a102, v156 + v_accvgpr_write_b32 a103, v157 + v_accvgpr_write_b32 a104, v158 + v_accvgpr_write_b32 a105, v159 + v_accvgpr_write_b32 a106, v160 + v_accvgpr_write_b32 a107, v161 + v_accvgpr_write_b32 a108, v162 + v_accvgpr_write_b32 a109, v163 + v_accvgpr_write_b32 a110, v164 + v_accvgpr_write_b32 a111, v165 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[96:111], v[34:35], v[94:95], a[96:111] + ds_read_b32 v96, v97 offset:16384 + ds_read_b32 v97, v98 offset:16384 + v_accvgpr_write_b32 a48, v134 + v_accvgpr_write_b32 a49, v135 + v_accvgpr_write_b32 a50, v136 + v_accvgpr_write_b32 a51, v137 + v_accvgpr_write_b32 a52, v138 + v_accvgpr_write_b32 a53, v139 + v_accvgpr_write_b32 a54, v140 + v_accvgpr_write_b32 a55, v141 + v_accvgpr_write_b32 a56, v142 + v_accvgpr_write_b32 a57, v143 + v_accvgpr_write_b32 a58, v144 + v_accvgpr_write_b32 a59, v145 + v_accvgpr_write_b32 a60, v146 + v_accvgpr_write_b32 a61, v147 + v_accvgpr_write_b32 a62, v148 + v_accvgpr_write_b32 a63, v149 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[48:63], v[34:35], v[96:97], a[48:63] + ds_read_b32 v98, v99 offset:16384 + ds_read_b32 v99, v100 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[34:35], v[98:99], a[0:15] + ds_read_b32 v34, v76 + ds_read_b32 v35, v79 + v_accvgpr_write_b32 a207, v133 + v_accvgpr_write_b32 a206, v132 + v_accvgpr_write_b32 a205, v131 + v_accvgpr_write_b32 a204, v130 + v_accvgpr_write_b32 a203, v129 + v_accvgpr_write_b32 a202, v128 + v_accvgpr_write_b32 a201, v127 + v_accvgpr_write_b32 a200, v126 + v_accvgpr_write_b32 a199, v125 + v_accvgpr_write_b32 a198, v124 + v_accvgpr_write_b32 a197, v123 + v_accvgpr_write_b32 a196, v122 + v_accvgpr_write_b32 a195, v121 + v_accvgpr_write_b32 a194, v120 + v_accvgpr_write_b32 a193, v119 + v_accvgpr_write_b32 a192, v118 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[192:207], v[34:35], v[182:183], a[192:207] + v_accvgpr_write_b32 a143, v117 + v_accvgpr_write_b32 a142, v116 + v_accvgpr_write_b32 a141, v115 + v_accvgpr_write_b32 a140, v114 + v_accvgpr_write_b32 a139, v113 + v_accvgpr_write_b32 a138, v112 + v_accvgpr_write_b32 a137, v111 + v_accvgpr_write_b32 a136, v110 + v_accvgpr_write_b32 a135, v109 + v_accvgpr_write_b32 a134, v108 + v_accvgpr_write_b32 a133, v107 + v_accvgpr_write_b32 a132, v106 + v_accvgpr_write_b32 a131, v105 + v_accvgpr_write_b32 a130, v104 + v_accvgpr_write_b32 a129, v103 + v_accvgpr_write_b32 a128, v102 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[128:143], v[34:35], v[94:95], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[34:35], v[96:97], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[34:35], v[98:99], a[16:31] + ds_read_b32 v34, v73 + ds_read_b32 v35, v77 + v_accvgpr_write_b32 a223, v33 + v_accvgpr_write_b32 a222, v32 + v_accvgpr_write_b32 a221, v31 + v_accvgpr_write_b32 a220, v30 + v_accvgpr_write_b32 a219, v29 + v_accvgpr_write_b32 a218, v28 + v_accvgpr_write_b32 a217, v27 + v_accvgpr_write_b32 a216, v26 + v_accvgpr_write_b32 a215, v25 + v_accvgpr_write_b32 a214, v24 + v_accvgpr_write_b32 a213, v23 + v_accvgpr_write_b32 a212, v22 + v_accvgpr_write_b32 a211, v21 + v_accvgpr_write_b32 a210, v20 + v_accvgpr_write_b32 a209, v19 + v_accvgpr_write_b32 a208, v18 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[208:223], v[34:35], v[182:183], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[34:35], v[94:95], a[144:159] + v_accvgpr_write_b32 a95, v17 + v_accvgpr_write_b32 a94, v16 + v_accvgpr_write_b32 a93, v15 + v_accvgpr_write_b32 a92, v14 + v_accvgpr_write_b32 a91, v13 + v_accvgpr_write_b32 a90, v12 + v_accvgpr_write_b32 a89, v11 + v_accvgpr_write_b32 a88, v10 + v_accvgpr_write_b32 a87, v9 + v_accvgpr_write_b32 a86, v8 + v_accvgpr_write_b32 a85, v7 + v_accvgpr_write_b32 a84, v6 + v_accvgpr_write_b32 a83, v5 + v_accvgpr_write_b32 a82, v4 + v_accvgpr_write_b32 a81, v3 + v_accvgpr_write_b32 a80, v2 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[80:95], v[34:35], v[96:97], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[34:35], v[98:99], a[32:47] + ds_read_b32 v2, v70 + ds_read_b32 v3, v72 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[182:183], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[94:95], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[96:97], a[112:127] + ds_read_b32 v4, v42 + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[98:99], a[240:255] + ds_read_b32 v5, v43 + ds_read_b32 v2, v69 offset:16384 + ds_read_b32 v3, v71 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[160:175], v[4:5], v[2:3], a[160:175] + ds_read_b32 v6, v82 offset:16384 + ds_read_b32 v7, v83 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[96:111], v[4:5], v[6:7], a[96:111] + ds_read_b32 v8, v88 offset:16384 + ds_read_b32 v9, v89 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[4:5], v[8:9], a[48:63] + ds_read_b32 v10, v92 offset:16384 + ds_read_b32 v11, v93 offset:16384 + ds_read_b32 v12, v51 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[4:5], v[10:11], a[0:15] + ds_read_b32 v13, v52 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[12:13], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[12:13], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[12:13], v[8:9], a[64:79] + ds_read_b32 v4, v57 + v_mfma_i32_32x32x16_i8 a[16:31], v[12:13], v[10:11], a[16:31] + ds_read_b32 v5, v58 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[4:5], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[4:5], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[4:5], v[8:9], a[80:95] + ds_read_b32 v12, v61 + v_mfma_i32_32x32x16_i8 a[32:47], v[4:5], v[10:11], a[32:47] + ds_read_b32 v13, v62 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[12:13], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[6:7], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[8:9], a[112:127] + ds_read_b32 v2, v39 + v_mfma_i32_32x32x16_i8 a[240:255], v[12:13], v[10:11], a[240:255] + ds_read_b32 v3, v41 + ds_read_b32 v4, v65 offset:16384 + ds_read_b32 v5, v66 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[4:5], a[160:175] + ds_read_b32 v6, v74 offset:16384 + ds_read_b32 v7, v78 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[6:7], a[96:111] + ds_read_b32 v8, v84 offset:16384 + ds_read_b32 v9, v85 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v10, v90 offset:16384 + ds_read_b32 v11, v91 offset:16384 + ds_read_b32 v12, v47 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b32 v13, v48 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[12:13], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[12:13], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[12:13], v[8:9], a[64:79] + ds_read_b32 v2, v53 + v_mfma_i32_32x32x16_i8 a[16:31], v[12:13], v[10:11], a[16:31] + ds_read_b32 v3, v54 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + ds_read_b32 v12, v59 + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b32 v13, v60 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[12:13], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[6:7], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[8:9], a[112:127] + ds_read_b32 v2, v38 + v_mfma_i32_32x32x16_i8 a[240:255], v[12:13], v[10:11], a[240:255] + ds_read_b32 v3, v40 + ds_read_b32 v4, v63 offset:16384 + ds_read_b32 v5, v64 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[4:5], a[160:175] + ds_read_b32 v6, v67 offset:16384 + ds_read_b32 v7, v68 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[6:7], a[96:111] + ds_read_b32 v8, v80 offset:16384 + ds_read_b32 v9, v81 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v10, v86 offset:16384 + ds_read_b32 v11, v87 offset:16384 + ds_read_b32 v12, v44 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b32 v13, v45 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[12:13], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[12:13], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[12:13], v[8:9], a[64:79] + ds_read_b32 v2, v49 + v_mfma_i32_32x32x16_i8 a[16:31], v[12:13], v[10:11], a[16:31] + ds_read_b32 v3, v50 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + ds_read_b32 v12, v55 + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b32 v13, v56 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[12:13], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[176:191], v[12:13], v[6:7], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[12:13], v[8:9], a[112:127] + v_mfma_i32_32x32x16_i8 a[240:255], v[12:13], v[10:11], a[240:255] +.LBB35_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSA_8RowMajorESC_Li1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi64EEENS1D_ILi256EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RKT2_iPv.exit.i.i + s_nop 10 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x3fffffff + s_mul_i32 s3, s4, s16 + s_mul_hi_u32 s4, 0, s16 + s_add_i32 s4, s4, s3 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v1, 28, v36 + v_and_b32_e32 v18, 3, v36 + v_lshrrev_b32_e32 v19, 3, v36 + v_and_b32_e32 v21, 12, v19 + s_waitcnt lgkmcnt(0) + s_mov_b64 s[2:3], -1 + v_lshlrev_b32_e32 v22, 2, v18 + v_lshlrev_b32_e32 v20, 2, v1 + v_lshlrev_b32_e32 v1, 2, v36 + s_cbranch_scc1 .LBB35_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB35_14 +.LBB35_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSD_8RowMajorESF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB35_13: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_or_b32_e32 v18, s3, v21 + s_barrier + v_lshl_or_b32 v18, v18, 8, v22 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v23, v18, v20, s3 + ds_write_b32 v23, a160 + ds_write_b32 v23, a161 offset:256 + ds_write_b32 v23, a162 offset:512 + ds_write_b32 v23, a163 offset:768 + ds_write_b32 v23, a164 offset:2048 + ds_write_b32 v23, a165 offset:2304 + ds_write_b32 v23, a166 offset:2560 + ds_write_b32 v23, a167 offset:2816 + ds_write_b32 v23, a168 offset:4096 + ds_write_b32 v23, a169 offset:4352 + ds_write_b32 v23, a170 offset:4608 + ds_write_b32 v23, a171 offset:4864 + ds_write_b32 v23, a172 offset:6144 + ds_write_b32 v23, a173 offset:6400 + ds_write_b32 v23, a174 offset:6656 + ds_write_b32 v23, a175 offset:6912 + ds_write_b32 v23, a192 offset:16384 + ds_write_b32 v23, a193 offset:16640 + ds_write_b32 v23, a194 offset:16896 + ds_write_b32 v23, a195 offset:17152 + ds_write_b32 v23, a196 offset:18432 + ds_write_b32 v23, a197 offset:18688 + ds_write_b32 v23, a198 offset:18944 + ds_write_b32 v23, a199 offset:19200 + ds_write_b32 v23, a200 offset:20480 + ds_write_b32 v23, a201 offset:20736 + ds_write_b32 v23, a202 offset:20992 + ds_write_b32 v23, a203 offset:21248 + ds_write_b32 v23, a204 offset:22528 + ds_write_b32 v23, a205 offset:22784 + ds_write_b32 v23, a206 offset:23040 + ds_write_b32 v23, a207 offset:23296 + ds_write_b32 v23, a208 offset:32768 + ds_write_b32 v23, a209 offset:33024 + ds_write_b32 v23, a210 offset:33280 + ds_write_b32 v23, a211 offset:33536 + ds_write_b32 v23, a212 offset:34816 + ds_write_b32 v23, a213 offset:35072 + ds_write_b32 v23, a214 offset:35328 + ds_write_b32 v23, a215 offset:35584 + ds_write_b32 v23, a216 offset:36864 + ds_write_b32 v23, a217 offset:37120 + ds_write_b32 v23, a218 offset:37376 + ds_write_b32 v23, a219 offset:37632 + ds_write_b32 v23, a220 offset:38912 + ds_write_b32 v23, a221 offset:39168 + ds_write_b32 v23, a222 offset:39424 + ds_write_b32 v23, a223 offset:39680 + ds_write_b32 v23, a224 offset:49152 + ds_write_b32 v23, a225 offset:49408 + ds_write_b32 v23, a226 offset:49664 + ds_write_b32 v23, a227 offset:49920 + ds_write_b32 v23, a228 offset:51200 + ds_write_b32 v23, a229 offset:51456 + ds_write_b32 v23, a230 offset:51712 + ds_write_b32 v23, a231 offset:51968 + ds_write_b32 v23, a232 offset:53248 + ds_write_b32 v23, a233 offset:53504 + ds_write_b32 v23, a234 offset:53760 + ds_write_b32 v23, a235 offset:54016 + ds_write_b32 v23, a236 offset:55296 + ds_write_b32 v23, a237 offset:55552 + ds_write_b32 v23, a238 offset:55808 + ds_write_b32 v23, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v18, 60, v1 + s_andn2_b32 s2, s2, 63 + v_and_b32_e32 v19, 0x70, v36 + v_add_u32_e32 v19, s2, v19 + v_lshlrev_b32_e32 v24, 8, v19 + v_lshl_or_b32 v24, v18, 2, v24 + ds_read_b128 v[26:29], v24 + ds_read_b128 v[30:33], v24 offset:256 + ds_read_b128 v[38:41], v24 offset:512 + ds_read_b128 v[42:45], v24 offset:768 + ds_read_b128 v[46:49], v24 offset:1024 + ds_read_b128 v[50:53], v24 offset:1280 + ds_read_b128 v[54:57], v24 offset:1536 + ds_read_b128 v[58:61], v24 offset:1792 + ds_read_b128 v[62:65], v24 offset:2048 + ds_read_b128 v[66:69], v24 offset:2304 + ds_read_b128 v[70:73], v24 offset:2560 + ds_read_b128 v[74:77], v24 offset:2816 + ds_read_b128 v[78:81], v24 offset:3072 + ds_read_b128 v[82:85], v24 offset:3328 + ds_read_b128 v[86:89], v24 offset:3584 + ds_read_b128 v[90:93], v24 offset:3840 + v_add_u32_e32 v19, s20, v19 + v_or_b32_e32 v18, s21, v18 + v_mad_u64_u32 v[18:19], s[2:3], v19, s16, v[18:19] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v18 + v_lshlrev_b32_e32 v25, 2, v19 + buffer_atomic_add v30, v25, s[0:3], 0 offen + buffer_atomic_add v31, v25, s[0:3], 4 offen + buffer_atomic_add v32, v25, s[0:3], 8 offen + buffer_atomic_add v33, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v38, v25, s[0:3], 0 offen + buffer_atomic_add v39, v25, s[0:3], 4 offen + buffer_atomic_add v40, v25, s[0:3], 8 offen + buffer_atomic_add v41, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v42, v25, s[0:3], 0 offen + buffer_atomic_add v43, v25, s[0:3], 4 offen + buffer_atomic_add v44, v25, s[0:3], 8 offen + buffer_atomic_add v45, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v46, v25, s[0:3], 0 offen + buffer_atomic_add v47, v25, s[0:3], 4 offen + buffer_atomic_add v48, v25, s[0:3], 8 offen + buffer_atomic_add v49, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v50, v25, s[0:3], 0 offen + buffer_atomic_add v51, v25, s[0:3], 4 offen + buffer_atomic_add v52, v25, s[0:3], 8 offen + buffer_atomic_add v53, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v54, v25, s[0:3], 0 offen + buffer_atomic_add v55, v25, s[0:3], 4 offen + buffer_atomic_add v56, v25, s[0:3], 8 offen + buffer_atomic_add v57, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v58, v25, s[0:3], 0 offen + buffer_atomic_add v59, v25, s[0:3], 4 offen + buffer_atomic_add v60, v25, s[0:3], 8 offen + buffer_atomic_add v61, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v62, v25, s[0:3], 0 offen + buffer_atomic_add v63, v25, s[0:3], 4 offen + buffer_atomic_add v64, v25, s[0:3], 8 offen + buffer_atomic_add v65, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v66, v25, s[0:3], 0 offen + buffer_atomic_add v67, v25, s[0:3], 4 offen + buffer_atomic_add v68, v25, s[0:3], 8 offen + buffer_atomic_add v69, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v70, v25, s[0:3], 0 offen + buffer_atomic_add v71, v25, s[0:3], 4 offen + buffer_atomic_add v72, v25, s[0:3], 8 offen + buffer_atomic_add v73, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v74, v25, s[0:3], 0 offen + buffer_atomic_add v75, v25, s[0:3], 4 offen + buffer_atomic_add v76, v25, s[0:3], 8 offen + buffer_atomic_add v77, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v78, v25, s[0:3], 0 offen + buffer_atomic_add v79, v25, s[0:3], 4 offen + buffer_atomic_add v80, v25, s[0:3], 8 offen + buffer_atomic_add v81, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v82, v25, s[0:3], 0 offen + buffer_atomic_add v83, v25, s[0:3], 4 offen + buffer_atomic_add v84, v25, s[0:3], 8 offen + buffer_atomic_add v85, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v86, v25, s[0:3], 0 offen + buffer_atomic_add v87, v25, s[0:3], 4 offen + buffer_atomic_add v88, v25, s[0:3], 8 offen + buffer_atomic_add v89, v25, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v90, v19, s[0:3], 0 offen + buffer_atomic_add v91, v19, s[0:3], 4 offen + buffer_atomic_add v92, v19, s[0:3], 8 offen + buffer_atomic_add v93, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v23, a96 + ds_write_b32 v23, a97 offset:256 + ds_write_b32 v23, a98 offset:512 + ds_write_b32 v23, a99 offset:768 + ds_write_b32 v23, a100 offset:2048 + ds_write_b32 v23, a101 offset:2304 + ds_write_b32 v23, a102 offset:2560 + ds_write_b32 v23, a103 offset:2816 + ds_write_b32 v23, a104 offset:4096 + ds_write_b32 v23, a105 offset:4352 + ds_write_b32 v23, a106 offset:4608 + ds_write_b32 v23, a107 offset:4864 + ds_write_b32 v23, a108 offset:6144 + ds_write_b32 v23, a109 offset:6400 + ds_write_b32 v23, a110 offset:6656 + ds_write_b32 v23, a111 offset:6912 + ds_write_b32 v23, a128 offset:16384 + ds_write_b32 v23, a129 offset:16640 + ds_write_b32 v23, a130 offset:16896 + ds_write_b32 v23, a131 offset:17152 + ds_write_b32 v23, a132 offset:18432 + ds_write_b32 v23, a133 offset:18688 + ds_write_b32 v23, a134 offset:18944 + ds_write_b32 v23, a135 offset:19200 + ds_write_b32 v23, a136 offset:20480 + ds_write_b32 v23, a137 offset:20736 + ds_write_b32 v23, a138 offset:20992 + ds_write_b32 v23, a139 offset:21248 + ds_write_b32 v23, a140 offset:22528 + ds_write_b32 v23, a141 offset:22784 + ds_write_b32 v23, a142 offset:23040 + ds_write_b32 v23, a143 offset:23296 + ds_write_b32 v23, a144 offset:32768 + ds_write_b32 v23, a145 offset:33024 + ds_write_b32 v23, a146 offset:33280 + ds_write_b32 v23, a147 offset:33536 + ds_write_b32 v23, a148 offset:34816 + ds_write_b32 v23, a149 offset:35072 + ds_write_b32 v23, a150 offset:35328 + ds_write_b32 v23, a151 offset:35584 + ds_write_b32 v23, a152 offset:36864 + ds_write_b32 v23, a153 offset:37120 + ds_write_b32 v23, a154 offset:37376 + ds_write_b32 v23, a155 offset:37632 + ds_write_b32 v23, a156 offset:38912 + ds_write_b32 v23, a157 offset:39168 + ds_write_b32 v23, a158 offset:39424 + ds_write_b32 v23, a159 offset:39680 + ds_write_b32 v23, a176 offset:49152 + ds_write_b32 v23, a177 offset:49408 + ds_write_b32 v23, a178 offset:49664 + ds_write_b32 v23, a179 offset:49920 + ds_write_b32 v23, a180 offset:51200 + ds_write_b32 v23, a181 offset:51456 + ds_write_b32 v23, a182 offset:51712 + ds_write_b32 v23, a183 offset:51968 + ds_write_b32 v23, a184 offset:53248 + ds_write_b32 v23, a185 offset:53504 + ds_write_b32 v23, a186 offset:53760 + ds_write_b32 v23, a187 offset:54016 + ds_write_b32 v23, a188 offset:55296 + ds_write_b32 v23, a189 offset:55552 + ds_write_b32 v23, a190 offset:55808 + ds_write_b32 v23, a191 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v24 + ds_read_b128 v[30:33], v24 offset:256 + ds_read_b128 v[38:41], v24 offset:512 + ds_read_b128 v[42:45], v24 offset:768 + ds_read_b128 v[46:49], v24 offset:1024 + ds_read_b128 v[50:53], v24 offset:1280 + ds_read_b128 v[54:57], v24 offset:1536 + ds_read_b128 v[58:61], v24 offset:1792 + ds_read_b128 v[62:65], v24 offset:2048 + ds_read_b128 v[66:69], v24 offset:2304 + ds_read_b128 v[70:73], v24 offset:2560 + ds_read_b128 v[74:77], v24 offset:2816 + ds_read_b128 v[78:81], v24 offset:3072 + ds_read_b128 v[82:85], v24 offset:3328 + ds_read_b128 v[86:89], v24 offset:3584 + ds_read_b128 v[90:93], v24 offset:3840 + v_add_u32_e32 v19, 64, v18 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v25, s[0:3], 0 offen + buffer_atomic_add v27, v25, s[0:3], 4 offen + buffer_atomic_add v28, v25, s[0:3], 8 offen + buffer_atomic_add v29, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + buffer_atomic_add v30, v25, s[0:3], 0 offen + buffer_atomic_add v31, v25, s[0:3], 4 offen + buffer_atomic_add v32, v25, s[0:3], 8 offen + buffer_atomic_add v33, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v38, v25, s[0:3], 0 offen + buffer_atomic_add v39, v25, s[0:3], 4 offen + buffer_atomic_add v40, v25, s[0:3], 8 offen + buffer_atomic_add v41, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v42, v25, s[0:3], 0 offen + buffer_atomic_add v43, v25, s[0:3], 4 offen + buffer_atomic_add v44, v25, s[0:3], 8 offen + buffer_atomic_add v45, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v46, v25, s[0:3], 0 offen + buffer_atomic_add v47, v25, s[0:3], 4 offen + buffer_atomic_add v48, v25, s[0:3], 8 offen + buffer_atomic_add v49, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v50, v25, s[0:3], 0 offen + buffer_atomic_add v51, v25, s[0:3], 4 offen + buffer_atomic_add v52, v25, s[0:3], 8 offen + buffer_atomic_add v53, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v54, v25, s[0:3], 0 offen + buffer_atomic_add v55, v25, s[0:3], 4 offen + buffer_atomic_add v56, v25, s[0:3], 8 offen + buffer_atomic_add v57, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v58, v25, s[0:3], 0 offen + buffer_atomic_add v59, v25, s[0:3], 4 offen + buffer_atomic_add v60, v25, s[0:3], 8 offen + buffer_atomic_add v61, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v62, v25, s[0:3], 0 offen + buffer_atomic_add v63, v25, s[0:3], 4 offen + buffer_atomic_add v64, v25, s[0:3], 8 offen + buffer_atomic_add v65, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v66, v25, s[0:3], 0 offen + buffer_atomic_add v67, v25, s[0:3], 4 offen + buffer_atomic_add v68, v25, s[0:3], 8 offen + buffer_atomic_add v69, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v70, v25, s[0:3], 0 offen + buffer_atomic_add v71, v25, s[0:3], 4 offen + buffer_atomic_add v72, v25, s[0:3], 8 offen + buffer_atomic_add v73, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v74, v25, s[0:3], 0 offen + buffer_atomic_add v75, v25, s[0:3], 4 offen + buffer_atomic_add v76, v25, s[0:3], 8 offen + buffer_atomic_add v77, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v78, v25, s[0:3], 0 offen + buffer_atomic_add v79, v25, s[0:3], 4 offen + buffer_atomic_add v80, v25, s[0:3], 8 offen + buffer_atomic_add v81, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v82, v25, s[0:3], 0 offen + buffer_atomic_add v83, v25, s[0:3], 4 offen + buffer_atomic_add v84, v25, s[0:3], 8 offen + buffer_atomic_add v85, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v86, v25, s[0:3], 0 offen + buffer_atomic_add v87, v25, s[0:3], 4 offen + buffer_atomic_add v88, v25, s[0:3], 8 offen + buffer_atomic_add v89, v25, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v90, v19, s[0:3], 0 offen + buffer_atomic_add v91, v19, s[0:3], 4 offen + buffer_atomic_add v92, v19, s[0:3], 8 offen + buffer_atomic_add v93, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v23, a48 + ds_write_b32 v23, a49 offset:256 + ds_write_b32 v23, a50 offset:512 + ds_write_b32 v23, a51 offset:768 + ds_write_b32 v23, a52 offset:2048 + ds_write_b32 v23, a53 offset:2304 + ds_write_b32 v23, a54 offset:2560 + ds_write_b32 v23, a55 offset:2816 + ds_write_b32 v23, a56 offset:4096 + ds_write_b32 v23, a57 offset:4352 + ds_write_b32 v23, a58 offset:4608 + ds_write_b32 v23, a59 offset:4864 + ds_write_b32 v23, a60 offset:6144 + ds_write_b32 v23, a61 offset:6400 + ds_write_b32 v23, a62 offset:6656 + ds_write_b32 v23, a63 offset:6912 + ds_write_b32 v23, a64 offset:16384 + ds_write_b32 v23, a65 offset:16640 + ds_write_b32 v23, a66 offset:16896 + ds_write_b32 v23, a67 offset:17152 + ds_write_b32 v23, a68 offset:18432 + ds_write_b32 v23, a69 offset:18688 + ds_write_b32 v23, a70 offset:18944 + ds_write_b32 v23, a71 offset:19200 + ds_write_b32 v23, a72 offset:20480 + ds_write_b32 v23, a73 offset:20736 + ds_write_b32 v23, a74 offset:20992 + ds_write_b32 v23, a75 offset:21248 + ds_write_b32 v23, a76 offset:22528 + ds_write_b32 v23, a77 offset:22784 + ds_write_b32 v23, a78 offset:23040 + ds_write_b32 v23, a79 offset:23296 + ds_write_b32 v23, a80 offset:32768 + ds_write_b32 v23, a81 offset:33024 + ds_write_b32 v23, a82 offset:33280 + ds_write_b32 v23, a83 offset:33536 + ds_write_b32 v23, a84 offset:34816 + ds_write_b32 v23, a85 offset:35072 + ds_write_b32 v23, a86 offset:35328 + ds_write_b32 v23, a87 offset:35584 + ds_write_b32 v23, a88 offset:36864 + ds_write_b32 v23, a89 offset:37120 + ds_write_b32 v23, a90 offset:37376 + ds_write_b32 v23, a91 offset:37632 + ds_write_b32 v23, a92 offset:38912 + ds_write_b32 v23, a93 offset:39168 + ds_write_b32 v23, a94 offset:39424 + ds_write_b32 v23, a95 offset:39680 + ds_write_b32 v23, a112 offset:49152 + ds_write_b32 v23, a113 offset:49408 + ds_write_b32 v23, a114 offset:49664 + ds_write_b32 v23, a115 offset:49920 + ds_write_b32 v23, a116 offset:51200 + ds_write_b32 v23, a117 offset:51456 + ds_write_b32 v23, a118 offset:51712 + ds_write_b32 v23, a119 offset:51968 + ds_write_b32 v23, a120 offset:53248 + ds_write_b32 v23, a121 offset:53504 + ds_write_b32 v23, a122 offset:53760 + ds_write_b32 v23, a123 offset:54016 + ds_write_b32 v23, a124 offset:55296 + ds_write_b32 v23, a125 offset:55552 + ds_write_b32 v23, a126 offset:55808 + ds_write_b32 v23, a127 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v24 + ds_read_b128 v[30:33], v24 offset:256 + ds_read_b128 v[38:41], v24 offset:512 + ds_read_b128 v[42:45], v24 offset:768 + ds_read_b128 v[46:49], v24 offset:1024 + ds_read_b128 v[50:53], v24 offset:1280 + ds_read_b128 v[54:57], v24 offset:1536 + ds_read_b128 v[58:61], v24 offset:1792 + ds_read_b128 v[62:65], v24 offset:2048 + ds_read_b128 v[66:69], v24 offset:2304 + ds_read_b128 v[70:73], v24 offset:2560 + ds_read_b128 v[74:77], v24 offset:2816 + ds_read_b128 v[78:81], v24 offset:3072 + ds_read_b128 v[82:85], v24 offset:3328 + ds_read_b128 v[86:89], v24 offset:3584 + ds_read_b128 v[90:93], v24 offset:3840 + v_add_u32_e32 v19, 0x80, v18 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v25, s[0:3], 0 offen + buffer_atomic_add v27, v25, s[0:3], 4 offen + buffer_atomic_add v28, v25, s[0:3], 8 offen + buffer_atomic_add v29, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + buffer_atomic_add v30, v25, s[0:3], 0 offen + buffer_atomic_add v31, v25, s[0:3], 4 offen + buffer_atomic_add v32, v25, s[0:3], 8 offen + buffer_atomic_add v33, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v38, v25, s[0:3], 0 offen + buffer_atomic_add v39, v25, s[0:3], 4 offen + buffer_atomic_add v40, v25, s[0:3], 8 offen + buffer_atomic_add v41, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v42, v25, s[0:3], 0 offen + buffer_atomic_add v43, v25, s[0:3], 4 offen + buffer_atomic_add v44, v25, s[0:3], 8 offen + buffer_atomic_add v45, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v46, v25, s[0:3], 0 offen + buffer_atomic_add v47, v25, s[0:3], 4 offen + buffer_atomic_add v48, v25, s[0:3], 8 offen + buffer_atomic_add v49, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v50, v25, s[0:3], 0 offen + buffer_atomic_add v51, v25, s[0:3], 4 offen + buffer_atomic_add v52, v25, s[0:3], 8 offen + buffer_atomic_add v53, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v54, v25, s[0:3], 0 offen + buffer_atomic_add v55, v25, s[0:3], 4 offen + buffer_atomic_add v56, v25, s[0:3], 8 offen + buffer_atomic_add v57, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v58, v25, s[0:3], 0 offen + buffer_atomic_add v59, v25, s[0:3], 4 offen + buffer_atomic_add v60, v25, s[0:3], 8 offen + buffer_atomic_add v61, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v62, v25, s[0:3], 0 offen + buffer_atomic_add v63, v25, s[0:3], 4 offen + buffer_atomic_add v64, v25, s[0:3], 8 offen + buffer_atomic_add v65, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v66, v25, s[0:3], 0 offen + buffer_atomic_add v67, v25, s[0:3], 4 offen + buffer_atomic_add v68, v25, s[0:3], 8 offen + buffer_atomic_add v69, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v70, v25, s[0:3], 0 offen + buffer_atomic_add v71, v25, s[0:3], 4 offen + buffer_atomic_add v72, v25, s[0:3], 8 offen + buffer_atomic_add v73, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v74, v25, s[0:3], 0 offen + buffer_atomic_add v75, v25, s[0:3], 4 offen + buffer_atomic_add v76, v25, s[0:3], 8 offen + buffer_atomic_add v77, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v78, v25, s[0:3], 0 offen + buffer_atomic_add v79, v25, s[0:3], 4 offen + buffer_atomic_add v80, v25, s[0:3], 8 offen + buffer_atomic_add v81, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v82, v25, s[0:3], 0 offen + buffer_atomic_add v83, v25, s[0:3], 4 offen + buffer_atomic_add v84, v25, s[0:3], 8 offen + buffer_atomic_add v85, v25, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v25, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v86, v25, s[0:3], 0 offen + buffer_atomic_add v87, v25, s[0:3], 4 offen + buffer_atomic_add v88, v25, s[0:3], 8 offen + buffer_atomic_add v89, v25, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v90, v19, s[0:3], 0 offen + buffer_atomic_add v91, v19, s[0:3], 4 offen + buffer_atomic_add v92, v19, s[0:3], 8 offen + buffer_atomic_add v93, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v23, a0 + ds_write_b32 v23, a1 offset:256 + ds_write_b32 v23, a2 offset:512 + ds_write_b32 v23, a3 offset:768 + ds_write_b32 v23, a4 offset:2048 + ds_write_b32 v23, a5 offset:2304 + ds_write_b32 v23, a6 offset:2560 + ds_write_b32 v23, a7 offset:2816 + ds_write_b32 v23, a8 offset:4096 + ds_write_b32 v23, a9 offset:4352 + ds_write_b32 v23, a10 offset:4608 + ds_write_b32 v23, a11 offset:4864 + ds_write_b32 v23, a12 offset:6144 + ds_write_b32 v23, a13 offset:6400 + ds_write_b32 v23, a14 offset:6656 + ds_write_b32 v23, a15 offset:6912 + ds_write_b32 v23, a16 offset:16384 + ds_write_b32 v23, a17 offset:16640 + ds_write_b32 v23, a18 offset:16896 + ds_write_b32 v23, a19 offset:17152 + ds_write_b32 v23, a20 offset:18432 + ds_write_b32 v23, a21 offset:18688 + ds_write_b32 v23, a22 offset:18944 + ds_write_b32 v23, a23 offset:19200 + ds_write_b32 v23, a24 offset:20480 + ds_write_b32 v23, a25 offset:20736 + ds_write_b32 v23, a26 offset:20992 + ds_write_b32 v23, a27 offset:21248 + ds_write_b32 v23, a28 offset:22528 + ds_write_b32 v23, a29 offset:22784 + ds_write_b32 v23, a30 offset:23040 + ds_write_b32 v23, a31 offset:23296 + ds_write_b32 v23, a32 offset:32768 + ds_write_b32 v23, a33 offset:33024 + ds_write_b32 v23, a34 offset:33280 + ds_write_b32 v23, a35 offset:33536 + ds_write_b32 v23, a36 offset:34816 + ds_write_b32 v23, a37 offset:35072 + ds_write_b32 v23, a38 offset:35328 + ds_write_b32 v23, a39 offset:35584 + ds_write_b32 v23, a40 offset:36864 + ds_write_b32 v23, a41 offset:37120 + ds_write_b32 v23, a42 offset:37376 + ds_write_b32 v23, a43 offset:37632 + ds_write_b32 v23, a44 offset:38912 + ds_write_b32 v23, a45 offset:39168 + ds_write_b32 v23, a46 offset:39424 + ds_write_b32 v23, a47 offset:39680 + ds_write2st64_b32 v23, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v23, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v23, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v23, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v23, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v23, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v23, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v23, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v24 + ds_read_b128 v[30:33], v24 offset:256 + ds_read_b128 v[38:41], v24 offset:512 + ds_read_b128 v[42:45], v24 offset:768 + ds_read_b128 v[46:49], v24 offset:1024 + ds_read_b128 v[50:53], v24 offset:1280 + ds_read_b128 v[54:57], v24 offset:1536 + ds_read_b128 v[58:61], v24 offset:1792 + ds_read_b128 v[62:65], v24 offset:2048 + ds_read_b128 v[66:69], v24 offset:2304 + ds_read_b128 v[70:73], v24 offset:2560 + ds_read_b128 v[74:77], v24 offset:2816 + ds_read_b128 v[78:81], v24 offset:3072 + ds_read_b128 v[82:85], v24 offset:3328 + ds_read_b128 v[86:89], v24 offset:3584 + ds_read_b128 v[90:93], v24 offset:3840 + v_add_u32_e32 v18, 0xc0, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + buffer_atomic_add v30, v19, s[0:3], 0 offen + buffer_atomic_add v31, v19, s[0:3], 4 offen + buffer_atomic_add v32, v19, s[0:3], 8 offen + buffer_atomic_add v33, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v38, v19, s[0:3], 0 offen + buffer_atomic_add v39, v19, s[0:3], 4 offen + buffer_atomic_add v40, v19, s[0:3], 8 offen + buffer_atomic_add v41, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v42, v19, s[0:3], 0 offen + buffer_atomic_add v43, v19, s[0:3], 4 offen + buffer_atomic_add v44, v19, s[0:3], 8 offen + buffer_atomic_add v45, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v46, v19, s[0:3], 0 offen + buffer_atomic_add v47, v19, s[0:3], 4 offen + buffer_atomic_add v48, v19, s[0:3], 8 offen + buffer_atomic_add v49, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v50, v19, s[0:3], 0 offen + buffer_atomic_add v51, v19, s[0:3], 4 offen + buffer_atomic_add v52, v19, s[0:3], 8 offen + buffer_atomic_add v53, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v54, v19, s[0:3], 0 offen + buffer_atomic_add v55, v19, s[0:3], 4 offen + buffer_atomic_add v56, v19, s[0:3], 8 offen + buffer_atomic_add v57, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v58, v19, s[0:3], 0 offen + buffer_atomic_add v59, v19, s[0:3], 4 offen + buffer_atomic_add v60, v19, s[0:3], 8 offen + buffer_atomic_add v61, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v62, v19, s[0:3], 0 offen + buffer_atomic_add v63, v19, s[0:3], 4 offen + buffer_atomic_add v64, v19, s[0:3], 8 offen + buffer_atomic_add v65, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v66, v19, s[0:3], 0 offen + buffer_atomic_add v67, v19, s[0:3], 4 offen + buffer_atomic_add v68, v19, s[0:3], 8 offen + buffer_atomic_add v69, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v70, v19, s[0:3], 0 offen + buffer_atomic_add v71, v19, s[0:3], 4 offen + buffer_atomic_add v72, v19, s[0:3], 8 offen + buffer_atomic_add v73, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v74, v19, s[0:3], 0 offen + buffer_atomic_add v75, v19, s[0:3], 4 offen + buffer_atomic_add v76, v19, s[0:3], 8 offen + buffer_atomic_add v77, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v78, v19, s[0:3], 0 offen + buffer_atomic_add v79, v19, s[0:3], 4 offen + buffer_atomic_add v80, v19, s[0:3], 8 offen + buffer_atomic_add v81, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v82, v19, s[0:3], 0 offen + buffer_atomic_add v83, v19, s[0:3], 4 offen + buffer_atomic_add v84, v19, s[0:3], 8 offen + buffer_atomic_add v85, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + v_add_lshl_u32 v18, v18, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v90, v18, s[0:3], 0 offen + buffer_atomic_add v91, v18, s[0:3], 4 offen + buffer_atomic_add v92, v18, s[0:3], 8 offen + buffer_atomic_add v93, v18, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB35_12 +.LBB35_14: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_or_b32_e32 v0, s3, v21 + s_barrier + v_lshl_or_b32 v0, v0, 8, v22 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v82, v0, v20, s3 + ds_write_b32 v82, a160 + ds_write_b32 v82, a161 offset:256 + ds_write_b32 v82, a162 offset:512 + ds_write_b32 v82, a163 offset:768 + ds_write_b32 v82, a164 offset:2048 + ds_write_b32 v82, a165 offset:2304 + ds_write_b32 v82, a166 offset:2560 + ds_write_b32 v82, a167 offset:2816 + ds_write_b32 v82, a168 offset:4096 + ds_write_b32 v82, a169 offset:4352 + ds_write_b32 v82, a170 offset:4608 + ds_write_b32 v82, a171 offset:4864 + ds_write_b32 v82, a172 offset:6144 + ds_write_b32 v82, a173 offset:6400 + ds_write_b32 v82, a174 offset:6656 + ds_write_b32 v82, a175 offset:6912 + ds_write_b32 v82, a192 offset:16384 + ds_write_b32 v82, a193 offset:16640 + ds_write_b32 v82, a194 offset:16896 + ds_write_b32 v82, a195 offset:17152 + ds_write_b32 v82, a196 offset:18432 + ds_write_b32 v82, a197 offset:18688 + ds_write_b32 v82, a198 offset:18944 + ds_write_b32 v82, a199 offset:19200 + ds_write_b32 v82, a200 offset:20480 + ds_write_b32 v82, a201 offset:20736 + ds_write_b32 v82, a202 offset:20992 + ds_write_b32 v82, a203 offset:21248 + ds_write_b32 v82, a204 offset:22528 + ds_write_b32 v82, a205 offset:22784 + ds_write_b32 v82, a206 offset:23040 + ds_write_b32 v82, a207 offset:23296 + ds_write_b32 v82, a208 offset:32768 + ds_write_b32 v82, a209 offset:33024 + ds_write_b32 v82, a210 offset:33280 + ds_write_b32 v82, a211 offset:33536 + ds_write_b32 v82, a212 offset:34816 + ds_write_b32 v82, a213 offset:35072 + ds_write_b32 v82, a214 offset:35328 + ds_write_b32 v82, a215 offset:35584 + ds_write_b32 v82, a216 offset:36864 + ds_write_b32 v82, a217 offset:37120 + ds_write_b32 v82, a218 offset:37376 + ds_write_b32 v82, a219 offset:37632 + ds_write_b32 v82, a220 offset:38912 + ds_write_b32 v82, a221 offset:39168 + ds_write_b32 v82, a222 offset:39424 + ds_write_b32 v82, a223 offset:39680 + ds_write_b32 v82, a224 offset:49152 + ds_write_b32 v82, a225 offset:49408 + ds_write_b32 v82, a226 offset:49664 + ds_write_b32 v82, a227 offset:49920 + ds_write_b32 v82, a228 offset:51200 + ds_write_b32 v82, a229 offset:51456 + ds_write_b32 v82, a230 offset:51712 + ds_write_b32 v82, a231 offset:51968 + ds_write_b32 v82, a232 offset:53248 + ds_write_b32 v82, a233 offset:53504 + ds_write_b32 v82, a234 offset:53760 + ds_write_b32 v82, a235 offset:54016 + ds_write_b32 v82, a236 offset:55296 + ds_write_b32 v82, a237 offset:55552 + ds_write_b32 v82, a238 offset:55808 + ds_write_b32 v82, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 60, v1 + s_andn2_b32 s2, s2, 63 + v_and_b32_e32 v1, 0x70, v36 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 8, v1 + v_lshl_or_b32 v83, v0, 2, v18 + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v0, s21, v0 + v_mad_u64_u32 v[0:1], s[2:3], v1, s16, v[0:1] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a96 + ds_write_b32 v82, a97 offset:256 + ds_write_b32 v82, a98 offset:512 + ds_write_b32 v82, a99 offset:768 + ds_write_b32 v82, a100 offset:2048 + ds_write_b32 v82, a101 offset:2304 + ds_write_b32 v82, a102 offset:2560 + ds_write_b32 v82, a103 offset:2816 + ds_write_b32 v82, a104 offset:4096 + ds_write_b32 v82, a105 offset:4352 + ds_write_b32 v82, a106 offset:4608 + ds_write_b32 v82, a107 offset:4864 + ds_write_b32 v82, a108 offset:6144 + ds_write_b32 v82, a109 offset:6400 + ds_write_b32 v82, a110 offset:6656 + ds_write_b32 v82, a111 offset:6912 + ds_write_b32 v82, a128 offset:16384 + ds_write_b32 v82, a129 offset:16640 + ds_write_b32 v82, a130 offset:16896 + ds_write_b32 v82, a131 offset:17152 + ds_write_b32 v82, a132 offset:18432 + ds_write_b32 v82, a133 offset:18688 + ds_write_b32 v82, a134 offset:18944 + ds_write_b32 v82, a135 offset:19200 + ds_write_b32 v82, a136 offset:20480 + ds_write_b32 v82, a137 offset:20736 + ds_write_b32 v82, a138 offset:20992 + ds_write_b32 v82, a139 offset:21248 + ds_write_b32 v82, a140 offset:22528 + ds_write_b32 v82, a141 offset:22784 + ds_write_b32 v82, a142 offset:23040 + ds_write_b32 v82, a143 offset:23296 + ds_write_b32 v82, a144 offset:32768 + ds_write_b32 v82, a145 offset:33024 + ds_write_b32 v82, a146 offset:33280 + ds_write_b32 v82, a147 offset:33536 + ds_write_b32 v82, a148 offset:34816 + ds_write_b32 v82, a149 offset:35072 + ds_write_b32 v82, a150 offset:35328 + ds_write_b32 v82, a151 offset:35584 + ds_write_b32 v82, a152 offset:36864 + ds_write_b32 v82, a153 offset:37120 + ds_write_b32 v82, a154 offset:37376 + ds_write_b32 v82, a155 offset:37632 + ds_write_b32 v82, a156 offset:38912 + ds_write_b32 v82, a157 offset:39168 + ds_write_b32 v82, a158 offset:39424 + ds_write_b32 v82, a159 offset:39680 + ds_write_b32 v82, a176 offset:49152 + ds_write_b32 v82, a177 offset:49408 + ds_write_b32 v82, a178 offset:49664 + ds_write_b32 v82, a179 offset:49920 + ds_write_b32 v82, a180 offset:51200 + ds_write_b32 v82, a181 offset:51456 + ds_write_b32 v82, a182 offset:51712 + ds_write_b32 v82, a183 offset:51968 + ds_write_b32 v82, a184 offset:53248 + ds_write_b32 v82, a185 offset:53504 + ds_write_b32 v82, a186 offset:53760 + ds_write_b32 v82, a187 offset:54016 + ds_write_b32 v82, a188 offset:55296 + ds_write_b32 v82, a189 offset:55552 + ds_write_b32 v82, a190 offset:55808 + ds_write_b32 v82, a191 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 64, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a48 + ds_write_b32 v82, a49 offset:256 + ds_write_b32 v82, a50 offset:512 + ds_write_b32 v82, a51 offset:768 + ds_write_b32 v82, a52 offset:2048 + ds_write_b32 v82, a53 offset:2304 + ds_write_b32 v82, a54 offset:2560 + ds_write_b32 v82, a55 offset:2816 + ds_write_b32 v82, a56 offset:4096 + ds_write_b32 v82, a57 offset:4352 + ds_write_b32 v82, a58 offset:4608 + ds_write_b32 v82, a59 offset:4864 + ds_write_b32 v82, a60 offset:6144 + ds_write_b32 v82, a61 offset:6400 + ds_write_b32 v82, a62 offset:6656 + ds_write_b32 v82, a63 offset:6912 + ds_write_b32 v82, a64 offset:16384 + ds_write_b32 v82, a65 offset:16640 + ds_write_b32 v82, a66 offset:16896 + ds_write_b32 v82, a67 offset:17152 + ds_write_b32 v82, a68 offset:18432 + ds_write_b32 v82, a69 offset:18688 + ds_write_b32 v82, a70 offset:18944 + ds_write_b32 v82, a71 offset:19200 + ds_write_b32 v82, a72 offset:20480 + ds_write_b32 v82, a73 offset:20736 + ds_write_b32 v82, a74 offset:20992 + ds_write_b32 v82, a75 offset:21248 + ds_write_b32 v82, a76 offset:22528 + ds_write_b32 v82, a77 offset:22784 + ds_write_b32 v82, a78 offset:23040 + ds_write_b32 v82, a79 offset:23296 + ds_write_b32 v82, a80 offset:32768 + ds_write_b32 v82, a81 offset:33024 + ds_write_b32 v82, a82 offset:33280 + ds_write_b32 v82, a83 offset:33536 + ds_write_b32 v82, a84 offset:34816 + ds_write_b32 v82, a85 offset:35072 + ds_write_b32 v82, a86 offset:35328 + ds_write_b32 v82, a87 offset:35584 + ds_write_b32 v82, a88 offset:36864 + ds_write_b32 v82, a89 offset:37120 + ds_write_b32 v82, a90 offset:37376 + ds_write_b32 v82, a91 offset:37632 + ds_write_b32 v82, a92 offset:38912 + ds_write_b32 v82, a93 offset:39168 + ds_write_b32 v82, a94 offset:39424 + ds_write_b32 v82, a95 offset:39680 + ds_write_b32 v82, a112 offset:49152 + ds_write_b32 v82, a113 offset:49408 + ds_write_b32 v82, a114 offset:49664 + ds_write_b32 v82, a115 offset:49920 + ds_write_b32 v82, a116 offset:51200 + ds_write_b32 v82, a117 offset:51456 + ds_write_b32 v82, a118 offset:51712 + ds_write_b32 v82, a119 offset:51968 + ds_write_b32 v82, a120 offset:53248 + ds_write_b32 v82, a121 offset:53504 + ds_write_b32 v82, a122 offset:53760 + ds_write_b32 v82, a123 offset:54016 + ds_write_b32 v82, a124 offset:55296 + ds_write_b32 v82, a125 offset:55552 + ds_write_b32 v82, a126 offset:55808 + ds_write_b32 v82, a127 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 0x80, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a0 + ds_write_b32 v82, a1 offset:256 + ds_write_b32 v82, a2 offset:512 + ds_write_b32 v82, a3 offset:768 + ds_write_b32 v82, a4 offset:2048 + ds_write_b32 v82, a5 offset:2304 + ds_write_b32 v82, a6 offset:2560 + ds_write_b32 v82, a7 offset:2816 + ds_write_b32 v82, a8 offset:4096 + ds_write_b32 v82, a9 offset:4352 + ds_write_b32 v82, a10 offset:4608 + ds_write_b32 v82, a11 offset:4864 + ds_write_b32 v82, a12 offset:6144 + ds_write_b32 v82, a13 offset:6400 + ds_write_b32 v82, a14 offset:6656 + ds_write_b32 v82, a15 offset:6912 + ds_write_b32 v82, a16 offset:16384 + ds_write_b32 v82, a17 offset:16640 + ds_write_b32 v82, a18 offset:16896 + ds_write_b32 v82, a19 offset:17152 + ds_write_b32 v82, a20 offset:18432 + ds_write_b32 v82, a21 offset:18688 + ds_write_b32 v82, a22 offset:18944 + ds_write_b32 v82, a23 offset:19200 + ds_write_b32 v82, a24 offset:20480 + ds_write_b32 v82, a25 offset:20736 + ds_write_b32 v82, a26 offset:20992 + ds_write_b32 v82, a27 offset:21248 + ds_write_b32 v82, a28 offset:22528 + ds_write_b32 v82, a29 offset:22784 + ds_write_b32 v82, a30 offset:23040 + ds_write_b32 v82, a31 offset:23296 + ds_write_b32 v82, a32 offset:32768 + ds_write_b32 v82, a33 offset:33024 + ds_write_b32 v82, a34 offset:33280 + ds_write_b32 v82, a35 offset:33536 + ds_write_b32 v82, a36 offset:34816 + ds_write_b32 v82, a37 offset:35072 + ds_write_b32 v82, a38 offset:35328 + ds_write_b32 v82, a39 offset:35584 + ds_write_b32 v82, a40 offset:36864 + ds_write_b32 v82, a41 offset:37120 + ds_write_b32 v82, a42 offset:37376 + ds_write_b32 v82, a43 offset:37632 + ds_write_b32 v82, a44 offset:38912 + ds_write_b32 v82, a45 offset:39168 + ds_write_b32 v82, a46 offset:39424 + ds_write_b32 v82, a47 offset:39680 + ds_write2st64_b32 v82, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v82, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v82, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v82, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v82, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v82, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v82, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v82, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[2:5], v83 + ds_read_b128 v[6:9], v83 offset:256 + ds_read_b128 v[10:13], v83 offset:512 + ds_read_b128 v[14:17], v83 offset:768 + ds_read_b128 v[18:21], v83 offset:1024 + ds_read_b128 v[22:25], v83 offset:1280 + ds_read_b128 v[26:29], v83 offset:1536 + ds_read_b128 v[30:33], v83 offset:1792 + ds_read_b128 v[34:37], v83 offset:2048 + ds_read_b128 v[38:41], v83 offset:2304 + ds_read_b128 v[42:45], v83 offset:2560 + ds_read_b128 v[46:49], v83 offset:2816 + ds_read_b128 v[50:53], v83 offset:3072 + ds_read_b128 v[54:57], v83 offset:3328 + ds_read_b128 v[58:61], v83 offset:3584 + ds_read_b128 v[62:65], v83 offset:3840 + v_add_u32_e32 v0, 0xc0, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[2:5], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + buffer_store_dwordx4 v[6:9], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[10:13], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[14:17], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[26:29], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[30:33], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[34:37], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[38:41], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[42:45], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[46:49], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[50:53], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[54:57], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[58:61], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 440 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 184 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end35: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end35-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 184 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 30 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorENSE_8RowMajorESG_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 30352 +; TotalNumSgprs: 36 +; NumVgprs: 184 +; NumAgprs: 256 +; TotalNumVgprs: 440 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 54 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 440 +; AccumOffset: 184 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 45 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v6, 0 + global_load_ushort v1, v6, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v2, s3 + v_rcp_iflag_f32_e32 v2, v2 + s_nop 0 + v_mul_f32_e32 v2, 0x4f7ffffe, v2 + v_cvt_u32_f32_e32 v2, v2 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v3, s8, v2 + v_mul_hi_u32 v3, v2, v3 + v_add_u32_e32 v4, v2, v3 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v1, s2, v1 + v_add_u32_e32 v2, v1, v0 + v_xor_b32_e32 v0, s5, v2 + v_sub_u32_e32 v1, 0, v2 + v_ashrrev_i32_e32 v3, 31, v0 + v_max_i32_e32 v0, v2, v1 + v_mul_hi_u32 v1, v0, v4 + v_mul_lo_u32 v4, v1, s3 + v_add_u32_e32 v5, 1, v1 + v_sub_u32_e32 v0, v0, v4 + v_cmp_le_u32_e32 vcc, s3, v0 + s_nop 1 + v_cndmask_b32_e32 v1, v1, v5, vcc + v_subrev_u32_e32 v4, s3, v0 + v_cndmask_b32_e32 v0, v0, v4, vcc + v_add_u32_e32 v4, 1, v1 + v_cmp_le_u32_e32 vcc, s3, v0 + s_nop 1 + v_cndmask_b32_e32 v0, v1, v4, vcc + v_xor_b32_e32 v4, v0, v3 + v_sub_u32_e32 v1, v4, v3 + v_cmp_gt_i32_e32 vcc, s4, v1 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB36_12 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v5, v1, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v2, v5 + s_cbranch_scc1 .LBB36_11 +; %bb.2: ; %.lr.ph.preheader + s_cmp_eq_u32 s6, 1 + s_cselect_b64 s[0:1], -1, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB36_8 +; %bb.3: ; %vector.scevcheck + s_cmp_eq_u32 s7, 1 + s_cselect_b64 s[0:1], -1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_eq_u32 s2, 1 + s_cselect_b64 s[4:5], -1, 0 + s_and_b64 s[0:1], s[0:1], s[4:5] + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccz .LBB36_7 +; %bb.4: ; %vector.ph + s_and_b32 s4, s6, 0x7ffffffe + s_mov_b32 s0, 0 + v_mov_b32_e32 v6, 0 + v_mov_b32_e32 v7, 0 +.LBB36_5: ; %vector.body + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v8, s0, v1 + v_add_u32_e32 v10, s0, v0 + v_ashrrev_i32_e32 v9, 31, v8 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshl_add_u64 v[8:9], s[8:9], 0, v[8:9] + v_lshl_add_u64 v[10:11], s[10:11], 0, v[10:11] + global_load_ushort v12, v[8:9], off + global_load_ushort v13, v[10:11], off + s_add_i32 s0, s0, 2 + s_cmp_lg_u32 s0, s4 + s_waitcnt vmcnt(1) + v_lshrrev_b16_e32 v8, 8, v12 + v_bfe_i32 v9, v12, 0, 8 + s_waitcnt vmcnt(0) + v_lshrrev_b16_e32 v10, 8, v13 + v_bfe_i32 v11, v13, 0, 8 + v_bfe_i32 v8, v8, 0, 8 + v_bfe_i32 v10, v10, 0, 8 + v_mad_i32_i24 v6, v11, v9, v6 + v_mad_i32_i24 v7, v10, v8, v7 + s_cbranch_scc1 .LBB36_5 +; %bb.6: ; %middle.block + v_add_u32_e32 v6, v6, v7 + s_cmp_lg_u32 s6, s4 + s_cselect_b64 s[0:1], -1, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB36_9 + s_branch .LBB36_11 +.LBB36_7: + s_mov_b64 s[0:1], -1 +.LBB36_8: ; %Flow82 + s_mov_b32 s4, 0 + v_mov_b32_e32 v6, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccz .LBB36_11 +.LBB36_9: ; %.lr.ph.preheader40 + s_sub_i32 s0, s6, s4 + s_waitcnt lgkmcnt(0) + s_mul_i32 s1, s4, s2 + v_add_u32_e32 v2, s1, v2 + v_sub_u32_e32 v2, v2, v5 + s_mul_i32 s1, s4, s7 + v_add_u32_e32 v4, s1, v4 + v_sub_u32_e32 v4, v4, v3 +.LBB36_10: ; %.lr.ph + ; =>This Inner Loop Header: Depth=1 + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[8:9], 0, v[4:5] + global_load_sbyte v5, v[8:9], off + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[2:3] + global_load_sbyte v3, v[8:9], off + s_add_i32 s0, s0, -1 + v_add_u32_e32 v2, s2, v2 + s_cmp_eq_u32 s0, 0 + s_waitcnt vmcnt(0) + v_mad_i32_i24 v6, v3, v5, v6 + v_add_u32_e32 v4, s7, v4 + s_cbranch_scc0 .LBB36_10 +.LBB36_11: ; %._crit_edge + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[0:1], s[0:1], v1, s3, v[0:1] + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] + global_store_dword v[0:1], v6, off +.LBB36_12: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 14 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 16 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end36: + .size _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end36-_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm11ColumnMajorENS2_8RowMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 664 +; TotalNumSgprs: 20 +; NumVgprs: 14 +; NumAgprs: 0 +; TotalNumVgprs: 14 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 14 +; AccumOffset: 16 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 3 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_sub_i32 s2, s2, s13 + s_waitcnt lgkmcnt(0) + s_abs_i32 s13, s17 + v_cvt_f32_u32_e32 v1, s13 + s_lshl_b32 s20, s12, 8 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s12, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s12 + s_sub_i32 s15, 0, s13 + v_readfirstlane_b32 s18, v1 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s13 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s13 + s_cmp_ge_u32 s14, s13 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s12, s12, s14 + s_xor_b32 s15, s12, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s12, s12 + s_mul_hi_u32 s18, s12, s18 + s_mul_i32 s19, s18, s13 + s_sub_i32 s12, s12, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s12, s13 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s12, s23, s12 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s12, s13 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s18, s18, s15 + s_sub_i32 s6, s6, s18 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s8, s8, s18 + s_addc_u32 s9, s9, s2 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s3, s3, 1 + s_add_u32 s10, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s22, s2 + s_add_u32 s14, s2, s3 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[18:19], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[18:19] + s_nop 0 + v_readfirstlane_b32 s11, v1 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v4, -1, 0 + s_cbranch_scc0 .LBB37_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + v_mbcnt_hi_u32_b32 v1, -1, v4 + v_lshlrev_b32_e32 v2, 4, v1 + v_and_b32_e32 v2, 48, v2 + v_and_b32_e32 v3, 0x7c, v1 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v5, s11, v3 + v_add_u32_e32 v3, s20, v5 + v_mad_u64_u32 v[6:7], s[18:19], v3, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[26:29], v6, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v6 + buffer_load_dwordx4 v[32:35], v3, s[8:11], 0 offen + v_and_b32_e32 v6, 31, v1 + v_add_u32_e32 v7, s7, v3 + buffer_load_dwordx4 v[36:39], v7, s[8:11], 0 offen + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v3, 3, v1 + v_lshrrev_b32_e32 v8, 5, v1 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s23, s18, 0x3fffffe0 + v_and_or_b32 v56, v3, 8, v8 + s_and_b32 s18, s19, 32 + v_or_b32_e32 v57, s23, v6 + v_add_u32_e32 v3, s21, v5 + v_or_b32_e32 v6, s18, v6 + v_lshrrev_b32_e32 v8, 3, v2 + v_ashrrev_i32_e32 v9, 1, v5 + v_ashrrev_i32_e32 v10, 31, v5 + v_lshlrev_b32_e32 v11, 6, v5 + v_or_b32_e32 v12, 1, v5 + v_lshrrev_b32_e32 v13, 31, v5 + v_lshrrev_b32_e32 v14, 1, v57 + v_bfe_u32 v15, v57, 1, 4 + v_mad_u64_u32 v[2:3], s[24:25], v3, s22, v[2:3] + v_add_u32_e32 v3, s7, v7 + buffer_load_dwordx4 v[40:43], v3, s[8:11], 0 offen + v_lshrrev_b32_e32 v16, 1, v6 + v_bfe_u32 v22, v6, 1, 4 + v_lshrrev_b32_e32 v3, 28, v10 + v_or_b32_e32 v6, 1, v8 + buffer_load_dwordx4 v[44:47], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[48:51], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[52:55], v2, s[12:15], 0 offen + v_add_u32_e32 v2, s22, v2 + buffer_load_dwordx4 v[58:61], v2, s[12:15], 0 offen + v_add_u32_e32 v2, v12, v13 + v_or_b32_e32 v7, 1, v9 + v_xor_b32_e32 v10, v15, v56 + v_lshlrev_b32_e32 v17, 7, v14 + v_xor_b32_e32 v30, v22, v56 + v_lshlrev_b32_e32 v18, 7, v16 + v_add_u32_e32 v19, v9, v3 + v_sub_u32_e32 v20, v8, v6 + v_ashrrev_i32_e32 v21, 1, v2 + v_and_b32_e32 v23, 0x1ffffffe, v2 + v_ashrrev_i32_e32 v2, 31, v2 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v24, v21, v9 + v_sub_u32_e32 v12, v12, v23 + v_lshrrev_b32_e32 v2, 28, v2 + v_sub_u32_e32 v9, v9, v19 + v_lshl_or_b32 v12, v12, 3, v6 + v_add_u32_e32 v2, v21, v2 + v_xor_b32_e32 v19, v9, v8 + v_xor_b32_e32 v9, v9, v6 + v_add_u32_e32 v23, v12, v20 + v_and_b32_e32 v2, -16, v2 + v_lshl_add_u32 v19, v19, 3, v11 + v_lshl_add_u32 v11, v9, 3, v11 + v_sub_u32_e32 v2, v21, v2 + v_xor_b32_e32 v23, v23, v2 + v_lshl_add_u32 v24, v24, 7, v11 + v_xor_b32_e32 v2, v12, v2 + v_sub_u32_e32 v12, v23, v9 + v_sub_u32_e32 v9, v2, v9 + v_lshl_add_u32 v12, v12, 3, v24 + v_lshl_add_u32 v9, v9, 3, v24 + s_waitcnt vmcnt(7) + ds_write_b64 v19, v[26:27] + ds_write_b64 v11, v[28:29] + s_waitcnt vmcnt(6) + ds_write_b64 v12, v[32:33] + ds_write_b64 v9, v[34:35] + v_sub_u32_e32 v21, v7, v21 + v_add_u32_e32 v3, v7, v3 + v_and_b32_e32 v3, -16, v3 + v_sub_u32_e32 v3, v7, v3 + v_xor_b32_e32 v8, v3, v8 + v_sub_u32_e32 v2, v8, v2 + v_lshlrev_b32_e32 v2, 3, v2 + v_lshlrev_b32_e32 v21, 7, v21 + v_add3_u32 v2, v2, v21, v9 + s_waitcnt vmcnt(5) + ds_write_b64 v2, v[36:37] + v_xor_b32_e32 v3, v3, v6 + v_sub_u32_e32 v8, v3, v8 + v_lshl_add_u32 v8, v8, 3, v2 + ds_write_b64 v8, v[38:39] + v_or_b32_e32 v5, 3, v5 + v_add_u32_e32 v13, v5, v13 + v_ashrrev_i32_e32 v21, 1, v13 + v_sub_u32_e32 v7, v21, v7 + v_and_b32_e32 v23, 0x1ffffffe, v13 + v_sub_u32_e32 v5, v5, v23 + v_lshl_or_b32 v5, v5, 3, v6 + v_add_u32_e32 v6, v5, v20 + v_ashrrev_i32_e32 v13, 31, v13 + v_lshrrev_b32_e32 v13, 28, v13 + v_add_u32_e32 v13, v21, v13 + v_and_b32_e32 v13, -16, v13 + v_sub_u32_e32 v13, v21, v13 + v_xor_b32_e32 v6, v6, v13 + v_sub_u32_e32 v3, v6, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_lshlrev_b32_e32 v7, 7, v7 + v_add3_u32 v3, v3, v7, v8 + s_waitcnt vmcnt(4) + ds_write_b64 v3, v[40:41] + v_xor_b32_e32 v5, v5, v13 + v_sub_u32_e32 v5, v5, v6 + v_lshl_add_u32 v5, v5, 3, v3 + ds_write_b64 v5, v[42:43] + s_waitcnt vmcnt(3) + ds_write_b64 v19, v[44:45] offset:16384 + ds_write_b64 v11, v[46:47] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v12, v[48:49] offset:16384 + ds_write_b64 v9, v[50:51] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v2, v[52:53] offset:16384 + ds_write_b64 v8, v[54:55] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v3, v[58:59] offset:16384 + ds_write_b64 v5, v[60:61] offset:16384 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v2, v10, 3, v17 + v_add_u32_e32 v5, 2, v56 + v_xor_b32_e32 v3, v5, v15 + v_lshl_add_u32 v3, v3, 3, v17 + v_or_b32_e32 v58, 4, v56 + v_xor_b32_e32 v6, v58, v15 + v_lshl_add_u32 v10, v6, 3, v17 + v_add_u32_e32 v59, 6, v56 + v_xor_b32_e32 v46, v59, v15 + v_lshl_add_u32 v12, v46, 3, v17 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[8:9], v3 + ds_read_b64 v[10:11], v10 + ds_read_b64 v[2:3], v12 + v_add_u32_e32 v13, 64, v57 + v_lshrrev_b32_e32 v50, 1, v13 + v_sub_u32_e32 v14, v50, v14 + v_bfe_u32 v47, v13, 1, 4 + v_xor_b32_e32 v13, v47, v56 + v_sub_u32_e32 v13, v13, v46 + v_lshl_add_u32 v48, v14, 7, v12 + v_lshl_add_u32 v12, v13, 3, v48 + ds_read_b64 v[12:13], v12 + v_xor_b32_e32 v14, v47, v5 + v_sub_u32_e32 v14, v14, v46 + v_lshl_add_u32 v49, v14, 3, v48 + v_xor_b32_e32 v14, v47, v58 + v_sub_u32_e32 v14, v14, v46 + v_lshl_add_u32 v51, v14, 3, v48 + v_lshl_or_b32 v14, v30, 3, v18 + v_add_u32_e32 v15, -16, v16 + s_cmp_eq_u32 s18, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v15, v15, v16, vcc + v_xor_b32_e32 v16, v15, v5 + v_lshl_add_u32 v16, v16, 3, v18 + v_xor_b32_e32 v17, v15, v58 + v_lshl_add_u32 v19, v17, 3, v18 + v_xor_b32_e32 v23, v15, v59 + v_lshl_add_u32 v24, v23, 3, v18 + ds_read_b64 v[14:15], v14 offset:16384 + ds_read_b64 v[16:17], v16 offset:16384 + ds_read_b64 v[18:19], v19 offset:16384 + ds_read_b64 v[20:21], v24 offset:16384 + v_sub_u32_e32 v23, v30, v23 + v_lshl_add_u32 v23, v23, 3, v24 + v_xor_b32_e32 v24, v22, v5 + v_sub_u32_e32 v24, v24, v30 + v_lshlrev_b32_e32 v40, 3, v24 + v_add_u32_e32 v24, v23, v40 + v_xor_b32_e32 v25, v22, v58 + v_sub_u32_e32 v25, v25, v30 + v_lshlrev_b32_e32 v41, 3, v25 + v_add_u32_e32 v26, v23, v41 + v_xor_b32_e32 v31, v22, v59 + v_sub_u32_e32 v22, v31, v30 + v_lshlrev_b32_e32 v42, 3, v22 + v_add_u32_e32 v32, v23, v42 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[176:191], v[6:7], v[14:15], 0 + ds_read_b64 v[22:23], v23 offset:20480 + ds_read_b64 v[24:25], v24 offset:20480 + ds_read_b64 v[26:27], v26 offset:20480 + ds_read_b64 v[28:29], v32 offset:20480 + v_sub_u32_e32 v30, v30, v31 + v_lshlrev_b32_e32 v38, 3, v30 + v_add_u32_e32 v30, v32, v38 + v_add_u32_e32 v32, v30, v40 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[112:127], v[6:7], v[22:23], 0 + v_add_u32_e32 v34, v30, v41 + v_add_u32_e32 v39, v30, v42 + ds_read_b64 v[30:31], v30 offset:24576 + ds_read_b64 v[32:33], v32 offset:24576 + ds_read_b64 v[34:35], v34 offset:24576 + ds_read_b64 v[36:37], v39 offset:24576 + v_add_u32_e32 v43, v39, v38 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[48:63], v[6:7], v[30:31], 0 + ds_read_b64 v[38:39], v43 offset:28672 + v_add_u32_e32 v40, v43, v40 + v_add_u32_e32 v44, v43, v41 + v_add_u32_e32 v45, v43, v42 + ds_read_b64 v[40:41], v40 offset:28672 + ds_read_b64 v[42:43], v44 offset:28672 + ds_read_b64 v[44:45], v45 offset:28672 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[0:15], v[6:7], v[38:39], 0 + v_xor_b32_e32 v52, v47, v59 + v_sub_u32_e32 v6, v52, v46 + v_lshlrev_b32_e32 v6, 3, v6 + v_add_u32_e32 v60, v6, v48 + ds_read_b64 v[6:7], v49 + ds_read_b64 v[46:47], v51 + ds_read_b64 v[48:49], v60 + v_mfma_i32_32x32x16_i8 a[192:207], v[12:13], v[14:15], 0 + v_add_u32_e32 v51, 0x80, v57 + v_lshrrev_b32_e32 v61, 1, v51 + v_mfma_i32_32x32x16_i8 a[128:143], v[12:13], v[22:23], 0 + v_sub_u32_e32 v50, v61, v50 + v_bfe_u32 v53, v51, 1, 4 + v_xor_b32_e32 v54, v53, v56 + v_sub_u32_e32 v51, v54, v52 + v_lshlrev_b32_e32 v50, 7, v50 + v_lshl_add_u32 v62, v51, 3, v50 + v_add_u32_e32 v52, v60, v62 + v_mfma_i32_32x32x16_i8 a[64:79], v[12:13], v[30:31], 0 + ds_read_b64 v[50:51], v52 + v_xor_b32_e32 v55, v53, v5 + v_sub_u32_e32 v55, v55, v54 + v_lshl_add_u32 v55, v55, 3, v52 + v_xor_b32_e32 v63, v53, v58 + v_sub_u32_e32 v63, v63, v54 + v_lshl_add_u32 v63, v63, 3, v52 + v_mfma_i32_32x32x16_i8 a[16:31], v[12:13], v[38:39], 0 + v_xor_b32_e32 v64, v53, v59 + v_sub_u32_e32 v12, v64, v54 + v_lshlrev_b32_e32 v65, 3, v12 + v_add_u32_e32 v54, v52, v65 + ds_read_b64 v[12:13], v55 + ds_read_b64 v[52:53], v63 + ds_read_b64 v[54:55], v54 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[208:223], v[50:51], v[14:15], 0 + v_add3_u32 v60, v62, v60, v65 + v_add_u32_e32 v57, 0xc0, v57 + v_mfma_i32_32x32x16_i8 a[144:159], v[50:51], v[22:23], 0 + v_lshrrev_b32_e32 v62, 1, v57 + v_sub_u32_e32 v61, v62, v61 + v_bfe_u32 v62, v57, 1, 4 + v_xor_b32_e32 v63, v62, v56 + v_sub_u32_e32 v56, v63, v64 + v_lshlrev_b32_e32 v56, 3, v56 + v_lshlrev_b32_e32 v57, 7, v61 + v_mfma_i32_32x32x16_i8 a[80:95], v[50:51], v[30:31], 0 + v_add3_u32 v60, v56, v57, v60 + ds_read_b64 v[56:57], v60 + v_xor_b32_e32 v5, v62, v5 + v_sub_u32_e32 v5, v5, v63 + v_lshl_add_u32 v5, v5, 3, v60 + v_xor_b32_e32 v58, v62, v58 + v_sub_u32_e32 v58, v58, v63 + v_mfma_i32_32x32x16_i8 a[32:47], v[50:51], v[38:39], 0 + v_lshl_add_u32 v58, v58, 3, v60 + v_xor_b32_e32 v50, v62, v59 + v_sub_u32_e32 v50, v50, v63 + v_lshl_add_u32 v60, v50, 3, v60 + ds_read_b64 v[50:51], v5 + ds_read_b64 v[58:59], v58 + ds_read_b64 v[60:61], v60 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[224:239], v[56:57], v[14:15], 0 + v_mfma_i32_32x32x16_i8 a[160:175], v[56:57], v[22:23], 0 + v_mfma_i32_32x32x16_i8 a[96:111], v[56:57], v[30:31], 0 + v_mfma_i32_32x32x16_i8 a[240:255], v[56:57], v[38:39], 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[8:9], v[16:17], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[8:9], v[24:25], a[112:127] + v_mfma_i32_32x32x16_i8 a[48:63], v[8:9], v[32:33], a[48:63] + v_mfma_i32_32x32x16_i8 a[0:15], v[8:9], v[40:41], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[6:7], v[16:17], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[6:7], v[24:25], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[6:7], v[32:33], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[6:7], v[40:41], a[16:31] + v_mfma_i32_32x32x16_i8 a[208:223], v[12:13], v[16:17], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[12:13], v[24:25], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[12:13], v[32:33], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[12:13], v[40:41], a[32:47] + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[224:239], v[50:51], v[16:17], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[50:51], v[24:25], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[50:51], v[32:33], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[50:51], v[40:41], a[240:255] + v_mfma_i32_32x32x16_i8 a[176:191], v[10:11], v[18:19], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[10:11], v[26:27], a[112:127] + v_mfma_i32_32x32x16_i8 a[48:63], v[10:11], v[34:35], a[48:63] + v_mfma_i32_32x32x16_i8 a[0:15], v[10:11], v[42:43], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[46:47], v[18:19], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[46:47], v[26:27], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[46:47], v[34:35], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[46:47], v[42:43], a[16:31] + v_mfma_i32_32x32x16_i8 a[208:223], v[52:53], v[18:19], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[52:53], v[26:27], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[52:53], v[34:35], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[52:53], v[42:43], a[32:47] + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[224:239], v[58:59], v[18:19], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[58:59], v[26:27], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[58:59], v[34:35], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[58:59], v[42:43], a[240:255] + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[20:21], a[176:191] + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[28:29], a[112:127] + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[36:37], a[48:63] + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[44:45], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[48:49], v[20:21], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[48:49], v[28:29], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[48:49], v[36:37], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[48:49], v[44:45], a[16:31] + v_mfma_i32_32x32x16_i8 a[208:223], v[54:55], v[20:21], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[54:55], v[28:29], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[54:55], v[36:37], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[54:55], v[44:45], a[32:47] + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[60:61], v[20:21], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[60:61], v[28:29], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[60:61], v[36:37], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[60:61], v[44:45], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB37_3 + s_branch .LBB37_10 +.LBB37_2: + ; implicit-def: $agpr111 + ; implicit-def: $agpr175 + ; implicit-def: $agpr239 + ; implicit-def: $agpr47 + ; implicit-def: $agpr95 + ; implicit-def: $agpr159 + ; implicit-def: $agpr223 + ; implicit-def: $agpr31 + ; implicit-def: $agpr79 + ; implicit-def: $agpr143 + ; implicit-def: $agpr207 + ; implicit-def: $agpr15 + ; implicit-def: $agpr63 + ; implicit-def: $agpr127 + ; implicit-def: $agpr191 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr1 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB37_3: + s_mov_b32 s11, s7 + v_readfirstlane_b32 s15, v0 + v_mbcnt_hi_u32_b32 v1, -1, v4 + v_lshlrev_b32_e32 v2, 4, v1 + v_and_b32_e32 v4, 48, v2 + s_and_b32 s18, s15, 0xffffffc0 + v_and_b32_e32 v54, 0x7c, v1 + v_add_u32_e32 v13, s18, v54 + v_add_u32_e32 v2, s20, v13 + v_mad_u64_u32 v[2:3], s[18:19], v2, s11, v[4:5] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[26:29], v2, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v2 + buffer_load_dwordx4 v[30:33], v3, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[34:37], v3, s[8:11], 0 offen + v_lshrrev_b32_e32 v5, 5, v1 + v_and_b32_e32 v6, 31, v1 + s_lshr_b32 s18, s15, 2 + v_lshlrev_b32_e32 v7, 3, v1 + s_lshr_b32 s19, s15, 1 + s_mov_b32 s15, s11 + s_and_b32 s18, s18, 0x3fffffe0 + v_and_or_b32 v7, v7, 8, v5 + v_and_or_b32 v5, s19, 32, v6 + v_or_b32_e32 v8, s18, v6 + v_add_u32_e32 v9, s21, v13 + v_lshrrev_b32_e32 v12, 1, v5 + v_bfe_u32 v6, v5, 1, 4 + v_lshrrev_b32_e32 v55, 3, v4 + v_ashrrev_i32_e32 v14, 1, v13 + v_ashrrev_i32_e32 v15, 31, v13 + v_lshlrev_b32_e32 v16, 6, v13 + v_or_b32_e32 v17, 1, v13 + v_lshrrev_b32_e32 v18, 31, v13 + v_lshrrev_b32_e32 v10, 1, v8 + v_bfe_u32 v11, v8, 1, 4 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[38:41], v3, s[8:11], 0 offen + v_mad_u64_u32 v[4:5], s[18:19], v9, s22, v[4:5] + v_xor_b32_e32 v5, v6, v7 + v_lshlrev_b32_e32 v9, 7, v12 + buffer_load_dwordx4 v[42:45], v4, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v4 + buffer_load_dwordx4 v[46:49], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[50:53], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[58:61], v3, s[12:15], 0 offen + v_lshrrev_b32_e32 v15, 28, v15 + v_or_b32_e32 v56, 1, v55 + v_add_u32_e32 v19, v17, v18 + v_or_b32_e32 v20, 1, v14 + v_xor_b32_e32 v3, v11, v7 + v_lshlrev_b32_e32 v12, 7, v10 + v_add_u32_e32 v21, v14, v15 + v_sub_u32_e32 v57, v55, v56 + v_ashrrev_i32_e32 v22, 1, v19 + v_and_b32_e32 v23, 0x1ffffffe, v19 + v_ashrrev_i32_e32 v19, 31, v19 + v_and_b32_e32 v21, -16, v21 + v_sub_u32_e32 v24, v22, v14 + v_sub_u32_e32 v17, v17, v23 + v_lshrrev_b32_e32 v19, 28, v19 + v_sub_u32_e32 v14, v14, v21 + v_lshl_or_b32 v17, v17, 3, v56 + v_add_u32_e32 v19, v22, v19 + v_xor_b32_e32 v21, v14, v55 + v_xor_b32_e32 v14, v14, v56 + v_add_u32_e32 v23, v17, v57 + v_and_b32_e32 v19, -16, v19 + v_lshl_add_u32 v21, v21, 3, v16 + v_lshl_add_u32 v16, v14, 3, v16 + v_sub_u32_e32 v19, v22, v19 + v_xor_b32_e32 v23, v23, v19 + v_lshl_add_u32 v24, v24, 7, v16 + v_xor_b32_e32 v17, v17, v19 + v_sub_u32_e32 v19, v23, v14 + v_sub_u32_e32 v14, v17, v14 + v_lshl_add_u32 v19, v19, 3, v24 + v_lshl_add_u32 v14, v14, 3, v24 + s_waitcnt vmcnt(7) + ds_write_b64 v21, v[26:27] + ds_write_b64 v16, v[28:29] + s_waitcnt vmcnt(6) + ds_write_b64 v19, v[30:31] + ds_write_b64 v14, v[32:33] + v_sub_u32_e32 v22, v20, v22 + v_add_u32_e32 v15, v20, v15 + v_and_b32_e32 v15, -16, v15 + v_sub_u32_e32 v15, v20, v15 + v_xor_b32_e32 v23, v15, v55 + v_sub_u32_e32 v17, v23, v17 + v_lshlrev_b32_e32 v17, 3, v17 + v_lshlrev_b32_e32 v22, 7, v22 + v_add3_u32 v17, v17, v22, v14 + s_waitcnt vmcnt(5) + ds_write_b64 v17, v[34:35] + v_xor_b32_e32 v15, v15, v56 + v_sub_u32_e32 v22, v15, v23 + v_lshl_add_u32 v22, v22, 3, v17 + ds_write_b64 v22, v[36:37] + v_or_b32_e32 v13, 3, v13 + v_add_u32_e32 v18, v13, v18 + v_ashrrev_i32_e32 v23, 1, v18 + v_sub_u32_e32 v20, v23, v20 + v_and_b32_e32 v24, 0x1ffffffe, v18 + v_sub_u32_e32 v13, v13, v24 + v_lshl_or_b32 v13, v13, 3, v56 + v_add_u32_e32 v24, v13, v57 + v_ashrrev_i32_e32 v18, 31, v18 + v_lshrrev_b32_e32 v18, 28, v18 + v_add_u32_e32 v18, v23, v18 + v_and_b32_e32 v18, -16, v18 + v_sub_u32_e32 v18, v23, v18 + v_xor_b32_e32 v23, v24, v18 + v_sub_u32_e32 v15, v23, v15 + v_lshlrev_b32_e32 v15, 3, v15 + v_lshlrev_b32_e32 v20, 7, v20 + v_add3_u32 v15, v15, v20, v22 + s_waitcnt vmcnt(4) + ds_write_b64 v15, v[38:39] + v_xor_b32_e32 v13, v13, v18 + v_sub_u32_e32 v13, v13, v23 + v_lshl_add_u32 v13, v13, 3, v15 + ds_write_b64 v13, v[40:41] + s_waitcnt vmcnt(3) + ds_write_b64 v21, v[42:43] offset:16384 + ds_write_b64 v16, v[44:45] offset:16384 + s_waitcnt vmcnt(2) + ds_write_b64 v19, v[46:47] offset:16384 + ds_write_b64 v14, v[48:49] offset:16384 + s_waitcnt vmcnt(1) + ds_write_b64 v17, v[50:51] offset:16384 + ds_write_b64 v22, v[52:53] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v15, v[58:59] offset:16384 + ds_write_b64 v13, v[60:61] offset:16384 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v15, 2, v7 + v_add_u32_e32 v14, 4, v7 + v_add_u32_e32 v13, 6, v7 + v_add_u32_e32 v16, 64, v8 + s_cbranch_vccnz .LBB37_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit993.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v17, v15, v11 + v_lshl_add_u32 v27, v17, 3, v12 + v_xor_b32_e32 v17, v14, v11 + v_lshl_add_u32 v24, v17, 3, v12 + v_xor_b32_e32 v17, v13, v11 + v_lshl_add_u32 v22, v17, 3, v12 + v_lshrrev_b32_e32 v18, 1, v16 + v_sub_u32_e32 v19, v18, v10 + v_bfe_u32 v20, v16, 1, 4 + v_xor_b32_e32 v21, v20, v7 + v_sub_u32_e32 v21, v21, v17 + v_lshl_add_u32 v19, v19, 7, v22 + v_lshl_add_u32 v48, v21, 3, v19 + v_xor_b32_e32 v21, v20, v15 + v_sub_u32_e32 v21, v21, v17 + v_lshl_add_u32 v30, v21, 3, v19 + v_xor_b32_e32 v21, v20, v14 + v_sub_u32_e32 v21, v21, v17 + v_lshl_add_u32 v26, v21, 3, v19 + v_xor_b32_e32 v20, v20, v13 + v_sub_u32_e32 v17, v20, v17 + v_lshl_add_u32 v23, v17, 3, v19 + v_add_u32_e32 v17, 0x80, v8 + v_lshrrev_b32_e32 v19, 1, v17 + v_sub_u32_e32 v18, v19, v18 + v_bfe_u32 v17, v17, 1, 4 + v_xor_b32_e32 v21, v17, v7 + v_sub_u32_e32 v20, v21, v20 + v_lshlrev_b32_e32 v20, 3, v20 + v_lshlrev_b32_e32 v18, 7, v18 + v_add3_u32 v47, v20, v18, v23 + v_xor_b32_e32 v18, v17, v15 + v_sub_u32_e32 v18, v18, v21 + v_lshl_add_u32 v32, v18, 3, v47 + v_xor_b32_e32 v18, v17, v14 + v_sub_u32_e32 v18, v18, v21 + v_lshl_add_u32 v29, v18, 3, v47 + v_xor_b32_e32 v17, v17, v13 + v_sub_u32_e32 v18, v17, v21 + v_lshl_add_u32 v25, v18, 3, v47 + v_add_u32_e32 v18, 0xc0, v8 + v_lshrrev_b32_e32 v20, 1, v18 + v_sub_u32_e32 v19, v20, v19 + v_bfe_u32 v18, v18, 1, 4 + v_xor_b32_e32 v20, v18, v7 + v_sub_u32_e32 v17, v20, v17 + v_lshlrev_b32_e32 v17, 3, v17 + v_lshlrev_b32_e32 v19, 7, v19 + v_add3_u32 v46, v17, v19, v25 + v_xor_b32_e32 v17, v18, v15 + v_sub_u32_e32 v17, v17, v20 + v_lshl_add_u32 v34, v17, 3, v46 + v_xor_b32_e32 v17, v18, v14 + v_sub_u32_e32 v17, v17, v20 + v_lshl_add_u32 v31, v17, 3, v46 + v_xor_b32_e32 v17, v18, v13 + v_sub_u32_e32 v17, v17, v20 + v_lshl_add_u32 v28, v17, 3, v46 + v_xor_b32_e32 v17, v6, v15 + v_lshl_add_u32 v40, v17, 3, v9 + v_xor_b32_e32 v18, v6, v14 + v_lshl_add_u32 v36, v18, 3, v9 + v_xor_b32_e32 v19, v6, v13 + v_lshl_add_u32 v33, v19, 3, v9 + v_sub_u32_e32 v20, v5, v19 + v_mov_b32_e32 v21, 0x1000 + v_lshl_add_u32 v20, v20, 3, v21 + v_add_u32_e32 v50, v20, v33 + v_sub_u32_e32 v17, v17, v5 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v43, v50, v17 + v_sub_u32_e32 v18, v18, v5 + v_lshlrev_b32_e32 v18, 3, v18 + v_add_u32_e32 v39, v50, v18 + v_sub_u32_e32 v19, v19, v5 + v_lshlrev_b32_e32 v19, 3, v19 + v_add_u32_e32 v35, v50, v19 + v_add_u32_e32 v51, v35, v20 + v_add_u32_e32 v44, v51, v17 + v_add_u32_e32 v41, v51, v18 + v_add_u32_e32 v37, v51, v19 + v_add_u32_e32 v49, v37, v20 + v_add_u32_e32 v45, v49, v17 + v_add_u32_e32 v42, v49, v18 + v_add_u32_e32 v38, v49, v19 + s_mov_b64 s[2:3], 0 + s_branch .LBB37_6 +.LBB37_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr27 + ; implicit-def: $vgpr24 + ; implicit-def: $vgpr22 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr30 + ; implicit-def: $vgpr26 + ; implicit-def: $vgpr23 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr32 + ; implicit-def: $vgpr29 + ; implicit-def: $vgpr25 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr34 + ; implicit-def: $vgpr31 + ; implicit-def: $vgpr28 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr33 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr35 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr38 +.LBB37_6: ; %Flow80 + v_lshl_or_b32 v53, v3, 3, v12 + v_lshl_or_b32 v52, v5, 3, v9 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + s_cbranch_vccnz .LBB37_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.lr.ph.i.i.i.i.i.i.i + v_mov_b32_e32 v3, v4 + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v4, v15, v11 + v_lshl_add_u32 v27, v4, 3, v12 + v_xor_b32_e32 v4, v14, v11 + v_lshl_add_u32 v24, v4, 3, v12 + v_xor_b32_e32 v4, v13, v11 + v_lshl_add_u32 v22, v4, 3, v12 + v_lshrrev_b32_e32 v11, 1, v16 + v_sub_u32_e32 v10, v11, v10 + v_bfe_u32 v12, v16, 1, 4 + v_xor_b32_e32 v16, v12, v7 + v_sub_u32_e32 v16, v16, v4 + v_lshl_add_u32 v10, v10, 7, v22 + v_lshl_add_u32 v48, v16, 3, v10 + v_xor_b32_e32 v16, v12, v15 + v_sub_u32_e32 v16, v16, v4 + v_lshl_add_u32 v30, v16, 3, v10 + v_xor_b32_e32 v16, v12, v14 + v_sub_u32_e32 v16, v16, v4 + v_lshl_add_u32 v26, v16, 3, v10 + v_xor_b32_e32 v12, v12, v13 + v_sub_u32_e32 v4, v12, v4 + v_lshl_add_u32 v23, v4, 3, v10 + v_add_u32_e32 v4, 0x80, v8 + v_lshrrev_b32_e32 v10, 1, v4 + v_sub_u32_e32 v11, v10, v11 + v_bfe_u32 v4, v4, 1, 4 + v_xor_b32_e32 v16, v4, v7 + v_sub_u32_e32 v12, v16, v12 + v_lshlrev_b32_e32 v12, 3, v12 + v_lshlrev_b32_e32 v11, 7, v11 + v_add3_u32 v47, v12, v11, v23 + v_xor_b32_e32 v11, v4, v15 + v_sub_u32_e32 v11, v11, v16 + v_lshl_add_u32 v32, v11, 3, v47 + v_xor_b32_e32 v11, v4, v14 + v_sub_u32_e32 v11, v11, v16 + v_lshl_add_u32 v29, v11, 3, v47 + v_xor_b32_e32 v4, v4, v13 + v_sub_u32_e32 v11, v4, v16 + v_lshl_add_u32 v25, v11, 3, v47 + v_add_u32_e32 v8, 0xc0, v8 + v_lshrrev_b32_e32 v11, 1, v8 + v_sub_u32_e32 v10, v11, v10 + v_bfe_u32 v8, v8, 1, 4 + v_xor_b32_e32 v7, v8, v7 + v_sub_u32_e32 v4, v7, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_lshlrev_b32_e32 v10, 7, v10 + v_add3_u32 v46, v4, v10, v25 + v_xor_b32_e32 v4, v8, v15 + v_sub_u32_e32 v4, v4, v7 + v_lshl_add_u32 v34, v4, 3, v46 + v_xor_b32_e32 v4, v8, v14 + v_sub_u32_e32 v4, v4, v7 + v_lshl_add_u32 v31, v4, 3, v46 + v_xor_b32_e32 v4, v8, v13 + v_sub_u32_e32 v4, v4, v7 + v_lshl_add_u32 v28, v4, 3, v46 + v_xor_b32_e32 v4, v6, v15 + v_lshl_add_u32 v40, v4, 3, v9 + v_xor_b32_e32 v7, v6, v14 + v_lshl_add_u32 v36, v7, 3, v9 + v_xor_b32_e32 v6, v6, v13 + v_lshl_add_u32 v33, v6, 3, v9 + v_sub_u32_e32 v8, v5, v6 + v_lshlrev_b32_e32 v8, 3, v8 + v_add_u32_e32 v9, 0x1000, v8 + v_add_u32_e32 v50, v9, v33 + v_add_u32_e32 v58, v8, v33 + v_sub_u32_e32 v4, v4, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v43, v50, v4 + v_add_u32_e32 v59, v58, v4 + v_sub_u32_e32 v7, v7, v5 + v_lshlrev_b32_e32 v7, 3, v7 + v_add_u32_e32 v39, v50, v7 + v_add_u32_e32 v60, v58, v7 + v_sub_u32_e32 v5, v6, v5 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v35, v50, v5 + v_add_u32_e32 v61, v58, v5 + v_add_u32_e32 v51, v35, v9 + v_add_u32_e32 v62, v61, v9 + v_add_u32_e32 v44, v51, v4 + v_add_u32_e32 v41, v51, v7 + v_add_u32_e32 v37, v51, v5 + v_add_u32_e32 v49, v37, v9 + v_add_u32_e32 v45, v49, v4 + v_add_u32_e32 v42, v49, v7 + v_add_u32_e32 v38, v49, v5 + s_add_i32 s2, s2, 1 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 +.LBB37_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1753.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v5, 64, v3 + v_add_u32_e32 v4, 64, v2 + buffer_load_dwordx4 v[64:67], v2, s[8:11], 0 offen offset:64 + buffer_load_dwordx4 v[68:71], v3, s[12:15], 0 offen offset:64 + v_add_u32_e32 v2, s7, v4 + v_add_u32_e32 v3, s22, v5 + v_add_u32_e32 v6, s7, v2 + buffer_load_dwordx4 v[72:75], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[88:91], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[84:87], v6, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v6 + buffer_load_dwordx4 v[76:79], v3, s[12:15], 0 offen + v_add_u32_e32 v3, s22, v3 + buffer_load_dwordx4 v[92:95], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[80:83], v3, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[14:15], v53 + ds_read_b64 v[10:11], v52 offset:16384 + ds_read_b64 v[8:9], v58 offset:20480 + ds_read_b64 v[2:3], v59 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[32:47], v[14:15], v[10:11], a[32:47] + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[80:95], v[14:15], v[8:9], a[80:95] + ds_read_b64 v[18:19], v62 offset:20480 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[96:111], v[14:15], v[18:19], a[96:111] + ds_read_b64 v[20:21], v51 offset:20480 + ds_read_b64 v[12:13], v44 offset:20480 + ds_read_b64 v[16:17], v41 offset:20480 + ds_read_b64 v[6:7], v37 offset:20480 + s_waitcnt lgkmcnt(3) + v_mfma_i32_32x32x16_i8 a[112:127], v[14:15], v[20:21], a[112:127] + ds_read_b64 v[96:97], v48 + ds_read_b64 v[14:15], v30 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[128:143], v[96:97], v[10:11], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[96:97], v[8:9], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[96:97], v[18:19], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[96:97], v[20:21], a[176:191] + ds_read_b64 v[96:97], v47 + ds_read_b64 v[98:99], v32 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[192:207], v[96:97], v[10:11], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[96:97], v[8:9], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[96:97], v[18:19], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[96:97], v[20:21], a[240:255] + ds_read_b64 v[96:97], v46 + ds_read_b64 v[100:101], v34 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[64:79], v[96:97], v[10:11], a[64:79] + v_mfma_i32_32x32x16_i8 a[48:63], v[96:97], v[8:9], a[48:63] + v_mfma_i32_32x32x16_i8 a[16:31], v[96:97], v[18:19], a[16:31] + v_mfma_i32_32x32x16_i8 a[0:15], v[96:97], v[20:21], a[0:15] + ds_read_b64 v[10:11], v27 + ds_read_b64 v[18:19], v40 offset:16384 + ds_read_b64 v[20:21], v36 offset:16384 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[32:47], v[10:11], v[18:19], a[32:47] + v_mfma_i32_32x32x16_i8 a[80:95], v[10:11], v[2:3], a[80:95] + ds_read_b64 v[96:97], v43 offset:20480 + ds_read_b64 v[102:103], v39 offset:20480 + ds_read_b64 v[8:9], v35 offset:20480 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[96:97], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[10:11], v[12:13], a[112:127] + v_mfma_i32_32x32x16_i8 a[128:143], v[14:15], v[18:19], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[14:15], v[2:3], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[14:15], v[96:97], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[14:15], v[12:13], a[176:191] + v_mfma_i32_32x32x16_i8 a[192:207], v[98:99], v[18:19], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[98:99], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[98:99], v[96:97], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[98:99], v[12:13], a[240:255] + v_mfma_i32_32x32x16_i8 a[64:79], v[100:101], v[18:19], a[64:79] + v_mfma_i32_32x32x16_i8 a[48:63], v[100:101], v[2:3], a[48:63] + v_mfma_i32_32x32x16_i8 a[16:31], v[100:101], v[96:97], a[16:31] + v_mfma_i32_32x32x16_i8 a[0:15], v[100:101], v[12:13], a[0:15] + ds_read_b64 v[2:3], v24 + ds_read_b64 v[96:97], v22 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[20:21], a[32:47] + ds_read_b64 v[98:99], v60 offset:20480 + ds_read_b64 v[10:11], v61 offset:20480 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[98:99], a[80:95] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[102:103], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[16:17], a[112:127] + ds_read_b64 v[2:3], v26 + ds_read_b64 v[18:19], v23 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[20:21], a[128:143] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[98:99], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[102:103], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[16:17], a[176:191] + ds_read_b64 v[2:3], v29 + ds_read_b64 v[14:15], v25 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[20:21], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[98:99], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[102:103], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[16:17], a[240:255] + ds_read_b64 v[2:3], v31 + ds_read_b64 v[12:13], v28 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[20:21], a[64:79] + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[98:99], a[48:63] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[102:103], a[16:31] + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[16:17], a[0:15] + ds_read_b64 v[16:17], v33 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[32:47], v[96:97], v[16:17], a[32:47] + v_mfma_i32_32x32x16_i8 a[80:95], v[96:97], v[10:11], a[80:95] + v_mfma_i32_32x32x16_i8 a[96:111], v[96:97], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[96:97], v[6:7], a[112:127] + v_mfma_i32_32x32x16_i8 a[128:143], v[18:19], v[16:17], a[128:143] + v_readfirstlane_b32 s3, v0 + s_add_i32 s2, s2, -1 + s_andn2_b32 s3, s3, 63 + v_add_u32_e32 v2, s3, v54 + v_mfma_i32_32x32x16_i8 a[144:159], v[18:19], v[10:11], a[144:159] + s_cmp_gt_u32 s2, 2 + v_ashrrev_i32_e32 v20, 1, v2 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshlrev_b32_e32 v21, 6, v2 + v_or_b32_e32 v63, 1, v2 + v_lshrrev_b32_e32 v96, 31, v2 + v_or_b32_e32 v97, 3, v2 + v_mfma_i32_32x32x16_i8 a[160:175], v[18:19], v[8:9], a[160:175] + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v98, 28, v3 + v_add_u32_e32 v99, v63, v96 + v_or_b32_e32 v100, 1, v20 + v_add_u32_e32 v96, v97, v96 + v_mov_b64_e32 v[2:3], v[4:5] + v_mfma_i32_32x32x16_i8 a[176:191], v[18:19], v[6:7], a[176:191] + v_add_u32_e32 v4, v20, v98 + v_ashrrev_i32_e32 v5, 1, v99 + v_and_b32_e32 v18, 0x1ffffffe, v99 + v_ashrrev_i32_e32 v19, 31, v99 + v_add_u32_e32 v98, v100, v98 + v_ashrrev_i32_e32 v99, 1, v96 + v_and_b32_e32 v101, 0x1ffffffe, v96 + v_mfma_i32_32x32x16_i8 a[192:207], v[14:15], v[16:17], a[192:207] + v_ashrrev_i32_e32 v96, 31, v96 + v_and_b32_e32 v4, -16, v4 + v_sub_u32_e32 v102, v5, v20 + v_sub_u32_e32 v18, v63, v18 + v_lshrrev_b32_e32 v19, 28, v19 + v_sub_u32_e32 v63, v100, v5 + v_and_b32_e32 v98, -16, v98 + v_mfma_i32_32x32x16_i8 a[208:223], v[14:15], v[10:11], a[208:223] + v_sub_u32_e32 v103, v99, v100 + v_sub_u32_e32 v97, v97, v101 + v_lshrrev_b32_e32 v96, 28, v96 + v_sub_u32_e32 v4, v20, v4 + v_lshl_or_b32 v18, v18, 3, v56 + v_add_u32_e32 v19, v5, v19 + v_sub_u32_e32 v20, v100, v98 + v_mfma_i32_32x32x16_i8 a[224:239], v[14:15], v[8:9], a[224:239] + v_lshlrev_b32_e32 v63, 7, v63 + v_lshl_or_b32 v97, v97, 3, v56 + v_add_u32_e32 v96, v99, v96 + v_lshlrev_b32_e32 v98, 7, v103 + v_xor_b32_e32 v100, v4, v55 + v_xor_b32_e32 v4, v4, v56 + v_add_u32_e32 v101, v18, v57 + v_mfma_i32_32x32x16_i8 a[240:255], v[14:15], v[6:7], a[240:255] + v_and_b32_e32 v14, -16, v19 + v_xor_b32_e32 v15, v20, v55 + v_xor_b32_e32 v19, v20, v56 + v_add_u32_e32 v20, v97, v57 + v_and_b32_e32 v96, -16, v96 + v_lshl_add_u32 v100, v100, 3, v21 + v_lshl_add_u32 v21, v4, 3, v21 + v_mfma_i32_32x32x16_i8 a[64:79], v[12:13], v[16:17], a[64:79] + v_sub_u32_e32 v5, v5, v14 + v_sub_u32_e32 v14, v19, v15 + v_sub_u32_e32 v16, v99, v96 + v_xor_b32_e32 v17, v101, v5 + v_lshl_add_u32 v96, v102, 7, v21 + v_xor_b32_e32 v5, v18, v5 + v_xor_b32_e32 v18, v20, v16 + v_mfma_i32_32x32x16_i8 a[48:63], v[12:13], v[10:11], a[48:63] + v_xor_b32_e32 v10, v97, v16 + v_sub_u32_e32 v11, v17, v4 + v_sub_u32_e32 v4, v5, v4 + v_sub_u32_e32 v5, v15, v5 + v_sub_u32_e32 v15, v18, v19 + v_sub_u32_e32 v10, v10, v18 + v_lshl_add_u32 v11, v11, 3, v96 + v_mfma_i32_32x32x16_i8 a[16:31], v[12:13], v[8:9], a[16:31] + v_lshl_add_u32 v4, v4, 3, v96 + v_lshlrev_b32_e32 v5, 3, v5 + v_lshlrev_b32_e32 v8, 3, v15 + v_add3_u32 v5, v5, v63, v4 + v_lshl_add_u32 v9, v14, 3, v5 + v_add3_u32 v8, v8, v98, v9 + v_lshl_add_u32 v10, v10, 3, v8 + v_mfma_i32_32x32x16_i8 a[0:15], v[12:13], v[6:7], a[0:15] + s_waitcnt vmcnt(7) + ds_write_b64 v100, v[64:65] + ds_write_b64 v21, v[66:67] + s_waitcnt vmcnt(4) + ds_write_b64 v11, v[88:89] + ds_write_b64 v4, v[90:91] + s_waitcnt vmcnt(3) + ds_write_b64 v5, v[84:85] + ds_write_b64 v9, v[86:87] + s_waitcnt vmcnt(1) + ds_write_b64 v8, v[92:93] + ds_write_b64 v10, v[94:95] + ds_write_b64 v100, v[68:69] offset:16384 + ds_write_b64 v21, v[70:71] offset:16384 + ds_write_b64 v11, v[72:73] offset:16384 + ds_write_b64 v4, v[74:75] offset:16384 + ds_write_b64 v5, v[76:77] offset:16384 + ds_write_b64 v9, v[78:79] offset:16384 + s_waitcnt vmcnt(0) + ds_write_b64 v8, v[80:81] offset:16384 + ds_write_b64 v10, v[82:83] offset:16384 + s_cbranch_scc1 .LBB37_8 +.LBB37_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RKT2_iPvENKUlS1L + v_accvgpr_read_b32 v150, a32 + v_accvgpr_read_b32 v151, a33 + v_accvgpr_read_b32 v152, a34 + v_accvgpr_read_b32 v153, a35 + v_accvgpr_read_b32 v154, a36 + v_accvgpr_read_b32 v155, a37 + v_accvgpr_read_b32 v156, a38 + v_accvgpr_read_b32 v157, a39 + v_accvgpr_read_b32 v158, a40 + v_accvgpr_read_b32 v159, a41 + v_accvgpr_read_b32 v160, a42 + v_accvgpr_read_b32 v161, a43 + v_accvgpr_read_b32 v162, a44 + v_accvgpr_read_b32 v163, a45 + v_accvgpr_read_b32 v164, a46 + v_accvgpr_read_b32 v165, a47 + v_accvgpr_read_b32 v6, a80 + v_accvgpr_read_b32 v7, a81 + v_accvgpr_read_b32 v8, a82 + v_accvgpr_read_b32 v9, a83 + v_accvgpr_read_b32 v10, a84 + v_accvgpr_read_b32 v11, a85 + v_accvgpr_read_b32 v12, a86 + v_accvgpr_read_b32 v13, a87 + v_accvgpr_read_b32 v14, a88 + v_accvgpr_read_b32 v15, a89 + v_accvgpr_read_b32 v16, a90 + v_accvgpr_read_b32 v17, a91 + v_accvgpr_read_b32 v18, a92 + v_accvgpr_read_b32 v19, a93 + v_accvgpr_read_b32 v20, a94 + v_accvgpr_read_b32 v21, a95 + v_accvgpr_read_b32 v134, a96 + v_accvgpr_read_b32 v135, a97 + v_accvgpr_read_b32 v136, a98 + v_accvgpr_read_b32 v137, a99 + v_accvgpr_read_b32 v138, a100 + v_accvgpr_read_b32 v139, a101 + v_accvgpr_read_b32 v140, a102 + v_accvgpr_read_b32 v141, a103 + v_accvgpr_read_b32 v142, a104 + v_accvgpr_read_b32 v143, a105 + v_accvgpr_read_b32 v144, a106 + v_accvgpr_read_b32 v145, a107 + v_accvgpr_read_b32 v146, a108 + v_accvgpr_read_b32 v147, a109 + v_accvgpr_read_b32 v148, a110 + v_accvgpr_read_b32 v149, a111 + v_accvgpr_read_b32 v118, a112 + v_accvgpr_read_b32 v119, a113 + v_accvgpr_read_b32 v120, a114 + v_accvgpr_read_b32 v121, a115 + v_accvgpr_read_b32 v122, a116 + v_accvgpr_read_b32 v123, a117 + v_accvgpr_read_b32 v124, a118 + v_accvgpr_read_b32 v125, a119 + v_accvgpr_read_b32 v126, a120 + v_accvgpr_read_b32 v127, a121 + v_accvgpr_read_b32 v128, a122 + v_accvgpr_read_b32 v129, a123 + v_accvgpr_read_b32 v130, a124 + v_accvgpr_read_b32 v131, a125 + v_accvgpr_read_b32 v132, a126 + v_accvgpr_read_b32 v133, a127 + v_accvgpr_read_b32 v102, a128 + v_accvgpr_read_b32 v103, a129 + v_accvgpr_read_b32 v104, a130 + v_accvgpr_read_b32 v105, a131 + v_accvgpr_read_b32 v106, a132 + v_accvgpr_read_b32 v107, a133 + v_accvgpr_read_b32 v108, a134 + v_accvgpr_read_b32 v109, a135 + v_accvgpr_read_b32 v110, a136 + v_accvgpr_read_b32 v111, a137 + v_accvgpr_read_b32 v112, a138 + v_accvgpr_read_b32 v113, a139 + v_accvgpr_read_b32 v114, a140 + v_accvgpr_read_b32 v115, a141 + v_accvgpr_read_b32 v116, a142 + v_accvgpr_read_b32 v117, a143 + v_accvgpr_mov_b32 a128, a144 + v_accvgpr_mov_b32 a129, a145 + v_accvgpr_mov_b32 a130, a146 + v_accvgpr_mov_b32 a131, a147 + v_accvgpr_mov_b32 a132, a148 + v_accvgpr_mov_b32 a133, a149 + v_accvgpr_mov_b32 a134, a150 + v_accvgpr_mov_b32 a135, a151 + v_accvgpr_mov_b32 a136, a152 + v_accvgpr_mov_b32 a137, a153 + v_accvgpr_mov_b32 a138, a154 + v_accvgpr_mov_b32 a139, a155 + v_accvgpr_mov_b32 a140, a156 + v_accvgpr_mov_b32 a141, a157 + v_accvgpr_mov_b32 a142, a158 + v_accvgpr_mov_b32 a143, a159 + v_accvgpr_read_b32 v86, a160 + v_accvgpr_read_b32 v87, a161 + v_accvgpr_read_b32 v88, a162 + v_accvgpr_read_b32 v89, a163 + v_accvgpr_read_b32 v90, a164 + v_accvgpr_read_b32 v91, a165 + v_accvgpr_read_b32 v92, a166 + v_accvgpr_read_b32 v93, a167 + v_accvgpr_read_b32 v94, a168 + v_accvgpr_read_b32 v95, a169 + v_accvgpr_read_b32 v96, a170 + v_accvgpr_read_b32 v97, a171 + v_accvgpr_read_b32 v98, a172 + v_accvgpr_read_b32 v99, a173 + v_accvgpr_read_b32 v100, a174 + v_accvgpr_read_b32 v101, a175 + v_accvgpr_read_b32 v70, a176 + v_accvgpr_read_b32 v71, a177 + v_accvgpr_read_b32 v72, a178 + v_accvgpr_read_b32 v73, a179 + v_accvgpr_read_b32 v74, a180 + v_accvgpr_read_b32 v75, a181 + v_accvgpr_read_b32 v76, a182 + v_accvgpr_read_b32 v77, a183 + v_accvgpr_read_b32 v78, a184 + v_accvgpr_read_b32 v79, a185 + v_accvgpr_read_b32 v80, a186 + v_accvgpr_read_b32 v81, a187 + v_accvgpr_read_b32 v82, a188 + v_accvgpr_read_b32 v83, a189 + v_accvgpr_read_b32 v84, a190 + v_accvgpr_read_b32 v85, a191 + v_accvgpr_read_b32 v54, a192 + v_accvgpr_read_b32 v55, a193 + v_accvgpr_read_b32 v56, a194 + v_accvgpr_read_b32 v57, a195 + v_accvgpr_read_b32 v58, a196 + v_accvgpr_read_b32 v59, a197 + v_accvgpr_read_b32 v60, a198 + v_accvgpr_read_b32 v61, a199 + v_accvgpr_read_b32 v62, a200 + v_accvgpr_read_b32 v63, a201 + v_accvgpr_read_b32 v64, a202 + v_accvgpr_read_b32 v65, a203 + v_accvgpr_read_b32 v66, a204 + v_accvgpr_read_b32 v67, a205 + v_accvgpr_read_b32 v68, a206 + v_accvgpr_read_b32 v69, a207 + v_accvgpr_mov_b32 a144, a208 + v_accvgpr_mov_b32 a145, a209 + v_accvgpr_mov_b32 a146, a210 + v_accvgpr_mov_b32 a147, a211 + v_accvgpr_mov_b32 a148, a212 + v_accvgpr_mov_b32 a149, a213 + v_accvgpr_mov_b32 a150, a214 + v_accvgpr_mov_b32 a151, a215 + v_accvgpr_mov_b32 a152, a216 + v_accvgpr_mov_b32 a153, a217 + v_accvgpr_mov_b32 a154, a218 + v_accvgpr_mov_b32 a155, a219 + v_accvgpr_mov_b32 a156, a220 + v_accvgpr_mov_b32 a157, a221 + v_accvgpr_mov_b32 a158, a222 + v_accvgpr_mov_b32 a159, a223 + v_accvgpr_mov_b32 a80, a224 + v_accvgpr_mov_b32 a81, a225 + v_accvgpr_mov_b32 a82, a226 + v_accvgpr_mov_b32 a83, a227 + v_accvgpr_mov_b32 a84, a228 + v_accvgpr_mov_b32 a85, a229 + v_accvgpr_mov_b32 a86, a230 + v_accvgpr_mov_b32 a87, a231 + v_accvgpr_mov_b32 a88, a232 + v_accvgpr_mov_b32 a89, a233 + v_accvgpr_mov_b32 a90, a234 + v_accvgpr_mov_b32 a91, a235 + v_accvgpr_mov_b32 a92, a236 + v_accvgpr_mov_b32 a93, a237 + v_accvgpr_mov_b32 a94, a238 + v_accvgpr_mov_b32 a95, a239 + v_accvgpr_mov_b32 a32, a240 + v_accvgpr_mov_b32 a33, a241 + v_accvgpr_mov_b32 a34, a242 + v_accvgpr_mov_b32 a35, a243 + v_accvgpr_mov_b32 a36, a244 + v_accvgpr_mov_b32 a37, a245 + v_accvgpr_mov_b32 a38, a246 + v_accvgpr_mov_b32 a39, a247 + v_accvgpr_mov_b32 a40, a248 + v_accvgpr_mov_b32 a41, a249 + v_accvgpr_mov_b32 a42, a250 + v_accvgpr_mov_b32 a43, a251 + v_accvgpr_mov_b32 a44, a252 + v_accvgpr_mov_b32 a45, a253 + v_accvgpr_mov_b32 a46, a254 + v_accvgpr_mov_b32 a47, a255 + v_accvgpr_mov_b32 a224, a64 + v_accvgpr_mov_b32 a225, a65 + v_accvgpr_mov_b32 a226, a66 + v_accvgpr_mov_b32 a227, a67 + v_accvgpr_mov_b32 a228, a68 + v_accvgpr_mov_b32 a229, a69 + v_accvgpr_mov_b32 a230, a70 + v_accvgpr_mov_b32 a231, a71 + v_accvgpr_mov_b32 a232, a72 + v_accvgpr_mov_b32 a233, a73 + v_accvgpr_mov_b32 a234, a74 + v_accvgpr_mov_b32 a235, a75 + v_accvgpr_mov_b32 a236, a76 + v_accvgpr_mov_b32 a237, a77 + v_accvgpr_mov_b32 a238, a78 + v_accvgpr_mov_b32 a239, a79 + v_accvgpr_mov_b32 a160, a48 + v_accvgpr_mov_b32 a161, a49 + v_accvgpr_mov_b32 a162, a50 + v_accvgpr_mov_b32 a163, a51 + v_accvgpr_mov_b32 a164, a52 + v_accvgpr_mov_b32 a165, a53 + v_accvgpr_mov_b32 a166, a54 + v_accvgpr_mov_b32 a167, a55 + v_accvgpr_mov_b32 a168, a56 + v_accvgpr_mov_b32 a169, a57 + v_accvgpr_mov_b32 a170, a58 + v_accvgpr_mov_b32 a171, a59 + v_accvgpr_mov_b32 a172, a60 + v_accvgpr_mov_b32 a173, a61 + v_accvgpr_mov_b32 a174, a62 + v_accvgpr_mov_b32 a175, a63 + v_accvgpr_mov_b32 a96, a16 + v_accvgpr_mov_b32 a97, a17 + v_accvgpr_mov_b32 a98, a18 + v_accvgpr_mov_b32 a99, a19 + v_accvgpr_mov_b32 a100, a20 + v_accvgpr_mov_b32 a101, a21 + v_accvgpr_mov_b32 a102, a22 + v_accvgpr_mov_b32 a103, a23 + v_accvgpr_mov_b32 a104, a24 + v_accvgpr_mov_b32 a105, a25 + v_accvgpr_mov_b32 a106, a26 + v_accvgpr_mov_b32 a107, a27 + v_accvgpr_mov_b32 a108, a28 + v_accvgpr_mov_b32 a109, a29 + v_accvgpr_mov_b32 a110, a30 + v_accvgpr_mov_b32 a111, a31 + v_accvgpr_mov_b32 a240, a0 + v_accvgpr_mov_b32 a241, a1 + v_accvgpr_mov_b32 a242, a2 + v_accvgpr_mov_b32 a243, a3 + v_accvgpr_mov_b32 a244, a4 + v_accvgpr_mov_b32 a245, a5 + v_accvgpr_mov_b32 a246, a6 + v_accvgpr_mov_b32 a247, a7 + v_accvgpr_mov_b32 a248, a8 + v_accvgpr_mov_b32 a249, a9 + v_accvgpr_mov_b32 a250, a10 + v_accvgpr_mov_b32 a251, a11 + v_accvgpr_mov_b32 a252, a12 + v_accvgpr_mov_b32 a253, a13 + v_accvgpr_mov_b32 a254, a14 + v_accvgpr_mov_b32 a255, a15 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[166:167], v53 + ds_read_b64 v[2:3], v52 offset:16384 + v_accvgpr_write_b32 a191, v165 + v_accvgpr_write_b32 a190, v164 + v_accvgpr_write_b32 a189, v163 + v_accvgpr_write_b32 a188, v162 + v_accvgpr_write_b32 a187, v161 + v_accvgpr_write_b32 a186, v160 + v_accvgpr_write_b32 a185, v159 + v_accvgpr_write_b32 a184, v158 + v_accvgpr_write_b32 a183, v157 + v_accvgpr_write_b32 a182, v156 + v_accvgpr_write_b32 a181, v155 + v_accvgpr_write_b32 a180, v154 + v_accvgpr_write_b32 a179, v153 + v_accvgpr_write_b32 a178, v152 + v_accvgpr_write_b32 a177, v151 + v_accvgpr_write_b32 a176, v150 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[166:167], v[2:3], a[176:191] + ds_read_b64 v[4:5], v50 offset:16384 + v_accvgpr_write_b32 a127, v21 + v_accvgpr_write_b32 a126, v20 + v_accvgpr_write_b32 a125, v19 + v_accvgpr_write_b32 a124, v18 + v_accvgpr_write_b32 a123, v17 + v_accvgpr_write_b32 a122, v16 + v_accvgpr_write_b32 a121, v15 + v_accvgpr_write_b32 a120, v14 + v_accvgpr_write_b32 a119, v13 + v_accvgpr_write_b32 a118, v12 + v_accvgpr_write_b32 a117, v11 + v_accvgpr_write_b32 a116, v10 + v_accvgpr_write_b32 a115, v9 + v_accvgpr_write_b32 a114, v8 + v_accvgpr_write_b32 a113, v7 + v_accvgpr_write_b32 a112, v6 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[112:127], v[166:167], v[4:5], a[112:127] + ds_read_b64 v[6:7], v51 offset:16384 + v_accvgpr_write_b32 a48, v134 + v_accvgpr_write_b32 a49, v135 + v_accvgpr_write_b32 a50, v136 + v_accvgpr_write_b32 a51, v137 + v_accvgpr_write_b32 a52, v138 + v_accvgpr_write_b32 a53, v139 + v_accvgpr_write_b32 a54, v140 + v_accvgpr_write_b32 a55, v141 + v_accvgpr_write_b32 a56, v142 + v_accvgpr_write_b32 a57, v143 + v_accvgpr_write_b32 a58, v144 + v_accvgpr_write_b32 a59, v145 + v_accvgpr_write_b32 a60, v146 + v_accvgpr_write_b32 a61, v147 + v_accvgpr_write_b32 a62, v148 + v_accvgpr_write_b32 a63, v149 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[48:63], v[166:167], v[6:7], a[48:63] + ds_read_b64 v[8:9], v49 offset:16384 + v_accvgpr_write_b32 a0, v118 + v_accvgpr_write_b32 a1, v119 + v_accvgpr_write_b32 a2, v120 + v_accvgpr_write_b32 a3, v121 + v_accvgpr_write_b32 a4, v122 + v_accvgpr_write_b32 a5, v123 + v_accvgpr_write_b32 a6, v124 + v_accvgpr_write_b32 a7, v125 + v_accvgpr_write_b32 a8, v126 + v_accvgpr_write_b32 a9, v127 + v_accvgpr_write_b32 a10, v128 + v_accvgpr_write_b32 a11, v129 + v_accvgpr_write_b32 a12, v130 + v_accvgpr_write_b32 a13, v131 + v_accvgpr_write_b32 a14, v132 + v_accvgpr_write_b32 a15, v133 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[0:15], v[166:167], v[8:9], a[0:15] + ds_read_b64 v[10:11], v48 + v_accvgpr_write_b32 a207, v117 + v_accvgpr_write_b32 a206, v116 + v_accvgpr_write_b32 a205, v115 + v_accvgpr_write_b32 a204, v114 + v_accvgpr_write_b32 a203, v113 + v_accvgpr_write_b32 a202, v112 + v_accvgpr_write_b32 a201, v111 + v_accvgpr_write_b32 a200, v110 + v_accvgpr_write_b32 a199, v109 + v_accvgpr_write_b32 a198, v108 + v_accvgpr_write_b32 a197, v107 + v_accvgpr_write_b32 a196, v106 + v_accvgpr_write_b32 a195, v105 + v_accvgpr_write_b32 a194, v104 + v_accvgpr_write_b32 a193, v103 + v_accvgpr_write_b32 a192, v102 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[192:207], v[10:11], v[2:3], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[10:11], v[4:5], a[128:143] + v_accvgpr_write_b32 a64, v86 + v_accvgpr_write_b32 a65, v87 + v_accvgpr_write_b32 a66, v88 + v_accvgpr_write_b32 a67, v89 + v_accvgpr_write_b32 a68, v90 + v_accvgpr_write_b32 a69, v91 + v_accvgpr_write_b32 a70, v92 + v_accvgpr_write_b32 a71, v93 + v_accvgpr_write_b32 a72, v94 + v_accvgpr_write_b32 a73, v95 + v_accvgpr_write_b32 a74, v96 + v_accvgpr_write_b32 a75, v97 + v_accvgpr_write_b32 a76, v98 + v_accvgpr_write_b32 a77, v99 + v_accvgpr_write_b32 a78, v100 + v_accvgpr_write_b32 a79, v101 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[64:79], v[10:11], v[6:7], a[64:79] + v_accvgpr_write_b32 a16, v70 + v_accvgpr_write_b32 a17, v71 + v_accvgpr_write_b32 a18, v72 + v_accvgpr_write_b32 a19, v73 + v_accvgpr_write_b32 a20, v74 + v_accvgpr_write_b32 a21, v75 + v_accvgpr_write_b32 a22, v76 + v_accvgpr_write_b32 a23, v77 + v_accvgpr_write_b32 a24, v78 + v_accvgpr_write_b32 a25, v79 + v_accvgpr_write_b32 a26, v80 + v_accvgpr_write_b32 a27, v81 + v_accvgpr_write_b32 a28, v82 + v_accvgpr_write_b32 a29, v83 + v_accvgpr_write_b32 a30, v84 + v_accvgpr_write_b32 a31, v85 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[16:31], v[10:11], v[8:9], a[16:31] + ds_read_b64 v[10:11], v47 + v_accvgpr_write_b32 a223, v69 + v_accvgpr_write_b32 a222, v68 + v_accvgpr_write_b32 a221, v67 + v_accvgpr_write_b32 a220, v66 + v_accvgpr_write_b32 a219, v65 + v_accvgpr_write_b32 a218, v64 + v_accvgpr_write_b32 a217, v63 + v_accvgpr_write_b32 a216, v62 + v_accvgpr_write_b32 a215, v61 + v_accvgpr_write_b32 a214, v60 + v_accvgpr_write_b32 a213, v59 + v_accvgpr_write_b32 a212, v58 + v_accvgpr_write_b32 a211, v57 + v_accvgpr_write_b32 a210, v56 + v_accvgpr_write_b32 a209, v55 + v_accvgpr_write_b32 a208, v54 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[208:223], v[10:11], v[2:3], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[10:11], v[4:5], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[10:11], v[6:7], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[10:11], v[8:9], a[32:47] + ds_read_b64 v[10:11], v46 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[10:11], v[2:3], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[10:11], v[4:5], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[10:11], v[6:7], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[10:11], v[8:9], a[240:255] + ds_read_b64 v[2:3], v27 + ds_read_b64 v[4:5], v40 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b64 v[6:7], v43 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b64 v[8:9], v44 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b64 v[10:11], v45 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v30 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v32 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v34 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] + ds_read_b64 v[2:3], v24 + ds_read_b64 v[4:5], v36 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b64 v[6:7], v39 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b64 v[8:9], v41 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b64 v[10:11], v42 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v26 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v29 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v31 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] + ds_read_b64 v[2:3], v22 + ds_read_b64 v[4:5], v33 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b64 v[6:7], v35 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b64 v[8:9], v37 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b64 v[10:11], v38 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v23 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v25 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v28 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] +.LBB37_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSA_11ColumnMajorESB_Li1EEEaNS_12element_wise11PassThroughESF_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSK_IJNS_5embedINSK_IJiiEEESU_Lb0EEENS_12pass_throughIiEESX_EEENSK_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSK_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSK_IJNS_8constantILi256EEENS1D_ILi64EEEEEEEEEEES1I_SF_SF_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1K_T0_EE5valueEbE4typeELPb0EEEDaRKS1L_RKT1_RKS1M_RKT2_iPv.exit.i.i + s_nop 10 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s5, s4 + s_add_u32 s4, s2, 2.0 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v18, 28, v1 + v_and_b32_e32 v19, 3, v1 + v_lshrrev_b32_e32 v20, 3, v1 + v_and_b32_e32 v22, 0x1ffffffc, v20 + s_waitcnt lgkmcnt(0) + s_mov_b64 s[2:3], -1 + v_lshlrev_b32_e32 v23, 2, v19 + v_lshlrev_b32_e32 v21, 2, v18 + v_lshlrev_b32_e32 v20, 2, v1 + v_and_b32_e32 v1, -16, v1 + s_cbranch_scc1 .LBB37_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB37_14 +.LBB37_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSD_11ColumnMajorESE_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SE_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB37_13: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_add_u32_e32 v18, s3, v22 + s_barrier + v_lshl_or_b32 v18, v18, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v24, v18, v21, s3 + ds_write_b32 v24, a176 + ds_write_b32 v24, a177 offset:256 + ds_write_b32 v24, a178 offset:512 + ds_write_b32 v24, a179 offset:768 + ds_write_b32 v24, a180 offset:2048 + ds_write_b32 v24, a181 offset:2304 + ds_write_b32 v24, a182 offset:2560 + ds_write_b32 v24, a183 offset:2816 + ds_write_b32 v24, a184 offset:4096 + ds_write_b32 v24, a185 offset:4352 + ds_write_b32 v24, a186 offset:4608 + ds_write_b32 v24, a187 offset:4864 + ds_write_b32 v24, a188 offset:6144 + ds_write_b32 v24, a189 offset:6400 + ds_write_b32 v24, a190 offset:6656 + ds_write_b32 v24, a191 offset:6912 + ds_write_b32 v24, a192 offset:16384 + ds_write_b32 v24, a193 offset:16640 + ds_write_b32 v24, a194 offset:16896 + ds_write_b32 v24, a195 offset:17152 + ds_write_b32 v24, a196 offset:18432 + ds_write_b32 v24, a197 offset:18688 + ds_write_b32 v24, a198 offset:18944 + ds_write_b32 v24, a199 offset:19200 + ds_write_b32 v24, a200 offset:20480 + ds_write_b32 v24, a201 offset:20736 + ds_write_b32 v24, a202 offset:20992 + ds_write_b32 v24, a203 offset:21248 + ds_write_b32 v24, a204 offset:22528 + ds_write_b32 v24, a205 offset:22784 + ds_write_b32 v24, a206 offset:23040 + ds_write_b32 v24, a207 offset:23296 + ds_write_b32 v24, a208 offset:32768 + ds_write_b32 v24, a209 offset:33024 + ds_write_b32 v24, a210 offset:33280 + ds_write_b32 v24, a211 offset:33536 + ds_write_b32 v24, a212 offset:34816 + ds_write_b32 v24, a213 offset:35072 + ds_write_b32 v24, a214 offset:35328 + ds_write_b32 v24, a215 offset:35584 + ds_write_b32 v24, a216 offset:36864 + ds_write_b32 v24, a217 offset:37120 + ds_write_b32 v24, a218 offset:37376 + ds_write_b32 v24, a219 offset:37632 + ds_write_b32 v24, a220 offset:38912 + ds_write_b32 v24, a221 offset:39168 + ds_write_b32 v24, a222 offset:39424 + ds_write_b32 v24, a223 offset:39680 + ds_write_b32 v24, a224 offset:49152 + ds_write_b32 v24, a225 offset:49408 + ds_write_b32 v24, a226 offset:49664 + ds_write_b32 v24, a227 offset:49920 + ds_write_b32 v24, a228 offset:51200 + ds_write_b32 v24, a229 offset:51456 + ds_write_b32 v24, a230 offset:51712 + ds_write_b32 v24, a231 offset:51968 + ds_write_b32 v24, a232 offset:53248 + ds_write_b32 v24, a233 offset:53504 + ds_write_b32 v24, a234 offset:53760 + ds_write_b32 v24, a235 offset:54016 + ds_write_b32 v24, a236 offset:55296 + ds_write_b32 v24, a237 offset:55552 + ds_write_b32 v24, a238 offset:55808 + ds_write_b32 v24, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v18, 60, v20 + s_andn2_b32 s2, s2, 63 + v_add_u32_e32 v19, s2, v1 + v_lshlrev_b32_e32 v25, 8, v19 + v_lshl_or_b32 v25, v18, 2, v25 + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, s20, v19 + v_or_b32_e32 v18, s21, v18 + v_mad_u64_u32 v[18:19], s[2:3], v19, s16, v[18:19] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v18 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a112 + ds_write_b32 v24, a113 offset:256 + ds_write_b32 v24, a114 offset:512 + ds_write_b32 v24, a115 offset:768 + ds_write_b32 v24, a116 offset:2048 + ds_write_b32 v24, a117 offset:2304 + ds_write_b32 v24, a118 offset:2560 + ds_write_b32 v24, a119 offset:2816 + ds_write_b32 v24, a120 offset:4096 + ds_write_b32 v24, a121 offset:4352 + ds_write_b32 v24, a122 offset:4608 + ds_write_b32 v24, a123 offset:4864 + ds_write_b32 v24, a124 offset:6144 + ds_write_b32 v24, a125 offset:6400 + ds_write_b32 v24, a126 offset:6656 + ds_write_b32 v24, a127 offset:6912 + ds_write_b32 v24, a128 offset:16384 + ds_write_b32 v24, a129 offset:16640 + ds_write_b32 v24, a130 offset:16896 + ds_write_b32 v24, a131 offset:17152 + ds_write_b32 v24, a132 offset:18432 + ds_write_b32 v24, a133 offset:18688 + ds_write_b32 v24, a134 offset:18944 + ds_write_b32 v24, a135 offset:19200 + ds_write_b32 v24, a136 offset:20480 + ds_write_b32 v24, a137 offset:20736 + ds_write_b32 v24, a138 offset:20992 + ds_write_b32 v24, a139 offset:21248 + ds_write_b32 v24, a140 offset:22528 + ds_write_b32 v24, a141 offset:22784 + ds_write_b32 v24, a142 offset:23040 + ds_write_b32 v24, a143 offset:23296 + ds_write_b32 v24, a144 offset:32768 + ds_write_b32 v24, a145 offset:33024 + ds_write_b32 v24, a146 offset:33280 + ds_write_b32 v24, a147 offset:33536 + ds_write_b32 v24, a148 offset:34816 + ds_write_b32 v24, a149 offset:35072 + ds_write_b32 v24, a150 offset:35328 + ds_write_b32 v24, a151 offset:35584 + ds_write_b32 v24, a152 offset:36864 + ds_write_b32 v24, a153 offset:37120 + ds_write_b32 v24, a154 offset:37376 + ds_write_b32 v24, a155 offset:37632 + ds_write_b32 v24, a156 offset:38912 + ds_write_b32 v24, a157 offset:39168 + ds_write_b32 v24, a158 offset:39424 + ds_write_b32 v24, a159 offset:39680 + ds_write_b32 v24, a160 offset:49152 + ds_write_b32 v24, a161 offset:49408 + ds_write_b32 v24, a162 offset:49664 + ds_write_b32 v24, a163 offset:49920 + ds_write_b32 v24, a164 offset:51200 + ds_write_b32 v24, a165 offset:51456 + ds_write_b32 v24, a166 offset:51712 + ds_write_b32 v24, a167 offset:51968 + ds_write_b32 v24, a168 offset:53248 + ds_write_b32 v24, a169 offset:53504 + ds_write_b32 v24, a170 offset:53760 + ds_write_b32 v24, a171 offset:54016 + ds_write_b32 v24, a172 offset:55296 + ds_write_b32 v24, a173 offset:55552 + ds_write_b32 v24, a174 offset:55808 + ds_write_b32 v24, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 64, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a48 + ds_write_b32 v24, a49 offset:256 + ds_write_b32 v24, a50 offset:512 + ds_write_b32 v24, a51 offset:768 + ds_write_b32 v24, a52 offset:2048 + ds_write_b32 v24, a53 offset:2304 + ds_write_b32 v24, a54 offset:2560 + ds_write_b32 v24, a55 offset:2816 + ds_write_b32 v24, a56 offset:4096 + ds_write_b32 v24, a57 offset:4352 + ds_write_b32 v24, a58 offset:4608 + ds_write_b32 v24, a59 offset:4864 + ds_write_b32 v24, a60 offset:6144 + ds_write_b32 v24, a61 offset:6400 + ds_write_b32 v24, a62 offset:6656 + ds_write_b32 v24, a63 offset:6912 + ds_write_b32 v24, a64 offset:16384 + ds_write_b32 v24, a65 offset:16640 + ds_write_b32 v24, a66 offset:16896 + ds_write_b32 v24, a67 offset:17152 + ds_write_b32 v24, a68 offset:18432 + ds_write_b32 v24, a69 offset:18688 + ds_write_b32 v24, a70 offset:18944 + ds_write_b32 v24, a71 offset:19200 + ds_write_b32 v24, a72 offset:20480 + ds_write_b32 v24, a73 offset:20736 + ds_write_b32 v24, a74 offset:20992 + ds_write_b32 v24, a75 offset:21248 + ds_write_b32 v24, a76 offset:22528 + ds_write_b32 v24, a77 offset:22784 + ds_write_b32 v24, a78 offset:23040 + ds_write_b32 v24, a79 offset:23296 + ds_write_b32 v24, a80 offset:32768 + ds_write_b32 v24, a81 offset:33024 + ds_write_b32 v24, a82 offset:33280 + ds_write_b32 v24, a83 offset:33536 + ds_write_b32 v24, a84 offset:34816 + ds_write_b32 v24, a85 offset:35072 + ds_write_b32 v24, a86 offset:35328 + ds_write_b32 v24, a87 offset:35584 + ds_write_b32 v24, a88 offset:36864 + ds_write_b32 v24, a89 offset:37120 + ds_write_b32 v24, a90 offset:37376 + ds_write_b32 v24, a91 offset:37632 + ds_write_b32 v24, a92 offset:38912 + ds_write_b32 v24, a93 offset:39168 + ds_write_b32 v24, a94 offset:39424 + ds_write_b32 v24, a95 offset:39680 + ds_write_b32 v24, a96 offset:49152 + ds_write_b32 v24, a97 offset:49408 + ds_write_b32 v24, a98 offset:49664 + ds_write_b32 v24, a99 offset:49920 + ds_write_b32 v24, a100 offset:51200 + ds_write_b32 v24, a101 offset:51456 + ds_write_b32 v24, a102 offset:51712 + ds_write_b32 v24, a103 offset:51968 + ds_write_b32 v24, a104 offset:53248 + ds_write_b32 v24, a105 offset:53504 + ds_write_b32 v24, a106 offset:53760 + ds_write_b32 v24, a107 offset:54016 + ds_write_b32 v24, a108 offset:55296 + ds_write_b32 v24, a109 offset:55552 + ds_write_b32 v24, a110 offset:55808 + ds_write_b32 v24, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 0x80, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a0 + ds_write_b32 v24, a1 offset:256 + ds_write_b32 v24, a2 offset:512 + ds_write_b32 v24, a3 offset:768 + ds_write_b32 v24, a4 offset:2048 + ds_write_b32 v24, a5 offset:2304 + ds_write_b32 v24, a6 offset:2560 + ds_write_b32 v24, a7 offset:2816 + ds_write_b32 v24, a8 offset:4096 + ds_write_b32 v24, a9 offset:4352 + ds_write_b32 v24, a10 offset:4608 + ds_write_b32 v24, a11 offset:4864 + ds_write_b32 v24, a12 offset:6144 + ds_write_b32 v24, a13 offset:6400 + ds_write_b32 v24, a14 offset:6656 + ds_write_b32 v24, a15 offset:6912 + ds_write_b32 v24, a16 offset:16384 + ds_write_b32 v24, a17 offset:16640 + ds_write_b32 v24, a18 offset:16896 + ds_write_b32 v24, a19 offset:17152 + ds_write_b32 v24, a20 offset:18432 + ds_write_b32 v24, a21 offset:18688 + ds_write_b32 v24, a22 offset:18944 + ds_write_b32 v24, a23 offset:19200 + ds_write_b32 v24, a24 offset:20480 + ds_write_b32 v24, a25 offset:20736 + ds_write_b32 v24, a26 offset:20992 + ds_write_b32 v24, a27 offset:21248 + ds_write_b32 v24, a28 offset:22528 + ds_write_b32 v24, a29 offset:22784 + ds_write_b32 v24, a30 offset:23040 + ds_write_b32 v24, a31 offset:23296 + ds_write_b32 v24, a32 offset:32768 + ds_write_b32 v24, a33 offset:33024 + ds_write_b32 v24, a34 offset:33280 + ds_write_b32 v24, a35 offset:33536 + ds_write_b32 v24, a36 offset:34816 + ds_write_b32 v24, a37 offset:35072 + ds_write_b32 v24, a38 offset:35328 + ds_write_b32 v24, a39 offset:35584 + ds_write_b32 v24, a40 offset:36864 + ds_write_b32 v24, a41 offset:37120 + ds_write_b32 v24, a42 offset:37376 + ds_write_b32 v24, a43 offset:37632 + ds_write_b32 v24, a44 offset:38912 + ds_write_b32 v24, a45 offset:39168 + ds_write_b32 v24, a46 offset:39424 + ds_write_b32 v24, a47 offset:39680 + ds_write2st64_b32 v24, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v24, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v24, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v24, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v24, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v24, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v24, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v24, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v18, 0xc0, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + buffer_atomic_add v30, v19, s[0:3], 0 offen + buffer_atomic_add v31, v19, s[0:3], 4 offen + buffer_atomic_add v32, v19, s[0:3], 8 offen + buffer_atomic_add v33, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v19, s[0:3], 0 offen + buffer_atomic_add v35, v19, s[0:3], 4 offen + buffer_atomic_add v36, v19, s[0:3], 8 offen + buffer_atomic_add v37, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v19, s[0:3], 0 offen + buffer_atomic_add v39, v19, s[0:3], 4 offen + buffer_atomic_add v40, v19, s[0:3], 8 offen + buffer_atomic_add v41, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v19, s[0:3], 0 offen + buffer_atomic_add v43, v19, s[0:3], 4 offen + buffer_atomic_add v44, v19, s[0:3], 8 offen + buffer_atomic_add v45, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v19, s[0:3], 0 offen + buffer_atomic_add v47, v19, s[0:3], 4 offen + buffer_atomic_add v48, v19, s[0:3], 8 offen + buffer_atomic_add v49, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v19, s[0:3], 0 offen + buffer_atomic_add v51, v19, s[0:3], 4 offen + buffer_atomic_add v52, v19, s[0:3], 8 offen + buffer_atomic_add v53, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v19, s[0:3], 0 offen + buffer_atomic_add v55, v19, s[0:3], 4 offen + buffer_atomic_add v56, v19, s[0:3], 8 offen + buffer_atomic_add v57, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v19, s[0:3], 0 offen + buffer_atomic_add v59, v19, s[0:3], 4 offen + buffer_atomic_add v60, v19, s[0:3], 8 offen + buffer_atomic_add v61, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v19, s[0:3], 0 offen + buffer_atomic_add v63, v19, s[0:3], 4 offen + buffer_atomic_add v64, v19, s[0:3], 8 offen + buffer_atomic_add v65, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v19, s[0:3], 0 offen + buffer_atomic_add v67, v19, s[0:3], 4 offen + buffer_atomic_add v68, v19, s[0:3], 8 offen + buffer_atomic_add v69, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v19, s[0:3], 0 offen + buffer_atomic_add v71, v19, s[0:3], 4 offen + buffer_atomic_add v72, v19, s[0:3], 8 offen + buffer_atomic_add v73, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v19, s[0:3], 0 offen + buffer_atomic_add v75, v19, s[0:3], 4 offen + buffer_atomic_add v76, v19, s[0:3], 8 offen + buffer_atomic_add v77, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v19, s[0:3], 0 offen + buffer_atomic_add v79, v19, s[0:3], 4 offen + buffer_atomic_add v80, v19, s[0:3], 8 offen + buffer_atomic_add v81, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v19, s[0:3], 0 offen + buffer_atomic_add v83, v19, s[0:3], 4 offen + buffer_atomic_add v84, v19, s[0:3], 8 offen + buffer_atomic_add v85, v19, s[0:3], 12 offen + v_add_lshl_u32 v18, v18, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v18, s[0:3], 0 offen + buffer_atomic_add v87, v18, s[0:3], 4 offen + buffer_atomic_add v88, v18, s[0:3], 8 offen + buffer_atomic_add v89, v18, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB37_12 +.LBB37_14: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_add_u32_e32 v0, s3, v22 + s_barrier + v_lshl_or_b32 v0, v0, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v82, v0, v21, s3 + ds_write_b32 v82, a176 + ds_write_b32 v82, a177 offset:256 + ds_write_b32 v82, a178 offset:512 + ds_write_b32 v82, a179 offset:768 + ds_write_b32 v82, a180 offset:2048 + ds_write_b32 v82, a181 offset:2304 + ds_write_b32 v82, a182 offset:2560 + ds_write_b32 v82, a183 offset:2816 + ds_write_b32 v82, a184 offset:4096 + ds_write_b32 v82, a185 offset:4352 + ds_write_b32 v82, a186 offset:4608 + ds_write_b32 v82, a187 offset:4864 + ds_write_b32 v82, a188 offset:6144 + ds_write_b32 v82, a189 offset:6400 + ds_write_b32 v82, a190 offset:6656 + ds_write_b32 v82, a191 offset:6912 + ds_write_b32 v82, a192 offset:16384 + ds_write_b32 v82, a193 offset:16640 + ds_write_b32 v82, a194 offset:16896 + ds_write_b32 v82, a195 offset:17152 + ds_write_b32 v82, a196 offset:18432 + ds_write_b32 v82, a197 offset:18688 + ds_write_b32 v82, a198 offset:18944 + ds_write_b32 v82, a199 offset:19200 + ds_write_b32 v82, a200 offset:20480 + ds_write_b32 v82, a201 offset:20736 + ds_write_b32 v82, a202 offset:20992 + ds_write_b32 v82, a203 offset:21248 + ds_write_b32 v82, a204 offset:22528 + ds_write_b32 v82, a205 offset:22784 + ds_write_b32 v82, a206 offset:23040 + ds_write_b32 v82, a207 offset:23296 + ds_write_b32 v82, a208 offset:32768 + ds_write_b32 v82, a209 offset:33024 + ds_write_b32 v82, a210 offset:33280 + ds_write_b32 v82, a211 offset:33536 + ds_write_b32 v82, a212 offset:34816 + ds_write_b32 v82, a213 offset:35072 + ds_write_b32 v82, a214 offset:35328 + ds_write_b32 v82, a215 offset:35584 + ds_write_b32 v82, a216 offset:36864 + ds_write_b32 v82, a217 offset:37120 + ds_write_b32 v82, a218 offset:37376 + ds_write_b32 v82, a219 offset:37632 + ds_write_b32 v82, a220 offset:38912 + ds_write_b32 v82, a221 offset:39168 + ds_write_b32 v82, a222 offset:39424 + ds_write_b32 v82, a223 offset:39680 + ds_write_b32 v82, a224 offset:49152 + ds_write_b32 v82, a225 offset:49408 + ds_write_b32 v82, a226 offset:49664 + ds_write_b32 v82, a227 offset:49920 + ds_write_b32 v82, a228 offset:51200 + ds_write_b32 v82, a229 offset:51456 + ds_write_b32 v82, a230 offset:51712 + ds_write_b32 v82, a231 offset:51968 + ds_write_b32 v82, a232 offset:53248 + ds_write_b32 v82, a233 offset:53504 + ds_write_b32 v82, a234 offset:53760 + ds_write_b32 v82, a235 offset:54016 + ds_write_b32 v82, a236 offset:55296 + ds_write_b32 v82, a237 offset:55552 + ds_write_b32 v82, a238 offset:55808 + ds_write_b32 v82, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 60, v20 + s_andn2_b32 s2, s2, 63 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 8, v1 + v_lshl_or_b32 v83, v0, 2, v18 + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v0, s21, v0 + v_mad_u64_u32 v[0:1], s[2:3], v1, s16, v[0:1] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a112 + ds_write_b32 v82, a113 offset:256 + ds_write_b32 v82, a114 offset:512 + ds_write_b32 v82, a115 offset:768 + ds_write_b32 v82, a116 offset:2048 + ds_write_b32 v82, a117 offset:2304 + ds_write_b32 v82, a118 offset:2560 + ds_write_b32 v82, a119 offset:2816 + ds_write_b32 v82, a120 offset:4096 + ds_write_b32 v82, a121 offset:4352 + ds_write_b32 v82, a122 offset:4608 + ds_write_b32 v82, a123 offset:4864 + ds_write_b32 v82, a124 offset:6144 + ds_write_b32 v82, a125 offset:6400 + ds_write_b32 v82, a126 offset:6656 + ds_write_b32 v82, a127 offset:6912 + ds_write_b32 v82, a128 offset:16384 + ds_write_b32 v82, a129 offset:16640 + ds_write_b32 v82, a130 offset:16896 + ds_write_b32 v82, a131 offset:17152 + ds_write_b32 v82, a132 offset:18432 + ds_write_b32 v82, a133 offset:18688 + ds_write_b32 v82, a134 offset:18944 + ds_write_b32 v82, a135 offset:19200 + ds_write_b32 v82, a136 offset:20480 + ds_write_b32 v82, a137 offset:20736 + ds_write_b32 v82, a138 offset:20992 + ds_write_b32 v82, a139 offset:21248 + ds_write_b32 v82, a140 offset:22528 + ds_write_b32 v82, a141 offset:22784 + ds_write_b32 v82, a142 offset:23040 + ds_write_b32 v82, a143 offset:23296 + ds_write_b32 v82, a144 offset:32768 + ds_write_b32 v82, a145 offset:33024 + ds_write_b32 v82, a146 offset:33280 + ds_write_b32 v82, a147 offset:33536 + ds_write_b32 v82, a148 offset:34816 + ds_write_b32 v82, a149 offset:35072 + ds_write_b32 v82, a150 offset:35328 + ds_write_b32 v82, a151 offset:35584 + ds_write_b32 v82, a152 offset:36864 + ds_write_b32 v82, a153 offset:37120 + ds_write_b32 v82, a154 offset:37376 + ds_write_b32 v82, a155 offset:37632 + ds_write_b32 v82, a156 offset:38912 + ds_write_b32 v82, a157 offset:39168 + ds_write_b32 v82, a158 offset:39424 + ds_write_b32 v82, a159 offset:39680 + ds_write_b32 v82, a160 offset:49152 + ds_write_b32 v82, a161 offset:49408 + ds_write_b32 v82, a162 offset:49664 + ds_write_b32 v82, a163 offset:49920 + ds_write_b32 v82, a164 offset:51200 + ds_write_b32 v82, a165 offset:51456 + ds_write_b32 v82, a166 offset:51712 + ds_write_b32 v82, a167 offset:51968 + ds_write_b32 v82, a168 offset:53248 + ds_write_b32 v82, a169 offset:53504 + ds_write_b32 v82, a170 offset:53760 + ds_write_b32 v82, a171 offset:54016 + ds_write_b32 v82, a172 offset:55296 + ds_write_b32 v82, a173 offset:55552 + ds_write_b32 v82, a174 offset:55808 + ds_write_b32 v82, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 64, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a48 + ds_write_b32 v82, a49 offset:256 + ds_write_b32 v82, a50 offset:512 + ds_write_b32 v82, a51 offset:768 + ds_write_b32 v82, a52 offset:2048 + ds_write_b32 v82, a53 offset:2304 + ds_write_b32 v82, a54 offset:2560 + ds_write_b32 v82, a55 offset:2816 + ds_write_b32 v82, a56 offset:4096 + ds_write_b32 v82, a57 offset:4352 + ds_write_b32 v82, a58 offset:4608 + ds_write_b32 v82, a59 offset:4864 + ds_write_b32 v82, a60 offset:6144 + ds_write_b32 v82, a61 offset:6400 + ds_write_b32 v82, a62 offset:6656 + ds_write_b32 v82, a63 offset:6912 + ds_write_b32 v82, a64 offset:16384 + ds_write_b32 v82, a65 offset:16640 + ds_write_b32 v82, a66 offset:16896 + ds_write_b32 v82, a67 offset:17152 + ds_write_b32 v82, a68 offset:18432 + ds_write_b32 v82, a69 offset:18688 + ds_write_b32 v82, a70 offset:18944 + ds_write_b32 v82, a71 offset:19200 + ds_write_b32 v82, a72 offset:20480 + ds_write_b32 v82, a73 offset:20736 + ds_write_b32 v82, a74 offset:20992 + ds_write_b32 v82, a75 offset:21248 + ds_write_b32 v82, a76 offset:22528 + ds_write_b32 v82, a77 offset:22784 + ds_write_b32 v82, a78 offset:23040 + ds_write_b32 v82, a79 offset:23296 + ds_write_b32 v82, a80 offset:32768 + ds_write_b32 v82, a81 offset:33024 + ds_write_b32 v82, a82 offset:33280 + ds_write_b32 v82, a83 offset:33536 + ds_write_b32 v82, a84 offset:34816 + ds_write_b32 v82, a85 offset:35072 + ds_write_b32 v82, a86 offset:35328 + ds_write_b32 v82, a87 offset:35584 + ds_write_b32 v82, a88 offset:36864 + ds_write_b32 v82, a89 offset:37120 + ds_write_b32 v82, a90 offset:37376 + ds_write_b32 v82, a91 offset:37632 + ds_write_b32 v82, a92 offset:38912 + ds_write_b32 v82, a93 offset:39168 + ds_write_b32 v82, a94 offset:39424 + ds_write_b32 v82, a95 offset:39680 + ds_write_b32 v82, a96 offset:49152 + ds_write_b32 v82, a97 offset:49408 + ds_write_b32 v82, a98 offset:49664 + ds_write_b32 v82, a99 offset:49920 + ds_write_b32 v82, a100 offset:51200 + ds_write_b32 v82, a101 offset:51456 + ds_write_b32 v82, a102 offset:51712 + ds_write_b32 v82, a103 offset:51968 + ds_write_b32 v82, a104 offset:53248 + ds_write_b32 v82, a105 offset:53504 + ds_write_b32 v82, a106 offset:53760 + ds_write_b32 v82, a107 offset:54016 + ds_write_b32 v82, a108 offset:55296 + ds_write_b32 v82, a109 offset:55552 + ds_write_b32 v82, a110 offset:55808 + ds_write_b32 v82, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 0x80, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a0 + ds_write_b32 v82, a1 offset:256 + ds_write_b32 v82, a2 offset:512 + ds_write_b32 v82, a3 offset:768 + ds_write_b32 v82, a4 offset:2048 + ds_write_b32 v82, a5 offset:2304 + ds_write_b32 v82, a6 offset:2560 + ds_write_b32 v82, a7 offset:2816 + ds_write_b32 v82, a8 offset:4096 + ds_write_b32 v82, a9 offset:4352 + ds_write_b32 v82, a10 offset:4608 + ds_write_b32 v82, a11 offset:4864 + ds_write_b32 v82, a12 offset:6144 + ds_write_b32 v82, a13 offset:6400 + ds_write_b32 v82, a14 offset:6656 + ds_write_b32 v82, a15 offset:6912 + ds_write_b32 v82, a16 offset:16384 + ds_write_b32 v82, a17 offset:16640 + ds_write_b32 v82, a18 offset:16896 + ds_write_b32 v82, a19 offset:17152 + ds_write_b32 v82, a20 offset:18432 + ds_write_b32 v82, a21 offset:18688 + ds_write_b32 v82, a22 offset:18944 + ds_write_b32 v82, a23 offset:19200 + ds_write_b32 v82, a24 offset:20480 + ds_write_b32 v82, a25 offset:20736 + ds_write_b32 v82, a26 offset:20992 + ds_write_b32 v82, a27 offset:21248 + ds_write_b32 v82, a28 offset:22528 + ds_write_b32 v82, a29 offset:22784 + ds_write_b32 v82, a30 offset:23040 + ds_write_b32 v82, a31 offset:23296 + ds_write_b32 v82, a32 offset:32768 + ds_write_b32 v82, a33 offset:33024 + ds_write_b32 v82, a34 offset:33280 + ds_write_b32 v82, a35 offset:33536 + ds_write_b32 v82, a36 offset:34816 + ds_write_b32 v82, a37 offset:35072 + ds_write_b32 v82, a38 offset:35328 + ds_write_b32 v82, a39 offset:35584 + ds_write_b32 v82, a40 offset:36864 + ds_write_b32 v82, a41 offset:37120 + ds_write_b32 v82, a42 offset:37376 + ds_write_b32 v82, a43 offset:37632 + ds_write_b32 v82, a44 offset:38912 + ds_write_b32 v82, a45 offset:39168 + ds_write_b32 v82, a46 offset:39424 + ds_write_b32 v82, a47 offset:39680 + ds_write2st64_b32 v82, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v82, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v82, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v82, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v82, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v82, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v82, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v82, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[2:5], v83 + ds_read_b128 v[6:9], v83 offset:256 + ds_read_b128 v[10:13], v83 offset:512 + ds_read_b128 v[14:17], v83 offset:768 + ds_read_b128 v[18:21], v83 offset:1024 + ds_read_b128 v[22:25], v83 offset:1280 + ds_read_b128 v[26:29], v83 offset:1536 + ds_read_b128 v[30:33], v83 offset:1792 + ds_read_b128 v[34:37], v83 offset:2048 + ds_read_b128 v[38:41], v83 offset:2304 + ds_read_b128 v[42:45], v83 offset:2560 + ds_read_b128 v[46:49], v83 offset:2816 + ds_read_b128 v[50:53], v83 offset:3072 + ds_read_b128 v[54:57], v83 offset:3328 + ds_read_b128 v[58:61], v83 offset:3584 + ds_read_b128 v[62:65], v83 offset:3840 + v_add_u32_e32 v0, 0xc0, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[2:5], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + buffer_store_dwordx4 v[6:9], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[10:13], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[14:17], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[26:29], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[30:33], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[34:37], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[38:41], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[42:45], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[46:49], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[50:53], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[54:57], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[58:61], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 424 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 168 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end37: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end37-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 168 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 26 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEaNS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 23032 +; TotalNumSgprs: 32 +; NumVgprs: 168 +; NumAgprs: 256 +; TotalNumVgprs: 424 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 52 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 424 +; AccumOffset: 168 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 41 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v6, 0 + global_load_ushort v1, v6, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v2, s3 + v_rcp_iflag_f32_e32 v2, v2 + s_nop 0 + v_mul_f32_e32 v2, 0x4f7ffffe, v2 + v_cvt_u32_f32_e32 v2, v2 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v3, s8, v2 + v_mul_hi_u32 v3, v2, v3 + v_add_u32_e32 v2, v2, v3 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v1, s2, v1 + v_add_u32_e32 v0, v1, v0 + v_xor_b32_e32 v1, s5, v0 + v_sub_u32_e32 v3, 0, v0 + v_ashrrev_i32_e32 v1, 31, v1 + v_max_i32_e32 v3, v0, v3 + v_mul_hi_u32 v2, v3, v2 + v_mul_lo_u32 v4, v2, s3 + v_add_u32_e32 v5, 1, v2 + v_sub_u32_e32 v3, v3, v4 + v_cmp_le_u32_e32 vcc, s3, v3 + s_nop 1 + v_cndmask_b32_e32 v2, v2, v5, vcc + v_subrev_u32_e32 v4, s3, v3 + v_cndmask_b32_e32 v3, v3, v4, vcc + v_add_u32_e32 v4, 1, v2 + v_cmp_le_u32_e32 vcc, s3, v3 + s_nop 1 + v_cndmask_b32_e32 v2, v2, v4, vcc + v_xor_b32_e32 v2, v2, v1 + v_sub_u32_e32 v1, v2, v1 + v_cmp_gt_i32_e32 vcc, s4, v1 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB38_10 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v1, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB38_9 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v2, v1, s7 + s_cmp_eq_u32 s6, 1 + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v4, v0, s2 + s_cbranch_scc1 .LBB38_6 +; %bb.3: ; %vector.ph + s_and_b32 s2, s6, 0x7ffffffe + s_mov_b32 s0, 0 + v_mov_b32_e32 v3, 0 + v_mov_b32_e32 v5, 0 +.LBB38_4: ; %vector.body + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v6, s0, v2 + v_add_u32_e32 v8, s0, v4 + v_ashrrev_i32_e32 v7, 31, v6 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[6:7], s[8:9], 0, v[6:7] + v_lshl_add_u64 v[8:9], s[10:11], 0, v[8:9] + global_load_ushort v10, v[6:7], off + global_load_ushort v11, v[8:9], off + s_add_i32 s0, s0, 2 + s_cmp_lg_u32 s0, s2 + s_waitcnt vmcnt(1) + v_lshrrev_b16_e32 v6, 8, v10 + v_bfe_i32 v7, v10, 0, 8 + s_waitcnt vmcnt(0) + v_lshrrev_b16_e32 v8, 8, v11 + v_bfe_i32 v9, v11, 0, 8 + v_bfe_i32 v6, v6, 0, 8 + v_bfe_i32 v8, v8, 0, 8 + v_mad_i32_i24 v3, v9, v7, v3 + v_mad_i32_i24 v5, v8, v6, v5 + s_cbranch_scc1 .LBB38_4 +; %bb.5: ; %middle.block + v_add_u32_e32 v6, v3, v5 + s_cmp_lg_u32 s6, s2 + s_cselect_b64 s[0:1], -1, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB38_7 + s_branch .LBB38_9 +.LBB38_6: + s_mov_b32 s2, 0 + v_mov_b32_e32 v6, 0 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB38_9 +.LBB38_7: ; %scalar.ph.preheader + s_sub_i32 s0, s6, s2 + v_ashrrev_i32_e32 v5, 31, v4 + s_add_u32 s4, s10, s2 + s_addc_u32 s5, s11, 0 + v_lshl_add_u64 v[4:5], s[4:5], 0, v[4:5] + v_ashrrev_i32_e32 v3, 31, v2 + s_add_u32 s4, s8, s2 + s_addc_u32 s5, s9, 0 + v_lshl_add_u64 v[2:3], s[4:5], 0, v[2:3] +.LBB38_8: ; %scalar.ph + ; =>This Inner Loop Header: Depth=1 + global_load_sbyte v7, v[2:3], off + global_load_sbyte v8, v[4:5], off + s_add_i32 s0, s0, -1 + v_lshl_add_u64 v[4:5], v[4:5], 0, 1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + s_cmp_eq_u32 s0, 0 + s_waitcnt vmcnt(0) + v_mad_i32_i24 v6, v8, v7, v6 + s_cbranch_scc0 .LBB38_8 +.LBB38_9: ; %._crit_edge + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[0:1], s[0:1], v1, s3, v[0:1] + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] + global_store_dword v[0:1], v6, off +.LBB38_10: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 12 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end38: + .size _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end38-_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 12 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorENS2_11ColumnMajorES3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 636 +; TotalNumSgprs: 20 +; NumVgprs: 12 +; NumAgprs: 0 +; TotalNumVgprs: 12 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 12 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v1, s15 + s_load_dword s22, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v2, 0 + v_rcp_iflag_f32_e32 v1, v1 + v_mov_b32_e32 v3, s5 + global_store_dword v2, v3, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v1 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s20, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s20, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s20, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v1, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s21, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v1, v1 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s18, v1 + s_mul_i32 s15, s15, s18 + s_mul_hi_u32 s15, s18, s15 + s_add_i32 s18, s18, s15 + s_mul_hi_u32 s15, s14, s18 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s2, s17, s2 + s_add_i32 s14, s17, -1 + s_add_i32 s13, s13, s14 + s_xor_b32 s15, s13, s17 + s_ashr_i32 s15, s15, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s18, s13, s18 + s_mul_i32 s19, s18, s12 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s23, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s19, s18 + s_xor_b32 s12, s12, s15 + s_sub_i32 s12, s12, s15 + s_max_i32 s12, s12, 1 + s_lshl_b32 s12, s12, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s15, s2, s3 + s_mul_i32 s15, s12, s15 + s_sub_i32 s18, s3, s2 + s_max_i32 s18, s18, 0 + s_mul_i32 s18, s13, s18 + s_add_i32 s15, s18, s15 + s_mul_i32 s18, s15, s22 + s_sub_i32 s6, s6, s15 + s_cmp_lt_i32 s3, s2 + s_cselect_b32 s2, s12, s13 + s_cmp_eq_u32 s3, s14 + s_cselect_b32 s6, s6, s2 + s_ashr_i32 s2, s15, 31 + s_add_u32 s8, s8, s15 + s_addc_u32 s9, s9, s2 + s_ashr_i32 s2, s18, 31 + s_add_u32 s12, s10, s18 + s_addc_u32 s13, s11, s2 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s10, s2, 1 + s_mul_i32 s2, s22, s3 + s_add_i32 s3, s5, -1 + s_add_u32 s2, s3, s2 + s_add_u32 s14, s2, 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s18, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[24:25], -1, 0 + v_cndmask_b32_e64 v1, 0, 1, s[24:25] + s_nop 0 + v_readfirstlane_b32 s11, v1 + s_bitcmp0_b32 s11, 0 + v_mbcnt_lo_u32_b32 v1, -1, 0 + v_mbcnt_hi_u32_b32 v1, -1, v1 + v_and_b32_e32 v30, 31, v1 + v_lshlrev_b32_e32 v11, 3, v1 + v_lshrrev_b32_e32 v9, 5, v1 + v_lshlrev_b32_e32 v12, 4, v1 + v_lshrrev_b32_e32 v10, 2, v1 + v_and_b32_e32 v8, 15, v1 + s_cbranch_scc0 .LBB39_2 +; %bb.1: + v_readfirstlane_b32 s15, v0 + v_and_b32_e32 v2, 48, v12 + v_and_b32_e32 v3, 0x7c, v1 + s_and_b32 s11, s15, 0xffffffc0 + v_add_u32_e32 v28, s11, v3 + v_add_u32_e32 v3, s20, v28 + v_mad_u64_u32 v[4:5], s[24:25], v3, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[52:55], v4, s[8:11], 0 offen + v_add_u32_e32 v3, s7, v4 + buffer_load_dwordx4 v[56:59], v3, s[8:11], 0 offen + v_and_or_b32 v13, v11, 8, v9 + v_lshlrev_b32_e32 v29, 3, v9 + v_add_u32_e32 v3, s7, v3 + buffer_load_dwordx4 v[60:63], v3, s[8:11], 0 offen + v_and_b32_e32 v5, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v6, 12, v9 + s_lshr_b32 s19, s15, 2 + s_lshr_b32 s23, s15, 1 + v_lshl_or_b32 v24, v8, 7, v6 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v31, 3, v2 + s_and_b32 s24, s19, 0x3fffffe0 + s_and_b32 s19, s19, 0x3ffffff0 + v_and_or_b32 v2, s23, 32, v30 + v_or_b32_e32 v32, 1, v31 + v_or_b32_e32 v14, s24, v30 + v_add_u32_e32 v33, s19, v5 + v_lshrrev_b32_e32 v15, 4, v2 + v_ashrrev_i32_e32 v34, 1, v28 + v_ashrrev_i32_e32 v16, 31, v28 + v_lshlrev_b32_e32 v35, 6, v28 + v_or_b32_e32 v36, 1, v28 + v_sub_u32_e32 v37, v31, v32 + v_lshrrev_b32_e32 v38, 31, v28 + v_add_u32_e32 v2, s7, v3 + buffer_load_dwordx4 v[64:67], v2, s[8:11], 0 offen + v_lshrrev_b32_e32 v39, 1, v14 + v_bfe_u32 v40, v14, 1, 4 + v_mad_u64_u32 v[6:7], s[24:25], v33, s22, v[4:5] + v_xor_b32_e32 v41, v15, v8 + buffer_load_dwordx4 v[2:5], v6, s[12:15], 0 offen + v_lshrrev_b32_e32 v7, 28, v16 + v_add_u32_e32 v42, v36, v38 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[16:19], v6, s[12:15], 0 offen + v_or_b32_e32 v43, 1, v34 + v_xor_b32_e32 v44, v40, v13 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[20:23], v6, s[12:15], 0 offen + v_lshlrev_b32_e32 v45, 7, v39 + v_lshl_or_b32 v46, v41, 2, v24 + v_add_u32_e32 v6, s22, v6 + buffer_load_dwordx4 v[24:27], v6, s[12:15], 0 offen + v_add_u32_e32 v6, v34, v7 + v_ashrrev_i32_e32 v47, 1, v42 + v_and_b32_e32 v48, 0x1ffffffe, v42 + v_ashrrev_i32_e32 v42, 31, v42 + v_and_b32_e32 v6, -16, v6 + v_sub_u32_e32 v49, v47, v34 + v_sub_u32_e32 v36, v36, v48 + v_lshrrev_b32_e32 v42, 28, v42 + v_sub_u32_e32 v48, v43, v47 + v_sub_u32_e32 v6, v34, v6 + v_lshl_or_b32 v34, v36, 3, v32 + v_add_u32_e32 v36, v47, v42 + v_xor_b32_e32 v42, v6, v31 + v_xor_b32_e32 v6, v6, v32 + v_add_u32_e32 v50, v34, v37 + v_and_b32_e32 v36, -16, v36 + v_lshl_add_u32 v42, v42, 3, v35 + v_lshl_add_u32 v35, v6, 3, v35 + v_sub_u32_e32 v36, v47, v36 + v_xor_b32_e32 v47, v50, v36 + v_lshl_add_u32 v49, v49, 7, v35 + v_xor_b32_e32 v34, v34, v36 + v_sub_u32_e32 v36, v47, v6 + v_sub_u32_e32 v6, v34, v6 + v_lshl_add_u32 v36, v36, 3, v49 + v_lshl_add_u32 v6, v6, 3, v49 + s_waitcnt vmcnt(7) + ds_write_b64 v42, v[52:53] + ds_write_b64 v35, v[54:55] + s_waitcnt vmcnt(6) + ds_write_b64 v36, v[56:57] + ds_write_b64 v6, v[58:59] + v_add_u32_e32 v7, v43, v7 + v_and_b32_e32 v7, -16, v7 + v_sub_u32_e32 v7, v43, v7 + v_xor_b32_e32 v31, v7, v31 + v_sub_u32_e32 v34, v31, v34 + v_lshlrev_b32_e32 v34, 3, v34 + v_lshlrev_b32_e32 v35, 7, v48 + v_add3_u32 v6, v34, v35, v6 + s_waitcnt vmcnt(5) + ds_write_b64 v6, v[60:61] + v_xor_b32_e32 v7, v7, v32 + v_sub_u32_e32 v31, v7, v31 + v_lshl_add_u32 v6, v31, 3, v6 + ds_write_b64 v6, v[62:63] + v_or_b32_e32 v28, 3, v28 + v_add_u32_e32 v31, v28, v38 + v_ashrrev_i32_e32 v34, 1, v31 + v_sub_u32_e32 v35, v34, v43 + v_and_b32_e32 v36, 0x1ffffffe, v31 + v_sub_u32_e32 v28, v28, v36 + v_lshl_or_b32 v28, v28, 3, v32 + v_add_u32_e32 v32, v28, v37 + v_ashrrev_i32_e32 v31, 31, v31 + v_lshrrev_b32_e32 v31, 28, v31 + v_add_u32_e32 v31, v34, v31 + v_and_b32_e32 v31, -16, v31 + v_sub_u32_e32 v31, v34, v31 + v_xor_b32_e32 v32, v32, v31 + v_sub_u32_e32 v7, v32, v7 + v_lshlrev_b32_e32 v7, 3, v7 + v_lshlrev_b32_e32 v34, 7, v35 + v_add3_u32 v6, v7, v34, v6 + s_waitcnt vmcnt(4) + ds_write_b64 v6, v[64:65] + v_xor_b32_e32 v7, v28, v31 + v_sub_u32_e32 v7, v7, v32 + v_lshl_add_u32 v6, v7, 3, v6 + ds_write_b64 v6, v[66:67] + s_mov_b32 s11, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v2, v2, v2, s11 + v_perm_b32 v3, v3, v3, s11 + v_perm_b32 v4, v4, v4, s11 + v_perm_b32 v5, v5, v5, s11 + s_waitcnt vmcnt(2) + v_perm_b32 v6, v16, v16, s11 + v_perm_b32 v7, v17, v17, s11 + v_perm_b32 v16, v18, v18, s11 + v_perm_b32 v17, v19, v19, s11 + s_waitcnt vmcnt(1) + v_perm_b32 v18, v20, v20, s11 + v_perm_b32 v19, v21, v21, s11 + v_perm_b32 v20, v22, v22, s11 + v_perm_b32 v21, v23, v23, s11 + s_waitcnt vmcnt(0) + v_perm_b32 v22, v24, v24, s11 + v_perm_b32 v23, v25, v25, s11 + v_perm_b32 v24, v26, v26, s11 + v_perm_b32 v25, v27, v27, s11 + s_mov_b32 s11, 0x5010400 + v_perm_b32 v26, v6, v2, s11 + v_perm_b32 v27, v22, v18, s11 + s_mov_b32 s15, 0x5040100 + v_perm_b32 v28, v27, v26, s15 + s_mov_b32 s19, 0x7060302 + v_perm_b32 v26, v27, v26, s19 + s_mov_b32 s23, 0x7030602 + v_perm_b32 v2, v6, v2, s23 + v_perm_b32 v6, v22, v18, s23 + v_perm_b32 v18, v6, v2, s15 + v_perm_b32 v2, v6, v2, s19 + v_perm_b32 v6, v7, v3, s11 + v_perm_b32 v22, v23, v19, s11 + v_perm_b32 v27, v22, v6, s15 + v_perm_b32 v6, v22, v6, s19 + v_perm_b32 v3, v7, v3, s23 + v_perm_b32 v7, v23, v19, s23 + v_perm_b32 v19, v7, v3, s15 + v_perm_b32 v3, v7, v3, s19 + v_perm_b32 v7, v16, v4, s11 + v_perm_b32 v22, v24, v20, s11 + v_perm_b32 v23, v22, v7, s15 + v_perm_b32 v7, v22, v7, s19 + v_perm_b32 v4, v16, v4, s23 + v_perm_b32 v16, v24, v20, s23 + v_perm_b32 v20, v16, v4, s15 + v_perm_b32 v4, v16, v4, s19 + v_perm_b32 v16, v17, v5, s11 + v_perm_b32 v22, v25, v21, s11 + v_perm_b32 v24, v22, v16, s15 + v_perm_b32 v16, v22, v16, s19 + v_perm_b32 v5, v17, v5, s23 + v_perm_b32 v17, v25, v21, s23 + v_perm_b32 v21, v17, v5, s15 + v_perm_b32 v5, v17, v5, s19 + v_lshrrev_b32_e32 v17, 1, v33 + v_and_b32_e32 v17, 16, v17 + v_xor_b32_e32 v22, v17, v30 + v_lshlrev_b32_e32 v25, 9, v33 + v_and_b32_e32 v25, 0x3000, v25 + v_lshlrev_b32_e32 v31, 6, v33 + s_movk_i32 s11, 0xf800 + v_and_b32_e32 v31, 0xfffff800, v31 + v_add_u32_e32 v25, v25, v31 + v_lshl_or_b32 v25, v22, 2, v25 + ds_write_b32 v25, v28 offset:16384 + v_or_b32_e32 v28, 1, v17 + v_xor_b32_e32 v28, v28, v30 + v_sub_u32_e32 v22, v28, v22 + v_lshl_add_u32 v22, v22, 2, v25 + v_or_b32_e32 v25, 2, v17 + v_xor_b32_e32 v25, v25, v30 + v_sub_u32_e32 v28, v25, v28 + v_lshl_add_u32 v28, v28, 2, v22 + ds_write_b32 v22, v26 offset:16512 + v_or_b32_e32 v22, 3, v17 + v_xor_b32_e32 v22, v22, v30 + v_sub_u32_e32 v25, v22, v25 + v_lshlrev_b32_e32 v25, 2, v25 + v_add3_u32 v25, v28, s18, v25 + ds_write_b32 v28, v18 offset:16640 + v_or_b32_e32 v18, 4, v17 + v_xor_b32_e32 v18, v18, v30 + v_sub_u32_e32 v22, v18, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v22, v25, s18, v22 + ds_write_b32 v25, v2 offset:16640 + v_or_b32_e32 v2, 5, v17 + v_xor_b32_e32 v2, v2, v30 + v_sub_u32_e32 v18, v2, v18 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v22, s18, v18 + ds_write_b32 v22, v27 offset:16640 + v_or_b32_e32 v22, 6, v17 + v_xor_b32_e32 v22, v22, v30 + v_sub_u32_e32 v2, v22, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v18, s18, v2 + ds_write_b32 v18, v6 offset:16640 + v_or_b32_e32 v6, 7, v17 + v_xor_b32_e32 v6, v6, v30 + v_sub_u32_e32 v18, v6, v22 + v_lshlrev_b32_e32 v18, 2, v18 + v_add3_u32 v18, v2, s18, v18 + ds_write_b32 v2, v19 offset:16640 + v_or_b32_e32 v2, 8, v17 + v_xor_b32_e32 v2, v2, v30 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v18, s18, v6 + ds_write_b32 v18, v3 offset:16640 + v_or_b32_e32 v3, 9, v17 + v_xor_b32_e32 v3, v3, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v23 offset:16640 + v_or_b32_e32 v6, 10, v17 + v_xor_b32_e32 v6, v6, v30 + v_sub_u32_e32 v3, v6, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v7 offset:16640 + v_or_b32_e32 v2, 11, v17 + v_xor_b32_e32 v2, v2, v30 + v_sub_u32_e32 v6, v2, v6 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v6, v3, s18, v6 + ds_write_b32 v3, v20 offset:16640 + v_or_b32_e32 v3, 12, v17 + v_xor_b32_e32 v3, v3, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v2, v6, s18, v2 + ds_write_b32 v6, v4 offset:16640 + v_or_b32_e32 v4, 13, v17 + v_xor_b32_e32 v4, v4, v30 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v3, v2, s18, v3 + ds_write_b32 v2, v24 offset:16640 + v_or_b32_e32 v2, 14, v17 + v_xor_b32_e32 v2, v2, v30 + v_sub_u32_e32 v4, v2, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_add3_u32 v4, v3, s18, v4 + ds_write_b32 v3, v16 offset:16640 + v_or_b32_e32 v3, 15, v17 + v_xor_b32_e32 v3, v3, v30 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v2, v2, 2, v4 + ds_write_b32 v4, v21 offset:16640 + ds_write_b32 v2, v5 offset:16768 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshl_or_b32 v2, v44, 3, v45 + v_add_u32_e32 v26, 2, v13 + v_xor_b32_e32 v3, v40, v26 + v_lshl_or_b32 v3, v3, 3, v45 + v_or_b32_e32 v27, 4, v13 + v_xor_b32_e32 v4, v40, v27 + v_lshl_or_b32 v18, v4, 3, v45 + v_add_u32_e32 v16, 6, v13 + v_xor_b32_e32 v22, v40, v16 + v_lshl_add_u32 v17, v22, 3, v45 + v_add_u32_e32 v4, 64, v14 + v_lshrrev_b32_e32 v23, 1, v4 + v_sub_u32_e32 v19, v23, v39 + v_bfe_u32 v24, v4, 1, 4 + v_xor_b32_e32 v4, v24, v13 + v_sub_u32_e32 v20, v4, v22 + ds_read_b64 v[6:7], v2 + ds_read_b64 v[4:5], v3 + ds_read_b64 v[2:3], v18 + ds_read_b32 v76, v46 offset:16384 + v_lshrrev_b16_e32 v18, 3, v29 + v_or_b32_e32 v21, 16, v15 + v_xor_b32_e32 v25, v21, v8 + v_sub_u32_e32 v28, v25, v41 + v_lshlrev_b32_e32 v28, 2, v28 + v_sub_u32_e32 v31, v18, v9 + v_lshlrev_b32_e32 v31, 12, v31 + v_add3_u32 v28, v46, v31, v28 + v_add_u32_e32 v31, 16, v29 + v_lshrrev_b32_e32 v32, 5, v31 + v_lshrrev_b16_e32 v31, 3, v31 + v_and_b32_e32 v31, 3, v31 + v_sub_u16_e32 v33, v31, v18 + v_bfe_i32 v33, v33, 0, 16 + v_lshlrev_b32_e32 v34, 4, v32 + v_or_b32_e32 v35, v34, v8 + v_and_b32_e32 v35, 31, v35 + v_xor_b32_e32 v35, v15, v35 + v_sub_u32_e32 v25, v35, v25 + v_lshlrev_b32_e32 v36, 11, v32 + v_lshlrev_b32_e32 v25, 2, v25 + v_lshl_or_b32 v33, v33, 12, v36 + v_add3_u32 v25, v25, v33, v28 + v_add_u32_e32 v36, 20, v29 + v_lshrrev_b32_e32 v37, 5, v36 + v_sub_u32_e32 v32, v37, v32 + v_lshrrev_b16_e32 v36, 3, v36 + v_and_b32_e32 v36, 3, v36 + v_sub_u16_e32 v31, v36, v31 + v_bfe_i32 v31, v31, 0, 16 + v_lshlrev_b32_e32 v38, 4, v37 + v_or_b32_e32 v39, v38, v8 + v_and_b32_e32 v39, 31, v39 + v_xor_b32_e32 v39, v21, v39 + v_sub_u32_e32 v35, v39, v35 + v_lshlrev_b32_e32 v32, 11, v32 + v_lshlrev_b32_e32 v35, 2, v35 + v_lshl_add_u32 v31, v31, 12, v32 + v_add3_u32 v32, v35, v31, v25 + v_sub_u16_e32 v35, v18, v36 + v_bfe_i32 v35, v35, 0, 16 + v_or_b32_e32 v36, 16, v8 + v_xor_b32_e32 v40, v15, v36 + v_sub_u32_e32 v39, v40, v39 + v_lshlrev_b32_e32 v37, 11, v37 + v_xor_b32_e32 v37, 0x800, v37 + v_lshlrev_b32_e32 v39, 2, v39 + v_lshl_add_u32 v35, v35, 12, v37 + v_add3_u32 v37, v39, v35, v32 + v_xor_b32_e32 v36, v21, v36 + v_sub_u32_e32 v39, v36, v40 + v_lshl_add_u32 v39, v39, 2, v37 + v_add_u32_e32 v40, 48, v29 + v_lshrrev_b32_e32 v41, 5, v40 + v_lshlrev_b32_e32 v42, 11, v41 + v_lshrrev_b16_e32 v40, 3, v40 + v_and_b32_e32 v40, 3, v40 + v_sub_u16_e32 v43, v40, v18 + v_lshlrev_b32_e32 v44, 4, v41 + v_or_b32_e32 v45, v44, v8 + v_and_b32_e32 v45, 31, v45 + v_xor_b32_e32 v45, v15, v45 + v_sub_u32_e32 v36, v45, v36 + v_lshlrev_b32_e32 v36, 2, v36 + v_mov_b32_e32 v46, 12 + v_lshlrev_b32_sdwa v43, v46, sext(v43) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v42, v42, v43, s11 + v_add3_u32 v36, v36, v42, v39 + v_add_u32_e32 v29, 52, v29 + v_lshrrev_b32_e32 v43, 5, v29 + v_sub_u32_e32 v41, v43, v41 + v_lshrrev_b16_e32 v29, 3, v29 + v_and_b32_e32 v29, 3, v29 + v_sub_u16_e32 v40, v29, v40 + v_bfe_i32 v40, v40, 0, 16 + v_lshlrev_b32_e32 v47, 4, v43 + v_or_b32_e32 v48, v47, v8 + v_and_b32_e32 v49, 31, v48 + v_xor_b32_e32 v21, v21, v49 + v_sub_u32_e32 v45, v21, v45 + v_lshlrev_b32_e32 v41, 11, v41 + v_lshlrev_b32_e32 v45, 2, v45 + v_lshl_add_u32 v40, v40, 12, v41 + v_add3_u32 v41, v45, v40, v36 + ds_read_b32 v77, v28 offset:16384 + ds_read_b32 v78, v25 offset:16384 + ds_read_b32 v79, v32 offset:16384 + ds_read_b32 v80, v37 offset:16384 + ds_read_b32 v81, v39 offset:16384 + ds_read_b32 v82, v36 offset:16384 + ds_read_b32 v83, v41 offset:16384 + v_or_b32_e32 v25, 4, v15 + v_sub_u16_e32 v18, v18, v29 + v_sub_u32_e32 v28, v48, v47 + v_ashrrev_i32_e32 v29, 31, v28 + v_lshrrev_b32_e32 v29, 27, v29 + v_add_u32_e32 v29, v28, v29 + v_and_b32_e32 v29, 0xffffffe0, v29 + v_sub_u32_e32 v29, v28, v29 + v_xor_b32_e32 v32, v25, v29 + v_sub_u32_e32 v21, v32, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_lshlrev_b32_sdwa v18, v46, sext(v18) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v36, 11, v43 + v_sub_u32_e32 v18, v18, v36 + v_add3_u32 v21, v21, v18, v41 + v_or_b32_e32 v36, 20, v15 + v_xor_b32_e32 v37, v36, v29 + v_sub_u32_e32 v32, v37, v32 + v_lshl_add_u32 v32, v32, 2, v21 + ds_read_b32 v84, v21 offset:16384 + ds_read_b32 v85, v32 offset:16384 + v_add_u32_e32 v21, v28, v34 + v_ashrrev_i32_e32 v34, 31, v21 + v_lshrrev_b32_e32 v34, 27, v34 + v_add_u32_e32 v34, v21, v34 + v_and_b32_e32 v34, 0xffffffe0, v34 + v_sub_u32_e32 v34, v21, v34 + v_xor_b32_e32 v21, v25, v34 + v_sub_u32_e32 v37, v21, v37 + v_lshl_add_u32 v37, v37, 2, v33 + v_add_u32_e32 v32, v37, v32 + v_add_u32_e32 v37, v28, v38 + v_ashrrev_i32_e32 v38, 31, v37 + v_lshrrev_b32_e32 v38, 27, v38 + v_add_u32_e32 v38, v37, v38 + v_and_b32_e32 v38, 0xffffffe0, v38 + v_sub_u32_e32 v37, v37, v38 + v_xor_b32_e32 v38, v36, v37 + v_sub_u32_e32 v21, v38, v21 + v_lshl_add_u32 v39, v21, 2, v31 + v_add_u32_e32 v41, v32, v39 + v_add_u32_e32 v21, 16, v28 + v_ashrrev_i32_e32 v43, 31, v21 + v_lshrrev_b32_e32 v43, 27, v43 + v_add_u32_e32 v43, v21, v43 + v_and_b32_e32 v43, 0xffffffe0, v43 + v_sub_u32_e32 v43, v21, v43 + v_xor_b32_e32 v21, v25, v43 + v_sub_u32_e32 v38, v21, v38 + v_lshl_add_u32 v38, v38, 2, v35 + v_add_u32_e32 v45, v41, v38 + v_xor_b32_e32 v46, v36, v43 + v_sub_u32_e32 v21, v46, v21 + v_lshlrev_b32_e32 v47, 2, v21 + v_add_u32_e32 v48, v45, v47 + v_add_u32_e32 v21, v28, v44 + v_ashrrev_i32_e32 v28, 31, v21 + v_lshrrev_b32_e32 v28, 27, v28 + v_add_u32_e32 v28, v21, v28 + v_and_b32_e32 v28, 0xffffffe0, v28 + v_sub_u32_e32 v28, v21, v28 + v_xor_b32_e32 v21, v25, v28 + v_sub_u32_e32 v25, v21, v46 + v_lshl_add_u32 v44, v25, 2, v42 + v_add_u32_e32 v46, v48, v44 + v_xor_b32_e32 v25, v36, v49 + v_sub_u32_e32 v21, v25, v21 + v_lshl_add_u32 v36, v21, 2, v40 + v_add_u32_e32 v50, v46, v36 + v_or_b32_e32 v21, 8, v15 + v_xor_b32_e32 v51, v21, v29 + v_sub_u32_e32 v25, v51, v25 + v_lshl_add_u32 v52, v25, 2, v18 + v_add_u32_e32 v25, v50, v52 + ds_read_b32 v86, v25 offset:16384 + v_or_b32_e32 v53, 24, v15 + v_xor_b32_e32 v54, v53, v29 + v_sub_u32_e32 v51, v54, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add_u32_e32 v25, v25, v51 + ds_read_b32 v87, v25 offset:16384 + v_xor_b32_e32 v55, v21, v34 + v_sub_u32_e32 v54, v55, v54 + v_lshl_add_u32 v54, v54, 2, v33 + v_add_u32_e32 v56, v25, v54 + v_xor_b32_e32 v25, v53, v37 + v_sub_u32_e32 v55, v25, v55 + v_lshl_add_u32 v55, v55, 2, v31 + v_add_u32_e32 v57, v56, v55 + v_xor_b32_e32 v58, v21, v43 + v_sub_u32_e32 v25, v58, v25 + v_lshl_add_u32 v59, v25, 2, v35 + v_add_u32_e32 v60, v57, v59 + v_xor_b32_e32 v25, v53, v43 + v_sub_u32_e32 v58, v25, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add_u32_e32 v61, v60, v58 + v_xor_b32_e32 v21, v21, v28 + v_sub_u32_e32 v25, v21, v25 + v_lshl_add_u32 v62, v25, 2, v42 + s_waitcnt lgkmcnt(10) + v_mfma_i32_32x32x16_i8 a[176:191], v[6:7], v[76:77], 0 + v_add_u32_e32 v63, v61, v62 + v_xor_b32_e32 v25, v53, v49 + v_sub_u32_e32 v21, v25, v21 + v_lshl_add_u32 v53, v21, 2, v40 + v_add_u32_e32 v64, v63, v53 + v_or_b32_e32 v65, 12, v15 + v_xor_b32_e32 v21, v65, v29 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[6:7], v[84:85], 0 + v_sub_u32_e32 v25, v21, v25 + v_lshl_add_u32 v66, v25, 2, v18 + v_add_u32_e32 v18, v64, v66 + ds_read_b32 v88, v18 offset:16384 + v_or_b32_e32 v67, 28, v15 + v_xor_b32_e32 v29, v67, v29 + v_sub_u32_e32 v15, v29, v21 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[6:7], v[86:87], 0 + v_lshlrev_b32_e32 v68, 2, v15 + v_add_u32_e32 v69, v18, v68 + ds_read_b32 v89, v69 offset:16384 + v_lshl_add_u32 v15, v19, 7, v17 + v_lshl_add_u32 v18, v20, 3, v15 + ds_read_b64 v[18:19], v18 + v_xor_b32_e32 v20, v24, v26 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[0:15], v[6:7], v[88:89], 0 + v_sub_u32_e32 v6, v20, v22 + v_lshl_add_u32 v6, v6, 3, v15 + v_xor_b32_e32 v7, v24, v27 + v_sub_u32_e32 v7, v7, v22 + v_lshl_add_u32 v20, v7, 3, v15 + ds_read_b64 v[6:7], v6 + ds_read_b64 v[20:21], v20 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[192:207], v[18:19], v[76:77], 0 + v_xor_b32_e32 v24, v24, v16 + v_mfma_i32_32x32x16_i8 a[128:143], v[18:19], v[84:85], 0 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add_u32_e32 v70, v22, v15 + v_add_u32_e32 v15, 0x80, v14 + v_lshrrev_b32_e32 v71, 1, v15 + v_sub_u32_e32 v22, v71, v23 + v_bfe_u32 v15, v15, 1, 4 + v_mfma_i32_32x32x16_i8 a[64:79], v[18:19], v[86:87], 0 + v_xor_b32_e32 v72, v15, v13 + v_sub_u32_e32 v23, v72, v24 + v_lshlrev_b32_e32 v22, 7, v22 + v_lshl_add_u32 v73, v23, 3, v22 + v_add_u32_e32 v74, v70, v73 + ds_read_b64 v[22:23], v74 + v_xor_b32_e32 v24, v15, v26 + v_mfma_i32_32x32x16_i8 a[16:31], v[18:19], v[88:89], 0 + v_sub_u32_e32 v18, v24, v72 + v_lshl_add_u32 v18, v18, 3, v74 + v_xor_b32_e32 v19, v15, v27 + v_sub_u32_e32 v19, v19, v72 + v_lshl_add_u32 v24, v19, 3, v74 + ds_read_b64 v[18:19], v18 + ds_read_b64 v[24:25], v24 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[208:223], v[22:23], v[76:77], 0 + v_xor_b32_e32 v15, v15, v16 + v_mfma_i32_32x32x16_i8 a[144:159], v[22:23], v[84:85], 0 + v_sub_u32_e32 v72, v15, v72 + v_lshlrev_b32_e32 v72, 3, v72 + v_add3_u32 v73, v73, v70, v72 + v_add_u32_e32 v14, 0xc0, v14 + v_lshrrev_b32_e32 v75, 1, v14 + v_sub_u32_e32 v71, v75, v71 + v_bfe_u32 v75, v14, 1, 4 + v_mfma_i32_32x32x16_i8 a[80:95], v[22:23], v[86:87], 0 + v_xor_b32_e32 v13, v75, v13 + v_sub_u32_e32 v14, v13, v15 + v_lshlrev_b32_e32 v14, 3, v14 + v_lshlrev_b32_e32 v15, 7, v71 + v_add3_u32 v71, v14, v15, v73 + ds_read_b64 v[14:15], v71 + v_xor_b32_e32 v26, v75, v26 + v_mfma_i32_32x32x16_i8 a[32:47], v[22:23], v[88:89], 0 + v_sub_u32_e32 v22, v26, v13 + v_lshl_add_u32 v22, v22, 3, v71 + v_xor_b32_e32 v23, v75, v27 + v_sub_u32_e32 v23, v23, v13 + v_lshl_add_u32 v26, v23, 3, v71 + ds_read_b64 v[22:23], v22 + ds_read_b64 v[26:27], v26 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[224:239], v[14:15], v[76:77], 0 + v_mfma_i32_32x32x16_i8 a[160:175], v[14:15], v[84:85], 0 + v_mfma_i32_32x32x16_i8 a[96:111], v[14:15], v[86:87], 0 + v_mfma_i32_32x32x16_i8 a[240:255], v[14:15], v[88:89], 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[4:5], v[78:79], a[176:191] + ds_read_b32 v76, v32 offset:16384 + ds_read_b32 v77, v41 offset:16384 + ds_read_b32 v56, v56 offset:16384 + ds_read_b32 v57, v57 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[4:5], v[76:77], a[112:127] + v_xor_b32_e32 v14, v65, v34 + v_sub_u32_e32 v15, v14, v29 + v_lshl_add_u32 v15, v15, 2, v33 + v_add_u32_e32 v29, v69, v15 + ds_read_b32 v84, v29 offset:16384 + v_xor_b32_e32 v33, v67, v37 + v_sub_u32_e32 v14, v33, v14 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[4:5], v[56:57], a[48:63] + v_lshl_add_u32 v14, v14, 2, v31 + v_add_u32_e32 v29, v29, v14 + ds_read_b32 v85, v29 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[4:5], v[84:85], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[6:7], v[78:79], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[6:7], v[76:77], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[6:7], v[56:57], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[6:7], v[84:85], a[16:31] + v_mfma_i32_32x32x16_i8 a[208:223], v[18:19], v[78:79], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[18:19], v[76:77], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[18:19], v[56:57], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[18:19], v[84:85], a[32:47] + v_mfma_i32_32x32x16_i8 a[224:239], v[22:23], v[78:79], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[22:23], v[76:77], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[22:23], v[56:57], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[22:23], v[84:85], a[240:255] + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[80:81], a[176:191] + ds_read_b32 v18, v45 offset:16384 + ds_read_b32 v19, v48 offset:16384 + ds_read_b32 v22, v60 offset:16384 + ds_read_b32 v23, v61 offset:16384 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[18:19], a[112:127] + v_xor_b32_e32 v4, v65, v43 + v_sub_u32_e32 v5, v4, v33 + v_lshl_add_u32 v5, v5, 2, v35 + v_add_u32_e32 v6, v29, v5 + ds_read_b32 v34, v6 offset:16384 + v_xor_b32_e32 v7, v67, v43 + v_sub_u32_e32 v4, v7, v4 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[22:23], a[48:63] + v_lshlrev_b32_e32 v4, 2, v4 + v_add_u32_e32 v6, v6, v4 + ds_read_b32 v35, v6 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[34:35], a[0:15] + v_mfma_i32_32x32x16_i8 a[192:207], v[20:21], v[80:81], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[20:21], v[18:19], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[20:21], v[22:23], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[20:21], v[34:35], a[16:31] + v_mfma_i32_32x32x16_i8 a[208:223], v[24:25], v[80:81], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[24:25], v[18:19], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[24:25], v[22:23], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[24:25], v[34:35], a[32:47] + v_mfma_i32_32x32x16_i8 a[224:239], v[26:27], v[80:81], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[26:27], v[18:19], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[26:27], v[22:23], a[96:111] + ds_read_b64 v[2:3], v17 + v_mfma_i32_32x32x16_i8 a[240:255], v[26:27], v[34:35], a[240:255] + v_add3_u32 v17, v39, v32, v38 + v_add3_u32 v17, v47, v17, v44 + ds_read_b32 v18, v46 offset:16384 + ds_read_b32 v19, v50 offset:16384 + v_add3_u32 v17, v36, v17, v52 + v_add3_u32 v17, v17, v51, v54 + v_add3_u32 v17, v55, v17, v59 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[82:83], a[176:191] + v_add3_u32 v17, v58, v17, v62 + ds_read_b32 v20, v63 offset:16384 + ds_read_b32 v21, v64 offset:16384 + v_add3_u32 v17, v53, v17, v66 + v_add3_u32 v15, v17, v68, v15 + v_add3_u32 v5, v14, v15, v5 + v_xor_b32_e32 v14, v65, v28 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[18:19], a[112:127] + v_sub_u32_e32 v7, v14, v7 + v_lshl_add_u32 v7, v7, 2, v42 + v_add3_u32 v4, v4, v5, v7 + v_add_u32_e32 v5, v6, v7 + ds_read_b32 v6, v5 offset:16384 + v_xor_b32_e32 v5, v67, v49 + v_sub_u32_e32 v5, v5, v14 + s_waitcnt lgkmcnt(1) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[20:21], a[48:63] + v_lshlrev_b32_e32 v5, 2, v5 + v_add3_u32 v4, v5, v40, v4 + ds_read_b32 v7, v4 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[6:7], a[0:15] + ds_read_b64 v[2:3], v70 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[82:83], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[18:19], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[20:21], a[64:79] + v_add_u32_e32 v4, v74, v72 + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[6:7], a[16:31] + ds_read_b64 v[2:3], v4 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[82:83], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[18:19], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[20:21], a[80:95] + v_xor_b32_e32 v4, v75, v16 + v_sub_u32_e32 v4, v4, v13 + v_lshl_add_u32 v4, v4, 3, v71 + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[6:7], a[32:47] + ds_read_b64 v[2:3], v4 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[82:83], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[18:19], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[20:21], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[6:7], a[240:255] + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB39_3 + s_branch .LBB39_10 +.LBB39_2: + ; implicit-def: $agpr111 + ; implicit-def: $agpr175 + ; implicit-def: $agpr239 + ; implicit-def: $agpr47 + ; implicit-def: $agpr95 + ; implicit-def: $agpr159 + ; implicit-def: $agpr223 + ; implicit-def: $agpr31 + ; implicit-def: $agpr79 + ; implicit-def: $agpr143 + ; implicit-def: $agpr207 + ; implicit-def: $agpr15 + ; implicit-def: $agpr63 + ; implicit-def: $agpr127 + ; implicit-def: $agpr191 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB39_3: + v_readfirstlane_b32 s15, v0 + v_and_b32_e32 v2, 48, v12 + s_and_b32 s11, s15, 0xffffffc0 + v_and_b32_e32 v78, 0x7c, v1 + v_add_u32_e32 v16, s11, v78 + v_add_u32_e32 v3, s20, v16 + v_mad_u64_u32 v[20:21], s[18:19], v3, s7, v[2:3] + s_mov_b32 s11, 0x20000 + buffer_load_dwordx4 v[46:49], v20, s[8:11], 0 offen + v_add_u32_e32 v4, s7, v20 + buffer_load_dwordx4 v[50:53], v4, s[8:11], 0 offen + v_and_or_b32 v3, v11, 8, v9 + v_lshlrev_b32_e32 v11, 3, v9 + v_add_u32_e32 v6, s7, v4 + buffer_load_dwordx4 v[54:57], v6, s[8:11], 0 offen + v_and_b32_e32 v79, 28, v10 + v_lshl_or_b32 v4, v8, 4, s21 + v_lshlrev_b32_e32 v5, 12, v9 + s_lshr_b32 s18, s15, 2 + s_lshr_b32 s19, s15, 1 + v_lshl_or_b32 v17, v8, 7, v5 + s_mov_b32 s15, s11 + v_lshrrev_b32_e32 v80, 3, v2 + s_and_b32 s23, s18, 0x3fffffe0 + s_and_b32 s18, s18, 0x3ffffff0 + v_and_or_b32 v2, s19, 32, v30 + v_or_b32_e32 v81, 1, v80 + v_or_b32_e32 v5, s23, v30 + v_add_u32_e32 v21, s18, v79 + v_lshrrev_b32_e32 v2, 4, v2 + v_ashrrev_i32_e32 v31, 1, v16 + v_ashrrev_i32_e32 v10, 31, v16 + v_lshlrev_b32_e32 v36, 6, v16 + v_or_b32_e32 v37, 1, v16 + v_sub_u32_e32 v82, v80, v81 + v_lshrrev_b32_e32 v38, 31, v16 + v_add_u32_e32 v6, s7, v6 + buffer_load_dwordx4 v[58:61], v6, s[8:11], 0 offen + v_lshrrev_b32_e32 v6, 1, v5 + v_bfe_u32 v7, v5, 1, 4 + v_mad_u64_u32 v[18:19], s[18:19], v21, s22, v[4:5] + v_xor_b32_e32 v4, v2, v8 + buffer_load_dwordx4 v[12:15], v18, s[12:15], 0 offen + v_lshrrev_b32_e32 v19, 28, v10 + v_add_u32_e32 v39, v37, v38 + v_add_u32_e32 v10, s22, v18 + buffer_load_dwordx4 v[22:25], v10, s[12:15], 0 offen + v_or_b32_e32 v40, 1, v31 + v_xor_b32_e32 v77, v7, v3 + v_add_u32_e32 v32, s22, v10 + buffer_load_dwordx4 v[26:29], v32, s[12:15], 0 offen + v_lshlrev_b32_e32 v10, 7, v6 + v_lshl_or_b32 v42, v4, 2, v17 + v_add_u32_e32 v17, s22, v32 + buffer_load_dwordx4 v[32:35], v17, s[12:15], 0 offen + v_add_u32_e32 v17, v31, v19 + v_ashrrev_i32_e32 v41, 1, v39 + v_and_b32_e32 v43, 0x1ffffffe, v39 + v_ashrrev_i32_e32 v39, 31, v39 + v_and_b32_e32 v17, -16, v17 + v_sub_u32_e32 v44, v41, v31 + v_sub_u32_e32 v37, v37, v43 + v_lshrrev_b32_e32 v39, 28, v39 + v_sub_u32_e32 v43, v40, v41 + v_sub_u32_e32 v17, v31, v17 + v_lshl_or_b32 v31, v37, 3, v81 + v_add_u32_e32 v37, v41, v39 + v_xor_b32_e32 v39, v17, v80 + v_xor_b32_e32 v17, v17, v81 + v_add_u32_e32 v45, v31, v82 + v_and_b32_e32 v37, -16, v37 + v_lshl_add_u32 v39, v39, 3, v36 + v_lshl_add_u32 v36, v17, 3, v36 + v_sub_u32_e32 v37, v41, v37 + v_xor_b32_e32 v41, v45, v37 + v_lshl_add_u32 v44, v44, 7, v36 + v_xor_b32_e32 v31, v31, v37 + v_sub_u32_e32 v37, v41, v17 + v_sub_u32_e32 v17, v31, v17 + v_lshl_add_u32 v37, v37, 3, v44 + v_lshl_add_u32 v17, v17, 3, v44 + s_waitcnt vmcnt(7) + ds_write_b64 v39, v[46:47] + ds_write_b64 v36, v[48:49] + s_waitcnt vmcnt(6) + ds_write_b64 v37, v[50:51] + ds_write_b64 v17, v[52:53] + v_add_u32_e32 v19, v40, v19 + v_and_b32_e32 v19, -16, v19 + v_sub_u32_e32 v19, v40, v19 + v_xor_b32_e32 v36, v19, v80 + v_sub_u32_e32 v31, v36, v31 + v_lshlrev_b32_e32 v31, 3, v31 + v_lshlrev_b32_e32 v37, 7, v43 + v_add3_u32 v17, v31, v37, v17 + s_waitcnt vmcnt(5) + ds_write_b64 v17, v[54:55] + v_xor_b32_e32 v19, v19, v81 + v_sub_u32_e32 v31, v19, v36 + v_lshl_add_u32 v17, v31, 3, v17 + ds_write_b64 v17, v[56:57] + v_or_b32_e32 v16, 3, v16 + v_add_u32_e32 v31, v16, v38 + v_ashrrev_i32_e32 v36, 1, v31 + v_sub_u32_e32 v37, v36, v40 + v_and_b32_e32 v38, 0x1ffffffe, v31 + v_sub_u32_e32 v16, v16, v38 + v_lshl_or_b32 v16, v16, 3, v81 + v_add_u32_e32 v38, v16, v82 + v_ashrrev_i32_e32 v31, 31, v31 + v_lshrrev_b32_e32 v31, 28, v31 + v_add_u32_e32 v31, v36, v31 + v_and_b32_e32 v31, -16, v31 + v_sub_u32_e32 v31, v36, v31 + v_xor_b32_e32 v36, v38, v31 + v_sub_u32_e32 v19, v36, v19 + v_lshlrev_b32_e32 v19, 3, v19 + v_lshlrev_b32_e32 v37, 7, v37 + v_add3_u32 v17, v19, v37, v17 + s_waitcnt vmcnt(4) + ds_write_b64 v17, v[58:59] + v_xor_b32_e32 v16, v16, v31 + v_sub_u32_e32 v16, v16, v36 + v_lshl_add_u32 v16, v16, 3, v17 + ds_write_b64 v16, v[60:61] + s_mov_b32 s18, 0x3020504 + s_waitcnt vmcnt(3) + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + v_perm_b32 v14, v14, v14, s18 + v_perm_b32 v15, v15, v15, s18 + s_waitcnt vmcnt(2) + v_perm_b32 v16, v22, v22, s18 + v_perm_b32 v17, v23, v23, s18 + v_perm_b32 v19, v24, v24, s18 + v_perm_b32 v22, v25, v25, s18 + s_waitcnt vmcnt(1) + v_perm_b32 v23, v26, v26, s18 + v_perm_b32 v24, v27, v27, s18 + v_perm_b32 v25, v28, v28, s18 + v_perm_b32 v26, v29, v29, s18 + s_waitcnt vmcnt(0) + v_perm_b32 v27, v32, v32, s18 + v_perm_b32 v28, v33, v33, s18 + v_perm_b32 v29, v34, v34, s18 + v_perm_b32 v31, v35, v35, s18 + s_mov_b32 s18, 0x5010400 + v_perm_b32 v32, v16, v12, s18 + v_perm_b32 v33, v27, v23, s18 + s_mov_b32 s19, 0x5040100 + v_perm_b32 v34, v33, v32, s19 + s_mov_b32 s23, 0x7060302 + v_perm_b32 v32, v33, v32, s23 + s_mov_b32 s24, 0x7030602 + v_perm_b32 v12, v16, v12, s24 + v_perm_b32 v16, v27, v23, s24 + v_perm_b32 v23, v16, v12, s19 + v_perm_b32 v12, v16, v12, s23 + v_perm_b32 v16, v17, v13, s18 + v_perm_b32 v27, v28, v24, s18 + v_perm_b32 v33, v27, v16, s19 + v_perm_b32 v16, v27, v16, s23 + v_perm_b32 v13, v17, v13, s24 + v_perm_b32 v17, v28, v24, s24 + v_perm_b32 v24, v17, v13, s19 + v_perm_b32 v13, v17, v13, s23 + v_perm_b32 v17, v19, v14, s18 + v_perm_b32 v27, v29, v25, s18 + v_perm_b32 v28, v27, v17, s19 + v_perm_b32 v17, v27, v17, s23 + v_perm_b32 v14, v19, v14, s24 + v_perm_b32 v19, v29, v25, s24 + v_perm_b32 v25, v19, v14, s19 + v_perm_b32 v14, v19, v14, s23 + v_perm_b32 v19, v22, v15, s18 + v_perm_b32 v27, v31, v26, s18 + v_perm_b32 v29, v27, v19, s19 + v_perm_b32 v19, v27, v19, s23 + v_perm_b32 v15, v22, v15, s24 + v_perm_b32 v22, v31, v26, s24 + v_perm_b32 v26, v22, v15, s19 + v_perm_b32 v15, v22, v15, s23 + v_lshrrev_b32_e32 v22, 1, v21 + v_and_b32_e32 v22, 16, v22 + v_xor_b32_e32 v27, v22, v30 + v_lshlrev_b32_e32 v31, 9, v21 + v_and_b32_e32 v31, 0x3000, v31 + v_lshlrev_b32_e32 v21, 6, v21 + s_movk_i32 s18, 0xf800 + v_and_b32_e32 v21, 0xfffff800, v21 + v_add_u32_e32 v21, v31, v21 + v_lshl_or_b32 v21, v27, 2, v21 + ds_write_b32 v21, v34 offset:16384 + v_or_b32_e32 v31, 1, v22 + v_xor_b32_e32 v31, v31, v30 + v_sub_u32_e32 v27, v31, v27 + v_lshl_add_u32 v21, v27, 2, v21 + v_or_b32_e32 v27, 2, v22 + v_xor_b32_e32 v27, v27, v30 + v_sub_u32_e32 v31, v27, v31 + v_lshl_add_u32 v31, v31, 2, v21 + ds_write_b32 v21, v32 offset:16512 + v_or_b32_e32 v21, 3, v22 + v_xor_b32_e32 v21, v21, v30 + v_sub_u32_e32 v27, v21, v27 + v_lshlrev_b32_e32 v27, 2, v27 + s_movk_i32 s19, 0x80 + v_add3_u32 v27, v31, s19, v27 + ds_write_b32 v31, v23 offset:16640 + v_or_b32_e32 v23, 4, v22 + v_xor_b32_e32 v23, v23, v30 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v27, s19, v21 + ds_write_b32 v27, v12 offset:16640 + v_or_b32_e32 v12, 5, v22 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v23, v12, v23 + v_lshlrev_b32_e32 v23, 2, v23 + v_add3_u32 v23, v21, s19, v23 + ds_write_b32 v21, v33 offset:16640 + v_or_b32_e32 v21, 6, v22 + v_xor_b32_e32 v21, v21, v30 + v_sub_u32_e32 v12, v21, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v23, s19, v12 + ds_write_b32 v23, v16 offset:16640 + v_or_b32_e32 v16, 7, v22 + v_xor_b32_e32 v16, v16, v30 + v_sub_u32_e32 v21, v16, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v21, v12, s19, v21 + ds_write_b32 v12, v24 offset:16640 + v_or_b32_e32 v12, 8, v22 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v16, v12, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v21, s19, v16 + ds_write_b32 v21, v13 offset:16640 + v_or_b32_e32 v13, 9, v22 + v_xor_b32_e32 v13, v13, v30 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v16, s19, v12 + ds_write_b32 v16, v28 offset:16640 + v_or_b32_e32 v16, 10, v22 + v_xor_b32_e32 v16, v16, v30 + v_sub_u32_e32 v13, v16, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v12, s19, v13 + ds_write_b32 v12, v17 offset:16640 + v_or_b32_e32 v12, 11, v22 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v16, v12, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v16, v13, s19, v16 + ds_write_b32 v13, v25 offset:16640 + v_or_b32_e32 v13, 12, v22 + v_xor_b32_e32 v13, v13, v30 + v_sub_u32_e32 v12, v13, v12 + v_lshlrev_b32_e32 v12, 2, v12 + v_add3_u32 v12, v16, s19, v12 + ds_write_b32 v16, v14 offset:16640 + v_or_b32_e32 v14, 13, v22 + v_xor_b32_e32 v14, v14, v30 + v_sub_u32_e32 v13, v14, v13 + v_lshlrev_b32_e32 v13, 2, v13 + v_add3_u32 v13, v12, s19, v13 + ds_write_b32 v12, v29 offset:16640 + v_or_b32_e32 v12, 14, v22 + v_xor_b32_e32 v12, v12, v30 + v_sub_u32_e32 v14, v12, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v14, v13, s19, v14 + ds_write_b32 v13, v19 offset:16640 + v_or_b32_e32 v13, 15, v22 + v_xor_b32_e32 v13, v13, v30 + v_sub_u32_e32 v12, v13, v12 + v_lshl_add_u32 v12, v12, 2, v14 + ds_write_b32 v14, v26 offset:16640 + ds_write_b32 v12, v15 offset:16768 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v83, 2, v3 + v_add_u32_e32 v29, 4, v3 + v_add_u32_e32 v28, 6, v3 + v_add_u32_e32 v84, 64, v5 + v_lshrrev_b16_e32 v21, 3, v11 + v_or_b32_e32 v22, 16, v2 + v_add_u32_e32 v27, 16, v11 + v_add_u32_e32 v26, 20, v11 + v_or_b32_e32 v12, 16, v8 + v_add_u32_e32 v25, 36, v11 + v_add_u32_e32 v24, 48, v11 + v_add_u32_e32 v23, 52, v11 + v_or_b32_e32 v17, 4, v2 + v_or_b32_e32 v16, 20, v2 + v_or_b32_e32 v15, 8, v2 + v_or_b32_e32 v14, 24, v2 + v_or_b32_e32 v13, 12, v2 + v_or_b32_e32 v11, 28, v2 + s_cbranch_vccnz .LBB39_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit967.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v19, v7, v83 + v_lshl_add_u32 v37, v19, 3, v10 + v_xor_b32_e32 v19, v7, v29 + v_lshl_add_u32 v33, v19, 3, v10 + v_xor_b32_e32 v31, v7, v28 + v_lshl_add_u32 v19, v31, 3, v10 + v_lshrrev_b32_e32 v32, 1, v84 + v_sub_u32_e32 v34, v32, v6 + v_bfe_u32 v35, v84, 1, 4 + v_xor_b32_e32 v36, v35, v3 + v_sub_u32_e32 v36, v36, v31 + v_lshl_add_u32 v39, v34, 7, v19 + v_lshl_add_u32 v52, v36, 3, v39 + v_xor_b32_e32 v34, v35, v83 + v_sub_u32_e32 v34, v34, v31 + v_lshl_add_u32 v38, v34, 3, v39 + v_xor_b32_e32 v34, v35, v29 + v_sub_u32_e32 v34, v34, v31 + v_lshl_add_u32 v34, v34, 3, v39 + v_xor_b32_e32 v35, v35, v28 + v_sub_u32_e32 v31, v35, v31 + v_lshl_add_u32 v31, v31, 3, v39 + v_add_u32_e32 v36, 0x80, v5 + v_lshrrev_b32_e32 v39, 1, v36 + v_sub_u32_e32 v32, v39, v32 + v_bfe_u32 v41, v36, 1, 4 + v_xor_b32_e32 v43, v41, v3 + v_sub_u32_e32 v35, v43, v35 + v_lshlrev_b32_e32 v35, 3, v35 + v_lshlrev_b32_e32 v32, 7, v32 + v_add3_u32 v50, v35, v32, v31 + v_xor_b32_e32 v32, v41, v83 + v_sub_u32_e32 v32, v32, v43 + v_lshl_add_u32 v40, v32, 3, v50 + v_xor_b32_e32 v32, v41, v29 + v_sub_u32_e32 v32, v32, v43 + v_lshl_add_u32 v36, v32, 3, v50 + v_xor_b32_e32 v35, v41, v28 + v_sub_u32_e32 v32, v35, v43 + v_lshl_add_u32 v32, v32, 3, v50 + v_add_u32_e32 v41, 0xc0, v5 + v_lshrrev_b32_e32 v43, 1, v41 + v_sub_u32_e32 v39, v43, v39 + v_bfe_u32 v43, v41, 1, 4 + v_xor_b32_e32 v44, v43, v3 + v_sub_u32_e32 v35, v44, v35 + v_lshlrev_b32_e32 v35, 3, v35 + v_lshlrev_b32_e32 v39, 7, v39 + v_add3_u32 v46, v35, v39, v32 + v_xor_b32_e32 v35, v43, v83 + v_sub_u32_e32 v35, v35, v44 + v_lshl_add_u32 v41, v35, 3, v46 + v_xor_b32_e32 v35, v43, v29 + v_sub_u32_e32 v35, v35, v44 + v_lshl_add_u32 v39, v35, 3, v46 + v_xor_b32_e32 v35, v43, v28 + v_sub_u32_e32 v35, v35, v44 + v_lshl_add_u32 v35, v35, 3, v46 + v_xor_b32_e32 v43, v22, v8 + v_sub_u32_e32 v44, v43, v4 + v_lshlrev_b32_e32 v44, 2, v44 + v_sub_u32_e32 v45, v21, v9 + v_lshlrev_b32_e32 v45, 12, v45 + v_add3_u32 v70, v42, v45, v44 + v_lshrrev_b32_e32 v45, 5, v27 + v_lshrrev_b16_e32 v44, 3, v27 + v_and_b32_e32 v47, 3, v44 + v_sub_u16_e32 v44, v47, v21 + v_bfe_i32 v44, v44, 0, 16 + v_lshl_or_b32 v62, v45, 4, v8 + v_xor_b32_e32 v48, v2, v62 + v_sub_u32_e32 v43, v48, v43 + v_lshlrev_b32_e32 v49, 11, v45 + v_lshlrev_b32_e32 v43, 2, v43 + v_lshl_or_b32 v64, v44, 12, v49 + v_add3_u32 v44, v43, v64, v70 + v_lshrrev_b32_e32 v43, 5, v26 + v_sub_u32_e32 v45, v43, v45 + v_lshrrev_b16_e32 v49, 3, v26 + v_and_b32_e32 v49, 3, v49 + v_sub_u16_e32 v47, v49, v47 + v_bfe_i32 v47, v47, 0, 16 + v_lshl_or_b32 v66, v43, 4, v8 + v_xor_b32_e32 v51, v22, v66 + v_sub_u32_e32 v48, v51, v48 + v_lshlrev_b32_e32 v45, 11, v45 + v_lshlrev_b32_e32 v48, 2, v48 + v_lshl_add_u32 v67, v47, 12, v45 + v_add3_u32 v48, v48, v67, v44 + v_sub_u16_e32 v45, v21, v49 + v_bfe_i32 v45, v45, 0, 16 + v_xor_b32_e32 v47, v2, v12 + v_sub_u32_e32 v49, v47, v51 + v_lshlrev_b32_e32 v43, 11, v43 + v_xor_b32_e32 v43, 0x800, v43 + v_lshlrev_b32_e32 v49, 2, v49 + v_lshl_or_b32 v85, v45, 12, v43 + v_add3_u32 v43, v49, v85, v48 + v_lshrrev_b32_e32 v45, 5, v25 + v_lshlrev_b32_e32 v49, 11, v45 + v_lshrrev_b16_e32 v51, 3, v25 + v_and_b32_e32 v51, 3, v51 + v_sub_u16_e32 v53, v51, v21 + v_lshl_or_b32 v54, v45, 4, v8 + v_and_b32_e32 v86, 31, v54 + v_xor_b32_e32 v54, v22, v86 + v_sub_u32_e32 v47, v54, v47 + v_lshlrev_b32_e32 v47, 2, v47 + v_mov_b32_e32 v55, 12 + v_lshlrev_b32_sdwa v53, v55, sext(v53) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v87, v49, v53, s18 + v_add3_u32 v47, v47, v87, v43 + v_lshrrev_b32_e32 v49, 5, v24 + v_sub_u32_e32 v45, v49, v45 + v_lshrrev_b16_e32 v53, 3, v24 + v_and_b32_e32 v53, 3, v53 + v_sub_u16_e32 v51, v53, v51 + v_bfe_i32 v51, v51, 0, 16 + v_lshl_or_b32 v56, v49, 4, v8 + v_and_b32_e32 v88, 31, v56 + v_xor_b32_e32 v56, v2, v88 + v_sub_u32_e32 v54, v56, v54 + v_lshlrev_b32_e32 v45, 11, v45 + v_lshlrev_b32_e32 v54, 2, v54 + v_lshl_add_u32 v89, v51, 12, v45 + v_add3_u32 v45, v54, v89, v47 + v_lshrrev_b32_e32 v51, 5, v23 + v_sub_u32_e32 v49, v51, v49 + v_lshrrev_b16_e32 v54, 3, v23 + v_and_b32_e32 v54, 3, v54 + v_sub_u16_e32 v53, v54, v53 + v_bfe_i32 v53, v53, 0, 16 + v_lshl_or_b32 v57, v51, 4, v8 + v_and_b32_e32 v90, 31, v57 + v_xor_b32_e32 v57, v22, v90 + v_sub_u32_e32 v56, v57, v56 + v_lshlrev_b32_e32 v49, 11, v49 + v_lshlrev_b32_e32 v56, 2, v56 + v_lshl_add_u32 v91, v53, 12, v49 + v_add3_u32 v49, v56, v91, v45 + v_sub_u16_e32 v53, v21, v54 + v_xor_b32_e32 v54, v17, v8 + v_sub_u32_e32 v56, v54, v57 + v_lshlrev_b32_e32 v56, 2, v56 + v_lshlrev_b32_sdwa v53, v55, sext(v53) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v51, 11, v51 + v_sub_u32_e32 v68, v53, v51 + v_add3_u32 v71, v56, v68, v49 + v_xor_b32_e32 v51, v16, v8 + v_sub_u32_e32 v53, v51, v54 + v_lshl_add_u32 v72, v53, 2, v71 + v_xor_b32_e32 v53, v17, v62 + v_sub_u32_e32 v51, v53, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v57, v51, v64, v72 + v_xor_b32_e32 v51, v16, v66 + v_sub_u32_e32 v53, v51, v53 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v59, v53, v67, v57 + v_xor_b32_e32 v53, v17, v12 + v_sub_u32_e32 v51, v53, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v54, v51, v85, v59 + v_xor_b32_e32 v51, v16, v86 + v_sub_u32_e32 v53, v51, v53 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v55, v53, v87, v54 + v_xor_b32_e32 v53, v17, v88 + v_sub_u32_e32 v51, v53, v51 + v_lshlrev_b32_e32 v51, 2, v51 + v_add3_u32 v51, v51, v89, v55 + v_xor_b32_e32 v56, v16, v90 + v_sub_u32_e32 v53, v56, v53 + v_lshlrev_b32_e32 v53, 2, v53 + v_add3_u32 v53, v53, v91, v51 + v_xor_b32_e32 v58, v15, v8 + v_sub_u32_e32 v56, v58, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v73, v56, v68, v53 + v_xor_b32_e32 v56, v14, v8 + v_sub_u32_e32 v58, v56, v58 + v_lshl_add_u32 v74, v58, 2, v73 + v_xor_b32_e32 v58, v15, v62 + v_sub_u32_e32 v56, v58, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v63, v56, v64, v74 + v_xor_b32_e32 v56, v14, v66 + v_sub_u32_e32 v58, v56, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v65, v58, v67, v63 + v_xor_b32_e32 v58, v15, v12 + v_sub_u32_e32 v56, v58, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v60, v56, v85, v65 + v_xor_b32_e32 v56, v14, v86 + v_sub_u32_e32 v58, v56, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v61, v58, v87, v60 + v_xor_b32_e32 v58, v15, v88 + v_sub_u32_e32 v56, v58, v56 + v_lshlrev_b32_e32 v56, 2, v56 + v_add3_u32 v56, v56, v89, v61 + v_xor_b32_e32 v69, v14, v90 + v_sub_u32_e32 v58, v69, v58 + v_lshlrev_b32_e32 v58, 2, v58 + v_add3_u32 v58, v58, v91, v56 + v_xor_b32_e32 v76, v13, v8 + v_sub_u32_e32 v69, v76, v69 + v_lshlrev_b32_e32 v69, 2, v69 + v_add3_u32 v75, v69, v68, v58 + v_xor_b32_e32 v68, v11, v8 + v_sub_u32_e32 v69, v68, v76 + v_lshl_add_u32 v76, v69, 2, v75 + v_xor_b32_e32 v62, v13, v62 + v_sub_u32_e32 v68, v62, v68 + v_lshlrev_b32_e32 v68, 2, v68 + v_add3_u32 v68, v68, v64, v76 + v_xor_b32_e32 v64, v11, v66 + v_sub_u32_e32 v62, v64, v62 + v_lshlrev_b32_e32 v62, 2, v62 + v_add3_u32 v69, v62, v67, v68 + v_xor_b32_e32 v62, v13, v12 + v_sub_u32_e32 v64, v62, v64 + v_lshlrev_b32_e32 v64, 2, v64 + v_add3_u32 v66, v64, v85, v69 + v_xor_b32_e32 v64, v11, v86 + v_sub_u32_e32 v62, v64, v62 + v_lshlrev_b32_e32 v62, 2, v62 + v_add3_u32 v67, v62, v87, v66 + v_xor_b32_e32 v85, v13, v88 + v_sub_u32_e32 v62, v85, v64 + v_lshlrev_b32_e32 v62, 2, v62 + v_add3_u32 v62, v62, v89, v67 + v_xor_b32_e32 v64, v11, v90 + v_sub_u32_e32 v64, v64, v85 + v_lshlrev_b32_e32 v64, 2, v64 + v_add3_u32 v64, v64, v91, v62 + s_mov_b64 s[2:3], 0 + s_branch .LBB39_6 +.LBB39_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr37 + ; implicit-def: $vgpr33 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr52 + ; implicit-def: $vgpr38 + ; implicit-def: $vgpr34 + ; implicit-def: $vgpr31 + ; implicit-def: $vgpr50 + ; implicit-def: $vgpr40 + ; implicit-def: $vgpr36 + ; implicit-def: $vgpr32 + ; implicit-def: $vgpr46 + ; implicit-def: $vgpr41 + ; implicit-def: $vgpr39 + ; implicit-def: $vgpr35 + ; implicit-def: $vgpr70 + ; implicit-def: $vgpr44 + ; implicit-def: $vgpr48 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr47 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr49 + ; implicit-def: $vgpr71 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr57 + ; implicit-def: $vgpr59 + ; implicit-def: $vgpr54 + ; implicit-def: $vgpr55 + ; implicit-def: $vgpr51 + ; implicit-def: $vgpr53 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr63 + ; implicit-def: $vgpr65 + ; implicit-def: $vgpr60 + ; implicit-def: $vgpr61 + ; implicit-def: $vgpr56 + ; implicit-def: $vgpr58 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr68 + ; implicit-def: $vgpr69 + ; implicit-def: $vgpr66 + ; implicit-def: $vgpr67 + ; implicit-def: $vgpr62 + ; implicit-def: $vgpr64 +.LBB39_6: ; %Flow116 + v_lshl_or_b32 v77, v77, 3, v10 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + s_cbranch_vccnz .LBB39_9 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s22, 6 + v_xor_b32_e32 v19, v7, v83 + v_lshl_add_u32 v37, v19, 3, v10 + v_xor_b32_e32 v19, v7, v29 + v_lshl_add_u32 v33, v19, 3, v10 + v_xor_b32_e32 v7, v7, v28 + v_lshl_add_u32 v19, v7, 3, v10 + v_lshrrev_b32_e32 v10, 1, v84 + v_sub_u32_e32 v6, v10, v6 + v_bfe_u32 v31, v84, 1, 4 + v_xor_b32_e32 v32, v31, v3 + v_sub_u32_e32 v32, v32, v7 + v_lshl_add_u32 v6, v6, 7, v19 + v_lshl_add_u32 v52, v32, 3, v6 + v_xor_b32_e32 v32, v31, v83 + v_sub_u32_e32 v32, v32, v7 + v_lshl_add_u32 v38, v32, 3, v6 + v_xor_b32_e32 v32, v31, v29 + v_sub_u32_e32 v32, v32, v7 + v_lshl_add_u32 v34, v32, 3, v6 + v_xor_b32_e32 v32, v31, v28 + v_sub_u32_e32 v7, v32, v7 + v_lshl_add_u32 v31, v7, 3, v6 + s_movk_i32 s6, 0x80 + v_add_u32_e32 v6, 0x80, v5 + v_lshrrev_b32_e32 v7, 1, v6 + v_sub_u32_e32 v10, v7, v10 + v_bfe_u32 v6, v6, 1, 4 + v_xor_b32_e32 v35, v6, v3 + v_sub_u32_e32 v32, v35, v32 + v_lshlrev_b32_e32 v32, 3, v32 + v_lshlrev_b32_e32 v10, 7, v10 + v_add3_u32 v50, v32, v10, v31 + v_xor_b32_e32 v10, v6, v83 + v_sub_u32_e32 v10, v10, v35 + v_lshl_add_u32 v40, v10, 3, v50 + v_xor_b32_e32 v10, v6, v29 + v_sub_u32_e32 v10, v10, v35 + v_lshl_add_u32 v36, v10, 3, v50 + v_xor_b32_e32 v6, v6, v28 + v_sub_u32_e32 v10, v6, v35 + v_lshl_add_u32 v32, v10, 3, v50 + v_add_u32_e32 v5, 0xc0, v5 + v_lshrrev_b32_e32 v10, 1, v5 + v_sub_u32_e32 v7, v10, v7 + v_bfe_u32 v5, v5, 1, 4 + v_xor_b32_e32 v3, v5, v3 + v_sub_u32_e32 v6, v3, v6 + v_lshlrev_b32_e32 v6, 3, v6 + v_lshlrev_b32_e32 v7, 7, v7 + v_add3_u32 v46, v6, v7, v32 + v_xor_b32_e32 v6, v5, v83 + v_sub_u32_e32 v6, v6, v3 + v_lshl_add_u32 v41, v6, 3, v46 + v_xor_b32_e32 v6, v5, v29 + v_sub_u32_e32 v6, v6, v3 + v_lshl_add_u32 v39, v6, 3, v46 + v_xor_b32_e32 v5, v5, v28 + v_sub_u32_e32 v3, v5, v3 + v_lshl_add_u32 v35, v3, 3, v46 + v_xor_b32_e32 v3, v22, v8 + v_sub_u32_e32 v4, v3, v4 + v_lshlrev_b32_e32 v4, 2, v4 + v_sub_u32_e32 v5, v21, v9 + v_lshlrev_b32_e32 v5, 12, v5 + v_add3_u32 v70, v42, v5, v4 + v_lshrrev_b32_e32 v4, 5, v27 + v_lshrrev_b16_e32 v5, 3, v27 + v_and_b32_e32 v5, 3, v5 + v_sub_u16_e32 v6, v5, v21 + v_bfe_i32 v6, v6, 0, 16 + v_lshl_or_b32 v7, v4, 4, v8 + v_xor_b32_e32 v9, v2, v7 + v_sub_u32_e32 v3, v9, v3 + v_lshlrev_b32_e32 v10, 11, v4 + v_lshlrev_b32_e32 v3, 2, v3 + v_lshl_or_b32 v6, v6, 12, v10 + v_add3_u32 v44, v3, v6, v70 + v_lshrrev_b32_e32 v3, 5, v26 + v_sub_u32_e32 v4, v3, v4 + v_lshrrev_b16_e32 v10, 3, v26 + v_and_b32_e32 v10, 3, v10 + v_sub_u16_e32 v5, v10, v5 + v_bfe_i32 v5, v5, 0, 16 + v_lshl_or_b32 v26, v3, 4, v8 + v_xor_b32_e32 v27, v22, v26 + v_sub_u32_e32 v9, v27, v9 + v_lshlrev_b32_e32 v4, 11, v4 + v_lshlrev_b32_e32 v9, 2, v9 + v_lshl_add_u32 v4, v5, 12, v4 + v_add3_u32 v48, v9, v4, v44 + v_sub_u16_e32 v5, v21, v10 + v_bfe_i32 v5, v5, 0, 16 + v_xor_b32_e32 v9, v2, v12 + v_sub_u32_e32 v10, v9, v27 + v_lshlrev_b32_e32 v3, 11, v3 + v_xor_b32_e32 v3, 0x800, v3 + v_lshlrev_b32_e32 v10, 2, v10 + v_lshl_or_b32 v3, v5, 12, v3 + v_add3_u32 v43, v10, v3, v48 + v_lshrrev_b32_e32 v5, 5, v25 + v_lshlrev_b32_e32 v10, 11, v5 + v_lshrrev_b16_e32 v25, 3, v25 + v_and_b32_e32 v25, 3, v25 + v_sub_u16_e32 v27, v25, v21 + v_lshl_or_b32 v28, v5, 4, v8 + v_and_b32_e32 v28, 31, v28 + v_xor_b32_e32 v29, v22, v28 + v_sub_u32_e32 v9, v29, v9 + v_lshlrev_b32_e32 v9, 2, v9 + v_mov_b32_e32 v51, 12 + v_lshlrev_b32_sdwa v27, v51, sext(v27) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_add3_u32 v10, v10, v27, s18 + v_add3_u32 v47, v9, v10, v43 + v_lshrrev_b32_e32 v9, 5, v24 + v_sub_u32_e32 v5, v9, v5 + v_lshrrev_b16_e32 v24, 3, v24 + v_and_b32_e32 v24, 3, v24 + v_sub_u16_e32 v25, v24, v25 + v_bfe_i32 v25, v25, 0, 16 + v_lshl_or_b32 v27, v9, 4, v8 + v_and_b32_e32 v27, 31, v27 + v_xor_b32_e32 v2, v2, v27 + v_sub_u32_e32 v29, v2, v29 + v_lshlrev_b32_e32 v5, 11, v5 + v_lshlrev_b32_e32 v29, 2, v29 + v_lshl_add_u32 v5, v25, 12, v5 + v_add3_u32 v45, v29, v5, v47 + v_lshrrev_b32_e32 v25, 5, v23 + v_sub_u32_e32 v9, v25, v9 + v_lshrrev_b16_e32 v23, 3, v23 + v_and_b32_e32 v23, 3, v23 + v_sub_u16_e32 v24, v23, v24 + v_bfe_i32 v24, v24, 0, 16 + v_lshl_or_b32 v29, v25, 4, v8 + v_and_b32_e32 v29, 31, v29 + v_xor_b32_e32 v22, v22, v29 + v_sub_u32_e32 v2, v22, v2 + v_lshlrev_b32_e32 v9, 11, v9 + v_lshlrev_b32_e32 v2, 2, v2 + v_lshl_add_u32 v9, v24, 12, v9 + v_add3_u32 v49, v2, v9, v45 + v_sub_u16_e32 v2, v21, v23 + v_xor_b32_e32 v21, v17, v8 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_lshlrev_b32_sdwa v2, v51, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 + v_lshlrev_b32_e32 v23, 11, v25 + v_sub_u32_e32 v2, v2, v23 + v_add3_u32 v71, v22, v2, v49 + v_xor_b32_e32 v22, v16, v8 + v_sub_u32_e32 v21, v22, v21 + v_lshl_add_u32 v72, v21, 2, v71 + v_xor_b32_e32 v21, v17, v7 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v57, v22, v6, v72 + v_xor_b32_e32 v22, v16, v26 + v_sub_u32_e32 v21, v22, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v59, v21, v4, v57 + v_xor_b32_e32 v21, v17, v12 + v_sub_u32_e32 v22, v21, v22 + v_lshlrev_b32_e32 v22, 2, v22 + v_add3_u32 v54, v22, v3, v59 + v_xor_b32_e32 v22, v16, v28 + v_sub_u32_e32 v21, v22, v21 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v55, v21, v10, v54 + v_xor_b32_e32 v17, v17, v27 + v_sub_u32_e32 v21, v17, v22 + v_lshlrev_b32_e32 v21, 2, v21 + v_add3_u32 v51, v21, v5, v55 + v_xor_b32_e32 v16, v16, v29 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v53, v17, v9, v51 + v_xor_b32_e32 v17, v15, v8 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v73, v16, v2, v53 + v_xor_b32_e32 v16, v14, v8 + v_sub_u32_e32 v17, v16, v17 + v_lshl_add_u32 v74, v17, 2, v73 + v_xor_b32_e32 v17, v15, v7 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v63, v16, v6, v74 + v_xor_b32_e32 v16, v14, v26 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v65, v17, v4, v63 + v_xor_b32_e32 v17, v15, v12 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v60, v16, v3, v65 + v_xor_b32_e32 v16, v14, v28 + v_sub_u32_e32 v17, v16, v17 + v_lshlrev_b32_e32 v17, 2, v17 + v_add3_u32 v61, v17, v10, v60 + v_xor_b32_e32 v15, v15, v27 + v_sub_u32_e32 v16, v15, v16 + v_lshlrev_b32_e32 v16, 2, v16 + v_add3_u32 v56, v16, v5, v61 + v_xor_b32_e32 v14, v14, v29 + v_sub_u32_e32 v15, v14, v15 + v_lshlrev_b32_e32 v15, 2, v15 + v_add3_u32 v58, v15, v9, v56 + v_xor_b32_e32 v15, v13, v8 + v_sub_u32_e32 v14, v15, v14 + v_lshlrev_b32_e32 v14, 2, v14 + v_add3_u32 v75, v14, v2, v58 + v_xor_b32_e32 v2, v11, v8 + v_sub_u32_e32 v8, v2, v15 + v_lshl_add_u32 v76, v8, 2, v75 + v_xor_b32_e32 v7, v13, v7 + v_sub_u32_e32 v2, v7, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v68, v2, v6, v76 + v_xor_b32_e32 v2, v11, v26 + v_sub_u32_e32 v6, v2, v7 + v_lshlrev_b32_e32 v6, 2, v6 + v_add3_u32 v69, v6, v4, v68 + v_xor_b32_e32 v4, v13, v12 + v_sub_u32_e32 v2, v4, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v66, v2, v3, v69 + v_xor_b32_e32 v2, v11, v28 + v_sub_u32_e32 v3, v2, v4 + v_lshlrev_b32_e32 v3, 2, v3 + v_add3_u32 v67, v3, v10, v66 + v_xor_b32_e32 v3, v13, v27 + v_sub_u32_e32 v2, v3, v2 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v62, v2, v5, v67 + v_xor_b32_e32 v2, v11, v29 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 2, v2 + v_add3_u32 v64, v2, v9, v62 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + s_mov_b32 s18, 0x3020504 + s_mov_b32 s19, 0x5010400 + s_mov_b32 s23, 0x5040100 + s_mov_b32 s24, 0x7060302 + s_mov_b32 s25, 0x7030602 +.LBB39_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi16ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1477.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v18, s2, v18 + v_add_u32_e32 v83, 64, v20 + buffer_load_dwordx4 v[84:87], v20, s[8:11], 0 offen offset:64 + v_add_u32_e32 v6, s7, v83 + buffer_load_dwordx4 v[2:5], v18, s[12:15], 0 offen + v_add_u32_e32 v7, s22, v18 + buffer_load_dwordx4 v[92:95], v6, s[8:11], 0 offen + v_add_u32_e32 v6, s7, v6 + buffer_load_dwordx4 v[14:17], v7, s[12:15], 0 offen + v_add_u32_e32 v7, s22, v7 + v_add_u32_e32 v8, s7, v6 + buffer_load_dwordx4 v[10:13], v7, s[12:15], 0 offen + v_add_u32_e32 v7, s22, v7 + buffer_load_dwordx4 v[96:99], v6, s[8:11], 0 offen + buffer_load_dwordx4 v[88:91], v8, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[6:9], v7, s[12:15], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[22:23], v77 + ds_read_b64 v[20:21], v33 + ds_read_b32 v122, v42 offset:16384 + ds_read_b32 v123, v70 offset:16384 + ds_read_b32 v124, v44 offset:16384 + ds_read_b32 v125, v48 offset:16384 + ds_read_b32 v108, v43 offset:16384 + ds_read_b32 v109, v47 offset:16384 + ds_read_b32 v100, v45 offset:16384 + ds_read_b32 v101, v49 offset:16384 + ds_read_b32 v126, v71 offset:16384 + ds_read_b32 v127, v72 offset:16384 + ds_read_b32 v128, v57 offset:16384 + s_waitcnt lgkmcnt(9) + v_mfma_i32_32x32x16_i8 a[48:63], v[22:23], v[122:123], a[48:63] + ds_read_b32 v129, v59 offset:16384 + ds_read_b32 v110, v54 offset:16384 + ds_read_b32 v111, v55 offset:16384 + ds_read_b32 v102, v51 offset:16384 + ds_read_b32 v103, v53 offset:16384 + ds_read_b32 v130, v73 offset:16384 + ds_read_b32 v131, v74 offset:16384 + s_waitcnt lgkmcnt(8) + v_mfma_i32_32x32x16_i8 a[64:79], v[22:23], v[126:127], a[64:79] + ds_read_b32 v132, v63 offset:16384 + ds_read_b32 v133, v65 offset:16384 + ds_read_b32 v112, v60 offset:16384 + ds_read_b32 v113, v61 offset:16384 + ds_read_b32 v104, v56 offset:16384 + ds_read_b32 v105, v58 offset:16384 + ds_read_b32 v134, v75 offset:16384 + s_waitcnt lgkmcnt(7) + v_mfma_i32_32x32x16_i8 a[80:95], v[22:23], v[130:131], a[80:95] + ds_read_b32 v135, v76 offset:16384 + ds_read_b32 v136, v68 offset:16384 + ds_read_b32 v137, v69 offset:16384 + ds_read_b32 v114, v66 offset:16384 + ds_read_b32 v115, v67 offset:16384 + ds_read_b32 v106, v62 offset:16384 + ds_read_b32 v107, v64 offset:16384 + s_waitcnt lgkmcnt(6) + v_mfma_i32_32x32x16_i8 a[96:111], v[22:23], v[134:135], a[96:111] + ds_read_b64 v[22:23], v52 + ds_read_b64 v[28:29], v38 + ds_read_b64 v[26:27], v34 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[112:127], v[22:23], v[122:123], a[112:127] + v_mfma_i32_32x32x16_i8 a[144:159], v[22:23], v[126:127], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[22:23], v[130:131], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[22:23], v[134:135], a[176:191] + ds_read_b64 v[24:25], v50 + ds_read_b64 v[116:117], v40 + ds_read_b64 v[22:23], v36 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[192:207], v[24:25], v[122:123], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[24:25], v[126:127], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[24:25], v[130:131], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[24:25], v[134:135], a[240:255] + ds_read_b64 v[118:119], v46 + ds_read_b64 v[120:121], v41 + ds_read_b64 v[24:25], v39 + s_waitcnt lgkmcnt(2) + v_mfma_i32_32x32x16_i8 a[128:143], v[118:119], v[122:123], a[128:143] + v_mfma_i32_32x32x16_i8 a[32:47], v[118:119], v[126:127], a[32:47] + v_mfma_i32_32x32x16_i8 a[16:31], v[118:119], v[130:131], a[16:31] + v_mfma_i32_32x32x16_i8 a[0:15], v[118:119], v[134:135], a[0:15] + ds_read_b64 v[118:119], v37 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[118:119], v[124:125], a[48:63] + v_mfma_i32_32x32x16_i8 a[64:79], v[118:119], v[128:129], a[64:79] + v_mfma_i32_32x32x16_i8 a[80:95], v[118:119], v[132:133], a[80:95] + v_mfma_i32_32x32x16_i8 a[96:111], v[118:119], v[136:137], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[28:29], v[124:125], a[112:127] + v_mfma_i32_32x32x16_i8 a[144:159], v[28:29], v[128:129], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[28:29], v[132:133], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[28:29], v[136:137], a[176:191] + v_mfma_i32_32x32x16_i8 a[192:207], v[116:117], v[124:125], a[192:207] + v_mfma_i32_32x32x16_i8 a[208:223], v[116:117], v[128:129], a[208:223] + v_mfma_i32_32x32x16_i8 a[224:239], v[116:117], v[132:133], a[224:239] + v_mfma_i32_32x32x16_i8 a[240:255], v[116:117], v[136:137], a[240:255] + v_mfma_i32_32x32x16_i8 a[128:143], v[120:121], v[124:125], a[128:143] + v_mfma_i32_32x32x16_i8 a[32:47], v[120:121], v[128:129], a[32:47] + v_mfma_i32_32x32x16_i8 a[16:31], v[120:121], v[132:133], a[16:31] + v_mfma_i32_32x32x16_i8 a[0:15], v[120:121], v[136:137], a[0:15] + v_mfma_i32_32x32x16_i8 a[48:63], v[20:21], v[108:109], a[48:63] + v_mfma_i32_32x32x16_i8 a[64:79], v[20:21], v[110:111], a[64:79] + v_mfma_i32_32x32x16_i8 a[80:95], v[20:21], v[112:113], a[80:95] + v_mfma_i32_32x32x16_i8 a[96:111], v[20:21], v[114:115], a[96:111] + v_mfma_i32_32x32x16_i8 a[112:127], v[26:27], v[108:109], a[112:127] + v_mfma_i32_32x32x16_i8 a[144:159], v[26:27], v[110:111], a[144:159] + v_mfma_i32_32x32x16_i8 a[160:175], v[26:27], v[112:113], a[160:175] + v_mfma_i32_32x32x16_i8 a[176:191], v[26:27], v[114:115], a[176:191] + s_add_i32 s26, s3, -1 + v_readfirstlane_b32 s27, v0 + v_mfma_i32_32x32x16_i8 a[192:207], v[22:23], v[108:109], a[192:207] + s_and_b32 s28, s27, 0xffffffc0 + s_lshr_b32 s27, s27, 2 + v_add_u32_e32 v21, s28, v78 + s_and_b32 s27, s27, 0x3ffffff0 + v_mov_b32_e32 v20, v83 + v_ashrrev_i32_e32 v83, 1, v21 + v_ashrrev_i32_e32 v120, 31, v21 + v_mfma_i32_32x32x16_i8 a[208:223], v[22:23], v[110:111], a[208:223] + v_lshlrev_b32_e32 v121, 6, v21 + v_or_b32_e32 v122, 1, v21 + v_lshrrev_b32_e32 v123, 31, v21 + v_or_b32_e32 v21, 3, v21 + v_add_u32_e32 v124, s27, v79 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s26 + v_mfma_i32_32x32x16_i8 a[224:239], v[22:23], v[112:113], a[224:239] + ds_read_b64 v[26:27], v19 + ds_read_b64 v[28:29], v31 + ds_read_b64 v[116:117], v32 + ds_read_b64 v[118:119], v35 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshrrev_b32_e32 v120, 28, v120 + v_mfma_i32_32x32x16_i8 a[240:255], v[22:23], v[114:115], a[240:255] + v_add_u32_e32 v22, v122, v123 + v_or_b32_e32 v23, 1, v83 + v_add_u32_e32 v123, v21, v123 + v_lshrrev_b32_e32 v125, 1, v124 + v_lshlrev_b32_e32 v126, 9, v124 + v_lshlrev_b32_e32 v124, 6, v124 + v_add_u32_e32 v127, v83, v120 + v_mfma_i32_32x32x16_i8 a[128:143], v[24:25], v[108:109], a[128:143] + v_ashrrev_i32_e32 v108, 1, v22 + v_and_b32_e32 v109, 0x1ffffffe, v22 + v_ashrrev_i32_e32 v22, 31, v22 + v_add_u32_e32 v120, v23, v120 + v_ashrrev_i32_e32 v128, 1, v123 + v_and_b32_e32 v129, 0x1ffffffe, v123 + v_ashrrev_i32_e32 v123, 31, v123 + v_mfma_i32_32x32x16_i8 a[32:47], v[24:25], v[110:111], a[32:47] + v_and_b32_e32 v110, 16, v125 + v_and_b32_e32 v111, 0x3000, v126 + v_and_b32_e32 v124, 0xfffff800, v124 + v_and_b32_e32 v125, -16, v127 + v_sub_u32_e32 v126, v108, v83 + v_sub_u32_e32 v109, v122, v109 + v_lshrrev_b32_e32 v22, 28, v22 + v_mfma_i32_32x32x16_i8 a[16:31], v[24:25], v[112:113], a[16:31] + v_sub_u32_e32 v112, v23, v108 + v_and_b32_e32 v113, -16, v120 + v_sub_u32_e32 v120, v128, v23 + v_sub_u32_e32 v21, v21, v129 + v_lshrrev_b32_e32 v122, 28, v123 + v_xor_b32_e32 v123, v110, v30 + v_add_u32_e32 v111, v111, v124 + v_mfma_i32_32x32x16_i8 a[0:15], v[24:25], v[114:115], a[0:15] + v_or_b32_e32 v24, 1, v110 + v_or_b32_e32 v25, 2, v110 + v_or_b32_e32 v114, 3, v110 + v_or_b32_e32 v115, 4, v110 + v_or_b32_e32 v124, 5, v110 + v_or_b32_e32 v127, 6, v110 + v_or_b32_e32 v129, 7, v110 + v_mfma_i32_32x32x16_i8 a[48:63], v[26:27], v[100:101], a[48:63] + v_or_b32_e32 v130, 8, v110 + v_or_b32_e32 v131, 9, v110 + v_or_b32_e32 v132, 10, v110 + v_or_b32_e32 v133, 11, v110 + v_or_b32_e32 v134, 12, v110 + v_or_b32_e32 v135, 13, v110 + v_or_b32_e32 v136, 14, v110 + v_mfma_i32_32x32x16_i8 a[64:79], v[26:27], v[102:103], a[64:79] + v_or_b32_e32 v110, 15, v110 + v_sub_u32_e32 v83, v83, v125 + v_lshl_or_b32 v109, v109, 3, v81 + v_add_u32_e32 v22, v108, v22 + v_sub_u32_e32 v23, v23, v113 + v_lshlrev_b32_e32 v112, 7, v112 + v_lshl_or_b32 v21, v21, 3, v81 + v_mfma_i32_32x32x16_i8 a[80:95], v[26:27], v[104:105], a[80:95] + v_add_u32_e32 v113, v128, v122 + v_lshlrev_b32_e32 v120, 7, v120 + v_lshl_or_b32 v111, v123, 2, v111 + v_xor_b32_e32 v24, v24, v30 + v_xor_b32_e32 v25, v25, v30 + v_xor_b32_e32 v114, v114, v30 + v_xor_b32_e32 v115, v115, v30 + v_mfma_i32_32x32x16_i8 a[96:111], v[26:27], v[106:107], a[96:111] + v_xor_b32_e32 v26, v124, v30 + v_xor_b32_e32 v27, v127, v30 + v_xor_b32_e32 v122, v129, v30 + v_xor_b32_e32 v124, v130, v30 + v_xor_b32_e32 v125, v131, v30 + v_xor_b32_e32 v127, v132, v30 + v_xor_b32_e32 v129, v133, v30 + v_mfma_i32_32x32x16_i8 a[112:127], v[28:29], v[100:101], a[112:127] + v_xor_b32_e32 v130, v134, v30 + v_xor_b32_e32 v131, v135, v30 + v_xor_b32_e32 v132, v136, v30 + v_xor_b32_e32 v110, v110, v30 + v_xor_b32_e32 v133, v83, v80 + v_xor_b32_e32 v83, v83, v81 + v_add_u32_e32 v134, v109, v82 + v_mfma_i32_32x32x16_i8 a[144:159], v[28:29], v[102:103], a[144:159] + v_and_b32_e32 v22, -16, v22 + v_xor_b32_e32 v135, v23, v80 + v_xor_b32_e32 v23, v23, v81 + v_add_u32_e32 v136, v21, v82 + v_and_b32_e32 v113, -16, v113 + v_sub_u32_e32 v123, v24, v123 + v_sub_u32_e32 v24, v25, v24 + v_mfma_i32_32x32x16_i8 a[160:175], v[28:29], v[104:105], a[160:175] + v_sub_u32_e32 v25, v114, v25 + v_sub_u32_e32 v114, v115, v114 + v_sub_u32_e32 v115, v26, v115 + v_sub_u32_e32 v26, v27, v26 + v_sub_u32_e32 v27, v122, v27 + v_sub_u32_e32 v122, v124, v122 + v_sub_u32_e32 v124, v125, v124 + v_mfma_i32_32x32x16_i8 a[176:191], v[28:29], v[106:107], a[176:191] + v_sub_u32_e32 v28, v127, v125 + v_sub_u32_e32 v29, v129, v127 + v_sub_u32_e32 v125, v130, v129 + v_sub_u32_e32 v127, v131, v130 + v_sub_u32_e32 v129, v132, v131 + v_sub_u32_e32 v110, v110, v132 + v_lshl_add_u32 v130, v133, 3, v121 + v_mfma_i32_32x32x16_i8 a[192:207], v[116:117], v[100:101], a[192:207] + v_lshl_add_u32 v121, v83, 3, v121 + v_sub_u32_e32 v22, v108, v22 + v_sub_u32_e32 v108, v23, v135 + v_sub_u32_e32 v113, v128, v113 + v_lshl_add_u32 v123, v123, 2, v111 + v_lshlrev_b32_e32 v25, 2, v25 + v_lshlrev_b32_e32 v114, 2, v114 + v_mfma_i32_32x32x16_i8 a[208:223], v[116:117], v[102:103], a[208:223] + v_lshlrev_b32_e32 v115, 2, v115 + v_lshlrev_b32_e32 v26, 2, v26 + v_lshlrev_b32_e32 v27, 2, v27 + v_lshlrev_b32_e32 v122, 2, v122 + v_lshlrev_b32_e32 v124, 2, v124 + v_lshlrev_b32_e32 v28, 2, v28 + v_lshlrev_b32_e32 v29, 2, v29 + v_mfma_i32_32x32x16_i8 a[224:239], v[116:117], v[104:105], a[224:239] + v_lshlrev_b32_e32 v125, 2, v125 + v_lshlrev_b32_e32 v127, 2, v127 + v_lshlrev_b32_e32 v128, 2, v129 + v_xor_b32_e32 v129, v134, v22 + v_lshl_add_u32 v126, v126, 7, v121 + v_xor_b32_e32 v22, v109, v22 + v_xor_b32_e32 v109, v136, v113 + v_mfma_i32_32x32x16_i8 a[240:255], v[116:117], v[106:107], a[240:255] + v_xor_b32_e32 v21, v21, v113 + v_lshl_add_u32 v24, v24, 2, v123 + v_sub_u32_e32 v113, v129, v83 + v_sub_u32_e32 v83, v22, v83 + v_sub_u32_e32 v22, v135, v22 + v_sub_u32_e32 v23, v109, v23 + v_sub_u32_e32 v21, v21, v109 + v_mfma_i32_32x32x16_i8 a[128:143], v[118:119], v[100:101], a[128:143] + v_add3_u32 v25, v24, s6, v25 + v_lshl_add_u32 v100, v113, 3, v126 + v_lshl_add_u32 v83, v83, 3, v126 + v_lshlrev_b32_e32 v22, 3, v22 + v_lshlrev_b32_e32 v23, 3, v23 + v_add3_u32 v101, v25, s6, v114 + v_add3_u32 v22, v22, v112, v83 + v_mfma_i32_32x32x16_i8 a[32:47], v[118:119], v[102:103], a[32:47] + v_add3_u32 v102, v101, s6, v115 + v_lshl_add_u32 v103, v108, 3, v22 + v_add3_u32 v26, v102, s6, v26 + v_add3_u32 v23, v23, v120, v103 + v_add3_u32 v27, v26, s6, v27 + v_lshl_add_u32 v21, v21, 3, v23 + v_add3_u32 v108, v27, s6, v122 + v_mfma_i32_32x32x16_i8 a[16:31], v[118:119], v[104:105], a[16:31] + v_add3_u32 v104, v108, s6, v124 + v_add3_u32 v28, v104, s6, v28 + v_add3_u32 v29, v28, s6, v29 + v_add3_u32 v105, v29, s6, v125 + v_add3_u32 v109, v105, s6, v127 + v_add3_u32 v112, v109, s6, v128 + v_lshl_add_u32 v110, v110, 2, v112 + v_mfma_i32_32x32x16_i8 a[0:15], v[118:119], v[106:107], a[0:15] + s_waitcnt vmcnt(7) + ds_write_b64 v130, v[84:85] + ds_write_b64 v121, v[86:87] + s_waitcnt vmcnt(6) + v_perm_b32 v2, v2, v2, s18 + v_perm_b32 v3, v3, v3, s18 + v_perm_b32 v4, v4, v4, s18 + v_perm_b32 v5, v5, v5, s18 + s_waitcnt vmcnt(5) + ds_write_b64 v100, v[92:93] + ds_write_b64 v83, v[94:95] + s_waitcnt vmcnt(4) + v_perm_b32 v14, v14, v14, s18 + v_perm_b32 v15, v15, v15, s18 + v_perm_b32 v16, v16, v16, s18 + v_perm_b32 v17, v17, v17, s18 + s_waitcnt vmcnt(2) + ds_write_b64 v22, v[96:97] + ds_write_b64 v103, v[98:99] + v_perm_b32 v10, v10, v10, s18 + v_perm_b32 v11, v11, v11, s18 + v_perm_b32 v12, v12, v12, s18 + v_perm_b32 v13, v13, v13, s18 + v_perm_b32 v22, v14, v2, s19 + v_perm_b32 v2, v14, v2, s25 + v_perm_b32 v14, v15, v3, s19 + v_perm_b32 v3, v15, v3, s25 + v_perm_b32 v15, v16, v4, s19 + v_perm_b32 v4, v16, v4, s25 + v_perm_b32 v16, v17, v5, s19 + v_perm_b32 v5, v17, v5, s25 + s_waitcnt vmcnt(1) + ds_write_b64 v23, v[88:89] + ds_write_b64 v21, v[90:91] + s_waitcnt vmcnt(0) + v_perm_b32 v6, v6, v6, s18 + v_perm_b32 v7, v7, v7, s18 + v_perm_b32 v8, v8, v8, s18 + v_perm_b32 v9, v9, v9, s18 + v_perm_b32 v17, v6, v10, s19 + v_perm_b32 v6, v6, v10, s25 + v_perm_b32 v10, v7, v11, s19 + v_perm_b32 v7, v7, v11, s25 + v_perm_b32 v11, v8, v12, s19 + v_perm_b32 v8, v8, v12, s25 + v_perm_b32 v12, v9, v13, s19 + v_perm_b32 v9, v9, v13, s25 + v_perm_b32 v13, v17, v22, s23 + v_perm_b32 v17, v17, v22, s24 + v_perm_b32 v21, v6, v2, s23 + v_perm_b32 v2, v6, v2, s24 + v_perm_b32 v6, v10, v14, s23 + v_perm_b32 v10, v10, v14, s24 + v_perm_b32 v14, v7, v3, s23 + v_perm_b32 v3, v7, v3, s24 + v_perm_b32 v7, v11, v15, s23 + v_perm_b32 v11, v11, v15, s24 + v_perm_b32 v15, v8, v4, s23 + v_perm_b32 v4, v8, v4, s24 + v_perm_b32 v8, v12, v16, s23 + v_perm_b32 v12, v12, v16, s24 + v_perm_b32 v16, v9, v5, s23 + v_perm_b32 v5, v9, v5, s24 + ds_write_b32 v111, v13 offset:16384 + ds_write_b32 v123, v17 offset:16512 + ds_write_b32 v24, v21 offset:16640 + ds_write_b32 v25, v2 offset:16640 + ds_write_b32 v101, v6 offset:16640 + ds_write_b32 v102, v10 offset:16640 + ds_write_b32 v26, v14 offset:16640 + ds_write_b32 v27, v3 offset:16640 + ds_write_b32 v108, v7 offset:16640 + ds_write_b32 v104, v11 offset:16640 + ds_write_b32 v28, v15 offset:16640 + ds_write_b32 v29, v4 offset:16640 + ds_write_b32 v105, v8 offset:16640 + ds_write_b32 v109, v12 offset:16640 + ds_write_b32 v112, v16 offset:16640 + ds_write_b32 v110, v5 offset:16768 + s_cbranch_scc1 .LBB39_8 +.LBB39_9: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEaNS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDaRKS1N_RKT1_RKS1 + v_accvgpr_read_b32 v174, a48 + v_accvgpr_read_b32 v175, a49 + v_accvgpr_read_b32 v176, a50 + v_accvgpr_read_b32 v177, a51 + v_accvgpr_read_b32 v178, a52 + v_accvgpr_read_b32 v179, a53 + v_accvgpr_read_b32 v180, a54 + v_accvgpr_read_b32 v181, a55 + v_accvgpr_read_b32 v182, a56 + v_accvgpr_read_b32 v183, a57 + v_accvgpr_read_b32 v184, a58 + v_accvgpr_read_b32 v185, a59 + v_accvgpr_read_b32 v186, a60 + v_accvgpr_read_b32 v187, a61 + v_accvgpr_read_b32 v188, a62 + v_accvgpr_read_b32 v189, a63 + v_accvgpr_read_b32 v158, a64 + v_accvgpr_read_b32 v159, a65 + v_accvgpr_read_b32 v160, a66 + v_accvgpr_read_b32 v161, a67 + v_accvgpr_read_b32 v162, a68 + v_accvgpr_read_b32 v163, a69 + v_accvgpr_read_b32 v164, a70 + v_accvgpr_read_b32 v165, a71 + v_accvgpr_read_b32 v166, a72 + v_accvgpr_read_b32 v167, a73 + v_accvgpr_read_b32 v168, a74 + v_accvgpr_read_b32 v169, a75 + v_accvgpr_read_b32 v170, a76 + v_accvgpr_read_b32 v171, a77 + v_accvgpr_read_b32 v172, a78 + v_accvgpr_read_b32 v173, a79 + v_accvgpr_mov_b32 a48, a80 + v_accvgpr_mov_b32 a49, a81 + v_accvgpr_mov_b32 a50, a82 + v_accvgpr_mov_b32 a51, a83 + v_accvgpr_mov_b32 a52, a84 + v_accvgpr_mov_b32 a53, a85 + v_accvgpr_mov_b32 a54, a86 + v_accvgpr_mov_b32 a55, a87 + v_accvgpr_mov_b32 a56, a88 + v_accvgpr_mov_b32 a57, a89 + v_accvgpr_mov_b32 a58, a90 + v_accvgpr_mov_b32 a59, a91 + v_accvgpr_mov_b32 a60, a92 + v_accvgpr_mov_b32 a61, a93 + v_accvgpr_mov_b32 a62, a94 + v_accvgpr_mov_b32 a63, a95 + v_accvgpr_read_b32 v142, a96 + v_accvgpr_read_b32 v143, a97 + v_accvgpr_read_b32 v144, a98 + v_accvgpr_read_b32 v145, a99 + v_accvgpr_read_b32 v146, a100 + v_accvgpr_read_b32 v147, a101 + v_accvgpr_read_b32 v148, a102 + v_accvgpr_read_b32 v149, a103 + v_accvgpr_read_b32 v150, a104 + v_accvgpr_read_b32 v151, a105 + v_accvgpr_read_b32 v152, a106 + v_accvgpr_read_b32 v153, a107 + v_accvgpr_read_b32 v154, a108 + v_accvgpr_read_b32 v155, a109 + v_accvgpr_read_b32 v156, a110 + v_accvgpr_read_b32 v157, a111 + v_accvgpr_read_b32 v126, a112 + v_accvgpr_read_b32 v127, a113 + v_accvgpr_read_b32 v128, a114 + v_accvgpr_read_b32 v129, a115 + v_accvgpr_read_b32 v130, a116 + v_accvgpr_read_b32 v131, a117 + v_accvgpr_read_b32 v132, a118 + v_accvgpr_read_b32 v133, a119 + v_accvgpr_read_b32 v134, a120 + v_accvgpr_read_b32 v135, a121 + v_accvgpr_read_b32 v136, a122 + v_accvgpr_read_b32 v137, a123 + v_accvgpr_read_b32 v138, a124 + v_accvgpr_read_b32 v139, a125 + v_accvgpr_read_b32 v140, a126 + v_accvgpr_read_b32 v141, a127 + v_accvgpr_read_b32 v110, a144 + v_accvgpr_read_b32 v111, a145 + v_accvgpr_read_b32 v112, a146 + v_accvgpr_read_b32 v113, a147 + v_accvgpr_read_b32 v114, a148 + v_accvgpr_read_b32 v115, a149 + v_accvgpr_read_b32 v116, a150 + v_accvgpr_read_b32 v117, a151 + v_accvgpr_read_b32 v118, a152 + v_accvgpr_read_b32 v119, a153 + v_accvgpr_read_b32 v120, a154 + v_accvgpr_read_b32 v121, a155 + v_accvgpr_read_b32 v122, a156 + v_accvgpr_read_b32 v123, a157 + v_accvgpr_read_b32 v124, a158 + v_accvgpr_read_b32 v125, a159 + v_accvgpr_mov_b32 a64, a160 + v_accvgpr_mov_b32 a65, a161 + v_accvgpr_mov_b32 a66, a162 + v_accvgpr_mov_b32 a67, a163 + v_accvgpr_mov_b32 a68, a164 + v_accvgpr_mov_b32 a69, a165 + v_accvgpr_mov_b32 a70, a166 + v_accvgpr_mov_b32 a71, a167 + v_accvgpr_mov_b32 a72, a168 + v_accvgpr_mov_b32 a73, a169 + v_accvgpr_mov_b32 a74, a170 + v_accvgpr_mov_b32 a75, a171 + v_accvgpr_mov_b32 a76, a172 + v_accvgpr_mov_b32 a77, a173 + v_accvgpr_mov_b32 a78, a174 + v_accvgpr_mov_b32 a79, a175 + v_accvgpr_read_b32 v94, a176 + v_accvgpr_read_b32 v95, a177 + v_accvgpr_read_b32 v96, a178 + v_accvgpr_read_b32 v97, a179 + v_accvgpr_read_b32 v98, a180 + v_accvgpr_read_b32 v99, a181 + v_accvgpr_read_b32 v100, a182 + v_accvgpr_read_b32 v101, a183 + v_accvgpr_read_b32 v102, a184 + v_accvgpr_read_b32 v103, a185 + v_accvgpr_read_b32 v104, a186 + v_accvgpr_read_b32 v105, a187 + v_accvgpr_read_b32 v106, a188 + v_accvgpr_read_b32 v107, a189 + v_accvgpr_read_b32 v108, a190 + v_accvgpr_read_b32 v109, a191 + v_accvgpr_read_b32 v78, a192 + v_accvgpr_read_b32 v79, a193 + v_accvgpr_read_b32 v80, a194 + v_accvgpr_read_b32 v81, a195 + v_accvgpr_read_b32 v82, a196 + v_accvgpr_read_b32 v83, a197 + v_accvgpr_read_b32 v84, a198 + v_accvgpr_read_b32 v85, a199 + v_accvgpr_read_b32 v86, a200 + v_accvgpr_read_b32 v87, a201 + v_accvgpr_read_b32 v88, a202 + v_accvgpr_read_b32 v89, a203 + v_accvgpr_read_b32 v90, a204 + v_accvgpr_read_b32 v91, a205 + v_accvgpr_read_b32 v92, a206 + v_accvgpr_read_b32 v93, a207 + v_accvgpr_mov_b32 a144, a208 + v_accvgpr_mov_b32 a145, a209 + v_accvgpr_mov_b32 a146, a210 + v_accvgpr_mov_b32 a147, a211 + v_accvgpr_mov_b32 a148, a212 + v_accvgpr_mov_b32 a149, a213 + v_accvgpr_mov_b32 a150, a214 + v_accvgpr_mov_b32 a151, a215 + v_accvgpr_mov_b32 a152, a216 + v_accvgpr_mov_b32 a153, a217 + v_accvgpr_mov_b32 a154, a218 + v_accvgpr_mov_b32 a155, a219 + v_accvgpr_mov_b32 a156, a220 + v_accvgpr_mov_b32 a157, a221 + v_accvgpr_mov_b32 a158, a222 + v_accvgpr_mov_b32 a159, a223 + v_accvgpr_mov_b32 a80, a224 + v_accvgpr_mov_b32 a81, a225 + v_accvgpr_mov_b32 a82, a226 + v_accvgpr_mov_b32 a83, a227 + v_accvgpr_mov_b32 a84, a228 + v_accvgpr_mov_b32 a85, a229 + v_accvgpr_mov_b32 a86, a230 + v_accvgpr_mov_b32 a87, a231 + v_accvgpr_mov_b32 a88, a232 + v_accvgpr_mov_b32 a89, a233 + v_accvgpr_mov_b32 a90, a234 + v_accvgpr_mov_b32 a91, a235 + v_accvgpr_mov_b32 a92, a236 + v_accvgpr_mov_b32 a93, a237 + v_accvgpr_mov_b32 a94, a238 + v_accvgpr_mov_b32 a95, a239 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + v_accvgpr_mov_b32 a224, a128 + v_accvgpr_mov_b32 a225, a129 + v_accvgpr_mov_b32 a226, a130 + v_accvgpr_mov_b32 a227, a131 + v_accvgpr_mov_b32 a228, a132 + v_accvgpr_mov_b32 a229, a133 + v_accvgpr_mov_b32 a230, a134 + v_accvgpr_mov_b32 a231, a135 + v_accvgpr_mov_b32 a232, a136 + v_accvgpr_mov_b32 a233, a137 + v_accvgpr_mov_b32 a234, a138 + v_accvgpr_mov_b32 a235, a139 + v_accvgpr_mov_b32 a236, a140 + v_accvgpr_mov_b32 a237, a141 + v_accvgpr_mov_b32 a238, a142 + v_accvgpr_mov_b32 a239, a143 + v_accvgpr_mov_b32 a160, a32 + v_accvgpr_mov_b32 a161, a33 + v_accvgpr_mov_b32 a162, a34 + v_accvgpr_mov_b32 a163, a35 + v_accvgpr_mov_b32 a164, a36 + v_accvgpr_mov_b32 a165, a37 + v_accvgpr_mov_b32 a166, a38 + v_accvgpr_mov_b32 a167, a39 + v_accvgpr_mov_b32 a168, a40 + v_accvgpr_mov_b32 a169, a41 + v_accvgpr_mov_b32 a170, a42 + v_accvgpr_mov_b32 a171, a43 + v_accvgpr_mov_b32 a172, a44 + v_accvgpr_mov_b32 a173, a45 + v_accvgpr_mov_b32 a174, a46 + v_accvgpr_mov_b32 a175, a47 + v_accvgpr_mov_b32 a96, a16 + v_accvgpr_mov_b32 a97, a17 + v_accvgpr_mov_b32 a98, a18 + v_accvgpr_mov_b32 a99, a19 + v_accvgpr_mov_b32 a100, a20 + v_accvgpr_mov_b32 a101, a21 + v_accvgpr_mov_b32 a102, a22 + v_accvgpr_mov_b32 a103, a23 + v_accvgpr_mov_b32 a104, a24 + v_accvgpr_mov_b32 a105, a25 + v_accvgpr_mov_b32 a106, a26 + v_accvgpr_mov_b32 a107, a27 + v_accvgpr_mov_b32 a108, a28 + v_accvgpr_mov_b32 a109, a29 + v_accvgpr_mov_b32 a110, a30 + v_accvgpr_mov_b32 a111, a31 + v_accvgpr_mov_b32 a240, a0 + v_accvgpr_mov_b32 a241, a1 + v_accvgpr_mov_b32 a242, a2 + v_accvgpr_mov_b32 a243, a3 + v_accvgpr_mov_b32 a244, a4 + v_accvgpr_mov_b32 a245, a5 + v_accvgpr_mov_b32 a246, a6 + v_accvgpr_mov_b32 a247, a7 + v_accvgpr_mov_b32 a248, a8 + v_accvgpr_mov_b32 a249, a9 + v_accvgpr_mov_b32 a250, a10 + v_accvgpr_mov_b32 a251, a11 + v_accvgpr_mov_b32 a252, a12 + v_accvgpr_mov_b32 a253, a13 + v_accvgpr_mov_b32 a254, a14 + v_accvgpr_mov_b32 a255, a15 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64 v[20:21], v77 + ds_read_b32 v22, v42 offset:16384 + ds_read_b32 v23, v70 offset:16384 + v_accvgpr_write_b32 a191, v189 + v_accvgpr_write_b32 a190, v188 + v_accvgpr_write_b32 a189, v187 + v_accvgpr_write_b32 a188, v186 + v_accvgpr_write_b32 a187, v185 + v_accvgpr_write_b32 a186, v184 + v_accvgpr_write_b32 a185, v183 + v_accvgpr_write_b32 a184, v182 + v_accvgpr_write_b32 a183, v181 + v_accvgpr_write_b32 a182, v180 + v_accvgpr_write_b32 a181, v179 + v_accvgpr_write_b32 a180, v178 + v_accvgpr_write_b32 a179, v177 + v_accvgpr_write_b32 a178, v176 + v_accvgpr_write_b32 a177, v175 + v_accvgpr_write_b32 a176, v174 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[176:191], v[20:21], v[22:23], a[176:191] + ds_read_b32 v24, v71 offset:16384 + ds_read_b32 v25, v72 offset:16384 + v_accvgpr_write_b32 a112, v158 + v_accvgpr_write_b32 a113, v159 + v_accvgpr_write_b32 a114, v160 + v_accvgpr_write_b32 a115, v161 + v_accvgpr_write_b32 a116, v162 + v_accvgpr_write_b32 a117, v163 + v_accvgpr_write_b32 a118, v164 + v_accvgpr_write_b32 a119, v165 + v_accvgpr_write_b32 a120, v166 + v_accvgpr_write_b32 a121, v167 + v_accvgpr_write_b32 a122, v168 + v_accvgpr_write_b32 a123, v169 + v_accvgpr_write_b32 a124, v170 + v_accvgpr_write_b32 a125, v171 + v_accvgpr_write_b32 a126, v172 + v_accvgpr_write_b32 a127, v173 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[112:127], v[20:21], v[24:25], a[112:127] + ds_read_b32 v26, v73 offset:16384 + ds_read_b32 v27, v74 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[20:21], v[26:27], a[48:63] + ds_read_b32 v28, v75 offset:16384 + ds_read_b32 v29, v76 offset:16384 + v_accvgpr_write_b32 a0, v142 + v_accvgpr_write_b32 a1, v143 + v_accvgpr_write_b32 a2, v144 + v_accvgpr_write_b32 a3, v145 + v_accvgpr_write_b32 a4, v146 + v_accvgpr_write_b32 a5, v147 + v_accvgpr_write_b32 a6, v148 + v_accvgpr_write_b32 a7, v149 + v_accvgpr_write_b32 a8, v150 + v_accvgpr_write_b32 a9, v151 + v_accvgpr_write_b32 a10, v152 + v_accvgpr_write_b32 a11, v153 + v_accvgpr_write_b32 a12, v154 + v_accvgpr_write_b32 a13, v155 + v_accvgpr_write_b32 a14, v156 + v_accvgpr_write_b32 a15, v157 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[0:15], v[20:21], v[28:29], a[0:15] + ds_read_b64 v[20:21], v52 + v_accvgpr_write_b32 a207, v141 + v_accvgpr_write_b32 a206, v140 + v_accvgpr_write_b32 a205, v139 + v_accvgpr_write_b32 a204, v138 + v_accvgpr_write_b32 a203, v137 + v_accvgpr_write_b32 a202, v136 + v_accvgpr_write_b32 a201, v135 + v_accvgpr_write_b32 a200, v134 + v_accvgpr_write_b32 a199, v133 + v_accvgpr_write_b32 a198, v132 + v_accvgpr_write_b32 a197, v131 + v_accvgpr_write_b32 a196, v130 + v_accvgpr_write_b32 a195, v129 + v_accvgpr_write_b32 a194, v128 + v_accvgpr_write_b32 a193, v127 + v_accvgpr_write_b32 a192, v126 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[192:207], v[20:21], v[22:23], a[192:207] + v_accvgpr_write_b32 a143, v125 + v_accvgpr_write_b32 a142, v124 + v_accvgpr_write_b32 a141, v123 + v_accvgpr_write_b32 a140, v122 + v_accvgpr_write_b32 a139, v121 + v_accvgpr_write_b32 a138, v120 + v_accvgpr_write_b32 a137, v119 + v_accvgpr_write_b32 a136, v118 + v_accvgpr_write_b32 a135, v117 + v_accvgpr_write_b32 a134, v116 + v_accvgpr_write_b32 a133, v115 + v_accvgpr_write_b32 a132, v114 + v_accvgpr_write_b32 a131, v113 + v_accvgpr_write_b32 a130, v112 + v_accvgpr_write_b32 a129, v111 + v_accvgpr_write_b32 a128, v110 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[128:143], v[20:21], v[24:25], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[20:21], v[26:27], a[64:79] + v_accvgpr_write_b32 a16, v94 + v_accvgpr_write_b32 a17, v95 + v_accvgpr_write_b32 a18, v96 + v_accvgpr_write_b32 a19, v97 + v_accvgpr_write_b32 a20, v98 + v_accvgpr_write_b32 a21, v99 + v_accvgpr_write_b32 a22, v100 + v_accvgpr_write_b32 a23, v101 + v_accvgpr_write_b32 a24, v102 + v_accvgpr_write_b32 a25, v103 + v_accvgpr_write_b32 a26, v104 + v_accvgpr_write_b32 a27, v105 + v_accvgpr_write_b32 a28, v106 + v_accvgpr_write_b32 a29, v107 + v_accvgpr_write_b32 a30, v108 + v_accvgpr_write_b32 a31, v109 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[16:31], v[20:21], v[28:29], a[16:31] + ds_read_b64 v[20:21], v50 + v_accvgpr_write_b32 a223, v93 + v_accvgpr_write_b32 a222, v92 + v_accvgpr_write_b32 a221, v91 + v_accvgpr_write_b32 a220, v90 + v_accvgpr_write_b32 a219, v89 + v_accvgpr_write_b32 a218, v88 + v_accvgpr_write_b32 a217, v87 + v_accvgpr_write_b32 a216, v86 + v_accvgpr_write_b32 a215, v85 + v_accvgpr_write_b32 a214, v84 + v_accvgpr_write_b32 a213, v83 + v_accvgpr_write_b32 a212, v82 + v_accvgpr_write_b32 a211, v81 + v_accvgpr_write_b32 a210, v80 + v_accvgpr_write_b32 a209, v79 + v_accvgpr_write_b32 a208, v78 + s_waitcnt lgkmcnt(0) + s_nop 0 + v_mfma_i32_32x32x16_i8 a[208:223], v[20:21], v[22:23], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[20:21], v[24:25], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[20:21], v[26:27], a[80:95] + v_accvgpr_write_b32 a47, v17 + v_accvgpr_write_b32 a46, v16 + v_accvgpr_write_b32 a45, v15 + v_accvgpr_write_b32 a44, v14 + v_accvgpr_write_b32 a43, v13 + v_accvgpr_write_b32 a42, v12 + v_accvgpr_write_b32 a41, v11 + v_accvgpr_write_b32 a40, v10 + v_accvgpr_write_b32 a39, v9 + v_accvgpr_write_b32 a38, v8 + v_accvgpr_write_b32 a37, v7 + v_accvgpr_write_b32 a36, v6 + v_accvgpr_write_b32 a35, v5 + v_accvgpr_write_b32 a34, v4 + v_accvgpr_write_b32 a33, v3 + v_accvgpr_write_b32 a32, v2 + s_nop 1 + v_mfma_i32_32x32x16_i8 a[32:47], v[20:21], v[28:29], a[32:47] + ds_read_b64 v[2:3], v46 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[22:23], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[24:25], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[26:27], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[28:29], a[240:255] + ds_read_b64 v[2:3], v37 + ds_read_b32 v4, v44 offset:16384 + ds_read_b32 v5, v48 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b32 v6, v57 offset:16384 + ds_read_b32 v7, v59 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b32 v8, v63 offset:16384 + ds_read_b32 v9, v65 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v10, v68 offset:16384 + ds_read_b32 v11, v69 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v38 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v40 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v41 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] + ds_read_b64 v[2:3], v33 + ds_read_b32 v4, v43 offset:16384 + ds_read_b32 v5, v47 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b32 v6, v54 offset:16384 + ds_read_b32 v7, v55 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b32 v8, v60 offset:16384 + ds_read_b32 v9, v61 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v10, v66 offset:16384 + ds_read_b32 v11, v67 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v34 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v36 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v39 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] + ds_read_b64 v[2:3], v19 + ds_read_b32 v4, v45 offset:16384 + ds_read_b32 v5, v49 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[176:191], v[2:3], v[4:5], a[176:191] + ds_read_b32 v6, v51 offset:16384 + ds_read_b32 v7, v53 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[112:127], v[2:3], v[6:7], a[112:127] + ds_read_b32 v8, v56 offset:16384 + ds_read_b32 v9, v58 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[48:63], v[2:3], v[8:9], a[48:63] + ds_read_b32 v10, v62 offset:16384 + ds_read_b32 v11, v64 offset:16384 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[0:15], v[2:3], v[10:11], a[0:15] + ds_read_b64 v[2:3], v31 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[192:207], v[2:3], v[4:5], a[192:207] + v_mfma_i32_32x32x16_i8 a[128:143], v[2:3], v[6:7], a[128:143] + v_mfma_i32_32x32x16_i8 a[64:79], v[2:3], v[8:9], a[64:79] + v_mfma_i32_32x32x16_i8 a[16:31], v[2:3], v[10:11], a[16:31] + ds_read_b64 v[2:3], v32 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[208:223], v[2:3], v[4:5], a[208:223] + v_mfma_i32_32x32x16_i8 a[144:159], v[2:3], v[6:7], a[144:159] + v_mfma_i32_32x32x16_i8 a[80:95], v[2:3], v[8:9], a[80:95] + v_mfma_i32_32x32x16_i8 a[32:47], v[2:3], v[10:11], a[32:47] + ds_read_b64 v[2:3], v35 + s_waitcnt lgkmcnt(0) + v_mfma_i32_32x32x16_i8 a[224:239], v[2:3], v[4:5], a[224:239] + v_mfma_i32_32x32x16_i8 a[160:175], v[2:3], v[6:7], a[160:175] + v_mfma_i32_32x32x16_i8 a[96:111], v[2:3], v[8:9], a[96:111] + v_mfma_i32_32x32x16_i8 a[240:255], v[2:3], v[10:11], a[240:255] +.LBB39_10: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESB_SB_Li1EEEaNS_12element_wise11PassThroughESE_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKalLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSJ_IJNS_5embedINSJ_IJiiEEEST_Lb0EEENS_12pass_throughIiEESW_EEENSJ_IJNS3_IJLi0EEEENS3_IJLi1EEEENS3_IJLi2EEEEEEENSJ_IJNS3_IJLi1ELi2EEEENS3_IJLi3EEEENS3_IJLi4EEEEEEENS3_IJLi3ELi4EEEElNS3_IJLin1ELin1ELi16ELin1ELin1EEEENS3_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSJ_IJNS_8constantILi256EEENS1C_ILi64EEEEEEEEEEENSJ_IJNSK_IS1B_NSJ_IJS1E_S1D_EEEEEEEESE_SE_TnPNSt9enable_ifIXaasr11is_detectedINS_8is_tupleET_EE5valuesr11is_detectedIS1M_T0_EE5valueEbE4typeELPb0EEEDaRKS1N_RKT1_RKS1O + s_nop 10 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_add_i32 s2, s5, 0x3fffffff + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s2, s4 + s_add_u32 s4, s2, 1 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v18, 28, v1 + v_and_b32_e32 v19, 3, v1 + v_lshrrev_b32_e32 v20, 3, v1 + v_and_b32_e32 v22, 12, v20 + s_waitcnt lgkmcnt(0) + s_mov_b64 s[2:3], -1 + v_lshlrev_b32_e32 v23, 2, v19 + v_lshlrev_b32_e32 v21, 2, v18 + v_lshlrev_b32_e32 v20, 2, v1 + s_cbranch_scc1 .LBB39_13 +; %bb.11: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB39_14 +.LBB39_12: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESE_SE_Li1EEEaNS_12element_wise11PassThroughESH_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSO_SE_SH_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB39_13: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_or_b32_e32 v18, s3, v22 + s_barrier + v_lshl_or_b32 v18, v18, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v24, v18, v21, s3 + ds_write_b32 v24, a176 + ds_write_b32 v24, a177 offset:256 + ds_write_b32 v24, a178 offset:512 + ds_write_b32 v24, a179 offset:768 + ds_write_b32 v24, a180 offset:2048 + ds_write_b32 v24, a181 offset:2304 + ds_write_b32 v24, a182 offset:2560 + ds_write_b32 v24, a183 offset:2816 + ds_write_b32 v24, a184 offset:4096 + ds_write_b32 v24, a185 offset:4352 + ds_write_b32 v24, a186 offset:4608 + ds_write_b32 v24, a187 offset:4864 + ds_write_b32 v24, a188 offset:6144 + ds_write_b32 v24, a189 offset:6400 + ds_write_b32 v24, a190 offset:6656 + ds_write_b32 v24, a191 offset:6912 + ds_write_b32 v24, a192 offset:16384 + ds_write_b32 v24, a193 offset:16640 + ds_write_b32 v24, a194 offset:16896 + ds_write_b32 v24, a195 offset:17152 + ds_write_b32 v24, a196 offset:18432 + ds_write_b32 v24, a197 offset:18688 + ds_write_b32 v24, a198 offset:18944 + ds_write_b32 v24, a199 offset:19200 + ds_write_b32 v24, a200 offset:20480 + ds_write_b32 v24, a201 offset:20736 + ds_write_b32 v24, a202 offset:20992 + ds_write_b32 v24, a203 offset:21248 + ds_write_b32 v24, a204 offset:22528 + ds_write_b32 v24, a205 offset:22784 + ds_write_b32 v24, a206 offset:23040 + ds_write_b32 v24, a207 offset:23296 + ds_write_b32 v24, a208 offset:32768 + ds_write_b32 v24, a209 offset:33024 + ds_write_b32 v24, a210 offset:33280 + ds_write_b32 v24, a211 offset:33536 + ds_write_b32 v24, a212 offset:34816 + ds_write_b32 v24, a213 offset:35072 + ds_write_b32 v24, a214 offset:35328 + ds_write_b32 v24, a215 offset:35584 + ds_write_b32 v24, a216 offset:36864 + ds_write_b32 v24, a217 offset:37120 + ds_write_b32 v24, a218 offset:37376 + ds_write_b32 v24, a219 offset:37632 + ds_write_b32 v24, a220 offset:38912 + ds_write_b32 v24, a221 offset:39168 + ds_write_b32 v24, a222 offset:39424 + ds_write_b32 v24, a223 offset:39680 + ds_write_b32 v24, a224 offset:49152 + ds_write_b32 v24, a225 offset:49408 + ds_write_b32 v24, a226 offset:49664 + ds_write_b32 v24, a227 offset:49920 + ds_write_b32 v24, a228 offset:51200 + ds_write_b32 v24, a229 offset:51456 + ds_write_b32 v24, a230 offset:51712 + ds_write_b32 v24, a231 offset:51968 + ds_write_b32 v24, a232 offset:53248 + ds_write_b32 v24, a233 offset:53504 + ds_write_b32 v24, a234 offset:53760 + ds_write_b32 v24, a235 offset:54016 + ds_write_b32 v24, a236 offset:55296 + ds_write_b32 v24, a237 offset:55552 + ds_write_b32 v24, a238 offset:55808 + ds_write_b32 v24, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v18, 60, v20 + s_andn2_b32 s2, s2, 63 + v_and_b32_e32 v19, 0x70, v1 + v_add_u32_e32 v19, s2, v19 + v_lshlrev_b32_e32 v25, 8, v19 + v_lshl_or_b32 v25, v18, 2, v25 + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, s20, v19 + v_or_b32_e32 v18, s21, v18 + v_mad_u64_u32 v[18:19], s[2:3], v19, s16, v[18:19] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v18 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a112 + ds_write_b32 v24, a113 offset:256 + ds_write_b32 v24, a114 offset:512 + ds_write_b32 v24, a115 offset:768 + ds_write_b32 v24, a116 offset:2048 + ds_write_b32 v24, a117 offset:2304 + ds_write_b32 v24, a118 offset:2560 + ds_write_b32 v24, a119 offset:2816 + ds_write_b32 v24, a120 offset:4096 + ds_write_b32 v24, a121 offset:4352 + ds_write_b32 v24, a122 offset:4608 + ds_write_b32 v24, a123 offset:4864 + ds_write_b32 v24, a124 offset:6144 + ds_write_b32 v24, a125 offset:6400 + ds_write_b32 v24, a126 offset:6656 + ds_write_b32 v24, a127 offset:6912 + ds_write_b32 v24, a128 offset:16384 + ds_write_b32 v24, a129 offset:16640 + ds_write_b32 v24, a130 offset:16896 + ds_write_b32 v24, a131 offset:17152 + ds_write_b32 v24, a132 offset:18432 + ds_write_b32 v24, a133 offset:18688 + ds_write_b32 v24, a134 offset:18944 + ds_write_b32 v24, a135 offset:19200 + ds_write_b32 v24, a136 offset:20480 + ds_write_b32 v24, a137 offset:20736 + ds_write_b32 v24, a138 offset:20992 + ds_write_b32 v24, a139 offset:21248 + ds_write_b32 v24, a140 offset:22528 + ds_write_b32 v24, a141 offset:22784 + ds_write_b32 v24, a142 offset:23040 + ds_write_b32 v24, a143 offset:23296 + ds_write_b32 v24, a144 offset:32768 + ds_write_b32 v24, a145 offset:33024 + ds_write_b32 v24, a146 offset:33280 + ds_write_b32 v24, a147 offset:33536 + ds_write_b32 v24, a148 offset:34816 + ds_write_b32 v24, a149 offset:35072 + ds_write_b32 v24, a150 offset:35328 + ds_write_b32 v24, a151 offset:35584 + ds_write_b32 v24, a152 offset:36864 + ds_write_b32 v24, a153 offset:37120 + ds_write_b32 v24, a154 offset:37376 + ds_write_b32 v24, a155 offset:37632 + ds_write_b32 v24, a156 offset:38912 + ds_write_b32 v24, a157 offset:39168 + ds_write_b32 v24, a158 offset:39424 + ds_write_b32 v24, a159 offset:39680 + ds_write_b32 v24, a160 offset:49152 + ds_write_b32 v24, a161 offset:49408 + ds_write_b32 v24, a162 offset:49664 + ds_write_b32 v24, a163 offset:49920 + ds_write_b32 v24, a164 offset:51200 + ds_write_b32 v24, a165 offset:51456 + ds_write_b32 v24, a166 offset:51712 + ds_write_b32 v24, a167 offset:51968 + ds_write_b32 v24, a168 offset:53248 + ds_write_b32 v24, a169 offset:53504 + ds_write_b32 v24, a170 offset:53760 + ds_write_b32 v24, a171 offset:54016 + ds_write_b32 v24, a172 offset:55296 + ds_write_b32 v24, a173 offset:55552 + ds_write_b32 v24, a174 offset:55808 + ds_write_b32 v24, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 64, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a48 + ds_write_b32 v24, a49 offset:256 + ds_write_b32 v24, a50 offset:512 + ds_write_b32 v24, a51 offset:768 + ds_write_b32 v24, a52 offset:2048 + ds_write_b32 v24, a53 offset:2304 + ds_write_b32 v24, a54 offset:2560 + ds_write_b32 v24, a55 offset:2816 + ds_write_b32 v24, a56 offset:4096 + ds_write_b32 v24, a57 offset:4352 + ds_write_b32 v24, a58 offset:4608 + ds_write_b32 v24, a59 offset:4864 + ds_write_b32 v24, a60 offset:6144 + ds_write_b32 v24, a61 offset:6400 + ds_write_b32 v24, a62 offset:6656 + ds_write_b32 v24, a63 offset:6912 + ds_write_b32 v24, a64 offset:16384 + ds_write_b32 v24, a65 offset:16640 + ds_write_b32 v24, a66 offset:16896 + ds_write_b32 v24, a67 offset:17152 + ds_write_b32 v24, a68 offset:18432 + ds_write_b32 v24, a69 offset:18688 + ds_write_b32 v24, a70 offset:18944 + ds_write_b32 v24, a71 offset:19200 + ds_write_b32 v24, a72 offset:20480 + ds_write_b32 v24, a73 offset:20736 + ds_write_b32 v24, a74 offset:20992 + ds_write_b32 v24, a75 offset:21248 + ds_write_b32 v24, a76 offset:22528 + ds_write_b32 v24, a77 offset:22784 + ds_write_b32 v24, a78 offset:23040 + ds_write_b32 v24, a79 offset:23296 + ds_write_b32 v24, a80 offset:32768 + ds_write_b32 v24, a81 offset:33024 + ds_write_b32 v24, a82 offset:33280 + ds_write_b32 v24, a83 offset:33536 + ds_write_b32 v24, a84 offset:34816 + ds_write_b32 v24, a85 offset:35072 + ds_write_b32 v24, a86 offset:35328 + ds_write_b32 v24, a87 offset:35584 + ds_write_b32 v24, a88 offset:36864 + ds_write_b32 v24, a89 offset:37120 + ds_write_b32 v24, a90 offset:37376 + ds_write_b32 v24, a91 offset:37632 + ds_write_b32 v24, a92 offset:38912 + ds_write_b32 v24, a93 offset:39168 + ds_write_b32 v24, a94 offset:39424 + ds_write_b32 v24, a95 offset:39680 + ds_write_b32 v24, a96 offset:49152 + ds_write_b32 v24, a97 offset:49408 + ds_write_b32 v24, a98 offset:49664 + ds_write_b32 v24, a99 offset:49920 + ds_write_b32 v24, a100 offset:51200 + ds_write_b32 v24, a101 offset:51456 + ds_write_b32 v24, a102 offset:51712 + ds_write_b32 v24, a103 offset:51968 + ds_write_b32 v24, a104 offset:53248 + ds_write_b32 v24, a105 offset:53504 + ds_write_b32 v24, a106 offset:53760 + ds_write_b32 v24, a107 offset:54016 + ds_write_b32 v24, a108 offset:55296 + ds_write_b32 v24, a109 offset:55552 + ds_write_b32 v24, a110 offset:55808 + ds_write_b32 v24, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v19, 0x80, v18 + v_lshlrev_b32_e32 v90, 2, v19 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v90, s[0:3], 0 offen + buffer_atomic_add v27, v90, s[0:3], 4 offen + buffer_atomic_add v28, v90, s[0:3], 8 offen + buffer_atomic_add v29, v90, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + buffer_atomic_add v30, v26, s[0:3], 0 offen + buffer_atomic_add v31, v26, s[0:3], 4 offen + buffer_atomic_add v32, v26, s[0:3], 8 offen + buffer_atomic_add v33, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v26, s[0:3], 0 offen + buffer_atomic_add v35, v26, s[0:3], 4 offen + buffer_atomic_add v36, v26, s[0:3], 8 offen + buffer_atomic_add v37, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v26, s[0:3], 0 offen + buffer_atomic_add v39, v26, s[0:3], 4 offen + buffer_atomic_add v40, v26, s[0:3], 8 offen + buffer_atomic_add v41, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v26, s[0:3], 0 offen + buffer_atomic_add v43, v26, s[0:3], 4 offen + buffer_atomic_add v44, v26, s[0:3], 8 offen + buffer_atomic_add v45, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v26, s[0:3], 0 offen + buffer_atomic_add v47, v26, s[0:3], 4 offen + buffer_atomic_add v48, v26, s[0:3], 8 offen + buffer_atomic_add v49, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v26, s[0:3], 0 offen + buffer_atomic_add v51, v26, s[0:3], 4 offen + buffer_atomic_add v52, v26, s[0:3], 8 offen + buffer_atomic_add v53, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v26, s[0:3], 0 offen + buffer_atomic_add v55, v26, s[0:3], 4 offen + buffer_atomic_add v56, v26, s[0:3], 8 offen + buffer_atomic_add v57, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v26, s[0:3], 0 offen + buffer_atomic_add v59, v26, s[0:3], 4 offen + buffer_atomic_add v60, v26, s[0:3], 8 offen + buffer_atomic_add v61, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v26, s[0:3], 0 offen + buffer_atomic_add v63, v26, s[0:3], 4 offen + buffer_atomic_add v64, v26, s[0:3], 8 offen + buffer_atomic_add v65, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v26, s[0:3], 0 offen + buffer_atomic_add v67, v26, s[0:3], 4 offen + buffer_atomic_add v68, v26, s[0:3], 8 offen + buffer_atomic_add v69, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v26, s[0:3], 0 offen + buffer_atomic_add v71, v26, s[0:3], 4 offen + buffer_atomic_add v72, v26, s[0:3], 8 offen + buffer_atomic_add v73, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v26, s[0:3], 0 offen + buffer_atomic_add v75, v26, s[0:3], 4 offen + buffer_atomic_add v76, v26, s[0:3], 8 offen + buffer_atomic_add v77, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v26, s[0:3], 0 offen + buffer_atomic_add v79, v26, s[0:3], 4 offen + buffer_atomic_add v80, v26, s[0:3], 8 offen + buffer_atomic_add v81, v26, s[0:3], 12 offen + v_add_u32_e32 v19, s16, v19 + v_lshlrev_b32_e32 v26, 2, v19 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v26, s[0:3], 0 offen + buffer_atomic_add v83, v26, s[0:3], 4 offen + buffer_atomic_add v84, v26, s[0:3], 8 offen + buffer_atomic_add v85, v26, s[0:3], 12 offen + v_add_lshl_u32 v19, v19, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v19, s[0:3], 0 offen + buffer_atomic_add v87, v19, s[0:3], 4 offen + buffer_atomic_add v88, v19, s[0:3], 8 offen + buffer_atomic_add v89, v19, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v24, a0 + ds_write_b32 v24, a1 offset:256 + ds_write_b32 v24, a2 offset:512 + ds_write_b32 v24, a3 offset:768 + ds_write_b32 v24, a4 offset:2048 + ds_write_b32 v24, a5 offset:2304 + ds_write_b32 v24, a6 offset:2560 + ds_write_b32 v24, a7 offset:2816 + ds_write_b32 v24, a8 offset:4096 + ds_write_b32 v24, a9 offset:4352 + ds_write_b32 v24, a10 offset:4608 + ds_write_b32 v24, a11 offset:4864 + ds_write_b32 v24, a12 offset:6144 + ds_write_b32 v24, a13 offset:6400 + ds_write_b32 v24, a14 offset:6656 + ds_write_b32 v24, a15 offset:6912 + ds_write_b32 v24, a16 offset:16384 + ds_write_b32 v24, a17 offset:16640 + ds_write_b32 v24, a18 offset:16896 + ds_write_b32 v24, a19 offset:17152 + ds_write_b32 v24, a20 offset:18432 + ds_write_b32 v24, a21 offset:18688 + ds_write_b32 v24, a22 offset:18944 + ds_write_b32 v24, a23 offset:19200 + ds_write_b32 v24, a24 offset:20480 + ds_write_b32 v24, a25 offset:20736 + ds_write_b32 v24, a26 offset:20992 + ds_write_b32 v24, a27 offset:21248 + ds_write_b32 v24, a28 offset:22528 + ds_write_b32 v24, a29 offset:22784 + ds_write_b32 v24, a30 offset:23040 + ds_write_b32 v24, a31 offset:23296 + ds_write_b32 v24, a32 offset:32768 + ds_write_b32 v24, a33 offset:33024 + ds_write_b32 v24, a34 offset:33280 + ds_write_b32 v24, a35 offset:33536 + ds_write_b32 v24, a36 offset:34816 + ds_write_b32 v24, a37 offset:35072 + ds_write_b32 v24, a38 offset:35328 + ds_write_b32 v24, a39 offset:35584 + ds_write_b32 v24, a40 offset:36864 + ds_write_b32 v24, a41 offset:37120 + ds_write_b32 v24, a42 offset:37376 + ds_write_b32 v24, a43 offset:37632 + ds_write_b32 v24, a44 offset:38912 + ds_write_b32 v24, a45 offset:39168 + ds_write_b32 v24, a46 offset:39424 + ds_write_b32 v24, a47 offset:39680 + ds_write2st64_b32 v24, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v24, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v24, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v24, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v24, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v24, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v24, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v24, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[26:29], v25 + ds_read_b128 v[30:33], v25 offset:256 + ds_read_b128 v[34:37], v25 offset:512 + ds_read_b128 v[38:41], v25 offset:768 + ds_read_b128 v[42:45], v25 offset:1024 + ds_read_b128 v[46:49], v25 offset:1280 + ds_read_b128 v[50:53], v25 offset:1536 + ds_read_b128 v[54:57], v25 offset:1792 + ds_read_b128 v[58:61], v25 offset:2048 + ds_read_b128 v[62:65], v25 offset:2304 + ds_read_b128 v[66:69], v25 offset:2560 + ds_read_b128 v[70:73], v25 offset:2816 + ds_read_b128 v[74:77], v25 offset:3072 + ds_read_b128 v[78:81], v25 offset:3328 + ds_read_b128 v[82:85], v25 offset:3584 + ds_read_b128 v[86:89], v25 offset:3840 + v_add_u32_e32 v18, 0xc0, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(14) + buffer_atomic_add v26, v19, s[0:3], 0 offen + buffer_atomic_add v27, v19, s[0:3], 4 offen + buffer_atomic_add v28, v19, s[0:3], 8 offen + buffer_atomic_add v29, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + buffer_atomic_add v30, v19, s[0:3], 0 offen + buffer_atomic_add v31, v19, s[0:3], 4 offen + buffer_atomic_add v32, v19, s[0:3], 8 offen + buffer_atomic_add v33, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(13) + buffer_atomic_add v34, v19, s[0:3], 0 offen + buffer_atomic_add v35, v19, s[0:3], 4 offen + buffer_atomic_add v36, v19, s[0:3], 8 offen + buffer_atomic_add v37, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(12) + buffer_atomic_add v38, v19, s[0:3], 0 offen + buffer_atomic_add v39, v19, s[0:3], 4 offen + buffer_atomic_add v40, v19, s[0:3], 8 offen + buffer_atomic_add v41, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(11) + buffer_atomic_add v42, v19, s[0:3], 0 offen + buffer_atomic_add v43, v19, s[0:3], 4 offen + buffer_atomic_add v44, v19, s[0:3], 8 offen + buffer_atomic_add v45, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(10) + buffer_atomic_add v46, v19, s[0:3], 0 offen + buffer_atomic_add v47, v19, s[0:3], 4 offen + buffer_atomic_add v48, v19, s[0:3], 8 offen + buffer_atomic_add v49, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(9) + buffer_atomic_add v50, v19, s[0:3], 0 offen + buffer_atomic_add v51, v19, s[0:3], 4 offen + buffer_atomic_add v52, v19, s[0:3], 8 offen + buffer_atomic_add v53, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(8) + buffer_atomic_add v54, v19, s[0:3], 0 offen + buffer_atomic_add v55, v19, s[0:3], 4 offen + buffer_atomic_add v56, v19, s[0:3], 8 offen + buffer_atomic_add v57, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(7) + buffer_atomic_add v58, v19, s[0:3], 0 offen + buffer_atomic_add v59, v19, s[0:3], 4 offen + buffer_atomic_add v60, v19, s[0:3], 8 offen + buffer_atomic_add v61, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(6) + buffer_atomic_add v62, v19, s[0:3], 0 offen + buffer_atomic_add v63, v19, s[0:3], 4 offen + buffer_atomic_add v64, v19, s[0:3], 8 offen + buffer_atomic_add v65, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(5) + buffer_atomic_add v66, v19, s[0:3], 0 offen + buffer_atomic_add v67, v19, s[0:3], 4 offen + buffer_atomic_add v68, v19, s[0:3], 8 offen + buffer_atomic_add v69, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(4) + buffer_atomic_add v70, v19, s[0:3], 0 offen + buffer_atomic_add v71, v19, s[0:3], 4 offen + buffer_atomic_add v72, v19, s[0:3], 8 offen + buffer_atomic_add v73, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(3) + buffer_atomic_add v74, v19, s[0:3], 0 offen + buffer_atomic_add v75, v19, s[0:3], 4 offen + buffer_atomic_add v76, v19, s[0:3], 8 offen + buffer_atomic_add v77, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(2) + buffer_atomic_add v78, v19, s[0:3], 0 offen + buffer_atomic_add v79, v19, s[0:3], 4 offen + buffer_atomic_add v80, v19, s[0:3], 8 offen + buffer_atomic_add v81, v19, s[0:3], 12 offen + v_add_u32_e32 v18, s16, v18 + v_lshlrev_b32_e32 v19, 2, v18 + s_waitcnt lgkmcnt(1) + buffer_atomic_add v82, v19, s[0:3], 0 offen + buffer_atomic_add v83, v19, s[0:3], 4 offen + buffer_atomic_add v84, v19, s[0:3], 8 offen + buffer_atomic_add v85, v19, s[0:3], 12 offen + v_add_lshl_u32 v18, v18, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_atomic_add v86, v18, s[0:3], 0 offen + buffer_atomic_add v87, v18, s[0:3], 4 offen + buffer_atomic_add v88, v18, s[0:3], 8 offen + buffer_atomic_add v89, v18, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB39_12 +.LBB39_14: + v_readfirstlane_b32 s2, v0 + s_lshr_b32 s3, s2, 2 + s_and_b32 s3, s3, 0xffffe0 + v_or_b32_e32 v0, s3, v22 + s_barrier + v_lshl_or_b32 v0, v0, 8, v23 + s_lshl_b32 s3, s2, 1 + s_and_b32 s3, s3, 0x80 + v_add3_u32 v82, v0, v21, s3 + ds_write_b32 v82, a176 + ds_write_b32 v82, a177 offset:256 + ds_write_b32 v82, a178 offset:512 + ds_write_b32 v82, a179 offset:768 + ds_write_b32 v82, a180 offset:2048 + ds_write_b32 v82, a181 offset:2304 + ds_write_b32 v82, a182 offset:2560 + ds_write_b32 v82, a183 offset:2816 + ds_write_b32 v82, a184 offset:4096 + ds_write_b32 v82, a185 offset:4352 + ds_write_b32 v82, a186 offset:4608 + ds_write_b32 v82, a187 offset:4864 + ds_write_b32 v82, a188 offset:6144 + ds_write_b32 v82, a189 offset:6400 + ds_write_b32 v82, a190 offset:6656 + ds_write_b32 v82, a191 offset:6912 + ds_write_b32 v82, a192 offset:16384 + ds_write_b32 v82, a193 offset:16640 + ds_write_b32 v82, a194 offset:16896 + ds_write_b32 v82, a195 offset:17152 + ds_write_b32 v82, a196 offset:18432 + ds_write_b32 v82, a197 offset:18688 + ds_write_b32 v82, a198 offset:18944 + ds_write_b32 v82, a199 offset:19200 + ds_write_b32 v82, a200 offset:20480 + ds_write_b32 v82, a201 offset:20736 + ds_write_b32 v82, a202 offset:20992 + ds_write_b32 v82, a203 offset:21248 + ds_write_b32 v82, a204 offset:22528 + ds_write_b32 v82, a205 offset:22784 + ds_write_b32 v82, a206 offset:23040 + ds_write_b32 v82, a207 offset:23296 + ds_write_b32 v82, a208 offset:32768 + ds_write_b32 v82, a209 offset:33024 + ds_write_b32 v82, a210 offset:33280 + ds_write_b32 v82, a211 offset:33536 + ds_write_b32 v82, a212 offset:34816 + ds_write_b32 v82, a213 offset:35072 + ds_write_b32 v82, a214 offset:35328 + ds_write_b32 v82, a215 offset:35584 + ds_write_b32 v82, a216 offset:36864 + ds_write_b32 v82, a217 offset:37120 + ds_write_b32 v82, a218 offset:37376 + ds_write_b32 v82, a219 offset:37632 + ds_write_b32 v82, a220 offset:38912 + ds_write_b32 v82, a221 offset:39168 + ds_write_b32 v82, a222 offset:39424 + ds_write_b32 v82, a223 offset:39680 + ds_write_b32 v82, a224 offset:49152 + ds_write_b32 v82, a225 offset:49408 + ds_write_b32 v82, a226 offset:49664 + ds_write_b32 v82, a227 offset:49920 + ds_write_b32 v82, a228 offset:51200 + ds_write_b32 v82, a229 offset:51456 + ds_write_b32 v82, a230 offset:51712 + ds_write_b32 v82, a231 offset:51968 + ds_write_b32 v82, a232 offset:53248 + ds_write_b32 v82, a233 offset:53504 + ds_write_b32 v82, a234 offset:53760 + ds_write_b32 v82, a235 offset:54016 + ds_write_b32 v82, a236 offset:55296 + ds_write_b32 v82, a237 offset:55552 + ds_write_b32 v82, a238 offset:55808 + ds_write_b32 v82, a239 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 60, v20 + s_andn2_b32 s2, s2, 63 + v_and_b32_e32 v1, 0x70, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 8, v1 + v_lshl_or_b32 v83, v0, 2, v18 + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, s20, v1 + v_or_b32_e32 v0, s21, v0 + v_mad_u64_u32 v[0:1], s[2:3], v1, s16, v[0:1] + s_lshl_b32 s2, s4, 2 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + s_nop 0 + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v0 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a112 + ds_write_b32 v82, a113 offset:256 + ds_write_b32 v82, a114 offset:512 + ds_write_b32 v82, a115 offset:768 + ds_write_b32 v82, a116 offset:2048 + ds_write_b32 v82, a117 offset:2304 + ds_write_b32 v82, a118 offset:2560 + ds_write_b32 v82, a119 offset:2816 + ds_write_b32 v82, a120 offset:4096 + ds_write_b32 v82, a121 offset:4352 + ds_write_b32 v82, a122 offset:4608 + ds_write_b32 v82, a123 offset:4864 + ds_write_b32 v82, a124 offset:6144 + ds_write_b32 v82, a125 offset:6400 + ds_write_b32 v82, a126 offset:6656 + ds_write_b32 v82, a127 offset:6912 + ds_write_b32 v82, a128 offset:16384 + ds_write_b32 v82, a129 offset:16640 + ds_write_b32 v82, a130 offset:16896 + ds_write_b32 v82, a131 offset:17152 + ds_write_b32 v82, a132 offset:18432 + ds_write_b32 v82, a133 offset:18688 + ds_write_b32 v82, a134 offset:18944 + ds_write_b32 v82, a135 offset:19200 + ds_write_b32 v82, a136 offset:20480 + ds_write_b32 v82, a137 offset:20736 + ds_write_b32 v82, a138 offset:20992 + ds_write_b32 v82, a139 offset:21248 + ds_write_b32 v82, a140 offset:22528 + ds_write_b32 v82, a141 offset:22784 + ds_write_b32 v82, a142 offset:23040 + ds_write_b32 v82, a143 offset:23296 + ds_write_b32 v82, a144 offset:32768 + ds_write_b32 v82, a145 offset:33024 + ds_write_b32 v82, a146 offset:33280 + ds_write_b32 v82, a147 offset:33536 + ds_write_b32 v82, a148 offset:34816 + ds_write_b32 v82, a149 offset:35072 + ds_write_b32 v82, a150 offset:35328 + ds_write_b32 v82, a151 offset:35584 + ds_write_b32 v82, a152 offset:36864 + ds_write_b32 v82, a153 offset:37120 + ds_write_b32 v82, a154 offset:37376 + ds_write_b32 v82, a155 offset:37632 + ds_write_b32 v82, a156 offset:38912 + ds_write_b32 v82, a157 offset:39168 + ds_write_b32 v82, a158 offset:39424 + ds_write_b32 v82, a159 offset:39680 + ds_write_b32 v82, a160 offset:49152 + ds_write_b32 v82, a161 offset:49408 + ds_write_b32 v82, a162 offset:49664 + ds_write_b32 v82, a163 offset:49920 + ds_write_b32 v82, a164 offset:51200 + ds_write_b32 v82, a165 offset:51456 + ds_write_b32 v82, a166 offset:51712 + ds_write_b32 v82, a167 offset:51968 + ds_write_b32 v82, a168 offset:53248 + ds_write_b32 v82, a169 offset:53504 + ds_write_b32 v82, a170 offset:53760 + ds_write_b32 v82, a171 offset:54016 + ds_write_b32 v82, a172 offset:55296 + ds_write_b32 v82, a173 offset:55552 + ds_write_b32 v82, a174 offset:55808 + ds_write_b32 v82, a175 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 64, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a48 + ds_write_b32 v82, a49 offset:256 + ds_write_b32 v82, a50 offset:512 + ds_write_b32 v82, a51 offset:768 + ds_write_b32 v82, a52 offset:2048 + ds_write_b32 v82, a53 offset:2304 + ds_write_b32 v82, a54 offset:2560 + ds_write_b32 v82, a55 offset:2816 + ds_write_b32 v82, a56 offset:4096 + ds_write_b32 v82, a57 offset:4352 + ds_write_b32 v82, a58 offset:4608 + ds_write_b32 v82, a59 offset:4864 + ds_write_b32 v82, a60 offset:6144 + ds_write_b32 v82, a61 offset:6400 + ds_write_b32 v82, a62 offset:6656 + ds_write_b32 v82, a63 offset:6912 + ds_write_b32 v82, a64 offset:16384 + ds_write_b32 v82, a65 offset:16640 + ds_write_b32 v82, a66 offset:16896 + ds_write_b32 v82, a67 offset:17152 + ds_write_b32 v82, a68 offset:18432 + ds_write_b32 v82, a69 offset:18688 + ds_write_b32 v82, a70 offset:18944 + ds_write_b32 v82, a71 offset:19200 + ds_write_b32 v82, a72 offset:20480 + ds_write_b32 v82, a73 offset:20736 + ds_write_b32 v82, a74 offset:20992 + ds_write_b32 v82, a75 offset:21248 + ds_write_b32 v82, a76 offset:22528 + ds_write_b32 v82, a77 offset:22784 + ds_write_b32 v82, a78 offset:23040 + ds_write_b32 v82, a79 offset:23296 + ds_write_b32 v82, a80 offset:32768 + ds_write_b32 v82, a81 offset:33024 + ds_write_b32 v82, a82 offset:33280 + ds_write_b32 v82, a83 offset:33536 + ds_write_b32 v82, a84 offset:34816 + ds_write_b32 v82, a85 offset:35072 + ds_write_b32 v82, a86 offset:35328 + ds_write_b32 v82, a87 offset:35584 + ds_write_b32 v82, a88 offset:36864 + ds_write_b32 v82, a89 offset:37120 + ds_write_b32 v82, a90 offset:37376 + ds_write_b32 v82, a91 offset:37632 + ds_write_b32 v82, a92 offset:38912 + ds_write_b32 v82, a93 offset:39168 + ds_write_b32 v82, a94 offset:39424 + ds_write_b32 v82, a95 offset:39680 + ds_write_b32 v82, a96 offset:49152 + ds_write_b32 v82, a97 offset:49408 + ds_write_b32 v82, a98 offset:49664 + ds_write_b32 v82, a99 offset:49920 + ds_write_b32 v82, a100 offset:51200 + ds_write_b32 v82, a101 offset:51456 + ds_write_b32 v82, a102 offset:51712 + ds_write_b32 v82, a103 offset:51968 + ds_write_b32 v82, a104 offset:53248 + ds_write_b32 v82, a105 offset:53504 + ds_write_b32 v82, a106 offset:53760 + ds_write_b32 v82, a107 offset:54016 + ds_write_b32 v82, a108 offset:55296 + ds_write_b32 v82, a109 offset:55552 + ds_write_b32 v82, a110 offset:55808 + ds_write_b32 v82, a111 offset:56064 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v83 + ds_read_b128 v[22:25], v83 offset:256 + ds_read_b128 v[26:29], v83 offset:512 + ds_read_b128 v[30:33], v83 offset:768 + ds_read_b128 v[34:37], v83 offset:1024 + ds_read_b128 v[38:41], v83 offset:1280 + ds_read_b128 v[42:45], v83 offset:1536 + ds_read_b128 v[46:49], v83 offset:1792 + ds_read_b128 v[50:53], v83 offset:2048 + ds_read_b128 v[54:57], v83 offset:2304 + ds_read_b128 v[58:61], v83 offset:2560 + ds_read_b128 v[62:65], v83 offset:2816 + ds_read_b128 v[66:69], v83 offset:3072 + ds_read_b128 v[70:73], v83 offset:3328 + ds_read_b128 v[74:77], v83 offset:3584 + ds_read_b128 v[78:81], v83 offset:3840 + v_add_u32_e32 v1, 0x80, v0 + v_lshlrev_b32_e32 v84, 2, v1 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[18:21], v84, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 2, v1 + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[26:29], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[30:33], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[34:37], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[38:41], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[42:45], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[46:49], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[50:53], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[54:57], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[58:61], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[62:65], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[66:69], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[70:73], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 2, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[74:77], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[78:81], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b32 v82, a0 + ds_write_b32 v82, a1 offset:256 + ds_write_b32 v82, a2 offset:512 + ds_write_b32 v82, a3 offset:768 + ds_write_b32 v82, a4 offset:2048 + ds_write_b32 v82, a5 offset:2304 + ds_write_b32 v82, a6 offset:2560 + ds_write_b32 v82, a7 offset:2816 + ds_write_b32 v82, a8 offset:4096 + ds_write_b32 v82, a9 offset:4352 + ds_write_b32 v82, a10 offset:4608 + ds_write_b32 v82, a11 offset:4864 + ds_write_b32 v82, a12 offset:6144 + ds_write_b32 v82, a13 offset:6400 + ds_write_b32 v82, a14 offset:6656 + ds_write_b32 v82, a15 offset:6912 + ds_write_b32 v82, a16 offset:16384 + ds_write_b32 v82, a17 offset:16640 + ds_write_b32 v82, a18 offset:16896 + ds_write_b32 v82, a19 offset:17152 + ds_write_b32 v82, a20 offset:18432 + ds_write_b32 v82, a21 offset:18688 + ds_write_b32 v82, a22 offset:18944 + ds_write_b32 v82, a23 offset:19200 + ds_write_b32 v82, a24 offset:20480 + ds_write_b32 v82, a25 offset:20736 + ds_write_b32 v82, a26 offset:20992 + ds_write_b32 v82, a27 offset:21248 + ds_write_b32 v82, a28 offset:22528 + ds_write_b32 v82, a29 offset:22784 + ds_write_b32 v82, a30 offset:23040 + ds_write_b32 v82, a31 offset:23296 + ds_write_b32 v82, a32 offset:32768 + ds_write_b32 v82, a33 offset:33024 + ds_write_b32 v82, a34 offset:33280 + ds_write_b32 v82, a35 offset:33536 + ds_write_b32 v82, a36 offset:34816 + ds_write_b32 v82, a37 offset:35072 + ds_write_b32 v82, a38 offset:35328 + ds_write_b32 v82, a39 offset:35584 + ds_write_b32 v82, a40 offset:36864 + ds_write_b32 v82, a41 offset:37120 + ds_write_b32 v82, a42 offset:37376 + ds_write_b32 v82, a43 offset:37632 + ds_write_b32 v82, a44 offset:38912 + ds_write_b32 v82, a45 offset:39168 + ds_write_b32 v82, a46 offset:39424 + ds_write_b32 v82, a47 offset:39680 + ds_write2st64_b32 v82, v2, v3 offset0:192 offset1:193 + ds_write2st64_b32 v82, v4, v5 offset0:194 offset1:195 + ds_write2st64_b32 v82, v6, v7 offset0:200 offset1:201 + ds_write2st64_b32 v82, v8, v9 offset0:202 offset1:203 + ds_write2st64_b32 v82, v10, v11 offset0:208 offset1:209 + ds_write2st64_b32 v82, v12, v13 offset0:210 offset1:211 + ds_write2st64_b32 v82, v14, v15 offset0:216 offset1:217 + ds_write2st64_b32 v82, v16, v17 offset0:218 offset1:219 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[2:5], v83 + ds_read_b128 v[6:9], v83 offset:256 + ds_read_b128 v[10:13], v83 offset:512 + ds_read_b128 v[14:17], v83 offset:768 + ds_read_b128 v[18:21], v83 offset:1024 + ds_read_b128 v[22:25], v83 offset:1280 + ds_read_b128 v[26:29], v83 offset:1536 + ds_read_b128 v[30:33], v83 offset:1792 + ds_read_b128 v[34:37], v83 offset:2048 + ds_read_b128 v[38:41], v83 offset:2304 + ds_read_b128 v[42:45], v83 offset:2560 + ds_read_b128 v[46:49], v83 offset:2816 + ds_read_b128 v[50:53], v83 offset:3072 + ds_read_b128 v[54:57], v83 offset:3328 + ds_read_b128 v[58:61], v83 offset:3584 + ds_read_b128 v[62:65], v83 offset:3840 + v_add_u32_e32 v0, 0xc0, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(14) + buffer_store_dwordx4 v[2:5], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + buffer_store_dwordx4 v[6:9], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(13) + buffer_store_dwordx4 v[10:13], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(12) + buffer_store_dwordx4 v[14:17], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(11) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(10) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(9) + buffer_store_dwordx4 v[26:29], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(8) + buffer_store_dwordx4 v[30:33], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(7) + buffer_store_dwordx4 v[34:37], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(6) + buffer_store_dwordx4 v[38:41], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(5) + buffer_store_dwordx4 v[42:45], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(4) + buffer_store_dwordx4 v[46:49], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[50:53], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[54:57], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 2, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[58:61], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 2 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[62:65], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 65536 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 448 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 192 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end39: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end39-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 190 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 29 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIaaiS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorESF_SF_Li1EEEaNS_12element_wise11PassThroughESI_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIaaNS_5tupleIJEEEiiSP_SF_SI_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 28784 +; TotalNumSgprs: 35 +; NumVgprs: 190 +; NumAgprs: 256 +; TotalNumVgprs: 448 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 65536 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 55 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 448 +; AccumOffset: 192 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 47 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v6, 0 + global_load_ushort v1, v6, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v2, s3 + v_rcp_iflag_f32_e32 v2, v2 + s_nop 0 + v_mul_f32_e32 v2, 0x4f7ffffe, v2 + v_cvt_u32_f32_e32 v2, v2 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v3, s8, v2 + v_mul_hi_u32 v3, v2, v3 + v_add_u32_e32 v2, v2, v3 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v1, s2, v1 + v_add_u32_e32 v3, v1, v0 + v_xor_b32_e32 v0, s5, v3 + v_sub_u32_e32 v1, 0, v3 + v_ashrrev_i32_e32 v0, 31, v0 + v_max_i32_e32 v1, v3, v1 + v_mul_hi_u32 v2, v1, v2 + v_mul_lo_u32 v4, v2, s3 + v_add_u32_e32 v5, 1, v2 + v_sub_u32_e32 v1, v1, v4 + v_cmp_le_u32_e32 vcc, s3, v1 + s_nop 1 + v_cndmask_b32_e32 v2, v2, v5, vcc + v_subrev_u32_e32 v4, s3, v1 + v_cndmask_b32_e32 v1, v1, v4, vcc + v_add_u32_e32 v4, 1, v2 + v_cmp_le_u32_e32 vcc, s3, v1 + s_nop 1 + v_cndmask_b32_e32 v1, v2, v4, vcc + v_xor_b32_e32 v1, v1, v0 + v_sub_u32_e32 v1, v1, v0 + v_cmp_gt_i32_e32 vcc, s4, v1 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB40_10 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v4, v1, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v3, v4 + s_cbranch_scc1 .LBB40_9 +; %bb.2: ; %.lr.ph + v_mul_lo_u32 v2, v1, s7 + s_cmp_eq_u32 s6, 1 + s_cselect_b64 s[0:1], -1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lg_u32 s2, 1 + s_cselect_b64 s[4:5], -1, 0 + s_or_b64 s[0:1], s[0:1], s[4:5] + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB40_6 +; %bb.3: ; %vector.ph + s_and_b32 s4, s6, 0x7ffffffe + s_mov_b32 s0, 0 + v_mov_b32_e32 v5, 0 + v_mov_b32_e32 v6, 0 +.LBB40_4: ; %vector.body + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v8, s0, v2 + v_add_u32_e32 v10, s0, v0 + v_ashrrev_i32_e32 v9, 31, v8 + v_ashrrev_i32_e32 v11, 31, v10 + v_lshl_add_u64 v[8:9], s[8:9], 0, v[8:9] + v_lshl_add_u64 v[10:11], s[10:11], 0, v[10:11] + global_load_ushort v7, v[8:9], off + global_load_ushort v12, v[10:11], off + s_add_i32 s0, s0, 2 + s_cmp_lg_u32 s0, s4 + s_waitcnt vmcnt(1) + v_lshrrev_b16_e32 v8, 8, v7 + v_bfe_i32 v7, v7, 0, 8 + s_waitcnt vmcnt(0) + v_lshrrev_b16_e32 v9, 8, v12 + v_bfe_i32 v10, v12, 0, 8 + v_bfe_i32 v8, v8, 0, 8 + v_bfe_i32 v9, v9, 0, 8 + v_mad_i32_i24 v5, v10, v7, v5 + v_mad_i32_i24 v6, v9, v8, v6 + s_cbranch_scc1 .LBB40_4 +; %bb.5: ; %middle.block + v_add_u32_e32 v6, v5, v6 + s_cmp_lg_u32 s6, s4 + s_cselect_b64 s[0:1], -1, 0 + s_and_b64 vcc, exec, s[0:1] + s_cbranch_vccnz .LBB40_7 + s_branch .LBB40_9 +.LBB40_6: + s_mov_b32 s4, 0 + v_mov_b32_e32 v6, 0 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB40_9 +.LBB40_7: ; %scalar.ph.preheader + s_sub_i32 s0, s6, s4 + s_mul_i32 s1, s4, s2 + v_add_u32_e32 v3, s1, v3 + v_sub_u32_e32 v4, v3, v4 + v_ashrrev_i32_e32 v3, 31, v2 + s_add_u32 s4, s8, s4 + s_addc_u32 s5, s9, 0 + v_lshl_add_u64 v[2:3], s[4:5], 0, v[2:3] +.LBB40_8: ; %scalar.ph + ; =>This Inner Loop Header: Depth=1 + global_load_sbyte v7, v[2:3], off + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[8:9], s[10:11], 0, v[4:5] + global_load_sbyte v5, v[8:9], off + s_add_i32 s0, s0, -1 + v_lshl_add_u64 v[2:3], v[2:3], 0, 1 + v_add_u32_e32 v4, s2, v4 + s_cmp_eq_u32 s0, 0 + s_waitcnt vmcnt(0) + v_mad_i32_i24 v6, v5, v7, v6 + s_cbranch_scc0 .LBB40_8 +.LBB40_9: ; %._crit_edge + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[0:1], s[0:1], v1, s3, v[0:1] + v_ashrrev_i32_e32 v1, 31, v0 + v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] + global_store_dword v[0:1], v6, off +.LBB40_10: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 13 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 16 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end40: + .size _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii, .Lfunc_end40-_ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_vgpr, 13 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIaaiiNS_13tensor_layout4gemm8RowMajorES3_S3_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 648 +; TotalNumSgprs: 20 +; NumVgprs: 13 +; NumAgprs: 0 +; TotalNumVgprs: 13 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 13 +; AccumOffset: 16 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 3 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v119, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s12, s2, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s12, s2 + s_sub_i32 s21, s3, s14 + s_max_i32 s21, s21, 0 + s_mul_i32 s21, s13, s21 + s_add_i32 s21, s21, s2 + s_mul_i32 s2, s21, s7 + s_sub_i32 s6, s6, s21 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s12, s12, s13 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s12 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[2:3], s[2:3], 1 + s_add_u32 s8, s8, s2 + s_addc_u32 s9, s9, s3 + s_ashr_i32 s2, s21, 31 + s_add_u32 s12, s10, s21 + s_addc_u32 s13, s11, s2 + s_add_i32 s2, s6, -1 + s_mul_i32 s3, s7, s2 + s_add_i32 s4, s4, -1 + s_add_u32 s3, s4, s3 + s_add_u32 s21, s3, 1 + s_add_i32 s3, s5, -1 + s_mul_i32 s3, s20, s3 + s_ashr_i32 s10, s3, 31 + s_ashr_i32 s11, s2, 31 + s_add_u32 s2, s2, s3 + s_addc_u32 s3, s11, s10 + s_add_u32 s2, s2, 1 + s_addc_u32 s3, s3, 0 + s_lshr_b32 s10, s3, 31 + s_add_u32 s2, s2, s10 + s_addc_u32 s3, s3, 0 + s_ashr_i64 s[14:15], s[2:3], 1 + s_add_i32 s6, s6, 63 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v38, -1, 0 + s_cbranch_scc0 .LBB41_2 +; %bb.1: + v_readfirstlane_b32 s15, v119 + v_mbcnt_hi_u32_b32 v72, -1, v38 + v_and_b32_e32 v36, 31, v72 + s_lshr_b32 s22, s15, 2 + v_lshrrev_b32_e32 v37, 5, v72 + v_lshlrev_b32_e32 v39, 3, v37 + s_and_b32 s23, s22, 0x3ffffff0 + v_lshl_or_b32 v0, v36, 3, s18 + v_add_u32_e32 v1, s23, v39 + v_mad_u64_u32 v[0:1], s[10:11], v1, s7, v[0:1] + s_lshl_b32 s10, s21, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v8, 1, v0 + v_add_u32_e32 v9, s7, v0 + v_lshlrev_b32_e32 v10, 1, v9 + buffer_load_dwordx4 v[0:3], v8, s[8:11], 0 offen + buffer_load_dwordx4 v[4:7], v10, s[8:11], 0 offen + v_add_u32_e32 v8, s7, v9 + v_lshlrev_b32_e32 v16, 1, v8 + v_add_u32_e32 v17, s7, v8 + v_lshlrev_b32_e32 v18, 1, v17 + buffer_load_dwordx4 v[8:11], v16, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v18, s[8:11], 0 offen + v_add_u32_e32 v16, s7, v17 + v_lshlrev_b32_e32 v24, 1, v16 + v_add_u32_e32 v25, s7, v16 + v_lshlrev_b32_e32 v26, 1, v25 + buffer_load_dwordx4 v[16:19], v24, s[8:11], 0 offen + buffer_load_dwordx4 v[20:23], v26, s[8:11], 0 offen + v_add_u32_e32 v24, s7, v25 + v_lshlrev_b32_e32 v32, 1, v24 + v_add_lshl_u32 v33, v24, s7, 1 + buffer_load_dwordx4 v[24:27], v32, s[8:11], 0 offen + buffer_load_dwordx4 v[28:31], v33, s[8:11], 0 offen + s_mov_b32 s24, 0x1000504 + s_mov_b32 s25, 0x3020706 + v_and_b32_e32 v73, 7, v72 + s_and_b32 s10, s15, 0xffffffc0 + s_lshr_b32 s26, s15, 1 + v_lshlrev_b32_e32 v32, 3, v72 + s_mov_b32 s15, s11 + s_and_b32 s11, s22, 0x3fffffe0 + v_lshlrev_b32_e32 v33, 12, v37 + v_add_u32_e32 v68, s10, v72 + s_and_b32 s10, s26, 32 + v_and_or_b32 v102, v32, 8, v37 + v_or_b32_e32 v78, s11, v36 + v_lshl_or_b32 v32, v73, 8, v33 + v_add_u32_e32 v33, s19, v68 + v_or_b32_e32 v34, s10, v36 + v_lshrrev_b32_e32 v69, 3, v78 + v_mul_lo_u32 v33, v33, s20 + v_lshrrev_b32_e32 v103, 1, v34 + v_bfe_u32 v104, v34, 1, 4 + v_xor_b32_e32 v70, v73, v69 + v_xor_b32_e32 v105, v104, v102 + v_lshlrev_b32_e32 v106, 7, v103 + v_lshrrev_b32_e32 v34, 31, v33 + v_lshl_add_u32 v71, v70, 3, v32 + v_lshl_or_b32 v107, v105, 3, v106 + v_add_u32_e32 v32, v33, v34 + v_ashrrev_i32_e32 v44, 1, v32 + buffer_load_dwordx4 v[32:35], v44, s[12:15], 0 offen + buffer_load_dwordx4 v[40:43], v44, s[12:15], 16 offen + s_waitcnt vmcnt(8) + v_perm_b32 v44, v0, v4, s24 + v_perm_b32 v0, v0, v4, s25 + v_perm_b32 v4, v1, v5, s24 + v_perm_b32 v48, v1, v5, s25 + v_perm_b32 v52, v2, v6, s24 + v_perm_b32 v56, v2, v6, s25 + v_perm_b32 v60, v3, v7, s24 + v_perm_b32 v64, v3, v7, s25 + s_waitcnt vmcnt(6) + v_perm_b32 v45, v8, v12, s24 + v_perm_b32 v1, v8, v12, s25 + v_perm_b32 v5, v9, v13, s24 + v_perm_b32 v49, v9, v13, s25 + v_perm_b32 v53, v10, v14, s24 + v_perm_b32 v57, v10, v14, s25 + v_perm_b32 v61, v11, v15, s24 + v_perm_b32 v65, v11, v15, s25 + s_waitcnt vmcnt(4) + v_perm_b32 v46, v16, v20, s24 + v_perm_b32 v2, v16, v20, s25 + v_perm_b32 v6, v17, v21, s24 + v_perm_b32 v50, v17, v21, s25 + v_perm_b32 v54, v18, v22, s24 + v_perm_b32 v58, v18, v22, s25 + s_waitcnt vmcnt(2) + v_perm_b32 v47, v24, v28, s24 + v_perm_b32 v3, v24, v28, s25 + v_perm_b32 v7, v25, v29, s24 + v_perm_b32 v51, v25, v29, s25 + v_perm_b32 v55, v26, v30, s24 + v_perm_b32 v59, v26, v30, s25 + v_perm_b32 v62, v19, v23, s24 + v_perm_b32 v66, v19, v23, s25 + v_perm_b32 v63, v27, v31, s24 + v_perm_b32 v67, v27, v31, s25 + scratch_store_dword off, v72, off offset:4 ; 4-byte Folded Spill + v_lshrrev_b32_e32 v8, 2, v72 + v_and_b32_e32 v8, 24, v8 + v_add_u32_e32 v8, s23, v8 + v_lshrrev_b32_e32 v9, 2, v8 + v_and_b32_e32 v9, 24, v9 + v_xor_b32_e32 v10, v9, v36 + v_lshlrev_b32_e32 v11, 9, v8 + v_and_b32_e32 v11, 0x3000, v11 + v_lshlrev_b32_e32 v8, 6, v8 + v_and_b32_e32 v8, 0xfffff800, v8 + v_add_u32_e32 v8, v8, v11 + v_lshl_or_b32 v8, v10, 3, v8 + v_lshlrev_b32_e32 v11, 1, v8 + ds_write_b128 v11, v[44:47] + v_or_b32_e32 v12, 1, v9 + v_xor_b32_e32 v12, v12, v36 + v_sub_u32_e32 v10, v12, v10 + v_lshlrev_b32_e32 v13, 3, v10 + v_or_b32_e32 v14, 2, v9 + v_xor_b32_e32 v14, v14, v36 + v_sub_u32_e32 v12, v14, v12 + v_lshlrev_b32_e32 v15, 3, v12 + v_add3_u32 v8, v13, v8, v15 + v_lshl_add_u32 v10, v10, 4, v11 + ds_write_b128 v10, v[0:3] offset:512 + v_or_b32_e32 v0, 3, v9 + v_xor_b32_e32 v0, v0, v36 + v_sub_u32_e32 v1, v0, v14 + v_lshlrev_b32_e32 v2, 3, v1 + v_or_b32_e32 v3, 4, v9 + v_xor_b32_e32 v3, v3, v36 + v_sub_u32_e32 v0, v3, v0 + v_lshlrev_b32_e32 v11, 3, v0 + v_add3_u32 v2, v8, v2, v11 + v_lshlrev_b32_e32 v8, 4, v12 + s_movk_i32 s11, 0x200 + v_add3_u32 v8, v10, s11, v8 + ds_write_b128 v8, v[4:7] offset:512 + v_or_b32_e32 v4, 5, v9 + v_xor_b32_e32 v4, v4, v36 + v_sub_u32_e32 v3, v4, v3 + v_lshlrev_b32_e32 v5, 3, v3 + v_or_b32_e32 v6, 6, v9 + v_xor_b32_e32 v6, v6, v36 + v_sub_u32_e32 v4, v6, v4 + v_lshlrev_b32_e32 v7, 3, v4 + v_add3_u32 v2, v2, v5, v7 + v_lshlrev_b32_e32 v1, 4, v1 + v_add3_u32 v1, v8, s11, v1 + ds_write_b128 v1, v[48:51] offset:512 + v_or_b32_e32 v5, 7, v9 + v_xor_b32_e32 v5, v5, v36 + v_sub_u32_e32 v5, v5, v6 + v_lshlrev_b32_e32 v5, 4, v5 + v_lshl_add_u32 v2, v2, 1, v5 + v_lshlrev_b32_e32 v0, 4, v0 + v_add3_u32 v0, v1, s11, v0 + ds_write_b128 v0, v[52:55] offset:512 + v_lshlrev_b32_e32 v1, 4, v3 + v_add3_u32 v0, v0, s11, v1 + ds_write_b128 v0, v[56:59] offset:512 + v_lshlrev_b32_e32 v1, 4, v4 + v_add3_u32 v0, v0, s11, v1 + ds_write_b128 v0, v[60:63] offset:512 + ds_write_b128 v2, v[64:67] offset:3584 + v_lshrrev_b32_e32 v0, 31, v68 + v_add_u32_e32 v0, v68, v0 + v_ashrrev_i32_e32 v1, 1, v0 + v_and_b32_e32 v2, 0x1ffffffe, v0 + v_sub_u32_e32 v2, v68, v2 + v_lshlrev_b32_e32 v2, 3, v2 + v_ashrrev_i32_e32 v0, 31, v0 + v_lshrrev_b32_e32 v0, 28, v0 + v_add_u32_e32 v0, v1, v0 + v_and_b32_e32 v0, -16, v0 + v_sub_u32_e32 v0, v1, v0 + v_xor_b32_e32 v3, v2, v0 + v_lshlrev_b32_e32 v1, 7, v1 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + s_waitcnt vmcnt(2) + ds_write_b32 v3, v32 offset:32768 + v_or_b32_e32 v3, 1, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + ds_write_b32 v3, v33 offset:32768 + v_or_b32_e32 v3, 2, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + ds_write_b32 v3, v34 offset:32768 + v_or_b32_e32 v3, 3, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + ds_write_b32 v3, v35 offset:32768 + v_or_b32_e32 v3, 4, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + s_waitcnt vmcnt(1) + ds_write_b32 v3, v40 offset:32768 + v_or_b32_e32 v3, 5, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + ds_write_b32 v3, v41 offset:32768 + v_or_b32_e32 v3, 6, v2 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v3, v3, 3, v1 + v_ashrrev_i32_e32 v3, 1, v3 + ds_write_b32 v3, v42 offset:32768 + v_or_b32_e32 v2, 7, v2 + v_xor_b32_e32 v0, v2, v0 + v_lshl_add_u32 v0, v0, 3, v1 + v_ashrrev_i32_e32 v0, 1, v0 + ds_write_b32 v0, v43 offset:32768 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 1, v71 + v_add_u32_e32 v1, 16, v39 + v_lshrrev_b32_e32 v2, 5, v1 + v_bfe_u32 v1, v1, 3, 2 + scratch_store_dword off, v73, off offset:8 ; 4-byte Folded Spill + v_lshl_or_b32 v3, v2, 3, v73 + v_and_b32_e32 v4, 31, v3 + v_xor_b32_e32 v5, v4, v69 + v_sub_u32_e32 v6, v5, v70 + v_lshlrev_b32_e32 v7, 11, v2 + v_lshlrev_b32_e32 v6, 3, v6 + v_sub_u32_e32 v8, v1, v37 + v_lshl_add_u32 v7, v8, 12, v7 + v_add3_u32 v6, v7, v71, v6 + v_lshlrev_b32_e32 v8, 1, v6 + ds_read_b128 v[86:89], v0 + ds_read_b128 v[70:73], v8 + v_xor_b32_e32 v0, 1, v2 + v_sub_u32_e32 v1, v37, v1 + v_lshl_add_u32 v2, v0, 3, v3 + v_and_b32_e32 v3, 31, v2 + v_xor_b32_e32 v9, v3, v69 + v_sub_u32_e32 v5, v9, v5 + v_lshlrev_b32_e32 v0, 11, v0 + v_lshl_add_u32 v0, v1, 12, v0 + v_lshl_add_u32 v1, v5, 3, v0 + v_lshl_add_u32 v5, v1, 1, v8 + v_add_u32_e32 v8, 48, v39 + v_lshrrev_b32_e32 v10, 5, v8 + v_add_u32_e32 v11, -1, v10 + v_bfe_u32 v8, v8, 3, 2 + v_sub_u32_e32 v12, v8, v37 + v_lshl_add_u32 v2, v11, 3, v2 + v_ashrrev_i32_e32 v13, 31, v2 + v_lshrrev_b32_e32 v13, 27, v13 + v_add_u32_e32 v13, v2, v13 + v_and_b32_e32 v13, 0xffffffe0, v13 + v_sub_u32_e32 v13, v2, v13 + v_xor_b32_e32 v14, v13, v69 + v_sub_u32_e32 v9, v14, v9 + v_lshlrev_b32_e32 v11, 11, v11 + v_lshl_add_u32 v11, v12, 12, v11 + v_lshl_add_u32 v9, v9, 3, v11 + v_add3_u32 v1, v1, v6, v9 + v_lshl_add_u32 v6, v9, 1, v5 + ds_read_b128 v[58:61], v5 + ds_read_b128 v[46:49], v6 + v_add_u32_e32 v5, 64, v78 + v_lshrrev_b32_e32 v5, 3, v5 + v_sub_u32_e32 v8, v37, v8 + v_lshlrev_b32_e32 v9, 3, v10 + v_sub_u32_e32 v2, v2, v9 + v_ashrrev_i32_e32 v9, 31, v2 + v_lshrrev_b32_e32 v9, 27, v9 + v_add_u32_e32 v9, v2, v9 + v_and_b32_e32 v9, 0xffffffe0, v9 + v_sub_u32_e32 v2, v2, v9 + v_xor_b32_e32 v9, v2, v5 + v_sub_u32_e32 v12, v9, v14 + v_lshlrev_b32_e32 v8, 12, v8 + v_lshlrev_b32_e32 v10, 11, v10 + v_sub_u32_e32 v8, v8, v10 + v_lshl_add_u32 v10, v12, 3, v8 + v_lshl_add_u32 v6, v10, 1, v6 + v_xor_b32_e32 v12, v4, v5 + v_sub_u32_e32 v9, v12, v9 + v_lshl_add_u32 v9, v9, 3, v7 + v_add3_u32 v1, v10, v1, v9 + v_lshl_add_u32 v9, v9, 1, v6 + ds_read_b128 v[98:101], v6 + ds_read_b128 v[82:85], v9 + v_xor_b32_e32 v6, v3, v5 + v_sub_u32_e32 v10, v6, v12 + v_lshl_add_u32 v10, v10, 3, v0 + v_lshl_add_u32 v9, v10, 1, v9 + v_xor_b32_e32 v5, v13, v5 + v_sub_u32_e32 v6, v5, v6 + v_lshl_add_u32 v6, v6, 3, v11 + v_add3_u32 v1, v10, v1, v6 + v_lshl_add_u32 v6, v6, 1, v9 + ds_read_b128 v[66:69], v9 + ds_read_b128 v[50:53], v6 + v_add_u32_e32 v9, 0x80, v78 + v_lshrrev_b32_e32 v9, 3, v9 + v_xor_b32_e32 v10, v2, v9 + v_sub_u32_e32 v5, v10, v5 + v_lshl_add_u32 v5, v5, 3, v8 + v_lshl_add_u32 v6, v5, 1, v6 + v_xor_b32_e32 v12, v4, v9 + v_sub_u32_e32 v10, v12, v10 + v_lshl_add_u32 v10, v10, 3, v7 + v_add3_u32 v1, v5, v1, v10 + v_lshl_add_u32 v5, v10, 1, v6 + ds_read_b128 v[120:123], v6 + ds_read_b128 v[90:93], v5 + v_xor_b32_e32 v6, v3, v9 + v_sub_u32_e32 v10, v6, v12 + v_lshl_add_u32 v10, v10, 3, v0 + v_lshl_add_u32 v5, v10, 1, v5 + ds_read_b128 v[74:77], v5 + v_xor_b32_e32 v9, v13, v9 + v_sub_u32_e32 v6, v9, v6 + v_lshl_add_u32 v6, v6, 3, v11 + v_add3_u32 v1, v10, v1, v6 + v_lshl_add_u32 v5, v6, 1, v5 + ds_read_b128 v[54:57], v5 + v_add_u32_e32 v6, 0xc0, v78 + v_lshrrev_b32_e32 v6, 3, v6 + v_xor_b32_e32 v2, v2, v6 + v_sub_u32_e32 v9, v2, v9 + v_lshl_add_u32 v8, v9, 3, v8 + v_lshl_add_u32 v5, v8, 1, v5 + ds_read_b128 v[124:127], v5 + v_xor_b32_e32 v4, v4, v6 + v_sub_u32_e32 v2, v4, v2 + v_lshl_add_u32 v2, v2, 3, v7 + v_add3_u32 v1, v8, v1, v2 + v_lshl_add_u32 v2, v2, 1, v5 + ds_read_b128 v[94:97], v2 + v_xor_b32_e32 v3, v3, v6 + v_sub_u32_e32 v4, v3, v4 + v_lshl_add_u32 v0, v4, 3, v0 + v_lshl_add_u32 v2, v0, 1, v2 + ds_read_b128 v[78:81], v2 + v_xor_b32_e32 v2, v13, v6 + v_sub_u32_e32 v2, v2, v3 + v_lshlrev_b32_e32 v2, 4, v2 + v_lshlrev_b32_e32 v3, 1, v11 + v_add_lshl_u32 v0, v0, v1, 1 + v_add3_u32 v0, v2, v3, v0 + v_lshrrev_b32_e32 v1, 1, v107 + v_add_u32_e32 v2, 2, v102 + v_add_u32_e32 v3, -16, v103 + s_cmp_eq_u32 s10, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v3, v3, v103, vcc + v_xor_b32_e32 v4, v3, v2 + v_lshl_add_u32 v4, v4, 3, v106 + v_ashrrev_i32_e32 v4, 1, v4 + v_or_b32_e32 v5, 4, v102 + v_xor_b32_e32 v6, v3, v5 + v_lshl_add_u32 v6, v6, 3, v106 + v_ashrrev_i32_e32 v6, 1, v6 + ds_read_b128 v[62:65], v0 + ds_read_b32 v1, v1 offset:32768 + ds_read_b32 v4, v4 offset:32768 + ds_read_b32 v6, v6 offset:32768 + v_add_u32_e32 v0, 6, v102 + v_xor_b32_e32 v3, v3, v0 + v_lshl_add_u32 v7, v3, 3, v106 + v_ashrrev_i32_e32 v8, 1, v7 + v_sub_u32_e32 v3, v105, v3 + v_lshlrev_b32_e32 v3, 3, v3 + s_movk_i32 s10, 0x1000 + v_add3_u32 v3, v3, v7, s10 + v_ashrrev_i32_e32 v7, 1, v3 + v_xor_b32_e32 v2, v104, v2 + v_sub_u32_e32 v2, v2, v105 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v9, v3, v2 + v_ashrrev_i32_e32 v9, 1, v9 + v_xor_b32_e32 v5, v104, v5 + v_sub_u32_e32 v5, v5, v105 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v10, v3, v5 + v_ashrrev_i32_e32 v10, 1, v10 + v_xor_b32_e32 v0, v104, v0 + v_sub_u32_e32 v11, v0, v105 + v_lshlrev_b32_e32 v11, 3, v11 + v_add_u32_e32 v3, v3, v11 + v_ashrrev_i32_e32 v12, 1, v3 + v_sub_u32_e32 v0, v105, v0 + v_mov_b32_e32 v13, 0x1000 + v_lshl_add_u32 v0, v0, 3, v13 + v_add_u32_e32 v3, v3, v0 + v_ashrrev_i32_e32 v13, 1, v3 + v_add_u32_e32 v14, v3, v2 + v_ashrrev_i32_e32 v14, 1, v14 + v_add_u32_e32 v15, v3, v5 + v_ashrrev_i32_e32 v15, 1, v15 + ds_read_b32 v20, v8 offset:32768 + ds_read_b32 v7, v7 offset:32768 + ds_read_b32 v21, v9 offset:32768 + ds_read_b32 v30, v10 offset:32768 + ds_read_b32 v31, v12 offset:32768 + ds_read_b32 v32, v13 offset:32768 + ds_read_b32 v33, v14 offset:32768 + ds_read_b32 v45, v15 offset:32768 + v_add_u32_e32 v3, v3, v11 + v_ashrrev_i32_e32 v8, 1, v3 + v_add_u32_e32 v0, v3, v0 + v_lshrrev_b32_e32 v3, 31, v0 + v_add_u32_e32 v3, v0, v3 + v_ashrrev_i32_e32 v3, 1, v3 + v_add_u32_e32 v2, v0, v2 + v_lshrrev_b32_e32 v9, 31, v2 + v_add_u32_e32 v2, v2, v9 + v_ashrrev_i32_e32 v2, 1, v2 + v_add_u32_e32 v5, v0, v5 + v_lshrrev_b32_e32 v9, 31, v5 + v_add_u32_e32 v5, v5, v9 + v_ashrrev_i32_e32 v5, 1, v5 + v_add_u32_e32 v0, v0, v11 + v_lshrrev_b32_e32 v9, 31, v0 + v_add_u32_e32 v0, v0, v9 + v_ashrrev_i32_e32 v0, 1, v0 + ds_read_b32 v114, v8 offset:32768 + ds_read_b32 v116, v3 offset:32768 + ds_read_b32 v117, v2 offset:32768 + ds_read_b32 v118, v5 offset:32768 + ds_read_b32 v0, v0 offset:32768 + v_mov_b32_e32 v39, 0xf000f + v_mov_b32_e32 v40, 0x64006400 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v2, v1, v39, v40 + ;;#ASMEND + v_mov_b32_e32 v41, 0xf000f0 + ;;#ASMSTART + v_and_or_b32 v3, v1, v41, v40 + ;;#ASMEND + v_mov_b32_e32 v42, 0xe408e408 + ;;#ASMSTART + v_pk_add_f16 v26, v2, v42 + ;;#ASMEND + v_mov_b32_e32 v43, 0x2c002c00 + v_mov_b32_e32 v44, 0xd480d480 + ;;#ASMSTART + v_pk_fma_f16 v27, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v1 + ;;#ASMSTART + v_and_or_b32 v2, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v1, v43, v44 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v4, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v4, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v2, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v4 + ;;#ASMSTART + v_and_or_b32 v2, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(13) + ;;#ASMSTART + v_and_or_b32 v1, v6, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v6, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v2, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v6 + ;;#ASMSTART + v_and_or_b32 v2, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(12) + ;;#ASMSTART + v_and_or_b32 v1, v20, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v20, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v2, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v3, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v20 + ;;#ASMSTART + v_and_or_b32 v4, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v4, v4, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v5, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v1, v7, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v7, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v34, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v35, v6, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v7 + ;;#ASMSTART + v_and_or_b32 v6, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v36, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v37, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(10) + ;;#ASMSTART + v_and_or_b32 v1, v21, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v21, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v22, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v23, v6, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v21 + ;;#ASMSTART + v_and_or_b32 v6, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v24, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v25, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(9) + ;;#ASMSTART + v_and_or_b32 v1, v30, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v30, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v12, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v13, v6, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v30 + ;;#ASMSTART + v_and_or_b32 v6, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v14, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v15, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(8) + ;;#ASMSTART + v_and_or_b32 v1, v31, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v31, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v6, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v7, v7, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v31 + ;;#ASMSTART + v_and_or_b32 v20, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[0:15], v[86:87], v[26:27], 0 + ;;#ASMSTART + v_pk_add_f16 v20, v20, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v1, v32, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v32, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v102, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v103, v30, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v32 + v_mfma_f32_32x32x8_f16 a[0:15], v[88:89], v[28:29], a[0:15] + ;;#ASMSTART + v_and_or_b32 v30, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v104, v30, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v105, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(6) + ;;#ASMSTART + v_and_or_b32 v1, v33, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v33, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v106, v1, v42 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], v[86:87], v[34:35], 0 + ;;#ASMSTART + v_pk_fma_f16 v107, v30, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v33 + ;;#ASMSTART + v_and_or_b32 v30, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v108, v30, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v109, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(5) + ;;#ASMSTART + v_and_or_b32 v1, v45, v39, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], v[88:89], v[36:37], a[64:79] + ;;#ASMSTART + v_and_or_b32 v30, v45, v41, v40 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v110, v1, v42 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v111, v30, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v45 + ;;#ASMSTART + v_and_or_b32 v30, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v112, v30, v42 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], v[86:87], v[102:103], 0 + ;;#ASMSTART + v_pk_fma_f16 v113, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(4) + ;;#ASMSTART + v_and_or_b32 v1, v114, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v114, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v30, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v31, v31, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v114 + ;;#ASMSTART + v_and_or_b32 v32, v1, v39, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], v[88:89], v[104:105], a[144:159] + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v32, v32, v42 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v33, v1, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v1, v116, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v116, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v114, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v115, v45, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[86:87], v[114:115], 0 + v_ashrrev_i32_e32 v1, 8, v116 + ;;#ASMSTART + v_and_or_b32 v45, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v86, v45, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v87, v1, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[88:89], v[86:87], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[98:99], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[100:101], v[28:29], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[98:99], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[100:101], v[36:37], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[98:99], v[102:103], 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[100:101], v[104:105], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[98:99], v[114:115], 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[100:101], v[86:87], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[120:121], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[122:123], v[28:29], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[120:121], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[122:123], v[36:37], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[120:121], v[102:103], 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[122:123], v[104:105], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[120:121], v[114:115], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[122:123], v[86:87], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[124:125], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[126:127], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[124:125], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[126:127], v[36:37], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[124:125], v[102:103], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[126:127], v[104:105], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[124:125], v[114:115], 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[126:127], v[86:87], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[70:71], v[16:17], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[72:73], v[18:19], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[70:71], v[22:23], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[72:73], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[70:71], v[106:107], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[72:73], v[108:109], a[144:159] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v1, v117, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v27, v117, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v26, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v27, v27, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[70:71], v[26:27], a[208:223] + v_ashrrev_i32_e32 v1, 8, v117 + ;;#ASMSTART + v_and_or_b32 v28, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v28, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v1, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[72:73], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[82:83], v[16:17], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[84:85], v[18:19], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[82:83], v[22:23], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[84:85], v[24:25], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[82:83], v[106:107], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[84:85], v[108:109], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[82:83], v[26:27], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[84:85], v[28:29], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[90:91], v[16:17], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[92:93], v[18:19], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[90:91], v[22:23], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[92:93], v[24:25], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[90:91], v[106:107], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[92:93], v[108:109], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[90:91], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[92:93], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[94:95], v[16:17], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[96:97], v[18:19], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[94:95], v[22:23], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[96:97], v[24:25], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[94:95], v[106:107], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[96:97], v[108:109], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[94:95], v[26:27], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[96:97], v[28:29], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[58:59], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[60:61], v[10:11], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[58:59], v[12:13], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[60:61], v[14:15], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[58:59], v[110:111], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[60:61], v[112:113], a[144:159] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v1, v118, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v17, v118, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v17, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[58:59], v[16:17], a[208:223] + v_ashrrev_i32_e32 v1, 8, v118 + ;;#ASMSTART + v_and_or_b32 v18, v1, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v18, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v1, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[60:61], v[18:19], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[66:67], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[68:69], v[10:11], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[66:67], v[12:13], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[68:69], v[14:15], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[66:67], v[110:111], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[68:69], v[112:113], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[66:67], v[16:17], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[68:69], v[18:19], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[74:75], v[8:9], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[76:77], v[10:11], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[74:75], v[12:13], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[76:77], v[14:15], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[74:75], v[110:111], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[76:77], v[112:113], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[74:75], v[16:17], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[76:77], v[18:19], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[78:79], v[8:9], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[80:81], v[10:11], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[78:79], v[12:13], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[80:81], v[14:15], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[78:79], v[110:111], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[80:81], v[112:113], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[78:79], v[16:17], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[80:81], v[18:19], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[46:47], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[48:49], v[4:5], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[46:47], v[6:7], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[48:49], v[20:21], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[46:47], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[48:49], v[32:33], a[144:159] + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v1, v0, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v9, v0, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v9, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[46:47], v[8:9], a[208:223] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v1, v0, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v10, v0, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v0, v1, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v1, v10, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[48:49], v[0:1], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[50:51], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[52:53], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[50:51], v[6:7], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[52:53], v[20:21], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[50:51], v[30:31], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[52:53], v[32:33], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[50:51], v[8:9], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[52:53], v[0:1], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[54:55], v[2:3], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[56:57], v[4:5], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[54:55], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[56:57], v[20:21], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[54:55], v[30:31], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[56:57], v[32:33], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[54:55], v[8:9], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[56:57], v[0:1], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[62:63], v[2:3], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[64:65], v[4:5], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[62:63], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[64:65], v[20:21], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[62:63], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[64:65], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[62:63], v[8:9], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[64:65], v[0:1], a[240:255] + scratch_store_dword off, v119, off ; 4-byte Folded Spill + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB41_3 + s_branch .LBB41_11 +.LBB41_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr159 + ; implicit-def: $agpr79 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr0 + ; kill: killed $vgpr0 + ; implicit-def: $vgpr0 + ; kill: killed $vgpr0 + scratch_store_dword off, v119, off ; 4-byte Folded Spill + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB41_3: + scratch_load_dword v182, off, off ; 4-byte Folded Reload + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s15, v182 + v_mbcnt_hi_u32_b32 v183, -1, v38 + v_lshrrev_b32_e32 v3, 5, v183 + v_and_b32_e32 v103, 31, v183 + s_lshr_b32 s22, s15, 2 + s_and_b32 s23, s22, 0x3ffffff0 + v_lshl_or_b32 v0, v103, 3, s18 + v_lshlrev_b32_e32 v1, 3, v3 + v_add_u32_e32 v2, s23, v1 + v_mad_u64_u32 v[42:43], s[10:11], v2, s7, v[0:1] + s_lshl_b32 s10, s21, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v0, 1, v42 + v_add_u32_e32 v2, s7, v42 + v_lshlrev_b32_e32 v4, 1, v2 + buffer_load_dwordx4 v[12:15], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[16:19], v4, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v2 + v_lshlrev_b32_e32 v2, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + buffer_load_dwordx4 v[20:23], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[24:27], v4, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v2, 1, v0 + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v4, 1, v0 + buffer_load_dwordx4 v[28:31], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[32:35], v4, s[8:11], 0 offen + v_add_u32_e32 v0, s7, v0 + v_lshlrev_b32_e32 v2, 1, v0 + v_add_lshl_u32 v0, v0, s7, 1 + buffer_load_dwordx4 v[36:39], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[44:47], v0, s[8:11], 0 offen + s_mov_b32 s21, 0x1000504 + s_mov_b32 s24, 0x3020706 + v_and_b32_e32 v184, 7, v183 + s_and_b32 s25, s15, 0xffffffc0 + s_lshr_b32 s26, s15, 1 + v_lshlrev_b32_e32 v0, 3, v183 + s_mov_b32 s15, s11 + s_and_b32 s22, s22, 0x3fffffe0 + v_lshlrev_b32_e32 v2, 12, v3 + v_add_u32_e32 v11, s25, v183 + v_and_or_b32 v4, s26, 32, v103 + v_and_or_b32 v40, v0, 8, v3 + v_or_b32_e32 v7, s22, v103 + v_lshl_or_b32 v0, v184, 8, v2 + v_add_u32_e32 v2, s19, v11 + v_lshrrev_b32_e32 v5, 1, v4 + v_bfe_u32 v6, v4, 1, 4 + v_lshrrev_b32_e32 v8, 3, v7 + v_mul_lo_u32 v105, v2, s20 + v_xor_b32_e32 v4, v6, v40 + v_lshlrev_b32_e32 v5, 7, v5 + v_xor_b32_e32 v10, v184, v8 + v_lshl_or_b32 v2, v4, 3, v5 + v_lshrrev_b32_e32 v41, 31, v105 + v_lshl_add_u32 v9, v10, 3, v0 + v_add_u32_e32 v0, v105, v41 + v_ashrrev_i32_e32 v0, 1, v0 + buffer_load_dwordx4 v[48:51], v0, s[12:15], 0 offen + buffer_load_dwordx4 v[52:55], v0, s[12:15], 16 offen + s_waitcnt vmcnt(8) + v_perm_b32 v56, v12, v16, s21 + v_perm_b32 v12, v12, v16, s24 + v_perm_b32 v16, v13, v17, s21 + v_perm_b32 v60, v13, v17, s24 + v_perm_b32 v64, v14, v18, s21 + v_perm_b32 v68, v14, v18, s24 + v_perm_b32 v72, v15, v19, s21 + v_perm_b32 v76, v15, v19, s24 + s_waitcnt vmcnt(6) + v_perm_b32 v57, v20, v24, s21 + v_perm_b32 v13, v20, v24, s24 + v_perm_b32 v17, v21, v25, s21 + v_perm_b32 v61, v21, v25, s24 + v_perm_b32 v65, v22, v26, s21 + v_perm_b32 v69, v22, v26, s24 + v_perm_b32 v73, v23, v27, s21 + v_perm_b32 v77, v23, v27, s24 + s_waitcnt vmcnt(4) + v_perm_b32 v58, v28, v32, s21 + v_perm_b32 v14, v28, v32, s24 + v_perm_b32 v18, v29, v33, s21 + v_perm_b32 v62, v29, v33, s24 + v_perm_b32 v66, v30, v34, s21 + v_perm_b32 v70, v30, v34, s24 + v_perm_b32 v74, v31, v35, s21 + s_waitcnt vmcnt(2) + v_perm_b32 v59, v36, v44, s21 + v_perm_b32 v15, v36, v44, s24 + v_perm_b32 v19, v37, v45, s21 + v_perm_b32 v63, v37, v45, s24 + v_perm_b32 v67, v38, v46, s21 + v_perm_b32 v71, v38, v46, s24 + v_perm_b32 v78, v31, v35, s24 + v_perm_b32 v75, v39, v47, s21 + v_perm_b32 v79, v39, v47, s24 + v_lshrrev_b32_e32 v0, 2, v183 + v_and_b32_e32 v106, 24, v0 + v_add_u32_e32 v0, s23, v106 + v_lshrrev_b32_e32 v20, 2, v0 + v_and_b32_e32 v20, 24, v20 + v_xor_b32_e32 v21, v20, v103 + v_lshlrev_b32_e32 v22, 9, v0 + v_and_b32_e32 v22, 0x3000, v22 + v_lshlrev_b32_e32 v0, 6, v0 + v_and_b32_e32 v0, 0xfffff800, v0 + v_add_u32_e32 v0, v0, v22 + v_lshl_or_b32 v0, v21, 3, v0 + v_lshlrev_b32_e32 v22, 1, v0 + ds_write_b128 v22, v[56:59] + v_or_b32_e32 v23, 1, v20 + v_xor_b32_e32 v23, v23, v103 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v24, 3, v21 + v_or_b32_e32 v25, 2, v20 + v_xor_b32_e32 v25, v25, v103 + v_sub_u32_e32 v23, v25, v23 + v_lshlrev_b32_e32 v26, 3, v23 + v_add3_u32 v0, v24, v0, v26 + v_lshl_add_u32 v21, v21, 4, v22 + ds_write_b128 v21, v[12:15] offset:512 + v_or_b32_e32 v12, 3, v20 + v_xor_b32_e32 v12, v12, v103 + v_sub_u32_e32 v13, v12, v25 + v_lshlrev_b32_e32 v14, 3, v13 + v_or_b32_e32 v15, 4, v20 + v_xor_b32_e32 v15, v15, v103 + v_sub_u32_e32 v12, v15, v12 + v_lshlrev_b32_e32 v22, 3, v12 + v_add3_u32 v0, v0, v14, v22 + v_lshlrev_b32_e32 v14, 4, v23 + s_movk_i32 s20, 0x200 + v_add3_u32 v14, v21, s20, v14 + ds_write_b128 v14, v[16:19] offset:512 + v_or_b32_e32 v16, 5, v20 + v_xor_b32_e32 v16, v16, v103 + v_sub_u32_e32 v15, v16, v15 + v_lshlrev_b32_e32 v17, 3, v15 + v_or_b32_e32 v18, 6, v20 + v_xor_b32_e32 v18, v18, v103 + v_sub_u32_e32 v16, v18, v16 + v_lshlrev_b32_e32 v19, 3, v16 + v_add3_u32 v0, v0, v17, v19 + v_lshlrev_b32_e32 v13, 4, v13 + v_add3_u32 v13, v14, s20, v13 + ds_write_b128 v13, v[60:63] offset:512 + v_or_b32_e32 v14, 7, v20 + v_xor_b32_e32 v14, v14, v103 + v_sub_u32_e32 v14, v14, v18 + v_lshlrev_b32_e32 v14, 4, v14 + v_lshl_add_u32 v0, v0, 1, v14 + v_lshlrev_b32_e32 v12, 4, v12 + v_add3_u32 v12, v13, s20, v12 + ds_write_b128 v12, v[64:67] offset:512 + v_lshlrev_b32_e32 v13, 4, v15 + v_add3_u32 v12, v12, s20, v13 + ds_write_b128 v12, v[68:71] offset:512 + v_lshlrev_b32_e32 v13, 4, v16 + v_add3_u32 v12, v12, s20, v13 + ds_write_b128 v12, v[72:75] offset:512 + ds_write_b128 v0, v[76:79] offset:3584 + v_lshrrev_b32_e32 v0, 31, v11 + v_add_u32_e32 v0, v11, v0 + v_ashrrev_i32_e32 v12, 1, v0 + v_and_b32_e32 v13, 0x1ffffffe, v0 + v_sub_u32_e32 v11, v11, v13 + v_lshlrev_b32_e32 v11, 3, v11 + v_ashrrev_i32_e32 v0, 31, v0 + v_lshrrev_b32_e32 v0, 28, v0 + v_add_u32_e32 v0, v12, v0 + v_and_b32_e32 v0, -16, v0 + v_sub_u32_e32 v0, v12, v0 + v_xor_b32_e32 v13, v11, v0 + v_lshlrev_b32_e32 v12, 7, v12 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + s_waitcnt vmcnt(1) + ds_write_b32 v13, v48 offset:32768 + v_or_b32_e32 v13, 1, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + ds_write_b32 v13, v49 offset:32768 + v_or_b32_e32 v13, 2, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + ds_write_b32 v13, v50 offset:32768 + v_or_b32_e32 v13, 3, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + ds_write_b32 v13, v51 offset:32768 + v_or_b32_e32 v13, 4, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + s_waitcnt vmcnt(0) + ds_write_b32 v13, v52 offset:32768 + v_or_b32_e32 v13, 5, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + ds_write_b32 v13, v53 offset:32768 + v_or_b32_e32 v13, 6, v11 + v_xor_b32_e32 v13, v13, v0 + v_lshl_add_u32 v13, v13, 3, v12 + v_ashrrev_i32_e32 v13, 1, v13 + ds_write_b32 v13, v54 offset:32768 + v_or_b32_e32 v11, 7, v11 + v_xor_b32_e32 v0, v11, v0 + v_lshl_add_u32 v0, v0, 3, v12 + v_ashrrev_i32_e32 v0, 1, v0 + ds_write_b32 v0, v55 offset:32768 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v15, 16, v1 + v_add_u32_e32 v14, 48, v1 + v_add_u32_e32 v0, 64, v7 + v_lshrrev_b32_e32 v104, 1, v2 + v_add_u32_e32 v13, 2, v40 + v_add_u32_e32 v12, 4, v40 + v_add_u32_e32 v11, 6, v40 + s_cbranch_vccnz .LBB41_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit255.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_lshrrev_b32_e32 v1, 5, v15 + v_bfe_u32 v16, v15, 3, 2 + v_lshl_or_b32 v17, v1, 3, v184 + v_xor_b32_e32 v18, v17, v8 + v_sub_u32_e32 v19, v18, v10 + v_lshlrev_b32_e32 v20, 11, v1 + v_lshlrev_b32_e32 v19, 3, v19 + v_sub_u32_e32 v21, v16, v3 + v_lshl_or_b32 v20, v21, 12, v20 + v_add3_u32 v43, v20, v9, v19 + v_xor_b32_e32 v1, 1, v1 + v_sub_u32_e32 v16, v3, v16 + v_lshl_add_u32 v19, v1, 3, v17 + v_xor_b32_e32 v21, v19, v8 + v_sub_u32_e32 v18, v21, v18 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v18, 3, v18 + v_lshl_or_b32 v1, v16, 12, v1 + v_add3_u32 v73, v18, v1, v43 + v_lshrrev_b32_e32 v16, 5, v14 + v_add_u32_e32 v18, -1, v16 + v_bfe_u32 v22, v14, 3, 2 + v_sub_u32_e32 v23, v22, v3 + v_lshl_add_u32 v24, v18, 3, v19 + v_ashrrev_i32_e32 v25, 31, v24 + v_lshrrev_b32_e32 v25, 27, v25 + v_add_u32_e32 v25, v24, v25 + v_and_b32_e32 v25, 0xffffffe0, v25 + v_sub_u32_e32 v25, v24, v25 + v_xor_b32_e32 v26, v25, v8 + v_sub_u32_e32 v21, v26, v21 + v_lshlrev_b32_e32 v18, 11, v18 + v_lshlrev_b32_e32 v21, 3, v21 + v_lshl_add_u32 v18, v23, 12, v18 + v_add3_u32 v74, v21, v18, v73 + v_lshrrev_b32_e32 v21, 3, v0 + v_sub_u32_e32 v22, v3, v22 + v_lshlrev_b32_e32 v23, 3, v16 + v_sub_u32_e32 v23, v24, v23 + v_ashrrev_i32_e32 v24, 31, v23 + v_lshrrev_b32_e32 v24, 27, v24 + v_add_u32_e32 v24, v23, v24 + v_and_b32_e32 v24, 0xffffffe0, v24 + v_sub_u32_e32 v23, v23, v24 + v_xor_b32_e32 v24, v23, v21 + v_sub_u32_e32 v26, v24, v26 + v_lshlrev_b32_e32 v26, 3, v26 + v_lshlrev_b32_e32 v22, 12, v22 + v_lshlrev_b32_e32 v16, 11, v16 + v_sub_u32_e32 v16, v22, v16 + v_add3_u32 v75, v26, v16, v74 + v_xor_b32_e32 v22, v17, v21 + v_sub_u32_e32 v24, v22, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v76, v24, v20, v75 + v_xor_b32_e32 v24, v19, v21 + v_sub_u32_e32 v22, v24, v22 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v77, v22, v1, v76 + v_xor_b32_e32 v21, v25, v21 + v_sub_u32_e32 v22, v21, v24 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v78, v22, v18, v77 + v_add_u32_e32 v22, 0x80, v7 + v_lshrrev_b32_e32 v22, 3, v22 + v_xor_b32_e32 v24, v23, v22 + v_sub_u32_e32 v21, v24, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v79, v21, v16, v78 + v_xor_b32_e32 v21, v17, v22 + v_sub_u32_e32 v24, v21, v24 + v_lshlrev_b32_e32 v24, 3, v24 + v_add3_u32 v80, v24, v20, v79 + v_xor_b32_e32 v24, v19, v22 + v_sub_u32_e32 v21, v24, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v81, v21, v1, v80 + v_xor_b32_e32 v21, v25, v22 + v_sub_u32_e32 v22, v21, v24 + v_lshlrev_b32_e32 v22, 3, v22 + v_add3_u32 v82, v22, v18, v81 + v_add_u32_e32 v22, 0xc0, v7 + v_lshrrev_b32_e32 v22, 3, v22 + v_xor_b32_e32 v23, v23, v22 + v_sub_u32_e32 v21, v23, v21 + v_lshlrev_b32_e32 v21, 3, v21 + v_add3_u32 v83, v21, v16, v82 + v_xor_b32_e32 v16, v17, v22 + v_sub_u32_e32 v17, v16, v23 + v_lshlrev_b32_e32 v17, 3, v17 + v_add3_u32 v84, v17, v20, v83 + v_xor_b32_e32 v17, v19, v22 + v_sub_u32_e32 v16, v17, v16 + v_lshlrev_b32_e32 v16, 3, v16 + v_add3_u32 v85, v16, v1, v84 + v_xor_b32_e32 v1, v25, v22 + v_sub_u32_e32 v1, v1, v17 + v_lshlrev_b32_e32 v1, 3, v1 + v_add3_u32 v72, v1, v18, v85 + v_lshrrev_b32_e32 v2, 1, v2 + v_xor_b32_e32 v16, v6, v13 + v_lshlrev_b32_e32 v1, 3, v16 + v_add_u16_e32 v1, v1, v5 + v_lshrrev_b16_e32 v185, 1, v1 + v_xor_b32_e32 v17, v6, v12 + v_lshlrev_b32_e32 v1, 3, v17 + v_add_u16_e32 v1, v1, v5 + v_lshrrev_b16_e32 v186, 1, v1 + v_xor_b32_e32 v18, v6, v11 + v_lshlrev_b32_e32 v1, 3, v18 + v_add_u16_e32 v19, v1, v5 + v_lshrrev_b16_e32 v187, 1, v19 + v_sub_u32_e32 v19, v4, v18 + v_mov_b32_e32 v20, 0x1000 + v_lshl_add_u32 v19, v19, 3, v20 + v_add3_u32 v20, v1, v5, v19 + v_ashrrev_i32_e32 v1, 1, v20 + v_sub_u32_e32 v16, v16, v4 + v_lshlrev_b32_e32 v16, 3, v16 + v_add_u32_e32 v21, v20, v16 + v_ashrrev_i32_e32 v188, 1, v21 + v_sub_u32_e32 v17, v17, v4 + v_lshlrev_b32_e32 v17, 3, v17 + v_add_u32_e32 v21, v20, v17 + v_ashrrev_i32_e32 v189, 1, v21 + v_sub_u32_e32 v18, v18, v4 + v_lshlrev_b32_e32 v18, 3, v18 + v_add_u32_e32 v20, v20, v18 + v_ashrrev_i32_e32 v190, 1, v20 + v_add_u32_e32 v20, v20, v19 + v_ashrrev_i32_e32 v94, 1, v20 + v_add_u32_e32 v21, v20, v16 + v_ashrrev_i32_e32 v95, 1, v21 + v_add_u32_e32 v21, v20, v17 + v_ashrrev_i32_e32 v96, 1, v21 + v_add_u32_e32 v20, v20, v18 + v_ashrrev_i32_e32 v97, 1, v20 + v_add_u32_e32 v19, v20, v19 + v_lshrrev_b32_e32 v20, 31, v19 + v_add_u32_e32 v20, v19, v20 + v_ashrrev_i32_e32 v98, 1, v20 + v_add_u32_e32 v16, v19, v16 + v_lshrrev_b32_e32 v20, 31, v16 + v_add_u32_e32 v16, v16, v20 + v_ashrrev_i32_e32 v99, 1, v16 + v_add_u32_e32 v16, v19, v17 + v_lshrrev_b32_e32 v17, 31, v16 + v_add_u32_e32 v16, v16, v17 + v_ashrrev_i32_e32 v100, 1, v16 + v_add_u32_e32 v16, v19, v18 + v_lshrrev_b32_e32 v17, 31, v16 + v_add_u32_e32 v16, v16, v17 + v_ashrrev_i32_e32 v101, 1, v16 + s_mov_b64 s[2:3], 0 + s_branch .LBB41_6 +.LBB41_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr73 + ; implicit-def: $vgpr74 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr72 + ; implicit-def: $vgpr2 + ; implicit-def: $vgpr185 + ; implicit-def: $vgpr186 + ; implicit-def: $vgpr187 + ; implicit-def: $vgpr1 + ; implicit-def: $vgpr188 + ; implicit-def: $vgpr189 + ; implicit-def: $vgpr190 + ; implicit-def: $vgpr94 + ; implicit-def: $vgpr95 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 +.LBB41_6: ; %Flow61 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a144, 0 + v_lshlrev_b32_e32 v102, 1, v9 + s_cbranch_vccnz .LBB41_10 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i510.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s3, s6, 6 + s_lshl_b32 s2, s7, 6 + v_lshrrev_b32_e32 v1, 5, v15 + v_bfe_u32 v2, v15, 3, 2 + v_lshl_or_b32 v15, v1, 3, v184 + v_xor_b32_e32 v16, v15, v8 + v_sub_u32_e32 v10, v16, v10 + v_lshlrev_b32_e32 v17, 11, v1 + v_lshlrev_b32_e32 v10, 3, v10 + v_sub_u32_e32 v18, v2, v3 + v_lshl_or_b32 v17, v18, 12, v17 + v_add3_u32 v43, v17, v9, v10 + v_xor_b32_e32 v1, 1, v1 + v_sub_u32_e32 v2, v3, v2 + v_lshl_add_u32 v9, v1, 3, v15 + v_xor_b32_e32 v10, v9, v8 + v_sub_u32_e32 v16, v10, v16 + v_lshlrev_b32_e32 v1, 11, v1 + v_lshlrev_b32_e32 v16, 3, v16 + v_lshl_or_b32 v1, v2, 12, v1 + v_add3_u32 v73, v16, v1, v43 + v_lshrrev_b32_e32 v2, 5, v14 + v_add_u32_e32 v16, -1, v2 + v_bfe_u32 v14, v14, 3, 2 + v_sub_u32_e32 v18, v14, v3 + v_lshl_add_u32 v19, v16, 3, v9 + v_ashrrev_i32_e32 v20, 31, v19 + v_lshrrev_b32_e32 v20, 27, v20 + v_add_u32_e32 v20, v19, v20 + v_and_b32_e32 v20, 0xffffffe0, v20 + v_sub_u32_e32 v20, v19, v20 + v_xor_b32_e32 v8, v20, v8 + v_sub_u32_e32 v10, v8, v10 + v_lshlrev_b32_e32 v16, 11, v16 + v_lshlrev_b32_e32 v10, 3, v10 + v_lshl_add_u32 v16, v18, 12, v16 + v_add3_u32 v74, v10, v16, v73 + v_lshrrev_b32_e32 v0, 3, v0 + v_sub_u32_e32 v3, v3, v14 + v_lshlrev_b32_e32 v10, 3, v2 + v_sub_u32_e32 v10, v19, v10 + v_ashrrev_i32_e32 v14, 31, v10 + v_lshrrev_b32_e32 v14, 27, v14 + v_add_u32_e32 v14, v10, v14 + v_and_b32_e32 v14, 0xffffffe0, v14 + v_sub_u32_e32 v10, v10, v14 + v_xor_b32_e32 v14, v10, v0 + v_sub_u32_e32 v8, v14, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_lshlrev_b32_e32 v3, 12, v3 + v_lshlrev_b32_e32 v2, 11, v2 + v_sub_u32_e32 v2, v3, v2 + v_add3_u32 v75, v8, v2, v74 + v_xor_b32_e32 v3, v15, v0 + v_sub_u32_e32 v8, v3, v14 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v76, v8, v17, v75 + v_xor_b32_e32 v8, v9, v0 + v_sub_u32_e32 v3, v8, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v77, v3, v1, v76 + v_xor_b32_e32 v0, v20, v0 + v_sub_u32_e32 v3, v0, v8 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v78, v3, v16, v77 + v_add_u32_e32 v3, 0x80, v7 + v_lshrrev_b32_e32 v3, 3, v3 + v_xor_b32_e32 v8, v10, v3 + v_sub_u32_e32 v0, v8, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v79, v0, v2, v78 + v_xor_b32_e32 v0, v15, v3 + v_sub_u32_e32 v8, v0, v8 + v_lshlrev_b32_e32 v8, 3, v8 + v_add3_u32 v80, v8, v17, v79 + v_xor_b32_e32 v8, v9, v3 + v_sub_u32_e32 v0, v8, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v81, v0, v1, v80 + v_xor_b32_e32 v0, v20, v3 + v_sub_u32_e32 v3, v0, v8 + v_lshlrev_b32_e32 v3, 3, v3 + v_add3_u32 v82, v3, v16, v81 + v_add_u32_e32 v3, 0xc0, v7 + v_lshrrev_b32_e32 v3, 3, v3 + v_xor_b32_e32 v7, v10, v3 + v_sub_u32_e32 v0, v7, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v83, v0, v2, v82 + v_xor_b32_e32 v0, v15, v3 + v_sub_u32_e32 v2, v0, v7 + v_lshlrev_b32_e32 v2, 3, v2 + v_add3_u32 v84, v2, v17, v83 + v_xor_b32_e32 v2, v9, v3 + v_sub_u32_e32 v0, v2, v0 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v85, v0, v1, v84 + v_xor_b32_e32 v0, v20, v3 + v_sub_u32_e32 v0, v0, v2 + v_lshlrev_b32_e32 v0, 3, v0 + v_add3_u32 v72, v0, v16, v85 + v_xor_b32_e32 v0, v6, v13 + v_lshlrev_b32_e32 v1, 3, v0 + v_add_u16_e32 v1, v1, v5 + v_lshrrev_b16_e32 v185, 1, v1 + v_xor_b32_e32 v2, v6, v12 + v_lshlrev_b32_e32 v1, 3, v2 + v_add_u16_e32 v1, v1, v5 + v_lshrrev_b16_e32 v186, 1, v1 + v_xor_b32_e32 v3, v6, v11 + v_lshlrev_b32_e32 v1, 3, v3 + v_add_u16_e32 v6, v1, v5 + v_lshrrev_b16_e32 v187, 1, v6 + v_sub_u32_e32 v6, v4, v3 + v_mov_b32_e32 v7, 0x1000 + v_lshl_add_u32 v6, v6, 3, v7 + v_add3_u32 v5, v1, v5, v6 + v_ashrrev_i32_e32 v1, 1, v5 + v_sub_u32_e32 v0, v0, v4 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v7, v5, v0 + v_ashrrev_i32_e32 v188, 1, v7 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v7, v5, v2 + v_ashrrev_i32_e32 v189, 1, v7 + v_sub_u32_e32 v3, v3, v4 + v_lshlrev_b32_e32 v3, 3, v3 + v_add_u32_e32 v4, v5, v3 + v_ashrrev_i32_e32 v190, 1, v4 + v_add_u32_e32 v4, v4, v6 + v_ashrrev_i32_e32 v94, 1, v4 + v_add_u32_e32 v5, v4, v0 + v_ashrrev_i32_e32 v95, 1, v5 + v_add_u32_e32 v5, v4, v2 + v_ashrrev_i32_e32 v96, 1, v5 + v_add_u32_e32 v4, v4, v3 + v_ashrrev_i32_e32 v97, 1, v4 + v_add_u32_e32 v4, v4, v6 + v_lshrrev_b32_e32 v5, 31, v4 + v_add_u32_e32 v5, v4, v5 + v_ashrrev_i32_e32 v98, 1, v5 + v_add_u32_e32 v0, v4, v0 + v_lshrrev_b32_e32 v5, 31, v0 + v_add_u32_e32 v0, v0, v5 + v_ashrrev_i32_e32 v99, 1, v0 + v_add_u32_e32 v0, v4, v2 + v_lshrrev_b32_e32 v2, 31, v0 + v_add_u32_e32 v0, v0, v2 + v_ashrrev_i32_e32 v100, 1, v0 + v_add_u32_e32 v0, v4, v3 + v_lshrrev_b32_e32 v2, 31, v0 + v_add_u32_e32 v0, v0, v2 + v_ashrrev_i32_e32 v101, 1, v0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a144, 0 + v_mov_b32_e32 v107, 0xf000f + v_mov_b32_e32 v108, 0x64006400 + v_mov_b32_e32 v109, 0xf000f0 + v_mov_b32_e32 v110, 0xe408e408 + v_mov_b32_e32 v111, 0x2c002c00 + v_mov_b32_e32 v112, 0xd480d480 + s_mov_b32 s6, 0x1000504 + s_mov_b32 s20, 0x3020706 + s_movk_i32 s21, 0x200 +.LBB41_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i510.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v105, 64, v105 + v_add_u32_e32 v42, s2, v42 + v_lshlrev_b32_e32 v0, 1, v42 + v_add_u32_e32 v2, s7, v42 + v_lshrrev_b32_e32 v3, 31, v105 + v_lshlrev_b32_e32 v4, 1, v2 + v_add_u32_e32 v2, s7, v2 + v_add_u32_e32 v3, v105, v3 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[34:37], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v2 + v_add_u32_e32 v2, s7, v2 + v_ashrrev_i32_e32 v3, 1, v3 + v_lshlrev_b32_e32 v10, 1, v2 + v_add_u32_e32 v11, s7, v2 + buffer_load_dwordx4 v[6:9], v3, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 16 offen + s_nop 0 + buffer_load_dwordx4 v[30:33], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[38:41], v10, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v11 + v_add_u32_e32 v10, s7, v11 + v_lshlrev_b32_e32 v11, 1, v10 + v_add_u32_e32 v10, s7, v10 + buffer_load_dwordx4 v[18:21], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[22:25], v11, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v10 + v_add_lshl_u32 v14, v10, s7, 1 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[14:17], v14, s[8:11], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 1, v43 + ds_read_b128 v[148:151], v0 + v_lshlrev_b32_e32 v0, 1, v73 + ds_read_b128 v[144:147], v0 + v_lshlrev_b32_e32 v0, 1, v74 + ds_read_b128 v[116:119], v0 + v_lshlrev_b32_e32 v0, 1, v75 + ds_read_b128 v[164:167], v0 + v_lshlrev_b32_e32 v0, 1, v76 + ds_read_b128 v[152:155], v0 + v_lshlrev_b32_e32 v0, 1, v77 + ds_read_b128 v[140:143], v0 + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[120:123], v0 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[168:171], v0 + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[156:159], v0 + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[132:135], v0 + v_lshlrev_b32_e32 v0, 1, v82 + ds_read_b128 v[124:127], v0 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[172:175], v0 + v_lshlrev_b32_e32 v0, 1, v84 + ds_read_b128 v[160:163], v0 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[136:139], v0 + ds_read_b128 v[176:179], v102 + v_lshlrev_b32_e32 v0, 1, v72 + ds_read_b128 v[128:131], v0 + ds_read_b32 v46, v104 offset:32768 + ds_read_b32 v47, v185 offset:32768 + ds_read_b32 v48, v186 offset:32768 + ds_read_b32 v49, v187 offset:32768 + ds_read_b32 v60, v1 offset:32768 + ds_read_b32 v61, v188 offset:32768 + ds_read_b32 v62, v189 offset:32768 + ds_read_b32 v69, v190 offset:32768 + ds_read_b32 v90, v94 offset:32768 + ds_read_b32 v68, v95 offset:32768 + ds_read_b32 v51, v96 offset:32768 + ds_read_b32 v50, v97 offset:32768 + ds_read_b32 v115, v98 offset:32768 + ds_read_b32 v114, v99 offset:32768 + ds_read_b32 v0, v100 offset:32768 + ds_read_b32 v113, v101 offset:32768 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v44, v46, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v46, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v44, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v45, v45, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[144:159], v[176:177], v[44:45], a[144:159] + v_ashrrev_i32_e32 v46, 8, v46 + v_ashrrev_i32_e32 v52, 8, v47 + s_waitcnt lgkmcnt(13) + v_ashrrev_i32_e32 v53, 8, v48 + s_waitcnt lgkmcnt(12) + v_ashrrev_i32_e32 v63, 8, v49 + v_mfma_f32_32x32x8_f16 a[160:175], v[164:165], v[44:45], a[160:175] + ;;#ASMSTART + v_and_or_b32 v54, v46, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v46, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v54, v54, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v55, v46, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v47, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v47, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v46, v46, v110 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[168:169], v[44:45], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v56, v52, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v52, v52, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v64, v56, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v65, v52, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v52, v48, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v48, v48, v109, v108 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[172:173], v[44:45], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v58, v52, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v59, v48, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v53, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v53, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v56, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v57, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v49, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v49, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v52, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v53, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v63, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v63, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v49, v45, v111, v112 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v44, v60, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v60, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v44, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v45, v45, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[0:15], v[176:177], v[44:45], a[0:15] + v_mfma_f32_32x32x8_f16 a[208:223], v[164:165], v[44:45], a[208:223] + v_mfma_f32_32x32x8_f16 a[48:63], v[168:169], v[44:45], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[172:173], v[44:45], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[178:179], v[54:55], a[144:159] + v_ashrrev_i32_e32 v44, 8, v60 + s_waitcnt lgkmcnt(10) + v_ashrrev_i32_e32 v45, 8, v61 + s_waitcnt lgkmcnt(9) + v_ashrrev_i32_e32 v60, 8, v62 + s_waitcnt lgkmcnt(8) + v_ashrrev_i32_e32 v88, 8, v69 + v_mfma_f32_32x32x8_f16 a[160:175], v[166:167], v[54:55], a[160:175] + ;;#ASMSTART + v_and_or_b32 v63, v44, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v44, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v86, v63, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v87, v44, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v61, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v61, v61, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v70, v44, v110 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[170:171], v[54:55], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v71, v61, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v45, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v45, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v66, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v67, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v62, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v62, v109, v108 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[174:175], v[54:55], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v62, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v63, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v60, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v60, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v60, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v61, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v69, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v69, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v54, v44, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v55, v45, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v88, v107, v108 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[0:15], v[178:179], v[86:87], a[0:15] + ;;#ASMSTART + v_and_or_b32 v45, v88, v109, v108 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v44, v44, v110 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v45, v45, v111, v112 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v69, v90, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v89, v90, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v88, v69, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v89, v89, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[176:177], v[88:89], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[166:167], v[86:87], a[208:223] + v_mfma_f32_32x32x8_f16 a[16:31], v[164:165], v[88:89], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[170:171], v[86:87], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[168:169], v[88:89], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[174:175], v[86:87], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[172:173], v[88:89], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[148:149], v[46:47], a[144:159] + v_ashrrev_i32_e32 v69, 8, v90 + s_waitcnt lgkmcnt(6) + v_ashrrev_i32_e32 v90, 8, v68 + s_waitcnt lgkmcnt(5) + v_ashrrev_i32_e32 v180, 8, v51 + s_waitcnt lgkmcnt(4) + v_ashrrev_i32_e32 v181, 8, v50 + v_mfma_f32_32x32x8_f16 a[160:175], v[152:153], v[46:47], a[160:175] + ;;#ASMSTART + v_and_or_b32 v86, v69, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v69, v69, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v86, v86, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v87, v69, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v69, v68, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v68, v68, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v88, v69, v110 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[156:157], v[46:47], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v89, v68, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v68, v90, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v69, v90, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v90, v68, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v91, v69, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v68, v51, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v51, v51, v109, v108 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[160:161], v[46:47], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v92, v68, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v93, v51, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v180, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v180, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v68, v46, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v69, v47, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v50, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v50, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v46, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v47, v111, v112 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v181, v107, v108 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[224:239], v[178:179], v[86:87], a[224:239] + ;;#ASMSTART + v_and_or_b32 v47, v181, v109, v108 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v46, v46, v110 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v111, v112 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v180, v115, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v181, v115, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v180, v180, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v181, v181, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[176:177], v[180:181], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[166:167], v[86:87], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[164:165], v[180:181], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[170:171], v[86:87], a[64:79] + v_mfma_f32_32x32x8_f16 a[80:95], v[168:169], v[180:181], a[80:95] + v_mfma_f32_32x32x8_f16 a[112:127], v[174:175], v[86:87], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[172:173], v[180:181], a[128:143] + v_mfma_f32_32x32x8_f16 a[0:15], v[148:149], v[70:71], a[0:15] + v_mfma_f32_32x32x8_f16 a[208:223], v[152:153], v[70:71], a[208:223] + v_mfma_f32_32x32x8_f16 a[48:63], v[156:157], v[70:71], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[160:161], v[70:71], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[150:151], v[64:65], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[154:155], v[64:65], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[158:159], v[64:65], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[162:163], v[64:65], a[192:207] + v_ashrrev_i32_e32 v64, 8, v115 + ;;#ASMSTART + v_and_or_b32 v65, v64, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v70, v64, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v64, v65, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v65, v70, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[178:179], v[64:65], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[166:167], v[64:65], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[170:171], v[64:65], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[174:175], v[64:65], a[128:143] + v_mfma_f32_32x32x8_f16 a[0:15], v[150:151], v[66:67], a[0:15] + v_mfma_f32_32x32x8_f16 a[224:239], v[148:149], v[88:89], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[154:155], v[66:67], a[208:223] + v_mfma_f32_32x32x8_f16 a[16:31], v[152:153], v[88:89], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[158:159], v[66:67], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[156:157], v[88:89], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[162:163], v[66:67], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[160:161], v[88:89], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[144:145], v[58:59], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[140:141], v[58:59], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[132:133], v[58:59], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[136:137], v[58:59], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[150:151], v[90:91], a[224:239] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v58, v114, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v59, v114, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v58, v58, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v59, v59, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[148:149], v[58:59], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[154:155], v[90:91], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[152:153], v[58:59], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[158:159], v[90:91], a[64:79] + v_mfma_f32_32x32x8_f16 a[80:95], v[156:157], v[58:59], a[80:95] + v_mfma_f32_32x32x8_f16 a[112:127], v[162:163], v[90:91], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[160:161], v[58:59], a[128:143] + v_mfma_f32_32x32x8_f16 a[0:15], v[144:145], v[62:63], a[0:15] + v_mfma_f32_32x32x8_f16 a[208:223], v[140:141], v[62:63], a[208:223] + v_mfma_f32_32x32x8_f16 a[48:63], v[132:133], v[62:63], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[136:137], v[62:63], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[146:147], v[56:57], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[142:143], v[56:57], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[134:135], v[56:57], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[138:139], v[56:57], a[192:207] + v_ashrrev_i32_e32 v56, 8, v114 + ;;#ASMSTART + v_and_or_b32 v57, v56, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v58, v56, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v56, v57, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v57, v58, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[150:151], v[56:57], a[240:255] + v_mfma_f32_32x32x8_f16 a[32:47], v[154:155], v[56:57], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[158:159], v[56:57], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[162:163], v[56:57], a[128:143] + v_mfma_f32_32x32x8_f16 a[0:15], v[146:147], v[60:61], a[0:15] + v_mfma_f32_32x32x8_f16 a[224:239], v[144:145], v[92:93], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[60:61], a[208:223] + v_mfma_f32_32x32x8_f16 a[16:31], v[140:141], v[92:93], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[134:135], v[60:61], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[132:133], v[92:93], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[138:139], v[60:61], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[136:137], v[92:93], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[116:117], v[52:53], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[120:121], v[52:53], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[124:125], v[52:53], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[128:129], v[52:53], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[146:147], v[68:69], a[224:239] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v52, v0, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v53, v0, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v52, v52, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v53, v53, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[144:145], v[52:53], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[142:143], v[68:69], a[16:31] + v_mfma_f32_32x32x8_f16 a[32:47], v[140:141], v[52:53], a[32:47] + v_mfma_f32_32x32x8_f16 a[64:79], v[134:135], v[68:69], a[64:79] + v_mfma_f32_32x32x8_f16 a[80:95], v[132:133], v[52:53], a[80:95] + v_mfma_f32_32x32x8_f16 a[112:127], v[138:139], v[68:69], a[112:127] + v_mfma_f32_32x32x8_f16 a[128:143], v[136:137], v[52:53], a[128:143] + v_mfma_f32_32x32x8_f16 a[0:15], v[116:117], v[54:55], a[0:15] + v_mfma_f32_32x32x8_f16 a[208:223], v[120:121], v[54:55], a[208:223] + v_mfma_f32_32x32x8_f16 a[48:63], v[124:125], v[54:55], a[48:63] + v_mfma_f32_32x32x8_f16 a[96:111], v[128:129], v[54:55], a[96:111] + v_mfma_f32_32x32x8_f16 a[144:159], v[118:119], v[48:49], a[144:159] + v_mfma_f32_32x32x8_f16 a[160:175], v[122:123], v[48:49], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[126:127], v[48:49], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[130:131], v[48:49], a[192:207] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v48, v0, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v0, v0, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v48, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v49, v0, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[146:147], v[48:49], a[240:255] + s_add_i32 s22, s3, -1 + v_readfirstlane_b32 s23, v182 + s_lshr_b32 s24, s23, 2 + v_mfma_f32_32x32x8_f16 a[32:47], v[142:143], v[48:49], a[32:47] + s_andn2_b32 s23, s23, 63 + s_and_b32 s24, s24, 0x3ffffff0 + v_add_u32_e32 v0, s23, v183 + v_add_u32_e32 v52, s24, v106 + v_lshrrev_b32_e32 v53, 31, v0 + s_cmp_gt_u32 s3, 2 + s_mov_b32 s3, s22 + v_mfma_f32_32x32x8_f16 a[80:95], v[134:135], v[48:49], a[80:95] + v_lshrrev_b32_e32 v54, 2, v52 + v_lshlrev_b32_e32 v55, 9, v52 + v_lshlrev_b32_e32 v52, 6, v52 + v_add_u32_e32 v53, v0, v53 + v_and_b32_e32 v54, 24, v54 + v_and_b32_e32 v55, 0x3000, v55 + v_and_b32_e32 v52, 0xfffff800, v52 + v_mfma_f32_32x32x8_f16 a[128:143], v[138:139], v[48:49], a[128:143] + v_ashrrev_i32_e32 v48, 1, v53 + v_and_b32_e32 v49, 0x1ffffffe, v53 + v_ashrrev_i32_e32 v53, 31, v53 + v_xor_b32_e32 v56, v54, v103 + v_add_u32_e32 v52, v52, v55 + v_or_b32_e32 v55, 1, v54 + v_or_b32_e32 v57, 2, v54 + v_mfma_f32_32x32x8_f16 a[0:15], v[118:119], v[44:45], a[0:15] + v_or_b32_e32 v58, 3, v54 + v_or_b32_e32 v59, 4, v54 + v_or_b32_e32 v60, 5, v54 + v_or_b32_e32 v61, 6, v54 + v_or_b32_e32 v54, 7, v54 + v_sub_u32_e32 v0, v0, v49 + v_lshrrev_b32_e32 v49, 28, v53 + v_mfma_f32_32x32x8_f16 a[224:239], v[116:117], v[50:51], a[224:239] + v_lshlrev_b32_e32 v53, 7, v48 + v_lshl_or_b32 v52, v56, 3, v52 + v_xor_b32_e32 v55, v55, v103 + v_xor_b32_e32 v57, v57, v103 + v_xor_b32_e32 v58, v58, v103 + v_xor_b32_e32 v59, v59, v103 + v_xor_b32_e32 v60, v60, v103 + v_mfma_f32_32x32x8_f16 a[208:223], v[122:123], v[44:45], a[208:223] + v_xor_b32_e32 v61, v61, v103 + v_xor_b32_e32 v54, v54, v103 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v49, v48, v49 + v_lshlrev_b32_e32 v70, 1, v52 + v_sub_u32_e32 v56, v55, v56 + v_sub_u32_e32 v55, v57, v55 + v_mfma_f32_32x32x8_f16 a[16:31], v[120:121], v[50:51], a[16:31] + v_sub_u32_e32 v57, v58, v57 + v_sub_u32_e32 v58, v59, v58 + v_sub_u32_e32 v59, v60, v59 + v_sub_u32_e32 v60, v61, v60 + v_sub_u32_e32 v54, v54, v61 + v_and_b32_e32 v49, -16, v49 + v_or_b32_e32 v61, 1, v0 + v_mfma_f32_32x32x8_f16 a[48:63], v[126:127], v[44:45], a[48:63] + v_or_b32_e32 v62, 2, v0 + v_or_b32_e32 v63, 3, v0 + v_or_b32_e32 v64, 4, v0 + v_or_b32_e32 v65, 5, v0 + v_or_b32_e32 v66, 6, v0 + v_or_b32_e32 v67, 7, v0 + v_lshlrev_b32_e32 v68, 3, v56 + v_mfma_f32_32x32x8_f16 a[64:79], v[124:125], v[50:51], a[64:79] + v_lshlrev_b32_e32 v69, 3, v55 + v_lshl_add_u32 v71, v56, 4, v70 + v_lshlrev_b32_e32 v56, 3, v57 + v_lshlrev_b32_e32 v86, 3, v58 + v_lshlrev_b32_e32 v55, 4, v55 + v_lshlrev_b32_e32 v87, 3, v59 + v_lshlrev_b32_e32 v88, 3, v60 + v_mfma_f32_32x32x8_f16 a[96:111], v[130:131], v[44:45], a[96:111] + v_lshlrev_b32_e32 v44, 4, v57 + v_lshlrev_b32_e32 v45, 4, v54 + v_lshlrev_b32_e32 v54, 4, v58 + v_lshlrev_b32_e32 v57, 4, v59 + v_lshlrev_b32_e32 v58, 4, v60 + v_sub_u32_e32 v48, v48, v49 + v_add3_u32 v49, v68, v52, v69 + v_mfma_f32_32x32x8_f16 a[112:127], v[128:129], v[50:51], a[112:127] + v_add3_u32 v89, v71, s21, v55 + v_xor_b32_e32 v0, v0, v48 + v_xor_b32_e32 v52, v61, v48 + v_xor_b32_e32 v55, v62, v48 + v_xor_b32_e32 v59, v63, v48 + v_xor_b32_e32 v60, v64, v48 + v_xor_b32_e32 v61, v65, v48 + v_mfma_f32_32x32x8_f16 a[224:239], v[118:119], v[46:47], a[224:239] + v_xor_b32_e32 v62, v66, v48 + v_xor_b32_e32 v48, v67, v48 + v_add3_u32 v49, v49, v56, v86 + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v50, v113, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v51, v113, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v50, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v51, v111, v112 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[116:117], v[50:51], a[240:255] + v_add3_u32 v86, v89, s21, v44 + v_lshl_add_u32 v0, v0, 3, v53 + v_lshl_add_u32 v44, v52, 3, v53 + v_lshl_add_u32 v52, v55, 3, v53 + v_lshl_add_u32 v55, v59, 3, v53 + v_lshl_add_u32 v56, v60, 3, v53 + v_lshl_add_u32 v59, v61, 3, v53 + v_mfma_f32_32x32x8_f16 a[16:31], v[122:123], v[46:47], a[16:31] + v_lshl_add_u32 v60, v62, 3, v53 + v_lshl_add_u32 v48, v48, 3, v53 + v_add3_u32 v49, v49, v87, v88 + v_add3_u32 v87, v86, s21, v54 + v_ashrrev_i32_e32 v0, 1, v0 + v_ashrrev_i32_e32 v88, 1, v44 + v_ashrrev_i32_e32 v90, 1, v52 + v_mfma_f32_32x32x8_f16 a[32:47], v[120:121], v[50:51], a[32:47] + v_ashrrev_i32_e32 v91, 1, v55 + v_ashrrev_i32_e32 v92, 1, v56 + v_ashrrev_i32_e32 v93, 1, v59 + v_ashrrev_i32_e32 v114, 1, v60 + v_ashrrev_i32_e32 v115, 1, v48 + v_ashrrev_i32_e32 v44, 8, v113 + v_lshl_add_u32 v113, v49, 1, v45 + v_mfma_f32_32x32x8_f16 a[64:79], v[126:127], v[46:47], a[64:79] + v_add3_u32 v116, v87, s21, v57 + v_add3_u32 v117, v116, s21, v58 + ;;#ASMSTART + v_and_or_b32 v45, v44, v107, v108 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v44, v44, v109, v108 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v68, v45, v110 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v69, v44, v111, v112 + ;;#ASMEND + s_waitcnt lgkmcnt(0) + v_mfma_f32_32x32x8_f16 a[80:95], v[124:125], v[50:51], a[80:95] + s_barrier + s_waitcnt vmcnt(8) + v_perm_b32 v44, v26, v34, s6 + v_perm_b32 v26, v26, v34, s20 + v_perm_b32 v34, v27, v35, s6 + v_perm_b32 v48, v27, v35, s20 + v_perm_b32 v52, v28, v36, s6 + v_perm_b32 v56, v28, v36, s20 + v_mfma_f32_32x32x8_f16 a[112:127], v[130:131], v[46:47], a[112:127] + v_perm_b32 v60, v29, v37, s6 + v_perm_b32 v64, v29, v37, s20 + s_waitcnt vmcnt(4) + v_perm_b32 v45, v30, v38, s6 + v_perm_b32 v27, v30, v38, s20 + v_perm_b32 v35, v31, v39, s6 + v_perm_b32 v49, v31, v39, s20 + v_perm_b32 v53, v32, v40, s6 + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[50:51], a[128:143] + v_perm_b32 v57, v32, v40, s20 + v_perm_b32 v61, v33, v41, s6 + v_perm_b32 v65, v33, v41, s20 + s_waitcnt vmcnt(2) + v_perm_b32 v46, v18, v22, s6 + v_perm_b32 v28, v18, v22, s20 + v_perm_b32 v36, v19, v23, s6 + v_perm_b32 v50, v19, v23, s20 + v_mfma_f32_32x32x8_f16 a[240:255], v[118:119], v[68:69], a[240:255] + v_perm_b32 v54, v20, v24, s6 + v_perm_b32 v58, v20, v24, s20 + v_perm_b32 v62, v21, v25, s6 + v_perm_b32 v66, v21, v25, s20 + s_waitcnt vmcnt(0) + v_perm_b32 v47, v10, v14, s6 + v_perm_b32 v29, v10, v14, s20 + v_perm_b32 v37, v11, v15, s6 + v_mfma_f32_32x32x8_f16 a[32:47], v[122:123], v[68:69], a[32:47] + v_perm_b32 v51, v11, v15, s20 + v_perm_b32 v55, v12, v16, s6 + v_perm_b32 v59, v12, v16, s20 + v_perm_b32 v63, v13, v17, s6 + v_perm_b32 v67, v13, v17, s20 + ds_write_b128 v70, v[44:47] + ds_write_b128 v71, v[26:29] offset:512 + v_mfma_f32_32x32x8_f16 a[80:95], v[126:127], v[68:69], a[80:95] + ds_write_b128 v89, v[34:37] offset:512 + ds_write_b128 v86, v[48:51] offset:512 + ds_write_b128 v87, v[52:55] offset:512 + ds_write_b128 v116, v[56:59] offset:512 + ds_write_b128 v117, v[60:63] offset:512 + ds_write_b128 v113, v[64:67] offset:3584 + ds_write_b32 v0, v6 offset:32768 + v_mfma_f32_32x32x8_f16 a[128:143], v[130:131], v[68:69], a[128:143] + ds_write_b32 v88, v7 offset:32768 + ds_write_b32 v90, v8 offset:32768 + ds_write_b32 v91, v9 offset:32768 + ds_write_b32 v92, v2 offset:32768 + ds_write_b32 v93, v3 offset:32768 + ds_write_b32 v114, v4 offset:32768 + ds_write_b32 v115, v5 offset:32768 + s_cbranch_scc1 .LBB41_8 +; %bb.9: ; %Flow60 + v_mov_b32_e32 v2, v104 +.LBB41_10: ; %Flow62 + scratch_store_dword off, v184, off offset:8 ; 4-byte Folded Spill + scratch_store_dword off, v183, off offset:4 ; 4-byte Folded Spill + v_mov_b32_e32 v9, v190 + v_mov_b32_e32 v8, v189 + v_mov_b32_e32 v7, v188 + v_mov_b32_e32 v6, v187 + v_mov_b32_e32 v5, v186 + v_mov_b32_e32 v4, v185 + v_accvgpr_read_b32 v220, a4 + v_accvgpr_read_b32 v221, a5 + v_accvgpr_read_b32 v222, a6 + v_accvgpr_read_b32 v223, a7 + v_accvgpr_read_b32 v224, a8 + v_accvgpr_read_b32 v225, a9 + v_accvgpr_read_b32 v226, a10 + v_accvgpr_read_b32 v227, a11 + v_accvgpr_read_b32 v228, a12 + v_accvgpr_read_b32 v229, a13 + v_accvgpr_read_b32 v230, a14 + v_accvgpr_read_b32 v231, a15 + v_accvgpr_read_b32 v200, a224 + v_accvgpr_read_b32 v201, a225 + v_accvgpr_read_b32 v202, a226 + v_accvgpr_read_b32 v203, a227 + v_accvgpr_read_b32 v204, a228 + v_accvgpr_read_b32 v205, a229 + v_accvgpr_read_b32 v206, a230 + v_accvgpr_read_b32 v207, a231 + v_accvgpr_read_b32 v208, a232 + v_accvgpr_read_b32 v209, a233 + v_accvgpr_read_b32 v210, a234 + v_accvgpr_read_b32 v211, a235 + v_accvgpr_read_b32 v212, a236 + v_accvgpr_read_b32 v213, a237 + v_accvgpr_read_b32 v214, a238 + v_accvgpr_read_b32 v215, a239 + v_accvgpr_read_b32 v184, a240 + v_accvgpr_read_b32 v185, a241 + v_accvgpr_read_b32 v186, a242 + v_accvgpr_read_b32 v187, a243 + v_accvgpr_read_b32 v188, a244 + v_accvgpr_read_b32 v189, a245 + v_accvgpr_read_b32 v190, a246 + v_accvgpr_read_b32 v191, a247 + v_accvgpr_read_b32 v192, a248 + v_accvgpr_read_b32 v193, a249 + v_accvgpr_read_b32 v194, a250 + v_accvgpr_read_b32 v195, a251 + v_accvgpr_read_b32 v196, a252 + v_accvgpr_read_b32 v197, a253 + v_accvgpr_read_b32 v198, a254 + v_accvgpr_read_b32 v199, a255 + v_accvgpr_mov_b32 a224, a160 + v_accvgpr_mov_b32 a225, a161 + v_accvgpr_mov_b32 a226, a162 + v_accvgpr_mov_b32 a227, a163 + v_accvgpr_mov_b32 a228, a164 + v_accvgpr_mov_b32 a229, a165 + v_accvgpr_mov_b32 a230, a166 + v_accvgpr_mov_b32 a231, a167 + v_accvgpr_mov_b32 a232, a168 + v_accvgpr_mov_b32 a233, a169 + v_accvgpr_mov_b32 a234, a170 + v_accvgpr_mov_b32 a235, a171 + v_accvgpr_mov_b32 a236, a172 + v_accvgpr_mov_b32 a237, a173 + v_accvgpr_mov_b32 a238, a174 + v_accvgpr_mov_b32 a239, a175 + v_accvgpr_read_b32 v168, a208 + v_accvgpr_read_b32 v169, a209 + v_accvgpr_read_b32 v170, a210 + v_accvgpr_read_b32 v171, a211 + v_accvgpr_read_b32 v172, a212 + v_accvgpr_read_b32 v173, a213 + v_accvgpr_read_b32 v174, a214 + v_accvgpr_read_b32 v175, a215 + v_accvgpr_read_b32 v176, a216 + v_accvgpr_read_b32 v177, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v179, a219 + v_accvgpr_read_b32 v180, a220 + v_accvgpr_read_b32 v181, a221 + v_accvgpr_read_b32 v182, a222 + v_accvgpr_read_b32 v183, a223 + v_accvgpr_read_b32 v152, a16 + v_accvgpr_read_b32 v153, a17 + v_accvgpr_read_b32 v154, a18 + v_accvgpr_read_b32 v155, a19 + v_accvgpr_read_b32 v156, a20 + v_accvgpr_read_b32 v157, a21 + v_accvgpr_read_b32 v158, a22 + v_accvgpr_read_b32 v159, a23 + v_accvgpr_read_b32 v160, a24 + v_accvgpr_read_b32 v161, a25 + v_accvgpr_read_b32 v162, a26 + v_accvgpr_read_b32 v163, a27 + v_accvgpr_read_b32 v164, a28 + v_accvgpr_read_b32 v165, a29 + v_accvgpr_read_b32 v166, a30 + v_accvgpr_read_b32 v167, a31 + v_accvgpr_mov_b32 a160, a32 + v_accvgpr_mov_b32 a161, a33 + v_accvgpr_mov_b32 a162, a34 + v_accvgpr_mov_b32 a163, a35 + v_accvgpr_mov_b32 a164, a36 + v_accvgpr_mov_b32 a165, a37 + v_accvgpr_mov_b32 a166, a38 + v_accvgpr_mov_b32 a167, a39 + v_accvgpr_mov_b32 a168, a40 + v_accvgpr_mov_b32 a169, a41 + v_accvgpr_mov_b32 a170, a42 + v_accvgpr_mov_b32 a171, a43 + v_accvgpr_mov_b32 a172, a44 + v_accvgpr_mov_b32 a173, a45 + v_accvgpr_mov_b32 a174, a46 + v_accvgpr_mov_b32 a175, a47 + v_accvgpr_read_b32 v136, a176 + v_accvgpr_read_b32 v137, a177 + v_accvgpr_read_b32 v138, a178 + v_accvgpr_read_b32 v139, a179 + v_accvgpr_read_b32 v140, a180 + v_accvgpr_read_b32 v141, a181 + v_accvgpr_read_b32 v142, a182 + v_accvgpr_read_b32 v143, a183 + v_accvgpr_read_b32 v144, a184 + v_accvgpr_read_b32 v145, a185 + v_accvgpr_read_b32 v146, a186 + v_accvgpr_read_b32 v147, a187 + v_accvgpr_read_b32 v148, a188 + v_accvgpr_read_b32 v149, a189 + v_accvgpr_read_b32 v150, a190 + v_accvgpr_read_b32 v151, a191 + v_accvgpr_read_b32 v120, a48 + v_accvgpr_read_b32 v121, a49 + v_accvgpr_read_b32 v122, a50 + v_accvgpr_read_b32 v123, a51 + v_accvgpr_read_b32 v124, a52 + v_accvgpr_read_b32 v125, a53 + v_accvgpr_read_b32 v126, a54 + v_accvgpr_read_b32 v127, a55 + v_accvgpr_read_b32 v128, a56 + v_accvgpr_read_b32 v129, a57 + v_accvgpr_read_b32 v130, a58 + v_accvgpr_read_b32 v131, a59 + v_accvgpr_read_b32 v132, a60 + v_accvgpr_read_b32 v133, a61 + v_accvgpr_read_b32 v134, a62 + v_accvgpr_read_b32 v135, a63 + v_accvgpr_read_b32 v104, a64 + v_accvgpr_read_b32 v105, a65 + v_accvgpr_read_b32 v106, a66 + v_accvgpr_read_b32 v107, a67 + v_accvgpr_read_b32 v108, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v110, a70 + v_accvgpr_read_b32 v111, a71 + v_accvgpr_read_b32 v112, a72 + v_accvgpr_read_b32 v113, a73 + v_accvgpr_read_b32 v114, a74 + v_accvgpr_read_b32 v115, a75 + v_accvgpr_read_b32 v116, a76 + v_accvgpr_read_b32 v117, a77 + v_accvgpr_read_b32 v118, a78 + v_accvgpr_read_b32 v119, a79 + v_accvgpr_mov_b32 a48, a192 + v_accvgpr_mov_b32 a49, a193 + v_accvgpr_mov_b32 a50, a194 + v_accvgpr_mov_b32 a51, a195 + v_accvgpr_mov_b32 a52, a196 + v_accvgpr_mov_b32 a53, a197 + v_accvgpr_mov_b32 a54, a198 + v_accvgpr_mov_b32 a55, a199 + v_accvgpr_mov_b32 a56, a200 + v_accvgpr_mov_b32 a57, a201 + v_accvgpr_mov_b32 a58, a202 + v_accvgpr_mov_b32 a59, a203 + v_accvgpr_mov_b32 a60, a204 + v_accvgpr_mov_b32 a61, a205 + v_accvgpr_mov_b32 a62, a206 + v_accvgpr_mov_b32 a63, a207 + v_accvgpr_mov_b32 a32, a96 + v_accvgpr_mov_b32 a33, a97 + v_accvgpr_mov_b32 a34, a98 + v_accvgpr_mov_b32 a35, a99 + v_accvgpr_mov_b32 a36, a100 + v_accvgpr_mov_b32 a37, a101 + v_accvgpr_mov_b32 a38, a102 + v_accvgpr_mov_b32 a39, a103 + v_accvgpr_mov_b32 a40, a104 + v_accvgpr_mov_b32 a41, a105 + v_accvgpr_mov_b32 a42, a106 + v_accvgpr_mov_b32 a43, a107 + v_accvgpr_mov_b32 a44, a108 + v_accvgpr_mov_b32 a45, a109 + v_accvgpr_mov_b32 a46, a110 + v_accvgpr_mov_b32 a47, a111 + v_accvgpr_mov_b32 a16, a112 + v_accvgpr_mov_b32 a17, a113 + v_accvgpr_mov_b32 a18, a114 + v_accvgpr_mov_b32 a19, a115 + v_accvgpr_mov_b32 a20, a116 + v_accvgpr_mov_b32 a21, a117 + v_accvgpr_mov_b32 a22, a118 + v_accvgpr_mov_b32 a23, a119 + v_accvgpr_mov_b32 a24, a120 + v_accvgpr_mov_b32 a25, a121 + v_accvgpr_mov_b32 a26, a122 + v_accvgpr_mov_b32 a27, a123 + v_accvgpr_mov_b32 a28, a124 + v_accvgpr_mov_b32 a29, a125 + v_accvgpr_mov_b32 a30, a126 + v_accvgpr_mov_b32 a31, a127 + v_accvgpr_mov_b32 a240, a128 + v_accvgpr_mov_b32 a241, a129 + v_accvgpr_mov_b32 a242, a130 + v_accvgpr_mov_b32 a243, a131 + v_accvgpr_mov_b32 a244, a132 + v_accvgpr_mov_b32 a245, a133 + v_accvgpr_mov_b32 a246, a134 + v_accvgpr_mov_b32 a247, a135 + v_accvgpr_mov_b32 a248, a136 + v_accvgpr_mov_b32 a249, a137 + v_accvgpr_mov_b32 a250, a138 + v_accvgpr_mov_b32 a251, a139 + v_accvgpr_mov_b32 a252, a140 + v_accvgpr_mov_b32 a253, a141 + v_accvgpr_mov_b32 a254, a142 + v_accvgpr_mov_b32 a255, a143 + v_accvgpr_read_b32 v219, a3 + v_accvgpr_read_b32 v218, a2 + v_accvgpr_read_b32 v217, a1 + v_accvgpr_read_b32 v216, a0 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 1, v43 + v_lshlrev_b32_e32 v3, 1, v73 + ds_read_b128 v[240:243], v0 + ds_read_b128 v[232:235], v3 + v_lshlrev_b32_e32 v0, 1, v74 + v_lshlrev_b32_e32 v3, 1, v75 + ds_read_b128 v[60:63], v0 + ds_read_b128 a[96:99], v3 + v_lshlrev_b32_e32 v0, 1, v76 + v_lshlrev_b32_e32 v3, 1, v77 + ds_read_b128 v[244:247], v0 + ds_read_b128 v[236:239], v3 + v_lshlrev_b32_e32 v0, 1, v78 + v_lshlrev_b32_e32 v3, 1, v79 + ds_read_b128 v[64:67], v0 + ds_read_b128 v[90:93], v3 + v_lshlrev_b32_e32 v0, 1, v80 + v_lshlrev_b32_e32 v3, 1, v81 + ds_read_b128 v[248:251], v0 + ds_read_b128 v[76:79], v3 + v_lshlrev_b32_e32 v0, 1, v82 + v_lshlrev_b32_e32 v3, 1, v83 + ds_read_b128 v[68:71], v0 + ds_read_b128 v[86:89], v3 + v_lshlrev_b32_e32 v0, 1, v84 + v_lshlrev_b32_e32 v3, 1, v85 + ds_read_b128 v[252:255], v0 + ds_read_b128 v[80:83], v3 + v_lshlrev_b32_e32 v0, 1, v72 + ds_read_b128 a[100:103], v102 + ds_read_b128 v[72:75], v0 + ds_read_b32 v2, v2 offset:32768 + ds_read_b32 v3, v4 offset:32768 + ds_read_b32 v4, v5 offset:32768 + ds_read_b32 v5, v6 offset:32768 + ds_read_b32 v1, v1 offset:32768 + ds_read_b32 v6, v7 offset:32768 + ds_read_b32 v7, v8 offset:32768 + ds_read_b32 v8, v9 offset:32768 + ds_read_b32 v30, v94 offset:32768 + ds_read_b32 v31, v95 offset:32768 + ds_read_b32 v32, v96 offset:32768 + ds_read_b32 v33, v97 offset:32768 + ds_read_b32 v84, v98 offset:32768 + ds_read_b32 v59, v99 offset:32768 + ds_read_b32 v58, v100 offset:32768 + ds_read_b32 v0, v101 offset:32768 + v_mov_b32_e32 v52, 0xf000f + v_mov_b32_e32 v53, 0x64006400 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v9, v2, v52, v53 + ;;#ASMEND + v_mov_b32_e32 v54, 0xf000f0 + ;;#ASMSTART + v_and_or_b32 v10, v2, v54, v53 + ;;#ASMEND + v_mov_b32_e32 v55, 0xe408e408 + ;;#ASMSTART + v_pk_add_f16 v26, v9, v55 + ;;#ASMEND + v_mov_b32_e32 v56, 0x2c002c00 + v_mov_b32_e32 v57, 0xd480d480 + ;;#ASMSTART + v_pk_fma_f16 v27, v10, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v2 + ;;#ASMSTART + v_and_or_b32 v9, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v9, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v2, v56, v57 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v3, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v9, v3, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v9, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v3 + ;;#ASMSTART + v_and_or_b32 v3, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v20, v3, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v2, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(13) + ;;#ASMSTART + v_and_or_b32 v2, v4, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v4, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v3, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v4 + ;;#ASMSTART + v_and_or_b32 v3, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v12, v3, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v13, v2, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(12) + ;;#ASMSTART + v_and_or_b32 v2, v5, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v5, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v2, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v3, v3, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v4, 8, v5 + ;;#ASMSTART + v_and_or_b32 v5, v4, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v9, v4, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v4, v5, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v5, v9, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v9, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v14, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v34, v9, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v35, v14, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v1 + ;;#ASMSTART + v_and_or_b32 v9, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v36, v9, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v37, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(10) + ;;#ASMSTART + v_and_or_b32 v1, v6, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v9, v6, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v22, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v23, v9, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v6 + ;;#ASMSTART + v_and_or_b32 v6, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v24, v6, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v25, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(9) + ;;#ASMSTART + v_and_or_b32 v1, v7, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v7, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v14, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v15, v6, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v7 + ;;#ASMSTART + v_and_or_b32 v6, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v6, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(8) + ;;#ASMSTART + v_and_or_b32 v1, v8, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v8, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v6, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v7, v7, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v8 + ;;#ASMSTART + v_and_or_b32 v8, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v8, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v1, v30, v52, v53 + ;;#ASMEND + v_accvgpr_mov_b32 a0, a144 + v_accvgpr_mov_b32 a1, a145 + v_accvgpr_mov_b32 a2, a146 + v_accvgpr_mov_b32 a3, a147 + v_accvgpr_mov_b32 a4, a148 + v_accvgpr_mov_b32 a5, a149 + v_accvgpr_mov_b32 a6, a150 + v_accvgpr_mov_b32 a7, a151 + v_accvgpr_mov_b32 a8, a152 + v_accvgpr_mov_b32 a9, a153 + v_accvgpr_mov_b32 a10, a154 + v_accvgpr_mov_b32 a11, a155 + v_accvgpr_mov_b32 a12, a156 + v_accvgpr_mov_b32 a13, a157 + v_accvgpr_mov_b32 a14, a158 + v_accvgpr_mov_b32 a15, a159 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[0:15], a[100:101], v[26:27], a[0:15] + ;;#ASMSTART + v_and_or_b32 v38, v30, v54, v53 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v46, v1, v55 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v47, v38, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v30 + ;;#ASMSTART + v_and_or_b32 v30, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v30, v55 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[0:15], a[102:103], v[28:29], a[0:15] + ;;#ASMSTART + v_pk_fma_f16 v49, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(6) + ;;#ASMSTART + v_and_or_b32 v1, v31, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v31, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v42, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v43, v30, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v31 + v_accvgpr_write_b32 a64, v216 + v_accvgpr_write_b32 a65, v217 + v_accvgpr_write_b32 a66, v218 + v_accvgpr_write_b32 a67, v219 + v_accvgpr_write_b32 a68, v220 + v_accvgpr_write_b32 a69, v221 + v_accvgpr_write_b32 a70, v222 + v_accvgpr_write_b32 a71, v223 + v_accvgpr_write_b32 a72, v224 + v_accvgpr_write_b32 a73, v225 + v_accvgpr_write_b32 a74, v226 + v_accvgpr_write_b32 a75, v227 + v_accvgpr_write_b32 a76, v228 + v_accvgpr_write_b32 a77, v229 + v_accvgpr_write_b32 a78, v230 + v_accvgpr_write_b32 a79, v231 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], a[100:101], v[34:35], a[64:79] + ;;#ASMSTART + v_and_or_b32 v30, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v44, v30, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v45, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(5) + ;;#ASMSTART + v_and_or_b32 v1, v32, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v32, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v38, v1, v55 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], a[102:103], v[36:37], a[64:79] + ;;#ASMSTART + v_pk_fma_f16 v39, v30, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v32 + ;;#ASMSTART + v_and_or_b32 v30, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v40, v30, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v41, v1, v56, v57 + ;;#ASMEND + v_accvgpr_write_b32 a144, v200 + v_accvgpr_write_b32 a145, v201 + v_accvgpr_write_b32 a146, v202 + v_accvgpr_write_b32 a147, v203 + v_accvgpr_write_b32 a148, v204 + v_accvgpr_write_b32 a149, v205 + v_accvgpr_write_b32 a150, v206 + v_accvgpr_write_b32 a151, v207 + v_accvgpr_write_b32 a152, v208 + v_accvgpr_write_b32 a153, v209 + v_accvgpr_write_b32 a154, v210 + v_accvgpr_write_b32 a155, v211 + v_accvgpr_write_b32 a156, v212 + v_accvgpr_write_b32 a157, v213 + v_accvgpr_write_b32 a158, v214 + v_accvgpr_write_b32 a159, v215 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[144:159], a[100:101], v[46:47], a[144:159] + s_waitcnt lgkmcnt(4) + ;;#ASMSTART + v_and_or_b32 v1, v33, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v33, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v30, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v31, v31, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v1, 8, v33 + ;;#ASMSTART + v_and_or_b32 v32, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], a[102:103], v[48:49], a[144:159] + ;;#ASMSTART + v_pk_add_f16 v32, v32, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v33, v1, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v1, v84, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v51, v84, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v51, v56, v57 + ;;#ASMEND + v_accvgpr_write_b32 a223, v199 + v_accvgpr_write_b32 a222, v198 + v_accvgpr_write_b32 a221, v197 + v_accvgpr_write_b32 a220, v196 + v_accvgpr_write_b32 a219, v195 + v_accvgpr_write_b32 a218, v194 + v_accvgpr_write_b32 a217, v193 + v_accvgpr_write_b32 a216, v192 + v_accvgpr_write_b32 a215, v191 + v_accvgpr_write_b32 a214, v190 + v_accvgpr_write_b32 a213, v189 + v_accvgpr_write_b32 a212, v188 + v_accvgpr_write_b32 a211, v187 + v_accvgpr_write_b32 a210, v186 + v_accvgpr_write_b32 a209, v185 + v_accvgpr_write_b32 a208, v184 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[208:223], a[100:101], v[50:51], a[208:223] + v_ashrrev_i32_e32 v1, 8, v84 + ;;#ASMSTART + v_and_or_b32 v84, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v84, v84, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v85, v1, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], a[102:103], v[84:85], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], a[96:97], v[26:27], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], a[98:99], v[28:29], a[224:239] + v_accvgpr_write_b32 a207, v183 + v_accvgpr_write_b32 a206, v182 + v_accvgpr_write_b32 a205, v181 + v_accvgpr_write_b32 a204, v180 + v_accvgpr_write_b32 a203, v179 + v_accvgpr_write_b32 a202, v178 + v_accvgpr_write_b32 a201, v177 + v_accvgpr_write_b32 a200, v176 + v_accvgpr_write_b32 a199, v175 + v_accvgpr_write_b32 a198, v174 + v_accvgpr_write_b32 a197, v173 + v_accvgpr_write_b32 a196, v172 + v_accvgpr_write_b32 a195, v171 + v_accvgpr_write_b32 a194, v170 + v_accvgpr_write_b32 a193, v169 + v_accvgpr_write_b32 a192, v168 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[192:207], a[96:97], v[34:35], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], a[98:99], v[36:37], a[192:207] + v_accvgpr_write_b32 a191, v167 + v_accvgpr_write_b32 a190, v166 + v_accvgpr_write_b32 a189, v165 + v_accvgpr_write_b32 a188, v164 + v_accvgpr_write_b32 a187, v163 + v_accvgpr_write_b32 a186, v162 + v_accvgpr_write_b32 a185, v161 + v_accvgpr_write_b32 a184, v160 + v_accvgpr_write_b32 a183, v159 + v_accvgpr_write_b32 a182, v158 + v_accvgpr_write_b32 a181, v157 + v_accvgpr_write_b32 a180, v156 + v_accvgpr_write_b32 a179, v155 + v_accvgpr_write_b32 a178, v154 + v_accvgpr_write_b32 a177, v153 + v_accvgpr_write_b32 a176, v152 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[176:191], a[96:97], v[46:47], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], a[98:99], v[48:49], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], a[96:97], v[50:51], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], a[98:99], v[84:85], a[160:175] + v_accvgpr_write_b32 a128, v136 + v_accvgpr_write_b32 a129, v137 + v_accvgpr_write_b32 a130, v138 + v_accvgpr_write_b32 a131, v139 + v_accvgpr_write_b32 a132, v140 + v_accvgpr_write_b32 a133, v141 + v_accvgpr_write_b32 a134, v142 + v_accvgpr_write_b32 a135, v143 + v_accvgpr_write_b32 a136, v144 + v_accvgpr_write_b32 a137, v145 + v_accvgpr_write_b32 a138, v146 + v_accvgpr_write_b32 a139, v147 + v_accvgpr_write_b32 a140, v148 + v_accvgpr_write_b32 a141, v149 + v_accvgpr_write_b32 a142, v150 + v_accvgpr_write_b32 a143, v151 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[128:143], v[90:91], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[92:93], v[28:29], a[128:143] + v_accvgpr_write_b32 a112, v120 + v_accvgpr_write_b32 a113, v121 + v_accvgpr_write_b32 a114, v122 + v_accvgpr_write_b32 a115, v123 + v_accvgpr_write_b32 a116, v124 + v_accvgpr_write_b32 a117, v125 + v_accvgpr_write_b32 a118, v126 + v_accvgpr_write_b32 a119, v127 + v_accvgpr_write_b32 a120, v128 + v_accvgpr_write_b32 a121, v129 + v_accvgpr_write_b32 a122, v130 + v_accvgpr_write_b32 a123, v131 + v_accvgpr_write_b32 a124, v132 + v_accvgpr_write_b32 a125, v133 + v_accvgpr_write_b32 a126, v134 + v_accvgpr_write_b32 a127, v135 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[112:127], v[90:91], v[34:35], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[92:93], v[36:37], a[112:127] + v_accvgpr_write_b32 a96, v104 + v_accvgpr_write_b32 a97, v105 + v_accvgpr_write_b32 a98, v106 + v_accvgpr_write_b32 a99, v107 + v_accvgpr_write_b32 a100, v108 + v_accvgpr_write_b32 a101, v109 + v_accvgpr_write_b32 a102, v110 + v_accvgpr_write_b32 a103, v111 + v_accvgpr_write_b32 a104, v112 + v_accvgpr_write_b32 a105, v113 + v_accvgpr_write_b32 a106, v114 + v_accvgpr_write_b32 a107, v115 + v_accvgpr_write_b32 a108, v116 + v_accvgpr_write_b32 a109, v117 + v_accvgpr_write_b32 a110, v118 + v_accvgpr_write_b32 a111, v119 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[96:111], v[90:91], v[46:47], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[92:93], v[48:49], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[90:91], v[50:51], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[92:93], v[84:85], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[86:87], v[26:27], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[88:89], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[86:87], v[34:35], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[88:89], v[36:37], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[86:87], v[46:47], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[88:89], v[48:49], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[86:87], v[50:51], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[88:89], v[84:85], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[240:241], v[18:19], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[242:243], v[20:21], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[240:241], v[22:23], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[242:243], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[240:241], v[42:43], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[242:243], v[44:45], a[144:159] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v1, v59, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v27, v59, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v26, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v27, v27, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[240:241], v[26:27], a[208:223] + v_ashrrev_i32_e32 v1, 8, v59 + ;;#ASMSTART + v_and_or_b32 v28, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v28, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v1, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[242:243], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[244:245], v[18:19], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[246:247], v[20:21], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[244:245], v[22:23], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[246:247], v[24:25], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[244:245], v[42:43], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[246:247], v[44:45], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[244:245], v[26:27], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[246:247], v[28:29], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[248:249], v[18:19], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[250:251], v[20:21], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[248:249], v[22:23], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[250:251], v[24:25], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[248:249], v[42:43], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[250:251], v[44:45], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[248:249], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[250:251], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[252:253], v[18:19], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[254:255], v[20:21], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[252:253], v[22:23], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[254:255], v[24:25], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[252:253], v[42:43], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[254:255], v[44:45], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[252:253], v[26:27], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[254:255], v[28:29], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[232:233], v[10:11], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[234:235], v[12:13], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[232:233], v[14:15], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[234:235], v[16:17], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[232:233], v[38:39], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[234:235], v[40:41], a[144:159] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v1, v58, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v19, v58, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v19, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[232:233], v[18:19], a[208:223] + v_ashrrev_i32_e32 v1, 8, v58 + ;;#ASMSTART + v_and_or_b32 v20, v1, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v1, v1, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v20, v20, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v1, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[234:235], v[20:21], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[236:237], v[10:11], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[238:239], v[12:13], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[236:237], v[14:15], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[238:239], v[16:17], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[236:237], v[38:39], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[238:239], v[40:41], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[236:237], v[18:19], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[238:239], v[20:21], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[76:77], v[10:11], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[78:79], v[12:13], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[76:77], v[14:15], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[78:79], v[16:17], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[76:77], v[38:39], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[78:79], v[40:41], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[76:77], v[18:19], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[78:79], v[20:21], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[80:81], v[10:11], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[82:83], v[12:13], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[80:81], v[14:15], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[82:83], v[16:17], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[80:81], v[38:39], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[82:83], v[40:41], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[80:81], v[18:19], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[82:83], v[20:21], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[60:61], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[62:63], v[4:5], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[60:61], v[6:7], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[62:63], v[8:9], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[60:61], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[62:63], v[32:33], a[144:159] + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v1, v0, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v11, v0, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v11, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[60:61], v[10:11], a[208:223] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v1, v0, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v12, v0, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v0, v1, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v1, v12, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[62:63], v[0:1], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[64:65], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[66:67], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[64:65], v[6:7], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[66:67], v[8:9], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[64:65], v[30:31], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[66:67], v[32:33], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[64:65], v[10:11], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[66:67], v[0:1], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[68:69], v[2:3], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[70:71], v[4:5], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[68:69], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[70:71], v[8:9], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[68:69], v[30:31], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[70:71], v[32:33], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[68:69], v[10:11], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[70:71], v[0:1], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[72:73], v[2:3], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[74:75], v[4:5], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[72:73], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[74:75], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[72:73], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[74:75], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[72:73], v[10:11], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[74:75], v[0:1], a[240:255] +.LBB41_11: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESC_NSB_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi8ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi64EEENS1E_ILi256EEEEEEEEEEENSL_IJNSM_INSN_INSO_ILSP_1EKS2_lLb1ELSR_0EEENST_ISZ_S13_S17_S18_lNS4_IJLin1ELin1ELi64ELin1ELin1EEEES1A_EELS1C_0EEENSL_IJS1G_S1F_ + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v139, a4 + v_accvgpr_read_b32 v18, a5 + v_accvgpr_read_b32 v0, a6 + v_accvgpr_read_b32 v138, a7 + v_accvgpr_read_b32 v137, a8 + v_accvgpr_read_b32 v136, a9 + v_accvgpr_read_b32 v135, a10 + v_accvgpr_read_b32 v134, a11 + v_accvgpr_read_b32 v133, a12 + v_accvgpr_read_b32 v132, a13 + v_accvgpr_read_b32 v131, a14 + v_accvgpr_read_b32 v130, a15 + v_accvgpr_read_b32 v108, a64 + v_accvgpr_read_b32 v107, a65 + v_accvgpr_read_b32 v106, a66 + v_accvgpr_read_b32 v105, a67 + v_accvgpr_read_b32 v104, a68 + v_accvgpr_read_b32 v103, a69 + v_accvgpr_read_b32 v102, a70 + v_accvgpr_read_b32 v101, a71 + v_accvgpr_read_b32 v100, a72 + v_accvgpr_read_b32 v99, a73 + v_accvgpr_read_b32 v98, a74 + v_accvgpr_read_b32 v97, a75 + v_accvgpr_read_b32 v96, a76 + v_accvgpr_read_b32 v95, a77 + v_accvgpr_read_b32 v94, a78 + v_accvgpr_read_b32 v93, a79 + v_accvgpr_read_b32 v92, a144 + v_accvgpr_read_b32 v91, a145 + v_accvgpr_read_b32 v90, a146 + v_accvgpr_read_b32 v89, a147 + v_accvgpr_read_b32 v88, a148 + v_accvgpr_read_b32 v87, a149 + v_accvgpr_read_b32 v86, a150 + v_accvgpr_read_b32 v85, a151 + v_accvgpr_read_b32 v84, a152 + v_accvgpr_read_b32 v83, a153 + v_accvgpr_read_b32 v82, a154 + v_accvgpr_read_b32 v81, a155 + v_accvgpr_read_b32 v80, a156 + v_accvgpr_read_b32 v79, a157 + v_accvgpr_read_b32 v78, a158 + v_accvgpr_read_b32 v77, a159 + v_accvgpr_read_b32 v76, a208 + v_accvgpr_read_b32 v75, a209 + v_accvgpr_read_b32 v74, a210 + v_accvgpr_read_b32 v73, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v70, a213 + v_accvgpr_read_b32 v69, a214 + v_accvgpr_read_b32 v68, a215 + v_accvgpr_read_b32 v67, a216 + v_accvgpr_read_b32 v66, a217 + v_accvgpr_read_b32 v65, a218 + v_accvgpr_read_b32 v64, a219 + v_accvgpr_read_b32 v63, a220 + v_accvgpr_read_b32 v62, a221 + v_accvgpr_read_b32 v61, a222 + v_accvgpr_read_b32 v20, a223 + v_accvgpr_read_b32 v224, a224 + v_accvgpr_read_b32 v223, a225 + v_accvgpr_read_b32 v222, a226 + v_accvgpr_read_b32 v221, a227 + v_accvgpr_read_b32 v220, a228 + v_accvgpr_read_b32 v219, a229 + v_accvgpr_read_b32 v218, a230 + v_accvgpr_read_b32 v217, a231 + v_accvgpr_read_b32 v216, a232 + v_accvgpr_read_b32 v215, a233 + v_accvgpr_read_b32 v214, a234 + v_accvgpr_read_b32 v213, a235 + v_accvgpr_read_b32 v212, a236 + v_accvgpr_read_b32 v211, a237 + v_accvgpr_read_b32 v210, a238 + v_accvgpr_read_b32 v209, a239 + v_accvgpr_read_b32 v177, a192 + v_accvgpr_read_b32 v176, a193 + v_accvgpr_read_b32 v175, a194 + v_accvgpr_read_b32 v174, a195 + v_accvgpr_read_b32 v173, a196 + v_accvgpr_read_b32 v172, a197 + v_accvgpr_read_b32 v171, a198 + v_accvgpr_read_b32 v170, a199 + v_accvgpr_read_b32 v169, a200 + v_accvgpr_read_b32 v168, a201 + v_accvgpr_read_b32 v167, a202 + v_accvgpr_read_b32 v166, a203 + v_accvgpr_read_b32 v165, a204 + v_accvgpr_read_b32 v164, a205 + v_accvgpr_read_b32 v163, a206 + v_accvgpr_read_b32 v162, a207 + v_accvgpr_read_b32 v161, a176 + v_accvgpr_read_b32 v160, a177 + v_accvgpr_read_b32 v159, a178 + v_accvgpr_read_b32 v158, a179 + v_accvgpr_read_b32 v157, a180 + v_accvgpr_read_b32 v156, a181 + v_accvgpr_read_b32 v155, a182 + v_accvgpr_read_b32 v154, a183 + v_accvgpr_read_b32 v153, a184 + v_accvgpr_read_b32 v152, a185 + v_accvgpr_read_b32 v151, a186 + v_accvgpr_read_b32 v150, a187 + v_accvgpr_read_b32 v149, a188 + v_accvgpr_read_b32 v148, a189 + v_accvgpr_read_b32 v145, a190 + v_accvgpr_read_b32 v144, a191 + v_accvgpr_read_b32 v146, a160 + v_accvgpr_read_b32 v147, a161 + v_accvgpr_read_b32 v129, a162 + v_accvgpr_read_b32 v128, a163 + v_accvgpr_read_b32 v127, a164 + v_accvgpr_read_b32 v126, a165 + v_accvgpr_read_b32 v125, a166 + v_accvgpr_read_b32 v124, a167 + v_accvgpr_read_b32 v123, a168 + v_accvgpr_read_b32 v122, a169 + v_accvgpr_read_b32 v121, a170 + v_accvgpr_read_b32 v120, a171 + v_accvgpr_read_b32 v119, a172 + v_accvgpr_read_b32 v118, a173 + v_accvgpr_read_b32 v117, a174 + v_accvgpr_read_b32 v116, a175 + v_accvgpr_mov_b32 a15, a128 + v_accvgpr_mov_b32 a14, a129 + v_accvgpr_mov_b32 a13, a130 + v_accvgpr_mov_b32 a12, a131 + v_accvgpr_mov_b32 a11, a132 + v_accvgpr_mov_b32 a10, a133 + v_accvgpr_mov_b32 a9, a134 + v_accvgpr_mov_b32 a8, a135 + v_accvgpr_mov_b32 a7, a136 + v_accvgpr_mov_b32 a6, a137 + v_accvgpr_mov_b32 a5, a138 + v_accvgpr_mov_b32 a4, a139 + v_accvgpr_mov_b32 a3, a140 + v_accvgpr_mov_b32 a2, a141 + v_accvgpr_mov_b32 a1, a142 + v_accvgpr_mov_b32 a0, a143 + v_accvgpr_read_b32 v60, a112 + v_accvgpr_read_b32 v59, a113 + v_accvgpr_read_b32 v58, a114 + v_accvgpr_read_b32 v57, a115 + v_accvgpr_read_b32 v56, a116 + v_accvgpr_read_b32 v55, a117 + v_accvgpr_read_b32 v54, a118 + v_accvgpr_read_b32 v53, a119 + v_accvgpr_read_b32 v52, a120 + v_accvgpr_read_b32 v51, a121 + v_accvgpr_read_b32 v50, a122 + v_accvgpr_read_b32 v25, a123 + v_accvgpr_read_b32 v24, a124 + v_accvgpr_read_b32 v23, a125 + v_accvgpr_read_b32 v22, a126 + v_accvgpr_read_b32 v21, a127 + v_accvgpr_read_b32 v115, a96 + v_accvgpr_read_b32 v114, a97 + v_accvgpr_read_b32 v113, a98 + v_accvgpr_read_b32 v112, a99 + v_accvgpr_read_b32 v111, a100 + v_accvgpr_read_b32 v110, a101 + v_accvgpr_read_b32 v109, a102 + v_accvgpr_read_b32 v72, a103 + v_accvgpr_read_b32 v49, a104 + v_accvgpr_read_b32 v48, a105 + v_accvgpr_read_b32 v47, a106 + v_accvgpr_read_b32 v46, a107 + v_accvgpr_read_b32 v45, a108 + v_accvgpr_read_b32 v44, a109 + v_accvgpr_read_b32 v43, a110 + v_accvgpr_read_b32 v42, a111 + v_accvgpr_read_b32 v208, a80 + v_accvgpr_read_b32 v207, a81 + v_accvgpr_read_b32 v206, a82 + v_accvgpr_read_b32 v205, a83 + v_accvgpr_read_b32 v204, a84 + v_accvgpr_read_b32 v203, a85 + v_accvgpr_read_b32 v202, a86 + v_accvgpr_read_b32 v201, a87 + v_accvgpr_read_b32 v200, a88 + v_accvgpr_read_b32 v199, a89 + v_accvgpr_read_b32 v198, a90 + v_accvgpr_read_b32 v197, a91 + v_accvgpr_read_b32 v196, a92 + v_accvgpr_read_b32 v195, a93 + v_accvgpr_read_b32 v194, a94 + v_accvgpr_read_b32 v1, a95 + v_accvgpr_mov_b32 a71, a48 + v_accvgpr_mov_b32 a70, a49 + v_accvgpr_mov_b32 a69, a50 + v_accvgpr_mov_b32 a68, a51 + v_accvgpr_mov_b32 a67, a52 + v_accvgpr_mov_b32 a66, a53 + v_accvgpr_mov_b32 a65, a54 + v_accvgpr_mov_b32 a64, a55 + v_accvgpr_mov_b32 a55, a56 + v_accvgpr_mov_b32 a54, a57 + v_accvgpr_mov_b32 a53, a58 + v_accvgpr_mov_b32 a52, a59 + v_accvgpr_mov_b32 a51, a60 + v_accvgpr_mov_b32 a50, a61 + v_accvgpr_mov_b32 a49, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v41, a32 + v_accvgpr_read_b32 v40, a33 + v_accvgpr_read_b32 v39, a34 + v_accvgpr_read_b32 v38, a35 + v_accvgpr_read_b32 v37, a36 + v_accvgpr_read_b32 v36, a37 + v_accvgpr_read_b32 v35, a38 + v_accvgpr_read_b32 v34, a39 + v_accvgpr_read_b32 v33, a40 + v_accvgpr_read_b32 v32, a41 + v_accvgpr_read_b32 v31, a42 + v_accvgpr_read_b32 v30, a43 + v_accvgpr_read_b32 v29, a44 + v_accvgpr_read_b32 v28, a45 + v_accvgpr_read_b32 v27, a46 + v_accvgpr_read_b32 v26, a47 + v_accvgpr_read_b32 v193, a16 + v_accvgpr_read_b32 v192, a17 + v_accvgpr_read_b32 v191, a18 + v_accvgpr_read_b32 v190, a19 + v_accvgpr_read_b32 v189, a20 + v_accvgpr_read_b32 v188, a21 + v_accvgpr_read_b32 v187, a22 + v_accvgpr_read_b32 v186, a23 + v_accvgpr_read_b32 v185, a24 + v_accvgpr_read_b32 v184, a25 + v_accvgpr_read_b32 v183, a26 + v_accvgpr_read_b32 v182, a27 + v_accvgpr_read_b32 v181, a28 + v_accvgpr_read_b32 v180, a29 + v_accvgpr_read_b32 v179, a30 + v_accvgpr_read_b32 v178, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s2, s4, s16 + s_mul_hi_u32 s3, 0, s16 + s_add_i32 s3, s3, s2 + s_add_u32 s2, s5, s3 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + scratch_load_dword v226, off, off offset:4 ; 4-byte Folded Reload + s_waitcnt vmcnt(0) + v_and_b32_e32 v225, 24, v226 + v_lshrrev_b32_e32 v19, 3, v226 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v227, v130 + v_cvt_f16_f32_e32 v228, v224 + v_cvt_f16_f32_e32 v229, v223 + v_cvt_f16_f32_e32 v230, v222 + v_cvt_f16_f32_e32 v231, v221 + v_cvt_f16_f32_e32 v232, v220 + v_cvt_f16_f32_e32 v233, v219 + v_cvt_f16_f32_e32 v234, v218 + v_cvt_f16_f32_e32 v235, v217 + v_cvt_f16_f32_e32 v236, v216 + v_cvt_f16_f32_e32 v237, v215 + v_cvt_f16_f32_e32 v238, v214 + v_cvt_f16_f32_e32 v239, v213 + v_cvt_f16_f32_e32 v240, v212 + v_cvt_f16_f32_e32 v241, v211 + v_cvt_f16_f32_e32 v242, v210 + v_cvt_f16_f32_e32 v243, v209 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v108, v108 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v209, v93 + v_cvt_f16_f32_e32 v210, v177 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v93, v162 + v_cvt_f16_f32_e32 v162, v92 + v_cvt_f16_f32_e32 v163, v91 + v_cvt_f16_f32_e32 v164, v90 + v_cvt_f16_f32_e32 v165, v89 + v_cvt_f16_f32_e32 v166, v88 + v_cvt_f16_f32_e32 v167, v87 + v_cvt_f16_f32_e32 v168, v86 + v_cvt_f16_f32_e32 v169, v85 + v_cvt_f16_f32_e32 v170, v84 + v_cvt_f16_f32_e32 v171, v83 + v_cvt_f16_f32_e32 v172, v82 + v_cvt_f16_f32_e32 v173, v81 + v_cvt_f16_f32_e32 v174, v80 + v_cvt_f16_f32_e32 v175, v79 + v_cvt_f16_f32_e32 v176, v78 + v_cvt_f16_f32_e32 v177, v77 + v_cvt_f16_f32_e32 v77, v161 + v_cvt_f16_f32_e32 v78, v160 + v_cvt_f16_f32_e32 v79, v159 + v_cvt_f16_f32_e32 v80, v158 + v_cvt_f16_f32_e32 v81, v157 + v_cvt_f16_f32_e32 v82, v156 + v_cvt_f16_f32_e32 v83, v155 + v_cvt_f16_f32_e32 v84, v154 + v_cvt_f16_f32_e32 v85, v153 + v_cvt_f16_f32_e32 v86, v152 + v_cvt_f16_f32_e32 v87, v151 + v_cvt_f16_f32_e32 v88, v150 + v_cvt_f16_f32_e32 v89, v149 + v_cvt_f16_f32_e32 v90, v148 + v_cvt_f16_f32_e32 v91, v145 + v_cvt_f16_f32_e32 v92, v144 + v_cvt_f16_f32_e32 v130, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v132, v74 + v_cvt_f16_f32_e32 v133, v73 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v129 + v_cvt_f16_f32_e32 v149, v128 + v_cvt_f16_f32_e32 v150, v127 + v_cvt_f16_f32_e32 v151, v126 + v_cvt_f16_f32_e32 v152, v125 + v_cvt_f16_f32_e32 v153, v124 + v_cvt_f16_f32_e32 v154, v123 + v_cvt_f16_f32_e32 v155, v122 + v_cvt_f16_f32_e32 v156, v121 + v_cvt_f16_f32_e32 v157, v120 + v_cvt_f16_f32_e32 v158, v119 + v_cvt_f16_f32_e32 v159, v118 + v_cvt_f16_f32_e32 v160, v117 + v_cvt_f16_f32_e32 v161, v116 + v_cvt_f16_f32_e32 v208, v208 + v_cvt_f16_f32_e32 v76, v207 + v_cvt_f16_f32_e32 v206, v206 + v_cvt_f16_f32_e32 v74, v205 + v_cvt_f16_f32_e32 v73, v204 + v_cvt_f16_f32_e32 v71, v203 + v_cvt_f16_f32_e32 v70, v202 + v_cvt_f16_f32_e32 v69, v201 + v_cvt_f16_f32_e32 v68, v200 + v_cvt_f16_f32_e32 v67, v199 + v_cvt_f16_f32_e32 v66, v198 + v_cvt_f16_f32_e32 v61, v197 + v_cvt_f16_f32_e32 v62, v196 + v_cvt_f16_f32_e32 v63, v195 + v_cvt_f16_f32_e32 v64, v194 + v_cvt_f16_f32_e32 v65, v1 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v3, v3 + v_cvt_f16_f32_e32 v116, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + scratch_load_dword v1, off, off offset:8 ; 4-byte Folded Reload + s_waitcnt vmcnt(0) + v_lshlrev_b32_e32 v20, 1, v1 + v_cvt_f16_f32_e32 v194, v115 + v_cvt_f16_f32_e32 v195, v114 + v_cvt_f16_f32_e32 v196, v113 + v_cvt_f16_f32_e32 v197, v112 + v_cvt_f16_f32_e32 v198, v111 + v_cvt_f16_f32_e32 v199, v110 + v_cvt_f16_f32_e32 v109, v109 + v_cvt_f16_f32_e32 v200, v72 + v_cvt_f16_f32_e32 v201, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v203, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v44, v44 + v_cvt_f16_f32_e32 v47, v43 + v_cvt_f16_f32_e32 v48, v42 + v_cvt_f16_f32_e32 v49, v193 + v_cvt_f16_f32_e32 v72, v192 + v_cvt_f16_f32_e32 v110, v191 + v_cvt_f16_f32_e32 v111, v190 + v_cvt_f16_f32_e32 v112, v189 + v_cvt_f16_f32_e32 v113, v188 + v_cvt_f16_f32_e32 v114, v187 + v_cvt_f16_f32_e32 v115, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v183, v183 + v_cvt_f16_f32_e32 v182, v182 + v_cvt_f16_f32_e32 v181, v181 + v_cvt_f16_f32_e32 v180, v180 + v_cvt_f16_f32_e32 v179, v179 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v43, v59 + v_cvt_f16_f32_e32 v4, v58 + v_cvt_f16_f32_e32 v5, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v225 + v_lshlrev_b32_e32 v21, 3, v226 + v_lshrrev_b32_e32 v1, 1, v226 + scratch_load_dword v207, off, off ; 4-byte Folded Reload + s_cbranch_scc1 .LBB41_14 +; %bb.12: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB41_15 +.LBB41_13: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SB_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB41_14: + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s2, v207 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_add_u32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v227 offset:3456 + ds_write_b16 v23, v228 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v204, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v108 + ds_write_b16 v23, v107 offset:128 + ds_write_b16 v23, v106 offset:256 + ds_write_b16 v23, v105 offset:384 + ds_write_b16 v23, v104 offset:1024 + ds_write_b16 v23, v103 offset:1152 + ds_write_b16 v23, v102 offset:1280 + ds_write_b16 v23, v101 offset:1408 + ds_write_b16 v23, v100 offset:2048 + ds_write_b16 v23, v99 offset:2176 + ds_write_b16 v23, v98 offset:2304 + ds_write_b16 v23, v97 offset:2432 + ds_write_b16 v23, v96 offset:3072 + ds_write_b16 v23, v95 offset:3200 + ds_write_b16 v23, v94 offset:3328 + ds_write_b16 v23, v209 offset:3456 + ds_write_b16 v23, v210 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v93 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v204, v31, v41 + v_lshlrev_b32_e32 v205, 1, v204 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v204 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v177 offset:3456 + ds_write_b16 v23, v77 offset:8192 + ds_write_b16 v23, v78 offset:8320 + ds_write_b16 v23, v79 offset:8448 + ds_write_b16 v23, v80 offset:8576 + ds_write_b16 v23, v81 offset:9216 + ds_write_b16 v23, v82 offset:9344 + ds_write_b16 v23, v83 offset:9472 + ds_write_b16 v23, v84 offset:9600 + ds_write_b16 v23, v85 offset:10240 + ds_write_b16 v23, v86 offset:10368 + ds_write_b16 v23, v87 offset:10496 + ds_write_b16 v23, v88 offset:10624 + ds_write_b16 v23, v89 offset:11264 + ds_write_b16 v23, v90 offset:11392 + ds_write_b16 v23, v91 offset:11520 + ds_write_b16 v23, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v204, 0x80, v25 + v_add_u32_e32 v205, v31, v204 + v_mov_b32_e32 v225, v206 + v_lshlrev_b32_e32 v206, 1, v205 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v205 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v130 + ds_write_b16 v23, v75 offset:128 + ds_write_b16 v23, v132 offset:256 + ds_write_b16 v23, v133 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v205, 0xc0, v25 + v_add_u32_e32 v31, v31, v205 + v_lshlrev_b32_e32 v206, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v206, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v206, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v206, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v206, s[0:3], 12 offen + v_mov_b32_e32 v206, v225 + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v208 + ds_write_b16 v23, v76 offset:128 + ds_write_b16 v23, v225 offset:256 + ds_write_b16 v23, v74 offset:384 + ds_write_b16 v23, v73 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v66 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v3 offset:8320 + ds_write_b16 v23, v116 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v205 + v_lshlrev_b32_e32 v205, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v205, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v205, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v205, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v205, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v194 + ds_write_b16 v23, v195 offset:128 + ds_write_b16 v23, v196 offset:256 + ds_write_b16 v23, v197 offset:384 + ds_write_b16 v23, v198 offset:1024 + ds_write_b16 v23, v199 offset:1152 + ds_write_b16 v23, v109 offset:1280 + ds_write_b16 v23, v200 offset:1408 + ds_write_b16 v23, v201 offset:2048 + ds_write_b16 v23, v202 offset:2176 + ds_write_b16 v23, v203 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v44 offset:3200 + ds_write_b16 v23, v47 offset:3328 + ds_write_b16 v23, v48 offset:3456 + ds_write_b16 v23, v49 offset:8192 + ds_write_b16 v23, v72 offset:8320 + ds_write_b16 v23, v110 offset:8448 + ds_write_b16 v23, v111 offset:8576 + ds_write_b16 v23, v112 offset:9216 + ds_write_b16 v23, v113 offset:9344 + ds_write_b16 v23, v114 offset:9472 + ds_write_b16 v23, v115 offset:9600 + ds_write_b16 v23, v185 offset:10240 + ds_write_b16 v23, v184 offset:10368 + ds_write_b16 v23, v183 offset:10496 + ds_write_b16 v23, v182 offset:10624 + ds_write_b16 v23, v181 offset:11264 + ds_write_b16 v23, v180 offset:11392 + ds_write_b16 v23, v179 offset:11520 + ds_write_b16 v23, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v204 + v_lshlrev_b32_e32 v204, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v204, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v204, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v204, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v204, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v43 offset:128 + ds_write_b16 v23, v4 offset:256 + ds_write_b16 v23, v5 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a71 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a70 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a69 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a68 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a67 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a66 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a65 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a64 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[186:189], v24 offset:256 + ds_read_b128 v[190:193], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v186, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v187, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v190, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v191, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v192, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v193, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB41_13 +.LBB41_15: + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s2, v207 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_add_u32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v227 offset:3456 + ds_write_b16 v31, v228 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v41, s18, v1 + v_or_b32_e32 v186, s19, v0 + v_mul_lo_u32 v0, v41, s16 + v_add_u32_e32 v1, v0, v186 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v187, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v187, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v108 + ds_write_b16 v31, v107 offset:128 + ds_write_b16 v31, v106 offset:256 + ds_write_b16 v31, v105 offset:384 + ds_write_b16 v31, v104 offset:1024 + ds_write_b16 v31, v103 offset:1152 + ds_write_b16 v31, v102 offset:1280 + ds_write_b16 v31, v101 offset:1408 + ds_write_b16 v31, v100 offset:2048 + ds_write_b16 v31, v99 offset:2176 + ds_write_b16 v31, v98 offset:2304 + ds_write_b16 v31, v97 offset:2432 + ds_write_b16 v31, v96 offset:3072 + ds_write_b16 v31, v95 offset:3200 + ds_write_b16 v31, v94 offset:3328 + ds_write_b16 v31, v209 offset:3456 + ds_write_b16 v31, v210 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v93 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v186 + v_add_u32_e32 v1, v0, v93 + v_lshlrev_b32_e32 v94, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v94, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v177 offset:3456 + ds_write_b16 v31, v77 offset:8192 + ds_write_b16 v31, v78 offset:8320 + ds_write_b16 v31, v79 offset:8448 + ds_write_b16 v31, v80 offset:8576 + ds_write_b16 v31, v81 offset:9216 + ds_write_b16 v31, v82 offset:9344 + ds_write_b16 v31, v83 offset:9472 + ds_write_b16 v31, v84 offset:9600 + ds_write_b16 v31, v85 offset:10240 + ds_write_b16 v31, v86 offset:10368 + ds_write_b16 v31, v87 offset:10496 + ds_write_b16 v31, v88 offset:10624 + ds_write_b16 v31, v89 offset:11264 + ds_write_b16 v31, v90 offset:11392 + ds_write_b16 v31, v91 offset:11520 + ds_write_b16 v31, v92 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v77, 0x80, v186 + v_add_u32_e32 v1, v0, v77 + v_lshlrev_b32_e32 v78, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v130 + ds_write_b16 v31, v75 offset:128 + ds_write_b16 v31, v132 offset:256 + ds_write_b16 v31, v133 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v78, 0xc0, v186 + v_add_u32_e32 v0, v0, v78 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v208 + ds_write_b16 v31, v76 offset:128 + ds_write_b16 v31, v206 offset:256 + ds_write_b16 v31, v74 offset:384 + ds_write_b16 v31, v73 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v66 offset:2304 + ds_write_b16 v31, v61 offset:2432 + ds_write_b16 v31, v62 offset:3072 + ds_write_b16 v31, v63 offset:3200 + ds_write_b16 v31, v64 offset:3328 + ds_write_b16 v31, v65 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v3 offset:8320 + ds_write_b16 v31, v116 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[18:21], v40 offset:128 + ds_read_b128 v[22:25], v40 offset:256 + ds_read_b128 v[32:35], v40 offset:384 + v_add_u32_e32 v36, 0x80, v41 + v_mul_lo_u32 v36, v36, s16 + v_add_u32_e32 v37, v36, v78 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v194 + ds_write_b16 v31, v195 offset:128 + ds_write_b16 v31, v196 offset:256 + ds_write_b16 v31, v197 offset:384 + ds_write_b16 v31, v198 offset:1024 + ds_write_b16 v31, v199 offset:1152 + ds_write_b16 v31, v109 offset:1280 + ds_write_b16 v31, v200 offset:1408 + ds_write_b16 v31, v201 offset:2048 + ds_write_b16 v31, v202 offset:2176 + ds_write_b16 v31, v203 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v44 offset:3200 + ds_write_b16 v31, v47 offset:3328 + ds_write_b16 v31, v48 offset:3456 + ds_write_b16 v31, v49 offset:8192 + ds_write_b16 v31, v72 offset:8320 + ds_write_b16 v31, v110 offset:8448 + ds_write_b16 v31, v111 offset:8576 + ds_write_b16 v31, v112 offset:9216 + ds_write_b16 v31, v113 offset:9344 + ds_write_b16 v31, v114 offset:9472 + ds_write_b16 v31, v115 offset:9600 + ds_write_b16 v31, v185 offset:10240 + ds_write_b16 v31, v184 offset:10368 + ds_write_b16 v31, v183 offset:10496 + ds_write_b16 v31, v182 offset:10624 + ds_write_b16 v31, v181 offset:11264 + ds_write_b16 v31, v180 offset:11392 + ds_write_b16 v31, v179 offset:11520 + ds_write_b16 v31, v178 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[18:21], v40 offset:128 + ds_read_b128 v[22:25], v40 offset:256 + ds_read_b128 v[32:35], v40 offset:384 + v_add_u32_e32 v37, v36, v77 + v_lshlrev_b32_e32 v38, 1, v37 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v38, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v37 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v43 offset:128 + ds_write_b16 v31, v4 offset:256 + ds_write_b16 v31, v5 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v36, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a71 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a70 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a69 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a68 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a67 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a66 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a65 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a64 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a55 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a54 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a53 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a52 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a51 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a50 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a49 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v36, v186 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 49152 + .amdhsa_private_segment_fixed_size 16 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end41: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end41-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 27 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 16 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 32444 +; TotalNumSgprs: 33 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 16 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 49152 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v4, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v4 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB42_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v4, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB42_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v1, v0, s2 + s_mov_b32 s0, 0 + v_mov_b32_e32 v5, 0 + v_mov_b32_e32 v2, v4 +.LBB42_3: ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v3, s0, v1 + v_lshrrev_b32_e32 v6, 31, v3 + v_add_u32_e32 v3, v3, v6 + v_ashrrev_i32_e32 v6, 1, v3 + v_ashrrev_i32_e32 v7, 31, v6 + v_lshl_add_u64 v[6:7], s[10:11], 0, v[6:7] + global_load_ubyte v8, v[6:7], off + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[6:7], v[2:3], 1, s[8:9] + global_load_ushort v3, v[6:7], off + s_bitcmp0_b32 s0, 0 + s_waitcnt vmcnt(1) + v_and_b32_e32 v6, 15, v8 + v_lshrrev_b32_e32 v7, 4, v8 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v6, v6, v7, vcc + v_add_u32_e32 v6, -8, v6 + v_cvt_f32_i32_e32 v6, v6 + v_add_u32_e32 v2, s7, v2 + s_add_i32 s0, s0, 1 + s_cmp_eq_u32 s6, s0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v5, v3, v6, v5 op_sel_hi:[1,0,0] + s_cbranch_scc0 .LBB42_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v5 +.LBB42_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v4, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB42_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 9 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end42: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii, .Lfunc_end42-_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_vgpr, 9 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 468 +; TotalNumSgprs: 20 +; NumVgprs: 9 +; NumAgprs: 0 +; TotalNumVgprs: 9 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 9 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat + .protected _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ ; -- Begin function _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .globl _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .p2align 8 + .type _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,@function +_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_: ; @_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ +; %bb.0: + v_mov_b32_e32 v117, v0 + s_load_dwordx4 s[4:7], s[0:1], 0x20 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_waitcnt lgkmcnt(0) + s_add_i32 s12, s5, 0xff + s_ashr_i32 s13, s12, 31 + s_lshr_b32 s13, s13, 24 + s_add_i32 s12, s12, s13 + s_ashr_i32 s14, s12, 8 + s_abs_i32 s15, s14 + v_cvt_f32_u32_e32 v0, s15 + s_load_dword s20, s[0:1], 0x30 + s_load_dwordx2 s[16:17], s[0:1], 0x38 + s_getpc_b64 s[12:13] + s_add_u32 s12, s12, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@lo+4 + s_addc_u32 s13, s13, _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E@rel32@hi+12 + v_mov_b32_e32 v1, 0 + v_rcp_iflag_f32_e32 v0, v0 + v_mov_b32_e32 v2, s5 + global_store_dword v1, v2, s[12:13] + s_xor_b32 s12, s2, s14 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s12, s12, 31 + s_abs_i32 s13, s2 + s_sub_i32 s18, 0, s15 + v_readfirstlane_b32 s19, v0 + s_mul_i32 s18, s18, s19 + s_mul_hi_u32 s18, s19, s18 + s_add_i32 s19, s19, s18 + s_mul_hi_u32 s18, s13, s19 + s_mul_i32 s19, s18, s15 + s_sub_i32 s13, s13, s19 + s_add_i32 s19, s18, 1 + s_sub_i32 s21, s13, s15 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s18, s19, s18 + s_cselect_b32 s13, s21, s13 + s_add_i32 s19, s18, 1 + s_cmp_ge_u32 s13, s15 + s_cselect_b32 s13, s19, s18 + s_xor_b32 s13, s13, s12 + s_sub_i32 s12, s13, s12 + s_mul_i32 s13, s12, s14 + s_lshl_b32 s18, s12, 8 + s_waitcnt lgkmcnt(0) + s_abs_i32 s12, s17 + v_cvt_f32_u32_e32 v0, s12 + s_sub_i32 s2, s2, s13 + s_lshl_b32 s19, s2, 8 + s_ashr_i32 s2, s6, 31 + v_rcp_iflag_f32_e32 v0, v0 + s_lshr_b32 s2, s2, 28 + s_add_i32 s2, s6, s2 + s_ashr_i32 s13, s2, 4 + v_mul_f32_e32 v0, 0x4f7ffffe, v0 + v_cvt_u32_f32_e32 v0, v0 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s14, s13 + s_sub_i32 s15, 0, s12 + v_readfirstlane_b32 s21, v0 + s_mul_i32 s15, s15, s21 + s_mul_hi_u32 s15, s21, s15 + s_add_i32 s21, s21, s15 + s_mul_hi_u32 s15, s14, s21 + s_mul_i32 s15, s15, s12 + s_sub_i32 s14, s14, s15 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_sub_i32 s15, s14, s12 + s_cmp_ge_u32 s14, s12 + s_cselect_b32 s14, s15, s14 + s_xor_b32 s14, s14, s2 + s_sub_i32 s2, s14, s2 + s_cmp_eq_u32 s2, 0 + s_cselect_b32 s14, s17, s2 + s_add_i32 s15, s17, -1 + s_add_i32 s13, s13, s15 + s_xor_b32 s2, s13, s17 + s_ashr_i32 s2, s2, 31 + s_abs_i32 s13, s13 + s_mul_hi_u32 s21, s13, s21 + s_mul_i32 s22, s21, s12 + s_sub_i32 s13, s13, s22 + s_add_i32 s22, s21, 1 + s_sub_i32 s23, s13, s12 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s21, s22, s21 + s_cselect_b32 s13, s23, s13 + s_add_i32 s22, s21, 1 + s_cmp_ge_u32 s13, s12 + s_cselect_b32 s12, s22, s21 + s_xor_b32 s12, s12, s2 + s_sub_i32 s2, s12, s2 + s_max_i32 s2, s2, 1 + s_lshl_b32 s12, s2, 4 + s_add_i32 s13, s12, -16 + s_min_i32 s2, s14, s3 + s_mul_i32 s2, s12, s2 + s_sub_i32 s21, s3, s14 + s_max_i32 s21, s21, 0 + s_mul_i32 s21, s13, s21 + s_add_i32 s2, s21, s2 + s_sub_i32 s6, s6, s2 + s_cmp_lt_i32 s3, s14 + s_cselect_b32 s12, s12, s13 + s_cmp_eq_u32 s3, s15 + s_cselect_b32 s6, s6, s12 + s_ashr_i32 s3, s2, 31 + s_lshl_b64 s[12:13], s[2:3], 1 + s_add_u32 s8, s8, s12 + s_addc_u32 s9, s9, s13 + s_add_u32 s12, s10, s2 + s_addc_u32 s13, s11, s3 + s_add_i32 s4, s4, -1 + s_mul_i32 s2, s7, s4 + s_add_i32 s3, s6, -1 + s_ashr_i32 s10, s3, 31 + s_add_u32 s3, s3, 1 + s_addc_u32 s10, s10, 0 + s_add_u32 s21, s2, s3 + s_add_i32 s2, s5, -1 + s_mul_i32 s2, s20, s2 + s_ashr_i32 s11, s2, 31 + s_add_u32 s2, s2, s3 + s_addc_u32 s3, s11, s10 + s_lshr_b32 s10, s3, 31 + s_add_u32 s2, s2, s10 + s_addc_u32 s3, s3, 0 + s_ashr_i64 s[14:15], s[2:3], 1 + s_add_i32 s6, s6, 63 + s_movk_i32 s23, 0x80 + s_cmpk_lt_i32 s6, 0x80 + s_cselect_b64 s[2:3], -1, 0 + s_cmpk_gt_i32 s6, 0x7f + s_cselect_b64 s[10:11], -1, 0 + v_cndmask_b32_e64 v0, 0, 1, s[10:11] + s_nop 0 + v_readfirstlane_b32 s10, v0 + s_bitcmp0_b32 s10, 0 + v_mbcnt_lo_u32_b32 v38, -1, 0 + s_cbranch_scc0 .LBB43_2 +; %bb.1: + v_readfirstlane_b32 s15, v117 + v_mbcnt_hi_u32_b32 v17, -1, v38 + v_and_b32_e32 v74, 7, v17 + v_lshlrev_b32_e32 v0, 3, v74 + v_and_b32_e32 v2, 0x78, v17 + s_and_b32 s22, s15, 0xffffffc0 + v_add_u32_e32 v39, s22, v2 + v_add_u32_e32 v2, s18, v39 + v_mad_u64_u32 v[2:3], s[10:11], v2, s7, v[0:1] + s_lshl_b32 s10, s21, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v10, 1, v2 + v_add_u32_e32 v11, s7, v2 + v_lshlrev_b32_e32 v12, 1, v11 + buffer_load_dwordx4 v[2:5], v10, s[8:11], 0 offen + buffer_load_dwordx4 v[6:9], v12, s[8:11], 0 offen + v_add_u32_e32 v14, s7, v11 + v_lshlrev_b32_e32 v10, 1, v14 + buffer_load_dwordx4 v[10:13], v10, s[8:11], 0 offen + v_and_b32_e32 v15, 31, v17 + s_lshr_b32 s24, s15, 2 + v_lshrrev_b32_e32 v44, 5, v17 + s_lshr_b32 s25, s15, 1 + v_lshlrev_b32_e32 v16, 3, v17 + s_mov_b32 s15, s11 + s_and_b32 s24, s24, 0x3ffffe0 + v_xor_b32_e32 v45, v44, v74 + v_mov_b32_e32 v1, v17 + v_add_u32_e32 v46, s22, v17 + s_and_b32 s22, s25, 32 + v_and_or_b32 v75, v16, 8, v44 + v_or_b32_e32 v47, s24, v15 + v_add_u32_e32 v18, s19, v46 + v_or_b32_e32 v34, s22, v15 + v_lshl_or_b32 v0, v39, 6, v0 + v_add_u32_e32 v19, s7, v14 + v_lshlrev_b32_e32 v14, 1, v19 + buffer_load_dwordx4 v[14:17], v14, s[8:11], 0 offen + v_or_b32_e32 v40, 1, v39 + v_ashrrev_i32_e32 v35, 31, v39 + v_or_b32_e32 v41, 2, v39 + v_or_b32_e32 v42, 3, v39 + v_lshlrev_b32_e32 v48, 6, v47 + v_mul_lo_u32 v36, v18, s20 + v_lshrrev_b32_e32 v100, 1, v34 + v_add_u32_e32 v18, s7, v19 + v_lshlrev_b32_e32 v19, 1, v18 + v_add_u32_e32 v22, s7, v18 + buffer_load_dwordx4 v[18:21], v19, s[8:11], 0 offen + v_lshlrev_b32_e32 v23, 1, v22 + v_add_u32_e32 v26, s7, v22 + buffer_load_dwordx4 v[22:25], v23, s[8:11], 0 offen + v_lshlrev_b32_e32 v37, 1, v26 + v_add_lshl_u32 v43, v26, s7, 1 + buffer_load_dwordx4 v[26:29], v37, s[8:11], 0 offen + buffer_load_dwordx4 v[30:33], v43, s[8:11], 0 offen + v_bfe_u32 v101, v34, 1, 4 + v_lshlrev_b32_e32 v49, 1, v0 + v_lshrrev_b32_e32 v50, 29, v35 + v_xor_b32_e32 v102, v101, v75 + v_lshlrev_b32_e32 v103, 7, v100 + v_lshrrev_b32_e32 v34, 31, v36 + v_add_u32_e32 v35, v40, v50 + v_add_u32_e32 v37, v41, v50 + v_add_u32_e32 v43, v42, v50 + v_lshl_or_b32 v104, v102, 3, v103 + v_add_u32_e32 v34, v36, v34 + v_and_b32_e32 v51, -8, v35 + v_and_b32_e32 v52, -8, v37 + v_and_b32_e32 v43, -8, v43 + v_ashrrev_i32_e32 v53, 1, v34 + buffer_load_dwordx4 v[34:37], v53, s[12:15], 0 offen + v_sub_u32_e32 v51, v40, v51 + v_sub_u32_e32 v52, v41, v52 + v_sub_u32_e32 v54, v42, v43 + buffer_load_dwordx4 v[40:43], v53, s[12:15], 16 offen + v_xor_b32_e32 v51, v51, v74 + v_xor_b32_e32 v52, v52, v74 + v_xor_b32_e32 v53, v54, v74 + v_sub_u32_e32 v54, v51, v74 + v_sub_u32_e32 v51, v52, v51 + v_sub_u32_e32 v52, v53, v52 + v_lshlrev_b32_e32 v55, 3, v54 + v_lshlrev_b32_e32 v56, 3, v51 + v_lshl_add_u32 v54, v54, 4, v49 + v_add3_u32 v0, v55, v0, v56 + s_waitcnt vmcnt(9) + ds_write_b128 v49, v[2:5] + s_waitcnt vmcnt(8) + ds_write_b128 v54, v[6:9] offset:128 + v_lshlrev_b32_e32 v2, 3, v52 + v_or_b32_e32 v3, 4, v39 + v_add_u32_e32 v4, v3, v50 + v_and_b32_e32 v4, -8, v4 + v_sub_u32_e32 v3, v3, v4 + v_xor_b32_e32 v3, v3, v74 + v_sub_u32_e32 v4, v3, v53 + v_lshlrev_b32_e32 v5, 3, v4 + v_add3_u32 v0, v0, v2, v5 + v_lshlrev_b32_e32 v2, 4, v51 + v_add3_u32 v2, v54, s23, v2 + s_waitcnt vmcnt(7) + ds_write_b128 v2, v[10:13] offset:128 + v_or_b32_e32 v5, 5, v39 + v_add_u32_e32 v6, v5, v50 + v_and_b32_e32 v6, -8, v6 + v_sub_u32_e32 v5, v5, v6 + v_xor_b32_e32 v5, v5, v74 + v_sub_u32_e32 v3, v5, v3 + v_lshlrev_b32_e32 v6, 3, v3 + v_or_b32_e32 v7, 6, v39 + v_add_u32_e32 v8, v7, v50 + v_and_b32_e32 v8, -8, v8 + v_sub_u32_e32 v7, v7, v8 + v_xor_b32_e32 v7, v7, v74 + v_sub_u32_e32 v5, v7, v5 + v_lshlrev_b32_e32 v8, 3, v5 + v_add3_u32 v0, v0, v6, v8 + v_lshlrev_b32_e32 v6, 4, v52 + v_add3_u32 v2, v2, s23, v6 + s_waitcnt vmcnt(6) + ds_write_b128 v2, v[14:17] offset:128 + v_or_b32_e32 v6, 7, v39 + v_add_u32_e32 v8, v6, v50 + v_and_b32_e32 v8, 0xffffff8, v8 + v_sub_u32_e32 v6, v6, v8 + v_xor_b32_e32 v6, v6, v74 + v_sub_u32_e32 v6, v6, v7 + v_lshlrev_b32_e32 v6, 4, v6 + v_lshl_add_u32 v0, v0, 1, v6 + v_lshlrev_b32_e32 v4, 4, v4 + v_add3_u32 v2, v2, s23, v4 + s_waitcnt vmcnt(5) + ds_write_b128 v2, v[18:21] offset:128 + v_lshlrev_b32_e32 v3, 4, v3 + v_add3_u32 v2, v2, s23, v3 + s_waitcnt vmcnt(4) + ds_write_b128 v2, v[22:25] offset:128 + v_lshlrev_b32_e32 v3, 4, v5 + v_add3_u32 v2, v2, s23, v3 + s_waitcnt vmcnt(3) + ds_write_b128 v2, v[26:29] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v0, v[30:33] offset:896 + v_lshrrev_b32_e32 v0, 31, v46 + v_add_u32_e32 v0, v46, v0 + v_ashrrev_i32_e32 v2, 1, v0 + v_and_b32_e32 v3, 0x1ffffffe, v0 + v_sub_u32_e32 v3, v46, v3 + v_lshlrev_b32_e32 v3, 3, v3 + v_ashrrev_i32_e32 v0, 31, v0 + v_lshrrev_b32_e32 v0, 28, v0 + v_add_u32_e32 v0, v2, v0 + v_and_b32_e32 v0, -16, v0 + v_sub_u32_e32 v0, v2, v0 + v_xor_b32_e32 v4, v3, v0 + v_lshlrev_b32_e32 v2, 7, v2 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + s_waitcnt vmcnt(1) + ds_write_b32 v4, v34 offset:32768 + v_or_b32_e32 v4, 1, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + ds_write_b32 v4, v35 offset:32768 + v_or_b32_e32 v4, 2, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + ds_write_b32 v4, v36 offset:32768 + v_or_b32_e32 v4, 3, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + ds_write_b32 v4, v37 offset:32768 + v_or_b32_e32 v4, 4, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + s_waitcnt vmcnt(0) + ds_write_b32 v4, v40 offset:32768 + v_or_b32_e32 v4, 5, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + ds_write_b32 v4, v41 offset:32768 + v_or_b32_e32 v4, 6, v3 + v_xor_b32_e32 v4, v4, v0 + v_lshl_add_u32 v4, v4, 3, v2 + v_ashrrev_i32_e32 v4, 1, v4 + ds_write_b32 v4, v42 offset:32768 + v_or_b32_e32 v3, 7, v3 + v_xor_b32_e32 v0, v3, v0 + v_lshl_add_u32 v0, v0, 3, v2 + v_ashrrev_i32_e32 v0, 1, v0 + ds_write_b32 v0, v43 offset:32768 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 7, v47 + v_lshl_or_b32 v2, v45, 4, v0 + v_add_u32_e32 v3, 2, v44 + v_xor_b32_e32 v3, v3, v74 + v_lshl_or_b32 v4, v3, 4, v0 + ds_read_b128 v[96:99], v2 + ds_read_b128 v[80:83], v4 + v_or_b32_e32 v2, 4, v44 + v_xor_b32_e32 v2, v2, v74 + v_lshl_or_b32 v4, v2, 4, v0 + v_add_u32_e32 v5, 6, v44 + v_xor_b32_e32 v5, v5, v74 + v_lshl_add_u32 v6, v5, 3, v48 + v_lshl_add_u32 v0, v5, 4, v0 + ds_read_b128 v[62:65], v4 + ds_read_b128 v[46:49], v0 + v_sub_u32_e32 v0, v45, v5 + v_lshlrev_b32_e32 v0, 4, v0 + v_lshl_add_u32 v4, v6, 1, v0 + v_sub_u32_e32 v3, v3, v45 + v_lshl_add_u32 v3, v3, 4, v4 + ds_read_b128 v[118:121], v4 offset:8192 + ds_read_b128 v[84:87], v3 offset:8192 + v_sub_u32_e32 v2, v2, v45 + v_lshl_add_u32 v2, v2, 4, v4 + v_sub_u32_e32 v5, v5, v45 + v_lshl_add_u32 v4, v5, 4, v4 + v_add_u32_e32 v0, v4, v0 + ds_read_b128 v[70:73], v2 offset:8192 + ds_read_b128 v[66:69], v2 offset:16384 + ds_read_b128 v[122:125], v0 offset:16384 + ds_read_b128 v[126:129], v0 offset:24576 + ds_read_b128 v[92:95], v3 offset:16384 + ds_read_b128 v[88:91], v3 offset:24576 + ds_read_b128 v[58:61], v4 offset:8192 + ds_read_b128 v[76:79], v2 offset:24576 + ds_read_b128 v[54:57], v4 offset:16384 + ds_read_b128 v[50:53], v4 offset:24576 + v_lshrrev_b32_e32 v0, 1, v104 + v_add_u32_e32 v2, 2, v75 + v_add_u32_e32 v3, -16, v100 + s_cmp_eq_u32 s22, 0 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v3, v3, v100, vcc + v_xor_b32_e32 v4, v3, v2 + v_lshl_add_u32 v4, v4, 3, v103 + v_ashrrev_i32_e32 v4, 1, v4 + v_or_b32_e32 v5, 4, v75 + v_xor_b32_e32 v6, v3, v5 + v_lshl_add_u32 v6, v6, 3, v103 + v_ashrrev_i32_e32 v6, 1, v6 + v_add_u32_e32 v7, 6, v75 + v_xor_b32_e32 v3, v3, v7 + v_lshl_add_u32 v8, v3, 3, v103 + v_ashrrev_i32_e32 v9, 1, v8 + v_sub_u32_e32 v3, v102, v3 + v_lshlrev_b32_e32 v3, 3, v3 + s_movk_i32 s10, 0x1000 + v_add3_u32 v3, v3, v8, s10 + v_ashrrev_i32_e32 v8, 1, v3 + v_xor_b32_e32 v2, v101, v2 + v_sub_u32_e32 v2, v2, v102 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v10, v3, v2 + v_ashrrev_i32_e32 v10, 1, v10 + v_xor_b32_e32 v5, v101, v5 + v_sub_u32_e32 v5, v5, v102 + v_lshlrev_b32_e32 v5, 3, v5 + v_add_u32_e32 v11, v3, v5 + v_ashrrev_i32_e32 v11, 1, v11 + v_xor_b32_e32 v7, v101, v7 + v_sub_u32_e32 v12, v7, v102 + v_lshlrev_b32_e32 v12, 3, v12 + v_add_u32_e32 v3, v3, v12 + v_ashrrev_i32_e32 v13, 1, v3 + ds_read_b32 v14, v0 offset:32768 + ds_read_b32 v4, v4 offset:32768 + ds_read_b32 v6, v6 offset:32768 + ds_read_b32 v15, v9 offset:32768 + ds_read_b32 v20, v8 offset:32768 + ds_read_b32 v21, v10 offset:32768 + ds_read_b32 v30, v11 offset:32768 + ds_read_b32 v31, v13 offset:32768 + v_sub_u32_e32 v0, v102, v7 + v_mov_b32_e32 v7, 0x1000 + v_lshl_add_u32 v0, v0, 3, v7 + v_add_u32_e32 v3, v3, v0 + v_ashrrev_i32_e32 v7, 1, v3 + v_add_u32_e32 v8, v3, v2 + v_ashrrev_i32_e32 v8, 1, v8 + v_add_u32_e32 v9, v3, v5 + v_ashrrev_i32_e32 v9, 1, v9 + v_add_u32_e32 v3, v3, v12 + v_ashrrev_i32_e32 v10, 1, v3 + v_add_u32_e32 v0, v3, v0 + v_lshrrev_b32_e32 v3, 31, v0 + v_add_u32_e32 v3, v0, v3 + v_ashrrev_i32_e32 v3, 1, v3 + v_add_u32_e32 v2, v0, v2 + v_lshrrev_b32_e32 v11, 31, v2 + v_add_u32_e32 v2, v2, v11 + v_ashrrev_i32_e32 v2, 1, v2 + v_add_u32_e32 v5, v0, v5 + v_lshrrev_b32_e32 v11, 31, v5 + v_add_u32_e32 v5, v5, v11 + v_ashrrev_i32_e32 v5, 1, v5 + v_add_u32_e32 v0, v0, v12 + v_lshrrev_b32_e32 v11, 31, v0 + v_add_u32_e32 v0, v0, v11 + v_ashrrev_i32_e32 v0, 1, v0 + ds_read_b32 v32, v7 offset:32768 + ds_read_b32 v33, v8 offset:32768 + ds_read_b32 v45, v9 offset:32768 + ds_read_b32 v75, v10 offset:32768 + ds_read_b32 v114, v3 offset:32768 + ds_read_b32 v115, v2 offset:32768 + ds_read_b32 v116, v5 offset:32768 + ds_read_b32 v0, v0 offset:32768 + v_mov_b32_e32 v39, 0xf000f + v_mov_b32_e32 v40, 0x64006400 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v2, v14, v39, v40 + ;;#ASMEND + v_mov_b32_e32 v41, 0xf000f0 + ;;#ASMSTART + v_and_or_b32 v3, v14, v41, v40 + ;;#ASMEND + v_mov_b32_e32 v42, 0xe408e408 + ;;#ASMSTART + v_pk_add_f16 v26, v2, v42 + ;;#ASMEND + v_mov_b32_e32 v43, 0x2c002c00 + v_mov_b32_e32 v44, 0xd480d480 + ;;#ASMSTART + v_pk_fma_f16 v27, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v14 + ;;#ASMSTART + v_and_or_b32 v3, v2, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v3, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v2, v43, v44 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v4, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v4, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v4 + ;;#ASMSTART + v_and_or_b32 v3, v2, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v3, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v2, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(13) + ;;#ASMSTART + v_and_or_b32 v2, v6, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v6, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v6 + ;;#ASMSTART + v_and_or_b32 v3, v2, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v3, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v2, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(12) + ;;#ASMSTART + v_and_or_b32 v2, v15, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v15, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v2, v2, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v3, v3, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v4, 8, v15 + ;;#ASMSTART + v_and_or_b32 v5, v4, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v4, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v4, v5, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v5, v6, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v6, v20, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v20, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v34, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v35, v7, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v20 + ;;#ASMSTART + v_and_or_b32 v7, v6, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v36, v7, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v37, v6, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(10) + ;;#ASMSTART + v_and_or_b32 v6, v21, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v21, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v22, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v23, v7, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v21 + ;;#ASMSTART + v_and_or_b32 v7, v6, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v24, v7, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v25, v6, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(9) + ;;#ASMSTART + v_and_or_b32 v6, v30, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v30, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v12, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v13, v7, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v30 + ;;#ASMSTART + v_and_or_b32 v7, v6, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v14, v7, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v15, v6, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(8) + ;;#ASMSTART + v_and_or_b32 v6, v31, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v31, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v6, v6, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v7, v7, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v20, 8, v31 + ;;#ASMSTART + v_and_or_b32 v21, v20, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v20, v41, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[0:15], v[96:97], v[26:27], 0 + ;;#ASMSTART + v_pk_add_f16 v20, v21, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v30, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v30, v32, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v32, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v100, v30, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v101, v31, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v32 + v_mfma_f32_32x32x8_f16 a[0:15], v[98:99], v[28:29], a[0:15] + ;;#ASMSTART + v_and_or_b32 v31, v30, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v102, v31, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v103, v30, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(6) + ;;#ASMSTART + v_and_or_b32 v30, v33, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v33, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v104, v30, v42 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], v[96:97], v[34:35], 0 + ;;#ASMSTART + v_pk_fma_f16 v105, v31, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v33 + ;;#ASMSTART + v_and_or_b32 v31, v30, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v106, v31, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v107, v30, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(5) + ;;#ASMSTART + v_and_or_b32 v30, v45, v39, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], v[98:99], v[36:37], a[64:79] + ;;#ASMSTART + v_and_or_b32 v31, v45, v41, v40 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v108, v30, v42 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v109, v31, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v45 + ;;#ASMSTART + v_and_or_b32 v31, v30, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v110, v31, v42 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], v[96:97], v[100:101], 0 + ;;#ASMSTART + v_pk_fma_f16 v111, v30, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(4) + ;;#ASMSTART + v_and_or_b32 v30, v75, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v75, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v30, v30, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v31, v31, v43, v44 + ;;#ASMEND + v_ashrrev_i32_e32 v32, 8, v75 + ;;#ASMSTART + v_and_or_b32 v33, v32, v39, v40 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], v[98:99], v[102:103], a[144:159] + ;;#ASMSTART + v_and_or_b32 v45, v32, v41, v40 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v32, v33, v42 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v33, v45, v43, v44 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v45, v114, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v75, v114, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v112, v45, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v113, v75, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[96:97], v[112:113], 0 + v_ashrrev_i32_e32 v45, 8, v114 + ;;#ASMSTART + v_and_or_b32 v75, v45, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v45, v45, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v96, v75, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v97, v45, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[98:99], v[96:97], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[118:119], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[120:121], v[28:29], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[118:119], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[192:207], v[120:121], v[36:37], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[118:119], v[100:101], 0 + v_mfma_f32_32x32x8_f16 a[176:191], v[120:121], v[102:103], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[118:119], v[112:113], 0 + v_mfma_f32_32x32x8_f16 a[160:175], v[120:121], v[96:97], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[122:123], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[124:125], v[28:29], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[122:123], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[112:127], v[124:125], v[36:37], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[122:123], v[100:101], 0 + v_mfma_f32_32x32x8_f16 a[96:111], v[124:125], v[102:103], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[122:123], v[112:113], 0 + v_mfma_f32_32x32x8_f16 a[80:95], v[124:125], v[96:97], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[126:127], v[26:27], 0 + v_mfma_f32_32x32x8_f16 a[48:63], v[128:129], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[126:127], v[34:35], 0 + v_mfma_f32_32x32x8_f16 a[32:47], v[128:129], v[36:37], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[126:127], v[100:101], 0 + v_mfma_f32_32x32x8_f16 a[16:31], v[128:129], v[102:103], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[126:127], v[112:113], 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[128:129], v[96:97], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[80:81], v[16:17], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[82:83], v[18:19], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[80:81], v[22:23], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[82:83], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[80:81], v[104:105], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[82:83], v[106:107], a[144:159] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v26, v115, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v27, v115, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v26, v26, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v27, v27, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[80:81], v[26:27], a[208:223] + v_ashrrev_i32_e32 v28, 8, v115 + ;;#ASMSTART + v_and_or_b32 v29, v28, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v34, v28, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v29, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v34, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[82:83], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[84:85], v[16:17], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[86:87], v[18:19], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[84:85], v[22:23], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[86:87], v[24:25], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[84:85], v[104:105], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[86:87], v[106:107], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[84:85], v[26:27], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[86:87], v[28:29], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[92:93], v[16:17], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[94:95], v[18:19], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[92:93], v[22:23], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[94:95], v[24:25], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[92:93], v[104:105], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[94:95], v[106:107], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[92:93], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[94:95], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[88:89], v[16:17], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[90:91], v[18:19], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[88:89], v[22:23], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[90:91], v[24:25], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[88:89], v[104:105], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[90:91], v[106:107], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[88:89], v[26:27], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[90:91], v[28:29], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[62:63], v[8:9], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[64:65], v[10:11], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[62:63], v[12:13], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[64:65], v[14:15], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[62:63], v[108:109], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[64:65], v[110:111], a[144:159] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v16, v116, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v17, v116, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v16, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v17, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[62:63], v[16:17], a[208:223] + v_ashrrev_i32_e32 v18, 8, v116 + ;;#ASMSTART + v_and_or_b32 v19, v18, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v22, v18, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v19, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v22, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[64:65], v[18:19], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[70:71], v[8:9], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[72:73], v[10:11], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[70:71], v[12:13], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[72:73], v[14:15], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[70:71], v[108:109], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[72:73], v[110:111], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[70:71], v[16:17], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[72:73], v[18:19], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[66:67], v[8:9], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[68:69], v[10:11], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[66:67], v[12:13], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[68:69], v[14:15], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[66:67], v[108:109], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[68:69], v[110:111], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[66:67], v[16:17], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[68:69], v[18:19], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[76:77], v[8:9], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[78:79], v[10:11], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[76:77], v[12:13], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[78:79], v[14:15], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[76:77], v[108:109], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[78:79], v[110:111], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[76:77], v[16:17], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[78:79], v[18:19], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[46:47], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[48:49], v[4:5], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[46:47], v[6:7], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[48:49], v[20:21], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[46:47], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[48:49], v[32:33], a[144:159] + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v8, v0, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v9, v0, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v8, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v9, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[46:47], v[8:9], a[208:223] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v10, v0, v39, v40 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v0, v0, v41, v40 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v10, v42 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v0, v43, v44 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[48:49], v[10:11], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[58:59], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[60:61], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[58:59], v[6:7], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[60:61], v[20:21], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[58:59], v[30:31], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[60:61], v[32:33], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[58:59], v[8:9], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[60:61], v[10:11], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[54:55], v[2:3], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[56:57], v[4:5], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[54:55], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[56:57], v[20:21], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[54:55], v[30:31], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[56:57], v[32:33], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[54:55], v[8:9], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[56:57], v[10:11], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[50:51], v[2:3], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[52:53], v[4:5], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[50:51], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[52:53], v[20:21], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[50:51], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[52:53], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[50:51], v[8:9], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[52:53], v[10:11], a[240:255] + scratch_store_dword off, v117, off ; 4-byte Folded Spill + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, exec + s_cbranch_execz .LBB43_3 + s_branch .LBB43_11 +.LBB43_2: + ; implicit-def: $agpr31 + ; implicit-def: $agpr47 + ; implicit-def: $agpr63 + ; implicit-def: $agpr95 + ; implicit-def: $agpr111 + ; implicit-def: $agpr127 + ; implicit-def: $agpr143 + ; implicit-def: $agpr175 + ; implicit-def: $agpr191 + ; implicit-def: $agpr207 + ; implicit-def: $agpr239 + ; implicit-def: $agpr223 + ; implicit-def: $agpr159 + ; implicit-def: $agpr79 + ; implicit-def: $agpr15 + ; implicit-def: $agpr240_agpr241_agpr242_agpr243_agpr244_agpr245_agpr246_agpr247_agpr248_agpr249_agpr250_agpr251_agpr252_agpr253_agpr254_agpr255 + ; implicit-def: $vgpr1 + ; implicit-def: $vgpr74 + scratch_store_dword off, v117, off ; 4-byte Folded Spill + s_load_dwordx2 s[0:1], s[0:1], 0x18 + s_mov_b64 vcc, 0 +.LBB43_3: + scratch_load_dword v1, off, off ; 4-byte Folded Reload + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s15, v1 + v_mbcnt_hi_u32_b32 v192, -1, v38 + v_and_b32_e32 v74, 7, v192 + v_lshlrev_b32_e32 v90, 3, v74 + s_and_b32 s22, s15, 0xffffffc0 + v_and_b32_e32 v105, 0x78, v192 + v_add_u32_e32 v0, s22, v105 + v_add_u32_e32 v2, s18, v0 + v_mad_u64_u32 v[44:45], s[10:11], v2, s7, v[90:91] + s_lshl_b32 s10, s21, 1 + s_mov_b32 s11, 0x20000 + v_lshlrev_b32_e32 v2, 1, v44 + v_add_u32_e32 v3, s7, v44 + v_lshlrev_b32_e32 v4, 1, v3 + buffer_load_dwordx4 v[8:11], v2, s[8:11], 0 offen + buffer_load_dwordx4 v[12:15], v4, s[8:11], 0 offen + v_add_u32_e32 v2, s7, v3 + v_lshlrev_b32_e32 v3, 1, v2 + buffer_load_dwordx4 v[16:19], v3, s[8:11], 0 offen + v_lshrrev_b32_e32 v45, 5, v192 + v_and_b32_e32 v3, 31, v192 + s_lshr_b32 s21, s15, 2 + s_lshr_b32 s23, s15, 1 + v_lshlrev_b32_e32 v5, 3, v192 + s_mov_b32 s15, s11 + s_and_b32 s21, s21, 0x3ffffe0 + v_xor_b32_e32 v4, v45, v74 + v_add_u32_e32 v50, s22, v192 + v_and_or_b32 v6, s23, 32, v3 + v_and_or_b32 v51, v5, 8, v45 + v_or_b32_e32 v5, s21, v3 + v_add_u32_e32 v24, s19, v50 + v_lshrrev_b32_e32 v40, 1, v6 + v_bfe_u32 v3, v6, 1, 4 + v_add_u32_e32 v2, s7, v2 + v_lshlrev_b32_e32 v6, 1, v2 + buffer_load_dwordx4 v[20:23], v6, s[8:11], 0 offen + v_lshl_or_b32 v52, v0, 6, v90 + v_or_b32_e32 v41, 1, v0 + v_ashrrev_i32_e32 v42, 31, v0 + v_or_b32_e32 v46, 2, v0 + v_or_b32_e32 v47, 3, v0 + v_lshlrev_b32_e32 v7, 6, v5 + v_mul_lo_u32 v106, v24, s20 + v_add_u32_e32 v2, s7, v2 + v_lshlrev_b32_e32 v5, 1, v2 + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[24:27], v5, s[8:11], 0 offen + v_lshlrev_b32_e32 v5, 1, v2 + v_add_u32_e32 v2, s7, v2 + buffer_load_dwordx4 v[28:31], v5, s[8:11], 0 offen + v_lshlrev_b32_e32 v5, 1, v2 + v_add_lshl_u32 v2, v2, s7, 1 + buffer_load_dwordx4 v[32:35], v5, s[8:11], 0 offen + buffer_load_dwordx4 v[36:39], v2, s[8:11], 0 offen + v_xor_b32_e32 v5, v3, v51 + v_lshlrev_b32_e32 v6, 7, v40 + v_lshlrev_b32_e32 v53, 1, v52 + v_lshrrev_b32_e32 v54, 29, v42 + v_lshl_or_b32 v2, v5, 3, v6 + v_lshrrev_b32_e32 v40, 31, v106 + v_add_u32_e32 v42, v41, v54 + v_add_u32_e32 v43, v46, v54 + v_add_u32_e32 v48, v47, v54 + v_add_u32_e32 v40, v106, v40 + v_and_b32_e32 v42, -8, v42 + v_and_b32_e32 v49, -8, v43 + v_and_b32_e32 v48, -8, v48 + v_ashrrev_i32_e32 v55, 1, v40 + v_sub_u32_e32 v56, v41, v42 + buffer_load_dwordx4 v[40:43], v55, s[12:15], 0 offen + v_sub_u32_e32 v57, v46, v49 + v_sub_u32_e32 v58, v47, v48 + buffer_load_dwordx4 v[46:49], v55, s[12:15], 16 offen + v_xor_b32_e32 v55, v56, v74 + v_xor_b32_e32 v56, v57, v74 + v_xor_b32_e32 v57, v58, v74 + v_sub_u32_e32 v58, v55, v74 + v_sub_u32_e32 v55, v56, v55 + v_sub_u32_e32 v56, v57, v56 + v_lshlrev_b32_e32 v59, 3, v58 + v_lshlrev_b32_e32 v60, 3, v55 + v_lshl_add_u32 v58, v58, 4, v53 + v_lshlrev_b32_e32 v61, 3, v56 + v_add3_u32 v52, v59, v52, v60 + s_waitcnt vmcnt(9) + ds_write_b128 v53, v[8:11] + s_waitcnt vmcnt(8) + ds_write_b128 v58, v[12:15] offset:128 + v_or_b32_e32 v8, 4, v0 + v_add_u32_e32 v9, v8, v54 + v_and_b32_e32 v9, -8, v9 + v_sub_u32_e32 v8, v8, v9 + v_xor_b32_e32 v8, v8, v74 + v_sub_u32_e32 v9, v8, v57 + v_lshlrev_b32_e32 v10, 3, v9 + v_add3_u32 v10, v52, v61, v10 + v_lshlrev_b32_e32 v11, 4, v55 + s_movk_i32 s20, 0x80 + v_add3_u32 v11, v58, s20, v11 + s_waitcnt vmcnt(7) + ds_write_b128 v11, v[16:19] offset:128 + v_or_b32_e32 v12, 5, v0 + v_add_u32_e32 v13, v12, v54 + v_and_b32_e32 v13, -8, v13 + v_sub_u32_e32 v12, v12, v13 + v_xor_b32_e32 v12, v12, v74 + v_sub_u32_e32 v8, v12, v8 + v_lshlrev_b32_e32 v13, 3, v8 + v_or_b32_e32 v14, 6, v0 + v_add_u32_e32 v15, v14, v54 + v_and_b32_e32 v15, -8, v15 + v_sub_u32_e32 v14, v14, v15 + v_xor_b32_e32 v14, v14, v74 + v_sub_u32_e32 v12, v14, v12 + v_lshlrev_b32_e32 v15, 3, v12 + v_add3_u32 v10, v10, v13, v15 + v_lshlrev_b32_e32 v13, 4, v56 + v_add3_u32 v11, v11, s20, v13 + s_waitcnt vmcnt(6) + ds_write_b128 v11, v[20:23] offset:128 + v_or_b32_e32 v0, 7, v0 + v_add_u32_e32 v13, v0, v54 + v_and_b32_e32 v13, 0xffffff8, v13 + v_sub_u32_e32 v0, v0, v13 + v_xor_b32_e32 v0, v0, v74 + v_sub_u32_e32 v0, v0, v14 + v_lshlrev_b32_e32 v0, 4, v0 + v_lshl_add_u32 v0, v10, 1, v0 + v_lshlrev_b32_e32 v9, 4, v9 + v_add3_u32 v9, v11, s20, v9 + s_waitcnt vmcnt(5) + ds_write_b128 v9, v[24:27] offset:128 + v_lshlrev_b32_e32 v8, 4, v8 + v_add3_u32 v8, v9, s20, v8 + s_waitcnt vmcnt(4) + ds_write_b128 v8, v[28:31] offset:128 + v_lshlrev_b32_e32 v9, 4, v12 + v_add3_u32 v8, v8, s20, v9 + s_waitcnt vmcnt(3) + ds_write_b128 v8, v[32:35] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v0, v[36:39] offset:896 + v_lshrrev_b32_e32 v0, 31, v50 + v_add_u32_e32 v0, v50, v0 + v_ashrrev_i32_e32 v8, 1, v0 + v_and_b32_e32 v9, 0x1ffffffe, v0 + v_sub_u32_e32 v9, v50, v9 + v_lshlrev_b32_e32 v9, 3, v9 + v_ashrrev_i32_e32 v0, 31, v0 + v_lshrrev_b32_e32 v0, 28, v0 + v_add_u32_e32 v0, v8, v0 + v_and_b32_e32 v0, -16, v0 + v_sub_u32_e32 v0, v8, v0 + v_xor_b32_e32 v10, v9, v0 + v_lshlrev_b32_e32 v8, 7, v8 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + s_waitcnt vmcnt(1) + ds_write_b32 v10, v40 offset:32768 + v_or_b32_e32 v10, 1, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + ds_write_b32 v10, v41 offset:32768 + v_or_b32_e32 v10, 2, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + ds_write_b32 v10, v42 offset:32768 + v_or_b32_e32 v10, 3, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + ds_write_b32 v10, v43 offset:32768 + v_or_b32_e32 v10, 4, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + s_waitcnt vmcnt(0) + ds_write_b32 v10, v46 offset:32768 + v_or_b32_e32 v10, 5, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + ds_write_b32 v10, v47 offset:32768 + v_or_b32_e32 v10, 6, v9 + v_xor_b32_e32 v10, v10, v0 + v_lshl_add_u32 v10, v10, 3, v8 + v_ashrrev_i32_e32 v10, 1, v10 + ds_write_b32 v10, v48 offset:32768 + v_or_b32_e32 v9, 7, v9 + v_xor_b32_e32 v0, v9, v0 + v_lshl_add_u32 v0, v0, 3, v8 + v_ashrrev_i32_e32 v0, 1, v0 + ds_write_b32 v0, v49 offset:32768 + s_andn2_b64 vcc, exec, s[2:3] + v_add_u32_e32 v12, 2, v45 + v_or_b32_e32 v11, 4, v45 + v_add_u32_e32 v10, 6, v45 + v_lshrrev_b32_e32 v104, 1, v2 + v_add_u32_e32 v9, 2, v51 + v_add_u32_e32 v8, 4, v51 + v_add_u32_e32 v0, 6, v51 + s_cbranch_vccnz .LBB43_5 +; %bb.4: ; %_ZN7ck_tile5arrayIiLi2EEC2ESt16initializer_listIiE.exit635.._crit_edge_crit_edge.i.i.i.i.i.i.i + v_xor_b32_e32 v13, v12, v74 + v_lshl_add_u32 v80, v13, 3, v7 + v_xor_b32_e32 v14, v11, v74 + v_lshl_add_u32 v81, v14, 3, v7 + v_xor_b32_e32 v15, v10, v74 + v_lshl_add_u32 v78, v15, 3, v7 + v_sub_u32_e32 v16, v4, v15 + v_mov_b32_e32 v17, 0x1000 + v_lshl_add_u32 v16, v16, 3, v17 + v_add_u32_e32 v84, v16, v78 + v_sub_u32_e32 v13, v13, v4 + v_lshlrev_b32_e32 v13, 3, v13 + v_add_u32_e32 v86, v84, v13 + v_sub_u32_e32 v14, v14, v4 + v_lshlrev_b32_e32 v14, 3, v14 + v_add_u32_e32 v87, v84, v14 + v_sub_u32_e32 v15, v15, v4 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v89, v84, v15 + v_add_u32_e32 v88, v89, v16 + v_add_u32_e32 v85, v88, v13 + v_add_u32_e32 v83, v88, v14 + v_add_u32_e32 v79, v88, v15 + v_add_u32_e32 v77, v79, v16 + v_add_u32_e32 v76, v77, v13 + v_add_u32_e32 v82, v77, v14 + v_add_u32_e32 v19, v77, v15 + v_lshrrev_b32_e32 v2, 1, v2 + v_xor_b32_e32 v13, v3, v9 + v_lshlrev_b32_e32 v14, 3, v13 + v_add_u16_e32 v14, v14, v6 + v_lshrrev_b16_e32 v194, 1, v14 + v_xor_b32_e32 v14, v3, v8 + v_lshlrev_b32_e32 v15, 3, v14 + v_add_u16_e32 v15, v15, v6 + v_lshrrev_b16_e32 v195, 1, v15 + v_xor_b32_e32 v15, v3, v0 + v_lshlrev_b32_e32 v16, 3, v15 + v_add_u16_e32 v18, v16, v6 + v_lshrrev_b16_e32 v196, 1, v18 + v_sub_u32_e32 v18, v5, v15 + v_lshl_add_u32 v17, v18, 3, v17 + v_add3_u32 v16, v16, v6, v17 + v_ashrrev_i32_e32 v197, 1, v16 + v_sub_u32_e32 v13, v13, v5 + v_lshlrev_b32_e32 v13, 3, v13 + v_add_u32_e32 v18, v16, v13 + v_ashrrev_i32_e32 v75, 1, v18 + v_sub_u32_e32 v14, v14, v5 + v_lshlrev_b32_e32 v14, 3, v14 + v_add_u32_e32 v18, v16, v14 + v_ashrrev_i32_e32 v43, 1, v18 + v_sub_u32_e32 v15, v15, v5 + v_lshlrev_b32_e32 v15, 3, v15 + v_add_u32_e32 v16, v16, v15 + v_ashrrev_i32_e32 v45, 1, v16 + v_add_u32_e32 v16, v16, v17 + v_ashrrev_i32_e32 v42, 1, v16 + v_add_u32_e32 v18, v16, v13 + v_ashrrev_i32_e32 v96, 1, v18 + v_add_u32_e32 v18, v16, v14 + v_ashrrev_i32_e32 v97, 1, v18 + v_add_u32_e32 v16, v16, v15 + v_ashrrev_i32_e32 v98, 1, v16 + v_add_u32_e32 v16, v16, v17 + v_lshrrev_b32_e32 v17, 31, v16 + v_add_u32_e32 v17, v16, v17 + v_ashrrev_i32_e32 v99, 1, v17 + v_add_u32_e32 v13, v16, v13 + v_lshrrev_b32_e32 v17, 31, v13 + v_add_u32_e32 v13, v13, v17 + v_ashrrev_i32_e32 v100, 1, v13 + v_add_u32_e32 v13, v16, v14 + v_lshrrev_b32_e32 v14, 31, v13 + v_add_u32_e32 v13, v13, v14 + v_ashrrev_i32_e32 v101, 1, v13 + v_add_u32_e32 v13, v16, v15 + v_lshrrev_b32_e32 v14, 31, v13 + v_add_u32_e32 v13, v13, v14 + v_ashrrev_i32_e32 v102, 1, v13 + s_mov_b64 s[2:3], 0 + s_branch .LBB43_6 +.LBB43_5: + s_mov_b64 s[2:3], -1 + ; implicit-def: $vgpr80 + ; implicit-def: $vgpr81 + ; implicit-def: $vgpr78 + ; implicit-def: $vgpr84 + ; implicit-def: $vgpr86 + ; implicit-def: $vgpr87 + ; implicit-def: $vgpr89 + ; implicit-def: $vgpr88 + ; implicit-def: $vgpr85 + ; implicit-def: $vgpr83 + ; implicit-def: $vgpr79 + ; implicit-def: $vgpr77 + ; implicit-def: $vgpr76 + ; implicit-def: $vgpr82 + ; implicit-def: $vgpr19 + ; implicit-def: $vgpr2 + ; implicit-def: $vgpr194 + ; implicit-def: $vgpr195 + ; implicit-def: $vgpr196 + ; implicit-def: $vgpr197 + ; implicit-def: $vgpr75 + ; implicit-def: $vgpr43 + ; implicit-def: $vgpr45 + ; implicit-def: $vgpr42 + ; implicit-def: $vgpr96 + ; implicit-def: $vgpr97 + ; implicit-def: $vgpr98 + ; implicit-def: $vgpr99 + ; implicit-def: $vgpr100 + ; implicit-def: $vgpr101 + ; implicit-def: $vgpr102 +.LBB43_6: ; %Flow73 + v_lshl_or_b32 v13, v4, 3, v7 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + s_andn2_b64 vcc, exec, s[2:3] + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_lshlrev_b32_e32 v103, 1, v13 + s_cbranch_vccnz .LBB43_10 +; %bb.7: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1089.lr.ph.i.i.i.i.i.i.i + s_ashr_i32 s2, s6, 31 + s_lshr_b32 s2, s2, 26 + s_add_i32 s6, s6, s2 + s_ashr_i32 s2, s6, 6 + v_xor_b32_e32 v2, v12, v74 + v_lshl_add_u32 v80, v2, 3, v7 + v_xor_b32_e32 v11, v11, v74 + v_lshl_add_u32 v81, v11, 3, v7 + v_xor_b32_e32 v10, v10, v74 + v_lshl_add_u32 v78, v10, 3, v7 + v_sub_u32_e32 v7, v4, v10 + v_lshlrev_b32_e32 v7, 3, v7 + v_add_u32_e32 v12, 0x1000, v7 + v_add_u32_e32 v84, v12, v78 + v_add_u32_e32 v7, v7, v78 + v_lshlrev_b32_e32 v107, 1, v7 + v_sub_u32_e32 v2, v2, v4 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v86, v84, v2 + v_add_lshl_u32 v108, v7, v2, 1 + v_sub_u32_e32 v11, v11, v4 + v_lshlrev_b32_e32 v11, 3, v11 + v_add_u32_e32 v87, v84, v11 + v_add_lshl_u32 v109, v7, v11, 1 + v_sub_u32_e32 v4, v10, v4 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v89, v84, v4 + v_add_u32_e32 v7, v7, v4 + v_lshlrev_b32_e32 v110, 1, v7 + v_add_u32_e32 v88, v89, v12 + v_add_lshl_u32 v111, v7, v12, 1 + v_add_u32_e32 v85, v88, v2 + v_add_u32_e32 v83, v88, v11 + v_add_u32_e32 v79, v88, v4 + v_add_u32_e32 v77, v79, v12 + v_add_u32_e32 v76, v77, v2 + v_add_u32_e32 v82, v77, v11 + v_add_u32_e32 v193, v77, v4 + v_xor_b32_e32 v2, v3, v9 + v_lshlrev_b32_e32 v4, 3, v2 + v_add_u16_e32 v4, v4, v6 + v_lshrrev_b16_e32 v194, 1, v4 + v_xor_b32_e32 v4, v3, v8 + v_lshlrev_b32_e32 v7, 3, v4 + v_add_u16_e32 v7, v7, v6 + v_lshrrev_b16_e32 v195, 1, v7 + v_xor_b32_e32 v0, v3, v0 + v_lshlrev_b32_e32 v3, 3, v0 + v_add_u16_e32 v7, v3, v6 + v_lshrrev_b16_e32 v196, 1, v7 + v_sub_u32_e32 v7, v5, v0 + v_mov_b32_e32 v8, 0x1000 + v_lshl_add_u32 v7, v7, 3, v8 + v_add3_u32 v3, v3, v6, v7 + v_ashrrev_i32_e32 v197, 1, v3 + v_sub_u32_e32 v2, v2, v5 + v_lshlrev_b32_e32 v2, 3, v2 + v_add_u32_e32 v6, v3, v2 + v_ashrrev_i32_e32 v75, 1, v6 + v_sub_u32_e32 v4, v4, v5 + v_lshlrev_b32_e32 v4, 3, v4 + v_add_u32_e32 v6, v3, v4 + v_ashrrev_i32_e32 v43, 1, v6 + v_sub_u32_e32 v0, v0, v5 + v_lshlrev_b32_e32 v0, 3, v0 + v_add_u32_e32 v3, v3, v0 + v_ashrrev_i32_e32 v45, 1, v3 + v_add_u32_e32 v3, v3, v7 + v_ashrrev_i32_e32 v42, 1, v3 + v_add_u32_e32 v5, v3, v2 + v_ashrrev_i32_e32 v96, 1, v5 + v_add_u32_e32 v5, v3, v4 + v_ashrrev_i32_e32 v97, 1, v5 + v_add_u32_e32 v3, v3, v0 + v_ashrrev_i32_e32 v98, 1, v3 + v_add_u32_e32 v3, v3, v7 + v_lshrrev_b32_e32 v5, 31, v3 + v_add_u32_e32 v5, v3, v5 + v_ashrrev_i32_e32 v99, 1, v5 + v_add_u32_e32 v2, v3, v2 + v_lshrrev_b32_e32 v5, 31, v2 + v_add_u32_e32 v2, v2, v5 + v_ashrrev_i32_e32 v100, 1, v2 + v_add_u32_e32 v2, v3, v4 + v_lshrrev_b32_e32 v4, 31, v2 + v_add_u32_e32 v2, v2, v4 + v_ashrrev_i32_e32 v101, 1, v2 + v_add_u32_e32 v0, v3, v0 + v_lshrrev_b32_e32 v2, 31, v0 + v_add_u32_e32 v0, v0, v2 + v_ashrrev_i32_e32 v102, 1, v0 + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + v_mov_b32_e32 v112, 0xf000f + v_mov_b32_e32 v113, 0x64006400 + v_mov_b32_e32 v114, 0xf000f0 + v_mov_b32_e32 v115, 0xe408e408 + v_mov_b32_e32 v116, 0x2c002c00 + v_mov_b32_e32 v117, 0xd480d480 + s_movk_i32 s3, 0x80 +.LBB43_8: ; %_ZZN7ck_tile30move_tensor_adaptor_coordinateILb1ENS_17tensor_descriptorINS_5tupleIJNS_5embedINS2_IJiiEEES4_Lb0EEENS_12pass_throughIiEES7_EEENS2_IJNS_8sequenceIJLi0EEEENS9_IJLi1EEEENS9_IJLi2EEEEEEENS2_IJNS9_IJLi1ELi2EEEENS9_IJLi3EEEENS9_IJLi4EEEEEEENS9_IJLi3ELi4EEEElNS9_IJLin1ELin1ELi8ELin1ELin1EEEENS9_IJLin1ELin1ELi1ELin1ELin1EEEEEENS_17tensor_coordinateILi5ESI_EENS_5arrayIiLi2EEENSO_IiLi1EEEEEvRKT0_RT1_RKT2_RT3_ENKUlT_E1_clINS_8constantILi2EEEEEDaS11_.exit.i.i.i.i.i.i.i.i.i.i.i.i1089.i.i.i.i.i.i.i + ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v106, 64, v106 + v_add_u32_e32 v44, 64, v44 + v_lshlrev_b32_e32 v0, 1, v44 + v_add_u32_e32 v2, s7, v44 + v_lshrrev_b32_e32 v3, 31, v106 + v_lshlrev_b32_e32 v4, 1, v2 + v_add_u32_e32 v2, s7, v2 + v_add_u32_e32 v3, v106, v3 + buffer_load_dwordx4 v[10:13], v0, s[8:11], 0 offen + buffer_load_dwordx4 v[14:17], v4, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v2 + v_add_u32_e32 v2, s7, v2 + v_ashrrev_i32_e32 v3, 1, v3 + v_lshlrev_b32_e32 v22, 1, v2 + v_add_u32_e32 v26, s7, v2 + buffer_load_dwordx4 v[6:9], v3, s[12:15], 0 offen + s_nop 0 + buffer_load_dwordx4 v[2:5], v3, s[12:15], 16 offen + s_nop 0 + buffer_load_dwordx4 v[18:21], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[22:25], v22, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v26 + v_add_u32_e32 v26, s7, v26 + v_lshlrev_b32_e32 v30, 1, v26 + v_add_u32_e32 v34, s7, v26 + buffer_load_dwordx4 v[26:29], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[30:33], v30, s[8:11], 0 offen + v_lshlrev_b32_e32 v0, 1, v34 + v_add_lshl_u32 v38, v34, s7, 1 + buffer_load_dwordx4 v[34:37], v0, s[8:11], 0 offen + s_nop 0 + buffer_load_dwordx4 v[38:41], v38, s[8:11], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 1, v80 + ds_read_b128 v[154:157], v0 + v_lshlrev_b32_e32 v0, 1, v81 + ds_read_b128 v[138:141], v0 + v_lshlrev_b32_e32 v0, 1, v78 + ds_read_b128 v[126:129], v0 + ds_read_b128 v[170:173], v107 offset:8192 + ds_read_b128 v[158:161], v108 offset:8192 + ds_read_b128 v[142:145], v109 offset:8192 + ds_read_b128 v[122:125], v110 offset:8192 + ds_read_b128 v[174:177], v111 offset:8192 + v_lshlrev_b32_e32 v0, 1, v86 + ds_read_b128 v[162:165], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v87 + ds_read_b128 v[146:149], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v89 + ds_read_b128 v[130:133], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v88 + ds_read_b128 v[178:181], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v85 + ds_read_b128 v[166:169], v0 offset:8192 + v_lshlrev_b32_e32 v0, 1, v83 + ds_read_b128 v[150:153], v0 offset:8192 + ds_read_b128 v[182:185], v103 + v_lshlrev_b32_e32 v0, 1, v79 + ds_read_b128 v[134:137], v0 offset:8192 + ds_read_b32 v48, v104 offset:32768 + ds_read_b32 v49, v194 offset:32768 + ds_read_b32 v50, v195 offset:32768 + ds_read_b32 v51, v196 offset:32768 + ds_read_b32 v62, v197 offset:32768 + ds_read_b32 v63, v75 offset:32768 + ds_read_b32 v64, v43 offset:32768 + ds_read_b32 v71, v45 offset:32768 + ds_read_b32 v91, v42 offset:32768 + ds_read_b32 v70, v96 offset:32768 + ds_read_b32 v55, v97 offset:32768 + ds_read_b32 v54, v98 offset:32768 + ds_read_b32 v120, v99 offset:32768 + ds_read_b32 v119, v100 offset:32768 + ds_read_b32 v0, v101 offset:32768 + ds_read_b32 v118, v102 offset:32768 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v46, v48, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v48, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v46, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[128:143], v[182:183], v[46:47], a[128:143] + v_ashrrev_i32_e32 v48, 8, v48 + v_ashrrev_i32_e32 v58, 8, v49 + s_waitcnt lgkmcnt(13) + v_ashrrev_i32_e32 v59, 8, v50 + s_waitcnt lgkmcnt(12) + v_ashrrev_i32_e32 v65, 8, v51 + v_mfma_f32_32x32x8_f16 a[160:175], v[170:171], v[46:47], a[160:175] + ;;#ASMSTART + v_and_or_b32 v52, v48, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v48, v48, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v56, v52, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v57, v48, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v48, v49, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v49, v49, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v52, v48, v115 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[174:175], v[46:47], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v53, v49, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v48, v58, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v49, v58, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v66, v48, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v67, v49, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v48, v50, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v49, v50, v114, v113 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[178:179], v[46:47], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v60, v48, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v61, v49, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v59, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v59, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v58, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v59, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v51, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v51, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v65, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v65, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v49, v47, v116, v117 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v46, v62, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v62, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v46, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[144:159], v[182:183], v[46:47], a[144:159] + v_mfma_f32_32x32x8_f16 a[208:223], v[170:171], v[46:47], a[208:223] + v_mfma_f32_32x32x8_f16 a[32:47], v[174:175], v[46:47], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[178:179], v[46:47], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[184:185], v[56:57], a[128:143] + v_ashrrev_i32_e32 v46, 8, v62 + s_waitcnt lgkmcnt(10) + v_ashrrev_i32_e32 v47, 8, v63 + s_waitcnt lgkmcnt(9) + v_ashrrev_i32_e32 v62, 8, v64 + s_waitcnt lgkmcnt(8) + v_ashrrev_i32_e32 v94, 8, v71 + v_mfma_f32_32x32x8_f16 a[160:175], v[172:173], v[56:57], a[160:175] + ;;#ASMSTART + v_and_or_b32 v65, v46, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v46, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v92, v65, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v93, v46, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v63, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v63, v63, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v72, v46, v115 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[176:177], v[56:57], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v73, v63, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v47, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v47, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v68, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v69, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v64, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v64, v114, v113 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[180:181], v[56:57], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v64, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v65, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v62, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v62, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v62, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v63, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v71, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v71, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v56, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v57, v47, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v46, v94, v112, v113 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], v[184:185], v[92:93], a[144:159] + ;;#ASMSTART + v_and_or_b32 v47, v94, v114, v113 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v46, v46, v115 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v116, v117 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v71, v91, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v95, v91, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v94, v71, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v95, v95, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[224:239], v[182:183], v[94:95], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[172:173], v[92:93], a[208:223] + v_mfma_f32_32x32x8_f16 a[0:15], v[170:171], v[94:95], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[176:177], v[92:93], a[32:47] + v_mfma_f32_32x32x8_f16 a[48:63], v[174:175], v[94:95], a[48:63] + v_mfma_f32_32x32x8_f16 a[80:95], v[180:181], v[92:93], a[80:95] + v_mfma_f32_32x32x8_f16 a[96:111], v[178:179], v[94:95], a[96:111] + v_mfma_f32_32x32x8_f16 a[128:143], v[154:155], v[52:53], a[128:143] + v_ashrrev_i32_e32 v71, 8, v91 + s_waitcnt lgkmcnt(6) + v_ashrrev_i32_e32 v91, 8, v70 + s_waitcnt lgkmcnt(5) + v_ashrrev_i32_e32 v121, 8, v55 + s_waitcnt lgkmcnt(4) + v_ashrrev_i32_e32 v190, 8, v54 + v_mfma_f32_32x32x8_f16 a[160:175], v[158:159], v[52:53], a[160:175] + ;;#ASMSTART + v_and_or_b32 v92, v71, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v71, v71, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v92, v92, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v93, v71, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v71, v70, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v70, v70, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v94, v71, v115 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[176:191], v[162:163], v[52:53], a[176:191] + ;;#ASMSTART + v_pk_fma_f16 v95, v70, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v70, v91, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v71, v91, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v186, v70, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v187, v71, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v70, v55, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v55, v55, v114, v113 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[192:207], v[166:167], v[52:53], a[192:207] + ;;#ASMSTART + v_pk_add_f16 v188, v70, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v189, v55, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v52, v121, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v53, v121, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v70, v52, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v71, v53, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v52, v54, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v53, v54, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v54, v52, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v55, v53, v116, v117 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v52, v190, v112, v113 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[224:239], v[184:185], v[92:93], a[224:239] + ;;#ASMSTART + v_and_or_b32 v53, v190, v114, v113 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v52, v52, v115 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v53, v53, v116, v117 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v91, v120, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v121, v120, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v190, v91, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v191, v121, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[182:183], v[190:191], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[172:173], v[92:93], a[0:15] + v_mfma_f32_32x32x8_f16 a[16:31], v[170:171], v[190:191], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[176:177], v[92:93], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[174:175], v[190:191], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[180:181], v[92:93], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[178:179], v[190:191], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[154:155], v[72:73], a[144:159] + v_mfma_f32_32x32x8_f16 a[208:223], v[158:159], v[72:73], a[208:223] + v_mfma_f32_32x32x8_f16 a[32:47], v[162:163], v[72:73], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[166:167], v[72:73], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[156:157], v[66:67], a[128:143] + v_mfma_f32_32x32x8_f16 a[160:175], v[160:161], v[66:67], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[164:165], v[66:67], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[168:169], v[66:67], a[192:207] + v_ashrrev_i32_e32 v66, 8, v120 + ;;#ASMSTART + v_and_or_b32 v67, v66, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v72, v66, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v66, v67, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v67, v72, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[184:185], v[66:67], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[172:173], v[66:67], a[16:31] + v_mfma_f32_32x32x8_f16 a[64:79], v[176:177], v[66:67], a[64:79] + v_mfma_f32_32x32x8_f16 a[112:127], v[180:181], v[66:67], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[156:157], v[68:69], a[144:159] + v_mfma_f32_32x32x8_f16 a[224:239], v[154:155], v[94:95], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[160:161], v[68:69], a[208:223] + v_mfma_f32_32x32x8_f16 a[0:15], v[158:159], v[94:95], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[164:165], v[68:69], a[32:47] + v_mfma_f32_32x32x8_f16 a[48:63], v[162:163], v[94:95], a[48:63] + v_mfma_f32_32x32x8_f16 a[80:95], v[168:169], v[68:69], a[80:95] + v_mfma_f32_32x32x8_f16 a[96:111], v[166:167], v[94:95], a[96:111] + v_mfma_f32_32x32x8_f16 a[128:143], v[138:139], v[60:61], a[128:143] + v_mfma_f32_32x32x8_f16 a[160:175], v[142:143], v[60:61], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[146:147], v[60:61], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[150:151], v[60:61], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[156:157], v[186:187], a[224:239] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v60, v119, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v61, v119, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v60, v60, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v61, v61, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[154:155], v[60:61], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[160:161], v[186:187], a[0:15] + v_mfma_f32_32x32x8_f16 a[16:31], v[158:159], v[60:61], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[164:165], v[186:187], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[162:163], v[60:61], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[168:169], v[186:187], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[166:167], v[60:61], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[138:139], v[64:65], a[144:159] + v_mfma_f32_32x32x8_f16 a[208:223], v[142:143], v[64:65], a[208:223] + v_mfma_f32_32x32x8_f16 a[32:47], v[146:147], v[64:65], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[150:151], v[64:65], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[140:141], v[58:59], a[128:143] + v_mfma_f32_32x32x8_f16 a[160:175], v[144:145], v[58:59], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[148:149], v[58:59], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[152:153], v[58:59], a[192:207] + v_ashrrev_i32_e32 v58, 8, v119 + ;;#ASMSTART + v_and_or_b32 v59, v58, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v60, v58, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v58, v59, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v59, v60, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[156:157], v[58:59], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[160:161], v[58:59], a[16:31] + v_mfma_f32_32x32x8_f16 a[64:79], v[164:165], v[58:59], a[64:79] + v_mfma_f32_32x32x8_f16 a[112:127], v[168:169], v[58:59], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[140:141], v[62:63], a[144:159] + v_mfma_f32_32x32x8_f16 a[224:239], v[138:139], v[188:189], a[224:239] + v_mfma_f32_32x32x8_f16 a[208:223], v[144:145], v[62:63], a[208:223] + v_mfma_f32_32x32x8_f16 a[0:15], v[142:143], v[188:189], a[0:15] + v_mfma_f32_32x32x8_f16 a[32:47], v[148:149], v[62:63], a[32:47] + v_mfma_f32_32x32x8_f16 a[48:63], v[146:147], v[188:189], a[48:63] + v_mfma_f32_32x32x8_f16 a[80:95], v[152:153], v[62:63], a[80:95] + v_mfma_f32_32x32x8_f16 a[96:111], v[150:151], v[188:189], a[96:111] + v_mfma_f32_32x32x8_f16 a[128:143], v[126:127], v[50:51], a[128:143] + v_mfma_f32_32x32x8_f16 a[160:175], v[122:123], v[50:51], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[130:131], v[50:51], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[134:135], v[50:51], a[192:207] + v_mfma_f32_32x32x8_f16 a[224:239], v[140:141], v[70:71], a[224:239] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v50, v0, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v51, v0, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v50, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v51, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[138:139], v[50:51], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[144:145], v[70:71], a[0:15] + v_mfma_f32_32x32x8_f16 a[16:31], v[142:143], v[50:51], a[16:31] + v_mfma_f32_32x32x8_f16 a[48:63], v[148:149], v[70:71], a[48:63] + v_mfma_f32_32x32x8_f16 a[64:79], v[146:147], v[50:51], a[64:79] + v_mfma_f32_32x32x8_f16 a[96:111], v[152:153], v[70:71], a[96:111] + v_mfma_f32_32x32x8_f16 a[112:127], v[150:151], v[50:51], a[112:127] + v_mfma_f32_32x32x8_f16 a[144:159], v[126:127], v[56:57], a[144:159] + v_mfma_f32_32x32x8_f16 a[208:223], v[122:123], v[56:57], a[208:223] + v_mfma_f32_32x32x8_f16 a[32:47], v[130:131], v[56:57], a[32:47] + v_mfma_f32_32x32x8_f16 a[80:95], v[134:135], v[56:57], a[80:95] + v_mfma_f32_32x32x8_f16 a[128:143], v[128:129], v[48:49], a[128:143] + v_mfma_f32_32x32x8_f16 a[160:175], v[124:125], v[48:49], a[160:175] + v_mfma_f32_32x32x8_f16 a[176:191], v[132:133], v[48:49], a[176:191] + v_mfma_f32_32x32x8_f16 a[192:207], v[136:137], v[48:49], a[192:207] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v48, v0, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v0, v0, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v48, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v49, v0, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[140:141], v[48:49], a[240:255] + v_mfma_f32_32x32x8_f16 a[16:31], v[144:145], v[48:49], a[16:31] + v_mfma_f32_32x32x8_f16 a[64:79], v[148:149], v[48:49], a[64:79] + v_mfma_f32_32x32x8_f16 a[112:127], v[152:153], v[48:49], a[112:127] + s_add_i32 s6, s2, -1 + v_readfirstlane_b32 s20, v1 + s_andn2_b32 s20, s20, 63 + s_nop 0 + v_add_u32_e32 v0, s20, v105 + v_add_u32_e32 v48, s20, v192 + v_mfma_f32_32x32x8_f16 a[144:159], v[128:129], v[46:47], a[144:159] + s_cmp_gt_u32 s2, 2 + s_mov_b32 s2, s6 + v_lshl_or_b32 v49, v0, 6, v90 + v_or_b32_e32 v50, 1, v0 + v_ashrrev_i32_e32 v51, 31, v0 + v_or_b32_e32 v56, 2, v0 + v_or_b32_e32 v57, 3, v0 + v_mfma_f32_32x32x8_f16 a[224:239], v[126:127], v[54:55], a[224:239] + v_or_b32_e32 v58, 4, v0 + v_or_b32_e32 v59, 5, v0 + v_or_b32_e32 v60, 6, v0 + v_or_b32_e32 v0, 7, v0 + v_lshrrev_b32_e32 v61, 31, v48 + v_lshlrev_b32_e32 v62, 1, v49 + v_lshrrev_b32_e32 v51, 29, v51 + v_mfma_f32_32x32x8_f16 a[208:223], v[124:125], v[46:47], a[208:223] + v_add_u32_e32 v61, v48, v61 + v_add_u32_e32 v63, v50, v51 + v_add_u32_e32 v64, v56, v51 + v_add_u32_e32 v65, v57, v51 + v_add_u32_e32 v66, v58, v51 + v_add_u32_e32 v67, v59, v51 + v_add_u32_e32 v68, v60, v51 + v_mfma_f32_32x32x8_f16 a[0:15], v[122:123], v[54:55], a[0:15] + v_add_u32_e32 v51, v0, v51 + v_ashrrev_i32_e32 v69, 1, v61 + v_and_b32_e32 v70, 0x1ffffffe, v61 + v_ashrrev_i32_e32 v61, 31, v61 + v_and_b32_e32 v63, -8, v63 + v_and_b32_e32 v64, -8, v64 + v_and_b32_e32 v65, -8, v65 + v_mfma_f32_32x32x8_f16 a[32:47], v[132:133], v[46:47], a[32:47] + v_and_b32_e32 v66, -8, v66 + v_and_b32_e32 v67, -8, v67 + v_and_b32_e32 v68, -8, v68 + v_and_b32_e32 v51, 0xffffff8, v51 + v_sub_u32_e32 v48, v48, v70 + v_lshrrev_b32_e32 v61, 28, v61 + v_lshlrev_b32_e32 v70, 7, v69 + v_mfma_f32_32x32x8_f16 a[48:63], v[130:131], v[54:55], a[48:63] + v_sub_u32_e32 v50, v50, v63 + v_sub_u32_e32 v56, v56, v64 + v_sub_u32_e32 v57, v57, v65 + v_sub_u32_e32 v58, v58, v66 + v_sub_u32_e32 v59, v59, v67 + v_sub_u32_e32 v60, v60, v68 + v_sub_u32_e32 v0, v0, v51 + v_mfma_f32_32x32x8_f16 a[80:95], v[136:137], v[46:47], a[80:95] + v_lshlrev_b32_e32 v48, 3, v48 + v_add_u32_e32 v46, v69, v61 + v_xor_b32_e32 v50, v50, v74 + v_xor_b32_e32 v51, v56, v74 + v_xor_b32_e32 v56, v57, v74 + v_xor_b32_e32 v57, v58, v74 + v_xor_b32_e32 v58, v59, v74 + v_mfma_f32_32x32x8_f16 a[96:111], v[134:135], v[54:55], a[96:111] + v_xor_b32_e32 v54, v60, v74 + v_xor_b32_e32 v0, v0, v74 + v_and_b32_e32 v55, -16, v46 + v_or_b32_e32 v59, 1, v48 + v_or_b32_e32 v60, 2, v48 + v_or_b32_e32 v61, 3, v48 + v_or_b32_e32 v63, 4, v48 + v_mfma_f32_32x32x8_f16 a[224:239], v[128:129], v[52:53], a[224:239] + v_or_b32_e32 v64, 5, v48 + v_or_b32_e32 v65, 6, v48 + v_or_b32_e32 v66, 7, v48 + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v46, v118, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v47, v118, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v46, v46, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v47, v47, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[126:127], v[46:47], a[240:255] + v_sub_u32_e32 v67, v50, v74 + v_sub_u32_e32 v50, v51, v50 + v_sub_u32_e32 v51, v56, v51 + v_sub_u32_e32 v56, v57, v56 + v_sub_u32_e32 v57, v58, v57 + v_sub_u32_e32 v58, v54, v58 + v_sub_u32_e32 v0, v0, v54 + v_mfma_f32_32x32x8_f16 a[0:15], v[124:125], v[52:53], a[0:15] + v_sub_u32_e32 v54, v69, v55 + v_lshlrev_b32_e32 v55, 3, v67 + v_lshlrev_b32_e32 v68, 3, v50 + v_lshl_add_u32 v67, v67, 4, v62 + v_lshlrev_b32_e32 v69, 3, v51 + v_lshlrev_b32_e32 v71, 3, v56 + v_lshlrev_b32_e32 v50, 4, v50 + v_mfma_f32_32x32x8_f16 a[16:31], v[122:123], v[46:47], a[16:31] + v_lshlrev_b32_e32 v72, 3, v57 + v_lshlrev_b32_e32 v73, 3, v58 + v_lshlrev_b32_e32 v51, 4, v51 + v_lshlrev_b32_e32 v0, 4, v0 + v_lshlrev_b32_e32 v56, 4, v56 + v_lshlrev_b32_e32 v57, 4, v57 + v_lshlrev_b32_e32 v58, 4, v58 + v_mfma_f32_32x32x8_f16 a[48:63], v[132:133], v[52:53], a[48:63] + v_xor_b32_e32 v48, v48, v54 + v_xor_b32_e32 v59, v59, v54 + v_xor_b32_e32 v60, v60, v54 + v_xor_b32_e32 v61, v61, v54 + v_xor_b32_e32 v63, v63, v54 + v_xor_b32_e32 v64, v64, v54 + v_xor_b32_e32 v65, v65, v54 + v_mfma_f32_32x32x8_f16 a[64:79], v[130:131], v[46:47], a[64:79] + v_xor_b32_e32 v54, v66, v54 + v_add3_u32 v49, v55, v49, v68 + v_add3_u32 v50, v67, s3, v50 + v_lshl_add_u32 v48, v48, 3, v70 + v_lshl_add_u32 v55, v59, 3, v70 + v_lshl_add_u32 v59, v60, 3, v70 + v_lshl_add_u32 v60, v61, 3, v70 + v_mfma_f32_32x32x8_f16 a[96:111], v[136:137], v[52:53], a[96:111] + v_lshl_add_u32 v52, v63, 3, v70 + v_lshl_add_u32 v53, v64, 3, v70 + v_lshl_add_u32 v61, v65, 3, v70 + v_lshl_add_u32 v54, v54, 3, v70 + v_add3_u32 v49, v49, v69, v71 + v_add3_u32 v51, v50, s3, v51 + v_ashrrev_i32_e32 v48, 1, v48 + v_mfma_f32_32x32x8_f16 a[112:127], v[134:135], v[46:47], a[112:127] + v_ashrrev_i32_e32 v55, 1, v55 + v_ashrrev_i32_e32 v59, 1, v59 + v_ashrrev_i32_e32 v46, 8, v118 + ;;#ASMSTART + v_and_or_b32 v47, v46, v112, v113 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v63, v46, v114, v113 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v46, v47, v115 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v47, v63, v116, v117 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[240:255], v[128:129], v[46:47], a[240:255] + v_ashrrev_i32_e32 v60, 1, v60 + v_ashrrev_i32_e32 v52, 1, v52 + v_ashrrev_i32_e32 v53, 1, v53 + v_ashrrev_i32_e32 v61, 1, v61 + v_ashrrev_i32_e32 v54, 1, v54 + v_add3_u32 v49, v49, v72, v73 + v_add3_u32 v56, v51, s3, v56 + v_mfma_f32_32x32x8_f16 a[16:31], v[124:125], v[46:47], a[16:31] + v_lshl_add_u32 v0, v49, 1, v0 + v_add3_u32 v49, v56, s3, v57 + v_add3_u32 v57, v49, s3, v58 + s_waitcnt lgkmcnt(0) + s_barrier + s_waitcnt vmcnt(9) + ds_write_b128 v62, v[10:13] + s_waitcnt vmcnt(8) + ds_write_b128 v67, v[14:17] offset:128 + v_mfma_f32_32x32x8_f16 a[64:79], v[132:133], v[46:47], a[64:79] + s_waitcnt vmcnt(5) + ds_write_b128 v50, v[18:21] offset:128 + s_waitcnt vmcnt(4) + ds_write_b128 v51, v[22:25] offset:128 + s_waitcnt vmcnt(3) + ds_write_b128 v56, v[26:29] offset:128 + s_waitcnt vmcnt(2) + ds_write_b128 v49, v[30:33] offset:128 + s_waitcnt vmcnt(1) + ds_write_b128 v57, v[34:37] offset:128 + s_waitcnt vmcnt(0) + ds_write_b128 v0, v[38:41] offset:896 + ds_write_b32 v48, v6 offset:32768 + v_mfma_f32_32x32x8_f16 a[112:127], v[136:137], v[46:47], a[112:127] + ds_write_b32 v55, v7 offset:32768 + ds_write_b32 v59, v8 offset:32768 + ds_write_b32 v60, v9 offset:32768 + ds_write_b32 v52, v2 offset:32768 + ds_write_b32 v53, v3 offset:32768 + ds_write_b32 v61, v4 offset:32768 + ds_write_b32 v54, v5 offset:32768 + s_cbranch_scc1 .LBB43_8 +; %bb.9: ; %Flow72 + v_mov_b32_e32 v2, v104 + v_mov_b32_e32 v19, v193 +.LBB43_10: ; %_ZZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEEDF16_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi8ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEENSL_IJNSM_INSN_INSO_ILSP_1EKS2_lLb1ELSR_0EEENST_ISZ_S13_S17_S18_lNS4_IJLin1ELin1ELi64ELin1ELin1EEEES1A_EELS1C_0EEES1H_EEEEESG_S + v_mov_b32_e32 v7, v197 + v_mov_b32_e32 v6, v196 + v_mov_b32_e32 v5, v195 + v_mov_b32_e32 v4, v194 + v_mov_b32_e32 v1, v192 + v_accvgpr_read_b32 v216, a128 + v_accvgpr_read_b32 v217, a129 + v_accvgpr_read_b32 v218, a130 + v_accvgpr_read_b32 v219, a131 + v_accvgpr_read_b32 v220, a132 + v_accvgpr_read_b32 v221, a133 + v_accvgpr_read_b32 v222, a134 + v_accvgpr_read_b32 v223, a135 + v_accvgpr_read_b32 v224, a136 + v_accvgpr_read_b32 v225, a137 + v_accvgpr_read_b32 v226, a138 + v_accvgpr_read_b32 v227, a139 + v_accvgpr_read_b32 v228, a140 + v_accvgpr_read_b32 v229, a141 + v_accvgpr_read_b32 v230, a142 + v_accvgpr_read_b32 v231, a143 + v_accvgpr_read_b32 v200, a144 + v_accvgpr_read_b32 v201, a145 + v_accvgpr_read_b32 v202, a146 + v_accvgpr_read_b32 v203, a147 + v_accvgpr_read_b32 v204, a148 + v_accvgpr_read_b32 v205, a149 + v_accvgpr_read_b32 v206, a150 + v_accvgpr_read_b32 v207, a151 + v_accvgpr_read_b32 v208, a152 + v_accvgpr_read_b32 v209, a153 + v_accvgpr_read_b32 v210, a154 + v_accvgpr_read_b32 v211, a155 + v_accvgpr_read_b32 v212, a156 + v_accvgpr_read_b32 v213, a157 + v_accvgpr_read_b32 v214, a158 + v_accvgpr_read_b32 v215, a159 + v_accvgpr_mov_b32 a144, a224 + v_accvgpr_mov_b32 a145, a225 + v_accvgpr_mov_b32 a146, a226 + v_accvgpr_mov_b32 a147, a227 + v_accvgpr_mov_b32 a148, a228 + v_accvgpr_mov_b32 a149, a229 + v_accvgpr_mov_b32 a150, a230 + v_accvgpr_mov_b32 a151, a231 + v_accvgpr_mov_b32 a152, a232 + v_accvgpr_mov_b32 a153, a233 + v_accvgpr_mov_b32 a154, a234 + v_accvgpr_mov_b32 a155, a235 + v_accvgpr_mov_b32 a156, a236 + v_accvgpr_mov_b32 a157, a237 + v_accvgpr_mov_b32 a158, a238 + v_accvgpr_mov_b32 a159, a239 + v_accvgpr_read_b32 v184, a240 + v_accvgpr_read_b32 v185, a241 + v_accvgpr_read_b32 v186, a242 + v_accvgpr_read_b32 v187, a243 + v_accvgpr_read_b32 v188, a244 + v_accvgpr_read_b32 v189, a245 + v_accvgpr_read_b32 v190, a246 + v_accvgpr_read_b32 v191, a247 + v_accvgpr_read_b32 v192, a248 + v_accvgpr_read_b32 v193, a249 + v_accvgpr_read_b32 v194, a250 + v_accvgpr_read_b32 v195, a251 + v_accvgpr_read_b32 v196, a252 + v_accvgpr_read_b32 v197, a253 + v_accvgpr_read_b32 v198, a254 + v_accvgpr_read_b32 v199, a255 + v_accvgpr_mov_b32 a224, a160 + v_accvgpr_mov_b32 a225, a161 + v_accvgpr_mov_b32 a226, a162 + v_accvgpr_mov_b32 a227, a163 + v_accvgpr_mov_b32 a228, a164 + v_accvgpr_mov_b32 a229, a165 + v_accvgpr_mov_b32 a230, a166 + v_accvgpr_mov_b32 a231, a167 + v_accvgpr_mov_b32 a232, a168 + v_accvgpr_mov_b32 a233, a169 + v_accvgpr_mov_b32 a234, a170 + v_accvgpr_mov_b32 a235, a171 + v_accvgpr_mov_b32 a236, a172 + v_accvgpr_mov_b32 a237, a173 + v_accvgpr_mov_b32 a238, a174 + v_accvgpr_mov_b32 a239, a175 + v_accvgpr_read_b32 v168, a208 + v_accvgpr_read_b32 v169, a209 + v_accvgpr_read_b32 v170, a210 + v_accvgpr_read_b32 v171, a211 + v_accvgpr_read_b32 v172, a212 + v_accvgpr_read_b32 v173, a213 + v_accvgpr_read_b32 v174, a214 + v_accvgpr_read_b32 v175, a215 + v_accvgpr_read_b32 v176, a216 + v_accvgpr_read_b32 v177, a217 + v_accvgpr_read_b32 v178, a218 + v_accvgpr_read_b32 v179, a219 + v_accvgpr_read_b32 v180, a220 + v_accvgpr_read_b32 v181, a221 + v_accvgpr_read_b32 v182, a222 + v_accvgpr_read_b32 v183, a223 + v_accvgpr_read_b32 v152, a0 + v_accvgpr_read_b32 v153, a1 + v_accvgpr_read_b32 v154, a2 + v_accvgpr_read_b32 v155, a3 + v_accvgpr_read_b32 v156, a4 + v_accvgpr_read_b32 v157, a5 + v_accvgpr_read_b32 v158, a6 + v_accvgpr_read_b32 v159, a7 + v_accvgpr_read_b32 v160, a8 + v_accvgpr_read_b32 v161, a9 + v_accvgpr_read_b32 v162, a10 + v_accvgpr_read_b32 v163, a11 + v_accvgpr_read_b32 v164, a12 + v_accvgpr_read_b32 v165, a13 + v_accvgpr_read_b32 v166, a14 + v_accvgpr_read_b32 v167, a15 + v_accvgpr_mov_b32 a160, a16 + v_accvgpr_mov_b32 a161, a17 + v_accvgpr_mov_b32 a162, a18 + v_accvgpr_mov_b32 a163, a19 + v_accvgpr_mov_b32 a164, a20 + v_accvgpr_mov_b32 a165, a21 + v_accvgpr_mov_b32 a166, a22 + v_accvgpr_mov_b32 a167, a23 + v_accvgpr_mov_b32 a168, a24 + v_accvgpr_mov_b32 a169, a25 + v_accvgpr_mov_b32 a170, a26 + v_accvgpr_mov_b32 a171, a27 + v_accvgpr_mov_b32 a172, a28 + v_accvgpr_mov_b32 a173, a29 + v_accvgpr_mov_b32 a174, a30 + v_accvgpr_mov_b32 a175, a31 + v_accvgpr_mov_b32 a128, a176 + v_accvgpr_mov_b32 a129, a177 + v_accvgpr_mov_b32 a130, a178 + v_accvgpr_mov_b32 a131, a179 + v_accvgpr_mov_b32 a132, a180 + v_accvgpr_mov_b32 a133, a181 + v_accvgpr_mov_b32 a134, a182 + v_accvgpr_mov_b32 a135, a183 + v_accvgpr_mov_b32 a136, a184 + v_accvgpr_mov_b32 a137, a185 + v_accvgpr_mov_b32 a138, a186 + v_accvgpr_mov_b32 a139, a187 + v_accvgpr_mov_b32 a140, a188 + v_accvgpr_mov_b32 a141, a189 + v_accvgpr_mov_b32 a142, a190 + v_accvgpr_mov_b32 a143, a191 + v_accvgpr_read_b32 v136, a32 + v_accvgpr_read_b32 v137, a33 + v_accvgpr_read_b32 v138, a34 + v_accvgpr_read_b32 v139, a35 + v_accvgpr_read_b32 v140, a36 + v_accvgpr_read_b32 v141, a37 + v_accvgpr_read_b32 v142, a38 + v_accvgpr_read_b32 v143, a39 + v_accvgpr_read_b32 v144, a40 + v_accvgpr_read_b32 v145, a41 + v_accvgpr_read_b32 v146, a42 + v_accvgpr_read_b32 v147, a43 + v_accvgpr_read_b32 v148, a44 + v_accvgpr_read_b32 v149, a45 + v_accvgpr_read_b32 v150, a46 + v_accvgpr_read_b32 v151, a47 + v_accvgpr_read_b32 v120, a48 + v_accvgpr_read_b32 v121, a49 + v_accvgpr_read_b32 v122, a50 + v_accvgpr_read_b32 v123, a51 + v_accvgpr_read_b32 v124, a52 + v_accvgpr_read_b32 v125, a53 + v_accvgpr_read_b32 v126, a54 + v_accvgpr_read_b32 v127, a55 + v_accvgpr_read_b32 v128, a56 + v_accvgpr_read_b32 v129, a57 + v_accvgpr_read_b32 v130, a58 + v_accvgpr_read_b32 v131, a59 + v_accvgpr_read_b32 v132, a60 + v_accvgpr_read_b32 v133, a61 + v_accvgpr_read_b32 v134, a62 + v_accvgpr_read_b32 v135, a63 + v_accvgpr_read_b32 v104, a64 + v_accvgpr_read_b32 v105, a65 + v_accvgpr_read_b32 v106, a66 + v_accvgpr_read_b32 v107, a67 + v_accvgpr_read_b32 v108, a68 + v_accvgpr_read_b32 v109, a69 + v_accvgpr_read_b32 v110, a70 + v_accvgpr_read_b32 v111, a71 + v_accvgpr_read_b32 v112, a72 + v_accvgpr_read_b32 v113, a73 + v_accvgpr_read_b32 v114, a74 + v_accvgpr_read_b32 v115, a75 + v_accvgpr_read_b32 v116, a76 + v_accvgpr_read_b32 v117, a77 + v_accvgpr_read_b32 v118, a78 + v_accvgpr_read_b32 v119, a79 + v_accvgpr_mov_b32 a48, a192 + v_accvgpr_mov_b32 a49, a193 + v_accvgpr_mov_b32 a50, a194 + v_accvgpr_mov_b32 a51, a195 + v_accvgpr_mov_b32 a52, a196 + v_accvgpr_mov_b32 a53, a197 + v_accvgpr_mov_b32 a54, a198 + v_accvgpr_mov_b32 a55, a199 + v_accvgpr_mov_b32 a56, a200 + v_accvgpr_mov_b32 a57, a201 + v_accvgpr_mov_b32 a58, a202 + v_accvgpr_mov_b32 a59, a203 + v_accvgpr_mov_b32 a60, a204 + v_accvgpr_mov_b32 a61, a205 + v_accvgpr_mov_b32 a62, a206 + v_accvgpr_mov_b32 a63, a207 + v_accvgpr_mov_b32 a32, a80 + v_accvgpr_mov_b32 a33, a81 + v_accvgpr_mov_b32 a34, a82 + v_accvgpr_mov_b32 a35, a83 + v_accvgpr_mov_b32 a36, a84 + v_accvgpr_mov_b32 a37, a85 + v_accvgpr_mov_b32 a38, a86 + v_accvgpr_mov_b32 a39, a87 + v_accvgpr_mov_b32 a40, a88 + v_accvgpr_mov_b32 a41, a89 + v_accvgpr_mov_b32 a42, a90 + v_accvgpr_mov_b32 a43, a91 + v_accvgpr_mov_b32 a44, a92 + v_accvgpr_mov_b32 a45, a93 + v_accvgpr_mov_b32 a46, a94 + v_accvgpr_mov_b32 a47, a95 + v_accvgpr_mov_b32 a16, a96 + v_accvgpr_mov_b32 a17, a97 + v_accvgpr_mov_b32 a18, a98 + v_accvgpr_mov_b32 a19, a99 + v_accvgpr_mov_b32 a20, a100 + v_accvgpr_mov_b32 a21, a101 + v_accvgpr_mov_b32 a22, a102 + v_accvgpr_mov_b32 a23, a103 + v_accvgpr_mov_b32 a24, a104 + v_accvgpr_mov_b32 a25, a105 + v_accvgpr_mov_b32 a26, a106 + v_accvgpr_mov_b32 a27, a107 + v_accvgpr_mov_b32 a28, a108 + v_accvgpr_mov_b32 a29, a109 + v_accvgpr_mov_b32 a30, a110 + v_accvgpr_mov_b32 a31, a111 + v_accvgpr_mov_b32 a240, a112 + v_accvgpr_mov_b32 a241, a113 + v_accvgpr_mov_b32 a242, a114 + v_accvgpr_mov_b32 a243, a115 + v_accvgpr_mov_b32 a244, a116 + v_accvgpr_mov_b32 a245, a117 + v_accvgpr_mov_b32 a246, a118 + v_accvgpr_mov_b32 a247, a119 + v_accvgpr_mov_b32 a248, a120 + v_accvgpr_mov_b32 a249, a121 + v_accvgpr_mov_b32 a250, a122 + v_accvgpr_mov_b32 a251, a123 + v_accvgpr_mov_b32 a252, a124 + v_accvgpr_mov_b32 a253, a125 + v_accvgpr_mov_b32 a254, a126 + v_accvgpr_mov_b32 a255, a127 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v0, 1, v80 + v_lshlrev_b32_e32 v3, 1, v81 + ds_read_b128 v[244:247], v0 + ds_read_b128 v[232:235], v3 + v_lshlrev_b32_e32 v0, 1, v78 + v_lshlrev_b32_e32 v3, 1, v84 + ds_read_b128 v[60:63], v0 + ds_read_b128 a[80:83], v3 + v_lshlrev_b32_e32 v0, 1, v86 + v_lshlrev_b32_e32 v3, 1, v87 + ds_read_b128 v[248:251], v0 + ds_read_b128 v[236:239], v3 + v_lshlrev_b32_e32 v0, 1, v89 + v_lshlrev_b32_e32 v3, 1, v88 + ds_read_b128 v[64:67], v0 + ds_read_b128 v[92:95], v3 + v_lshlrev_b32_e32 v0, 1, v85 + v_lshlrev_b32_e32 v3, 1, v83 + ds_read_b128 v[252:255], v0 + ds_read_b128 v[84:87], v3 + v_lshlrev_b32_e32 v0, 1, v79 + v_lshlrev_b32_e32 v3, 1, v77 + ds_read_b128 v[68:71], v0 + ds_read_b128 v[88:91], v3 + v_lshlrev_b32_e32 v0, 1, v76 + v_lshlrev_b32_e32 v3, 1, v82 + ds_read_b128 v[80:83], v0 + ds_read_b128 v[240:243], v3 + v_lshlrev_b32_e32 v0, 1, v19 + ds_read_b128 a[84:87], v103 + ds_read_b128 v[76:79], v0 + ds_read_b32 v2, v2 offset:32768 + ds_read_b32 v3, v4 offset:32768 + ds_read_b32 v4, v5 offset:32768 + ds_read_b32 v5, v6 offset:32768 + ds_read_b32 v6, v7 offset:32768 + ds_read_b32 v7, v75 offset:32768 + ds_read_b32 v8, v43 offset:32768 + ds_read_b32 v9, v45 offset:32768 + ds_read_b32 v30, v42 offset:32768 + ds_read_b32 v31, v96 offset:32768 + ds_read_b32 v32, v97 offset:32768 + ds_read_b32 v33, v98 offset:32768 + ds_read_b32 v72, v99 offset:32768 + ds_read_b32 v59, v100 offset:32768 + ds_read_b32 v58, v101 offset:32768 + ds_read_b32 v0, v102 offset:32768 + v_mov_b32_e32 v52, 0xf000f + v_mov_b32_e32 v53, 0x64006400 + s_waitcnt lgkmcnt(14) + ;;#ASMSTART + v_and_or_b32 v10, v2, v52, v53 + ;;#ASMEND + v_mov_b32_e32 v54, 0xf000f0 + ;;#ASMSTART + v_and_or_b32 v11, v2, v54, v53 + ;;#ASMEND + v_mov_b32_e32 v55, 0xe408e408 + ;;#ASMSTART + v_pk_add_f16 v26, v10, v55 + ;;#ASMEND + v_mov_b32_e32 v56, 0x2c002c00 + v_mov_b32_e32 v57, 0xd480d480 + ;;#ASMSTART + v_pk_fma_f16 v27, v11, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v2 + ;;#ASMSTART + v_and_or_b32 v10, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v10, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v2, v56, v57 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v3, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v10, v3, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v10, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v3 + ;;#ASMSTART + v_and_or_b32 v3, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v20, v3, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v2, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(13) + ;;#ASMSTART + v_and_or_b32 v2, v4, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v4, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v3, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v2, 8, v4 + ;;#ASMSTART + v_and_or_b32 v3, v2, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v2, v2, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v12, v3, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v13, v2, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(12) + ;;#ASMSTART + v_and_or_b32 v2, v5, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v3, v5, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v2, v2, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v3, v3, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v4, 8, v5 + ;;#ASMSTART + v_and_or_b32 v5, v4, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v14, v4, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v4, v5, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v5, v14, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(11) + ;;#ASMSTART + v_and_or_b32 v14, v6, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v15, v6, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v34, v14, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v35, v15, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v6 + ;;#ASMSTART + v_and_or_b32 v14, v6, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v36, v14, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v37, v6, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(10) + ;;#ASMSTART + v_and_or_b32 v6, v7, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v14, v7, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v22, v6, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v23, v14, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v7 + ;;#ASMSTART + v_and_or_b32 v7, v6, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v24, v7, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v25, v6, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(9) + ;;#ASMSTART + v_and_or_b32 v6, v8, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v8, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v14, v6, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v15, v7, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v6, 8, v8 + ;;#ASMSTART + v_and_or_b32 v7, v6, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v6, v6, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v16, v7, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v17, v6, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(8) + ;;#ASMSTART + v_and_or_b32 v6, v9, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v7, v9, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v6, v6, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v7, v7, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v8, 8, v9 + ;;#ASMSTART + v_and_or_b32 v9, v8, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v38, v8, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v8, v9, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v9, v38, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(7) + ;;#ASMSTART + v_and_or_b32 v38, v30, v52, v53 + ;;#ASMEND + v_accvgpr_write_b32 a0, v216 + v_accvgpr_write_b32 a1, v217 + v_accvgpr_write_b32 a2, v218 + v_accvgpr_write_b32 a3, v219 + v_accvgpr_write_b32 a4, v220 + v_accvgpr_write_b32 a5, v221 + v_accvgpr_write_b32 a6, v222 + v_accvgpr_write_b32 a7, v223 + v_accvgpr_write_b32 a8, v224 + v_accvgpr_write_b32 a9, v225 + v_accvgpr_write_b32 a10, v226 + v_accvgpr_write_b32 a11, v227 + v_accvgpr_write_b32 a12, v228 + v_accvgpr_write_b32 a13, v229 + v_accvgpr_write_b32 a14, v230 + v_accvgpr_write_b32 a15, v231 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[0:15], a[84:85], v[26:27], a[0:15] + ;;#ASMSTART + v_and_or_b32 v39, v30, v54, v53 + ;;#ASMEND + ;;#ASMSTART + v_pk_add_f16 v46, v38, v55 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_fma_f16 v47, v39, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v30 + ;;#ASMSTART + v_and_or_b32 v38, v30, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v48, v38, v55 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[0:15], a[86:87], v[28:29], a[0:15] + ;;#ASMSTART + v_pk_fma_f16 v49, v30, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(6) + ;;#ASMSTART + v_and_or_b32 v30, v31, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v38, v31, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v42, v30, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v43, v38, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v31 + v_accvgpr_write_b32 a64, v200 + v_accvgpr_write_b32 a65, v201 + v_accvgpr_write_b32 a66, v202 + v_accvgpr_write_b32 a67, v203 + v_accvgpr_write_b32 a68, v204 + v_accvgpr_write_b32 a69, v205 + v_accvgpr_write_b32 a70, v206 + v_accvgpr_write_b32 a71, v207 + v_accvgpr_write_b32 a72, v208 + v_accvgpr_write_b32 a73, v209 + v_accvgpr_write_b32 a74, v210 + v_accvgpr_write_b32 a75, v211 + v_accvgpr_write_b32 a76, v212 + v_accvgpr_write_b32 a77, v213 + v_accvgpr_write_b32 a78, v214 + v_accvgpr_write_b32 a79, v215 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[64:79], a[84:85], v[34:35], a[64:79] + ;;#ASMSTART + v_and_or_b32 v31, v30, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v44, v31, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v45, v30, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(5) + ;;#ASMSTART + v_and_or_b32 v30, v32, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v32, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v38, v30, v55 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[64:79], a[86:87], v[36:37], a[64:79] + ;;#ASMSTART + v_pk_fma_f16 v39, v31, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v30, 8, v32 + ;;#ASMSTART + v_and_or_b32 v31, v30, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v30, v30, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v40, v31, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v41, v30, v56, v57 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], a[84:85], v[46:47], a[144:159] + s_waitcnt lgkmcnt(4) + ;;#ASMSTART + v_and_or_b32 v30, v33, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v31, v33, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v30, v30, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v31, v31, v56, v57 + ;;#ASMEND + v_ashrrev_i32_e32 v32, 8, v33 + ;;#ASMSTART + v_and_or_b32 v33, v32, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v50, v32, v54, v53 + ;;#ASMEND + v_mfma_f32_32x32x8_f16 a[144:159], a[86:87], v[48:49], a[144:159] + ;;#ASMSTART + v_pk_add_f16 v32, v33, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v33, v50, v56, v57 + ;;#ASMEND + s_waitcnt lgkmcnt(3) + ;;#ASMSTART + v_and_or_b32 v50, v72, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v51, v72, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v50, v50, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v51, v51, v56, v57 + ;;#ASMEND + v_accvgpr_write_b32 a223, v199 + v_accvgpr_write_b32 a222, v198 + v_accvgpr_write_b32 a221, v197 + v_accvgpr_write_b32 a220, v196 + v_accvgpr_write_b32 a219, v195 + v_accvgpr_write_b32 a218, v194 + v_accvgpr_write_b32 a217, v193 + v_accvgpr_write_b32 a216, v192 + v_accvgpr_write_b32 a215, v191 + v_accvgpr_write_b32 a214, v190 + v_accvgpr_write_b32 a213, v189 + v_accvgpr_write_b32 a212, v188 + v_accvgpr_write_b32 a211, v187 + v_accvgpr_write_b32 a210, v186 + v_accvgpr_write_b32 a209, v185 + v_accvgpr_write_b32 a208, v184 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[208:223], a[84:85], v[50:51], a[208:223] + v_ashrrev_i32_e32 v72, 8, v72 + ;;#ASMSTART + v_and_or_b32 v73, v72, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v75, v72, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v72, v73, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v73, v75, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], a[86:87], v[72:73], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], a[80:81], v[26:27], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], a[82:83], v[28:29], a[224:239] + v_accvgpr_write_b32 a207, v183 + v_accvgpr_write_b32 a206, v182 + v_accvgpr_write_b32 a205, v181 + v_accvgpr_write_b32 a204, v180 + v_accvgpr_write_b32 a203, v179 + v_accvgpr_write_b32 a202, v178 + v_accvgpr_write_b32 a201, v177 + v_accvgpr_write_b32 a200, v176 + v_accvgpr_write_b32 a199, v175 + v_accvgpr_write_b32 a198, v174 + v_accvgpr_write_b32 a197, v173 + v_accvgpr_write_b32 a196, v172 + v_accvgpr_write_b32 a195, v171 + v_accvgpr_write_b32 a194, v170 + v_accvgpr_write_b32 a193, v169 + v_accvgpr_write_b32 a192, v168 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[192:207], a[80:81], v[34:35], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], a[82:83], v[36:37], a[192:207] + v_accvgpr_write_b32 a191, v167 + v_accvgpr_write_b32 a190, v166 + v_accvgpr_write_b32 a189, v165 + v_accvgpr_write_b32 a188, v164 + v_accvgpr_write_b32 a187, v163 + v_accvgpr_write_b32 a186, v162 + v_accvgpr_write_b32 a185, v161 + v_accvgpr_write_b32 a184, v160 + v_accvgpr_write_b32 a183, v159 + v_accvgpr_write_b32 a182, v158 + v_accvgpr_write_b32 a181, v157 + v_accvgpr_write_b32 a180, v156 + v_accvgpr_write_b32 a179, v155 + v_accvgpr_write_b32 a178, v154 + v_accvgpr_write_b32 a177, v153 + v_accvgpr_write_b32 a176, v152 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[176:191], a[80:81], v[46:47], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], a[82:83], v[48:49], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], a[80:81], v[50:51], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], a[82:83], v[72:73], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[92:93], v[26:27], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[94:95], v[28:29], a[128:143] + v_accvgpr_write_b32 a112, v136 + v_accvgpr_write_b32 a113, v137 + v_accvgpr_write_b32 a114, v138 + v_accvgpr_write_b32 a115, v139 + v_accvgpr_write_b32 a116, v140 + v_accvgpr_write_b32 a117, v141 + v_accvgpr_write_b32 a118, v142 + v_accvgpr_write_b32 a119, v143 + v_accvgpr_write_b32 a120, v144 + v_accvgpr_write_b32 a121, v145 + v_accvgpr_write_b32 a122, v146 + v_accvgpr_write_b32 a123, v147 + v_accvgpr_write_b32 a124, v148 + v_accvgpr_write_b32 a125, v149 + v_accvgpr_write_b32 a126, v150 + v_accvgpr_write_b32 a127, v151 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[112:127], v[92:93], v[34:35], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[94:95], v[36:37], a[112:127] + v_accvgpr_write_b32 a96, v120 + v_accvgpr_write_b32 a97, v121 + v_accvgpr_write_b32 a98, v122 + v_accvgpr_write_b32 a99, v123 + v_accvgpr_write_b32 a100, v124 + v_accvgpr_write_b32 a101, v125 + v_accvgpr_write_b32 a102, v126 + v_accvgpr_write_b32 a103, v127 + v_accvgpr_write_b32 a104, v128 + v_accvgpr_write_b32 a105, v129 + v_accvgpr_write_b32 a106, v130 + v_accvgpr_write_b32 a107, v131 + v_accvgpr_write_b32 a108, v132 + v_accvgpr_write_b32 a109, v133 + v_accvgpr_write_b32 a110, v134 + v_accvgpr_write_b32 a111, v135 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[96:111], v[92:93], v[46:47], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[94:95], v[48:49], a[96:111] + v_accvgpr_write_b32 a80, v104 + v_accvgpr_write_b32 a81, v105 + v_accvgpr_write_b32 a82, v106 + v_accvgpr_write_b32 a83, v107 + v_accvgpr_write_b32 a84, v108 + v_accvgpr_write_b32 a85, v109 + v_accvgpr_write_b32 a86, v110 + v_accvgpr_write_b32 a87, v111 + v_accvgpr_write_b32 a88, v112 + v_accvgpr_write_b32 a89, v113 + v_accvgpr_write_b32 a90, v114 + v_accvgpr_write_b32 a91, v115 + v_accvgpr_write_b32 a92, v116 + v_accvgpr_write_b32 a93, v117 + v_accvgpr_write_b32 a94, v118 + v_accvgpr_write_b32 a95, v119 + s_nop 1 + v_mfma_f32_32x32x8_f16 a[80:95], v[92:93], v[50:51], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[94:95], v[72:73], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[88:89], v[26:27], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[90:91], v[28:29], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[88:89], v[34:35], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[90:91], v[36:37], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[88:89], v[46:47], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[90:91], v[48:49], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[88:89], v[50:51], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[90:91], v[72:73], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[244:245], v[18:19], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[246:247], v[20:21], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[244:245], v[22:23], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[246:247], v[24:25], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[244:245], v[42:43], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[246:247], v[44:45], a[144:159] + s_waitcnt lgkmcnt(2) + ;;#ASMSTART + v_and_or_b32 v26, v59, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v27, v59, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v26, v26, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v27, v27, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[244:245], v[26:27], a[208:223] + v_ashrrev_i32_e32 v28, 8, v59 + ;;#ASMSTART + v_and_or_b32 v29, v28, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v34, v28, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v28, v29, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v29, v34, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[246:247], v[28:29], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[248:249], v[18:19], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[250:251], v[20:21], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[248:249], v[22:23], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[250:251], v[24:25], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[248:249], v[42:43], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[250:251], v[44:45], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[248:249], v[26:27], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[250:251], v[28:29], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[252:253], v[18:19], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[254:255], v[20:21], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[252:253], v[22:23], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[254:255], v[24:25], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[252:253], v[42:43], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[254:255], v[44:45], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[252:253], v[26:27], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[254:255], v[28:29], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[80:81], v[18:19], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[82:83], v[20:21], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[80:81], v[22:23], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[82:83], v[24:25], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[80:81], v[42:43], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[82:83], v[44:45], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[80:81], v[26:27], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[82:83], v[28:29], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[232:233], v[10:11], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[234:235], v[12:13], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[232:233], v[14:15], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[234:235], v[16:17], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[232:233], v[38:39], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[234:235], v[40:41], a[144:159] + s_waitcnt lgkmcnt(1) + ;;#ASMSTART + v_and_or_b32 v18, v58, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v19, v58, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v18, v18, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v19, v19, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[232:233], v[18:19], a[208:223] + v_ashrrev_i32_e32 v20, 8, v58 + ;;#ASMSTART + v_and_or_b32 v21, v20, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v22, v20, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v20, v21, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v21, v22, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[234:235], v[20:21], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[236:237], v[10:11], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[238:239], v[12:13], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[236:237], v[14:15], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[238:239], v[16:17], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[236:237], v[38:39], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[238:239], v[40:41], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[236:237], v[18:19], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[238:239], v[20:21], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[84:85], v[10:11], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[86:87], v[12:13], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[84:85], v[14:15], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[86:87], v[16:17], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[84:85], v[38:39], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[86:87], v[40:41], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[84:85], v[18:19], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[86:87], v[20:21], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[240:241], v[10:11], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[242:243], v[12:13], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[240:241], v[14:15], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[242:243], v[16:17], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[240:241], v[38:39], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[242:243], v[40:41], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[240:241], v[18:19], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[242:243], v[20:21], a[240:255] + v_mfma_f32_32x32x8_f16 a[0:15], v[60:61], v[2:3], a[0:15] + v_mfma_f32_32x32x8_f16 a[0:15], v[62:63], v[4:5], a[0:15] + v_mfma_f32_32x32x8_f16 a[64:79], v[60:61], v[6:7], a[64:79] + v_mfma_f32_32x32x8_f16 a[64:79], v[62:63], v[8:9], a[64:79] + v_mfma_f32_32x32x8_f16 a[144:159], v[60:61], v[30:31], a[144:159] + v_mfma_f32_32x32x8_f16 a[144:159], v[62:63], v[32:33], a[144:159] + s_waitcnt lgkmcnt(0) + ;;#ASMSTART + v_and_or_b32 v10, v0, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v11, v0, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v10, v10, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v11, v11, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[60:61], v[10:11], a[208:223] + v_ashrrev_i32_e32 v0, 8, v0 + ;;#ASMSTART + v_and_or_b32 v12, v0, v52, v53 + ;;#ASMEND + ;;#ASMSTART + v_and_or_b32 v0, v0, v54, v53 + ;;#ASMEND + s_nop 0 + ;;#ASMSTART + v_pk_add_f16 v12, v12, v55 + ;;#ASMEND + ;;#ASMSTART + v_pk_fma_f16 v13, v0, v56, v57 + ;;#ASMEND + s_nop 0 + v_mfma_f32_32x32x8_f16 a[208:223], v[62:63], v[12:13], a[208:223] + v_mfma_f32_32x32x8_f16 a[224:239], v[64:65], v[2:3], a[224:239] + v_mfma_f32_32x32x8_f16 a[224:239], v[66:67], v[4:5], a[224:239] + v_mfma_f32_32x32x8_f16 a[192:207], v[64:65], v[6:7], a[192:207] + v_mfma_f32_32x32x8_f16 a[192:207], v[66:67], v[8:9], a[192:207] + v_mfma_f32_32x32x8_f16 a[176:191], v[64:65], v[30:31], a[176:191] + v_mfma_f32_32x32x8_f16 a[176:191], v[66:67], v[32:33], a[176:191] + v_mfma_f32_32x32x8_f16 a[160:175], v[64:65], v[10:11], a[160:175] + v_mfma_f32_32x32x8_f16 a[160:175], v[66:67], v[12:13], a[160:175] + v_mfma_f32_32x32x8_f16 a[128:143], v[68:69], v[2:3], a[128:143] + v_mfma_f32_32x32x8_f16 a[128:143], v[70:71], v[4:5], a[128:143] + v_mfma_f32_32x32x8_f16 a[112:127], v[68:69], v[6:7], a[112:127] + v_mfma_f32_32x32x8_f16 a[112:127], v[70:71], v[8:9], a[112:127] + v_mfma_f32_32x32x8_f16 a[96:111], v[68:69], v[30:31], a[96:111] + v_mfma_f32_32x32x8_f16 a[96:111], v[70:71], v[32:33], a[96:111] + v_mfma_f32_32x32x8_f16 a[80:95], v[68:69], v[10:11], a[80:95] + v_mfma_f32_32x32x8_f16 a[80:95], v[70:71], v[12:13], a[80:95] + v_mfma_f32_32x32x8_f16 a[48:63], v[76:77], v[2:3], a[48:63] + v_mfma_f32_32x32x8_f16 a[48:63], v[78:79], v[4:5], a[48:63] + v_mfma_f32_32x32x8_f16 a[32:47], v[76:77], v[6:7], a[32:47] + v_mfma_f32_32x32x8_f16 a[32:47], v[78:79], v[8:9], a[32:47] + v_mfma_f32_32x32x8_f16 a[16:31], v[76:77], v[30:31], a[16:31] + v_mfma_f32_32x32x8_f16 a[16:31], v[78:79], v[32:33], a[16:31] + v_mfma_f32_32x32x8_f16 a[240:255], v[76:77], v[10:11], a[240:255] + v_mfma_f32_32x32x8_f16 a[240:255], v[78:79], v[12:13], a[240:255] +.LBB43_11: ; %_ZNK7ck_tile28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfNS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEENS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSB_11ColumnMajorESC_Li1EEEDF16_NS_12element_wise11PassThroughESG_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEclINS_5tupleIJNS_31tile_window_with_static_lengthsINS_11tensor_viewINS_11buffer_viewILNS_18address_space_enumE1EKDF16_lLb1ELNS_25amd_buffer_coherence_enumE0EEENS_17tensor_descriptorINSL_IJNS_5embedINSL_IJiiEEESV_Lb0EEENS_12pass_throughIiEESY_EEENSL_IJNS4_IJLi0EEEENS4_IJLi1EEEENS4_IJLi2EEEEEEENSL_IJNS4_IJLi1ELi2EEEENS4_IJLi3EEEENS4_IJLi4EEEEEEENS4_IJLi3ELi4EEEElNS4_IJLin1ELin1ELi8ELin1ELin1EEEENS4_IJLin1ELin1ELi1ELin1ELin1EEEEEELNS_21memory_operation_enumE0EEENSL_IJNS_8constantILi256EEENS1E_ILi64EEEEEEEEEEENSL_IJNSM_INSN_INSO_ILSP_1EKS2_lLb1ELSR_0EEENST_ISZ_S13_S17_S18_lNS4_IJLin1ELin1ELi64ELin1ELin1EEEES1A_EELS1C_0EEES1H_EEEEESG_SG + v_accvgpr_read_b32 v143, a0 + v_accvgpr_read_b32 v142, a1 + v_accvgpr_read_b32 v141, a2 + v_accvgpr_read_b32 v140, a3 + v_accvgpr_read_b32 v139, a4 + v_accvgpr_read_b32 v18, a5 + v_accvgpr_read_b32 v0, a6 + v_accvgpr_read_b32 v138, a7 + v_accvgpr_read_b32 v137, a8 + v_accvgpr_read_b32 v136, a9 + v_accvgpr_read_b32 v135, a10 + v_accvgpr_read_b32 v134, a11 + v_accvgpr_read_b32 v133, a12 + v_accvgpr_read_b32 v132, a13 + v_accvgpr_read_b32 v131, a14 + v_accvgpr_read_b32 v130, a15 + v_accvgpr_read_b32 v108, a64 + v_accvgpr_read_b32 v107, a65 + v_accvgpr_read_b32 v106, a66 + v_accvgpr_read_b32 v105, a67 + v_accvgpr_read_b32 v104, a68 + v_accvgpr_read_b32 v103, a69 + v_accvgpr_read_b32 v102, a70 + v_accvgpr_read_b32 v101, a71 + v_accvgpr_read_b32 v100, a72 + v_accvgpr_read_b32 v99, a73 + v_accvgpr_read_b32 v98, a74 + v_accvgpr_read_b32 v97, a75 + v_accvgpr_read_b32 v96, a76 + v_accvgpr_read_b32 v95, a77 + v_accvgpr_read_b32 v94, a78 + v_accvgpr_read_b32 v93, a79 + v_accvgpr_read_b32 v92, a144 + v_accvgpr_read_b32 v91, a145 + v_accvgpr_read_b32 v90, a146 + v_accvgpr_read_b32 v89, a147 + v_accvgpr_read_b32 v88, a148 + v_accvgpr_read_b32 v87, a149 + v_accvgpr_read_b32 v86, a150 + v_accvgpr_read_b32 v85, a151 + v_accvgpr_read_b32 v84, a152 + v_accvgpr_read_b32 v83, a153 + v_accvgpr_read_b32 v82, a154 + v_accvgpr_read_b32 v81, a155 + v_accvgpr_read_b32 v80, a156 + v_accvgpr_read_b32 v79, a157 + v_accvgpr_read_b32 v78, a158 + v_accvgpr_read_b32 v77, a159 + v_accvgpr_read_b32 v76, a208 + v_accvgpr_read_b32 v75, a209 + v_accvgpr_read_b32 v73, a210 + v_accvgpr_read_b32 v72, a211 + v_accvgpr_read_b32 v71, a212 + v_accvgpr_read_b32 v70, a213 + v_accvgpr_read_b32 v69, a214 + v_accvgpr_read_b32 v68, a215 + v_accvgpr_read_b32 v67, a216 + v_accvgpr_read_b32 v66, a217 + v_accvgpr_read_b32 v65, a218 + v_accvgpr_read_b32 v64, a219 + v_accvgpr_read_b32 v63, a220 + v_accvgpr_read_b32 v62, a221 + v_accvgpr_read_b32 v61, a222 + v_accvgpr_read_b32 v20, a223 + v_accvgpr_read_b32 v228, a224 + v_accvgpr_read_b32 v225, a225 + v_accvgpr_read_b32 v224, a226 + v_accvgpr_read_b32 v223, a227 + v_accvgpr_read_b32 v222, a228 + v_accvgpr_read_b32 v221, a229 + v_accvgpr_read_b32 v220, a230 + v_accvgpr_read_b32 v219, a231 + v_accvgpr_read_b32 v218, a232 + v_accvgpr_read_b32 v217, a233 + v_accvgpr_read_b32 v216, a234 + v_accvgpr_read_b32 v215, a235 + v_accvgpr_read_b32 v214, a236 + v_accvgpr_read_b32 v213, a237 + v_accvgpr_read_b32 v212, a238 + v_accvgpr_read_b32 v211, a239 + v_accvgpr_read_b32 v177, a192 + v_accvgpr_read_b32 v176, a193 + v_accvgpr_read_b32 v175, a194 + v_accvgpr_read_b32 v174, a195 + v_accvgpr_read_b32 v173, a196 + v_accvgpr_read_b32 v172, a197 + v_accvgpr_read_b32 v171, a198 + v_accvgpr_read_b32 v170, a199 + v_accvgpr_read_b32 v169, a200 + v_accvgpr_read_b32 v168, a201 + v_accvgpr_read_b32 v167, a202 + v_accvgpr_read_b32 v166, a203 + v_accvgpr_read_b32 v165, a204 + v_accvgpr_read_b32 v164, a205 + v_accvgpr_read_b32 v163, a206 + v_accvgpr_read_b32 v162, a207 + v_accvgpr_read_b32 v178, a176 + v_accvgpr_read_b32 v161, a177 + v_accvgpr_read_b32 v160, a178 + v_accvgpr_read_b32 v159, a179 + v_accvgpr_read_b32 v158, a180 + v_accvgpr_read_b32 v157, a181 + v_accvgpr_read_b32 v156, a182 + v_accvgpr_read_b32 v155, a183 + v_accvgpr_read_b32 v154, a184 + v_accvgpr_read_b32 v153, a185 + v_accvgpr_read_b32 v152, a186 + v_accvgpr_read_b32 v151, a187 + v_accvgpr_read_b32 v150, a188 + v_accvgpr_read_b32 v149, a189 + v_accvgpr_read_b32 v145, a190 + v_accvgpr_read_b32 v144, a191 + v_accvgpr_read_b32 v146, a160 + v_accvgpr_read_b32 v147, a161 + v_accvgpr_read_b32 v148, a162 + v_accvgpr_read_b32 v129, a163 + v_accvgpr_read_b32 v128, a164 + v_accvgpr_read_b32 v127, a165 + v_accvgpr_read_b32 v126, a166 + v_accvgpr_read_b32 v125, a167 + v_accvgpr_read_b32 v124, a168 + v_accvgpr_read_b32 v123, a169 + v_accvgpr_read_b32 v122, a170 + v_accvgpr_read_b32 v121, a171 + v_accvgpr_read_b32 v120, a172 + v_accvgpr_read_b32 v119, a173 + v_accvgpr_read_b32 v118, a174 + v_accvgpr_read_b32 v117, a175 + v_accvgpr_mov_b32 a15, a128 + v_accvgpr_mov_b32 a14, a129 + v_accvgpr_mov_b32 a13, a130 + v_accvgpr_mov_b32 a12, a131 + v_accvgpr_mov_b32 a11, a132 + v_accvgpr_mov_b32 a10, a133 + v_accvgpr_mov_b32 a9, a134 + v_accvgpr_mov_b32 a8, a135 + v_accvgpr_mov_b32 a7, a136 + v_accvgpr_mov_b32 a6, a137 + v_accvgpr_mov_b32 a5, a138 + v_accvgpr_mov_b32 a4, a139 + v_accvgpr_mov_b32 a3, a140 + v_accvgpr_mov_b32 a2, a141 + v_accvgpr_mov_b32 a1, a142 + v_accvgpr_mov_b32 a0, a143 + v_accvgpr_read_b32 v60, a112 + v_accvgpr_read_b32 v59, a113 + v_accvgpr_read_b32 v58, a114 + v_accvgpr_read_b32 v57, a115 + v_accvgpr_read_b32 v56, a116 + v_accvgpr_read_b32 v55, a117 + v_accvgpr_read_b32 v54, a118 + v_accvgpr_read_b32 v53, a119 + v_accvgpr_read_b32 v52, a120 + v_accvgpr_read_b32 v51, a121 + v_accvgpr_read_b32 v50, a122 + v_accvgpr_read_b32 v25, a123 + v_accvgpr_read_b32 v24, a124 + v_accvgpr_read_b32 v23, a125 + v_accvgpr_read_b32 v22, a126 + v_accvgpr_read_b32 v21, a127 + v_accvgpr_read_b32 v116, a96 + v_accvgpr_read_b32 v115, a97 + v_accvgpr_read_b32 v114, a98 + v_accvgpr_read_b32 v113, a99 + v_accvgpr_read_b32 v112, a100 + v_accvgpr_read_b32 v111, a101 + v_accvgpr_read_b32 v110, a102 + v_accvgpr_read_b32 v109, a103 + v_accvgpr_read_b32 v49, a104 + v_accvgpr_read_b32 v48, a105 + v_accvgpr_read_b32 v47, a106 + v_accvgpr_read_b32 v46, a107 + v_accvgpr_read_b32 v45, a108 + v_accvgpr_read_b32 v44, a109 + v_accvgpr_read_b32 v43, a110 + v_accvgpr_read_b32 v42, a111 + v_accvgpr_read_b32 v210, a80 + v_accvgpr_read_b32 v209, a81 + v_accvgpr_read_b32 v208, a82 + v_accvgpr_read_b32 v207, a83 + v_accvgpr_read_b32 v206, a84 + v_accvgpr_read_b32 v205, a85 + v_accvgpr_read_b32 v204, a86 + v_accvgpr_read_b32 v203, a87 + v_accvgpr_read_b32 v202, a88 + v_accvgpr_read_b32 v201, a89 + v_accvgpr_read_b32 v200, a90 + v_accvgpr_read_b32 v199, a91 + v_accvgpr_read_b32 v198, a92 + v_accvgpr_read_b32 v197, a93 + v_accvgpr_read_b32 v196, a94 + v_accvgpr_read_b32 v195, a95 + v_accvgpr_mov_b32 a71, a48 + v_accvgpr_mov_b32 a70, a49 + v_accvgpr_mov_b32 a69, a50 + v_accvgpr_mov_b32 a68, a51 + v_accvgpr_mov_b32 a67, a52 + v_accvgpr_mov_b32 a66, a53 + v_accvgpr_mov_b32 a65, a54 + v_accvgpr_mov_b32 a64, a55 + v_accvgpr_mov_b32 a55, a56 + v_accvgpr_mov_b32 a54, a57 + v_accvgpr_mov_b32 a53, a58 + v_accvgpr_mov_b32 a52, a59 + v_accvgpr_mov_b32 a51, a60 + v_accvgpr_mov_b32 a50, a61 + v_accvgpr_mov_b32 a49, a62 + v_accvgpr_mov_b32 a48, a63 + v_accvgpr_read_b32 v41, a32 + v_accvgpr_read_b32 v40, a33 + v_accvgpr_read_b32 v39, a34 + v_accvgpr_read_b32 v38, a35 + v_accvgpr_read_b32 v37, a36 + v_accvgpr_read_b32 v36, a37 + v_accvgpr_read_b32 v35, a38 + v_accvgpr_read_b32 v34, a39 + v_accvgpr_read_b32 v33, a40 + v_accvgpr_read_b32 v32, a41 + v_accvgpr_read_b32 v31, a42 + v_accvgpr_read_b32 v30, a43 + v_accvgpr_read_b32 v29, a44 + v_accvgpr_read_b32 v28, a45 + v_accvgpr_read_b32 v27, a46 + v_accvgpr_read_b32 v26, a47 + v_accvgpr_read_b32 v194, a16 + v_accvgpr_read_b32 v193, a17 + v_accvgpr_read_b32 v192, a18 + v_accvgpr_read_b32 v191, a19 + v_accvgpr_read_b32 v190, a20 + v_accvgpr_read_b32 v189, a21 + v_accvgpr_read_b32 v188, a22 + v_accvgpr_read_b32 v187, a23 + v_accvgpr_read_b32 v186, a24 + v_accvgpr_read_b32 v185, a25 + v_accvgpr_read_b32 v184, a26 + v_accvgpr_read_b32 v183, a27 + v_accvgpr_read_b32 v182, a28 + v_accvgpr_read_b32 v181, a29 + v_accvgpr_read_b32 v180, a30 + v_accvgpr_read_b32 v179, a31 + v_accvgpr_read_b32 v2, a240 + v_accvgpr_read_b32 v3, a241 + v_accvgpr_read_b32 v4, a242 + v_accvgpr_read_b32 v5, a243 + v_accvgpr_read_b32 v6, a244 + v_accvgpr_read_b32 v7, a245 + v_accvgpr_read_b32 v8, a246 + v_accvgpr_read_b32 v9, a247 + v_accvgpr_read_b32 v10, a248 + v_accvgpr_read_b32 v11, a249 + v_accvgpr_read_b32 v12, a250 + v_accvgpr_read_b32 v13, a251 + v_accvgpr_read_b32 v14, a252 + v_accvgpr_read_b32 v15, a253 + v_accvgpr_read_b32 v16, a254 + v_accvgpr_read_b32 v17, a255 + s_mul_i32 s4, s4, s16 + s_add_u32 s2, s5, s4 + s_add_u32 s4, s2, 0x80000000 + s_cmp_lg_u32 s17, 1 + v_and_b32_e32 v226, 24, v1 + v_lshrrev_b32_e32 v19, 3, v1 + v_and_b32_e32 v19, 0x1ffffffc, v19 + s_waitcnt lgkmcnt(0) + v_cvt_f16_f32_e32 v251, v143 + v_cvt_f16_f32_e32 v252, v142 + v_cvt_f16_f32_e32 v253, v141 + v_cvt_f16_f32_e32 v254, v140 + v_cvt_f16_f32_e32 v255, v139 + v_cvt_f16_f32_e32 v18, v18 + v_cvt_f16_f32_e32 v0, v0 + v_cvt_f16_f32_e32 v244, v138 + v_cvt_f16_f32_e32 v245, v137 + v_cvt_f16_f32_e32 v246, v136 + v_cvt_f16_f32_e32 v247, v135 + v_cvt_f16_f32_e32 v248, v134 + v_cvt_f16_f32_e32 v249, v133 + v_cvt_f16_f32_e32 v250, v132 + v_cvt_f16_f32_e32 v131, v131 + v_cvt_f16_f32_e32 v227, v130 + v_cvt_f16_f32_e32 v228, v228 + v_cvt_f16_f32_e32 v229, v225 + v_cvt_f16_f32_e32 v230, v224 + v_cvt_f16_f32_e32 v231, v223 + v_cvt_f16_f32_e32 v232, v222 + v_cvt_f16_f32_e32 v233, v221 + v_cvt_f16_f32_e32 v234, v220 + v_cvt_f16_f32_e32 v235, v219 + v_cvt_f16_f32_e32 v236, v218 + v_cvt_f16_f32_e32 v237, v217 + v_cvt_f16_f32_e32 v238, v216 + v_cvt_f16_f32_e32 v239, v215 + v_cvt_f16_f32_e32 v240, v214 + v_cvt_f16_f32_e32 v241, v213 + v_cvt_f16_f32_e32 v242, v212 + v_cvt_f16_f32_e32 v243, v211 + s_mov_b64 s[2:3], -1 + v_cvt_f16_f32_e32 v108, v108 + v_cvt_f16_f32_e32 v107, v107 + v_cvt_f16_f32_e32 v106, v106 + v_cvt_f16_f32_e32 v105, v105 + v_cvt_f16_f32_e32 v104, v104 + v_cvt_f16_f32_e32 v103, v103 + v_cvt_f16_f32_e32 v102, v102 + v_cvt_f16_f32_e32 v101, v101 + v_cvt_f16_f32_e32 v100, v100 + v_cvt_f16_f32_e32 v99, v99 + v_cvt_f16_f32_e32 v98, v98 + v_cvt_f16_f32_e32 v97, v97 + v_cvt_f16_f32_e32 v96, v96 + v_cvt_f16_f32_e32 v95, v95 + v_cvt_f16_f32_e32 v94, v94 + v_cvt_f16_f32_e32 v93, v93 + v_cvt_f16_f32_e32 v130, v177 + v_cvt_f16_f32_e32 v211, v176 + v_cvt_f16_f32_e32 v212, v175 + v_cvt_f16_f32_e32 v213, v174 + v_cvt_f16_f32_e32 v214, v173 + v_cvt_f16_f32_e32 v215, v172 + v_cvt_f16_f32_e32 v216, v171 + v_cvt_f16_f32_e32 v217, v170 + v_cvt_f16_f32_e32 v218, v169 + v_cvt_f16_f32_e32 v219, v168 + v_cvt_f16_f32_e32 v220, v167 + v_cvt_f16_f32_e32 v221, v166 + v_cvt_f16_f32_e32 v222, v165 + v_cvt_f16_f32_e32 v223, v164 + v_cvt_f16_f32_e32 v224, v163 + v_cvt_f16_f32_e32 v225, v162 + v_cvt_f16_f32_e32 v162, v92 + v_cvt_f16_f32_e32 v163, v91 + v_cvt_f16_f32_e32 v164, v90 + v_cvt_f16_f32_e32 v165, v89 + v_cvt_f16_f32_e32 v166, v88 + v_cvt_f16_f32_e32 v167, v87 + v_cvt_f16_f32_e32 v168, v86 + v_cvt_f16_f32_e32 v169, v85 + v_cvt_f16_f32_e32 v170, v84 + v_cvt_f16_f32_e32 v171, v83 + v_cvt_f16_f32_e32 v172, v82 + v_cvt_f16_f32_e32 v173, v81 + v_cvt_f16_f32_e32 v174, v80 + v_cvt_f16_f32_e32 v175, v79 + v_cvt_f16_f32_e32 v176, v78 + v_cvt_f16_f32_e32 v177, v77 + v_cvt_f16_f32_e32 v178, v178 + v_cvt_f16_f32_e32 v77, v161 + v_cvt_f16_f32_e32 v78, v160 + v_cvt_f16_f32_e32 v79, v159 + v_cvt_f16_f32_e32 v80, v158 + v_cvt_f16_f32_e32 v81, v157 + v_cvt_f16_f32_e32 v82, v156 + v_cvt_f16_f32_e32 v83, v155 + v_cvt_f16_f32_e32 v84, v154 + v_cvt_f16_f32_e32 v85, v153 + v_cvt_f16_f32_e32 v86, v152 + v_cvt_f16_f32_e32 v87, v151 + v_cvt_f16_f32_e32 v88, v150 + v_cvt_f16_f32_e32 v89, v149 + v_cvt_f16_f32_e32 v90, v145 + v_cvt_f16_f32_e32 v91, v144 + v_cvt_f16_f32_e32 v76, v76 + v_cvt_f16_f32_e32 v75, v75 + v_cvt_f16_f32_e32 v132, v73 + v_cvt_f16_f32_e32 v133, v72 + v_cvt_f16_f32_e32 v134, v71 + v_cvt_f16_f32_e32 v135, v70 + v_cvt_f16_f32_e32 v136, v69 + v_cvt_f16_f32_e32 v137, v68 + v_cvt_f16_f32_e32 v138, v67 + v_cvt_f16_f32_e32 v139, v66 + v_cvt_f16_f32_e32 v140, v65 + v_cvt_f16_f32_e32 v141, v64 + v_cvt_f16_f32_e32 v142, v63 + v_cvt_f16_f32_e32 v143, v62 + v_cvt_f16_f32_e32 v144, v61 + v_cvt_f16_f32_e32 v145, v20 + v_cvt_f16_f32_e32 v146, v146 + v_cvt_f16_f32_e32 v147, v147 + v_cvt_f16_f32_e32 v148, v148 + v_cvt_f16_f32_e32 v149, v129 + v_cvt_f16_f32_e32 v150, v128 + v_cvt_f16_f32_e32 v151, v127 + v_cvt_f16_f32_e32 v152, v126 + v_cvt_f16_f32_e32 v153, v125 + v_cvt_f16_f32_e32 v154, v124 + v_cvt_f16_f32_e32 v155, v123 + v_cvt_f16_f32_e32 v156, v122 + v_cvt_f16_f32_e32 v157, v121 + v_cvt_f16_f32_e32 v158, v120 + v_cvt_f16_f32_e32 v159, v119 + v_cvt_f16_f32_e32 v160, v118 + v_cvt_f16_f32_e32 v161, v117 + v_cvt_f16_f32_e32 v92, v210 + v_cvt_f16_f32_e32 v209, v209 + v_cvt_f16_f32_e32 v210, v208 + v_cvt_f16_f32_e32 v73, v207 + v_cvt_f16_f32_e32 v72, v206 + v_cvt_f16_f32_e32 v71, v205 + v_cvt_f16_f32_e32 v70, v204 + v_cvt_f16_f32_e32 v69, v203 + v_cvt_f16_f32_e32 v68, v202 + v_cvt_f16_f32_e32 v67, v201 + v_cvt_f16_f32_e32 v66, v200 + v_cvt_f16_f32_e32 v61, v199 + v_cvt_f16_f32_e32 v62, v198 + v_cvt_f16_f32_e32 v63, v197 + v_cvt_f16_f32_e32 v64, v196 + v_cvt_f16_f32_e32 v65, v195 + v_cvt_f16_f32_e32 v2, v2 + v_cvt_f16_f32_e32 v3, v3 + v_cvt_f16_f32_e32 v4, v4 + v_cvt_f16_f32_e32 v117, v5 + v_cvt_f16_f32_e32 v118, v6 + v_cvt_f16_f32_e32 v119, v7 + v_cvt_f16_f32_e32 v120, v8 + v_cvt_f16_f32_e32 v121, v9 + v_cvt_f16_f32_e32 v122, v10 + v_cvt_f16_f32_e32 v123, v11 + v_cvt_f16_f32_e32 v124, v12 + v_cvt_f16_f32_e32 v125, v13 + v_cvt_f16_f32_e32 v126, v14 + v_cvt_f16_f32_e32 v127, v15 + v_cvt_f16_f32_e32 v128, v16 + v_cvt_f16_f32_e32 v129, v17 + v_lshlrev_b32_e32 v20, 1, v74 + v_cvt_f16_f32_e32 v5, v116 + v_cvt_f16_f32_e32 v195, v115 + v_cvt_f16_f32_e32 v196, v114 + v_cvt_f16_f32_e32 v197, v113 + v_cvt_f16_f32_e32 v198, v112 + v_cvt_f16_f32_e32 v199, v111 + v_cvt_f16_f32_e32 v200, v110 + v_cvt_f16_f32_e32 v201, v109 + v_cvt_f16_f32_e32 v74, v49 + v_cvt_f16_f32_e32 v202, v48 + v_cvt_f16_f32_e32 v203, v47 + v_cvt_f16_f32_e32 v46, v46 + v_cvt_f16_f32_e32 v45, v45 + v_cvt_f16_f32_e32 v47, v44 + v_cvt_f16_f32_e32 v48, v43 + v_cvt_f16_f32_e32 v49, v42 + v_cvt_f16_f32_e32 v109, v194 + v_cvt_f16_f32_e32 v110, v193 + v_cvt_f16_f32_e32 v111, v192 + v_cvt_f16_f32_e32 v112, v191 + v_cvt_f16_f32_e32 v113, v190 + v_cvt_f16_f32_e32 v114, v189 + v_cvt_f16_f32_e32 v115, v188 + v_cvt_f16_f32_e32 v116, v187 + v_cvt_f16_f32_e32 v186, v186 + v_cvt_f16_f32_e32 v185, v185 + v_cvt_f16_f32_e32 v184, v184 + v_cvt_f16_f32_e32 v187, v183 + v_cvt_f16_f32_e32 v183, v182 + v_cvt_f16_f32_e32 v182, v181 + v_cvt_f16_f32_e32 v181, v180 + v_cvt_f16_f32_e32 v180, v179 + v_cvt_f16_f32_e32 v42, v60 + v_cvt_f16_f32_e32 v43, v59 + v_cvt_f16_f32_e32 v44, v58 + v_cvt_f16_f32_e32 v179, v57 + v_cvt_f16_f32_e32 v6, v56 + v_cvt_f16_f32_e32 v7, v55 + v_cvt_f16_f32_e32 v8, v54 + v_cvt_f16_f32_e32 v9, v53 + v_cvt_f16_f32_e32 v10, v52 + v_cvt_f16_f32_e32 v11, v51 + v_cvt_f16_f32_e32 v12, v50 + v_cvt_f16_f32_e32 v13, v25 + v_cvt_f16_f32_e32 v14, v24 + v_cvt_f16_f32_e32 v15, v23 + v_cvt_f16_f32_e32 v16, v22 + v_cvt_f16_f32_e32 v17, v21 + v_cvt_f16_f32_e32 v50, v41 + v_cvt_f16_f32_e32 v51, v40 + v_cvt_f16_f32_e32 v52, v39 + v_cvt_f16_f32_e32 v53, v38 + v_cvt_f16_f32_e32 v54, v37 + v_cvt_f16_f32_e32 v55, v36 + v_cvt_f16_f32_e32 v56, v35 + v_cvt_f16_f32_e32 v57, v34 + v_cvt_f16_f32_e32 v58, v33 + v_cvt_f16_f32_e32 v59, v32 + v_cvt_f16_f32_e32 v60, v31 + v_cvt_f16_f32_e32 v30, v30 + v_cvt_f16_f32_e32 v29, v29 + v_cvt_f16_f32_e32 v28, v28 + v_cvt_f16_f32_e32 v27, v27 + v_cvt_f16_f32_e32 v26, v26 + v_lshlrev_b32_e32 v22, 1, v226 + v_lshlrev_b32_e32 v21, 3, v1 + v_lshrrev_b32_e32 v1, 1, v1 + scratch_load_dword v208, off, off ; 4-byte Folded Reload + s_cbranch_scc1 .LBB43_14 +; %bb.12: ; %Flow + s_andn2_b64 vcc, exec, s[2:3] + s_cbranch_vccz .LBB43_15 +.LBB43_13: ; %_ZNK7ck_tile10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS3_IJLi2ELi2ELi1EEEENS3_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS7_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSE_11ColumnMajorESF_Li1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SB_NS_5tupleIJEEEfDF16_SQ_SF_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEclENS_23UniversalGemmKernelArgsILi1ELi1ELi0EEE.exit + s_endpgm +.LBB43_14: + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s2, v208 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + s_barrier + v_add_u32_e32 v23, s5, v19 + v_lshl_add_u32 v23, v23, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v23, v23, v22, s2 + ds_write_b16 v23, v251 + ds_write_b16 v23, v252 offset:128 + ds_write_b16 v23, v253 offset:256 + ds_write_b16 v23, v254 offset:384 + ds_write_b16 v23, v255 offset:1024 + ds_write_b16 v23, v18 offset:1152 + ds_write_b16 v23, v0 offset:1280 + ds_write_b16 v23, v244 offset:1408 + ds_write_b16 v23, v245 offset:2048 + ds_write_b16 v23, v246 offset:2176 + ds_write_b16 v23, v247 offset:2304 + ds_write_b16 v23, v248 offset:2432 + ds_write_b16 v23, v249 offset:3072 + ds_write_b16 v23, v250 offset:3200 + ds_write_b16 v23, v131 offset:3328 + ds_write_b16 v23, v227 offset:3456 + ds_write_b16 v23, v228 offset:8192 + ds_write_b16 v23, v229 offset:8320 + ds_write_b16 v23, v230 offset:8448 + ds_write_b16 v23, v231 offset:8576 + ds_write_b16 v23, v232 offset:9216 + ds_write_b16 v23, v233 offset:9344 + ds_write_b16 v23, v234 offset:9472 + ds_write_b16 v23, v235 offset:9600 + ds_write_b16 v23, v236 offset:10240 + ds_write_b16 v23, v237 offset:10368 + ds_write_b16 v23, v238 offset:10496 + ds_write_b16 v23, v239 offset:10624 + ds_write_b16 v23, v240 offset:11264 + ds_write_b16 v23, v241 offset:11392 + ds_write_b16 v23, v242 offset:11520 + ds_write_b16 v23, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v24, 0x7ffffffc, v1 + v_add_u32_e32 v25, s2, v24 + v_and_b32_e32 v31, 56, v21 + v_lshlrev_b32_e32 v24, 7, v25 + v_lshl_or_b32 v24, v31, 1, v24 + v_add_u32_e32 v40, s18, v25 + v_or_b32_e32 v25, s19, v31 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_mul_lo_u32 v31, v40, s16 + v_add_u32_e32 v41, v31, v25 + v_lshlrev_b32_e32 v192, 1, v41 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v41 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v108 + ds_write_b16 v23, v107 offset:128 + ds_write_b16 v23, v106 offset:256 + ds_write_b16 v23, v105 offset:384 + ds_write_b16 v23, v104 offset:1024 + ds_write_b16 v23, v103 offset:1152 + ds_write_b16 v23, v102 offset:1280 + ds_write_b16 v23, v101 offset:1408 + ds_write_b16 v23, v100 offset:2048 + ds_write_b16 v23, v99 offset:2176 + ds_write_b16 v23, v98 offset:2304 + ds_write_b16 v23, v97 offset:2432 + ds_write_b16 v23, v96 offset:3072 + ds_write_b16 v23, v95 offset:3200 + ds_write_b16 v23, v94 offset:3328 + ds_write_b16 v23, v93 offset:3456 + ds_write_b16 v23, v130 offset:8192 + ds_write_b16 v23, v211 offset:8320 + ds_write_b16 v23, v212 offset:8448 + ds_write_b16 v23, v213 offset:8576 + ds_write_b16 v23, v214 offset:9216 + ds_write_b16 v23, v215 offset:9344 + ds_write_b16 v23, v216 offset:9472 + ds_write_b16 v23, v217 offset:9600 + ds_write_b16 v23, v218 offset:10240 + ds_write_b16 v23, v219 offset:10368 + ds_write_b16 v23, v220 offset:10496 + ds_write_b16 v23, v221 offset:10624 + ds_write_b16 v23, v222 offset:11264 + ds_write_b16 v23, v223 offset:11392 + ds_write_b16 v23, v224 offset:11520 + ds_write_b16 v23, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v41, 64, v25 + v_add_u32_e32 v192, v31, v41 + v_lshlrev_b32_e32 v193, 1, v192 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v193, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v193, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v193, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v193, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v192 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v162 + ds_write_b16 v23, v163 offset:128 + ds_write_b16 v23, v164 offset:256 + ds_write_b16 v23, v165 offset:384 + ds_write_b16 v23, v166 offset:1024 + ds_write_b16 v23, v167 offset:1152 + ds_write_b16 v23, v168 offset:1280 + ds_write_b16 v23, v169 offset:1408 + ds_write_b16 v23, v170 offset:2048 + ds_write_b16 v23, v171 offset:2176 + ds_write_b16 v23, v172 offset:2304 + ds_write_b16 v23, v173 offset:2432 + ds_write_b16 v23, v174 offset:3072 + ds_write_b16 v23, v175 offset:3200 + ds_write_b16 v23, v176 offset:3328 + ds_write_b16 v23, v177 offset:3456 + ds_write_b16 v23, v178 offset:8192 + ds_write_b16 v23, v77 offset:8320 + ds_write_b16 v23, v78 offset:8448 + ds_write_b16 v23, v79 offset:8576 + ds_write_b16 v23, v80 offset:9216 + ds_write_b16 v23, v81 offset:9344 + ds_write_b16 v23, v82 offset:9472 + ds_write_b16 v23, v83 offset:9600 + ds_write_b16 v23, v84 offset:10240 + ds_write_b16 v23, v85 offset:10368 + ds_write_b16 v23, v86 offset:10496 + ds_write_b16 v23, v87 offset:10624 + ds_write_b16 v23, v88 offset:11264 + ds_write_b16 v23, v89 offset:11392 + ds_write_b16 v23, v90 offset:11520 + ds_write_b16 v23, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v192, 0x80, v25 + v_add_u32_e32 v193, v31, v192 + v_lshlrev_b32_e32 v194, 1, v193 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v194, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v194, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v194, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v194, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v193 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v76 + ds_write_b16 v23, v75 offset:128 + ds_write_b16 v23, v132 offset:256 + ds_write_b16 v23, v133 offset:384 + ds_write_b16 v23, v134 offset:1024 + ds_write_b16 v23, v135 offset:1152 + ds_write_b16 v23, v136 offset:1280 + ds_write_b16 v23, v137 offset:1408 + ds_write_b16 v23, v138 offset:2048 + ds_write_b16 v23, v139 offset:2176 + ds_write_b16 v23, v140 offset:2304 + ds_write_b16 v23, v141 offset:2432 + ds_write_b16 v23, v142 offset:3072 + ds_write_b16 v23, v143 offset:3200 + ds_write_b16 v23, v144 offset:3328 + ds_write_b16 v23, v145 offset:3456 + ds_write_b16 v23, v146 offset:8192 + ds_write_b16 v23, v147 offset:8320 + ds_write_b16 v23, v148 offset:8448 + ds_write_b16 v23, v149 offset:8576 + ds_write_b16 v23, v150 offset:9216 + ds_write_b16 v23, v151 offset:9344 + ds_write_b16 v23, v152 offset:9472 + ds_write_b16 v23, v153 offset:9600 + ds_write_b16 v23, v154 offset:10240 + ds_write_b16 v23, v155 offset:10368 + ds_write_b16 v23, v156 offset:10496 + ds_write_b16 v23, v157 offset:10624 + ds_write_b16 v23, v158 offset:11264 + ds_write_b16 v23, v159 offset:11392 + ds_write_b16 v23, v160 offset:11520 + ds_write_b16 v23, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_or_b32_e32 v193, 0xc0, v25 + v_add_u32_e32 v31, v31, v193 + v_lshlrev_b32_e32 v194, 1, v31 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v194, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v194, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v194, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v194, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v32, s[0:3], 12 offen + v_add_u32_e32 v31, s16, v31 + v_lshlrev_b32_e32 v32, 1, v31 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v32, s[0:3], 12 offen + v_add_lshl_u32 v31, v31, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v31, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v31, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v31, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v31, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v92 + ds_write_b16 v23, v209 offset:128 + ds_write_b16 v23, v210 offset:256 + ds_write_b16 v23, v73 offset:384 + ds_write_b16 v23, v72 offset:1024 + ds_write_b16 v23, v71 offset:1152 + ds_write_b16 v23, v70 offset:1280 + ds_write_b16 v23, v69 offset:1408 + ds_write_b16 v23, v68 offset:2048 + ds_write_b16 v23, v67 offset:2176 + ds_write_b16 v23, v66 offset:2304 + ds_write_b16 v23, v61 offset:2432 + ds_write_b16 v23, v62 offset:3072 + ds_write_b16 v23, v63 offset:3200 + ds_write_b16 v23, v64 offset:3328 + ds_write_b16 v23, v65 offset:3456 + ds_write_b16 v23, v2 offset:8192 + ds_write_b16 v23, v3 offset:8320 + ds_write_b16 v23, v4 offset:8448 + ds_write_b16 v23, v117 offset:8576 + ds_write_b16 v23, v118 offset:9216 + ds_write_b16 v23, v119 offset:9344 + ds_write_b16 v23, v120 offset:9472 + ds_write_b16 v23, v121 offset:9600 + ds_write_b16 v23, v122 offset:10240 + ds_write_b16 v23, v123 offset:10368 + ds_write_b16 v23, v124 offset:10496 + ds_write_b16 v23, v125 offset:10624 + ds_write_b16 v23, v126 offset:11264 + ds_write_b16 v23, v127 offset:11392 + ds_write_b16 v23, v128 offset:11520 + ds_write_b16 v23, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v31, 0x80, v40 + v_mul_lo_u32 v31, v31, s16 + v_add_u32_e32 v40, v31, v193 + v_lshlrev_b32_e32 v193, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v193, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v193, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v193, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v193, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v5 + ds_write_b16 v23, v195 offset:128 + ds_write_b16 v23, v196 offset:256 + ds_write_b16 v23, v197 offset:384 + ds_write_b16 v23, v198 offset:1024 + ds_write_b16 v23, v199 offset:1152 + ds_write_b16 v23, v200 offset:1280 + ds_write_b16 v23, v201 offset:1408 + ds_write_b16 v23, v74 offset:2048 + ds_write_b16 v23, v202 offset:2176 + ds_write_b16 v23, v203 offset:2304 + ds_write_b16 v23, v46 offset:2432 + ds_write_b16 v23, v45 offset:3072 + ds_write_b16 v23, v47 offset:3200 + ds_write_b16 v23, v48 offset:3328 + ds_write_b16 v23, v49 offset:3456 + ds_write_b16 v23, v109 offset:8192 + ds_write_b16 v23, v110 offset:8320 + ds_write_b16 v23, v111 offset:8448 + ds_write_b16 v23, v112 offset:8576 + ds_write_b16 v23, v113 offset:9216 + ds_write_b16 v23, v114 offset:9344 + ds_write_b16 v23, v115 offset:9472 + ds_write_b16 v23, v116 offset:9600 + ds_write_b16 v23, v186 offset:10240 + ds_write_b16 v23, v185 offset:10368 + ds_write_b16 v23, v184 offset:10496 + ds_write_b16 v23, v187 offset:10624 + ds_write_b16 v23, v183 offset:11264 + ds_write_b16 v23, v182 offset:11392 + ds_write_b16 v23, v181 offset:11520 + ds_write_b16 v23, v180 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v192 + v_lshlrev_b32_e32 v192, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v192, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v192, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v192, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v192, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v23, v42 + ds_write_b16 v23, v43 offset:128 + ds_write_b16 v23, v44 offset:256 + ds_write_b16 v23, v179 offset:384 + ds_write_b16 v23, v6 offset:1024 + ds_write_b16 v23, v7 offset:1152 + ds_write_b16 v23, v8 offset:1280 + ds_write_b16 v23, v9 offset:1408 + ds_write_b16 v23, v10 offset:2048 + ds_write_b16 v23, v11 offset:2176 + ds_write_b16 v23, v12 offset:2304 + ds_write_b16 v23, v13 offset:2432 + ds_write_b16 v23, v14 offset:3072 + ds_write_b16 v23, v15 offset:3200 + ds_write_b16 v23, v16 offset:3328 + ds_write_b16 v23, v17 offset:3456 + ds_write_b16 v23, v50 offset:8192 + ds_write_b16 v23, v51 offset:8320 + ds_write_b16 v23, v52 offset:8448 + ds_write_b16 v23, v53 offset:8576 + ds_write_b16 v23, v54 offset:9216 + ds_write_b16 v23, v55 offset:9344 + ds_write_b16 v23, v56 offset:9472 + ds_write_b16 v23, v57 offset:9600 + ds_write_b16 v23, v58 offset:10240 + ds_write_b16 v23, v59 offset:10368 + ds_write_b16 v23, v60 offset:10496 + ds_write_b16 v23, v30 offset:10624 + ds_write_b16 v23, v29 offset:11264 + ds_write_b16 v23, v28 offset:11392 + ds_write_b16 v23, v27 offset:11520 + ds_write_b16 v23, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_add_u32_e32 v40, v31, v41 + v_lshlrev_b32_e32 v41, 1, v40 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v41, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v41, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v41, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v41, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v40 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v33, s[0:3], 12 offen + v_add_u32_e32 v32, s16, v32 + v_lshlrev_b32_e32 v33, 1, v32 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v33, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v33, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v33, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v33, s[0:3], 12 offen + v_add_lshl_u32 v32, v32, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v32, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v32, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v32, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v32, s[0:3], 12 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v32, a15 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 + v_accvgpr_read_b32 v32, a14 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:128 + v_accvgpr_read_b32 v32, a13 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:256 + v_accvgpr_read_b32 v32, a12 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:384 + v_accvgpr_read_b32 v32, a11 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1024 + v_accvgpr_read_b32 v32, a10 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1152 + v_accvgpr_read_b32 v32, a9 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1280 + v_accvgpr_read_b32 v32, a8 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:1408 + v_accvgpr_read_b32 v32, a7 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2048 + v_accvgpr_read_b32 v32, a6 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2176 + v_accvgpr_read_b32 v32, a5 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2304 + v_accvgpr_read_b32 v32, a4 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:2432 + v_accvgpr_read_b32 v32, a3 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3072 + v_accvgpr_read_b32 v32, a2 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3200 + v_accvgpr_read_b32 v32, a1 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3328 + v_accvgpr_read_b32 v32, a0 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:3456 + v_accvgpr_read_b32 v32, a71 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8192 + v_accvgpr_read_b32 v32, a70 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8320 + v_accvgpr_read_b32 v32, a69 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8448 + v_accvgpr_read_b32 v32, a68 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:8576 + v_accvgpr_read_b32 v32, a67 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9216 + v_accvgpr_read_b32 v32, a66 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9344 + v_accvgpr_read_b32 v32, a65 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9472 + v_accvgpr_read_b32 v32, a64 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:9600 + v_accvgpr_read_b32 v32, a55 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10240 + v_accvgpr_read_b32 v32, a54 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10368 + v_accvgpr_read_b32 v32, a53 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10496 + v_accvgpr_read_b32 v32, a52 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:10624 + v_accvgpr_read_b32 v32, a51 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11264 + v_accvgpr_read_b32 v32, a50 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11392 + v_accvgpr_read_b32 v32, a49 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11520 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v23, v32 offset:11648 + v_add_u32_e32 v23, v31, v25 + s_waitcnt lgkmcnt(0) + s_barrier + v_lshlrev_b32_e32 v25, 1, v23 + ds_read_b128 v[32:35], v24 + ds_read_b128 v[36:39], v24 offset:128 + ds_read_b128 v[188:191], v24 offset:256 + ds_read_b128 v[204:207], v24 offset:384 + s_waitcnt lgkmcnt(3) + buffer_atomic_pk_add_f16 v32, v25, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v33, v25, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v34, v25, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v35, v25, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(2) + buffer_atomic_pk_add_f16 v36, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v37, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v38, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v39, v24, s[0:3], 12 offen + v_add_u32_e32 v23, s16, v23 + v_lshlrev_b32_e32 v24, 1, v23 + s_waitcnt lgkmcnt(1) + buffer_atomic_pk_add_f16 v188, v24, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v189, v24, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v190, v24, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v191, v24, s[0:3], 12 offen + v_add_lshl_u32 v23, v23, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_atomic_pk_add_f16 v204, v23, s[0:3], 0 offen + buffer_atomic_pk_add_f16 v205, v23, s[0:3], 4 offen + buffer_atomic_pk_add_f16 v206, v23, s[0:3], 8 offen + buffer_atomic_pk_add_f16 v207, v23, s[0:3], 12 offen + s_mov_b64 vcc, exec + s_cbranch_execnz .LBB43_13 +.LBB43_15: + s_waitcnt vmcnt(0) + v_readfirstlane_b32 s2, v208 + s_lshr_b32 s3, s2, 1 + s_lshr_b32 s5, s2, 2 + s_and_b32 s5, s5, 0x1ffffe0 + v_add_u32_e32 v19, s5, v19 + s_barrier + v_lshl_add_u32 v19, v19, 7, v20 + s_and_b32 s2, s2, 64 + v_add3_u32 v31, v19, v22, s2 + ds_write_b16 v31, v251 + ds_write_b16 v31, v252 offset:128 + ds_write_b16 v31, v253 offset:256 + ds_write_b16 v31, v254 offset:384 + ds_write_b16 v31, v255 offset:1024 + ds_write_b16 v31, v18 offset:1152 + ds_write_b16 v31, v0 offset:1280 + ds_write_b16 v31, v244 offset:1408 + ds_write_b16 v31, v245 offset:2048 + ds_write_b16 v31, v246 offset:2176 + ds_write_b16 v31, v247 offset:2304 + ds_write_b16 v31, v248 offset:2432 + ds_write_b16 v31, v249 offset:3072 + ds_write_b16 v31, v250 offset:3200 + ds_write_b16 v31, v131 offset:3328 + ds_write_b16 v31, v227 offset:3456 + ds_write_b16 v31, v228 offset:8192 + ds_write_b16 v31, v229 offset:8320 + ds_write_b16 v31, v230 offset:8448 + ds_write_b16 v31, v231 offset:8576 + ds_write_b16 v31, v232 offset:9216 + ds_write_b16 v31, v233 offset:9344 + ds_write_b16 v31, v234 offset:9472 + ds_write_b16 v31, v235 offset:9600 + ds_write_b16 v31, v236 offset:10240 + ds_write_b16 v31, v237 offset:10368 + ds_write_b16 v31, v238 offset:10496 + ds_write_b16 v31, v239 offset:10624 + ds_write_b16 v31, v240 offset:11264 + ds_write_b16 v31, v241 offset:11392 + ds_write_b16 v31, v242 offset:11520 + ds_write_b16 v31, v243 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + v_and_b32_e32 v0, 56, v21 + s_and_b32 s2, s3, 0x7fffffe0 + v_and_b32_e32 v1, 0x7ffffffc, v1 + v_add_u32_e32 v1, s2, v1 + v_lshlrev_b32_e32 v18, 7, v1 + v_lshl_or_b32 v40, v0, 1, v18 + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_add_u32_e32 v41, s18, v1 + v_or_b32_e32 v188, s19, v0 + v_mul_lo_u32 v0, v41, s16 + v_add_u32_e32 v1, v0, v188 + s_lshl_b32 s2, s4, 1 + s_mov_b32 s3, 0x20000 + v_lshlrev_b32_e32 v189, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v189, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v108 + ds_write_b16 v31, v107 offset:128 + ds_write_b16 v31, v106 offset:256 + ds_write_b16 v31, v105 offset:384 + ds_write_b16 v31, v104 offset:1024 + ds_write_b16 v31, v103 offset:1152 + ds_write_b16 v31, v102 offset:1280 + ds_write_b16 v31, v101 offset:1408 + ds_write_b16 v31, v100 offset:2048 + ds_write_b16 v31, v99 offset:2176 + ds_write_b16 v31, v98 offset:2304 + ds_write_b16 v31, v97 offset:2432 + ds_write_b16 v31, v96 offset:3072 + ds_write_b16 v31, v95 offset:3200 + ds_write_b16 v31, v94 offset:3328 + ds_write_b16 v31, v93 offset:3456 + ds_write_b16 v31, v130 offset:8192 + ds_write_b16 v31, v211 offset:8320 + ds_write_b16 v31, v212 offset:8448 + ds_write_b16 v31, v213 offset:8576 + ds_write_b16 v31, v214 offset:9216 + ds_write_b16 v31, v215 offset:9344 + ds_write_b16 v31, v216 offset:9472 + ds_write_b16 v31, v217 offset:9600 + ds_write_b16 v31, v218 offset:10240 + ds_write_b16 v31, v219 offset:10368 + ds_write_b16 v31, v220 offset:10496 + ds_write_b16 v31, v221 offset:10624 + ds_write_b16 v31, v222 offset:11264 + ds_write_b16 v31, v223 offset:11392 + ds_write_b16 v31, v224 offset:11520 + ds_write_b16 v31, v225 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v93, 64, v188 + v_add_u32_e32 v1, v0, v93 + v_lshlrev_b32_e32 v94, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v94, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v162 + ds_write_b16 v31, v163 offset:128 + ds_write_b16 v31, v164 offset:256 + ds_write_b16 v31, v165 offset:384 + ds_write_b16 v31, v166 offset:1024 + ds_write_b16 v31, v167 offset:1152 + ds_write_b16 v31, v168 offset:1280 + ds_write_b16 v31, v169 offset:1408 + ds_write_b16 v31, v170 offset:2048 + ds_write_b16 v31, v171 offset:2176 + ds_write_b16 v31, v172 offset:2304 + ds_write_b16 v31, v173 offset:2432 + ds_write_b16 v31, v174 offset:3072 + ds_write_b16 v31, v175 offset:3200 + ds_write_b16 v31, v176 offset:3328 + ds_write_b16 v31, v177 offset:3456 + ds_write_b16 v31, v178 offset:8192 + ds_write_b16 v31, v77 offset:8320 + ds_write_b16 v31, v78 offset:8448 + ds_write_b16 v31, v79 offset:8576 + ds_write_b16 v31, v80 offset:9216 + ds_write_b16 v31, v81 offset:9344 + ds_write_b16 v31, v82 offset:9472 + ds_write_b16 v31, v83 offset:9600 + ds_write_b16 v31, v84 offset:10240 + ds_write_b16 v31, v85 offset:10368 + ds_write_b16 v31, v86 offset:10496 + ds_write_b16 v31, v87 offset:10624 + ds_write_b16 v31, v88 offset:11264 + ds_write_b16 v31, v89 offset:11392 + ds_write_b16 v31, v90 offset:11520 + ds_write_b16 v31, v91 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v77, 0x80, v188 + v_add_u32_e32 v1, v0, v77 + v_lshlrev_b32_e32 v78, 1, v1 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v78, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + s_nop 0 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v18, s[0:3], 0 offen + v_add_u32_e32 v1, s16, v1 + v_lshlrev_b32_e32 v18, 1, v1 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v18, s[0:3], 0 offen + v_add_lshl_u32 v1, v1, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v1, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v76 + ds_write_b16 v31, v75 offset:128 + ds_write_b16 v31, v132 offset:256 + ds_write_b16 v31, v133 offset:384 + ds_write_b16 v31, v134 offset:1024 + ds_write_b16 v31, v135 offset:1152 + ds_write_b16 v31, v136 offset:1280 + ds_write_b16 v31, v137 offset:1408 + ds_write_b16 v31, v138 offset:2048 + ds_write_b16 v31, v139 offset:2176 + ds_write_b16 v31, v140 offset:2304 + ds_write_b16 v31, v141 offset:2432 + ds_write_b16 v31, v142 offset:3072 + ds_write_b16 v31, v143 offset:3200 + ds_write_b16 v31, v144 offset:3328 + ds_write_b16 v31, v145 offset:3456 + ds_write_b16 v31, v146 offset:8192 + ds_write_b16 v31, v147 offset:8320 + ds_write_b16 v31, v148 offset:8448 + ds_write_b16 v31, v149 offset:8576 + ds_write_b16 v31, v150 offset:9216 + ds_write_b16 v31, v151 offset:9344 + ds_write_b16 v31, v152 offset:9472 + ds_write_b16 v31, v153 offset:9600 + ds_write_b16 v31, v154 offset:10240 + ds_write_b16 v31, v155 offset:10368 + ds_write_b16 v31, v156 offset:10496 + ds_write_b16 v31, v157 offset:10624 + ds_write_b16 v31, v158 offset:11264 + ds_write_b16 v31, v159 offset:11392 + ds_write_b16 v31, v160 offset:11520 + ds_write_b16 v31, v161 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[18:21], v40 + ds_read_b128 v[22:25], v40 offset:128 + ds_read_b128 v[32:35], v40 offset:256 + ds_read_b128 v[36:39], v40 offset:384 + v_or_b32_e32 v76, 0xc0, v188 + v_add_u32_e32 v0, v0, v76 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[32:35], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[36:39], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v92 + ds_write_b16 v31, v209 offset:128 + ds_write_b16 v31, v210 offset:256 + ds_write_b16 v31, v73 offset:384 + ds_write_b16 v31, v72 offset:1024 + ds_write_b16 v31, v71 offset:1152 + ds_write_b16 v31, v70 offset:1280 + ds_write_b16 v31, v69 offset:1408 + ds_write_b16 v31, v68 offset:2048 + ds_write_b16 v31, v67 offset:2176 + ds_write_b16 v31, v66 offset:2304 + ds_write_b16 v31, v61 offset:2432 + ds_write_b16 v31, v62 offset:3072 + ds_write_b16 v31, v63 offset:3200 + ds_write_b16 v31, v64 offset:3328 + ds_write_b16 v31, v65 offset:3456 + ds_write_b16 v31, v2 offset:8192 + ds_write_b16 v31, v3 offset:8320 + ds_write_b16 v31, v4 offset:8448 + ds_write_b16 v31, v117 offset:8576 + ds_write_b16 v31, v118 offset:9216 + ds_write_b16 v31, v119 offset:9344 + ds_write_b16 v31, v120 offset:9472 + ds_write_b16 v31, v121 offset:9600 + ds_write_b16 v31, v122 offset:10240 + ds_write_b16 v31, v123 offset:10368 + ds_write_b16 v31, v124 offset:10496 + ds_write_b16 v31, v125 offset:10624 + ds_write_b16 v31, v126 offset:11264 + ds_write_b16 v31, v127 offset:11392 + ds_write_b16 v31, v128 offset:11520 + ds_write_b16 v31, v129 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[18:21], v40 offset:128 + ds_read_b128 v[22:25], v40 offset:256 + ds_read_b128 v[32:35], v40 offset:384 + v_add_u32_e32 v4, 0x80, v41 + v_mul_lo_u32 v36, v4, s16 + v_add_u32_e32 v4, v36, v76 + v_lshlrev_b32_e32 v37, 1, v4 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v37, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v4 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v5 + ds_write_b16 v31, v195 offset:128 + ds_write_b16 v31, v196 offset:256 + ds_write_b16 v31, v197 offset:384 + ds_write_b16 v31, v198 offset:1024 + ds_write_b16 v31, v199 offset:1152 + ds_write_b16 v31, v200 offset:1280 + ds_write_b16 v31, v201 offset:1408 + ds_write_b16 v31, v74 offset:2048 + ds_write_b16 v31, v202 offset:2176 + ds_write_b16 v31, v203 offset:2304 + ds_write_b16 v31, v46 offset:2432 + ds_write_b16 v31, v45 offset:3072 + ds_write_b16 v31, v47 offset:3200 + ds_write_b16 v31, v48 offset:3328 + ds_write_b16 v31, v49 offset:3456 + ds_write_b16 v31, v109 offset:8192 + ds_write_b16 v31, v110 offset:8320 + ds_write_b16 v31, v111 offset:8448 + ds_write_b16 v31, v112 offset:8576 + ds_write_b16 v31, v113 offset:9216 + ds_write_b16 v31, v114 offset:9344 + ds_write_b16 v31, v115 offset:9472 + ds_write_b16 v31, v116 offset:9600 + ds_write_b16 v31, v186 offset:10240 + ds_write_b16 v31, v185 offset:10368 + ds_write_b16 v31, v184 offset:10496 + ds_write_b16 v31, v187 offset:10624 + ds_write_b16 v31, v183 offset:11264 + ds_write_b16 v31, v182 offset:11392 + ds_write_b16 v31, v181 offset:11520 + ds_write_b16 v31, v180 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[18:21], v40 offset:128 + ds_read_b128 v[22:25], v40 offset:256 + ds_read_b128 v[32:35], v40 offset:384 + v_add_u32_e32 v4, v36, v77 + v_lshlrev_b32_e32 v5, 1, v4 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v5, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v4 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[18:21], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[22:25], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[32:35], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v31, v42 + ds_write_b16 v31, v43 offset:128 + ds_write_b16 v31, v44 offset:256 + ds_write_b16 v31, v179 offset:384 + ds_write_b16 v31, v6 offset:1024 + ds_write_b16 v31, v7 offset:1152 + ds_write_b16 v31, v8 offset:1280 + ds_write_b16 v31, v9 offset:1408 + ds_write_b16 v31, v10 offset:2048 + ds_write_b16 v31, v11 offset:2176 + ds_write_b16 v31, v12 offset:2304 + ds_write_b16 v31, v13 offset:2432 + ds_write_b16 v31, v14 offset:3072 + ds_write_b16 v31, v15 offset:3200 + ds_write_b16 v31, v16 offset:3328 + ds_write_b16 v31, v17 offset:3456 + ds_write_b16 v31, v50 offset:8192 + ds_write_b16 v31, v51 offset:8320 + ds_write_b16 v31, v52 offset:8448 + ds_write_b16 v31, v53 offset:8576 + ds_write_b16 v31, v54 offset:9216 + ds_write_b16 v31, v55 offset:9344 + ds_write_b16 v31, v56 offset:9472 + ds_write_b16 v31, v57 offset:9600 + ds_write_b16 v31, v58 offset:10240 + ds_write_b16 v31, v59 offset:10368 + ds_write_b16 v31, v60 offset:10496 + ds_write_b16 v31, v30 offset:10624 + ds_write_b16 v31, v29 offset:11264 + ds_write_b16 v31, v28 offset:11392 + ds_write_b16 v31, v27 offset:11520 + ds_write_b16 v31, v26 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v36, v93 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_waitcnt lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v0, a15 + v_cvt_f16_f32_e32 v0, v0 + v_accvgpr_read_b32 v1, a14 + v_cvt_f16_f32_e32 v1, v1 + v_accvgpr_read_b32 v2, a13 + v_cvt_f16_f32_e32 v2, v2 + v_accvgpr_read_b32 v3, a12 + v_cvt_f16_f32_e32 v3, v3 + v_accvgpr_read_b32 v4, a11 + v_cvt_f16_f32_e32 v4, v4 + v_accvgpr_read_b32 v5, a10 + v_cvt_f16_f32_e32 v5, v5 + v_accvgpr_read_b32 v6, a9 + v_cvt_f16_f32_e32 v6, v6 + v_accvgpr_read_b32 v7, a8 + v_cvt_f16_f32_e32 v7, v7 + v_accvgpr_read_b32 v8, a7 + v_cvt_f16_f32_e32 v8, v8 + v_accvgpr_read_b32 v9, a6 + v_cvt_f16_f32_e32 v9, v9 + v_accvgpr_read_b32 v10, a5 + v_cvt_f16_f32_e32 v10, v10 + v_accvgpr_read_b32 v11, a4 + v_cvt_f16_f32_e32 v11, v11 + v_accvgpr_read_b32 v12, a3 + v_cvt_f16_f32_e32 v12, v12 + v_accvgpr_read_b32 v13, a2 + v_cvt_f16_f32_e32 v13, v13 + v_accvgpr_read_b32 v14, a1 + v_cvt_f16_f32_e32 v14, v14 + v_accvgpr_read_b32 v15, a0 + v_cvt_f16_f32_e32 v15, v15 + v_accvgpr_read_b32 v16, a71 + v_cvt_f16_f32_e32 v16, v16 + v_accvgpr_read_b32 v17, a70 + v_cvt_f16_f32_e32 v17, v17 + v_accvgpr_read_b32 v18, a69 + v_cvt_f16_f32_e32 v18, v18 + v_accvgpr_read_b32 v19, a68 + v_cvt_f16_f32_e32 v19, v19 + v_accvgpr_read_b32 v20, a67 + v_cvt_f16_f32_e32 v20, v20 + v_accvgpr_read_b32 v21, a66 + v_cvt_f16_f32_e32 v21, v21 + v_accvgpr_read_b32 v22, a65 + v_cvt_f16_f32_e32 v22, v22 + v_accvgpr_read_b32 v23, a64 + v_cvt_f16_f32_e32 v23, v23 + v_accvgpr_read_b32 v24, a55 + v_cvt_f16_f32_e32 v24, v24 + v_accvgpr_read_b32 v25, a54 + v_cvt_f16_f32_e32 v25, v25 + v_accvgpr_read_b32 v26, a53 + v_cvt_f16_f32_e32 v26, v26 + v_accvgpr_read_b32 v27, a52 + v_cvt_f16_f32_e32 v27, v27 + v_accvgpr_read_b32 v28, a51 + v_cvt_f16_f32_e32 v28, v28 + v_accvgpr_read_b32 v29, a50 + v_cvt_f16_f32_e32 v29, v29 + v_accvgpr_read_b32 v30, a49 + v_cvt_f16_f32_e32 v30, v30 + v_accvgpr_read_b32 v32, a48 + v_cvt_f16_f32_e32 v32, v32 + ds_write_b16 v31, v0 + ds_write_b16 v31, v1 offset:128 + ds_write_b16 v31, v2 offset:256 + ds_write_b16 v31, v3 offset:384 + ds_write_b16 v31, v4 offset:1024 + ds_write_b16 v31, v5 offset:1152 + ds_write_b16 v31, v6 offset:1280 + ds_write_b16 v31, v7 offset:1408 + ds_write_b16 v31, v8 offset:2048 + ds_write_b16 v31, v9 offset:2176 + ds_write_b16 v31, v10 offset:2304 + ds_write_b16 v31, v11 offset:2432 + ds_write_b16 v31, v12 offset:3072 + ds_write_b16 v31, v13 offset:3200 + ds_write_b16 v31, v14 offset:3328 + ds_write_b16 v31, v15 offset:3456 + ds_write_b16 v31, v16 offset:8192 + ds_write_b16 v31, v17 offset:8320 + ds_write_b16 v31, v18 offset:8448 + ds_write_b16 v31, v19 offset:8576 + ds_write_b16 v31, v20 offset:9216 + ds_write_b16 v31, v21 offset:9344 + ds_write_b16 v31, v22 offset:9472 + ds_write_b16 v31, v23 offset:9600 + ds_write_b16 v31, v24 offset:10240 + ds_write_b16 v31, v25 offset:10368 + ds_write_b16 v31, v26 offset:10496 + ds_write_b16 v31, v27 offset:10624 + ds_write_b16 v31, v28 offset:11264 + ds_write_b16 v31, v29 offset:11392 + ds_write_b16 v31, v30 offset:11520 + ds_write_b16 v31, v32 offset:11648 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 v[0:3], v40 + ds_read_b128 v[4:7], v40 offset:128 + ds_read_b128 v[8:11], v40 offset:256 + ds_read_b128 v[12:15], v40 offset:384 + v_add_u32_e32 v16, v36, v188 + v_lshlrev_b32_e32 v17, 1, v16 + s_waitcnt lgkmcnt(3) + buffer_store_dwordx4 v[0:3], v17, s[0:3], 0 offen + s_nop 1 + v_add_u32_e32 v0, s16, v16 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(2) + buffer_store_dwordx4 v[4:7], v1, s[0:3], 0 offen + v_add_u32_e32 v0, s16, v0 + v_lshlrev_b32_e32 v1, 1, v0 + s_waitcnt lgkmcnt(1) + buffer_store_dwordx4 v[8:11], v1, s[0:3], 0 offen + v_add_lshl_u32 v0, v0, s16, 1 + s_waitcnt lgkmcnt(0) + buffer_store_dwordx4 v[12:15], v0, s[0:3], 0 offen + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .amdhsa_group_segment_fixed_size 49152 + .amdhsa_private_segment_fixed_size 8 + .amdhsa_kernarg_size 88 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr 96 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,"axG",@progbits,_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_,comdat +.Lfunc_end43: + .size _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_, .Lfunc_end43-_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + ; -- End function + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_vgpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_agpr, 256 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.numbered_sgpr, 26 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.num_named_barrier, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.private_seg_size, 8 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_vcc, 1 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.uses_flat_scratch, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_dyn_sized_stack, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_recursion, 0 + .set _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 30496 +; TotalNumSgprs: 32 +; NumVgprs: 256 +; NumAgprs: 256 +; TotalNumVgprs: 512 +; ScratchSize: 8 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 49152 bytes/workgroup (compile time only) +; SGPRBlocks: 12 +; VGPRBlocks: 63 +; NumSGPRsForWavesPerEU: 102 +; NumVGPRsForWavesPerEU: 512 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat + .protected _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii ; -- Begin function _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .globl _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .p2align 8 + .type _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,@function +_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii: ; @_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii +; %bb.0: + s_load_dword s3, s[0:1], 0x30 + s_add_u32 s4, s0, 48 + s_addc_u32 s5, s1, 0 + s_waitcnt lgkmcnt(0) + s_cmp_lt_u32 s2, s3 + s_cselect_b32 s3, 12, 18 + s_add_u32 s4, s4, s3 + s_addc_u32 s5, s5, 0 + v_mov_b32_e32 v1, 0 + global_load_ushort v2, v1, s[4:5] + s_load_dwordx4 s[4:7], s[0:1], 0x18 + s_waitcnt lgkmcnt(0) + s_abs_i32 s3, s5 + v_cvt_f32_u32_e32 v3, s3 + v_rcp_iflag_f32_e32 v3, v3 + s_nop 0 + v_mul_f32_e32 v3, 0x4f7ffffe, v3 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s8, 0, s3 + s_cmp_gt_i32 s5, -1 + v_mul_lo_u32 v4, s8, v3 + v_mul_hi_u32 v4, v3, v4 + v_add_u32_e32 v3, v3, v4 + s_waitcnt vmcnt(0) + v_mul_lo_u32 v2, s2, v2 + v_add_u32_e32 v0, v2, v0 + v_xor_b32_e32 v2, s5, v0 + v_sub_u32_e32 v4, 0, v0 + v_ashrrev_i32_e32 v2, 31, v2 + v_max_i32_e32 v4, v0, v4 + v_mul_hi_u32 v3, v4, v3 + v_mul_lo_u32 v5, v3, s3 + v_add_u32_e32 v6, 1, v3 + v_sub_u32_e32 v4, v4, v5 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v6, vcc + v_subrev_u32_e32 v5, s3, v4 + v_cndmask_b32_e32 v4, v4, v5, vcc + v_add_u32_e32 v5, 1, v3 + v_cmp_le_u32_e32 vcc, s3, v4 + s_nop 1 + v_cndmask_b32_e32 v3, v3, v5, vcc + v_xor_b32_e32 v3, v3, v2 + v_sub_u32_e32 v4, v3, v2 + v_cmp_gt_i32_e32 vcc, s4, v4 + s_cselect_b64 s[2:3], -1, 0 + s_and_b64 s[2:3], s[2:3], vcc + s_and_saveexec_b64 s[8:9], s[2:3] + s_cbranch_execz .LBB44_6 +; %bb.1: ; %.preheader + s_load_dwordx2 s[2:3], s[0:1], 0x28 + s_load_dwordx4 s[8:11], s[0:1], 0x0 + s_load_dwordx2 s[12:13], s[0:1], 0x10 + v_mul_lo_u32 v2, v4, s5 + s_cmp_lt_i32 s6, 1 + v_sub_u32_e32 v0, v0, v2 + s_cbranch_scc1 .LBB44_5 +; %bb.2: ; %.lr.ph + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s8 + v_mov_b32_e32 v3, s9 + v_mul_lo_u32 v6, v4, s7 + v_mul_lo_u32 v1, v0, s2 + v_ashrrev_i32_e32 v7, 31, v6 + v_lshl_add_u64 v[2:3], v[6:7], 1, v[2:3] + s_mov_b32 s0, 0 + v_mov_b32_e32 v5, 0 +.LBB44_3: ; =>This Inner Loop Header: Depth=1 + v_add_u32_e32 v6, s0, v1 + v_lshrrev_b32_e32 v7, 31, v6 + v_add_u32_e32 v6, v6, v7 + v_ashrrev_i32_e32 v6, 1, v6 + v_ashrrev_i32_e32 v7, 31, v6 + v_lshl_add_u64 v[6:7], s[10:11], 0, v[6:7] + global_load_ubyte v8, v[6:7], off + global_load_ushort v9, v[2:3], off + s_bitcmp0_b32 s0, 0 + s_waitcnt vmcnt(1) + v_and_b32_e32 v6, 15, v8 + v_lshrrev_b32_e32 v7, 4, v8 + s_cselect_b64 vcc, -1, 0 + v_cndmask_b32_e32 v6, v6, v7, vcc + v_add_u32_e32 v6, -8, v6 + v_cvt_f32_i32_e32 v6, v6 + v_lshl_add_u64 v[2:3], v[2:3], 0, 2 + s_add_i32 s0, s0, 1 + s_cmp_eq_u32 s6, s0 + s_waitcnt vmcnt(0) + v_fma_mix_f32 v5, v9, v6, v5 op_sel_hi:[1,0,0] + s_cbranch_scc0 .LBB44_3 +; %bb.4: ; %._crit_edge.loopexit + v_cvt_f16_f32_e32 v1, v5 +.LBB44_5: ; %Flow + s_waitcnt lgkmcnt(0) + v_mov_b32_e32 v2, s12 + v_mov_b32_e32 v3, s13 + v_mad_u64_u32 v[4:5], s[0:1], v4, s3, v[0:1] + v_ashrrev_i32_e32 v5, 31, v4 + v_lshl_add_u64 v[2:3], v[4:5], 1, v[2:3] + global_store_short v[2:3], v1, off +.LBB44_6: + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .amdhsa_group_segment_fixed_size 0 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 304 + .amdhsa_user_sgpr_count 2 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 0 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 10 + .amdhsa_next_free_sgpr 14 + .amdhsa_accum_offset 12 + .amdhsa_reserve_vcc 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .section .text._ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,"axG",@progbits,_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii,comdat +.Lfunc_end44: + .size _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii, .Lfunc_end44-_ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + ; -- End function + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_vgpr, 10 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_agpr, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.numbered_sgpr, 14 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.num_named_barrier, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.private_seg_size, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_vcc, 1 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.uses_flat_scratch, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_dyn_sized_stack, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_recursion, 0 + .set _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 484 +; TotalNumSgprs: 20 +; NumVgprs: 10 +; NumAgprs: 0 +; TotalNumVgprs: 10 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 2 +; VGPRBlocks: 1 +; NumSGPRsForWavesPerEU: 20 +; NumVGPRsForWavesPerEU: 10 +; AccumOffset: 12 +; Occupancy: 8 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 2 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 2 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .section .AMDGPU.gpr_maximums,"",@progbits + .set amdgpu.max_num_vgpr, 0 + .set amdgpu.max_num_agpr, 0 + .set amdgpu.max_num_sgpr, 0 + .section .AMDGPU.csdata,"",@progbits + .protected _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E ; @_ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E + .type _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E,@object + .section .bss._ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E,"awG",@nobits,_ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E,comdat + .weak _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E + .p2align 2, 0x0 +_ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E: + .long 0 ; 0x0 + .size _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E, 4 + + .type __hip_cuid_189e97bb64f986de,@object ; @__hip_cuid_189e97bb64f986de + .section .bss,"aw",@nobits + .globl __hip_cuid_189e97bb64f986de +__hip_cuid_189e97bb64f986de: + .byte 0 ; 0x0 + .size __hip_cuid_189e97bb64f986de, 1 + + .ident "AMD clang version 22.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-7.2.0 26014 7b800a19466229b8479a78de19143dc33c3ab9b5)" + .section ".note.GNU-stack","",@progbits + .addrsig + .addrsig_sym _ZN7ck_tile21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS2_IJLi2ELi2ELi1EEEENS2_IJLi32ELi32ELi16EEEELb0ELb0EEEE2N_E + .addrsig_sym __hip_cuid_189e97bb64f986de + .amdgpu_metadata +--- +amdhsa.kernels: + - .agpr_count: 0 + .args: [] + .group_segment_fixed_size: 0 + .kernarg_segment_align: 4 + .kernarg_segment_size: 0 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _ZN7ck_tileL11flush_cacheEv + .private_segment_fixed_size: 0 + .sgpr_count: 6 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tileL11flush_cacheEv.kd + .uses_dynamic_stack: false + .vgpr_count: 0 + .vgpr_spill_count: 0 + .wavefront_size: 64 + - .agpr_count: 256 + .args: + - .offset: 0 + .size: 88 + .value_kind: by_value + .group_segment_fixed_size: 65536 + .kernarg_segment_align: 8 + .kernarg_segment_size: 88 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .private_segment_fixed_size: 0 + .sgpr_count: 34 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_DF16_fS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESF_NSE_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESJ_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_DF16_NS_5tupleIJEEEfDF16_SQ_SG_SJ_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.kd + .uses_dynamic_stack: false + .vgpr_count: 512 + .vgpr_spill_count: 0 + .wavefront_size: 64 + - .agpr_count: 0 + .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .offset: 24 + .size: 4 + .value_kind: by_value + - .offset: 28 + .size: 4 + .value_kind: by_value + - .offset: 32 + .size: 4 + .value_kind: by_value + - .offset: 36 + .size: 4 + .value_kind: by_value + - .offset: 40 + .size: 4 + .value_kind: by_value + - .offset: 44 + .size: 4 + .value_kind: by_value + - .offset: 48 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 52 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 56 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 60 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 62 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 64 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 66 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 68 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 70 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 88 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 96 + .size: 8 + .value_kind: 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_ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .private_segment_fixed_size: 16 + .sgpr_count: 33 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm11ColumnMajorESG_NSF_8RowMajorELi1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SH_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.kd + .uses_dynamic_stack: false + .vgpr_count: 512 + .vgpr_spill_count: 5 + .wavefront_size: 64 + - .agpr_count: 0 + .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .offset: 24 + .size: 4 + .value_kind: by_value + - .offset: 28 + .size: 4 + .value_kind: by_value + - .offset: 32 + .size: 4 + .value_kind: by_value + - .offset: 36 + .size: 4 + .value_kind: by_value + - .offset: 40 + .size: 4 + .value_kind: by_value + - .offset: 44 + .size: 4 + .value_kind: by_value + - .offset: 48 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 52 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 56 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 60 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 62 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 64 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 66 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 68 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 70 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 88 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 96 + .size: 8 + .value_kind: hidden_global_offset_y + - .offset: 104 + .size: 8 + .value_kind: hidden_global_offset_z + - .offset: 112 + .size: 2 + .value_kind: hidden_grid_dims + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 304 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii + .private_segment_fixed_size: 0 + .sgpr_count: 20 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm11ColumnMajorES4_NS3_8RowMajorEEEvPT_PT0_PT2_iiiiii.kd + .uses_dynamic_stack: false + .vgpr_count: 9 + .vgpr_spill_count: 0 + .wavefront_size: 64 + - .agpr_count: 256 + .args: + - .offset: 0 + .size: 88 + .value_kind: by_value + .group_segment_fixed_size: 49152 + .kernarg_segment_align: 8 + .kernarg_segment_size: 88 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 256 + .name: _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_ + .private_segment_fixed_size: 8 + .sgpr_count: 32 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tile6kentryILi1ENS_10GemmKernelINS_21GemmTile1DPartitionerINS_13TileGemmShapeINS_8sequenceIJLi256ELi256ELi64EEEENS4_IJLi2ELi2ELi1EEEENS4_IJLi32ELi32ELi16EEEELb0ELb0EEEEENS_28GemmPipelineAGmemBGmemCRegV1INS_23GemmPipelineProblemBaseIDF16_NS_9pk_int4_tEfS8_NS_14TileGemmTraitsILb0ELb0ELb0ENS_13tensor_layout4gemm8RowMajorENSF_11ColumnMajorESG_Li1EEEDF16_NS_12element_wise11PassThroughESK_Lb0ELi1ELi1EEENS_33UniversalGemmPipelineAgBgCrPolicyEEENS_16CShuffleEpilogueINS_23CShuffleEpilogueProblemIDF16_SC_NS_5tupleIJEEEfDF16_SR_SG_SK_Li256ELi256ELi2ELi2ELi32ELi32ELi16ELb0ELi1ELb0ELi1ELb0ELi1ELb0EEEvEEEEJNS_23UniversalGemmKernelArgsILi1ELi1ELi0EEEEEEvDpT1_.kd + .uses_dynamic_stack: false + .vgpr_count: 512 + .vgpr_spill_count: 1 + .wavefront_size: 64 + - .agpr_count: 0 + .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .offset: 24 + .size: 4 + .value_kind: by_value + - .offset: 28 + .size: 4 + .value_kind: by_value + - .offset: 32 + .size: 4 + .value_kind: by_value + - .offset: 36 + .size: 4 + .value_kind: by_value + - .offset: 40 + .size: 4 + .value_kind: by_value + - .offset: 44 + .size: 4 + .value_kind: by_value + - .offset: 48 + .size: 4 + .value_kind: hidden_block_count_x + - .offset: 52 + .size: 4 + .value_kind: hidden_block_count_y + - .offset: 56 + .size: 4 + .value_kind: hidden_block_count_z + - .offset: 60 + .size: 2 + .value_kind: hidden_group_size_x + - .offset: 62 + .size: 2 + .value_kind: hidden_group_size_y + - .offset: 64 + .size: 2 + .value_kind: hidden_group_size_z + - .offset: 66 + .size: 2 + .value_kind: hidden_remainder_x + - .offset: 68 + .size: 2 + .value_kind: hidden_remainder_y + - .offset: 70 + .size: 2 + .value_kind: hidden_remainder_z + - .offset: 88 + .size: 8 + .value_kind: hidden_global_offset_x + - .offset: 96 + .size: 8 + .value_kind: hidden_global_offset_y + - .offset: 104 + .size: 8 + .value_kind: hidden_global_offset_z + - .offset: 112 + .size: 2 + .value_kind: hidden_grid_dims + .group_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .kernarg_segment_size: 304 + .language: OpenCL C + .language_version: + - 2 + - 0 + .max_flat_workgroup_size: 1024 + .name: _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii + .private_segment_fixed_size: 0 + .sgpr_count: 20 + .sgpr_spill_count: 0 + .symbol: _ZN7ck_tile17naive_gemm_kernelIDF16_NS_9pk_int4_tEfDF16_NS_13tensor_layout4gemm8RowMajorENS3_11ColumnMajorES4_EEvPT_PT0_PT2_iiiiii.kd + .uses_dynamic_stack: false + .vgpr_count: 10 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.target: amdgcn-amd-amdhsa--gfx942 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py index dc07955c7ed8..98dd136b06ac 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py @@ -169,8 +169,8 @@ def shortenFileBase(splitGSU, kernel): def getKernelFileBase(splitGSU: bool, kernel): - if "CustomKernelName" in kernel and kernel["CustomKernelName"]: - fileBase = kernel["CustomKernelName"] + if "CustomKernel" in kernel and kernel["CustomKernel"]["name"]: + fileBase = kernel["CustomKernel"]["name"] else: fileBase = shortenFileBase(splitGSU, kernel) return fileBase diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index ce4adec12d0e..42081c964e45 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -367,7 +367,7 @@ def __init__( isaInfoMap, assembler.rocm_version ) - self._name = config["CustomKernelName"] if "CustomKernelName" in config and config["CustomKernelName"] else None + self._name = config["CustomKernel"]["name"] if "CustomKernel" in config and config["CustomKernel"]["name"] else None # these keys are copied from ProblemType to internal that may be overridden InternalKeys = ["UseSgprForGRO","VectorStore"] @@ -3118,7 +3118,7 @@ def subCheckLdsBlockSizePerPad(tc, idx): else: reject(state, printRejectionReason, "%s's padded address is inconisstent"%tc) - if(not (state["CustomKernelName"] and state["CustomKernelName"] != "")): #don't check the custom kernel. + if(not ("CustomKernel" in state and state["CustomKernel"]["name"] != "")): #don't check the custom kernel. checkLdsBlockSizePerPad("A") checkLdsBlockSizePerPad("B") diff --git a/projects/hipblaslt/tensilelite/Tensile/Tensile.py b/projects/hipblaslt/tensilelite/Tensile/Tensile.py index 591517238112..9d09128ec065 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tensile.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tensile.py @@ -198,7 +198,7 @@ def splitExtraParameters(par): argParser.add_argument("--runtime-language", dest="RuntimeLanguage", \ choices=["HIP", "OCL"], help="override which runtime language to use") argParser.add_argument("--code-object-version", dest="CodeObjectVersion", \ - choices=["4", "5", "V4", "V5", "default"], action="store", default="4", help="HSA code-object version") + choices=["4", "5", "6", "V4", "V5", "V6", "default"], action="store", default="4", help="HSA code-object version") argParser.add_argument("-v", "--verbose", action="store_true", \ help="set PrintLevel=2") argParser.add_argument("--debug", dest="debug", action="store_true", \ diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/ParseArguments.py b/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/ParseArguments.py index 9c0b735baf25..28e6574dadef 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/ParseArguments.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/ParseArguments.py @@ -76,7 +76,7 @@ def parseArguments(input: Optional[List[str]] = None) -> Dict[str, Any]: argParser.add_argument( "--code-object-version", dest="CodeObjectVersion", - choices=["4", "5", "V4", "V5", "default"], + choices=["4", "5", "V4", "V5", "6", "V6", "default"], default="4", action="store", ) diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py index c74e0de612db..9597e4de2ff6 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py @@ -49,7 +49,7 @@ def handleCustomKernel(sol: dict, isaInfoMap: Dict[IsaVersion, IsaInfo]) -> Tupl if not isCustomKernelConfig(sol): return sol, False - name = sol["CustomKernelName"] + name = sol["CustomKernel"]["name"] dir = CUSTOM_KERNEL_PATH config = getCustomKernelConfig(name, {}, dir) sol.update(config) @@ -89,7 +89,7 @@ def hasCustomKernel(file: Path) -> bool: with open(file, "r") as f: for line in f: l = line.strip() - if l.startswith("CustomKernelName:") and not l.endswith("''"): + if l.startswith("name:") and not l.endswith("''"): return True return False diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml new file mode 100644 index 000000000000..3247a92ac1df --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -0,0 +1,98 @@ +TestParameters: + marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + + # PrintTensorA: 1 + # PrintTensorB: 1 + # PrintTensorD: 2 + # PrintTensorRef: 2 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Batched: True + Activation: False + UseScaleAlphaVec: 0 + + - # BenchmarkProblemSizeGroup - Standard - All problem + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942" + args: [AddressB, AddressA, AddressD, AddressD, SizeFree1, SizeFree0, SizeSum, StrideB0, StrideA0, StrideD0, StrideD0, SizeFree2, DebugPattern, DebugPattern, DebugPattern, DebugPattern, DebugPattern, DebugPattern] + - MatrixInstruction: + - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 + - PreloadKernArgs: [False] + # - PrefetchGlobalRead: [2] + # - PrefetchLocalRead: [1] + - DepthU: [64] + - VectorWidthA: [-1] + - VectorWidthB: [-1] + - GlobalReadVectorWidthA: [-1] + - GlobalReadVectorWidthB: [-1] + - LocalReadVectorWidth: [-1] + - TransposeLDS: [-1] + - LdsBlockSizePerPadA: [-1] + - LdsBlockSizePerPadB: [-1] + - LdsPadA: [-1] + - LdsPadB: [-1] + - StaggerU: [16] + - StaggerUStride: [-1] + - WorkGroupMapping: [1] + - StaggerUMapping: [0] + - 1LDSBuffer: [-1] + - WorkGroupMappingXCC: [8] + - WorkGroupMappingXCCGroup: [-1] + - GlobalSplitU: [1] + - GlobalSplitUAlgorithm: ["MultipleBuffer"] + - GlobalReadPerMfma: [1] + - LocalWritePerMfma: [-1] + - StoreRemapVectorWidth: [0] + - StoreVectorWidth: [-1] + - SourceSwap: [1] + - NumElementsPerBatchStore: [16] + - ClusterLocalRead: [1] + - NonTemporalA: [0] + - NonTemporalB: [0] + - DirectToVgprA: [1] + - DirectToVgprB: [0] + # - WorkGroup: [[32,4,4]] + + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] + # - Exact: [256, 256, 1, 256] + - Exact: [2048, 4096, 1, 1024] + # - Exact: [3328, 4096, 1, 4096] + +LibraryLogic: + ScheduleName: "aquavanjaram" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx942" + LibraryType: "GridBased" \ No newline at end of file diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 222f08c1b14d..a5dc602e011e 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -70,7 +70,8 @@ namespace TensileLite StrideD1, // 15 Alpha, // 16 Beta, // 17 - Count, // 18 + DebugPattern, // 18 + Count, // 19 }; std::string toString(KernelArgumentType arg); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 77355f10d325..4313a00c6111 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -94,6 +94,8 @@ namespace TensileLite return "Alpha"; case KernelArgumentType::Beta: return "Beta"; + case KernelArgumentType::DebugPattern: + return "DebugPattern"; case KernelArgumentType::Count: break; } @@ -183,6 +185,10 @@ namespace TensileLite { t = KernelArgumentType::Beta; } + else if(strValue == toString(KernelArgumentType::DebugPattern)) + { + t = KernelArgumentType::DebugPattern; + } else { throw std::runtime_error(concatenate("Invalid argument type: ", strValue)); @@ -901,7 +907,7 @@ namespace TensileLite // then no Stream-K tiles are needed, all data-parallel uint32_t skTiles = sk.grid; // If not evenly divisible, determine number of Stream-K tiles - if(tiles % sk.grid != 0) + if(tiles % sk.grid != 0) { // Number of data-parallel tiles on each workgroup would be: // dpTilesPerWG = bigEnough ? (tiles - skTiles) / skGrid : 0; @@ -1549,16 +1555,18 @@ namespace TensileLite rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; // Temporarily set internal args manually - uint32_t gemmCount = 1; - gemmCount = gemmCount & 0x3FFFFFFF; - rv.args.template append("gemm_count", gemmCount); - uint32_t internalArg0 = 1048577; - rv.args.template append("internalArgs", internalArg0); - int32_t internalArg1 = 436731905; - rv.args.template append("internalArgs1", internalArg1); + // uint32_t gemmCount = 1; + // gemmCount = gemmCount & 0x3FFFFFFF; + // rv.args.template append("gemm_count", gemmCount); + // uint32_t internalArg0 = 1048577; + // rv.args.template append("internalArgs", internalArg0); + // int32_t internalArg1 = 436731905; + // rv.args.template append("internalArgs1", internalArg1); - uint32_t numWorkGroups = getNumWorkGroups(rv); - rv.args.template append("numWorkGroups", numWorkGroups); + // uint32_t numWorkGroups = getNumWorkGroups(rv); + // rv.args.template append("numWorkGroups", numWorkGroups); + + uint32_t debugPattern = 0xDB000001; for(auto arg : sizeMapping.customKernel.args) { @@ -1618,6 +1626,10 @@ namespace TensileLite case KernelArgumentType::Beta: rv.args.append("Beta", inputs.beta, problem.betaType()); break; + case KernelArgumentType::DebugPattern: + rv.args.template append("DebugPattern", debugPattern); + ++debugPattern; + break; default: throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); } From 2e14d65a1f1f93bfb29be302d8a08412b790cb58 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Thu, 26 Feb 2026 16:24:45 +0000 Subject: [PATCH 04/58] Initial custom RR kernel work --- ..._SwizzleTileSize_8fd6cc113dd5231a_gfx942.s | 20177 ++++++++++++++++ .../Tensile/Tests/custom/custom_rr.yaml | 97 + .../include/Tensile/ContractionSolution.hpp | 6 +- .../tensilelite/src/ContractionSolution.cpp | 147 + 4 files changed, 20426 insertions(+), 1 deletion(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s new file mode 100644 index 000000000000..465d85556eb6 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s @@ -0,0 +1,20177 @@ + // Tensor.Half.d2 0, (base=&0, lim=&8, sizes={&16 &24 }, strides={&32 &40 }) + // T_LOAD_TILED 1 Source 0 + // Tensor.Half.d2 2, (base=&48, lim=&56, sizes={&64 &72 }, strides={&80 &88 }) + // T_LOAD_TILED 3 Source 2 + // Tensor.Half.d2 4, (base=&96, lim=&104, sizes={&112 &120 }, strides={&128 &136 }) + // T_LOAD_TILED 5 Source 4 + // Scalar.Float.6 + // T_LOAD_SCALAR 7Source 6 + // Scalar.Float.8 + // T_LOAD_SCALAR 9Source 8 + // T_Mul 1 3 Value: Float + // T_EXECUTE 7 10 9 5 + // E_Mul 11, 9, 5 + // E_Mul 12, 7, 10 + // E_Add 13, 11, 12 + // Tensor.Half.d2 15, (base=&152, lim=&160, sizes={&168 &176 }, strides={&184 &192 }) + // T_EXECUTE 13 + // E_Cvt 16, 13 + // T_STORE_TILED 18 Source 16 Dest 15 + + // Tensor_0_pointer: PointerGlobal: Half(offset: 0, size: 8, read_write) + // Tensor_0_extent: Value: Int64(offset: 8, size: 8, read_only) + // Tensor_0_size_0: Value: Int64(offset: 16, size: 8, read_only) + // Tensor_0_size_1: Value: Int64(offset: 24, size: 8, read_only) + // Tensor_0_stride_0: Value: Int64(offset: 32, size: 8, read_only) + // Tensor_0_stride_1: Value: Int64(offset: 40, size: 8, read_only) + // Tensor_2_pointer: PointerGlobal: Half(offset: 48, size: 8, read_write) + // Tensor_2_extent: Value: Int64(offset: 56, size: 8, read_only) + // Tensor_2_size_0: Value: Int64(offset: 64, size: 8, read_only) + // Tensor_2_size_1: Value: Int64(offset: 72, size: 8, read_only) + // Tensor_2_stride_0: Value: Int64(offset: 80, size: 8, read_only) + // Tensor_2_stride_1: Value: Int64(offset: 88, size: 8, read_only) + // Tensor_4_pointer: PointerGlobal: Half(offset: 96, size: 8, read_write) + // Tensor_4_extent: Value: Int64(offset: 104, size: 8, read_only) + // Tensor_4_size_0: Value: Int64(offset: 112, size: 8, read_only) + // Tensor_4_size_1: Value: Int64(offset: 120, size: 8, read_only) + // Tensor_4_stride_0: Value: Int64(offset: 128, size: 8, read_only) + // Tensor_4_stride_1: Value: Int64(offset: 136, size: 8, read_only) + // user_Float_Value_6: Value: Float(offset: 144, size: 4, read_only) + // user_Float_Value_8: Value: Float(offset: 148, size: 4, read_only) + // Tensor_15_pointer: PointerGlobal: Half(offset: 152, size: 8, read_write) + // Tensor_15_extent: Value: Int64(offset: 160, size: 8, read_only) + // Tensor_15_size_0: Value: Int64(offset: 168, size: 8, read_only) + // Tensor_15_size_1: Value: Int64(offset: 176, size: 8, read_only) + // Tensor_15_stride_0: Value: Int64(offset: 184, size: 8, read_only) + // Tensor_15_stride_1: Value: Int64(offset: 192, size: 8, read_only) + +.amdgcn_target "amdgcn-amd-amdhsa--gfx942" +.set .amdgcn.next_free_vgpr, 0 +.set .amdgcn.next_free_sgpr, 0 +.text +.globl RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a +.p2align 8 +.type RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a,@function +// Allocated Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 +// Allocated Workgroup Index X: 1 SGPR (Value: UInt32): s2 +// Allocated Workgroup Index Y: 1 SGPR (Value: UInt32): s3 +// Allocated Packed Workitem Index: 1 VGPR (Value: Raw32): v0 +// Allocated Workitem Index X: 1 VGPR (Value: UInt32): v1 +// Allocated Workitem Index Y: 1 VGPR (Value: UInt32): v2 +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a: + + // Kernel Options: + // dsObserver: DSMEMObserver + // logLevel: Verbose + // alwaysWaitAfterLoad: false + // alwaysWaitAfterStore: false + // alwaysWaitBeforeBranch: false + // alwaysWaitZeroBeforeBarrier: false + // preloadKernelArguments: true + // maxACCVGPRs: 256 + // maxSGPRs: 102 + // maxVGPRs: 256 + // loadLocalWidth: 4 + // loadGlobalWidth: 8 + // storeLocalWidth: 4 + // storeGlobalWidth: 4 + // assertWaitCntState: true + // setNextFreeVGPRToMax: false + // deduplicateArguments: true + // lazyAddArguments: true + // minLaunchTimeExpressionComplexity: 20 + // maxConcurrentSubExpressions: 1 + // maxConcurrentControlOps: none + // enableFullDivision: false + // scaleSkipPermlane: None + // assertOpKind: NoOp + // removeSetCoordinate: false + + // Loading Kernel Arguments: + // KernelArg{Tensor_0_extent_0, Value: Int64, CommandArgument(Tensor_0_extent)I64(c 0), o:0, s:8} + // KernelArg{Tensor_0_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_0_pointer)PG(c 0), o:8, s:8} + // KernelArg{Tensor_2_extent_2, Value: Int64, CommandArgument(Tensor_2_extent)I64(c 0), o:16, s:8} + // KernelArg{Tensor_2_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_2_pointer)PG(c 0), o:24, s:8} + // KernelArg{Tensor_4_extent_4, Value: Int64, CommandArgument(Tensor_4_extent)I64(c 0), o:32, s:8} + // KernelArg{Tensor_4_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_4_pointer)PG(c 0), o:40, s:8} + // KernelArg{user_Float_Value_6, Value: Float, CommandArgument(user_Float_Value_6)S(c 0), o:48, s:4} + // KernelArg{user_Float_Value_8, Value: Float, CommandArgument(user_Float_Value_8)S(c 0), o:52, s:4} + // KernelArg{Tensor_0_stride_0_9, Value: Int64, CommandArgument(Tensor_0_stride_0)I64(c 0), o:56, s:8} + // KernelArg{Tensor_0_size_1_10, Value: Int64, CommandArgument(Tensor_0_size_1)I64(c 0), o:64, s:8} + // KernelArg{Tensor_2_stride_1_12, Value: Int64, CommandArgument(Tensor_2_stride_1)I64(c 0), o:72, s:8} + // KernelArg{Tensor_4_stride_1_13, Value: Int64, CommandArgument(Tensor_4_stride_1)I64(c 0), o:80, s:8} + // KernelArg{Tensor_15_stride_1_14, Value: Int64, CommandArgument(Tensor_15_stride_1)I64(c 0), o:88, s:8} + // KernelArg{Tensor_15_extent_15, Value: Int64, CommandArgument(Tensor_15_extent)I64(c 0), o:96, s:8} + // KernelArg{Tensor_15_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_15_pointer)PG(c 0), o:104, s:8} + +s_load_dwordx2 s[4:5], s[0:1], 0 // Load scalar value +s_load_dwordx2 s[6:7], s[0:1], 8 // Load scalar value +s_load_dwordx2 s[8:9], s[0:1], 16 // Load scalar value +s_load_dwordx2 s[10:11], s[0:1], 24 // Load scalar value +s_load_dwordx2 s[12:13], s[0:1], 32 // Load scalar value +s_load_dwordx2 s[14:15], s[0:1], 40 // Load scalar value +s_load_dword s16, s[0:1], 48 // Load scalar value +s_load_dword s17, s[0:1], 52 // Load scalar value +s_load_dwordx2 s[18:19], s[0:1], 56 // Load scalar value +s_load_dwordx2 s[20:21], s[0:1], 64 // Load scalar value +s_load_dwordx2 s[22:23], s[0:1], 72 // Load scalar value +s_load_dwordx2 s[24:25], s[0:1], 80 // Load scalar value +s_load_dwordx2 s[26:27], s[0:1], 88 // Load scalar value +s_load_dwordx2 s[28:29], s[0:1], 96 // Load scalar value +s_load_dwordx2 s[30:31], s[0:1], 104 // Load scalar value + // Extract 10 bit X coordinate +v_bfe_u32 v1, v0, 0, 10 + // Generate {Workitem Index X: v1:U32} into Workitem Index X: VGPR Value: UInt32 x 1: v1 + // reg expression + // Extract 10 bit Y coordinate +v_bfe_u32 v2, v0, 10, 10 + // Generate {Workitem Index Y: v2:U32} into Workitem Index Y: VGPR Value: UInt32 x 1: v2 + // reg expression + // Freeing Packed Workitem Index: 1 VGPR (Value: Raw32): v0 + + // Freeing Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 + + // Marking Workgroup Index X: SGPR Value: UInt32 x 1: s2 as read-only + // Marking Workgroup Index Y: SGPR Value: UInt32 x 1: s3 as read-only + // Marking Workitem Index X: VGPR Value: UInt32 x 1: v1 as read-only + // Marking Workitem Index Y: VGPR Value: UInt32 x 1: v2 as read-only + // CodeGeneratorVisitor::generate() begin + // IdentifyParallelDimensions + // OrderMemory + // UpdateParameters + // AddLDS + // LowerLinear + // LowerTile + // LowerTensorContraction + // Simplify + // AddLDSPadding + // ConstantPropagation + // FuseExpressions + // ConnectWorkgroups + // WorkgroupRemapXCC + // UnrollLoops + // FuseLoops + // RemoveDuplicates + // OrderEpilogueBlocks + // Simplify + // CleanLoops + // SwizzleScale + // AddPrefetch + // AddF6LDSPadding + // AddDirect2LDS + // Simplify + // AddPRNG + // UpdateWavefrontParameters + // AssignIndexExpressions + // LoadPacked + // AddConvert + // NopExtraScopes + // InlineInits + // InlineIncrements + // RemoveImplicitScheduling + // OrderMultiplyNodes + // Simplify + // ScheduleMultiplyAndLDS + // Simplify + // OrderExchangeNodes + // AliasDataFlowTags + // AddLDSBarriers + // AddDeallocateDataFlow + // CleanArguments + // AddDeallocateArguments + // MergeAdjacentDeallocates + // Simplify + // SetWorkitemCount + // generate({1}) + // Kernel(1) BEGIN + // (op 1) generate({}) + // (op 1) end: generate({}) + // (op 1) generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) + // (op 1) NOP(1239) BEGIN + // (op 1239) generate({}) + // (op 1239) end: generate({}) + // (op 1) NOP(1239) END + // (op 1) NOP(1291) BEGIN + // (op 1291) generate({}) + // (op 1291) end: generate({}) + // (op 1) NOP(1291) END + // (op 1) NOP(1364) BEGIN + // (op 1364) generate({}) + // (op 1364) end: generate({}) + // (op 1) NOP(1364) END + // (op 1) NOP(1403) BEGIN + // (op 1403) generate({}) + // (op 1403) end: generate({}) + // (op 1) NOP(1403) END + // (op 1) NOP(1442) BEGIN + // (op 1442) generate({}) + // (op 1442) end: generate({}) + // (op 1) NOP(1442) END + // (op 1) NOP(1481) BEGIN + // (op 1481) generate({}) + // (op 1481) end: generate({}) + // (op 1) NOP(1481) END + // (op 1) NOP(1520) BEGIN + // (op 1520) generate({}) + // (op 1520) end: generate({}) + // (op 1) NOP(1520) END + // (op 1) NOP(1559) BEGIN + // (op 1559) generate({}) + // (op 1559) end: generate({}) + // (op 1) NOP(1559) END + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) BEGIN + // (op 1243) Assign dim(530) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 530: v**UNALLOCATED** + // (op 1243) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag530: VGPR Value: UInt32 x 1: (unallocated) + // (op 1243) reg expression + // (op 1243) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) BEGIN + // (op 1295) Assign dim(546) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 546: v**UNALLOCATED** + // (op 1295) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag546: VGPR Value: UInt32 x 1: (unallocated) + // (op 1295) reg expression + // (op 1295) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) BEGIN + // (op 1368) Assign dim(568) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 568: v**UNALLOCATED** + // (op 1368) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag568: VGPR Value: UInt32 x 1: (unallocated) + // (op 1368) reg expression + // (op 1368) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) BEGIN + // (op 1407) Assign dim(580) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 580: v**UNALLOCATED** + // (op 1407) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag580: VGPR Value: UInt32 x 1: (unallocated) + // (op 1407) reg expression + // (op 1407) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) BEGIN + // (op 1446) Assign dim(592) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 592: v**UNALLOCATED** + // (op 1446) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag592: VGPR Value: UInt32 x 1: (unallocated) + // (op 1446) reg expression + // (op 1446) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) BEGIN + // (op 1485) Assign dim(604) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 604: v**UNALLOCATED** + // (op 1485) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag604: VGPR Value: UInt32 x 1: (unallocated) + // (op 1485) reg expression + // (op 1485) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) BEGIN + // (op 1524) Assign dim(616) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 616: v**UNALLOCATED** + // (op 1524) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag616: VGPR Value: UInt32 x 1: (unallocated) + // (op 1524) reg expression + // (op 1524) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) BEGIN + // (op 1563) Assign dim(628) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 628: v**UNALLOCATED** + // (op 1563) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag628: VGPR Value: UInt32 x 1: (unallocated) + // (op 1563) reg expression + // (op 1563) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 +v_lshrrev_b32 v0, 7, v1 // (op 1243) + // (op 1243) BEGIN: Flatten[1] + // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 +v_and_b32 v3, 31, v1 // (op 1243) + // (op 1243) END: Flatten[1] + // (op 1243) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v4 +v_lshl_add_u32 v4, v0, 5, v3 // (op 1243) + // (op 1243) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v3 + + // Freeing : 1 VGPR (Value: UInt32) (op 1243): v0 + + // (op 1243) BEGIN: Flatten[1] + // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 +v_and_b32 v0, 63, v1 // (op 1243) + // (op 1243) END: Flatten[1] + // (op 1243) LogicalShiftR({Flatten[1]: v0:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 +v_lshrrev_b32 v3, 5, v0 // (op 1243) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v0 + + // (op 1243) BEGIN: TileTile + // (op 1243) {TileTile: ShiftL(v3:U32, 2:U32)U32} + // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1243) value (VGPR Value: UInt32 x 1: v3) + // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 +v_lshlrev_b32 v0, 2, v3 // (op 1243) + // (op 1243) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1243): v3 + + // (op 1243) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 +v_lshl_add_u32 v3, v4, 6, v0 // (op 1243) + // (op 1243) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1243): v0 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v4 + + // (op 1243) ShiftL({Tile: v3:U32}, 1:U32)U32 + // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1243) value (Tile: VGPR Value: UInt32 x 1: v3) + // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 +v_lshlrev_b32 v0, 1, v3 // (op 1243) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v3 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) END +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_lshrrev_b32 v3, 6, v1 // (op 1295) + // (op 1295) BEGIN: Tile + // (op 1295) {Tile: BitwiseAnd(v3:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 +v_and_b32 v4, 1, v3 // (op 1295) + // (op 1295) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1295): v3 + + // (op 1295) BEGIN: Flatten[1] + // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_and_b32 v3, 31, v1 // (op 1295) + // (op 1295) END: Flatten[1] + // (op 1295) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v5 +v_lshl_add_u32 v5, v4, 5, v3 // (op 1295) + // (op 1295) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v3 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v4 + + // (op 1295) BEGIN: Flatten[1] + // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_and_b32 v3, 63, v1 // (op 1295) + // (op 1295) END: Flatten[1] + // (op 1295) LogicalShiftR({Flatten[1]: v3:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 +v_lshrrev_b32 v4, 5, v3 // (op 1295) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v3 + + // (op 1295) BEGIN: TileTile + // (op 1295) {TileTile: ShiftL(v4:U32, 2:U32)U32} + // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1295) value (VGPR Value: UInt32 x 1: v4) + // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_lshlrev_b32 v3, 2, v4 // (op 1295) + // (op 1295) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1295): v4 + + // (op 1295) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 +v_lshl_add_u32 v4, v5, 6, v3 // (op 1295) + // (op 1295) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1295): v3 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v5 + + // (op 1295) ShiftL({Tile: v4:U32}, 1:U32)U32 + // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1295) value (Tile: VGPR Value: UInt32 x 1: v4) + // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v3 +v_lshlrev_b32 v3, 1, v4 // (op 1295) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v4 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) END +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 +v_lshrrev_b32 v4, 7, v1 // (op 1368) + // (op 1368) BEGIN: Flatten[1] + // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 +v_and_b32 v5, 31, v1 // (op 1368) + // (op 1368) END: Flatten[1] + // (op 1368) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v6 +v_lshl_add_u32 v6, v4, 5, v5 // (op 1368) + // (op 1368) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v5 + + // Freeing : 1 VGPR (Value: UInt32) (op 1368): v4 + + // (op 1368) BEGIN: Flatten[1] + // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 +v_and_b32 v4, 63, v1 // (op 1368) + // (op 1368) END: Flatten[1] + // (op 1368) LogicalShiftR({Flatten[1]: v4:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 +v_lshrrev_b32 v5, 5, v4 // (op 1368) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v4 + + // (op 1368) BEGIN: TileTile + // (op 1368) {TileTile: ShiftL(v5:U32, 2:U32)U32} + // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1368) value (VGPR Value: UInt32 x 1: v5) + // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 +v_lshlrev_b32 v4, 2, v5 // (op 1368) + // (op 1368) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1368): v5 + + // (op 1368) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 +v_lshl_add_u32 v5, v6, 6, v4 // (op 1368) + // (op 1368) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1368): v4 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v6 + + // (op 1368) ShiftL({Tile: v5:U32}, 1:U32)U32 + // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1368) value (Tile: VGPR Value: UInt32 x 1: v5) + // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v4 +v_lshlrev_b32 v4, 1, v5 // (op 1368) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v5 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) END +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_lshrrev_b32 v5, 6, v1 // (op 1407) + // (op 1407) BEGIN: Tile + // (op 1407) {Tile: BitwiseAnd(v5:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 +v_and_b32 v6, 1, v5 // (op 1407) + // (op 1407) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1407): v5 + + // (op 1407) BEGIN: Flatten[1] + // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_and_b32 v5, 31, v1 // (op 1407) + // (op 1407) END: Flatten[1] + // (op 1407) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v7 +v_lshl_add_u32 v7, v6, 5, v5 // (op 1407) + // (op 1407) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v5 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v6 + + // (op 1407) BEGIN: Flatten[1] + // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_and_b32 v5, 63, v1 // (op 1407) + // (op 1407) END: Flatten[1] + // (op 1407) LogicalShiftR({Flatten[1]: v5:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 +v_lshrrev_b32 v6, 5, v5 // (op 1407) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v5 + + // (op 1407) BEGIN: TileTile + // (op 1407) {TileTile: ShiftL(v6:U32, 2:U32)U32} + // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1407) value (VGPR Value: UInt32 x 1: v6) + // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_lshlrev_b32 v5, 2, v6 // (op 1407) + // (op 1407) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1407): v6 + + // (op 1407) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 +v_lshl_add_u32 v6, v7, 6, v5 // (op 1407) + // (op 1407) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1407): v5 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v7 + + // (op 1407) ShiftL({Tile: v6:U32}, 1:U32)U32 + // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1407) value (Tile: VGPR Value: UInt32 x 1: v6) + // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v5 +v_lshlrev_b32 v5, 1, v6 // (op 1407) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v6 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) END +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 +v_lshrrev_b32 v6, 7, v1 // (op 1446) + // (op 1446) BEGIN: Flatten[1] + // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 +v_and_b32 v7, 31, v1 // (op 1446) + // (op 1446) END: Flatten[1] + // (op 1446) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v8 +v_lshl_add_u32 v8, v6, 5, v7 // (op 1446) + // (op 1446) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v7 + + // Freeing : 1 VGPR (Value: UInt32) (op 1446): v6 + + // (op 1446) BEGIN: Flatten[1] + // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 +v_and_b32 v6, 63, v1 // (op 1446) + // (op 1446) END: Flatten[1] + // (op 1446) LogicalShiftR({Flatten[1]: v6:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 +v_lshrrev_b32 v7, 5, v6 // (op 1446) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v6 + + // (op 1446) BEGIN: TileTile + // (op 1446) {TileTile: ShiftL(v7:U32, 2:U32)U32} + // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1446) value (VGPR Value: UInt32 x 1: v7) + // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 +v_lshlrev_b32 v6, 2, v7 // (op 1446) + // (op 1446) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1446): v7 + + // (op 1446) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 +v_lshl_add_u32 v7, v8, 6, v6 // (op 1446) + // (op 1446) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1446): v6 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v8 + + // (op 1446) ShiftL({Tile: v7:U32}, 1:U32)U32 + // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1446) value (Tile: VGPR Value: UInt32 x 1: v7) + // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v6 +v_lshlrev_b32 v6, 1, v7 // (op 1446) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v7 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) END +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_lshrrev_b32 v7, 6, v1 // (op 1485) + // (op 1485) BEGIN: Tile + // (op 1485) {Tile: BitwiseAnd(v7:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 +v_and_b32 v8, 1, v7 // (op 1485) + // (op 1485) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1485): v7 + + // (op 1485) BEGIN: Flatten[1] + // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_and_b32 v7, 31, v1 // (op 1485) + // (op 1485) END: Flatten[1] + // (op 1485) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v9 +v_lshl_add_u32 v9, v8, 5, v7 // (op 1485) + // (op 1485) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v7 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v8 + + // (op 1485) BEGIN: Flatten[1] + // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_and_b32 v7, 63, v1 // (op 1485) + // (op 1485) END: Flatten[1] + // (op 1485) LogicalShiftR({Flatten[1]: v7:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 +v_lshrrev_b32 v8, 5, v7 // (op 1485) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v7 + + // (op 1485) BEGIN: TileTile + // (op 1485) {TileTile: ShiftL(v8:U32, 2:U32)U32} + // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1485) value (VGPR Value: UInt32 x 1: v8) + // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_lshlrev_b32 v7, 2, v8 // (op 1485) + // (op 1485) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1485): v8 + + // (op 1485) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 +v_lshl_add_u32 v8, v9, 6, v7 // (op 1485) + // (op 1485) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1485): v7 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v9 + + // (op 1485) ShiftL({Tile: v8:U32}, 1:U32)U32 + // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1485) value (Tile: VGPR Value: UInt32 x 1: v8) + // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v7 +v_lshlrev_b32 v7, 1, v8 // (op 1485) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v8 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) END +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 +v_lshrrev_b32 v8, 7, v1 // (op 1524) + // (op 1524) BEGIN: Flatten[1] + // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 +v_and_b32 v9, 31, v1 // (op 1524) + // (op 1524) END: Flatten[1] + // (op 1524) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v10 +v_lshl_add_u32 v10, v8, 5, v9 // (op 1524) + // (op 1524) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v9 + + // Freeing : 1 VGPR (Value: UInt32) (op 1524): v8 + + // (op 1524) BEGIN: Flatten[1] + // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 +v_and_b32 v8, 63, v1 // (op 1524) + // (op 1524) END: Flatten[1] + // (op 1524) LogicalShiftR({Flatten[1]: v8:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 +v_lshrrev_b32 v9, 5, v8 // (op 1524) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v8 + + // (op 1524) BEGIN: TileTile + // (op 1524) {TileTile: ShiftL(v9:U32, 2:U32)U32} + // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1524) value (VGPR Value: UInt32 x 1: v9) + // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 +v_lshlrev_b32 v8, 2, v9 // (op 1524) + // (op 1524) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1524): v9 + + // (op 1524) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 +v_lshl_add_u32 v9, v10, 6, v8 // (op 1524) + // (op 1524) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1524): v8 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v10 + + // (op 1524) ShiftL({Tile: v9:U32}, 1:U32)U32 + // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1524) value (Tile: VGPR Value: UInt32 x 1: v9) + // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v8 +v_lshlrev_b32 v8, 1, v9 // (op 1524) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v9 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_lshrrev_b32 v9, 6, v1 // (op 1563) + // (op 1563) BEGIN: Tile + // (op 1563) {Tile: BitwiseAnd(v9:U32, 1:U32)U32} + // (op 1) Deallocate{}(1913) BEGIN + // (op 1913) Deallocate 84 + // Deleting tag 84 + // (op 1) Deallocate{}(1913) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 +v_and_b32 v10, 1, v9 // (op 1563) + // (op 1563) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1563): v9 + + // (op 1563) BEGIN: Flatten[1] + // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1) Assign VGPR 16:U32(1244) BEGIN + // (op 1244) Assign dim(531) = 16:U32 + // (op 1244) Assign stride expression + // (op 1) Assign VGPR 16:U32(1244) END + // (op 1) Assign VGPR 16:U32(1369) BEGIN + // (op 1369) Assign dim(569) = 16:U32 + // (op 1369) Assign stride expression + // (op 1) Assign VGPR 16:U32(1369) END + // (op 1) Assign VGPR 16:U32(1447) BEGIN + // (op 1447) Assign dim(593) = 16:U32 + // (op 1447) Assign stride expression + // (op 1) Assign VGPR 16:U32(1447) END + // (op 1) Assign VGPR 16:U32(1525) BEGIN + // (op 1525) Assign dim(617) = 16:U32 + // (op 1525) Assign stride expression + // (op 1) Assign VGPR 16:U32(1525) END + // (op 1) NOP(1240) BEGIN + // (op 1240) generate({}) + // (op 1240) end: generate({}) + // (op 1) NOP(1240) END + // (op 1) NOP(1365) BEGIN + // (op 1365) generate({}) + // (op 1365) end: generate({}) + // (op 1) NOP(1365) END + // (op 1) NOP(1443) BEGIN + // (op 1443) generate({}) + // (op 1443) end: generate({}) + // (op 1) NOP(1443) END + // (op 1) NOP(1521) BEGIN + // (op 1521) generate({}) + // (op 1521) end: generate({}) + // (op 1) NOP(1521) END + // (op 1) Assign VGPR 2:U32(1248) BEGIN + // (op 1248) Assign dim(533) = 2:U32 + // (op 1248) Assign stride expression + // (op 1) Assign VGPR 2:U32(1248) END + // (op 1) Assign VGPR 2:U32(1373) BEGIN + // (op 1373) Assign dim(571) = 2:U32 + // (op 1373) Assign stride expression + // (op 1) Assign VGPR 2:U32(1373) END + // (op 1) Assign VGPR 2:U32(1451) BEGIN + // (op 1451) Assign dim(595) = 2:U32 + // (op 1451) Assign stride expression + // (op 1) Assign VGPR 2:U32(1451) END + // (op 1) Assign VGPR 2:U32(1529) BEGIN + // (op 1529) Assign dim(619) = 2:U32 + // (op 1529) Assign stride expression + // (op 1) Assign VGPR 2:U32(1529) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_and_b32 v9, 31, v1 // (op 1563) + // (op 1563) END: Flatten[1] + // (op 1563) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v11 +v_lshl_add_u32 v11, v10, 5, v9 // (op 1563) + // (op 1563) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v9 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v10 + + // (op 1563) BEGIN: Flatten[1] + // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_and_b32 v9, 63, v1 // (op 1563) + // (op 1563) END: Flatten[1] + // (op 1563) LogicalShiftR({Flatten[1]: v9:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 +v_lshrrev_b32 v10, 5, v9 // (op 1563) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v9 + + // (op 1563) BEGIN: TileTile + // (op 1563) {TileTile: ShiftL(v10:U32, 2:U32)U32} + // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1563) value (VGPR Value: UInt32 x 1: v10) + // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_lshlrev_b32 v9, 2, v10 // (op 1563) + // (op 1563) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1563): v10 + + // (op 1563) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 +v_lshl_add_u32 v10, v11, 6, v9 // (op 1563) + // (op 1563) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1563): v9 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v11 + + // (op 1563) ShiftL({Tile: v10:U32}, 1:U32)U32 + // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1563) value (Tile: VGPR Value: UInt32 x 1: v10) + // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v9 +v_lshlrev_b32 v9, 1, v10 // (op 1563) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v10 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) END + // (op 1) Deallocate{}(1918) BEGIN + // (op 1918) Deallocate 144 + // Deleting tag 144 + // (op 1) Deallocate{}(1918) END + // (op 1) Assign VGPR 16:U32(1296) BEGIN + // (op 1296) Assign dim(547) = 16:U32 + // (op 1296) Assign stride expression + // (op 1) Assign VGPR 16:U32(1296) END + // (op 1) Assign VGPR 16:U32(1408) BEGIN + // (op 1408) Assign dim(581) = 16:U32 + // (op 1408) Assign stride expression + // (op 1) Assign VGPR 16:U32(1408) END + // (op 1) Assign VGPR 16:U32(1486) BEGIN + // (op 1486) Assign dim(605) = 16:U32 + // (op 1486) Assign stride expression + // (op 1) Assign VGPR 16:U32(1486) END + // (op 1) Assign VGPR 16:U32(1564) BEGIN + // (op 1564) Assign dim(629) = 16:U32 + // (op 1564) Assign stride expression + // (op 1) Assign VGPR 16:U32(1564) END + // (op 1) NOP(1292) BEGIN + // (op 1292) generate({}) + // (op 1292) end: generate({}) + // (op 1) NOP(1292) END + // (op 1) NOP(1404) BEGIN + // (op 1404) generate({}) + // (op 1404) end: generate({}) + // (op 1) NOP(1404) END + // (op 1) NOP(1482) BEGIN + // (op 1482) generate({}) + // (op 1482) end: generate({}) + // (op 1) NOP(1482) END + // (op 1) NOP(1560) BEGIN + // (op 1560) generate({}) + // (op 1560) end: generate({}) + // (op 1) NOP(1560) END + // (op 1) Assign VGPR 2:U32(1300) BEGIN + // (op 1300) Assign dim(549) = 2:U32 + // (op 1300) Assign stride expression + // (op 1) Assign VGPR 2:U32(1300) END + // (op 1) Assign VGPR 2:U32(1412) BEGIN + // (op 1412) Assign dim(583) = 2:U32 + // (op 1412) Assign stride expression + // (op 1) Assign VGPR 2:U32(1412) END + // (op 1) Assign VGPR 2:U32(1490) BEGIN + // (op 1490) Assign dim(607) = 2:U32 + // (op 1490) Assign stride expression + // (op 1) Assign VGPR 2:U32(1490) END + // (op 1) Assign VGPR 2:U32(1568) BEGIN + // (op 1568) Assign dim(631) = 2:U32 + // (op 1568) Assign stride expression + // (op 1) Assign VGPR 2:U32(1568) END + // (op 1) LoadVGPR Value: Float(2) BEGIN + // tag 24: v**UNALLOCATED** + // (op 2) GEN: LoadVGPR; scalar value + // (op 2) Get arg user_Float_Value_8 + // (op 1) LoadVGPR Value: Float(24) BEGIN + // tag 33: v**UNALLOCATED** + // (op 24) GEN: LoadVGPR; scalar value + // (op 24) Get arg user_Float_Value_6 +// Allocated : 1 VGPR (Value: Float) (op 2): v10 +s_waitcnt lgkmcnt(0) +v_mov_b32 v10, s17 // (op 2) Move value + // (op 1) LoadVGPR Value: Float(2) END +// Allocated : 1 VGPR (Value: Float) (op 24): v11 +v_mov_b32 v11, s16 // (op 24) Move value + // (op 1) LoadVGPR Value: Float(24) END + // (op 1) Deallocate{user_Float_Value_8}(1997) BEGIN + // (op 1997) Deallocate user_Float_Value_8 + // Freeing user_Float_Value_8: 1 SGPR (Value: Raw32): s17 + + // (op 1) Deallocate{user_Float_Value_8}(1997) END + // (op 1) Deallocate{user_Float_Value_6}(1999) BEGIN + // (op 1999) Deallocate user_Float_Value_6 + // Freeing user_Float_Value_6: 1 SGPR (Value: Raw32): s16 + + // (op 1) Deallocate{user_Float_Value_6}(1999) END + // (op 1) Scope(670) BEGIN + // (op 670) Lock Scope 670 + // Lock Branch + // (op 670) generate({675}) + // (op 670) NOP(675) BEGIN + // (op 675) generate({}) + // (op 675) end: generate({}) + // (op 670) NOP(675) END + // (op 670) Assign ACCVGPR 0.00000:S(44) BEGIN + // (op 44) Assign dim(35) = 0.00000:S + // tag 35: a**UNALLOCATED** + // (op 44) Generate 0.00000:S into DataFlowTag35: ACCVGPR Value: Float x 16: (unallocated) +// Allocated DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 +v_accvgpr_write a0, 0.00000 // (op 44) call() +v_accvgpr_write a1, 0.00000 // (op 44) call() +v_accvgpr_write a2, 0.00000 // (op 44) call() +v_accvgpr_write a3, 0.00000 // (op 44) call() +v_accvgpr_write a4, 0.00000 // (op 44) call() +v_accvgpr_write a5, 0.00000 // (op 44) call() +v_accvgpr_write a6, 0.00000 // (op 44) call() +v_accvgpr_write a7, 0.00000 // (op 44) call() +v_accvgpr_write a8, 0.00000 // (op 44) call() +v_accvgpr_write a9, 0.00000 // (op 44) call() +v_accvgpr_write a10, 0.00000 // (op 44) call() +v_accvgpr_write a11, 0.00000 // (op 44) call() +v_accvgpr_write a12, 0.00000 // (op 44) call() +v_accvgpr_write a13, 0.00000 // (op 44) call() +v_accvgpr_write a14, 0.00000 // (op 44) call() +v_accvgpr_write a15, 0.00000 // (op 44) call() + // (op 670) Assign ACCVGPR 0.00000:S(44) END + // (op 670) Scope(1074) BEGIN + // (op 1074) Lock Scope 1074 + // Lock Branch + // (op 1074) generate({1069}) + // (op 1074) NOP(1069) BEGIN + // (op 1069) generate({}) + // (op 1069) end: generate({}) + // (op 1074) NOP(1069) END + // (op 1074) Assign VGPR 128:U64(1079) BEGIN + // (op 1079) Assign dim(482) = 128:U64 + // (op 1079) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1079) END + // (op 1074) NOP(1070) BEGIN + // (op 1070) generate({}) + // (op 1070) end: generate({}) + // (op 1074) NOP(1070) END + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) BEGIN + // (op 1082) Assign dim(483) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 + // tag 483: v**UNALLOCATED** + // (op 1082) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag483: VGPR Value: UInt64 x 1: (unallocated) + // (op 1082) Get arg Tensor_0_stride_0_9 + // (op 1082) reg expression + // (op 1082) reg expression + // (op 1082) reg expression + // (op 1082) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 +v_lshrrev_b32 v12, 5, v1 // (op 1082) + // (op 1082) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v13 +v_lshl_add_u32 v13, s2, 6, v12 // (op 1082) + // (op 1082) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1082): v12 + + // (op 1082) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 +v_and_b32 v12, -32, v1 // (op 1082) + // (op 1082) BEGIN: Flatten[1] + // (op 1082) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v14 +v_sub_u32 v14, v1, v12 // (op 1082) + // (op 1082) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1082): v12 + + // (op 1082) BEGIN: TileTile + // (op 1082) {TileTile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} + // (op 1082) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1082) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) + // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 +v_lshlrev_b32 v12, 1, v14 // (op 1082) + // (op 1082) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1082): v14 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 +v_mov_b32 v15, 0 // (op 1082) convert +v_mov_b32 v14, v12 // (op 1082) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1082): v12 + + // (op 1082) BEGIN: Split + // (op 1082) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1082) lhs (Tile: VGPR Value: UInt32 x 1: v13) + // (op 1082) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1082): v16, v17 +v_mul_lo_u32 v17, v13, s19 // (op 1082) most significant: low of low * high + // (op 1082) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1082): v12 +v_mul_hi_u32 v12, v13, s18 // (op 1082) most significant: high of low * low +v_mul_lo_u32 v16, v13, s18 // (op 1082) least significant: low of low * low +v_add_u32 v17, v17, v12 // (op 1082) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1082): v12 + + // (op 1082) Add: dest (VGPR Value: UInt64 x 1: v[16:17]) = + // (op 1082) lhs (VGPR Value: UInt64 x 1: v[16:17]) + // (op 1082) rhs (TileTile: VGPR Value: UInt64 x 1: v[14:15]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 +v_add_co_u32 v16, s[0:1], v16, v14 // (op 1082) least significant half +v_addc_co_u32 v17, s[0:1], v17, v15, s[0:1] // (op 1082) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 + + // (op 1082) END: Split + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1082): v13 + + // (op 1082) ShiftL({Split: v[16:17]:U64}, 1:U32)U64 + // (op 1082) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1082) value (Split: VGPR Value: UInt64 x 1: v[16:17]) + // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v12, v13 +v_lshlrev_b64 v[12:13], 1, v[16:17] // (op 1082) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1082): v16, v17 + + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) BEGIN + // (op 1083) Assign dim(484) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1083) Assign stride expression + // (op 1074) Tag 1083non referenced extraArgs = {Tensor_0_stride_0_9} + + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) END + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) BEGIN + // (op 1084) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 477: s**UNALLOCATED** + // (op 1084) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: (unallocated) + // (op 1084) Get arg Tensor_0_pointer + // (op 1084) Get arg Tensor_0_extent_0 + // (op 1084) reg expression + // (op 1084) reg expression + // (op 1084) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1084) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1084) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1084) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1084): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1084) + // (op 1084) reg expression +// Allocated DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 +s_mov_b32 s32, s6 // (op 1084) reg expression +s_mov_b32 s33, s7 // (op 1084) reg expression +s_mov_b32 s34, s0 // (op 1084) reg expression +s_mov_b32 s35, 131072 // (op 1084) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1084): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) END + // (op 1074) NOP(1071) BEGIN + // (op 1071) generate({}) + // (op 1071) end: generate({}) + // (op 1074) NOP(1071) END + // (op 1074) Assign VGPR 2:U64(1089) BEGIN + // (op 1089) Assign dim(486) = 2:U64 + // (op 1089) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1089) END + // (op 1074) NOP(1092) BEGIN + // (op 1092) generate({}) + // (op 1092) end: generate({}) + // (op 1074) NOP(1092) END + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) BEGIN + // (op 1101) Assign dim(487) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 + // tag 487: v**UNALLOCATED** + // (op 1101) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: (unallocated) + // (op 1101) Get arg Tensor_0_stride_0_9 + // (op 1101) reg expression + // (op 1101) reg expression + // (op 1101) reg expression + // (op 1101) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 +v_lshrrev_b32 v14, 5, v1 // (op 1101) + // (op 1101) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v15 +v_lshl_add_u32 v15, s2, 6, v14 // (op 1101) + // (op 1101) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1101): v14 + + // (op 1101) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 +v_and_b32 v14, -32, v1 // (op 1101) + // (op 1101) BEGIN: Flatten[1] + // (op 1101) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v14:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v16 +v_sub_u32 v16, v1, v14 // (op 1101) + // (op 1101) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1101): v14 + + // (op 1101) BEGIN: TileTile + // (op 1101) {TileTile: ShiftL({Flatten[1]: v16:U32}, 1:U32)U32} + // (op 1101) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1101) value (Flatten[1]: VGPR Value: UInt32 x 1: v16) + // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 +v_lshlrev_b32 v14, 1, v16 // (op 1101) + // (op 1101) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1101): v16 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 +v_mov_b32 v17, 0 // (op 1101) convert +v_mov_b32 v16, v14 // (op 1101) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1101): v14 + + // (op 1101) BEGIN: Split + // (op 1101) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1101) lhs (Tile: VGPR Value: UInt32 x 1: v15) + // (op 1101) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1101): v18, v19 +v_mul_lo_u32 v19, v15, s19 // (op 1101) most significant: low of low * high + // (op 1101) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1101): v14 +v_mul_hi_u32 v14, v15, s18 // (op 1101) most significant: high of low * low +v_mul_lo_u32 v18, v15, s18 // (op 1101) least significant: low of low * low +v_add_u32 v19, v19, v14 // (op 1101) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1101): v14 + + // (op 1101) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1101) lhs (VGPR Value: UInt64 x 1: v[18:19]) + // (op 1101) rhs (TileTile: VGPR Value: UInt64 x 1: v[16:17]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 +v_add_co_u32 v18, s[0:1], v18, v16 // (op 1101) least significant half +v_addc_co_u32 v19, s[0:1], v19, v17, s[0:1] // (op 1101) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 + + // (op 1101) END: Split + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1101): v15 + + // (op 1101) ShiftL({Split: v[18:19]:U64}, 1:U32)U64 + // (op 1101) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1101) value (Split: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v14, v15 +v_lshlrev_b64 v[14:15], 1, v[18:19] // (op 1101) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1101): v18, v19 + + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) END + // (op 1074) Assign VGPR 128:U64(1102) BEGIN + // (op 1102) Assign dim(488) = 128:U64 + // (op 1102) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1102) END + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) BEGIN + // (op 1103) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1103) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // (op 1103) Get arg Tensor_0_pointer + // (op 1103) Get arg Tensor_0_extent_0 + // (op 1103) reg expression + // (op 1103) reg expression + // (op 1103) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1103) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1103) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1103) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1103): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1103) + // (op 1103) reg expression +s_mov_b32 s32, s6 // (op 1103) reg expression +s_mov_b32 s33, s7 // (op 1103) reg expression +s_mov_b32 s34, s0 // (op 1103) reg expression +s_mov_b32 s35, 131072 // (op 1103) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1103): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) END + // (op 1074) NOP(1094) BEGIN + // (op 1094) generate({}) + // (op 1094) end: generate({}) + // (op 1074) NOP(1094) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) BEGIN + // (op 1108) Assign dim(490) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1108) Assign stride expression + // (op 1074) Tag 1108non referenced extraArgs = {Tensor_0_stride_0_9} + + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) END + // (op 1074) NOP(1095) BEGIN + // (op 1095) generate({}) + // (op 1095) end: generate({}) + // (op 1074) NOP(1095) END + // (op 1074) Assign VGPR 2:U64(1111) BEGIN + // (op 1111) Assign dim(492) = 2:U64 + // (op 1111) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1111) END + // (op 1074) NOP(1136) BEGIN + // (op 1136) generate({}) + // (op 1136) end: generate({}) + // (op 1074) NOP(1136) END + // (op 1074) Assign VGPR 128:U64(1143) BEGIN + // (op 1143) Assign dim(501) = 128:U64 + // (op 1143) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1143) END + // (op 1074) NOP(1137) BEGIN + // (op 1137) generate({}) + // (op 1137) end: generate({}) + // (op 1074) NOP(1137) END + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) BEGIN + // (op 1146) Assign dim(502) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 502: v**UNALLOCATED** + // (op 1146) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag502: VGPR Value: UInt64 x 1: (unallocated) + // (op 1146) Get arg Tensor_2_stride_1_12 + // (op 1146) reg expression + // (op 1146) reg expression + // (op 1146) reg expression + // (op 1146) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 +v_and_b32 v16, -32, v1 // (op 1146) + // (op 1146) BEGIN: Flatten[1] + // (op 1146) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 +v_sub_u32 v17, v1, v16 // (op 1146) + // (op 1146) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1146): v16 + + // (op 1146) BEGIN: TileTile + // (op 1146) {TileTile: ShiftL({Flatten[1]: v17:U32}, 1:U32)U32} + // (op 1146) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1146) value (Flatten[1]: VGPR Value: UInt32 x 1: v17) + // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 +v_lshlrev_b32 v16, 1, v17 // (op 1146) + // (op 1146) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1146): v17 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1146): v18, v19 +v_mov_b32 v19, 0 // (op 1146) convert +v_mov_b32 v18, v16 // (op 1146) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1146): v16 + + // (op 1146) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 +v_lshrrev_b32 v16, 5, v1 // (op 1146) + // (op 1146) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 +v_lshl_add_u32 v17, s3, 6, v16 // (op 1146) + // (op 1146) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1146): v16 + + // (op 1146) Multiply({Tile: v17:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1146) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1146) lhs (Tile: VGPR Value: UInt32 x 1: v17) + // (op 1146) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 2 VGPRs (Value: Int64) (op 1146): v20, v21 +v_mul_lo_u32 v21, v17, s23 // (op 1146) most significant: low of low * high + // (op 1146) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1146): v16 +v_mul_hi_u32 v16, v17, s22 // (op 1146) most significant: high of low * low +v_mul_lo_u32 v20, v17, s22 // (op 1146) least significant: low of low * low +v_add_u32 v21, v21, v16 // (op 1146) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1146): v16 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1146): v17 + + // (op 1146) BEGIN: Split + // (op 1146) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1146) lhs (TileTile: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1146) rhs (VGPR Value: Int64 x 1: v[20:21]) +// Allocated DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 +// Allocated : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 +v_add_co_u32 v16, s[0:1], v18, v20 // (op 1146) least significant half +v_addc_co_u32 v17, s[0:1], v19, v21, s[0:1] // (op 1146) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 + + // (op 1146) ShiftL: dest (VGPR Value: UInt64 x 1: v[16:17]) = + // (op 1146) value (VGPR Value: UInt64 x 1: v[16:17]) + // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[16:17], 1, v[16:17] // (op 1146) + // (op 1146) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1146): v20, v21 + + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1146): v18, v19 + + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) BEGIN + // (op 1147) Assign dim(503) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1147) Assign stride expression + // (op 1074) Tag 1147non referenced extraArgs = {Tensor_2_stride_1_12} + + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) END + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) BEGIN + // (op 1148) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 496: s**UNALLOCATED** + // (op 1148) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: (unallocated) + // (op 1148) Get arg Tensor_2_pointer + // (op 1148) Get arg Tensor_2_extent_2 + // (op 1148) reg expression + // (op 1148) reg expression + // (op 1148) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1148) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1148) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1148) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1148): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1148) + // (op 1148) reg expression +// Allocated DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 +s_mov_b32 s36, s10 // (op 1148) reg expression +s_mov_b32 s37, s11 // (op 1148) reg expression +s_mov_b32 s38, s0 // (op 1148) reg expression +s_mov_b32 s39, 131072 // (op 1148) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1148): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) END + // (op 1074) NOP(1138) BEGIN + // (op 1138) generate({}) + // (op 1138) end: generate({}) + // (op 1074) NOP(1138) END + // (op 1074) Assign VGPR 2:U64(1153) BEGIN + // (op 1153) Assign dim(505) = 2:U64 + // (op 1153) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1153) END + // (op 1074) NOP(1156) BEGIN + // (op 1156) generate({}) + // (op 1156) end: generate({}) + // (op 1074) NOP(1156) END + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) BEGIN + // (op 1165) Assign dim(506) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 506: v**UNALLOCATED** + // (op 1165) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag506: VGPR Value: UInt64 x 1: (unallocated) + // (op 1165) Get arg Tensor_2_stride_1_12 + // (op 1165) reg expression + // (op 1165) reg expression + // (op 1165) reg expression + // (op 1165) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 +v_and_b32 v18, -32, v1 // (op 1165) + // (op 1165) BEGIN: Flatten[1] + // (op 1165) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v18:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 +v_sub_u32 v19, v1, v18 // (op 1165) + // (op 1165) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1165): v18 + + // (op 1165) BEGIN: TileTile + // (op 1165) {TileTile: ShiftL({Flatten[1]: v19:U32}, 1:U32)U32} + // (op 1165) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1165) value (Flatten[1]: VGPR Value: UInt32 x 1: v19) + // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 +v_lshlrev_b32 v18, 1, v19 // (op 1165) + // (op 1165) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1165): v19 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1165): v20, v21 +v_mov_b32 v21, 0 // (op 1165) convert +v_mov_b32 v20, v18 // (op 1165) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1165): v18 + + // (op 1165) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 +v_lshrrev_b32 v18, 5, v1 // (op 1165) + // (op 1165) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 +v_lshl_add_u32 v19, s3, 6, v18 // (op 1165) + // (op 1165) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1165): v18 + + // (op 1165) Multiply({Tile: v19:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1165) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1165) lhs (Tile: VGPR Value: UInt32 x 1: v19) + // (op 1165) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 2 VGPRs (Value: Int64) (op 1165): v22, v23 +v_mul_lo_u32 v23, v19, s23 // (op 1165) most significant: low of low * high + // (op 1165) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1165): v18 +v_mul_hi_u32 v18, v19, s22 // (op 1165) most significant: high of low * low +v_mul_lo_u32 v22, v19, s22 // (op 1165) least significant: low of low * low +v_add_u32 v23, v23, v18 // (op 1165) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1165): v18 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1165): v19 + + // (op 1165) BEGIN: Split + // (op 1165) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1165) lhs (TileTile: VGPR Value: UInt64 x 1: v[20:21]) + // (op 1165) rhs (VGPR Value: Int64 x 1: v[22:23]) +// Allocated DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 +// Allocated : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 +v_add_co_u32 v18, s[0:1], v20, v22 // (op 1165) least significant half +v_addc_co_u32 v19, s[0:1], v21, v23, s[0:1] // (op 1165) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 + + // (op 1165) ShiftL: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1165) value (VGPR Value: UInt64 x 1: v[18:19]) + // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[18:19], 1, v[18:19] // (op 1165) + // (op 1165) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1165): v22, v23 + + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1165): v20, v21 + + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) END + // (op 1074) Assign VGPR 128:U64(1166) BEGIN + // (op 1166) Assign dim(507) = 128:U64 + // (op 1166) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1166) END + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) BEGIN + // (op 1167) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1167) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // (op 1167) Get arg Tensor_2_pointer + // (op 1167) Get arg Tensor_2_extent_2 + // (op 1167) reg expression + // (op 1167) reg expression + // (op 1167) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1167) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1167) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1167) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1167): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1167) + // (op 1167) reg expression +s_mov_b32 s36, s10 // (op 1167) reg expression +s_mov_b32 s37, s11 // (op 1167) reg expression +s_mov_b32 s38, s0 // (op 1167) reg expression +s_mov_b32 s39, 131072 // (op 1167) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1167): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) END + // (op 1074) NOP(1158) BEGIN + // (op 1158) generate({}) + // (op 1158) end: generate({}) + // (op 1074) NOP(1158) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) BEGIN + // (op 1172) Assign dim(509) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1172) Assign stride expression + // (op 1074) Tag 1172non referenced extraArgs = {Tensor_2_stride_1_12} + + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) END + // (op 1074) NOP(1159) BEGIN + // (op 1159) generate({}) + // (op 1159) end: generate({}) + // (op 1074) NOP(1159) END + // (op 1074) Assign VGPR 2:U64(1175) BEGIN + // (op 1175) Assign dim(511) = 2:U64 + // (op 1175) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1175) END + // (op 1074) NOP(690) BEGIN + // (op 690) generate({}) + // (op 690) end: generate({}) + // (op 1074) NOP(690) END + // (op 1074) SetCoordinate(696) BEGIN + // (op 696) generate({}) + // (op 696) end: generate({}) + // (op 696) generate({1279}) + // (op 696) Scope(1279) BEGIN + // (op 1279) Lock Scope 1279 + // Lock Branch + // (op 1279) generate({1276}) + // (op 1279) NOP(1276) BEGIN + // (op 1276) generate({}) + // (op 1276) end: generate({}) + // (op 1279) NOP(1276) END + // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) BEGIN + // (op 1283) Assign dim(542) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 542: s**UNALLOCATED** + // (op 1283) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag542: SGPR Value: UInt32 x 1: (unallocated) + // (op 1283) reg expression + // (op 1283) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 +v_and_b32 v20, -32, v1 // (op 1283) + // (op 1283) BEGIN: Tile[1] + // (op 1283) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 +v_sub_u32 v21, v1, v20 // (op 1283) + // (op 1283) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v20 + + // (op 1283) BEGIN: Flatten + // (op 1283) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1283) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1283) + // (op 1283) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1283): v21 + + // (op 1283) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1283) + // (op 1283) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1283) + // (op 1283) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v21 + + // (op 1283) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1283) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1283) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v22 + +// Allocated DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1283) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v20 + + // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) END + // (op 1279) Assign VGPR 1024:U32(1284) BEGIN + // (op 1284) Assign dim(543) = 1024:U32 + // (op 1284) Assign stride expression + // (op 1279) Assign VGPR 1024:U32(1284) END + // (op 1279) NOP(1277) BEGIN + // (op 1277) generate({}) + // (op 1277) end: generate({}) + // (op 1279) NOP(1277) END + // (op 1279) Assign VGPR 2:U32(1288) BEGIN + // (op 1288) Assign dim(545) = 2:U32 + // (op 1288) Assign stride expression + // (op 1279) Assign VGPR 2:U32(1288) END + // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) BEGIN + // (op 1023) GEN: LoadTileDirect2LDS + // (op 1023) GEN: loadMacroTileDirect2LDS OP 1023 LDS 21 MacroTile 7 + // (op 1023) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1023) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1023) Get arg Tensor_2_stride_1_12 + // (op 1023) reg expression + // (op 1023) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1023) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1023) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1023) + // (op 1023) convert + // (op 1023) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1023) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1023) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1023) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 + + // (op 1023) Generate 2:U64 into nullptr + // (op 1023) Generate 1024:U32 into nullptr + // (op 1023) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1023) + // (op 1023) Generate Add(0:U32, {DataFlowTag542: s0:U32})U32 into nullptr + // (op 1023) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1023) Generate {DataFlowTag542: s0:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1023) reg expression +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 268 (current 193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 272 (current 197) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 276 (current 201) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 280 (current 205) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 344 (current 269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 348 (current 273) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 352 (current 277) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) reg expression + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1023) + // (op 1023) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 356 (current 281) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 + + // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) END + // (op 1279) Deallocate{}(1895) BEGIN + // (op 1895) Deallocate 544 + // Deleting tag 544 + // (op 1895) Deallocate 543 + // Deleting tag 543 + // (op 1895) Deallocate 542 + // Freeing DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s0 + + // Deleting tag 542 + // (op 1895) Deallocate 545 + // Deleting tag 545 + // (op 1279) Deallocate{}(1895) END + // (op 1279) end: generate({1276}) + // (op 1279) Unlock Scope 1279 + // Unlock None + // (op 696) Scope(1279) END + // (op 696) end: generate({1279}) + // (op 1074) SetCoordinate(696) END + // (op 1074) SetCoordinate(699) BEGIN + // (op 699) generate({}) + // (op 699) end: generate({}) + // (op 699) generate({1227}) + // (op 699) Scope(1227) BEGIN + // (op 1227) Lock Scope 1227 + // Lock Branch + // (op 1227) generate({1224}) + // (op 1227) NOP(1224) BEGIN + // (op 1224) generate({}) + // (op 1224) end: generate({}) + // (op 1227) NOP(1224) END + // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) BEGIN + // (op 1231) Assign dim(526) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 526: s**UNALLOCATED** + // (op 1231) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag526: SGPR Value: UInt32 x 1: (unallocated) + // (op 1231) reg expression + // (op 1231) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 +v_and_b32 v20, -32, v1 // (op 1231) + // (op 1231) BEGIN: Tile[1] + // (op 1231) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 +v_sub_u32 v21, v1, v20 // (op 1231) + // (op 1231) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v20 + + // (op 1231) BEGIN: Flatten + // (op 1231) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1231) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1231) + // (op 1231) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1231): v21 + + // (op 1231) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1231) + // (op 1231) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1231) + // (op 1231) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v21 + + // (op 1231) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1231) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1231) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v22 + +// Allocated DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1231) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v20 + + // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) END + // (op 1227) Assign VGPR 1024:U32(1232) BEGIN + // (op 1232) Assign dim(527) = 1024:U32 + // (op 1232) Assign stride expression + // (op 1227) Assign VGPR 1024:U32(1232) END + // (op 1227) NOP(1225) BEGIN + // (op 1225) generate({}) + // (op 1225) end: generate({}) + // (op 1227) NOP(1225) END + // (op 1227) Assign VGPR 2:U32(1236) BEGIN + // (op 1236) Assign dim(529) = 2:U32 + // (op 1236) Assign stride expression + // (op 1227) Assign VGPR 2:U32(1236) END + // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) BEGIN + // (op 1028) GEN: LoadTileDirect2LDS + // (op 1028) GEN: loadMacroTileDirect2LDS OP 1028 LDS 13 MacroTile 6 + // (op 1028) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1028) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1028) Get arg Tensor_0_stride_0_9 + // (op 1028) reg expression + // (op 1028) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1028) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1028) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1028) + // (op 1028) convert + // (op 1028) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1028) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1028) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1028) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 + + // (op 1028) Generate 2:U64 into nullptr + // (op 1028) Generate 1024:U32 into nullptr + // (op 1028) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 +v_mov_b64 v[22:23], v[12:13] // (op 1028) + // (op 1028) Generate Add(8192:U32, {DataFlowTag526: s0:U32})U32 into nullptr + // (op 1028) reg expression + // (op 1028) Add(8192:U32, {DataFlowTag526: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1028): s1 +s_add_u32 s1, 8192, s0 // (op 1028) + // (op 1028) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1028) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1028) reg expression +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected stall of 50. CBNW: 4, Inc: 4 +// VMEM: Expected complete at 420 (current 345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 424 (current 349) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 428 (current 353) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 432 (current 357) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 +// VMEM: Expected complete at 496 (current 421) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 500 (current 425) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 504 (current 429) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) reg expression + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1028) + // (op 1028) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// VMEM: Expected complete at 508 (current 433) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1028): s1 + + // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) END + // (op 1227) Deallocate{}(1897) BEGIN + // (op 1897) Deallocate 529 + // Deleting tag 529 + // (op 1897) Deallocate 526 + // Freeing DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s0 + + // Deleting tag 526 + // (op 1897) Deallocate 528 + // Deleting tag 528 + // (op 1897) Deallocate 527 + // Deleting tag 527 + // (op 1227) Deallocate{}(1897) END + // (op 1227) end: generate({1224}) + // (op 1227) Unlock Scope 1227 + // Unlock None + // (op 699) Scope(1227) END + // (op 699) end: generate({1227}) + // (op 1074) SetCoordinate(699) END + // (op 1074) SetCoordinate(702) BEGIN + // (op 702) generate({}) + // (op 702) end: generate({}) + // (op 702) generate({1391}) + // (op 702) Scope(1391) BEGIN + // (op 1391) Lock Scope 1391 + // Lock Branch + // (op 1391) generate({1388}) + // (op 1391) NOP(1388) BEGIN + // (op 1388) generate({}) + // (op 1388) end: generate({}) + // (op 1391) NOP(1388) END + // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) BEGIN + // (op 1395) Assign dim(576) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 576: s**UNALLOCATED** + // (op 1395) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag576: SGPR Value: UInt32 x 1: (unallocated) + // (op 1395) reg expression + // (op 1395) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 +v_and_b32 v20, -32, v1 // (op 1395) + // (op 1395) BEGIN: Tile[1] + // (op 1395) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 +v_sub_u32 v21, v1, v20 // (op 1395) + // (op 1395) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v20 + + // (op 1395) BEGIN: Flatten + // (op 1395) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1395) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1395) + // (op 1395) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1395): v21 + + // (op 1395) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1395) + // (op 1395) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1395) + // (op 1395) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v21 + + // (op 1395) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1395) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1395) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v22 + +// Allocated DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1395) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v20 + + // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) END + // (op 1391) Assign VGPR 1024:U32(1396) BEGIN + // (op 1396) Assign dim(577) = 1024:U32 + // (op 1396) Assign stride expression + // (op 1391) Assign VGPR 1024:U32(1396) END + // (op 1391) NOP(1389) BEGIN + // (op 1389) generate({}) + // (op 1389) end: generate({}) + // (op 1391) NOP(1389) END + // (op 1391) Assign VGPR 2:U32(1400) BEGIN + // (op 1400) Assign dim(579) = 2:U32 + // (op 1400) Assign stride expression + // (op 1391) Assign VGPR 2:U32(1400) END + // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) BEGIN + // (op 1033) GEN: LoadTileDirect2LDS + // (op 1033) GEN: loadMacroTileDirect2LDS OP 1033 LDS 360 MacroTile 358 + // (op 1033) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1033) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1033) Get arg Tensor_2_stride_1_12 + // (op 1033) reg expression + // (op 1033) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1033) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1033) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1033) + // (op 1033) convert + // (op 1033) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1033) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1033) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1033) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 + + // (op 1033) Generate 2:U64 into nullptr + // (op 1033) Generate 1024:U32 into nullptr + // (op 1033) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 16384 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1033) + // (op 1033) Generate Add(16384:U32, {DataFlowTag576: s0:U32})U32 into nullptr + // (op 1033) reg expression + // (op 1033) Add(16384:U32, {DataFlowTag576: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1033): s1 +s_add_u32 s1, 16384, s0 // (op 1033) + // (op 1033) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1033) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1033) reg expression + // (op 1033) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 128 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s16 +s_mov_b32 s16, 128 // (op 1033) call() +// 128 is not a supported value! +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 12, Inc: 4 +// VMEM: Expected complete at 572 (current 497) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 576 (current 501) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 580 (current 505) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 584 (current 509) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 16, Inc: 4 +// VMEM: Expected complete at 648 (current 573) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 652 (current 577) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 656 (current 581) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) reg expression + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1033) + // (op 1033) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds +// VMEM: Expected complete at 660 (current 585) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s16 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1033): s1 + + // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) END + // (op 1391) Deallocate{}(1899) BEGIN + // (op 1899) Deallocate 578 + // Deleting tag 578 + // (op 1899) Deallocate 579 + // Deleting tag 579 + // (op 1899) Deallocate 576 + // Freeing DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s0 + + // Deleting tag 576 + // (op 1899) Deallocate 577 + // Deleting tag 577 + // (op 1391) Deallocate{}(1899) END + // (op 1391) end: generate({1388}) + // (op 1391) Unlock Scope 1391 + // Unlock None + // (op 702) Scope(1391) END + // (op 702) end: generate({1391}) + // (op 1074) SetCoordinate(702) END + // (op 1074) SetCoordinate(705) BEGIN + // (op 705) generate({}) + // (op 705) end: generate({}) + // (op 705) generate({1352}) + // (op 705) Scope(1352) BEGIN + // (op 1352) Lock Scope 1352 + // Lock Branch + // (op 1352) generate({1349}) + // (op 1352) NOP(1349) BEGIN + // (op 1349) generate({}) + // (op 1349) end: generate({}) + // (op 1352) NOP(1349) END + // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) BEGIN + // (op 1356) Assign dim(564) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 564: s**UNALLOCATED** + // (op 1356) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag564: SGPR Value: UInt32 x 1: (unallocated) + // (op 1356) reg expression + // (op 1356) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 +v_and_b32 v20, -32, v1 // (op 1356) + // (op 1356) BEGIN: Tile[1] + // (op 1356) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 +v_sub_u32 v21, v1, v20 // (op 1356) + // (op 1356) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v20 + + // (op 1356) BEGIN: Flatten + // (op 1356) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1356) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1356) + // (op 1356) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1356): v21 + + // (op 1356) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1356) + // (op 1356) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1356) + // (op 1356) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v21 + + // (op 1356) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1356) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1356) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v22 + +// Allocated DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1356) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v20 + + // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) END + // (op 1352) Assign VGPR 1024:U32(1357) BEGIN + // (op 1357) Assign dim(565) = 1024:U32 + // (op 1357) Assign stride expression + // (op 1352) Assign VGPR 1024:U32(1357) END + // (op 1352) NOP(1350) BEGIN + // (op 1350) generate({}) + // (op 1350) end: generate({}) + // (op 1352) NOP(1350) END + // (op 1352) Assign VGPR 2:U32(1361) BEGIN + // (op 1361) Assign dim(567) = 2:U32 + // (op 1361) Assign stride expression + // (op 1352) Assign VGPR 2:U32(1361) END + // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) BEGIN + // (op 1035) GEN: LoadTileDirect2LDS + // (op 1035) GEN: loadMacroTileDirect2LDS OP 1035 LDS 356 MacroTile 354 + // (op 1035) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1035) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1035) Get arg Tensor_0_stride_0_9 + // (op 1035) reg expression + // (op 1035) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1035) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1035) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1035) + // (op 1035) convert + // (op 1035) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1035) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1035) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1035) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 + + // (op 1035) Generate 2:U64 into nullptr + // (op 1035) Generate 1024:U32 into nullptr + // (op 1035) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 24576 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 +v_mov_b64 v[22:23], v[12:13] // (op 1035) + // (op 1035) Generate Add(24576:U32, {DataFlowTag564: s0:U32})U32 into nullptr + // (op 1035) reg expression + // (op 1035) Add(24576:U32, {DataFlowTag564: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1035): s1 +s_add_u32 s1, 24576, s0 // (op 1035) + // (op 1035) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1035) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1035) reg expression + // (op 1035) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 128 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s16 +s_mov_b32 s16, 128 // (op 1035) call() +// 128 is not a supported value! +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 20, Inc: 4 +// VMEM: Expected complete at 724 (current 649) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 728 (current 653) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 732 (current 657) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 736 (current 661) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 24, Inc: 4 +// VMEM: Expected complete at 800 (current 725) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 804 (current 729) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 808 (current 733) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) reg expression + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1035) + // (op 1035) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds +// VMEM: Expected complete at 812 (current 737) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s16 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1035): s1 + + // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) END + // (op 1352) Deallocate{}(1901) BEGIN + // (op 1901) Deallocate 565 + // Deleting tag 565 + // (op 1901) Deallocate 567 + // Deleting tag 567 + // (op 1901) Deallocate 564 + // Freeing DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s0 + + // Deleting tag 564 + // (op 1901) Deallocate 566 + // Deleting tag 566 + // (op 1352) Deallocate{}(1901) END + // (op 1352) end: generate({1349}) + // (op 1352) Unlock Scope 1352 + // Unlock None + // (op 705) Scope(1352) END + // (op 705) end: generate({1352}) + // (op 1074) SetCoordinate(705) END + // (op 1074) SetCoordinate(708) BEGIN + // (op 708) generate({}) + // (op 708) end: generate({}) + // (op 708) generate({1469}) + // (op 708) Scope(1469) BEGIN + // (op 1469) Lock Scope 1469 + // Lock Branch + // (op 1469) generate({1466}) + // (op 1469) NOP(1466) BEGIN + // (op 1466) generate({}) + // (op 1466) end: generate({}) + // (op 1469) NOP(1466) END + // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) BEGIN + // (op 1473) Assign dim(600) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 600: s**UNALLOCATED** + // (op 1473) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag600: SGPR Value: UInt32 x 1: (unallocated) + // (op 1473) reg expression + // (op 1473) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 +v_and_b32 v20, -32, v1 // (op 1473) + // (op 1473) BEGIN: Tile[1] + // (op 1473) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 +v_sub_u32 v21, v1, v20 // (op 1473) + // (op 1473) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v20 + + // (op 1473) BEGIN: Flatten + // (op 1473) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1473) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1473) + // (op 1473) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1473): v21 + + // (op 1473) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1473) + // (op 1473) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1473) + // (op 1473) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v21 + + // (op 1473) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1473) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1473) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v22 + +// Allocated DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1473) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v20 + + // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) END + // (op 1469) Assign VGPR 1024:U32(1474) BEGIN + // (op 1474) Assign dim(601) = 1024:U32 + // (op 1474) Assign stride expression + // (op 1469) Assign VGPR 1024:U32(1474) END + // (op 1469) NOP(1467) BEGIN + // (op 1467) generate({}) + // (op 1467) end: generate({}) + // (op 1469) NOP(1467) END + // (op 1469) Assign VGPR 2:U32(1478) BEGIN + // (op 1478) Assign dim(603) = 2:U32 + // (op 1478) Assign stride expression + // (op 1469) Assign VGPR 2:U32(1478) END + // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) BEGIN + // (op 1037) GEN: LoadTileDirect2LDS + // (op 1037) GEN: loadMacroTileDirect2LDS OP 1037 LDS 400 MacroTile 398 + // (op 1037) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1037) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1037) Get arg Tensor_2_stride_1_12 + // (op 1037) reg expression + // (op 1037) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1037) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1037) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1037) + // (op 1037) convert + // (op 1037) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1037) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1037) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1037) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 + + // (op 1037) Generate 2:U64 into nullptr + // (op 1037) Generate 1024:U32 into nullptr + // (op 1037) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 32768 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1037) + // (op 1037) Generate Add(32768:U32, {DataFlowTag600: s0:U32})U32 into nullptr + // (op 1037) reg expression + // (op 1037) Add(32768:U32, {DataFlowTag600: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1037): s1 +s_add_u32 s1, 32768, s0 // (op 1037) + // (op 1037) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1037) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1037) reg expression + // (op 1037) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 256 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s16 +s_mov_b32 s16, 256 // (op 1037) call() +// 256 is not a supported value! +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 28, Inc: 4 +// VMEM: Expected complete at 876 (current 801) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 880 (current 805) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 884 (current 809) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 888 (current 813) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 952 (current 877) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 956 (current 881) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 960 (current 885) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) reg expression + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1037) + // (op 1037) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds +// VMEM: Expected complete at 964 (current 889) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s16 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1037): s1 + + // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) END + // (op 1469) Deallocate{}(1903) BEGIN + // (op 1903) Deallocate 600 + // Freeing DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s0 + + // Deleting tag 600 + // (op 1903) Deallocate 603 + // Deleting tag 603 + // (op 1903) Deallocate 601 + // Deleting tag 601 + // (op 1903) Deallocate 602 + // Deleting tag 602 + // (op 1469) Deallocate{}(1903) END + // (op 1469) end: generate({1466}) + // (op 1469) Unlock Scope 1469 + // Unlock None + // (op 708) Scope(1469) END + // (op 708) end: generate({1469}) + // (op 1074) SetCoordinate(708) END + // (op 1074) SetCoordinate(711) BEGIN + // (op 711) generate({}) + // (op 711) end: generate({}) + // (op 711) generate({1430}) + // (op 711) Scope(1430) BEGIN + // (op 1430) Lock Scope 1430 + // Lock Branch + // (op 1430) generate({1427}) + // (op 1430) NOP(1427) BEGIN + // (op 1427) generate({}) + // (op 1427) end: generate({}) + // (op 1430) NOP(1427) END + // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) BEGIN + // (op 1434) Assign dim(588) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 588: s**UNALLOCATED** + // (op 1434) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag588: SGPR Value: UInt32 x 1: (unallocated) + // (op 1434) reg expression + // (op 1434) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 +v_and_b32 v20, -32, v1 // (op 1434) + // (op 1434) BEGIN: Tile[1] + // (op 1434) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 +v_sub_u32 v21, v1, v20 // (op 1434) + // (op 1434) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v20 + + // (op 1434) BEGIN: Flatten + // (op 1434) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1434) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1434) + // (op 1434) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1434): v21 + + // (op 1434) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1434) + // (op 1434) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1434) + // (op 1434) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v21 + + // (op 1434) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1434) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1434) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v22 + +// Allocated DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1434) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v20 + + // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) END + // (op 1430) Assign VGPR 1024:U32(1435) BEGIN + // (op 1435) Assign dim(589) = 1024:U32 + // (op 1435) Assign stride expression + // (op 1430) Assign VGPR 1024:U32(1435) END + // (op 1430) NOP(1428) BEGIN + // (op 1428) generate({}) + // (op 1428) end: generate({}) + // (op 1430) NOP(1428) END + // (op 1430) Assign VGPR 2:U32(1439) BEGIN + // (op 1439) Assign dim(591) = 2:U32 + // (op 1439) Assign stride expression + // (op 1430) Assign VGPR 2:U32(1439) END + // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) BEGIN + // (op 1039) GEN: LoadTileDirect2LDS + // (op 1039) GEN: loadMacroTileDirect2LDS OP 1039 LDS 396 MacroTile 394 + // (op 1039) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1039) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1039) Get arg Tensor_0_stride_0_9 + // (op 1039) reg expression + // (op 1039) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1039) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1039) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1039) + // (op 1039) convert + // (op 1039) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1039) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1039) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1039) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 + + // (op 1039) Generate 2:U64 into nullptr + // (op 1039) Generate 1024:U32 into nullptr + // (op 1039) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 40960 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 +v_mov_b64 v[22:23], v[12:13] // (op 1039) + // (op 1039) Generate Add(40960:U32, {DataFlowTag588: s0:U32})U32 into nullptr + // (op 1039) reg expression + // (op 1039) Add(40960:U32, {DataFlowTag588: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1039): s1 +s_add_u32 s1, 40960, s0 // (op 1039) + // (op 1039) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1039) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1039) reg expression + // (op 1039) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 256 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s16 +s_mov_b32 s16, 256 // (op 1039) call() +// 256 is not a supported value! +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 1028 (current 953) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1032 (current 957) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1036 (current 961) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1040 (current 965) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 1104 (current 1029) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1108 (current 1033) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1112 (current 1037) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) reg expression + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1039) + // (op 1039) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds +// VMEM: Expected complete at 1116 (current 1041) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s16 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1039): s1 + + // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) END + // (op 1430) Deallocate{}(1905) BEGIN + // (op 1905) Deallocate 588 + // Freeing DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s0 + + // Deleting tag 588 + // (op 1905) Deallocate 591 + // Deleting tag 591 + // (op 1905) Deallocate 589 + // Deleting tag 589 + // (op 1905) Deallocate 590 + // Deleting tag 590 + // (op 1430) Deallocate{}(1905) END + // (op 1430) end: generate({1427}) + // (op 1430) Unlock Scope 1430 + // Unlock None + // (op 711) Scope(1430) END + // (op 711) end: generate({1430}) + // (op 1074) SetCoordinate(711) END + // (op 1074) SetCoordinate(714) BEGIN + // (op 714) generate({}) + // (op 714) end: generate({}) + // (op 714) generate({1547}) + // (op 714) Scope(1547) BEGIN + // (op 1547) Lock Scope 1547 + // Lock Branch + // (op 1547) generate({1544}) + // (op 1547) NOP(1544) BEGIN + // (op 1544) generate({}) + // (op 1544) end: generate({}) + // (op 1547) NOP(1544) END + // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) BEGIN + // (op 1551) Assign dim(624) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 624: s**UNALLOCATED** + // (op 1551) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag624: SGPR Value: UInt32 x 1: (unallocated) + // (op 1551) reg expression + // (op 1551) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 +v_and_b32 v20, -32, v1 // (op 1551) + // (op 1551) BEGIN: Tile[1] + // (op 1551) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 +v_sub_u32 v21, v1, v20 // (op 1551) + // (op 1551) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v20 + + // (op 1551) BEGIN: Flatten + // (op 1551) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} + // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1551) value (Tile[1]: VGPR Value: UInt32 x 1: v21) + // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 +v_lshlrev_b32 v20, 1, v21 // (op 1551) + // (op 1551) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1551): v21 + + // (op 1551) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1551) + // (op 1551) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1551) + // (op 1551) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v21 + + // (op 1551) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1551) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1551) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v22 + +// Allocated DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s0 +s_nop 0 +v_readfirstlane_b32 s0, v20 // (op 1551) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v20 + + // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) END + // (op 1547) Assign VGPR 1024:U32(1552) BEGIN + // (op 1552) Assign dim(625) = 1024:U32 + // (op 1552) Assign stride expression + // (op 1547) Assign VGPR 1024:U32(1552) END + // (op 1547) NOP(1545) BEGIN + // (op 1545) generate({}) + // (op 1545) end: generate({}) + // (op 1547) NOP(1545) END + // (op 1547) Assign VGPR 2:U32(1556) BEGIN + // (op 1556) Assign dim(627) = 2:U32 + // (op 1556) Assign stride expression + // (op 1547) Assign VGPR 2:U32(1556) END + // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) BEGIN + // (op 1041) GEN: LoadTileDirect2LDS + // (op 1041) GEN: loadMacroTileDirect2LDS OP 1041 LDS 440 MacroTile 438 + // (op 1041) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1041) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1041) Get arg Tensor_2_stride_1_12 + // (op 1041) reg expression + // (op 1041) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1041) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1041) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1041) + // (op 1041) convert + // (op 1041) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1041) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1041) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1041) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 + + // (op 1041) Generate 2:U64 into nullptr + // (op 1041) Generate 1024:U32 into nullptr + // (op 1041) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 49152 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1041) + // (op 1041) Generate Add(49152:U32, {DataFlowTag624: s0:U32})U32 into nullptr + // (op 1041) reg expression + // (op 1041) Add(49152:U32, {DataFlowTag624: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1041): s1 +s_add_u32 s1, 49152, s0 // (op 1041) + // (op 1041) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1041) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1041) reg expression + // (op 1041) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 384 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s16 +s_mov_b32 s16, 384 // (op 1041) call() +// 384 is not a supported value! +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 44, Inc: 4 +// VMEM: Expected complete at 1180 (current 1105) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1184 (current 1109) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1188 (current 1113) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1192 (current 1117) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 48, Inc: 4 +// VMEM: Expected complete at 1256 (current 1181) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1260 (current 1185) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1264 (current 1189) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) reg expression + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1041) + // (op 1041) Expression temporary in special register + // Unlock None +buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds +// VMEM: Expected complete at 1268 (current 1193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s16 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1041): s1 + + // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) END + // (op 1547) Deallocate{}(1907) BEGIN + // (op 1907) Deallocate 626 + // Deleting tag 626 + // (op 1907) Deallocate 624 + // Freeing DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s0 + + // Deleting tag 624 + // (op 1907) Deallocate 627 + // Deleting tag 627 + // (op 1907) Deallocate 625 + // Deleting tag 625 + // (op 1547) Deallocate{}(1907) END + // (op 1547) end: generate({1544}) + // (op 1547) Unlock Scope 1547 + // Unlock None + // (op 714) Scope(1547) END + // (op 714) end: generate({1547}) + // (op 1074) SetCoordinate(714) END + // (op 1074) Deallocate{}(1871) BEGIN + // (op 1871) Deallocate 504 + // Deleting tag 504 + // (op 1871) Deallocate 503 + // Deleting tag 503 + // (op 1871) Deallocate 502 + // Freeing DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 + + // Deleting tag 502 + // (op 1871) Deallocate 505 + // Deleting tag 505 + // (op 1871) Deallocate 501 + // Deleting tag 501 + // (op 1074) Deallocate{}(1871) END + // (op 1074) SetCoordinate(717) BEGIN + // (op 717) generate({}) + // (op 717) end: generate({}) + // (op 717) generate({1508}) + // (op 717) Scope(1508) BEGIN + // (op 1508) Lock Scope 1508 + // Lock Branch + // (op 1508) generate({1505}) + // (op 1508) NOP(1505) BEGIN + // (op 1505) generate({}) + // (op 1505) end: generate({}) + // (op 1508) NOP(1505) END + // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) BEGIN + // (op 1512) Assign dim(612) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 612: s**UNALLOCATED** + // (op 1512) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag612: SGPR Value: UInt32 x 1: (unallocated) + // (op 1512) reg expression + // (op 1512) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 +v_and_b32 v16, -32, v1 // (op 1512) + // (op 1512) BEGIN: Tile[1] + // (op 1512) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 +v_sub_u32 v17, v1, v16 // (op 1512) + // (op 1512) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v16 + + // (op 1512) BEGIN: Flatten + // (op 1512) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} + // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1512) value (Tile[1]: VGPR Value: UInt32 x 1: v17) + // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 +v_lshlrev_b32 v16, 1, v17 // (op 1512) + // (op 1512) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1512): v17 + + // (op 1512) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1512) + // (op 1512) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v20 +v_lshl_add_u32 v20, v17, 6, v16 // (op 1512) + // (op 1512) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v16 + + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v17 + + // (op 1512) ShiftL({Flatten: v20:U32}, 1:U32)U32 + // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1512) value (Flatten: VGPR Value: UInt32 x 1: v20) + // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 +v_lshlrev_b32 v16, 1, v20 // (op 1512) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v20 + +// Allocated DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s0 +s_nop 0 +v_readfirstlane_b32 s0, v16 // (op 1512) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v16 + + // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) END + // (op 1508) Assign VGPR 1024:U32(1513) BEGIN + // (op 1513) Assign dim(613) = 1024:U32 + // (op 1513) Assign stride expression + // (op 1508) Assign VGPR 1024:U32(1513) END + // (op 1508) NOP(1506) BEGIN + // (op 1506) generate({}) + // (op 1506) end: generate({}) + // (op 1508) NOP(1506) END + // (op 1508) Assign VGPR 2:U32(1517) BEGIN + // (op 1517) Assign dim(615) = 2:U32 + // (op 1517) Assign stride expression + // (op 1508) Assign VGPR 2:U32(1517) END + // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) BEGIN + // (op 1043) GEN: LoadTileDirect2LDS + // (op 1043) GEN: loadMacroTileDirect2LDS OP 1043 LDS 436 MacroTile 434 + // (op 1043) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1043) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1043) Get arg Tensor_0_stride_0_9 + // (op 1043) reg expression + // (op 1043) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1043) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1043) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1043) + // (op 1043) convert + // (op 1043) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1043) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1043) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 1043) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 + + // (op 1043) Generate 2:U64 into nullptr + // (op 1043) Generate 1024:U32 into nullptr + // (op 1043) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 57344 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 +v_mov_b64 v[20:21], v[12:13] // (op 1043) + // (op 1043) Generate Add(57344:U32, {DataFlowTag612: s0:U32})U32 into nullptr + // (op 1043) reg expression + // (op 1043) Add(57344:U32, {DataFlowTag612: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1043): s1 +s_add_u32 s1, 57344, s0 // (op 1043) + // (op 1043) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1043) Generate s1:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1043) reg expression + // (op 1043) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 384 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s16 +s_mov_b32 s16, 384 // (op 1043) call() +// 384 is not a supported value! +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected stall of 49. CBNW: 52, Inc: 4 +// VMEM: Expected complete at 1332 (current 1257) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1336 (current 1261) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1340 (current 1265) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1344 (current 1269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 56, Inc: 4 +// VMEM: Expected complete at 1408 (current 1333) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1412 (current 1337) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1416 (current 1341) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) reg expression + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1043) + // (op 1043) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds +// VMEM: Expected complete at 1420 (current 1345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s16 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 + + // Freeing : 1 SGPR (Value: UInt32) (op 1043): s1 + + // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) END + // (op 1508) Deallocate{}(1909) BEGIN + // (op 1909) Deallocate 613 + // Deleting tag 613 + // (op 1909) Deallocate 614 + // Deleting tag 614 + // (op 1909) Deallocate 612 + // Freeing DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s0 + + // Deleting tag 612 + // (op 1909) Deallocate 615 + // Deleting tag 615 + // (op 1508) Deallocate{}(1909) END + // (op 1508) end: generate({1505}) + // (op 1508) Unlock Scope 1508 + // Unlock None + // (op 717) Scope(1508) END + // (op 717) end: generate({1508}) + // (op 1074) SetCoordinate(717) END + // (op 1074) Deallocate{}(1873) BEGIN + // (op 1873) Deallocate 484 + // Deleting tag 484 + // (op 1873) Deallocate 483 + // Freeing DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v12, v13 + + // Deleting tag 483 + // (op 1873) Deallocate 482 + // Deleting tag 482 + // (op 1873) Deallocate 486 + // Deleting tag 486 + // (op 1873) Deallocate 485 + // Deleting tag 485 + // (op 1074) Deallocate{}(1873) END + // (op 1074) NOP(1025) BEGIN + // (op 1025) generate({}) + // (op 1025) end: generate({}) + // (op 1074) NOP(1025) END + // (op 1074) NOP(1030) BEGIN + // (op 1030) generate({}) + // (op 1030) end: generate({}) + // (op 1074) NOP(1030) END + // (op 1074) Barrier(693) BEGIN +s_waitcnt vmcnt(48) +s_barrier // (op 693) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1074) Barrier(693) END + // (op 1074) SetCoordinate(757) BEGIN + // (op 757) generate({}) + // (op 757) end: generate({}) + // (op 757) generate({758}) + // (op 757) LoadLDSTile{Value: Halfx2}(758) BEGIN + // (op 758) GEN: loadMacroTileWAVELDS OP 758 LDS 21 WaveTile 145 + // (op 758) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 758) Generate 2:U32 into nullptr + // tag 19: v**UNALLOCATED** + // (op 758) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 758) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 758) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 758): v12, v13 +ds_read_b64 v[12:13], v3 // (op 758) Load local data +// DSMEM: Expected complete at 1368 (current 1348) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 757) LoadLDSTile{Value: Halfx2}(758) END + // (op 757) end: generate({758}) + // (op 1074) SetCoordinate(757) END + // (op 1074) SetCoordinate(760) BEGIN + // (op 760) generate({}) + // (op 760) end: generate({}) + // (op 760) generate({761}) + // (op 760) LoadLDSTile{Value: Halfx2}(761) BEGIN + // (op 761) GEN: loadMacroTileWAVELDS OP 761 LDS 21 WaveTile 145 + // (op 761) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 761) Generate 2:U32 into nullptr + // tag 255: v**UNALLOCATED** + // (op 761) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 761) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 761) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 761): v16, v17 +ds_read_b64 v[16:17], v3 offset:16 // (op 761) Load local data +// DSMEM: Expected complete at 1369 (current 1349) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 760) LoadLDSTile{Value: Halfx2}(761) END + // (op 760) end: generate({761}) + // (op 1074) SetCoordinate(760) END + // (op 1074) SetCoordinate(763) BEGIN + // (op 763) generate({}) + // (op 763) end: generate({}) + // (op 763) generate({764}) + // (op 763) LoadLDSTile{Value: Halfx2}(764) BEGIN + // (op 764) GEN: loadMacroTileWAVELDS OP 764 LDS 21 WaveTile 145 + // (op 764) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 764) Generate 2:U32 into nullptr + // tag 259: v**UNALLOCATED** + // (op 764) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 764) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 764) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 +ds_read_b64 v[20:21], v3 offset:32 // (op 764) Load local data +// DSMEM: Expected complete at 1370 (current 1350) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 763) LoadLDSTile{Value: Halfx2}(764) END + // (op 763) end: generate({764}) + // (op 1074) SetCoordinate(763) END + // (op 1074) SetCoordinate(766) BEGIN + // (op 766) generate({}) + // (op 766) end: generate({}) + // (op 766) generate({767}) + // (op 766) LoadLDSTile{Value: Halfx2}(767) BEGIN + // (op 767) GEN: loadMacroTileWAVELDS OP 767 LDS 21 WaveTile 145 + // (op 767) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 767) Generate 2:U32 into nullptr + // tag 263: v**UNALLOCATED** + // (op 767) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 767) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 767) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 +ds_read_b64 v[22:23], v3 offset:48 // (op 767) Load local data +// DSMEM: Expected complete at 1371 (current 1351) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 766) LoadLDSTile{Value: Halfx2}(767) END + // (op 766) end: generate({767}) + // (op 1074) SetCoordinate(766) END + // (op 1074) SetCoordinate(769) BEGIN + // (op 769) generate({}) + // (op 769) end: generate({}) + // (op 769) generate({770}) + // (op 769) LoadLDSTile{Value: Halfx2}(770) BEGIN + // (op 770) GEN: loadMacroTileWAVELDS OP 770 LDS 21 WaveTile 145 + // (op 770) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 770) Generate 2:U32 into nullptr + // tag 267: v**UNALLOCATED** + // (op 770) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 770) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 770) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 +ds_read_b64 v[24:25], v3 offset:64 // (op 770) Load local data +// DSMEM: Expected stall of 17. CBNW: 0, Inc: 4 +// DSMEM: Expected complete at 1389 (current 1369) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 769) LoadLDSTile{Value: Halfx2}(770) END + // (op 769) end: generate({770}) + // (op 1074) SetCoordinate(769) END + // (op 1074) SetCoordinate(772) BEGIN + // (op 772) generate({}) + // (op 772) end: generate({}) + // (op 772) generate({773}) + // (op 772) LoadLDSTile{Value: Halfx2}(773) BEGIN + // (op 773) GEN: loadMacroTileWAVELDS OP 773 LDS 21 WaveTile 145 + // (op 773) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 773) Generate 2:U32 into nullptr + // tag 271: v**UNALLOCATED** + // (op 773) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 773) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 773) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 +ds_read_b64 v[26:27], v3 offset:80 // (op 773) Load local data +// DSMEM: Expected complete at 1390 (current 1370) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 772) LoadLDSTile{Value: Halfx2}(773) END + // (op 772) end: generate({773}) + // (op 1074) SetCoordinate(772) END + // (op 1074) SetCoordinate(775) BEGIN + // (op 775) generate({}) + // (op 775) end: generate({}) + // (op 775) generate({776}) + // (op 775) LoadLDSTile{Value: Halfx2}(776) BEGIN + // (op 776) GEN: loadMacroTileWAVELDS OP 776 LDS 21 WaveTile 145 + // (op 776) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 776) Generate 2:U32 into nullptr + // tag 275: v**UNALLOCATED** + // (op 776) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 776) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 776) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 +ds_read_b64 v[28:29], v3 offset:96 // (op 776) Load local data +// DSMEM: Expected complete at 1391 (current 1371) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 775) LoadLDSTile{Value: Halfx2}(776) END + // (op 775) end: generate({776}) + // (op 1074) SetCoordinate(775) END + // (op 1074) SetCoordinate(778) BEGIN + // (op 778) generate({}) + // (op 778) end: generate({}) + // (op 778) generate({779}) + // (op 778) LoadLDSTile{Value: Halfx2}(779) BEGIN + // (op 779) GEN: loadMacroTileWAVELDS OP 779 LDS 21 WaveTile 145 + // (op 779) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 779) Generate 2:U32 into nullptr + // tag 279: v**UNALLOCATED** + // (op 779) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 779) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 779) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 +ds_read_b64 v[30:31], v3 offset:112 // (op 779) Load local data +// DSMEM: Expected complete at 1392 (current 1372) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 778) LoadLDSTile{Value: Halfx2}(779) END + // (op 778) end: generate({779}) + // (op 1074) SetCoordinate(778) END + // (op 1074) SetCoordinate(733) BEGIN + // (op 733) generate({}) + // (op 733) end: generate({}) + // (op 733) generate({734}) + // (op 733) LoadLDSTile{Value: Halfx2}(734) BEGIN + // (op 734) GEN: loadMacroTileWAVELDS OP 734 LDS 13 WaveTile 85 + // (op 734) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 734) Generate 2:U32 into nullptr + // tag 11: v**UNALLOCATED** + // (op 734) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 734) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 734) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 +ds_read_b64 v[32:33], v0 offset:8192 // (op 734) Load local data +// DSMEM: Expected stall of 17. CBNW: 4, Inc: 4 +// DSMEM: Expected complete at 1410 (current 1390) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 733) LoadLDSTile{Value: Halfx2}(734) END + // (op 733) end: generate({734}) + // (op 1074) SetCoordinate(733) END + // (op 1074) SetCoordinate(736) BEGIN + // (op 736) generate({}) + // (op 736) end: generate({}) + // (op 736) generate({737}) + // (op 736) LoadLDSTile{Value: Halfx2}(737) BEGIN + // (op 737) GEN: loadMacroTileWAVELDS OP 737 LDS 13 WaveTile 85 + // (op 737) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 737) Generate 2:U32 into nullptr + // tag 253: v**UNALLOCATED** + // (op 737) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 737) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 737) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 +ds_read_b64 v[34:35], v0 offset:8208 // (op 737) Load local data +// DSMEM: Expected complete at 1411 (current 1391) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 736) LoadLDSTile{Value: Halfx2}(737) END + // (op 736) end: generate({737}) + // (op 1074) SetCoordinate(736) END + // (op 1074) SetCoordinate(739) BEGIN + // (op 739) generate({}) + // (op 739) end: generate({}) + // (op 739) generate({740}) + // (op 739) LoadLDSTile{Value: Halfx2}(740) BEGIN + // (op 740) GEN: loadMacroTileWAVELDS OP 740 LDS 13 WaveTile 85 + // (op 740) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 740) Generate 2:U32 into nullptr + // tag 257: v**UNALLOCATED** + // (op 740) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 740) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 740) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 +ds_read_b64 v[36:37], v0 offset:8224 // (op 740) Load local data +// DSMEM: Expected complete at 1412 (current 1392) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 739) LoadLDSTile{Value: Halfx2}(740) END + // (op 739) end: generate({740}) + // (op 1074) SetCoordinate(739) END + // (op 1074) SetCoordinate(742) BEGIN + // (op 742) generate({}) + // (op 742) end: generate({}) + // (op 742) generate({743}) + // (op 742) LoadLDSTile{Value: Halfx2}(743) BEGIN + // (op 743) GEN: loadMacroTileWAVELDS OP 743 LDS 13 WaveTile 85 + // (op 743) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 743) Generate 2:U32 into nullptr + // tag 261: v**UNALLOCATED** + // (op 743) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 743) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 743) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 +ds_read_b64 v[38:39], v0 offset:8240 // (op 743) Load local data +// DSMEM: Expected complete at 1413 (current 1393) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 742) LoadLDSTile{Value: Halfx2}(743) END + // (op 742) end: generate({743}) + // (op 1074) SetCoordinate(742) END + // (op 1074) SetCoordinate(745) BEGIN + // (op 745) generate({}) + // (op 745) end: generate({}) + // (op 745) generate({746}) + // (op 745) LoadLDSTile{Value: Halfx2}(746) BEGIN + // (op 746) GEN: loadMacroTileWAVELDS OP 746 LDS 13 WaveTile 85 + // (op 746) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 746) Generate 2:U32 into nullptr + // tag 265: v**UNALLOCATED** + // (op 746) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 746) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 746) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 +ds_read_b64 v[40:41], v0 offset:8256 // (op 746) Load local data +// DSMEM: Expected stall of 17. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 1431 (current 1411) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 745) LoadLDSTile{Value: Halfx2}(746) END + // (op 745) end: generate({746}) + // (op 1074) SetCoordinate(745) END + // (op 1074) SetCoordinate(748) BEGIN + // (op 748) generate({}) + // (op 748) end: generate({}) + // (op 748) generate({749}) + // (op 748) LoadLDSTile{Value: Halfx2}(749) BEGIN + // (op 749) GEN: loadMacroTileWAVELDS OP 749 LDS 13 WaveTile 85 + // (op 749) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 749) Generate 2:U32 into nullptr + // tag 269: v**UNALLOCATED** + // (op 749) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 749) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 749) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 +ds_read_b64 v[42:43], v0 offset:8272 // (op 749) Load local data +// DSMEM: Expected complete at 1432 (current 1412) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 748) LoadLDSTile{Value: Halfx2}(749) END + // (op 748) end: generate({749}) + // (op 1074) SetCoordinate(748) END + // (op 1074) SetCoordinate(751) BEGIN + // (op 751) generate({}) + // (op 751) end: generate({}) + // (op 751) generate({752}) + // (op 751) LoadLDSTile{Value: Halfx2}(752) BEGIN + // (op 752) GEN: loadMacroTileWAVELDS OP 752 LDS 13 WaveTile 85 + // (op 752) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 752) Generate 2:U32 into nullptr + // tag 273: v**UNALLOCATED** + // (op 752) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 752) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 752) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 +ds_read_b64 v[44:45], v0 offset:8288 // (op 752) Load local data +// DSMEM: Expected complete at 1433 (current 1413) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 751) LoadLDSTile{Value: Halfx2}(752) END + // (op 751) end: generate({752}) + // (op 1074) SetCoordinate(751) END + // (op 1074) SetCoordinate(754) BEGIN + // (op 754) generate({}) + // (op 754) end: generate({}) + // (op 754) generate({755}) + // (op 754) LoadLDSTile{Value: Halfx2}(755) BEGIN + // (op 755) GEN: loadMacroTileWAVELDS OP 755 LDS 13 WaveTile 85 + // (op 755) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 755) Generate 2:U32 into nullptr + // tag 277: v**UNALLOCATED** + // (op 755) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 755) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 755) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 +ds_read_b64 v[46:47], v0 offset:8304 // (op 755) Load local data +// DSMEM: Expected complete at 1434 (current 1414) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 754) LoadLDSTile{Value: Halfx2}(755) END + // (op 754) end: generate({755}) + // (op 1074) SetCoordinate(754) END + // (op 1074) NOP(694) BEGIN + // (op 694) generate({}) + // (op 694) end: generate({}) + // (op 1074) NOP(694) END + // (op 1074) NOP(1199) BEGIN + // (op 1199) generate({}) + // (op 1199) end: generate({}) + // (op 1074) NOP(1199) END + // (op 1074) NOP(1196) BEGIN + // (op 1196) generate({}) + // (op 1196) end: generate({}) + // (op 1074) NOP(1196) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) BEGIN + // (op 1203) Assign dim(518) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 518: s**UNALLOCATED** + // (op 1203) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag518: SGPR Value: UInt32 x 1: (unallocated) + // (op 1203) reg expression + // (op 1203) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 +v_and_b32 v48, -32, v1 // (op 1203) + // (op 1203) BEGIN: Tile[1] + // (op 1203) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 +v_sub_u32 v49, v1, v48 // (op 1203) + // (op 1203) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v48 + + // (op 1203) BEGIN: Flatten + // (op 1203) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1203) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1203) + // (op 1203) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1203): v49 + + // (op 1203) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1203) + // (op 1203) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1203) + // (op 1203) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v49 + + // (op 1203) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1203) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1203) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v50 + +// Allocated DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s0 +s_nop 0 +v_readfirstlane_b32 s0, v48 // (op 1203) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) END + // (op 1074) Assign VGPR 1024:U32(1204) BEGIN + // (op 1204) Assign dim(519) = 1024:U32 + // (op 1204) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1204) END + // (op 1074) NOP(1197) BEGIN + // (op 1197) generate({}) + // (op 1197) end: generate({}) + // (op 1074) NOP(1197) END + // (op 1074) Assign VGPR 2:U32(1208) BEGIN + // (op 1208) Assign dim(521) = 2:U32 + // (op 1208) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1208) END + // (op 1074) NOP(1250) BEGIN + // (op 1250) generate({}) + // (op 1250) end: generate({}) + // (op 1074) NOP(1250) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) BEGIN + // (op 1255) Assign dim(534) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 534: s**UNALLOCATED** + // (op 1255) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag534: SGPR Value: UInt32 x 1: (unallocated) + // (op 1255) reg expression + // (op 1255) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 +v_and_b32 v48, -32, v1 // (op 1255) + // (op 1255) BEGIN: Tile[1] + // (op 1255) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 +v_sub_u32 v49, v1, v48 // (op 1255) + // (op 1255) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v48 + + // (op 1255) BEGIN: Flatten + // (op 1255) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1255) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1255) + // (op 1255) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1255): v49 + + // (op 1255) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1255) + // (op 1255) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1255) + // (op 1255) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v49 + + // (op 1255) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1255) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1255) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v50 + +// Allocated DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s1 +s_nop 0 +v_readfirstlane_b32 s1, v48 // (op 1255) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) END + // (op 1074) Assign VGPR 1024:U32(1256) BEGIN + // (op 1256) Assign dim(535) = 1024:U32 + // (op 1256) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1256) END + // (op 1074) NOP(1251) BEGIN + // (op 1251) generate({}) + // (op 1251) end: generate({}) + // (op 1074) NOP(1251) END + // (op 1074) Assign VGPR 2:U32(1260) BEGIN + // (op 1260) Assign dim(537) = 2:U32 + // (op 1260) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1260) END + // (op 1074) NOP(1336) BEGIN + // (op 1336) generate({}) + // (op 1336) end: generate({}) + // (op 1074) NOP(1336) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) BEGIN + // (op 1341) Assign dim(560) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 560: s**UNALLOCATED** + // (op 1341) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag560: SGPR Value: UInt32 x 1: (unallocated) + // (op 1341) reg expression + // (op 1341) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 +v_and_b32 v48, -32, v1 // (op 1341) + // (op 1341) BEGIN: Tile[1] + // (op 1341) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 +v_sub_u32 v49, v1, v48 // (op 1341) + // (op 1341) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v48 + + // (op 1341) BEGIN: Flatten + // (op 1341) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1341) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1341) + // (op 1341) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1341): v49 + + // (op 1341) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1341) + // (op 1341) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1341) + // (op 1341) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v49 + + // (op 1341) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1341) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1341) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v50 + +// Allocated DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s16 +s_nop 0 +v_readfirstlane_b32 s16, v48 // (op 1341) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) END + // (op 1074) Assign VGPR 1024:U32(1342) BEGIN + // (op 1342) Assign dim(561) = 1024:U32 + // (op 1342) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1342) END + // (op 1074) NOP(1337) BEGIN + // (op 1337) generate({}) + // (op 1337) end: generate({}) + // (op 1074) NOP(1337) END + // (op 1074) Assign VGPR 2:U32(1346) BEGIN + // (op 1346) Assign dim(563) = 2:U32 + // (op 1346) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1346) END + // (op 1074) NOP(1375) BEGIN + // (op 1375) generate({}) + // (op 1375) end: generate({}) + // (op 1074) NOP(1375) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) BEGIN + // (op 1380) Assign dim(572) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 572: s**UNALLOCATED** + // (op 1380) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag572: SGPR Value: UInt32 x 1: (unallocated) + // (op 1380) reg expression + // (op 1380) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 +v_and_b32 v48, -32, v1 // (op 1380) + // (op 1380) BEGIN: Tile[1] + // (op 1380) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 +v_sub_u32 v49, v1, v48 // (op 1380) + // (op 1380) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v48 + + // (op 1380) BEGIN: Flatten + // (op 1380) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1380) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1380) + // (op 1380) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1380): v49 + + // (op 1380) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1380) + // (op 1380) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1380) + // (op 1380) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v49 + + // (op 1380) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1380) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1380) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v50 + +// Allocated DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s17 +s_nop 0 +v_readfirstlane_b32 s17, v48 // (op 1380) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) END + // (op 1074) Assign VGPR 1024:U32(1381) BEGIN + // (op 1381) Assign dim(573) = 1024:U32 + // (op 1381) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1381) END + // (op 1074) NOP(1376) BEGIN + // (op 1376) generate({}) + // (op 1376) end: generate({}) + // (op 1074) NOP(1376) END + // (op 1074) Assign VGPR 2:U32(1385) BEGIN + // (op 1385) Assign dim(575) = 2:U32 + // (op 1385) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1385) END + // (op 1074) NOP(1414) BEGIN + // (op 1414) generate({}) + // (op 1414) end: generate({}) + // (op 1074) NOP(1414) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) BEGIN + // (op 1419) Assign dim(584) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 584: s**UNALLOCATED** + // (op 1419) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag584: SGPR Value: UInt32 x 1: (unallocated) + // (op 1419) reg expression + // (op 1419) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 +v_and_b32 v48, -32, v1 // (op 1419) + // (op 1419) BEGIN: Tile[1] + // (op 1419) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 +v_sub_u32 v49, v1, v48 // (op 1419) + // (op 1419) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v48 + + // (op 1419) BEGIN: Flatten + // (op 1419) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1419) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1419) + // (op 1419) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1419): v49 + + // (op 1419) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1419) + // (op 1419) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1419) + // (op 1419) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v49 + + // (op 1419) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1419) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1419) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v50 + +// Allocated DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 +s_nop 0 +v_readfirstlane_b32 s40, v48 // (op 1419) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) END + // (op 1074) Assign VGPR 1024:U32(1420) BEGIN + // (op 1420) Assign dim(585) = 1024:U32 + // (op 1420) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1420) END + // (op 1074) NOP(1415) BEGIN + // (op 1415) generate({}) + // (op 1415) end: generate({}) + // (op 1074) NOP(1415) END + // (op 1074) Assign VGPR 2:U32(1424) BEGIN + // (op 1424) Assign dim(587) = 2:U32 + // (op 1424) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1424) END + // (op 1074) NOP(1453) BEGIN + // (op 1453) generate({}) + // (op 1453) end: generate({}) + // (op 1074) NOP(1453) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) BEGIN + // (op 1458) Assign dim(596) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 596: s**UNALLOCATED** + // (op 1458) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag596: SGPR Value: UInt32 x 1: (unallocated) + // (op 1458) reg expression + // (op 1458) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 +v_and_b32 v48, -32, v1 // (op 1458) + // (op 1458) BEGIN: Tile[1] + // (op 1458) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 +v_sub_u32 v49, v1, v48 // (op 1458) + // (op 1458) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v48 + + // (op 1458) BEGIN: Flatten + // (op 1458) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1458) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1458) + // (op 1458) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1458): v49 + + // (op 1458) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1458) + // (op 1458) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1458) + // (op 1458) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v49 + + // (op 1458) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1458) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1458) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v50 + +// Allocated DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 +s_nop 0 +v_readfirstlane_b32 s41, v48 // (op 1458) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) END + // (op 1074) Assign VGPR 1024:U32(1459) BEGIN + // (op 1459) Assign dim(597) = 1024:U32 + // (op 1459) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1459) END + // (op 1074) NOP(1454) BEGIN + // (op 1454) generate({}) + // (op 1454) end: generate({}) + // (op 1074) NOP(1454) END + // (op 1074) Assign VGPR 2:U32(1463) BEGIN + // (op 1463) Assign dim(599) = 2:U32 + // (op 1463) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1463) END + // (op 1074) NOP(1492) BEGIN + // (op 1492) generate({}) + // (op 1492) end: generate({}) + // (op 1074) NOP(1492) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) BEGIN + // (op 1497) Assign dim(608) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 608: s**UNALLOCATED** + // (op 1497) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag608: SGPR Value: UInt32 x 1: (unallocated) + // (op 1497) reg expression + // (op 1497) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 +v_and_b32 v48, -32, v1 // (op 1497) + // (op 1497) BEGIN: Tile[1] + // (op 1497) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 +v_sub_u32 v49, v1, v48 // (op 1497) + // (op 1497) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v48 + + // (op 1497) BEGIN: Flatten + // (op 1497) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1497) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1497) + // (op 1497) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1497): v49 + + // (op 1497) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1497) + // (op 1497) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1497) + // (op 1497) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v49 + + // (op 1497) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1497) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1497) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v50 + +// Allocated DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 +s_nop 0 +v_readfirstlane_b32 s42, v48 // (op 1497) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) END + // (op 1074) Assign VGPR 1024:U32(1498) BEGIN + // (op 1498) Assign dim(609) = 1024:U32 + // (op 1498) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1498) END + // (op 1074) NOP(1493) BEGIN + // (op 1493) generate({}) + // (op 1493) end: generate({}) + // (op 1074) NOP(1493) END + // (op 1074) Assign VGPR 2:U32(1502) BEGIN + // (op 1502) Assign dim(611) = 2:U32 + // (op 1502) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1502) END + // (op 1074) NOP(1531) BEGIN + // (op 1531) generate({}) + // (op 1531) end: generate({}) + // (op 1074) NOP(1531) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) BEGIN + // (op 1536) Assign dim(620) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 620: s**UNALLOCATED** + // (op 1536) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag620: SGPR Value: UInt32 x 1: (unallocated) + // (op 1536) reg expression + // (op 1536) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 +v_and_b32 v48, -32, v1 // (op 1536) + // (op 1536) BEGIN: Tile[1] + // (op 1536) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 +v_sub_u32 v49, v1, v48 // (op 1536) + // (op 1536) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v48 + + // (op 1536) BEGIN: Flatten + // (op 1536) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} + // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1536) value (Tile[1]: VGPR Value: UInt32 x 1: v49) + // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 +v_lshlrev_b32 v48, 1, v49 // (op 1536) + // (op 1536) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1536): v49 + + // (op 1536) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1536) + // (op 1536) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1536) + // (op 1536) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v49 + + // (op 1536) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1536) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1536) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v50 + +// Allocated DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 +s_nop 0 +v_readfirstlane_b32 s43, v48 // (op 1536) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v48 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) END + // (op 1074) Assign VGPR 1024:U32(1537) BEGIN + // (op 1537) Assign dim(621) = 1024:U32 + // (op 1537) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1537) END + // (op 1074) NOP(1532) BEGIN + // (op 1532) generate({}) + // (op 1532) end: generate({}) + // (op 1074) NOP(1532) END + // (op 1074) Assign VGPR 2:U32(1541) BEGIN + // (op 1541) Assign dim(623) = 2:U32 + // (op 1541) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1541) END + // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) BEGIN + // (op 39) Initialize For Loop + // (op 39) generate({40}) + // (op 39) Assign SGPR 0:U32(40) BEGIN + // (op 40) Assign dim(245) = 0:U32 + // tag 245: s**UNALLOCATED** + // (op 40) Generate 0:U32 into DataFlowTag245: SGPR Value: UInt32 x 1: (unallocated) +// Allocated DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 +s_mov_b32 s44, 0 // (op 40) call() + // (op 39) Tag 40non referenced extraArgs = {Tensor_0_size_1_10} + + // (op 39) Assign SGPR 0:U32(40) END + // (op 39) end: generate({40}) + // (op 39) Lock For Loop + // Lock Branch + // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc + // (op 39) Get arg Tensor_0_size_1_10 + // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL + // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 + // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 +s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) +// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 +s_mov_b32 s45, s46 // (op 39) convert + // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 + +// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 +s_and_b32 s46, s45, 4294967292 // (op 39) + // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 + +s_cmp_lt_u32 s44, s46 // (op 39) + // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 39) +s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39 // (op 39) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39 if false) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39: + // (op 39) + // (op 39) generate({41, 57, 811, 1733}) + // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) BEGIN + // (op 41) Assign dim(245) = Add(DataFlowTag(245)U32, 4:U32)U32 + // (op 41) Generate Add(DataFlowTag(245)U32, 4:U32)U32 into DataFlowTag245: SGPR Value: UInt32 x 1: s44 + // (op 41) reg expression + // (op 41) Add({DataFlowTag245: s44:U32}, 4:U32)U32 + // (op 39) Multiply(57) BEGIN + // (op 57) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(811) BEGIN + // (op 39) Barrier(1733) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 811) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 39) Barrier(811) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 57) + // (op 39) Multiply(57) END +s_barrier // (op 1733) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 39) Barrier(1733) END + // (op 39) Multiply(66) BEGIN + // (op 66) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(332) BEGIN + // (op 332) generate({}) + // (op 332) end: generate({}) + // (op 332) generate({333}) + // (op 332) LoadLDSTile{Value: Halfx2}(333) BEGIN + // (op 333) GEN: loadMacroTileWAVELDS OP 333 LDS 360 WaveTile 145 + // (op 333) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 333) Generate 2:U32 into nullptr + // tag 364: v[12:13] alias 364 -> 19 + // (op 333) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 333) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 333) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) SetCoordinate(604) BEGIN + // (op 604) generate({}) + // (op 604) end: generate({}) + // (op 604) generate({976}) + // (op 604) LoadTileDirect2LDS Value: Halfx2(976) BEGIN + // (op 976) GEN: LoadTileDirect2LDS + // (op 976) GEN: loadMacroTileDirect2LDS OP 976 LDS 21 MacroTile 7 + // (op 976) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 976) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 976) Get arg Tensor_2_stride_1_12 + // (op 976) reg expression + // (op 976) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 976) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 976) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 976) shiftAmount (Literal Value: UInt32 x 0: 3) +ds_read_b64 v[12:13], v5 offset:16384 // (op 333) Load local data +// DSMEM: Expected complete at 1511 (current 1491) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 332) LoadLDSTile{Value: Halfx2}(333) END + // (op 332) end: generate({333}) + // (op 39) SetCoordinate(332) END +s_add_u32 s44, s44, 4 // (op 41) + // (op 39) Tag 41non referenced extraArgs = {Tensor_0_size_1_10} + + // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) END + // (op 39) SetCoordinate(337) BEGIN + // (op 337) generate({}) + // (op 337) end: generate({}) + // (op 337) generate({338}) + // (op 337) LoadLDSTile{Value: Halfx2}(338) BEGIN + // (op 338) GEN: loadMacroTileWAVELDS OP 338 LDS 360 WaveTile 145 + // (op 338) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 338) Generate 2:U32 into nullptr + // tag 368: v**UNALLOCATED** + // (op 338) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 338) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16400 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 338) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 +ds_read_b64 v[48:49], v5 offset:16400 // (op 338) Load local data +// DSMEM: Expected complete at 1513 (current 1493) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 337) LoadLDSTile{Value: Halfx2}(338) END + // (op 337) end: generate({338}) + // (op 39) SetCoordinate(337) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 976) + // (op 976) convert + // (op 976) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 976) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 976) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 976) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(342) BEGIN + // (op 342) generate({}) + // (op 342) end: generate({}) + // (op 342) generate({343}) + // (op 342) LoadLDSTile{Value: Halfx2}(343) BEGIN + // (op 343) GEN: loadMacroTileWAVELDS OP 343 LDS 360 WaveTile 145 + // (op 343) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 343) Generate 2:U32 into nullptr + // tag 372: v**UNALLOCATED** + // (op 343) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 343) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16416 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 343) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 976) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 + + // (op 976) Generate 2:U64 into nullptr + // (op 976) Generate 1024:U32 into nullptr + // (op 976) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 508: v**UNALLOCATED** +// Allocated Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 +v_mov_b64 v[52:53], v[18:19] // (op 976) +// Allocated : 2 VGPRs (Value: UInt64) (op 976): v54, v55 +v_mov_b64 v[54:55], v[52:53] // (op 976) + // (op 976) Generate Add(0:U32, {DataFlowTag534: s1:U32})U32 into nullptr + // (op 976) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 976) Generate {DataFlowTag534: s1:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 976) reg expression + // (op 976) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 512 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 +s_mov_b32 s45, 512 // (op 976) call() +// 512 is not a supported value! +s_waitcnt lgkmcnt(8) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[16:17], a[0:15] // (op 66) + // (op 39) Multiply(66) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1577 (current 1502) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Multiply(75) BEGIN + // (op 75) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1581 (current 1506) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1585 (current 1510) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 75) + // (op 39) Multiply(75) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half + // (op 39) Multiply(84) BEGIN + // (op 84) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1591 (current 1516) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 +ds_read_b64 v[56:57], v5 offset:16416 // (op 343) Load local data +// DSMEM: Expected complete at 1540 (current 1520) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 342) LoadLDSTile{Value: Halfx2}(343) END + // (op 342) end: generate({343}) + // (op 39) SetCoordinate(342) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[22:23], a[0:15] // (op 84) + // (op 39) Multiply(84) END + // (op 39) SetCoordinate(347) BEGIN + // (op 347) generate({}) + // (op 347) end: generate({}) + // (op 347) generate({348}) + // (op 347) LoadLDSTile{Value: Halfx2}(348) BEGIN + // (op 348) GEN: loadMacroTileWAVELDS OP 348 LDS 360 WaveTile 145 + // (op 348) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 348) Generate 2:U32 into nullptr + // tag 376: v**UNALLOCATED** + // (op 348) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 348) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16432 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 348) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(93) BEGIN + // (op 93) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 +ds_read_b64 v[58:59], v5 offset:16432 // (op 348) Load local data +// DSMEM: Expected complete at 1543 (current 1523) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 347) LoadLDSTile{Value: Halfx2}(348) END + // (op 347) end: generate({348}) + // (op 39) SetCoordinate(347) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[24:25], a[0:15] // (op 93) + // (op 39) Multiply(93) END + // (op 39) SetCoordinate(352) BEGIN + // (op 352) generate({}) + // (op 352) end: generate({}) + // (op 352) generate({353}) + // (op 352) LoadLDSTile{Value: Halfx2}(353) BEGIN + // (op 353) GEN: loadMacroTileWAVELDS OP 353 LDS 360 WaveTile 145 + // (op 353) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 353) Generate 2:U32 into nullptr + // tag 380: v**UNALLOCATED** + // (op 353) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 353) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16448 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 353) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(102) BEGIN + // (op 102) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 +ds_read_b64 v[60:61], v5 offset:16448 // (op 353) Load local data +// DSMEM: Expected complete at 1553 (current 1533) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 352) LoadLDSTile{Value: Halfx2}(353) END + // (op 352) end: generate({353}) + // (op 39) SetCoordinate(352) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[26:27], a[0:15] // (op 102) + // (op 39) Multiply(102) END + // (op 39) SetCoordinate(357) BEGIN + // (op 357) generate({}) + // (op 357) end: generate({}) + // (op 357) generate({358}) + // (op 357) LoadLDSTile{Value: Halfx2}(358) BEGIN + // (op 358) GEN: loadMacroTileWAVELDS OP 358 LDS 360 WaveTile 145 + // (op 358) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 358) Generate 2:U32 into nullptr + // tag 384: v**UNALLOCATED** + // (op 358) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 358) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16464 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 358) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(111) BEGIN + // (op 111) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 +ds_read_b64 v[62:63], v5 offset:16464 // (op 358) Load local data +// DSMEM: Expected complete at 1563 (current 1543) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 357) LoadLDSTile{Value: Halfx2}(358) END + // (op 357) end: generate({358}) + // (op 39) SetCoordinate(357) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[28:29], a[0:15] // (op 111) + // (op 39) Multiply(111) END + // (op 39) SetCoordinate(362) BEGIN + // (op 362) generate({}) + // (op 362) end: generate({}) + // (op 362) generate({363}) + // (op 362) LoadLDSTile{Value: Halfx2}(363) BEGIN + // (op 363) GEN: loadMacroTileWAVELDS OP 363 LDS 360 WaveTile 145 + // (op 363) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 363) Generate 2:U32 into nullptr + // tag 388: v**UNALLOCATED** + // (op 363) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 363) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16480 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 363) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(120) BEGIN + // (op 120) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 +ds_read_b64 v[64:65], v5 offset:16480 // (op 363) Load local data +// DSMEM: Expected complete at 1573 (current 1553) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 362) LoadLDSTile{Value: Halfx2}(363) END + // (op 362) end: generate({363}) + // (op 39) SetCoordinate(362) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[30:31], a[0:15] // (op 120) + // (op 39) Multiply(120) END + // (op 39) SetCoordinate(367) BEGIN + // (op 367) generate({}) + // (op 367) end: generate({}) + // (op 367) generate({368}) + // (op 367) LoadLDSTile{Value: Halfx2}(368) BEGIN + // (op 368) GEN: loadMacroTileWAVELDS OP 368 LDS 360 WaveTile 145 + // (op 368) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 368) Generate 2:U32 into nullptr + // tag 392: v**UNALLOCATED** + // (op 368) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 368) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16496 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 368) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 +ds_read_b64 v[66:67], v5 offset:16496 // (op 368) Load local data +// DSMEM: Expected complete at 1583 (current 1563) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 367) LoadLDSTile{Value: Halfx2}(368) END + // (op 367) end: generate({368}) + // (op 39) SetCoordinate(367) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected stall of 14. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 1653 (current 1578) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Deallocate{}(1819) BEGIN + // (op 1819) Deallocate 582 + // Deleting tag 582 + // (op 39) Deallocate{}(1819) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half + // (op 39) SetCoordinate(330) BEGIN + // (op 330) generate({}) + // (op 330) end: generate({}) + // (op 330) generate({331}) + // (op 330) LoadLDSTile{Value: Halfx2}(331) BEGIN + // (op 331) GEN: loadMacroTileWAVELDS OP 331 LDS 356 WaveTile 85 + // (op 331) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 331) Generate 2:U32 into nullptr + // tag 362: v[32:33] alias 362 -> 11 + // (op 331) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 331) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 331) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +ds_read_b64 v[32:33], v4 offset:24576 // (op 331) Load local data +// DSMEM: Expected complete at 1601 (current 1581) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 330) LoadLDSTile{Value: Halfx2}(331) END + // (op 330) end: generate({331}) + // (op 39) SetCoordinate(330) END +s_add_u32 m0, m0, 1024 // (op 976) + // (op 39) SetCoordinate(335) BEGIN + // (op 335) generate({}) + // (op 335) end: generate({}) + // (op 335) generate({336}) + // (op 335) LoadLDSTile{Value: Halfx2}(336) BEGIN + // (op 336) GEN: loadMacroTileWAVELDS OP 336 LDS 356 WaveTile 85 + // (op 336) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 336) Generate 2:U32 into nullptr + // tag 366: v[34:35] alias 366 -> 253 + // (op 336) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 336) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24592 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 336) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 976) Expression temporary in special register + // Unlock None +ds_read_b64 v[34:35], v4 offset:24592 // (op 336) Load local data +// DSMEM: Expected complete at 1603 (current 1583) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 335) LoadLDSTile{Value: Halfx2}(336) END + // (op 335) end: generate({336}) + // (op 39) SetCoordinate(335) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1659 (current 1584) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(340) BEGIN + // (op 340) generate({}) + // (op 340) end: generate({}) + // (op 340) generate({341}) + // (op 340) LoadLDSTile{Value: Halfx2}(341) BEGIN + // (op 341) GEN: loadMacroTileWAVELDS OP 341 LDS 356 WaveTile 85 + // (op 341) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 341) Generate 2:U32 into nullptr + // tag 370: v[36:37] alias 370 -> 257 + // (op 341) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 341) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24608 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 341) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v4 offset:24608 // (op 341) Load local data +// DSMEM: Expected complete at 1605 (current 1585) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 340) LoadLDSTile{Value: Halfx2}(341) END + // (op 340) end: generate({341}) + // (op 39) SetCoordinate(340) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half + // (op 39) SetCoordinate(345) BEGIN + // (op 345) generate({}) + // (op 345) end: generate({}) + // (op 345) generate({346}) + // (op 345) LoadLDSTile{Value: Halfx2}(346) BEGIN + // (op 346) GEN: loadMacroTileWAVELDS OP 346 LDS 356 WaveTile 85 + // (op 346) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 346) Generate 2:U32 into nullptr + // tag 374: v**UNALLOCATED** + // (op 346) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 346) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24624 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 346) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1664 (current 1589) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) reg expression + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 976) + // (op 976) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// VMEM: Expected complete at 1668 (current 1593) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 976): v54, v55 + + // (op 604) LoadTileDirect2LDS Value: Halfx2(976) END + // (op 604) Deallocate{}(1877) BEGIN + // (op 1877) Deallocate 536 + // Deleting tag 536 + // (op 604) Deallocate{}(1877) END + // (op 604) end: generate({976}) + // (op 39) SetCoordinate(604) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 +ds_read_b64 v[50:51], v4 offset:24624 // (op 346) Load local data +// DSMEM: Expected complete at 1614 (current 1594) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 345) LoadLDSTile{Value: Halfx2}(346) END + // (op 345) end: generate({346}) + // (op 39) SetCoordinate(345) END + // (op 39) Barrier(1723) BEGIN + // (op 39) SetCoordinate(350) BEGIN + // (op 350) generate({}) + // (op 350) end: generate({}) + // (op 350) generate({351}) + // (op 350) LoadLDSTile{Value: Halfx2}(351) BEGIN + // (op 351) GEN: loadMacroTileWAVELDS OP 351 LDS 356 WaveTile 85 + // (op 351) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 351) Generate 2:U32 into nullptr + // tag 378: v[38:39] alias 378 -> 261 + // (op 351) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 351) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24640 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 351) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_barrier // (op 1723) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 39) Barrier(1723) END +ds_read_b64 v[38:39], v4 offset:24640 // (op 351) Load local data +// DSMEM: Expected stall of 6. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 1622 (current 1602) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 350) LoadLDSTile{Value: Halfx2}(351) END + // (op 350) end: generate({351}) + // (op 39) SetCoordinate(350) END + // (op 39) SetCoordinate(599) BEGIN + // (op 599) generate({}) + // (op 599) end: generate({}) + // (op 599) generate({971}) + // (op 599) LoadTileDirect2LDS Value: Halfx2(971) BEGIN + // (op 971) GEN: LoadTileDirect2LDS + // (op 971) GEN: loadMacroTileDirect2LDS OP 971 LDS 13 MacroTile 6 + // (op 971) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 971) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 971) Get arg Tensor_0_stride_0_9 + // (op 971) reg expression + // (op 971) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 971) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 971) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 971) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) SetCoordinate(355) BEGIN + // (op 355) generate({}) + // (op 355) end: generate({}) + // (op 355) generate({356}) + // (op 355) LoadLDSTile{Value: Halfx2}(356) BEGIN + // (op 356) GEN: loadMacroTileWAVELDS OP 356 LDS 356 WaveTile 85 + // (op 356) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 356) Generate 2:U32 into nullptr + // tag 382: v**UNALLOCATED** + // (op 356) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 356) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24656 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 356) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 971) + // (op 971) convert + // (op 971) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 971) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 971) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 971) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 +v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 971) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 + + // (op 971) Generate 2:U64 into nullptr + // (op 971) Generate 1024:U32 into nullptr + // (op 971) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[54:55] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 489: v**UNALLOCATED** +// Allocated Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 +v_mov_b64 v[68:69], v[14:15] // (op 971) +// Allocated : 2 VGPRs (Value: UInt64) (op 971): v70, v71 +v_mov_b64 v[70:71], v[68:69] // (op 971) + // (op 971) Generate Add(8192:U32, {DataFlowTag518: s0:U32})U32 into nullptr + // (op 971) reg expression + // (op 971) Add(8192:U32, {DataFlowTag518: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 971): s45 +s_add_u32 s45, 8192, s0 // (op 971) + // (op 971) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 971) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 971) reg expression + // (op 971) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 512 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 +s_mov_b32 s46, 512 // (op 971) call() +// 512 is not a supported value! +// Allocated : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 +ds_read_b64 v[72:73], v4 offset:24656 // (op 356) Load local data +// DSMEM: Expected complete at 1630 (current 1610) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 355) LoadLDSTile{Value: Halfx2}(356) END + // (op 355) end: generate({356}) + // (op 39) SetCoordinate(355) END +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected stall of 43. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 1729 (current 1654) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) SetCoordinate(360) BEGIN + // (op 360) generate({}) + // (op 360) end: generate({}) + // (op 360) generate({361}) + // (op 360) LoadLDSTile{Value: Halfx2}(361) BEGIN + // (op 361) GEN: loadMacroTileWAVELDS OP 361 LDS 356 WaveTile 85 + // (op 361) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 361) Generate 2:U32 into nullptr + // tag 386: v[40:41] alias 386 -> 265 + // (op 361) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 361) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24672 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 361) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[40:41], v4 offset:24672 // (op 361) Load local data +// DSMEM: Expected complete at 1675 (current 1655) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 360) LoadLDSTile{Value: Halfx2}(361) END + // (op 360) end: generate({361}) + // (op 39) SetCoordinate(360) END +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half + // (op 39) SetCoordinate(365) BEGIN + // (op 365) generate({}) + // (op 365) end: generate({}) + // (op 365) generate({366}) + // (op 365) LoadLDSTile{Value: Halfx2}(366) BEGIN + // (op 366) GEN: loadMacroTileWAVELDS OP 366 LDS 356 WaveTile 85 + // (op 366) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 366) Generate 2:U32 into nullptr + // tag 390: v**UNALLOCATED** + // (op 366) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 366) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24688 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 366) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 +ds_read_b64 v[74:75], v4 offset:24688 // (op 366) Load local data +// DSMEM: Expected complete at 1679 (current 1659) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 365) LoadLDSTile{Value: Halfx2}(366) END + // (op 365) end: generate({366}) + // (op 39) SetCoordinate(365) END +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected complete at 1735 (current 1660) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1817) BEGIN + // (op 1817) Deallocate 570 + // Deleting tag 570 + // (op 39) Deallocate{}(1817) END +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 1740 (current 1665) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected complete at 1744 (current 1669) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected stall of 57. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 1805 (current 1730) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 1811 (current 1736) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 1816 (current 1741) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) reg expression + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 971) + // (op 971) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// VMEM: Expected complete at 1820 (current 1745) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 + + // Freeing : 2 VGPRs (Value: UInt64) (op 971): v70, v71 + + // Freeing : 1 SGPR (Value: UInt32) (op 971): s45 + + // (op 599) LoadTileDirect2LDS Value: Halfx2(971) END + // (op 599) Deallocate{}(1875) BEGIN + // (op 1875) Deallocate 520 + // Deleting tag 520 + // (op 599) Deallocate{}(1875) END + // (op 599) end: generate({971}) + // (op 39) SetCoordinate(599) END + // (op 39) NOP(1000) BEGIN + // (op 1000) generate({}) + // (op 1000) end: generate({}) + // (op 39) NOP(1000) END + // (op 39) NOP(995) BEGIN + // (op 995) generate({}) + // (op 995) end: generate({}) + // (op 39) NOP(995) END + // (op 39) NOP(799) BEGIN + // (op 799) generate({}) + // (op 799) end: generate({}) + // (op 39) NOP(799) END + // (op 39) Multiply(334) BEGIN + // (op 334) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(853) BEGIN + // (op 39) Barrier(1746) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 853) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 39) Barrier(853) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 334) + // (op 39) Multiply(334) END +s_barrier // (op 1746) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 39) Barrier(1746) END + // (op 39) Deallocate{}(1803) BEGIN + // (op 1803) Deallocate 364 + // Deleting tag 364alias (-> 19) + // (op 1803) Deallocate 362 + // Deleting tag 362alias (-> 11) + // (op 39) Deallocate{}(1803) END + // (op 39) SetCoordinate(615) BEGIN + // (op 615) generate({}) + // (op 615) end: generate({}) + // (op 615) generate({998}) + // (op 615) LoadTileDirect2LDS Value: Halfx2(998) BEGIN + // (op 998) GEN: LoadTileDirect2LDS + // (op 998) GEN: loadMacroTileDirect2LDS OP 998 LDS 360 MacroTile 358 + // (op 998) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 998) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 998) Get arg Tensor_2_stride_1_12 + // (op 998) reg expression + // (op 998) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 998) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 998) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 998) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) Multiply(339) BEGIN + // (op 339) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(422) BEGIN + // (op 422) generate({}) + // (op 422) end: generate({}) + // (op 422) generate({423}) + // (op 422) LoadLDSTile{Value: Halfx2}(423) BEGIN + // (op 423) GEN: loadMacroTileWAVELDS OP 423 LDS 400 WaveTile 145 + // (op 423) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 423) Generate 2:U32 into nullptr + // tag 404: v[12:13] alias 404 -> 19 + // (op 423) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 423) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 423) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[12:13], v7 offset:32768 // (op 423) Load local data +// DSMEM: Expected complete at 1771 (current 1751) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 422) LoadLDSTile{Value: Halfx2}(423) END + // (op 422) end: generate({423}) + // (op 39) SetCoordinate(422) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 998) + // (op 998) convert + // (op 998) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 998) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 998) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 998) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(427) BEGIN + // (op 427) generate({}) + // (op 427) end: generate({}) + // (op 427) generate({428}) + // (op 427) LoadLDSTile{Value: Halfx2}(428) BEGIN + // (op 428) GEN: loadMacroTileWAVELDS OP 428 LDS 400 WaveTile 145 + // (op 428) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 428) Generate 2:U32 into nullptr + // tag 408: v[16:17] alias 408 -> 255 + // (op 428) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 428) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32784 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 428) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[16:17], v7 offset:32784 // (op 428) Load local data +// DSMEM: Expected complete at 1773 (current 1753) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 427) LoadLDSTile{Value: Halfx2}(428) END + // (op 427) end: generate({428}) + // (op 39) SetCoordinate(427) END +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 +v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 998) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 + + // (op 998) Generate 2:U64 into nullptr + // (op 998) Generate 1024:U32 into nullptr + // (op 998) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 16384 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[54:55] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // (op 39) SetCoordinate(432) BEGIN + // (op 432) generate({}) + // (op 432) end: generate({}) + // (op 432) generate({433}) + // (op 432) LoadLDSTile{Value: Halfx2}(433) BEGIN + // (op 433) GEN: loadMacroTileWAVELDS OP 433 LDS 400 WaveTile 145 + // (op 433) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 433) Generate 2:U32 into nullptr + // tag 412: v[20:21] alias 412 -> 259 + // (op 433) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 433) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32800 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 433) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[20:21], v7 offset:32800 // (op 433) Load local data +// DSMEM: Expected complete at 1775 (current 1755) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 432) LoadLDSTile{Value: Halfx2}(433) END + // (op 432) end: generate({433}) + // (op 39) SetCoordinate(432) END +// Allocated : 2 VGPRs (Value: UInt64) (op 998): v70, v71 +v_mov_b64 v[70:71], v[52:53] // (op 998) + // (op 998) Generate Add(16384:U32, {DataFlowTag572: s17:U32})U32 into nullptr + // (op 998) reg expression + // (op 998) Add(16384:U32, {DataFlowTag572: s17:U32})U32 + // (op 39) SetCoordinate(437) BEGIN + // (op 437) generate({}) + // (op 437) end: generate({}) + // (op 437) generate({438}) + // (op 437) LoadLDSTile{Value: Halfx2}(438) BEGIN + // (op 438) GEN: loadMacroTileWAVELDS OP 438 LDS 400 WaveTile 145 + // (op 438) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 438) Generate 2:U32 into nullptr + // tag 416: v[22:23] alias 416 -> 263 + // (op 438) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 438) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32816 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 438) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[22:23], v7 offset:32816 // (op 438) Load local data +// DSMEM: Expected complete at 1777 (current 1757) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 437) LoadLDSTile{Value: Halfx2}(438) END + // (op 437) end: generate({438}) + // (op 39) SetCoordinate(437) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[48:49], a[0:15] // (op 339) + // (op 39) Multiply(339) END + // (op 39) SetCoordinate(442) BEGIN + // (op 442) generate({}) + // (op 442) end: generate({}) + // (op 442) generate({443}) + // (op 442) LoadLDSTile{Value: Halfx2}(443) BEGIN + // (op 443) GEN: loadMacroTileWAVELDS OP 443 LDS 400 WaveTile 145 + // (op 443) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 443) Generate 2:U32 into nullptr + // tag 420: v[24:25] alias 420 -> 267 + // (op 443) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 443) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32832 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 443) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1805) BEGIN + // (op 1805) Deallocate 366 + // Deleting tag 366alias (-> 253) + // (op 1805) Deallocate 368 + // Freeing : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 + + // Deleting tag 368 + // (op 39) Deallocate{}(1805) END +// Allocated : 1 SGPR (Value: UInt32) (op 998): s45 +s_add_u32 s45, 16384, s17 // (op 998) + // (op 998) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 998) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) Multiply(344) BEGIN + // (op 344) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_mov_b32 m0, s45 // (op 998) reg expression + // (op 998) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 640 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 +s_mov_b32 s46, 640 // (op 998) call() +// 640 is not a supported value! +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[56:57], a[0:15] // (op 344) + // (op 39) Multiply(344) END +ds_read_b64 v[24:25], v7 offset:32832 // (op 443) Load local data +// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 1792 (current 1772) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 442) LoadLDSTile{Value: Halfx2}(443) END + // (op 442) end: generate({443}) + // (op 39) SetCoordinate(442) END + // (op 39) Deallocate{}(1807) BEGIN + // (op 1807) Deallocate 372 + // Freeing : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 + + // Deleting tag 372 + // (op 1807) Deallocate 370 + // Deleting tag 370alias (-> 257) + // (op 39) Deallocate{}(1807) END + // (op 39) SetCoordinate(447) BEGIN + // (op 447) generate({}) + // (op 447) end: generate({}) + // (op 447) generate({448}) + // (op 447) LoadLDSTile{Value: Halfx2}(448) BEGIN + // (op 448) GEN: loadMacroTileWAVELDS OP 448 LDS 400 WaveTile 145 + // (op 448) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 448) Generate 2:U32 into nullptr + // tag 424: v[26:27] alias 424 -> 271 + // (op 448) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 448) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32848 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 448) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(349) BEGIN + // (op 349) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[26:27], v7 offset:32848 // (op 448) Load local data +// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 1794 (current 1774) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 447) LoadLDSTile{Value: Halfx2}(448) END + // (op 447) end: generate({448}) + // (op 39) SetCoordinate(447) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[50:51], v[58:59], a[0:15] // (op 349) + // (op 39) Multiply(349) END + // (op 39) SetCoordinate(452) BEGIN + // (op 452) generate({}) + // (op 452) end: generate({}) + // (op 452) generate({453}) + // (op 452) LoadLDSTile{Value: Halfx2}(453) BEGIN + // (op 453) GEN: loadMacroTileWAVELDS OP 453 LDS 400 WaveTile 145 + // (op 453) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 453) Generate 2:U32 into nullptr + // tag 428: v[28:29] alias 428 -> 275 + // (op 453) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 453) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32864 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 453) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1809) BEGIN + // (op 1809) Deallocate 376 + // Freeing : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 + + // Deleting tag 376 + // (op 1809) Deallocate 374 + // Freeing : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 + + // Deleting tag 374 + // (op 39) Deallocate{}(1809) END +ds_read_b64 v[28:29], v7 offset:32864 // (op 453) Load local data +// DSMEM: Expected complete at 1800 (current 1780) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 452) LoadLDSTile{Value: Halfx2}(453) END + // (op 452) end: generate({453}) + // (op 39) SetCoordinate(452) END + // (op 39) Multiply(354) BEGIN + // (op 354) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(457) BEGIN + // (op 457) generate({}) + // (op 457) end: generate({}) + // (op 457) generate({458}) + // (op 457) LoadLDSTile{Value: Halfx2}(458) BEGIN + // (op 458) GEN: loadMacroTileWAVELDS OP 458 LDS 400 WaveTile 145 + // (op 458) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 458) Generate 2:U32 into nullptr + // tag 432: v[30:31] alias 432 -> 279 + // (op 458) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 458) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32880 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 458) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[30:31], v7 offset:32880 // (op 458) Load local data +// DSMEM: Expected complete at 1801 (current 1781) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 457) LoadLDSTile{Value: Halfx2}(458) END + // (op 457) end: generate({458}) + // (op 39) SetCoordinate(457) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[60:61], a[0:15] // (op 354) + // (op 39) Multiply(354) END + // (op 39) Deallocate{}(1839) BEGIN + // (op 1839) Deallocate 606 + // Deleting tag 606 + // (op 39) Deallocate{}(1839) END + // (op 39) Deallocate{}(1811) BEGIN + // (op 1811) Deallocate 378 + // Deleting tag 378alias (-> 261) + // (op 1811) Deallocate 380 + // Freeing : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 + + // Deleting tag 380 + // (op 39) Deallocate{}(1811) END + // (op 39) SetCoordinate(420) BEGIN + // (op 420) generate({}) + // (op 420) end: generate({}) + // (op 420) generate({421}) + // (op 420) LoadLDSTile{Value: Halfx2}(421) BEGIN + // (op 421) GEN: loadMacroTileWAVELDS OP 421 LDS 396 WaveTile 85 + // (op 421) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 421) Generate 2:U32 into nullptr + // tag 402: v[32:33] alias 402 -> 11 + // (op 421) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 421) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 421) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(359) BEGIN + // (op 359) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[32:33], v6 offset:40960 // (op 421) Load local data +// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 1813 (current 1793) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 420) LoadLDSTile{Value: Halfx2}(421) END + // (op 420) end: generate({421}) + // (op 39) SetCoordinate(420) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[62:63], a[0:15] // (op 359) + // (op 39) Multiply(359) END + // (op 39) SetCoordinate(425) BEGIN + // (op 425) generate({}) + // (op 425) end: generate({}) + // (op 425) generate({426}) + // (op 425) LoadLDSTile{Value: Halfx2}(426) BEGIN + // (op 426) GEN: loadMacroTileWAVELDS OP 426 LDS 396 WaveTile 85 + // (op 426) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 426) Generate 2:U32 into nullptr + // tag 406: v[34:35] alias 406 -> 253 + // (op 426) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 426) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40976 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 426) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1813) BEGIN + // (op 1813) Deallocate 382 + // Freeing : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 + + // Deleting tag 382 + // (op 1813) Deallocate 384 + // Freeing : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 + + // Deleting tag 384 + // (op 39) Deallocate{}(1813) END +ds_read_b64 v[34:35], v6 offset:40976 // (op 426) Load local data +// DSMEM: Expected complete at 1820 (current 1800) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 425) LoadLDSTile{Value: Halfx2}(426) END + // (op 425) end: generate({426}) + // (op 39) SetCoordinate(425) END + // (op 39) Multiply(364) BEGIN + // (op 364) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(430) BEGIN + // (op 430) generate({}) + // (op 430) end: generate({}) + // (op 430) generate({431}) + // (op 430) LoadLDSTile{Value: Halfx2}(431) BEGIN + // (op 431) GEN: loadMacroTileWAVELDS OP 431 LDS 396 WaveTile 85 + // (op 431) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 431) Generate 2:U32 into nullptr + // tag 410: v[36:37] alias 410 -> 257 + // (op 431) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 431) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40992 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 431) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v6 offset:40992 // (op 431) Load local data +// DSMEM: Expected complete at 1821 (current 1801) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 430) LoadLDSTile{Value: Halfx2}(431) END + // (op 430) end: generate({431}) + // (op 39) SetCoordinate(430) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected stall of 4. CBNW: 28, Inc: 4 +// VMEM: Expected complete at 1881 (current 1806) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) SetCoordinate(435) BEGIN + // (op 435) generate({}) + // (op 435) end: generate({}) + // (op 435) generate({436}) + // (op 435) LoadLDSTile{Value: Halfx2}(436) BEGIN + // (op 436) GEN: loadMacroTileWAVELDS OP 436 LDS 396 WaveTile 85 + // (op 436) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 436) Generate 2:U32 into nullptr + // tag 414: v[42:43] alias 414 -> 269 + // (op 436) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 436) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41008 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 436) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[42:43], v6 offset:41008 // (op 436) Load local data +// DSMEM: Expected complete at 1827 (current 1807) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 435) LoadLDSTile{Value: Halfx2}(436) END + // (op 435) end: generate({436}) + // (op 39) SetCoordinate(435) END +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[64:65], a[0:15] // (op 364) + // (op 39) Multiply(364) END + // (op 39) SetCoordinate(440) BEGIN + // (op 440) generate({}) + // (op 440) end: generate({}) + // (op 440) generate({441}) + // (op 440) LoadLDSTile{Value: Halfx2}(441) BEGIN + // (op 441) GEN: loadMacroTileWAVELDS OP 441 LDS 396 WaveTile 85 + // (op 441) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 441) Generate 2:U32 into nullptr + // tag 418: v[44:45] alias 418 -> 273 + // (op 441) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 441) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41024 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 441) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1815) BEGIN + // (op 1815) Deallocate 386 + // Deleting tag 386alias (-> 265) + // (op 1815) Deallocate 388 + // Freeing : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 + + // Deleting tag 388 + // (op 39) Deallocate{}(1815) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half + // (op 39) Multiply(369) BEGIN + // (op 369) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected complete at 1888 (current 1813) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +ds_read_b64 v[44:45], v6 offset:41024 // (op 441) Load local data +// DSMEM: Expected complete at 1834 (current 1814) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 440) LoadLDSTile{Value: Halfx2}(441) END + // (op 440) end: generate({441}) + // (op 39) SetCoordinate(440) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half + // (op 39) SetCoordinate(445) BEGIN + // (op 445) generate({}) + // (op 445) end: generate({}) + // (op 445) generate({446}) + // (op 445) LoadLDSTile{Value: Halfx2}(446) BEGIN + // (op 446) GEN: loadMacroTileWAVELDS OP 446 LDS 396 WaveTile 85 + // (op 446) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 446) Generate 2:U32 into nullptr + // tag 422: v[46:47] alias 422 -> 277 + // (op 446) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 446) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41040 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 446) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[66:67], a[0:15] // (op 369) + // (op 39) Multiply(369) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected complete at 1895 (current 1820) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1821) BEGIN + // (op 1821) Deallocate 392 + // Freeing : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 + + // Deleting tag 392 + // (op 1821) Deallocate 390 + // Freeing : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 + + // Deleting tag 390 + // (op 39) Deallocate{}(1821) END +ds_read_b64 v[46:47], v6 offset:41040 // (op 446) Load local data +// DSMEM: Expected complete at 1841 (current 1821) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 445) LoadLDSTile{Value: Halfx2}(446) END + // (op 445) end: generate({446}) + // (op 39) SetCoordinate(445) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half + // (op 39) SetCoordinate(450) BEGIN + // (op 450) generate({}) + // (op 450) end: generate({}) + // (op 450) generate({451}) + // (op 450) LoadLDSTile{Value: Halfx2}(451) BEGIN + // (op 451) GEN: loadMacroTileWAVELDS OP 451 LDS 396 WaveTile 85 + // (op 451) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 451) Generate 2:U32 into nullptr + // tag 426: v[38:39] alias 426 -> 261 + // (op 451) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 451) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41056 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 451) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +ds_read_b64 v[38:39], v6 offset:41056 // (op 451) Load local data +// DSMEM: Expected complete at 1844 (current 1824) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 450) LoadLDSTile{Value: Halfx2}(451) END + // (op 450) end: generate({451}) + // (op 39) SetCoordinate(450) END +s_add_u32 m0, m0, 1024 // (op 998) + // (op 39) SetCoordinate(455) BEGIN + // (op 455) generate({}) + // (op 455) end: generate({}) + // (op 455) generate({456}) + // (op 455) LoadLDSTile{Value: Halfx2}(456) BEGIN + // (op 456) GEN: loadMacroTileWAVELDS OP 456 LDS 396 WaveTile 85 + // (op 456) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 456) Generate 2:U32 into nullptr + // tag 430: v**UNALLOCATED** + // (op 456) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 456) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41072 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 456) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 998) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected complete at 1901 (current 1826) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 456): v48, v49 +ds_read_b64 v[48:49], v6 offset:41072 // (op 456) Load local data +// DSMEM: Expected complete at 1850 (current 1830) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 455) LoadLDSTile{Value: Halfx2}(456) END + // (op 455) end: generate({456}) + // (op 39) SetCoordinate(455) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 1957 (current 1882) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1837) BEGIN + // (op 1837) Deallocate 594 + // Deleting tag 594 + // (op 39) Deallocate{}(1837) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 +// VMEM: Expected complete at 1964 (current 1889) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 1971 (current 1896) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) reg expression + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 998) + // (op 998) Expression temporary in special register + // Unlock None +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 1977 (current 1902) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 + + // Freeing : 2 VGPRs (Value: UInt64) (op 998): v70, v71 + + // Freeing : 1 SGPR (Value: UInt32) (op 998): s45 + + // (op 615) LoadTileDirect2LDS Value: Halfx2(998) END + // (op 615) Deallocate{}(1885) BEGIN + // (op 1885) Deallocate 574 + // Deleting tag 574 + // (op 615) Deallocate{}(1885) END + // (op 615) end: generate({998}) + // (op 39) SetCoordinate(615) END + // (op 39) Barrier(1743) BEGIN +s_barrier // (op 1743) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 39) Barrier(1743) END + // (op 39) SetCoordinate(610) BEGIN + // (op 610) generate({}) + // (op 610) end: generate({}) + // (op 610) generate({993}) + // (op 610) LoadTileDirect2LDS Value: Halfx2(993) BEGIN + // (op 993) GEN: LoadTileDirect2LDS + // (op 993) GEN: loadMacroTileDirect2LDS OP 993 LDS 356 MacroTile 354 + // (op 993) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 993) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 993) Get arg Tensor_0_stride_0_9 + // (op 993) reg expression + // (op 993) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 993) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 993) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 993) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 993) + // (op 993) convert + // (op 993) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 993) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 993) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 993) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 993): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 993) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 + + // (op 993) Generate 2:U64 into nullptr + // (op 993) Generate 1024:U32 into nullptr + // (op 993) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 24576 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 993): v54, v55 +v_mov_b64 v[54:55], v[68:69] // (op 993) + // (op 993) Generate Add(24576:U32, {DataFlowTag560: s16:U32})U32 into nullptr + // (op 993) reg expression + // (op 993) Add(24576:U32, {DataFlowTag560: s16:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 993): s45 +s_add_u32 s45, 24576, s16 // (op 993) + // (op 993) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 993) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 993) reg expression + // (op 993) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 640 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 +s_mov_b32 s46, 640 // (op 993) call() +// 640 is not a supported value! +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 48. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2033 (current 1958) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2040 (current 1965) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2047 (current 1972) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2053 (current 1978) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2109 (current 2034) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2116 (current 2041) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2123 (current 2048) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 993) reg expression + // (op 993) reg expression + // (op 993) Add(v[54:55]:U64, v50:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 993) + // (op 993) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2129 (current 2054) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 993): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 993): v54, v55 + + // Freeing : 1 SGPR (Value: UInt32) (op 993): s45 + + // (op 610) LoadTileDirect2LDS Value: Halfx2(993) END + // (op 610) Deallocate{}(1883) BEGIN + // (op 1883) Deallocate 562 + // Deleting tag 562 + // (op 610) Deallocate{}(1883) END + // (op 610) end: generate({993}) + // (op 39) SetCoordinate(610) END + // (op 39) NOP(1010) BEGIN + // (op 1010) generate({}) + // (op 1010) end: generate({}) + // (op 39) NOP(1010) END + // (op 39) NOP(1005) BEGIN + // (op 1005) generate({}) + // (op 1005) end: generate({}) + // (op 39) NOP(1005) END + // (op 39) NOP(800) BEGIN + // (op 800) generate({}) + // (op 800) end: generate({}) + // (op 39) NOP(800) END + // (op 39) Multiply(424) BEGIN + // (op 424) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(895) BEGIN + // (op 39) Barrier(1752) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 895) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 39) Barrier(895) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 424) + // (op 39) Multiply(424) END +s_barrier // (op 1752) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 39) Barrier(1752) END + // (op 39) Deallocate{}(1823) BEGIN + // (op 1823) Deallocate 402 + // Deleting tag 402alias (-> 11) + // (op 1823) Deallocate 404 + // Deleting tag 404alias (-> 19) + // (op 39) Deallocate{}(1823) END + // (op 39) SetCoordinate(629) BEGIN + // (op 629) generate({}) + // (op 629) end: generate({}) + // (op 629) generate({1008}) + // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) BEGIN + // (op 1008) GEN: LoadTileDirect2LDS + // (op 1008) GEN: loadMacroTileDirect2LDS OP 1008 LDS 400 MacroTile 398 + // (op 1008) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1008) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 1008) Get arg Tensor_2_stride_1_12 + // (op 1008) reg expression + // (op 1008) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1008) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1008) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) Multiply(429) BEGIN + // (op 429) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(512) BEGIN + // (op 512) generate({}) + // (op 512) end: generate({}) + // (op 512) generate({513}) + // (op 512) LoadLDSTile{Value: Halfx2}(513) BEGIN + // (op 513) GEN: loadMacroTileWAVELDS OP 513 LDS 440 WaveTile 145 + // (op 513) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 513) Generate 2:U32 into nullptr + // tag 444: v[12:13] alias 444 -> 19 + // (op 513) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 513) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 513) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[12:13], v9 offset:49152 // (op 513) Load local data +// DSMEM: Expected complete at 2080 (current 2060) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 512) LoadLDSTile{Value: Halfx2}(513) END + // (op 512) end: generate({513}) + // (op 39) SetCoordinate(512) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 1008) + // (op 1008) convert + // (op 1008) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1008) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1008) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(517) BEGIN + // (op 517) generate({}) + // (op 517) end: generate({}) + // (op 517) generate({518}) + // (op 517) LoadLDSTile{Value: Halfx2}(518) BEGIN + // (op 518) GEN: loadMacroTileWAVELDS OP 518 LDS 440 WaveTile 145 + // (op 518) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 518) Generate 2:U32 into nullptr + // tag 448: v**UNALLOCATED** + // (op 518) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 518) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49168 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 518) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1008): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1008) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 + + // (op 1008) Generate 2:U64 into nullptr + // (op 1008) Generate 1024:U32 into nullptr + // (op 1008) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 32768 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1008): v54, v55 +v_mov_b64 v[54:55], v[52:53] // (op 1008) + // (op 1008) Generate Add(32768:U32, {DataFlowTag596: s41:U32})U32 into nullptr + // (op 1008) reg expression + // (op 1008) Add(32768:U32, {DataFlowTag596: s41:U32})U32 +// Allocated : 2 VGPRs (Value: Halfx2) (op 518): v56, v57 +ds_read_b64 v[56:57], v9 offset:49168 // (op 518) Load local data +// DSMEM: Expected complete at 2084 (current 2064) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 517) LoadLDSTile{Value: Halfx2}(518) END + // (op 517) end: generate({518}) + // (op 39) SetCoordinate(517) END +// Allocated : 1 SGPR (Value: UInt32) (op 1008): s45 +s_add_u32 s45, 32768, s41 // (op 1008) + // (op 1008) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1008) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) SetCoordinate(522) BEGIN + // (op 522) generate({}) + // (op 522) end: generate({}) + // (op 522) generate({523}) + // (op 522) LoadLDSTile{Value: Halfx2}(523) BEGIN + // (op 523) GEN: loadMacroTileWAVELDS OP 523 LDS 440 WaveTile 145 + // (op 523) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 523) Generate 2:U32 into nullptr + // tag 452: v**UNALLOCATED** + // (op 523) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 523) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49184 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 523) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_mov_b32 m0, s45 // (op 1008) reg expression + // (op 1008) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 768 is not a supported value! +// Allocated : 2 VGPRs (Value: Halfx2) (op 523): v58, v59 +ds_read_b64 v[58:59], v9 offset:49184 // (op 523) Load local data +// DSMEM: Expected complete at 2087 (current 2067) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 522) LoadLDSTile{Value: Halfx2}(523) END + // (op 522) end: generate({523}) + // (op 39) SetCoordinate(522) END +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[16:17], a[0:15] // (op 429) + // (op 39) Multiply(429) END + // (op 39) SetCoordinate(527) BEGIN + // (op 527) generate({}) + // (op 527) end: generate({}) + // (op 527) generate({528}) + // (op 527) LoadLDSTile{Value: Halfx2}(528) BEGIN + // (op 528) GEN: loadMacroTileWAVELDS OP 528 LDS 440 WaveTile 145 + // (op 528) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 528) Generate 2:U32 into nullptr + // tag 456: v**UNALLOCATED** + // (op 528) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 528) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49200 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 528) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1825) BEGIN + // (op 1825) Deallocate 406 + // Deleting tag 406alias (-> 253) + // (op 1825) Deallocate 408 + // Deleting tag 408alias (-> 255) + // (op 39) Deallocate{}(1825) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 +ds_read_b64 v[60:61], v9 offset:49200 // (op 528) Load local data +// DSMEM: Expected complete at 2090 (current 2070) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 527) LoadLDSTile{Value: Halfx2}(528) END + // (op 527) end: generate({528}) + // (op 39) SetCoordinate(527) END + // (op 39) Multiply(434) BEGIN + // (op 434) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(532) BEGIN + // (op 532) generate({}) + // (op 532) end: generate({}) + // (op 532) generate({533}) + // (op 532) LoadLDSTile{Value: Halfx2}(533) BEGIN + // (op 533) GEN: loadMacroTileWAVELDS OP 533 LDS 440 WaveTile 145 + // (op 533) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 533) Generate 2:U32 into nullptr + // tag 460: v**UNALLOCATED** + // (op 533) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 533) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49216 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 533) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 +s_mov_b32 s46, 768 // (op 1008) call() +// 768 is not a supported value! +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 434) + // (op 39) Multiply(434) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 533): v62, v63 +ds_read_b64 v[62:63], v9 offset:49216 // (op 533) Load local data +// DSMEM: Expected stall of 1. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 2101 (current 2081) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 532) LoadLDSTile{Value: Halfx2}(533) END + // (op 532) end: generate({533}) + // (op 39) SetCoordinate(532) END + // (op 39) Deallocate{}(1827) BEGIN + // (op 1827) Deallocate 410 + // Deleting tag 410alias (-> 257) + // (op 1827) Deallocate 412 + // Deleting tag 412alias (-> 259) + // (op 39) Deallocate{}(1827) END + // (op 39) SetCoordinate(537) BEGIN + // (op 537) generate({}) + // (op 537) end: generate({}) + // (op 537) generate({538}) + // (op 537) LoadLDSTile{Value: Halfx2}(538) BEGIN + // (op 538) GEN: loadMacroTileWAVELDS OP 538 LDS 440 WaveTile 145 + // (op 538) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 538) Generate 2:U32 into nullptr + // tag 464: v**UNALLOCATED** + // (op 538) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 538) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49232 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 538) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(439) BEGIN + // (op 439) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 538): v64, v65 +ds_read_b64 v[64:65], v9 offset:49232 // (op 538) Load local data +// DSMEM: Expected stall of 3. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 2105 (current 2085) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 537) LoadLDSTile{Value: Halfx2}(538) END + // (op 537) end: generate({538}) + // (op 39) SetCoordinate(537) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[22:23], a[0:15] // (op 439) + // (op 39) Multiply(439) END + // (op 39) SetCoordinate(542) BEGIN + // (op 542) generate({}) + // (op 542) end: generate({}) + // (op 542) generate({543}) + // (op 542) LoadLDSTile{Value: Halfx2}(543) BEGIN + // (op 543) GEN: loadMacroTileWAVELDS OP 543 LDS 440 WaveTile 145 + // (op 543) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 543) Generate 2:U32 into nullptr + // tag 468: v**UNALLOCATED** + // (op 543) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 543) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49248 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 543) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1829) BEGIN + // (op 1829) Deallocate 414 + // Deleting tag 414alias (-> 269) + // (op 1829) Deallocate 416 + // Deleting tag 416alias (-> 263) + // (op 39) Deallocate{}(1829) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 543): v66, v67 +ds_read_b64 v[66:67], v9 offset:49248 // (op 543) Load local data +// DSMEM: Expected complete at 2110 (current 2090) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 542) LoadLDSTile{Value: Halfx2}(543) END + // (op 542) end: generate({543}) + // (op 39) SetCoordinate(542) END + // (op 39) Multiply(444) BEGIN + // (op 444) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(547) BEGIN + // (op 547) generate({}) + // (op 547) end: generate({}) + // (op 547) generate({548}) + // (op 547) LoadLDSTile{Value: Halfx2}(548) BEGIN + // (op 548) GEN: loadMacroTileWAVELDS OP 548 LDS 440 WaveTile 145 + // (op 548) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 548) Generate 2:U32 into nullptr + // tag 472: v**UNALLOCATED** + // (op 548) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 548) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49264 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 548) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 +ds_read_b64 v[70:71], v9 offset:49264 // (op 548) Load local data +// DSMEM: Expected complete at 2111 (current 2091) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 547) LoadLDSTile{Value: Halfx2}(548) END + // (op 547) end: generate({548}) + // (op 39) SetCoordinate(547) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[24:25], a[0:15] // (op 444) + // (op 39) Multiply(444) END + // (op 39) Deallocate{}(1859) BEGIN + // (op 1859) Deallocate 630 + // Deleting tag 630 + // (op 39) Deallocate{}(1859) END + // (op 39) Deallocate{}(1831) BEGIN + // (op 1831) Deallocate 418 + // Deleting tag 418alias (-> 273) + // (op 1831) Deallocate 420 + // Deleting tag 420alias (-> 267) + // (op 39) Deallocate{}(1831) END + // (op 39) SetCoordinate(510) BEGIN + // (op 510) generate({}) + // (op 510) end: generate({}) + // (op 510) generate({511}) + // (op 510) LoadLDSTile{Value: Halfx2}(511) BEGIN + // (op 511) GEN: loadMacroTileWAVELDS OP 511 LDS 436 WaveTile 85 + // (op 511) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 511) Generate 2:U32 into nullptr + // tag 442: v[32:33] alias 442 -> 11 + // (op 511) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 511) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 511) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(449) BEGIN + // (op 449) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[32:33], v8 offset:57344 // (op 511) Load local data +// DSMEM: Expected stall of 2. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 2122 (current 2102) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 510) LoadLDSTile{Value: Halfx2}(511) END + // (op 510) end: generate({511}) + // (op 39) SetCoordinate(510) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[26:27], a[0:15] // (op 449) + // (op 39) Multiply(449) END + // (op 39) SetCoordinate(515) BEGIN + // (op 515) generate({}) + // (op 515) end: generate({}) + // (op 515) generate({516}) + // (op 515) LoadLDSTile{Value: Halfx2}(516) BEGIN + // (op 516) GEN: loadMacroTileWAVELDS OP 516 LDS 436 WaveTile 85 + // (op 516) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 516) Generate 2:U32 into nullptr + // tag 446: v[34:35] alias 446 -> 253 + // (op 516) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 516) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57360 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 516) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1833) BEGIN + // (op 1833) Deallocate 422 + // Deleting tag 422alias (-> 277) + // (op 1833) Deallocate 424 + // Deleting tag 424alias (-> 271) + // (op 39) Deallocate{}(1833) END +ds_read_b64 v[34:35], v8 offset:57360 // (op 516) Load local data +// DSMEM: Expected complete at 2130 (current 2110) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 515) LoadLDSTile{Value: Halfx2}(516) END + // (op 515) end: generate({516}) + // (op 39) SetCoordinate(515) END + // (op 39) Multiply(454) BEGIN + // (op 454) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(520) BEGIN + // (op 520) generate({}) + // (op 520) end: generate({}) + // (op 520) generate({521}) + // (op 520) LoadLDSTile{Value: Halfx2}(521) BEGIN + // (op 521) GEN: loadMacroTileWAVELDS OP 521 LDS 436 WaveTile 85 + // (op 521) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 521) Generate 2:U32 into nullptr + // tag 450: v[36:37] alias 450 -> 257 + // (op 521) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 521) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57376 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 521) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v8 offset:57376 // (op 521) Load local data +// DSMEM: Expected complete at 2131 (current 2111) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 520) LoadLDSTile{Value: Halfx2}(521) END + // (op 520) end: generate({521}) + // (op 39) SetCoordinate(520) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected complete at 2187 (current 2112) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(525) BEGIN + // (op 525) generate({}) + // (op 525) end: generate({}) + // (op 525) generate({526}) + // (op 525) LoadLDSTile{Value: Halfx2}(526) BEGIN + // (op 526) GEN: loadMacroTileWAVELDS OP 526 LDS 436 WaveTile 85 + // (op 526) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 526) Generate 2:U32 into nullptr + // tag 454: v[40:41] alias 454 -> 265 + // (op 526) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 526) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57392 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 526) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[40:41], v8 offset:57392 // (op 526) Load local data +// DSMEM: Expected complete at 2133 (current 2113) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 525) LoadLDSTile{Value: Halfx2}(526) END + // (op 525) end: generate({526}) + // (op 39) SetCoordinate(525) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half + // (op 39) SetCoordinate(530) BEGIN + // (op 530) generate({}) + // (op 530) end: generate({}) + // (op 530) generate({531}) + // (op 530) LoadLDSTile{Value: Halfx2}(531) BEGIN + // (op 531) GEN: loadMacroTileWAVELDS OP 531 LDS 436 WaveTile 85 + // (op 531) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 531) Generate 2:U32 into nullptr + // tag 458: v**UNALLOCATED** + // (op 531) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 531) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57408 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 531) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected complete at 2192 (current 2117) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[28:29], a[0:15] // (op 454) + // (op 39) Multiply(454) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half + // (op 39) Deallocate{}(1835) BEGIN + // (op 1835) Deallocate 426 + // Deleting tag 426alias (-> 261) + // (op 1835) Deallocate 428 + // Deleting tag 428alias (-> 275) + // (op 39) Deallocate{}(1835) END +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 39) Multiply(459) BEGIN + // (op 459) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 +ds_read_b64 v[72:73], v8 offset:57408 // (op 531) Load local data +// DSMEM: Expected complete at 2143 (current 2123) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 530) LoadLDSTile{Value: Halfx2}(531) END + // (op 530) end: generate({531}) + // (op 39) SetCoordinate(530) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected complete at 2199 (current 2124) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(535) BEGIN + // (op 535) generate({}) + // (op 535) end: generate({}) + // (op 535) generate({536}) + // (op 535) LoadLDSTile{Value: Halfx2}(536) BEGIN + // (op 536) GEN: loadMacroTileWAVELDS OP 536 LDS 436 WaveTile 85 + // (op 536) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 536) Generate 2:U32 into nullptr + // tag 462: v**UNALLOCATED** + // (op 536) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 536) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57424 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 536) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[48:49], v[30:31], a[0:15] // (op 459) + // (op 39) Multiply(459) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected complete at 2205 (current 2130) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Deallocate{}(1841) BEGIN + // (op 1841) Deallocate 430 + // Freeing : 2 VGPRs (Value: Halfx2) (op 456): v48, v49 + + // Deleting tag 430 + // (op 1841) Deallocate 432 + // Deleting tag 432alias (-> 279) + // (op 39) Deallocate{}(1841) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 536): v48, v49 +ds_read_b64 v[48:49], v8 offset:57424 // (op 536) Load local data +// DSMEM: Expected complete at 2151 (current 2131) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 535) LoadLDSTile{Value: Halfx2}(536) END + // (op 535) end: generate({536}) + // (op 39) SetCoordinate(535) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half + // (op 39) SetCoordinate(540) BEGIN + // (op 540) generate({}) + // (op 540) end: generate({}) + // (op 540) generate({541}) + // (op 540) LoadLDSTile{Value: Halfx2}(541) BEGIN + // (op 541) GEN: loadMacroTileWAVELDS OP 541 LDS 436 WaveTile 85 + // (op 541) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 541) Generate 2:U32 into nullptr + // tag 466: v**UNALLOCATED** + // (op 541) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 541) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57440 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 541) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 +ds_read_b64 v[74:75], v8 offset:57440 // (op 541) Load local data +// DSMEM: Expected complete at 2155 (current 2135) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 540) LoadLDSTile{Value: Halfx2}(541) END + // (op 540) end: generate({541}) + // (op 39) SetCoordinate(540) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected stall of 52. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 2263 (current 2188) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(545) BEGIN + // (op 545) generate({}) + // (op 545) end: generate({}) + // (op 545) generate({546}) + // (op 545) LoadLDSTile{Value: Halfx2}(546) BEGIN + // (op 546) GEN: loadMacroTileWAVELDS OP 546 LDS 436 WaveTile 85 + // (op 546) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 546) Generate 2:U32 into nullptr + // tag 470: v**UNALLOCATED** + // (op 546) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 546) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57456 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 546) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +// Allocated : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 +ds_read_b64 v[76:77], v8 offset:57456 // (op 546) Load local data +// DSMEM: Expected complete at 2212 (current 2192) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 545) LoadLDSTile{Value: Halfx2}(546) END + // (op 545) end: generate({546}) + // (op 39) SetCoordinate(545) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected complete at 2268 (current 2193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Deallocate{}(1857) BEGIN + // (op 1857) Deallocate 618 + // Deleting tag 618 + // (op 39) Deallocate{}(1857) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 2275 (current 2200) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1008) reg expression + // (op 1008) reg expression + // (op 1008) Add(v[54:55]:U64, v50:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1008) + // (op 1008) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 2281 (current 2206) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1008): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1008): v54, v55 + + // Freeing : 1 SGPR (Value: UInt32) (op 1008): s45 + + // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) END + // (op 629) Deallocate{}(1889) BEGIN + // (op 1889) Deallocate 598 + // Deleting tag 598 + // (op 629) Deallocate{}(1889) END + // (op 629) end: generate({1008}) + // (op 39) SetCoordinate(629) END + // (op 39) Barrier(1749) BEGIN +s_barrier // (op 1749) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 39) Barrier(1749) END + // (op 39) SetCoordinate(624) BEGIN + // (op 624) generate({}) + // (op 624) end: generate({}) + // (op 624) generate({1003}) + // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) BEGIN + // (op 1003) GEN: LoadTileDirect2LDS + // (op 1003) GEN: loadMacroTileDirect2LDS OP 1003 LDS 396 MacroTile 394 + // (op 1003) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1003) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 1003) Get arg Tensor_0_stride_0_9 + // (op 1003) reg expression + // (op 1003) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1003) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1003) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 1003) + // (op 1003) convert + // (op 1003) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1003) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1003) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1003): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1003) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 + + // (op 1003) Generate 2:U64 into nullptr + // (op 1003) Generate 1024:U32 into nullptr + // (op 1003) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 40960 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1003): v54, v55 +v_mov_b64 v[54:55], v[68:69] // (op 1003) + // (op 1003) Generate Add(40960:U32, {DataFlowTag584: s40:U32})U32 into nullptr + // (op 1003) reg expression + // (op 1003) Add(40960:U32, {DataFlowTag584: s40:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1003): s45 +s_add_u32 s45, 40960, s40 // (op 1003) + // (op 1003) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1003) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 1003) reg expression + // (op 1003) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 768 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 +s_mov_b32 s46, 768 // (op 1003) call() +// 768 is not a supported value! +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 50. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2339 (current 2264) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2344 (current 2269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2351 (current 2276) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2357 (current 2282) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 54. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2415 (current 2340) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2420 (current 2345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2427 (current 2352) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1003) reg expression + // (op 1003) reg expression + // (op 1003) Add(v[54:55]:U64, v50:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1003) + // (op 1003) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2433 (current 2358) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1003): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1003): v54, v55 + + // Freeing : 1 SGPR (Value: UInt32) (op 1003): s45 + + // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) END + // (op 624) Deallocate{}(1887) BEGIN + // (op 1887) Deallocate 586 + // Deleting tag 586 + // (op 624) Deallocate{}(1887) END + // (op 624) end: generate({1003}) + // (op 39) SetCoordinate(624) END + // (op 39) NOP(1020) BEGIN + // (op 1020) generate({}) + // (op 1020) end: generate({}) + // (op 39) NOP(1020) END + // (op 39) NOP(1015) BEGIN + // (op 1015) generate({}) + // (op 1015) end: generate({}) + // (op 39) NOP(1015) END + // (op 39) NOP(801) BEGIN + // (op 801) generate({}) + // (op 801) end: generate({}) + // (op 39) NOP(801) END + // (op 39) Multiply(514) BEGIN + // (op 514) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(937) BEGIN + // (op 39) Barrier(1758) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 937) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 39) Barrier(937) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 514) + // (op 39) Multiply(514) END +s_barrier // (op 1758) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 39) Barrier(1758) END + // (op 39) Deallocate{}(1843) BEGIN + // (op 1843) Deallocate 442 + // Deleting tag 442alias (-> 11) + // (op 1843) Deallocate 444 + // Deleting tag 444alias (-> 19) + // (op 39) Deallocate{}(1843) END + // (op 39) SetCoordinate(643) BEGIN + // (op 643) generate({}) + // (op 643) end: generate({}) + // (op 643) generate({1018}) + // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) BEGIN + // (op 1018) GEN: LoadTileDirect2LDS + // (op 1018) GEN: loadMacroTileDirect2LDS OP 1018 LDS 440 MacroTile 438 + // (op 1018) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1018) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 1018) Get arg Tensor_2_stride_1_12 + // (op 1018) reg expression + // (op 1018) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1018) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1018) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) SetCoordinate(52) BEGIN + // (op 52) generate({}) + // (op 52) end: generate({}) + // (op 52) generate({54}) + // (op 52) LoadLDSTile{Value: Halfx2}(54) BEGIN + // (op 54) GEN: loadMacroTileWAVELDS OP 54 LDS 21 WaveTile 145 + // (op 54) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 54) Generate 2:U32 into nullptr + // (op 54) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 54) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[12:13] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 54) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(519) BEGIN + // (op 519) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[12:13], v3 // (op 54) Load local data +// DSMEM: Expected complete at 2384 (current 2364) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 52) LoadLDSTile{Value: Halfx2}(54) END + // (op 52) end: generate({54}) + // (op 39) SetCoordinate(52) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 1018) + // (op 1018) convert + // (op 1018) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1018) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1018) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(62) BEGIN + // (op 62) generate({}) + // (op 62) end: generate({}) + // (op 62) generate({64}) + // (op 62) LoadLDSTile{Value: Halfx2}(64) BEGIN + // (op 64) GEN: loadMacroTileWAVELDS OP 64 LDS 21 WaveTile 145 + // (op 64) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 64) Generate 2:U32 into nullptr + // (op 64) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 64) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 64) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[16:17], v3 offset:16 // (op 64) Load local data +// DSMEM: Expected complete at 2386 (current 2366) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 62) LoadLDSTile{Value: Halfx2}(64) END + // (op 62) end: generate({64}) + // (op 39) SetCoordinate(62) END +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1018): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1018) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 + + // (op 1018) Generate 2:U64 into nullptr + // (op 1018) Generate 1024:U32 into nullptr + // (op 1018) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 49152 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // (op 39) SetCoordinate(71) BEGIN + // (op 71) generate({}) + // (op 71) end: generate({}) + // (op 71) generate({73}) + // (op 71) LoadLDSTile{Value: Halfx2}(73) BEGIN + // (op 73) GEN: loadMacroTileWAVELDS OP 73 LDS 21 WaveTile 145 + // (op 73) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 73) Generate 2:U32 into nullptr + // (op 73) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 73) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 73) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[20:21], v3 offset:32 // (op 73) Load local data +// DSMEM: Expected complete at 2388 (current 2368) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 71) LoadLDSTile{Value: Halfx2}(73) END + // (op 71) end: generate({73}) + // (op 39) SetCoordinate(71) END +// Allocated : 2 VGPRs (Value: UInt64) (op 1018): v54, v55 +v_mov_b64 v[54:55], v[52:53] // (op 1018) + // (op 1018) Generate Add(49152:U32, {DataFlowTag620: s43:U32})U32 into nullptr + // (op 1018) reg expression + // (op 1018) Add(49152:U32, {DataFlowTag620: s43:U32})U32 + // (op 39) SetCoordinate(80) BEGIN + // (op 80) generate({}) + // (op 80) end: generate({}) + // (op 80) generate({82}) + // (op 80) LoadLDSTile{Value: Halfx2}(82) BEGIN + // (op 82) GEN: loadMacroTileWAVELDS OP 82 LDS 21 WaveTile 145 + // (op 82) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 82) Generate 2:U32 into nullptr + // (op 82) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 82) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 82) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[22:23], v3 offset:48 // (op 82) Load local data +// DSMEM: Expected complete at 2390 (current 2370) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 80) LoadLDSTile{Value: Halfx2}(82) END + // (op 80) end: generate({82}) + // (op 39) SetCoordinate(80) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[56:57], a[0:15] // (op 519) + // (op 39) Multiply(519) END + // (op 39) SetCoordinate(89) BEGIN + // (op 89) generate({}) + // (op 89) end: generate({}) + // (op 89) generate({91}) + // (op 89) LoadLDSTile{Value: Halfx2}(91) BEGIN + // (op 91) GEN: loadMacroTileWAVELDS OP 91 LDS 21 WaveTile 145 + // (op 91) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 91) Generate 2:U32 into nullptr + // (op 91) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 91) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 91) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1845) BEGIN + // (op 1845) Deallocate 446 + // Deleting tag 446alias (-> 253) + // (op 1845) Deallocate 448 + // Freeing : 2 VGPRs (Value: Halfx2) (op 518): v56, v57 + + // Deleting tag 448 + // (op 39) Deallocate{}(1845) END +// Allocated : 1 SGPR (Value: UInt32) (op 1018): s45 +s_add_u32 s45, 49152, s43 // (op 1018) + // (op 1018) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1018) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) Multiply(524) BEGIN + // (op 524) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_mov_b32 m0, s45 // (op 1018) reg expression + // (op 1018) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 896 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 +s_mov_b32 s46, 896 // (op 1018) call() +// 896 is not a supported value! +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[58:59], a[0:15] // (op 524) + // (op 39) Multiply(524) END +ds_read_b64 v[24:25], v3 offset:64 // (op 91) Load local data +// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 2405 (current 2385) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 89) LoadLDSTile{Value: Halfx2}(91) END + // (op 89) end: generate({91}) + // (op 39) SetCoordinate(89) END + // (op 39) Deallocate{}(1847) BEGIN + // (op 1847) Deallocate 450 + // Deleting tag 450alias (-> 257) + // (op 1847) Deallocate 452 + // Freeing : 2 VGPRs (Value: Halfx2) (op 523): v58, v59 + + // Deleting tag 452 + // (op 39) Deallocate{}(1847) END + // (op 39) SetCoordinate(98) BEGIN + // (op 98) generate({}) + // (op 98) end: generate({}) + // (op 98) generate({100}) + // (op 98) LoadLDSTile{Value: Halfx2}(100) BEGIN + // (op 100) GEN: loadMacroTileWAVELDS OP 100 LDS 21 WaveTile 145 + // (op 100) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 100) Generate 2:U32 into nullptr + // (op 100) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 100) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 100) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(529) BEGIN + // (op 529) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[26:27], v3 offset:80 // (op 100) Load local data +// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 2407 (current 2387) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 98) LoadLDSTile{Value: Halfx2}(100) END + // (op 98) end: generate({100}) + // (op 39) SetCoordinate(98) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[60:61], a[0:15] // (op 529) + // (op 39) Multiply(529) END + // (op 39) SetCoordinate(107) BEGIN + // (op 107) generate({}) + // (op 107) end: generate({}) + // (op 107) generate({109}) + // (op 107) LoadLDSTile{Value: Halfx2}(109) BEGIN + // (op 109) GEN: loadMacroTileWAVELDS OP 109 LDS 21 WaveTile 145 + // (op 109) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 109) Generate 2:U32 into nullptr + // (op 109) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 109) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 109) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1849) BEGIN + // (op 1849) Deallocate 454 + // Deleting tag 454alias (-> 265) + // (op 1849) Deallocate 456 + // Freeing : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 + + // Deleting tag 456 + // (op 39) Deallocate{}(1849) END +ds_read_b64 v[28:29], v3 offset:96 // (op 109) Load local data +// DSMEM: Expected complete at 2413 (current 2393) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 107) LoadLDSTile{Value: Halfx2}(109) END + // (op 107) end: generate({109}) + // (op 39) SetCoordinate(107) END + // (op 39) Multiply(534) BEGIN + // (op 534) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(116) BEGIN + // (op 116) generate({}) + // (op 116) end: generate({}) + // (op 116) generate({118}) + // (op 116) LoadLDSTile{Value: Halfx2}(118) BEGIN + // (op 118) GEN: loadMacroTileWAVELDS OP 118 LDS 21 WaveTile 145 + // (op 118) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 118) Generate 2:U32 into nullptr + // (op 118) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 118) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 118) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[30:31], v3 offset:112 // (op 118) Load local data +// DSMEM: Expected complete at 2414 (current 2394) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 116) LoadLDSTile{Value: Halfx2}(118) END + // (op 116) end: generate({118}) + // (op 39) SetCoordinate(116) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[62:63], a[0:15] // (op 534) + // (op 39) Multiply(534) END + // (op 39) SetCoordinate(47) BEGIN + // (op 47) generate({}) + // (op 47) end: generate({}) + // (op 47) generate({49}) + // (op 47) LoadLDSTile{Value: Halfx2}(49) BEGIN + // (op 49) GEN: loadMacroTileWAVELDS OP 49 LDS 13 WaveTile 85 + // (op 49) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 49) Generate 2:U32 into nullptr + // (op 49) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 49) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 49) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1851) BEGIN + // (op 1851) Deallocate 458 + // Freeing : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 + + // Deleting tag 458 + // (op 1851) Deallocate 460 + // Freeing : 2 VGPRs (Value: Halfx2) (op 533): v62, v63 + + // Deleting tag 460 + // (op 39) Deallocate{}(1851) END +ds_read_b64 v[32:33], v0 offset:8192 // (op 49) Load local data +// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 2426 (current 2406) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 47) LoadLDSTile{Value: Halfx2}(49) END + // (op 47) end: generate({49}) + // (op 39) SetCoordinate(47) END + // (op 39) Multiply(539) BEGIN + // (op 539) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(58) BEGIN + // (op 58) generate({}) + // (op 58) end: generate({}) + // (op 58) generate({60}) + // (op 58) LoadLDSTile{Value: Halfx2}(60) BEGIN + // (op 60) GEN: loadMacroTileWAVELDS OP 60 LDS 13 WaveTile 85 + // (op 60) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 60) Generate 2:U32 into nullptr + // (op 60) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 60) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 60) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[34:35], v0 offset:8208 // (op 60) Load local data +// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 2428 (current 2408) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 58) LoadLDSTile{Value: Halfx2}(60) END + // (op 58) end: generate({60}) + // (op 39) SetCoordinate(58) END +s_waitcnt lgkmcnt(12) +v_mfma_f32_32x32x8f16 a[0:15], v[48:49], v[64:65], a[0:15] // (op 539) + // (op 39) Multiply(539) END + // (op 39) SetCoordinate(67) BEGIN + // (op 67) generate({}) + // (op 67) end: generate({}) + // (op 67) generate({69}) + // (op 67) LoadLDSTile{Value: Halfx2}(69) BEGIN + // (op 69) GEN: loadMacroTileWAVELDS OP 69 LDS 13 WaveTile 85 + // (op 69) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 69) Generate 2:U32 into nullptr + // (op 69) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 69) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 69) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1853) BEGIN + // (op 1853) Deallocate 462 + // Freeing : 2 VGPRs (Value: Halfx2) (op 536): v48, v49 + + // Deleting tag 462 + // (op 1853) Deallocate 464 + // Freeing : 2 VGPRs (Value: Halfx2) (op 538): v64, v65 + + // Deleting tag 464 + // (op 39) Deallocate{}(1853) END +ds_read_b64 v[36:37], v0 offset:8224 // (op 69) Load local data +// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 2434 (current 2414) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 67) LoadLDSTile{Value: Halfx2}(69) END + // (op 67) end: generate({69}) + // (op 39) SetCoordinate(67) END + // (op 39) Multiply(544) BEGIN + // (op 544) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(76) BEGIN + // (op 76) generate({}) + // (op 76) end: generate({}) + // (op 76) generate({78}) + // (op 76) LoadLDSTile{Value: Halfx2}(78) BEGIN + // (op 78) GEN: loadMacroTileWAVELDS OP 78 LDS 13 WaveTile 85 + // (op 78) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 78) Generate 2:U32 into nullptr + // (op 78) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 78) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 78) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[38:39], v0 offset:8240 // (op 78) Load local data +// DSMEM: Expected complete at 2435 (current 2415) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 76) LoadLDSTile{Value: Halfx2}(78) END + // (op 76) end: generate({78}) + // (op 39) SetCoordinate(76) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected complete at 2491 (current 2416) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(85) BEGIN + // (op 85) generate({}) + // (op 85) end: generate({}) + // (op 85) generate({87}) + // (op 85) LoadLDSTile{Value: Halfx2}(87) BEGIN + // (op 87) GEN: loadMacroTileWAVELDS OP 87 LDS 13 WaveTile 85 + // (op 87) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 87) Generate 2:U32 into nullptr + // (op 87) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 87) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 87) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[66:67], a[0:15] // (op 544) + // (op 39) Multiply(544) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected complete at 2498 (current 2423) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Deallocate{}(1855) BEGIN + // (op 1855) Deallocate 466 + // Freeing : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 + + // Deleting tag 466 + // (op 1855) Deallocate 468 + // Freeing : 2 VGPRs (Value: Halfx2) (op 543): v66, v67 + + // Deleting tag 468 + // (op 39) Deallocate{}(1855) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half + // (op 39) Multiply(549) BEGIN + // (op 549) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +ds_read_b64 v[40:41], v0 offset:8256 // (op 87) Load local data +// DSMEM: Expected complete at 2447 (current 2427) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 85) LoadLDSTile{Value: Halfx2}(87) END + // (op 85) end: generate({87}) + // (op 39) SetCoordinate(85) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected complete at 2503 (current 2428) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(94) BEGIN + // (op 94) generate({}) + // (op 94) end: generate({}) + // (op 94) generate({96}) + // (op 94) LoadLDSTile{Value: Halfx2}(96) BEGIN + // (op 96) GEN: loadMacroTileWAVELDS OP 96 LDS 13 WaveTile 85 + // (op 96) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 96) Generate 2:U32 into nullptr + // (op 96) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 96) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 96) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[42:43], v0 offset:8272 // (op 96) Load local data +// DSMEM: Expected complete at 2449 (current 2429) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 94) LoadLDSTile{Value: Halfx2}(96) END + // (op 94) end: generate({96}) + // (op 39) SetCoordinate(94) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half + // (op 39) SetCoordinate(103) BEGIN + // (op 103) generate({}) + // (op 103) end: generate({}) + // (op 103) generate({105}) + // (op 103) LoadLDSTile{Value: Halfx2}(105) BEGIN + // (op 105) GEN: loadMacroTileWAVELDS OP 105 LDS 13 WaveTile 85 + // (op 105) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 105) Generate 2:U32 into nullptr + // (op 105) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 105) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 105) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_waitcnt lgkmcnt(14) +v_mfma_f32_32x32x8f16 a[0:15], v[76:77], v[70:71], a[0:15] // (op 549) + // (op 39) Multiply(549) END +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 39) Deallocate{}(1861) BEGIN + // (op 1861) Deallocate 470 + // Freeing : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 + + // Deleting tag 470 + // (op 1861) Deallocate 472 + // Freeing : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 + + // Deleting tag 472 + // (op 39) Deallocate{}(1861) END + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +ds_read_b64 v[44:45], v0 offset:8288 // (op 105) Load local data +// DSMEM: Expected complete at 2455 (current 2435) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 103) LoadLDSTile{Value: Halfx2}(105) END + // (op 103) end: generate({105}) + // (op 39) SetCoordinate(103) END +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected complete at 2511 (current 2436) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(112) BEGIN + // (op 112) generate({}) + // (op 112) end: generate({}) + // (op 112) generate({114}) + // (op 112) LoadLDSTile{Value: Halfx2}(114) BEGIN + // (op 114) GEN: loadMacroTileWAVELDS OP 114 LDS 13 WaveTile 85 + // (op 114) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 114) Generate 2:U32 into nullptr + // (op 114) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 114) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 114) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[46:47], v0 offset:8304 // (op 114) Load local data +// DSMEM: Expected complete at 2457 (current 2437) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 112) LoadLDSTile{Value: Halfx2}(114) END + // (op 112) end: generate({114}) + // (op 39) SetCoordinate(112) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 2567 (current 2492) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 +// VMEM: Expected complete at 2574 (current 2499) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 2579 (current 2504) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 1018) reg expression + // (op 1018) reg expression + // (op 1018) Add(v[54:55]:U64, v50:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half +v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1018) + // (op 1018) Expression temporary in special register + // Unlock None +buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// VMEM: Expected stall of 4. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 2587 (current 2512) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1018): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1018): v54, v55 + + // Freeing : 1 SGPR (Value: UInt32) (op 1018): s45 + + // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) END + // (op 643) Deallocate{}(1893) BEGIN + // (op 1893) Deallocate 622 + // Deleting tag 622 + // (op 643) Deallocate{}(1893) END + // (op 643) end: generate({1018}) + // (op 39) SetCoordinate(643) END + // (op 39) Deallocate{}(1865) BEGIN + // (op 1865) Deallocate 508 + // Freeing Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 + + // Deleting tag 508 + // (op 1865) Deallocate 510 + // Deleting tag 510 + // (op 39) Deallocate{}(1865) END + // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) BEGIN + // (op 1157) Assign dim(506) = Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 + // (op 1157) Generate Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 into DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19] + // (op 1157) reg expression + // (op 1157) Add({DataFlowTag506: v[18:19]:U64}, 512:U64)U64 + // (op 1157) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1157) lhs (DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1157) rhs (Literal Value: UInt64 x 0: 512) + // (op 39) Barrier(1755) BEGIN +s_barrier // (op 1755) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 39) Barrier(1755) END +v_add_co_u32 v18, vcc, 512, v18 // (op 1157) least significant half + // Lock VCC +// Start of Int64 add, locking VCC + // (op 39) SetCoordinate(638) BEGIN + // (op 638) generate({}) + // (op 638) end: generate({}) + // (op 638) generate({1013}) + // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) BEGIN + // (op 1013) GEN: LoadTileDirect2LDS + // (op 1013) GEN: loadMacroTileDirect2LDS OP 1013 LDS 436 MacroTile 434 + // (op 1013) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1013) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 1013) Get arg Tensor_0_stride_0_9 + // (op 1013) reg expression + // (op 1013) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1013) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1013) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 3) +v_addc_co_u32 v19, vcc, 0, v19, vcc // (op 1157) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. + // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 1013) + // (op 1013) convert + // (op 1013) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1013) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1013) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1013): v48, v49 +v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 1013) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 + + // (op 1013) Generate 2:U64 into nullptr + // (op 1013) Generate 1024:U32 into nullptr + // (op 1013) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 57344 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[48:49] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1013): v50, v51 +v_mov_b64 v[50:51], v[68:69] // (op 1013) + // (op 1013) Generate Add(57344:U32, {DataFlowTag608: s42:U32})U32 into nullptr + // (op 1013) reg expression + // (op 1013) Add(57344:U32, {DataFlowTag608: s42:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1013): s45 +s_add_u32 s45, 57344, s42 // (op 1013) + // (op 1013) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1013) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 1013) reg expression + // (op 1013) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 896 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 +s_mov_b32 s46, 896 // (op 1013) call() +// 896 is not a supported value! +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 46. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2643 (current 2568) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2650 (current 2575) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2655 (current 2580) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 4. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2663 (current 2588) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2719 (current 2644) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2726 (current 2651) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2731 (current 2656) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] + // (op 1013) reg expression + // (op 1013) reg expression + // (op 1013) Add(v[50:51]:U64, v48:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half +v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 1013) + // (op 1013) Expression temporary in special register + // Unlock None +buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// VMEM: Expected stall of 4. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2739 (current 2664) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1013): v48, v49 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1013): v50, v51 + + // Freeing : 1 SGPR (Value: UInt32) (op 1013): s45 + + // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) END + // (op 638) Deallocate{}(1891) BEGIN + // (op 1891) Deallocate 610 + // Deleting tag 610 + // (op 638) Deallocate{}(1891) END + // (op 638) end: generate({1013}) + // (op 39) SetCoordinate(638) END + // (op 39) Deallocate{}(1863) BEGIN + // (op 1863) Deallocate 491 + // Deleting tag 491 + // (op 1863) Deallocate 489 + // Freeing Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 + + // Deleting tag 489 + // (op 39) Deallocate{}(1863) END + // (op 39) NOP(978) BEGIN + // (op 978) generate({}) + // (op 978) end: generate({}) + // (op 39) NOP(978) END + // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) BEGIN + // (op 1093) Assign dim(487) = Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 + // (op 1093) Generate Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: v[14:15] + // (op 1093) reg expression + // (op 1093) Add({DataFlowTag487: v[14:15]:U64}, 512:U64)U64 + // (op 1093) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1093) lhs (DataFlowTag487: VGPR Value: UInt64 x 1: v[14:15]) + // (op 1093) rhs (Literal Value: UInt64 x 0: 512) + // (op 39) NOP(973) BEGIN + // (op 973) generate({}) + // (op 973) end: generate({}) + // (op 39) NOP(973) END +v_add_co_u32 v14, vcc, 512, v14 // (op 1093) least significant half + // Lock VCC +// Start of Int64 add, locking VCC + // (op 39) NOP(802) BEGIN + // (op 802) generate({}) + // (op 802) end: generate({}) + // (op 39) NOP(802) END +v_addc_co_u32 v15, vcc, 0, v15, vcc // (op 1093) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. + // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) END + // (op 39) end: generate({41, 57, 811, 1733}) + // (op 39) For Loop Increment + // (op 39) generate({}) + // (op 39) end: generate({}) + // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 if true) + // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc + // (op 39) Get arg Tensor_0_size_1_10 + // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL + // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 + // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 +s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) +// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 +s_mov_b32 s45, s46 // (op 39) convert + // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 + +// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 +s_and_b32 s46, s45, 4294967292 // (op 39) + // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 + +s_cmp_lt_u32 s44, s46 // (op 39) + // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 39) +s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 if true) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39: + // (op 39) +s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch + // (op 39) + // (op 39) Unlock For Loop + // Unlock None + // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) END + // (op 1074) Deallocate{}(1765) BEGIN + // (op 1765) Deallocate 623 + // Deleting tag 623 + // (op 1765) Deallocate 621 + // Deleting tag 621 + // (op 1765) Deallocate 620 + // Freeing DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 + + // Deleting tag 620 + // (op 1765) Deallocate 609 + // Deleting tag 609 + // (op 1765) Deallocate 6 + // Deleting tag 6 + // (op 1765) Deallocate 611 + // Deleting tag 611 + // (op 1765) Deallocate 354 + // Deleting tag 354 + // (op 1765) Deallocate 537 + // Deleting tag 537 + // (op 1765) Deallocate 265 + // Freeing : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 + + // Deleting tag 265 + // (op 1765) Deallocate 535 + // Deleting tag 535 + // (op 1765) Deallocate 534 + // Freeing DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s1 + + // Deleting tag 534 + // (op 1765) Deallocate 277 + // Freeing : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 + + // Deleting tag 277 + // (op 1765) Deallocate 261 + // Freeing : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 + + // Deleting tag 261 + // (op 1765) Deallocate 518 + // Freeing DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s0 + + // Deleting tag 518 + // (op 1765) Deallocate 438 + // Deleting tag 438 + // (op 1765) Deallocate 358 + // Deleting tag 358 + // (op 1765) Deallocate 271 + // Freeing : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 + + // Deleting tag 271 + // (op 1765) Deallocate 7 + // Deleting tag 7 + // (op 1765) Deallocate 521 + // Deleting tag 521 + // (op 1765) Deallocate 394 + // Deleting tag 394 + // (op 1765) Deallocate 572 + // Freeing DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s17 + + // Deleting tag 572 + // (op 1765) Deallocate 360 + // Deleting tag 360 + // (op 1765) Deallocate 490 + // Deleting tag 490 + // (op 1765) Deallocate 587 + // Deleting tag 587 + // (op 1765) Deallocate 511 + // Deleting tag 511 + // (op 1765) Deallocate 257 + // Freeing : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 + + // Deleting tag 257 + // (op 1765) Deallocate 279 + // Freeing : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 + + // Deleting tag 279 + // (op 1765) Deallocate 263 + // Freeing : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 + + // Deleting tag 263 + // (op 1765) Deallocate 253 + // Freeing : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 + + // Deleting tag 253 + // (op 1765) Deallocate 507 + // Deleting tag 507 + // (op 1765) Deallocate 273 + // Freeing : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 + + // Deleting tag 273 + // (op 1765) Deallocate 400 + // Deleting tag 400 + // (op 1765) Deallocate 267 + // Freeing : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 + + // Deleting tag 267 + // (op 1765) Deallocate 259 + // Freeing : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 + + // Deleting tag 259 + // (op 1765) Deallocate 255 + // Freeing : 2 VGPRs (Value: Halfx2) (op 761): v16, v17 + + // Deleting tag 255 + // (op 1765) Deallocate 519 + // Deleting tag 519 + // (op 1765) Deallocate 11 + // Freeing : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 + + // Deleting tag 11 + // (op 1765) Deallocate 398 + // Deleting tag 398 + // (op 1765) Deallocate 436 + // Deleting tag 436 + // (op 1765) Deallocate 434 + // Deleting tag 434 + // (op 1765) Deallocate 269 + // Freeing : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 + + // Deleting tag 269 + // (op 1765) Deallocate 396 + // Deleting tag 396 + // (op 1765) Deallocate 440 + // Deleting tag 440 + // (op 1765) Deallocate 487 + // Freeing DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v14, v15 + + // Deleting tag 487 + // (op 1765) Deallocate 488 + // Deleting tag 488 + // (op 1765) Deallocate 275 + // Freeing : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 + + // Deleting tag 275 + // (op 1765) Deallocate 356 + // Deleting tag 356 + // (op 1765) Deallocate 509 + // Deleting tag 509 + // (op 1765) Deallocate 492 + // Deleting tag 492 + // (op 1765) Deallocate 19 + // Freeing : 2 VGPRs (Value: Halfx2) (op 758): v12, v13 + + // Deleting tag 19 + // (op 1765) Deallocate 560 + // Freeing DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s16 + + // Deleting tag 560 + // (op 1765) Deallocate 245 + // Freeing DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 + + // Deleting tag 245 + // (op 1765) Deallocate 506 + // Freeing DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 + + // Deleting tag 506 + // (op 1765) Deallocate 561 + // Deleting tag 561 + // (op 1765) Deallocate 563 + // Deleting tag 563 + // (op 1765) Deallocate 573 + // Deleting tag 573 + // (op 1765) Deallocate 575 + // Deleting tag 575 + // (op 1765) Deallocate 584 + // Freeing DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 + + // Deleting tag 584 + // (op 1765) Deallocate 585 + // Deleting tag 585 + // (op 1765) Deallocate 596 + // Freeing DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 + + // Deleting tag 596 + // (op 1765) Deallocate 597 + // Deleting tag 597 + // (op 1765) Deallocate 599 + // Deleting tag 599 + // (op 1765) Deallocate 608 + // Freeing DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 + + // Deleting tag 608 + // (op 1074) Deallocate{}(1765) END + // (op 1074) Barrier(1767) BEGIN +s_barrier // (op 1767) + // (op 1074) Barrier(1767) END + // (op 1074) end: generate({1069}) + // (op 1074) Unlock Scope 1074 + // Unlock None + // (op 670) Scope(1074) END + // (op 670) SetCoordinate(313) BEGIN + // (op 313) generate({}) + // (op 313) end: generate({}) + // (op 313) generate({314}) + // (op 313) SetCoordinate(314) BEGIN + // (op 314) generate({}) + // (op 314) end: generate({}) + // (op 314) generate({1051}) + // (op 314) Scope(1051) BEGIN + // (op 1051) Lock Scope 1051 + // Lock Branch + // (op 1051) generate({1045}) + // (op 1051) NOP(1045) BEGIN + // (op 1045) generate({}) + // (op 1045) end: generate({}) + // (op 1051) NOP(1045) END + // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) BEGIN + // (op 1056) Assign dim(474) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 + // tag 474: v**UNALLOCATED** + // (op 1056) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: (unallocated) + // (op 1056) Get arg Tensor_0_stride_0_9 + // (op 1056) Get arg Tensor_0_size_1_10 + // (op 1056) reg expression + // (op 1056) reg expression + // (op 1056) reg expression + // (op 1056) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 + // (op 1056) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 +v_lshrrev_b32 v12, 5, v1 // (op 1056) +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 +s_ashr_i64 s[0:1], s[20:21], 6 // (op 1056) + // (op 1056) BEGIN: Tile + // (op 1056) convert +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v13 +v_lshl_add_u32 v13, s2, 6, v12 // (op 1056) + // (op 1056) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1056): v12 + + // (op 1056) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 + // (op 1056) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 +v_and_b32 v12, -32, v1 // (op 1056) +// Allocated : 1 SGPR (Value: UInt32) (op 1056): s16 +s_lshr_b32 s16, s0, 2 // (op 1056) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 + + // (op 1056) BEGIN: Flatten[1] + // (op 1056) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} + // (op 1056) reg expression +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 +v_sub_u32 v14, v1, v12 // (op 1056) + // (op 1056) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1056): v12 + + // (op 1056) BEGIN: Tile + // (op 1056) {Tile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} + // (op 1056) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1056) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) + // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 +v_lshlrev_b32 v12, 1, v14 // (op 1056) + // (op 1056) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1056): v14 + + // (op 1056) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 +v_lshl_add_u32 v14, s16, 8, v12 // (op 1056) + // (op 1056) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v12 + + // Freeing : 1 SGPR (Value: UInt32) (op 1056): s16 + +// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 +v_mov_b32 v17, 0 // (op 1056) convert +v_mov_b32 v16, v14 // (op 1056) convert + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v14 + + // (op 1056) BEGIN: Split + // (op 1056) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1056) lhs (Tile: VGPR Value: UInt32 x 1: v13) + // (op 1056) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1056): v14, v15 +v_mul_lo_u32 v15, v13, s19 // (op 1056) most significant: low of low * high + // (op 1056) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1056): v12 +v_mul_hi_u32 v12, v13, s18 // (op 1056) most significant: high of low * low +v_mul_lo_u32 v14, v13, s18 // (op 1056) least significant: low of low * low +v_add_u32 v15, v15, v12 // (op 1056) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1056): v12 + + // (op 1056) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1056) lhs (VGPR Value: UInt64 x 1: v[14:15]) + // (op 1056) rhs (Tile: VGPR Value: UInt64 x 1: v[16:17]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 +v_add_co_u32 v14, s[0:1], v14, v16 // (op 1056) least significant half +v_addc_co_u32 v15, s[0:1], v15, v17, s[0:1] // (op 1056) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 + + // (op 1056) END: Split + // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v13 + + // (op 1056) ShiftL({Split: v[14:15]:U64}, 1:U32)U64 + // (op 1056) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1056) value (Split: VGPR Value: UInt64 x 1: v[14:15]) + // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 +v_lshlrev_b64 v[12:13], 1, v[14:15] // (op 1056) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1056): v14, v15 + + // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) END + // (op 1051) Assign VGPR 128:U64(1057) BEGIN + // (op 1057) Assign dim(475) = 128:U64 + // (op 1057) Assign stride expression + // (op 1051) Assign VGPR 128:U64(1057) END + // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) BEGIN + // (op 1058) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1058) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // (op 1058) Get arg Tensor_0_pointer + // (op 1058) Get arg Tensor_0_extent_0 + // (op 1058) reg expression + // (op 1058) reg expression + // (op 1058) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1058) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1058) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1058) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1058): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1058) + // (op 1058) reg expression +s_mov_b32 s32, s6 // (op 1058) reg expression +s_mov_b32 s33, s7 // (op 1058) reg expression +s_mov_b32 s34, s0 // (op 1058) reg expression +s_mov_b32 s35, 131072 // (op 1058) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1058): s0, s1 + + // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) END + // (op 1051) NOP(1047) BEGIN + // (op 1047) generate({}) + // (op 1047) end: generate({}) + // (op 1051) NOP(1047) END + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) BEGIN + // (op 1063) Assign dim(479) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1063) Assign stride expression + // (op 1051) Tag 1063non referenced extraArgs = {Tensor_0_stride_0_9} + + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) END + // (op 1051) NOP(1048) BEGIN + // (op 1048) generate({}) + // (op 1048) end: generate({}) + // (op 1051) NOP(1048) END + // (op 1051) Assign VGPR 2:U64(1066) BEGIN + // (op 1066) Assign dim(481) = 2:U64 + // (op 1066) Assign stride expression + // (op 1051) Assign VGPR 2:U64(1066) END + // (op 1051) NOP(1114) BEGIN + // (op 1114) generate({}) + // (op 1114) end: generate({}) + // (op 1051) NOP(1114) END + // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) BEGIN + // (op 1123) Assign dim(493) = {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 493: v**UNALLOCATED** + // (op 1123) Generate {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag493: VGPR Value: UInt64 x 1: (unallocated) + // (op 1123) Get arg Tensor_0_size_1_10 + // (op 1123) Get arg Tensor_2_stride_1_12 + // (op 1123) reg expression + // (op 1123) reg expression + // (op 1123) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 + // (op 1123) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_and_b32 v14, -32, v1 // (op 1123) +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 +s_ashr_i64 s[0:1], s[20:21], 6 // (op 1123) + // (op 1123) BEGIN: Flatten[1] + // (op 1123) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v14:U32)U32} + // (op 1123) convert +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 +v_sub_u32 v15, v1, v14 // (op 1123) + // (op 1123) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1123): v14 + + // (op 1123) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 + // (op 1123) BEGIN: Tile + // (op 1123) {Tile: ShiftL({Flatten[1]: v15:U32}, 1:U32)U32} + // (op 1123) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1123) value (Flatten[1]: VGPR Value: UInt32 x 1: v15) + // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_lshlrev_b32 v14, 1, v15 // (op 1123) + // (op 1123) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1123): v15 + +// Allocated : 1 SGPR (Value: UInt32) (op 1123): s16 +s_lshr_b32 s16, s0, 2 // (op 1123) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 + + // (op 1123) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 + // (op 1123) reg expression +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 +v_lshrrev_b32 v15, 5, v1 // (op 1123) + // (op 1123) reg expression + // (op 1123) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v16 +v_lshl_add_u32 v16, s16, 8, v14 // (op 1123) + // (op 1123) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 + + // Freeing : 1 SGPR (Value: UInt32) (op 1123): s16 + +// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 +v_mov_b32 v19, 0 // (op 1123) convert +v_mov_b32 v18, v16 // (op 1123) convert + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v16 + + // (op 1123) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_lshl_add_u32 v14, s3, 6, v15 // (op 1123) + // (op 1123) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1123): v15 + + // (op 1123) Multiply({Tile: v14:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1123) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1123) lhs (Tile: VGPR Value: UInt32 x 1: v14) + // (op 1123) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 2 VGPRs (Value: Int64) (op 1123): v16, v17 +v_mul_lo_u32 v17, v14, s23 // (op 1123) most significant: low of low * high + // (op 1123) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1123): v15 +v_mul_hi_u32 v15, v14, s22 // (op 1123) most significant: high of low * low +v_mul_lo_u32 v16, v14, s22 // (op 1123) least significant: low of low * low +v_add_u32 v17, v17, v15 // (op 1123) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1123): v15 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 + + // (op 1123) BEGIN: Split + // (op 1123) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1123) lhs (Tile: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1123) rhs (VGPR Value: Int64 x 1: v[16:17]) +// Allocated DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 +// Allocated : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 +v_add_co_u32 v14, s[0:1], v18, v16 // (op 1123) least significant half +v_addc_co_u32 v15, s[0:1], v19, v17, s[0:1] // (op 1123) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 + + // (op 1123) ShiftL: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1123) value (VGPR Value: UInt64 x 1: v[14:15]) + // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[14:15], 1, v[14:15] // (op 1123) + // (op 1123) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1123): v16, v17 + + // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 + + // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) END + // (op 1051) Assign VGPR 128:U64(1124) BEGIN + // (op 1124) Assign dim(494) = 128:U64 + // (op 1124) Assign stride expression + // (op 1051) Assign VGPR 128:U64(1124) END + // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) BEGIN + // (op 1125) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1125) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // (op 1125) Get arg Tensor_2_pointer + // (op 1125) Get arg Tensor_2_extent_2 + // (op 1125) reg expression + // (op 1125) reg expression + // (op 1125) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1125) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1125) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1125) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1125): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1125) + // (op 1125) reg expression +s_mov_b32 s36, s10 // (op 1125) reg expression +s_mov_b32 s37, s11 // (op 1125) reg expression +s_mov_b32 s38, s0 // (op 1125) reg expression +s_mov_b32 s39, 131072 // (op 1125) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1125): s0, s1 + + // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) END + // (op 1051) NOP(1116) BEGIN + // (op 1116) generate({}) + // (op 1116) end: generate({}) + // (op 1051) NOP(1116) END + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) BEGIN + // (op 1130) Assign dim(498) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1130) Assign stride expression + // (op 1051) Tag 1130non referenced extraArgs = {Tensor_2_stride_1_12} + + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) END + // (op 1051) NOP(1117) BEGIN + // (op 1117) generate({}) + // (op 1117) end: generate({}) + // (op 1051) NOP(1117) END + // (op 1051) Assign VGPR 2:U64(1133) BEGIN + // (op 1133) Assign dim(500) = 2:U64 + // (op 1133) Assign stride expression + // (op 1051) Assign VGPR 2:U64(1133) END + // (op 1051) NOP(1211) BEGIN + // (op 1211) generate({}) + // (op 1211) end: generate({}) + // (op 1051) NOP(1211) END + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) BEGIN + // (op 1216) Assign dim(522) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 522: s**UNALLOCATED** + // (op 1216) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag522: SGPR Value: UInt32 x 1: (unallocated) + // (op 1216) reg expression + // (op 1216) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 +v_and_b32 v16, -32, v1 // (op 1216) + // (op 1216) BEGIN: Tile[1] + // (op 1216) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 +v_sub_u32 v17, v1, v16 // (op 1216) + // (op 1216) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v16 + + // (op 1216) BEGIN: Flatten + // (op 1216) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} + // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1216) value (Tile[1]: VGPR Value: UInt32 x 1: v17) + // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 +v_lshlrev_b32 v16, 1, v17 // (op 1216) + // (op 1216) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1216): v17 + + // (op 1216) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1216) + // (op 1216) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v18 +v_lshl_add_u32 v18, v17, 6, v16 // (op 1216) + // (op 1216) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v16 + + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v17 + + // (op 1216) ShiftL({Flatten: v18:U32}, 1:U32)U32 + // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1216) value (Flatten: VGPR Value: UInt32 x 1: v18) + // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 +v_lshlrev_b32 v16, 1, v18 // (op 1216) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v18 + +// Allocated DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s0 +s_nop 0 +v_readfirstlane_b32 s0, v16 // (op 1216) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v16 + + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) END + // (op 1051) Assign VGPR 1024:U32(1217) BEGIN + // (op 1217) Assign dim(523) = 1024:U32 + // (op 1217) Assign stride expression + // (op 1051) Assign VGPR 1024:U32(1217) END + // (op 1051) NOP(1212) BEGIN + // (op 1212) generate({}) + // (op 1212) end: generate({}) + // (op 1051) NOP(1212) END + // (op 1051) Assign VGPR 2:U32(1221) BEGIN + // (op 1221) Assign dim(525) = 2:U32 + // (op 1221) Assign stride expression + // (op 1051) Assign VGPR 2:U32(1221) END + // (op 1051) NOP(1263) BEGIN + // (op 1263) generate({}) + // (op 1263) end: generate({}) + // (op 1051) NOP(1263) END + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) BEGIN + // (op 1268) Assign dim(538) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 538: s**UNALLOCATED** + // (op 1268) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag538: SGPR Value: UInt32 x 1: (unallocated) + // (op 1268) reg expression + // (op 1268) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 +v_and_b32 v16, -32, v1 // (op 1268) + // (op 1268) BEGIN: Tile[1] + // (op 1268) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 +v_sub_u32 v17, v1, v16 // (op 1268) + // (op 1268) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v16 + + // (op 1268) BEGIN: Flatten + // (op 1268) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} + // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1268) value (Tile[1]: VGPR Value: UInt32 x 1: v17) + // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 +v_lshlrev_b32 v16, 1, v17 // (op 1268) + // (op 1268) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1268): v17 + + // (op 1268) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1268) + // (op 1268) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v18 +v_lshl_add_u32 v18, v17, 6, v16 // (op 1268) + // (op 1268) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v16 + + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v17 + + // (op 1268) ShiftL({Flatten: v18:U32}, 1:U32)U32 + // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1268) value (Flatten: VGPR Value: UInt32 x 1: v18) + // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 +v_lshlrev_b32 v16, 1, v18 // (op 1268) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v18 + +// Allocated DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s1 +s_nop 0 +v_readfirstlane_b32 s1, v16 // (op 1268) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v16 + + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) END + // (op 1051) Assign VGPR 1024:U32(1269) BEGIN + // (op 1269) Assign dim(539) = 1024:U32 + // (op 1269) Assign stride expression + // (op 1051) Assign VGPR 1024:U32(1269) END + // (op 1051) NOP(1264) BEGIN + // (op 1264) generate({}) + // (op 1264) end: generate({}) + // (op 1051) NOP(1264) END + // (op 1051) Assign VGPR 2:U32(1273) BEGIN + // (op 1273) Assign dim(541) = 2:U32 + // (op 1273) Assign stride expression + // (op 1051) Assign VGPR 2:U32(1273) END + // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) BEGIN + // (op 217) Initialize For Loop + // (op 217) generate({218}) + // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) BEGIN + // (op 218) Assign dim(316) = BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 + // tag 316: s**UNALLOCATED** + // (op 218) Generate BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: (unallocated) + // (op 218) Get arg Tensor_0_size_1_10 + // (op 218) reg expression + // (op 218) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 218) + // (op 218) convert + // (op 218) BitwiseAnd({ convertForwardSubset: s16:U32}, 4294967292:U32)U32 +// Allocated DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 +s_and_b32 s40, s16, 4294967292 // (op 218) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 + + // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) END + // (op 217) end: generate({218}) + // (op 217) Lock For Loop + // Lock Branch + // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc + // (op 217) Get arg Tensor_0_size_1_10 + // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL + // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) +// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 +s_mov_b32 s41, s16 // (op 217) convert + // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 + +s_cmp_lt_u32 s40, s41 // (op 217) + // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 217) +s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217 // (op 217) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217 if false) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217: + // (op 217) + // (op 217) generate({219, 1726}) + // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) BEGIN + // (op 219) Assign dim(316) = Add(DataFlowTag(316)U32, 1:U32)U32 + // (op 219) Generate Add(DataFlowTag(316)U32, 1:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: s40 + // (op 219) reg expression + // (op 219) Add({DataFlowTag316: s40:U32}, 1:U32)U32 + // (op 217) Barrier(1726) BEGIN +s_barrier // (op 1726) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 217) Barrier(1726) END +s_add_u32 s40, s40, 1 // (op 219) + // (op 217) Tag 219non referenced extraArgs = {Tensor_0_size_1_10} + + // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) END + // (op 217) SetCoordinate(318) BEGIN + // (op 318) generate({}) + // (op 318) end: generate({}) + // (op 318) generate({981}) + // (op 318) LoadTileDirect2LDS Value: Halfx2(981) BEGIN + // (op 981) GEN: LoadTileDirect2LDS + // (op 981) GEN: loadMacroTileDirect2LDS OP 981 LDS 13 MacroTile 318 + // (op 981) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 981) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride479: VGPR Value: UInt64 x 1: (unallocated) + // (op 981) Get arg Tensor_0_stride_0_9 + // (op 981) reg expression + // (op 981) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 981) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 981) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 981) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 981) + // (op 981) convert + // (op 981) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 981) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 981) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 981) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 981) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 + + // (op 981) Generate 2:U64 into nullptr + // (op 981) Generate 1024:U32 into nullptr + // (op 981) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride479: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 478: v**UNALLOCATED** +// Allocated Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 +v_mov_b64 v[18:19], v[12:13] // (op 981) +// Allocated : 2 VGPRs (Value: UInt64) (op 981): v20, v21 +v_mov_b64 v[20:21], v[18:19] // (op 981) + // (op 981) Generate Add(8192:U32, {DataFlowTag522: s0:U32})U32 into nullptr + // (op 981) reg expression + // (op 981) Add(8192:U32, {DataFlowTag522: s0:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 981): s16 +s_add_u32 s16, 8192, s0 // (op 981) + // (op 981) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride479: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 981) Generate s16:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s16 // (op 981) reg expression +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2892 (current 2817) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2896 (current 2821) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2900 (current 2825) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2904 (current 2829) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 2968 (current 2893) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2972 (current 2897) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2976 (current 2901) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) reg expression + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 981) + // (op 981) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2980 (current 2905) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 981): v20, v21 + + // Freeing : 1 SGPR (Value: UInt32) (op 981): s16 + + // (op 318) LoadTileDirect2LDS Value: Halfx2(981) END + // (op 318) Deallocate{}(1879) BEGIN + // (op 1879) Deallocate 318 + // Deleting tag 318 + // (op 1879) Deallocate 524 + // Deleting tag 524 + // (op 1879) Deallocate 478 + // Freeing Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 + + // Deleting tag 478 + // (op 1879) Deallocate 480 + // Deleting tag 480 + // (op 318) Deallocate{}(1879) END + // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) BEGIN + // (op 1046) Assign dim(474) = Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 + // (op 1046) Generate Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13] + // (op 1046) reg expression + // (op 1046) Add({DataFlowTag474: v[12:13]:U64}, 128:U64)U64 + // (op 1046) Add: dest (VGPR Value: UInt64 x 1: v[12:13]) = + // (op 1046) lhs (DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13]) + // (op 1046) rhs (Literal Value: UInt64 x 0: 128) +v_add_co_u32 v12, vcc, 128, v12 // (op 1046) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +v_addc_co_u32 v13, vcc, 0, v13, vcc // (op 1046) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. + // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) END + // (op 318) end: generate({981}) + // (op 217) SetCoordinate(318) END + // (op 217) NOP(983) BEGIN + // (op 983) generate({}) + // (op 983) end: generate({}) + // (op 217) NOP(983) END + // (op 217) Barrier(1736) BEGIN +s_barrier // (op 1736) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 217) Barrier(1736) END + // (op 217) SetCoordinate(323) BEGIN + // (op 323) generate({}) + // (op 323) end: generate({}) + // (op 323) generate({987}) + // (op 323) LoadTileDirect2LDS Value: Halfx2(987) BEGIN + // (op 987) GEN: LoadTileDirect2LDS + // (op 987) GEN: loadMacroTileDirect2LDS OP 987 LDS 21 MacroTile 320 + // (op 987) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 987) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride498: VGPR Value: UInt64 x 1: (unallocated) + // (op 987) Get arg Tensor_2_stride_1_12 + // (op 987) reg expression + // (op 987) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 987) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 987) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 987) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 987) + // (op 987) convert + // (op 987) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 987) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 987) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 987) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 987) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 + + // (op 987) Generate 2:U64 into nullptr + // (op 987) Generate 1024:U32 into nullptr + // (op 987) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride498: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 497: v**UNALLOCATED** +// Allocated Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 +v_mov_b64 v[18:19], v[14:15] // (op 987) +// Allocated : 2 VGPRs (Value: UInt64) (op 987): v20, v21 +v_mov_b64 v[20:21], v[18:19] // (op 987) + // (op 987) Generate Add(0:U32, {DataFlowTag538: s1:U32})U32 into nullptr + // (op 987) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride498: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 987) Generate {DataFlowTag538: s1:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 987) reg expression +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected stall of 55. CBNW: 4, Inc: 4 +// VMEM: Expected complete at 3044 (current 2969) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3048 (current 2973) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3052 (current 2977) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3056 (current 2981) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 +// VMEM: Expected complete at 3120 (current 3045) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3124 (current 3049) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3128 (current 3053) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) reg expression + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +s_add_u32 m0, m0, 1024 // (op 987) + // (op 987) Expression temporary in special register + // Unlock None +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// VMEM: Expected complete at 3132 (current 3057) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 987): v20, v21 + + // (op 323) LoadTileDirect2LDS Value: Halfx2(987) END + // (op 323) Deallocate{}(1881) BEGIN + // (op 1881) Deallocate 320 + // Deleting tag 320 + // (op 1881) Deallocate 497 + // Freeing Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 + + // Deleting tag 497 + // (op 1881) Deallocate 540 + // Deleting tag 540 + // (op 1881) Deallocate 499 + // Deleting tag 499 + // (op 323) Deallocate{}(1881) END + // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) BEGIN + // (op 1115) Assign dim(493) = Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 + // (op 1115) Generate Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 into DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15] + // (op 1115) reg expression + // (op 1115) Add({DataFlowTag493: v[14:15]:U64}, 128:U64)U64 + // (op 1115) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1115) lhs (DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15]) + // (op 1115) rhs (Literal Value: UInt64 x 0: 128) +v_add_co_u32 v14, vcc, 128, v14 // (op 1115) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +v_addc_co_u32 v15, vcc, 0, v15, vcc // (op 1115) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. + // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) END + // (op 323) end: generate({987}) + // (op 217) SetCoordinate(323) END + // (op 217) NOP(989) BEGIN + // (op 989) generate({}) + // (op 989) end: generate({}) + // (op 217) NOP(989) END + // (op 217) Barrier(1729) BEGIN +s_waitcnt vmcnt(8) +s_barrier // (op 1729) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 217) Barrier(1729) END + // (op 217) SetCoordinate(224) BEGIN + // (op 224) generate({}) + // (op 224) end: generate({}) + // (op 224) generate({225}) + // (op 224) LoadLDSTile{Value: Halfx2}(225) BEGIN + // (op 225) GEN: loadMacroTileWAVELDS OP 225 LDS 13 WaveTile 85 + // (op 225) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 225) Generate 2:U32 into nullptr + // tag 322: v**UNALLOCATED** + // (op 225) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 225) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 225) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 +ds_read_b64 v[16:17], v0 offset:8192 // (op 225) Load local data +// DSMEM: Expected complete at 3015 (current 2995) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 224) LoadLDSTile{Value: Halfx2}(225) END + // (op 224) end: generate({225}) + // (op 217) SetCoordinate(224) END + // (op 217) Barrier(1739) BEGIN +s_waitcnt vmcnt(0) +s_barrier // (op 1739) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 217) Barrier(1739) END + // (op 217) SetCoordinate(226) BEGIN + // (op 226) generate({}) + // (op 226) end: generate({}) + // (op 226) generate({227}) + // (op 226) LoadLDSTile{Value: Halfx2}(227) BEGIN + // (op 227) GEN: loadMacroTileWAVELDS OP 227 LDS 21 WaveTile 145 + // (op 227) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 227) Generate 2:U32 into nullptr + // tag 324: v**UNALLOCATED** + // (op 227) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 227) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 227) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 +ds_read_b64 v[18:19], v3 // (op 227) Load local data +// DSMEM: Expected complete at 3018 (current 2998) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 226) LoadLDSTile{Value: Halfx2}(227) END + // (op 226) end: generate({227}) + // (op 217) SetCoordinate(226) END + // (op 217) Multiply(228) BEGIN + // (op 228) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 228) + // (op 217) Multiply(228) END + // (op 217) Deallocate{}(1783) BEGIN + // (op 1783) Deallocate 322 + // Freeing : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 + + // Deleting tag 322 + // (op 1783) Deallocate 324 + // Freeing : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 + + // Deleting tag 324 + // (op 217) Deallocate{}(1783) END + // (op 217) SetCoordinate(229) BEGIN + // (op 229) generate({}) + // (op 229) end: generate({}) + // (op 229) generate({230}) + // (op 229) LoadLDSTile{Value: Halfx2}(230) BEGIN + // (op 230) GEN: loadMacroTileWAVELDS OP 230 LDS 13 WaveTile 85 + // (op 230) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 230) Generate 2:U32 into nullptr + // tag 326: v**UNALLOCATED** + // (op 230) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 230) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 230) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 +ds_read_b64 v[16:17], v0 offset:8208 // (op 230) Load local data +// DSMEM: Expected complete at 3041 (current 3021) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 229) LoadLDSTile{Value: Halfx2}(230) END + // (op 229) end: generate({230}) + // (op 217) SetCoordinate(229) END + // (op 217) SetCoordinate(231) BEGIN + // (op 231) generate({}) + // (op 231) end: generate({}) + // (op 231) generate({232}) + // (op 231) LoadLDSTile{Value: Halfx2}(232) BEGIN + // (op 232) GEN: loadMacroTileWAVELDS OP 232 LDS 21 WaveTile 145 + // (op 232) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 232) Generate 2:U32 into nullptr + // tag 328: v**UNALLOCATED** + // (op 232) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 232) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 232) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 +ds_read_b64 v[18:19], v3 offset:16 // (op 232) Load local data +// DSMEM: Expected complete at 3042 (current 3022) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 231) LoadLDSTile{Value: Halfx2}(232) END + // (op 231) end: generate({232}) + // (op 217) SetCoordinate(231) END + // (op 217) Multiply(233) BEGIN + // (op 233) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 233) + // (op 217) Multiply(233) END + // (op 217) Deallocate{}(1785) BEGIN + // (op 1785) Deallocate 328 + // Freeing : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 + + // Deleting tag 328 + // (op 1785) Deallocate 326 + // Freeing : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 + + // Deleting tag 326 + // (op 217) Deallocate{}(1785) END + // (op 217) SetCoordinate(234) BEGIN + // (op 234) generate({}) + // (op 234) end: generate({}) + // (op 234) generate({235}) + // (op 234) LoadLDSTile{Value: Halfx2}(235) BEGIN + // (op 235) GEN: loadMacroTileWAVELDS OP 235 LDS 13 WaveTile 85 + // (op 235) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 235) Generate 2:U32 into nullptr + // tag 330: v**UNALLOCATED** + // (op 235) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 235) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 235) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 +ds_read_b64 v[16:17], v0 offset:8224 // (op 235) Load local data +// DSMEM: Expected complete at 3071 (current 3051) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 234) LoadLDSTile{Value: Halfx2}(235) END + // (op 234) end: generate({235}) + // (op 217) SetCoordinate(234) END + // (op 217) SetCoordinate(236) BEGIN + // (op 236) generate({}) + // (op 236) end: generate({}) + // (op 236) generate({237}) + // (op 236) LoadLDSTile{Value: Halfx2}(237) BEGIN + // (op 237) GEN: loadMacroTileWAVELDS OP 237 LDS 21 WaveTile 145 + // (op 237) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 237) Generate 2:U32 into nullptr + // tag 332: v**UNALLOCATED** + // (op 237) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 237) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 237) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 +ds_read_b64 v[18:19], v3 offset:32 // (op 237) Load local data +// DSMEM: Expected complete at 3072 (current 3052) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 236) LoadLDSTile{Value: Halfx2}(237) END + // (op 236) end: generate({237}) + // (op 217) SetCoordinate(236) END + // (op 217) Multiply(238) BEGIN + // (op 238) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 238) + // (op 217) Multiply(238) END + // (op 217) Deallocate{}(1787) BEGIN + // (op 1787) Deallocate 332 + // Freeing : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 + + // Deleting tag 332 + // (op 1787) Deallocate 330 + // Freeing : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 + + // Deleting tag 330 + // (op 217) Deallocate{}(1787) END + // (op 217) SetCoordinate(239) BEGIN + // (op 239) generate({}) + // (op 239) end: generate({}) + // (op 239) generate({240}) + // (op 239) LoadLDSTile{Value: Halfx2}(240) BEGIN + // (op 240) GEN: loadMacroTileWAVELDS OP 240 LDS 13 WaveTile 85 + // (op 240) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 240) Generate 2:U32 into nullptr + // tag 334: v**UNALLOCATED** + // (op 240) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 240) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 240) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 +ds_read_b64 v[16:17], v0 offset:8240 // (op 240) Load local data +// DSMEM: Expected complete at 3101 (current 3081) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 239) LoadLDSTile{Value: Halfx2}(240) END + // (op 239) end: generate({240}) + // (op 217) SetCoordinate(239) END + // (op 217) SetCoordinate(241) BEGIN + // (op 241) generate({}) + // (op 241) end: generate({}) + // (op 241) generate({242}) + // (op 241) LoadLDSTile{Value: Halfx2}(242) BEGIN + // (op 242) GEN: loadMacroTileWAVELDS OP 242 LDS 21 WaveTile 145 + // (op 242) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 242) Generate 2:U32 into nullptr + // tag 336: v**UNALLOCATED** + // (op 242) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 242) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 242) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 +ds_read_b64 v[18:19], v3 offset:48 // (op 242) Load local data +// DSMEM: Expected complete at 3102 (current 3082) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 241) LoadLDSTile{Value: Halfx2}(242) END + // (op 241) end: generate({242}) + // (op 217) SetCoordinate(241) END + // (op 217) Multiply(243) BEGIN + // (op 243) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 243) + // (op 217) Multiply(243) END + // (op 217) Deallocate{}(1789) BEGIN + // (op 1789) Deallocate 334 + // Freeing : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 + + // Deleting tag 334 + // (op 1789) Deallocate 336 + // Freeing : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 + + // Deleting tag 336 + // (op 217) Deallocate{}(1789) END + // (op 217) SetCoordinate(244) BEGIN + // (op 244) generate({}) + // (op 244) end: generate({}) + // (op 244) generate({245}) + // (op 244) LoadLDSTile{Value: Halfx2}(245) BEGIN + // (op 245) GEN: loadMacroTileWAVELDS OP 245 LDS 13 WaveTile 85 + // (op 245) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 245) Generate 2:U32 into nullptr + // tag 338: v**UNALLOCATED** + // (op 245) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 245) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 245) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 +ds_read_b64 v[16:17], v0 offset:8256 // (op 245) Load local data +// DSMEM: Expected complete at 3131 (current 3111) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 244) LoadLDSTile{Value: Halfx2}(245) END + // (op 244) end: generate({245}) + // (op 217) SetCoordinate(244) END + // (op 217) SetCoordinate(246) BEGIN + // (op 246) generate({}) + // (op 246) end: generate({}) + // (op 246) generate({247}) + // (op 246) LoadLDSTile{Value: Halfx2}(247) BEGIN + // (op 247) GEN: loadMacroTileWAVELDS OP 247 LDS 21 WaveTile 145 + // (op 247) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 247) Generate 2:U32 into nullptr + // tag 340: v**UNALLOCATED** + // (op 247) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 247) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 247) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 +ds_read_b64 v[18:19], v3 offset:64 // (op 247) Load local data +// DSMEM: Expected complete at 3132 (current 3112) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 246) LoadLDSTile{Value: Halfx2}(247) END + // (op 246) end: generate({247}) + // (op 217) SetCoordinate(246) END + // (op 217) Multiply(248) BEGIN + // (op 248) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 248) + // (op 217) Multiply(248) END + // (op 217) Deallocate{}(1791) BEGIN + // (op 1791) Deallocate 340 + // Freeing : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 + + // Deleting tag 340 + // (op 1791) Deallocate 338 + // Freeing : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 + + // Deleting tag 338 + // (op 217) Deallocate{}(1791) END + // (op 217) SetCoordinate(249) BEGIN + // (op 249) generate({}) + // (op 249) end: generate({}) + // (op 249) generate({250}) + // (op 249) LoadLDSTile{Value: Halfx2}(250) BEGIN + // (op 250) GEN: loadMacroTileWAVELDS OP 250 LDS 13 WaveTile 85 + // (op 250) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 250) Generate 2:U32 into nullptr + // tag 342: v**UNALLOCATED** + // (op 250) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 250) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 250) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 +ds_read_b64 v[16:17], v0 offset:8272 // (op 250) Load local data +// DSMEM: Expected complete at 3161 (current 3141) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 249) LoadLDSTile{Value: Halfx2}(250) END + // (op 249) end: generate({250}) + // (op 217) SetCoordinate(249) END + // (op 217) SetCoordinate(251) BEGIN + // (op 251) generate({}) + // (op 251) end: generate({}) + // (op 251) generate({252}) + // (op 251) LoadLDSTile{Value: Halfx2}(252) BEGIN + // (op 252) GEN: loadMacroTileWAVELDS OP 252 LDS 21 WaveTile 145 + // (op 252) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 252) Generate 2:U32 into nullptr + // tag 344: v**UNALLOCATED** + // (op 252) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 252) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 252) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 +ds_read_b64 v[18:19], v3 offset:80 // (op 252) Load local data +// DSMEM: Expected complete at 3162 (current 3142) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 251) LoadLDSTile{Value: Halfx2}(252) END + // (op 251) end: generate({252}) + // (op 217) SetCoordinate(251) END + // (op 217) Multiply(253) BEGIN + // (op 253) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 253) + // (op 217) Multiply(253) END + // (op 217) Deallocate{}(1793) BEGIN + // (op 1793) Deallocate 342 + // Freeing : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 + + // Deleting tag 342 + // (op 1793) Deallocate 344 + // Freeing : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 + + // Deleting tag 344 + // (op 217) Deallocate{}(1793) END + // (op 217) SetCoordinate(254) BEGIN + // (op 254) generate({}) + // (op 254) end: generate({}) + // (op 254) generate({255}) + // (op 254) LoadLDSTile{Value: Halfx2}(255) BEGIN + // (op 255) GEN: loadMacroTileWAVELDS OP 255 LDS 13 WaveTile 85 + // (op 255) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 255) Generate 2:U32 into nullptr + // tag 346: v**UNALLOCATED** + // (op 255) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 255) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 255) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 +ds_read_b64 v[16:17], v0 offset:8288 // (op 255) Load local data +// DSMEM: Expected complete at 3191 (current 3171) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 254) LoadLDSTile{Value: Halfx2}(255) END + // (op 254) end: generate({255}) + // (op 217) SetCoordinate(254) END + // (op 217) SetCoordinate(256) BEGIN + // (op 256) generate({}) + // (op 256) end: generate({}) + // (op 256) generate({257}) + // (op 256) LoadLDSTile{Value: Halfx2}(257) BEGIN + // (op 257) GEN: loadMacroTileWAVELDS OP 257 LDS 21 WaveTile 145 + // (op 257) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 257) Generate 2:U32 into nullptr + // tag 348: v**UNALLOCATED** + // (op 257) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 257) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 257) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 +ds_read_b64 v[18:19], v3 offset:96 // (op 257) Load local data +// DSMEM: Expected complete at 3192 (current 3172) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 256) LoadLDSTile{Value: Halfx2}(257) END + // (op 256) end: generate({257}) + // (op 217) SetCoordinate(256) END + // (op 217) Multiply(258) BEGIN + // (op 258) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 258) + // (op 217) Multiply(258) END + // (op 217) Deallocate{}(1795) BEGIN + // (op 1795) Deallocate 348 + // Freeing : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 + + // Deleting tag 348 + // (op 1795) Deallocate 346 + // Freeing : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 + + // Deleting tag 346 + // (op 217) Deallocate{}(1795) END + // (op 217) SetCoordinate(259) BEGIN + // (op 259) generate({}) + // (op 259) end: generate({}) + // (op 259) generate({260}) + // (op 259) LoadLDSTile{Value: Halfx2}(260) BEGIN + // (op 260) GEN: loadMacroTileWAVELDS OP 260 LDS 13 WaveTile 85 + // (op 260) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 260) Generate 2:U32 into nullptr + // tag 350: v**UNALLOCATED** + // (op 260) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 260) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 260) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 +ds_read_b64 v[16:17], v0 offset:8304 // (op 260) Load local data +// DSMEM: Expected complete at 3221 (current 3201) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 259) LoadLDSTile{Value: Halfx2}(260) END + // (op 259) end: generate({260}) + // (op 217) SetCoordinate(259) END + // (op 217) SetCoordinate(261) BEGIN + // (op 261) generate({}) + // (op 261) end: generate({}) + // (op 261) generate({262}) + // (op 261) LoadLDSTile{Value: Halfx2}(262) BEGIN + // (op 262) GEN: loadMacroTileWAVELDS OP 262 LDS 21 WaveTile 145 + // (op 262) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 262) Generate 2:U32 into nullptr + // tag 352: v**UNALLOCATED** + // (op 262) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 262) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 262) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 +ds_read_b64 v[18:19], v3 offset:112 // (op 262) Load local data +// DSMEM: Expected complete at 3222 (current 3202) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 261) LoadLDSTile{Value: Halfx2}(262) END + // (op 261) end: generate({262}) + // (op 217) SetCoordinate(261) END + // (op 217) Multiply(263) BEGIN + // (op 263) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 263) + // (op 217) Multiply(263) END + // (op 217) Deallocate{}(1797) BEGIN + // (op 1797) Deallocate 352 + // Freeing : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 + + // Deleting tag 352 + // (op 1797) Deallocate 350 + // Freeing : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 + + // Deleting tag 350 + // (op 217) Deallocate{}(1797) END + // (op 217) end: generate({219, 1726}) + // (op 217) For Loop Increment + // (op 217) generate({}) + // (op 217) end: generate({}) + // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 if true) + // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc + // (op 217) Get arg Tensor_0_size_1_10 + // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL + // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) +// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 +s_mov_b32 s41, s16 // (op 217) convert + // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 + +s_cmp_lt_u32 s40, s41 // (op 217) + // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 217) +s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 if true) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217: + // (op 217) +s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch + // (op 217) + // (op 217) Unlock For Loop + // Unlock None + // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) END + // (op 1051) Deallocate{}(1781) BEGIN + // (op 1781) Deallocate 316 + // Freeing DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 + + // Deleting tag 316 + // (op 1781) Deallocate 538 + // Freeing DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s1 + + // Deleting tag 538 + // (op 1781) Deallocate 541 + // Deleting tag 541 + // (op 1781) Deallocate 539 + // Deleting tag 539 + // (op 1781) Deallocate 523 + // Deleting tag 523 + // (op 1781) Deallocate 500 + // Deleting tag 500 + // (op 1781) Deallocate 498 + // Deleting tag 498 + // (op 1781) Deallocate 494 + // Deleting tag 494 + // (op 1781) Deallocate 493 + // Freeing DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 + + // Deleting tag 493 + // (op 1781) Deallocate 481 + // Deleting tag 481 + // (op 1781) Deallocate 479 + // Deleting tag 479 + // (op 1781) Deallocate 475 + // Deleting tag 475 + // (op 1781) Deallocate 474 + // Freeing DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 + + // Deleting tag 474 + // (op 1781) Deallocate 522 + // Freeing DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s0 + + // Deleting tag 522 + // (op 1781) Deallocate 525 + // Deleting tag 525 + // (op 1051) Deallocate{}(1781) END + // (op 1051) end: generate({1045}) + // (op 1051) Unlock Scope 1051 + // Unlock None + // (op 314) Scope(1051) END + // (op 314) end: generate({1051}) + // (op 313) SetCoordinate(314) END + // (op 313) end: generate({314}) + // (op 670) SetCoordinate(313) END + // (op 670) Deallocate{}(1799) BEGIN + // (op 1799) Deallocate 58 + // Deleting tag 58 + // (op 1799) Deallocate 303 + // Deleting tag 303 + // (op 1799) Deallocate 118 + // Deleting tag 118 + // (op 1799) Deallocate 477 + // Freeing DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 + + // Deleting tag 477 + // (op 1799) Deallocate 496 + // Freeing DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 + + // Deleting tag 496 + // (op 1799) Deallocate 532 + // Deleting tag 532 + // (op 1799) Deallocate 133 + // Deleting tag 133 + // (op 1799) Deallocate 73 + // Deleting tag 73 + // (op 1799) Deallocate 301 + // Deleting tag 301 + // (op 1799) Deallocate 21 + // Deleting tag 21 + // (op 1799) Deallocate 548 + // Deleting tag 548 + // (op 1799) Deallocate 13 + // Deleting tag 13 + // (op 670) Deallocate{}(1799) END + // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) BEGIN + // (op 2003) Deallocate Tensor_2_pointer + // Freeing Tensor_2_pointer: 2 SGPRs (Value: Raw32): s10, s11 + + // (op 2003) Deallocate Tensor_0_pointer + // Freeing Tensor_0_pointer: 2 SGPRs (Value: Raw32): s6, s7 + + // (op 2003) Deallocate Tensor_0_extent_0 + // Freeing Tensor_0_extent_0: 2 SGPRs (Value: Raw32): s4, s5 + + // (op 2003) Deallocate Tensor_2_stride_1_12 + // Freeing Tensor_2_stride_1_12: 2 SGPRs (Value: Raw32): s22, s23 + + // (op 2003) Deallocate Tensor_0_stride_0_9 + // Freeing Tensor_0_stride_0_9: 2 SGPRs (Value: Raw32): s18, s19 + + // (op 2003) Deallocate Tensor_2_extent_2 + // Freeing Tensor_2_extent_2: 2 SGPRs (Value: Raw32): s8, s9 + + // (op 2003) Deallocate Tensor_0_size_1_10 + // Freeing Tensor_0_size_1_10: 2 SGPRs (Value: Raw32): s20, s21 + + // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) END + // (op 670) Barrier(1801) BEGIN +s_barrier // (op 1801) + // (op 670) Barrier(1801) END + // (op 670) end: generate({675}) + // (op 670) Unlock Scope 670 + // Unlock None + // (op 1) Scope(670) END + // (op 1) Deallocate{}(1867) BEGIN + // (op 1867) Deallocate 631 + // Deleting tag 631 + // (op 1867) Deallocate 629 + // Deleting tag 629 + // (op 1867) Deallocate 619 + // Deleting tag 619 + // (op 1867) Deallocate 531 + // Deleting tag 531 + // (op 1867) Deallocate 568 + // Freeing DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v4 + + // Deleting tag 568 + // (op 1867) Deallocate 604 + // Freeing DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v7 + + // Deleting tag 604 + // (op 1867) Deallocate 546 + // Freeing DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v3 + + // Deleting tag 546 + // (op 1867) Deallocate 605 + // Deleting tag 605 + // (op 1867) Deallocate 547 + // Deleting tag 547 + // (op 1867) Deallocate 530 + // Freeing DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 + + // Deleting tag 530 + // (op 1867) Deallocate 533 + // Deleting tag 533 + // (op 1867) Deallocate 580 + // Freeing DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v5 + + // Deleting tag 580 + // (op 1867) Deallocate 616 + // Freeing DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v8 + + // Deleting tag 616 + // (op 1867) Deallocate 628 + // Freeing DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v9 + + // Deleting tag 628 + // (op 1867) Deallocate 569 + // Deleting tag 569 + // (op 1867) Deallocate 617 + // Deleting tag 617 + // (op 1867) Deallocate 581 + // Deleting tag 581 + // (op 1867) Deallocate 593 + // Deleting tag 593 + // (op 1867) Deallocate 571 + // Deleting tag 571 + // (op 1867) Deallocate 549 + // Deleting tag 549 + // (op 1867) Deallocate 607 + // Deleting tag 607 + // (op 1867) Deallocate 583 + // Deleting tag 583 + // (op 1867) Deallocate 592 + // Freeing DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v6 + + // Deleting tag 592 + // (op 1867) Deallocate 595 + // Deleting tag 595 + // (op 1) Deallocate{}(1867) END + // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) BEGIN + // (op 177) Lock for Conditional + // Lock Branch + // (op 177) Generate Equal(0.00000:S, DataFlowTag(24)S)BL into VCC Value: Bool64 x 1: vcc + // (op 177) reg expression + // (op 177) Equal(0.00000:S, v10:S)BL64 +v_cmp_eq_f32 vcc, 0.00000, v10 // (op 177) +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 177) +s_cbranch_vccz RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177 // (op 177) Condition: False, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177 + // (op 177) generate({678}) + // (op 177) Scope(678) BEGIN + // (op 678) Lock Scope 678 + // Lock Branch + // (op 678) generate({681}) + // (op 678) NOP(681) BEGIN + // (op 681) generate({}) + // (op 681) end: generate({}) + // (op 678) NOP(681) END + // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) BEGIN + // (op 29) Assign dim(39) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA + // (op 29) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr + // (op 29) reg expression + // (op 29) reg expression + // (op 29) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S +// Allocated : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 +s_nop 3 +v_accvgpr_read v12, a0 // (op 29) Wait state hazard: XDL Write Hazard +v_accvgpr_read v13, a1 // (op 29) +v_accvgpr_read v14, a2 // (op 29) +v_accvgpr_read v15, a3 // (op 29) +v_accvgpr_read v16, a4 // (op 29) +v_accvgpr_read v17, a5 // (op 29) +v_accvgpr_read v18, a6 // (op 29) +v_accvgpr_read v19, a7 // (op 29) +v_accvgpr_read v20, a8 // (op 29) +v_accvgpr_read v21, a9 // (op 29) +v_accvgpr_read v22, a10 // (op 29) +v_accvgpr_read v23, a11 // (op 29) +v_accvgpr_read v24, a12 // (op 29) +v_accvgpr_read v25, a13 // (op 29) +v_accvgpr_read v26, a14 // (op 29) +v_accvgpr_read v27, a15 // (op 29) +// Allocated : 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 +v_mul_f32 v28, v11, v12 // (op 29) +v_mul_f32 v29, v11, v13 // (op 29) +v_mul_f32 v30, v11, v14 // (op 29) +v_mul_f32 v31, v11, v15 // (op 29) +v_mul_f32 v32, v11, v16 // (op 29) +v_mul_f32 v33, v11, v17 // (op 29) +v_mul_f32 v34, v11, v18 // (op 29) +v_mul_f32 v35, v11, v19 // (op 29) +v_mul_f32 v36, v11, v20 // (op 29) +v_mul_f32 v37, v11, v21 // (op 29) +v_mul_f32 v38, v11, v22 // (op 29) +v_mul_f32 v39, v11, v23 // (op 29) +v_mul_f32 v40, v11, v24 // (op 29) +v_mul_f32 v41, v11, v25 // (op 29) +v_mul_f32 v42, v11, v26 // (op 29) +v_mul_f32 v43, v11, v27 // (op 29) + // Freeing : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 + + // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) END + // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) BEGIN + // (op 35) Assign dim(41) = Convert(DataFlowTag(39)NA)H + // (op 35) Generate Convert(DataFlowTag(39)NA)H into nullptr + // (op 35) reg expression +// Allocated DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 +v_cvt_f16_f32 v12, v28 // (op 35) +v_cvt_f16_f32 v13, v29 // (op 35) +v_cvt_f16_f32 v14, v30 // (op 35) +v_cvt_f16_f32 v15, v31 // (op 35) +v_cvt_f16_f32 v16, v32 // (op 35) +v_cvt_f16_f32 v17, v33 // (op 35) +v_cvt_f16_f32 v18, v34 // (op 35) +v_cvt_f16_f32 v19, v35 // (op 35) +v_cvt_f16_f32 v20, v36 // (op 35) +v_cvt_f16_f32 v21, v37 // (op 35) +v_cvt_f16_f32 v22, v38 // (op 35) +v_cvt_f16_f32 v23, v39 // (op 35) +v_cvt_f16_f32 v24, v40 // (op 35) +v_cvt_f16_f32 v25, v41 // (op 35) +v_cvt_f16_f32 v26, v42 // (op 35) +v_cvt_f16_f32 v27, v43 // (op 35) + // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) END + // (op 678) Deallocate{}(1761) BEGIN + // (op 1761) Deallocate 39 + // Freeing DataFlowTag39: 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 + + // Deleting tag 39 + // (op 678) Deallocate{}(1761) END + // (op 678) NOP(1305) BEGIN + // (op 1305) generate({}) + // (op 1305) end: generate({}) + // (op 678) NOP(1305) END + // (op 678) NOP(1302) BEGIN + // (op 1302) generate({}) + // (op 1302) end: generate({}) + // (op 678) NOP(1302) END + // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) BEGIN + // (op 1309) Assign dim(550) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} + // tag 550: v**UNALLOCATED** + // (op 1309) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag550: VGPR Value: UInt32 x 1: (unallocated) + // (op 1309) Get arg Tensor_15_stride_1_14 + // (op 1309) reg expression + // (op 1309) reg expression + // (op 1309) reg expression + // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1309) reg expression +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_lshrrev_b32 v0, 7, v1 // (op 1309) + // (op 1309) convert + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_and_b32 v3, 63, v1 // (op 1309) + // (op 1309) END: Tile[1] + // (op 1309) LogicalShiftR({Tile[1]: v3:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_lshrrev_b32 v4, 5, v3 // (op 1309) + // (op 1309) BEGIN: Flatten + // (op 1309) {Flatten: ShiftL(v4:U32, 2:U32)U32} + // (op 1309) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1309) value (VGPR Value: UInt32 x 1: v4) + // (op 1309) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v5 +v_lshlrev_b32 v5, 2, v4 // (op 1309) + // (op 1309) END: Flatten + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_lshl_add_u32 v4, v0, 5, v5 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v5 + + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v0 + + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_lshl_add_u32 v0, s2, 6, v4 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) LogicalShiftR({Tile[1]: v3:U32}, 2:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_lshrrev_b32 v4, 2, v3 // (op 1309) + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v3 + + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd(v4:U32, 7:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_and_b32 v3, 7, v4 // (op 1309) + // (op 1309) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_and_b32 v4, 3, v1 // (op 1309) + // (op 1309) END: Tile[1] + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v5 +v_lshl_add_u32 v5, v3, 2, v4 // (op 1309) + // (op 1309) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v4 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v3 + + // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_lshrrev_b32 v3, 6, v1 // (op 1309) + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd(v3:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_and_b32 v4, 1, v3 // (op 1309) + // (op 1309) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v3 + + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_lshl_add_u32 v3, v4, 5, v5 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v5 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_lshl_add_u32 v4, s3, 6, v3 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v3 + + // (op 1309) Multiply({Flatten: v4:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_mul_lo_u32 v3, v4, s26 // (op 1309) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) BEGIN: Join +// Allocated DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v4 +v_add_lshl_u32 v4, v0, v3, 1 // (op 1309) + // (op 1309) END: Join + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v3 + + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v0 + + // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) END + // (op 678) Assign VGPR 16:U64(1310) BEGIN + // (op 1310) Assign dim(551) = 16:U64 + // (op 1310) Assign stride expression + // (op 678) Assign VGPR 16:U64(1310) END + // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) BEGIN + // (op 1311) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 553: s**UNALLOCATED** + // (op 1311) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: (unallocated) + // (op 1311) Get arg Tensor_15_pointer + // (op 1311) Get arg Tensor_15_extent_15 + // (op 1311) reg expression + // (op 1311) reg expression + // (op 1311) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 + // (op 1311) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1311) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) + // (op 1311) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1311): s0, s1 +s_lshl_b64 s[0:1], s[28:29], 1 // (op 1311) + // (op 1311) reg expression +// Allocated DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s4, s5, s6, s7 +s_mov_b32 s4, s30 // (op 1311) reg expression +s_mov_b32 s5, s31 // (op 1311) reg expression +s_mov_b32 s6, s0 // (op 1311) reg expression +s_mov_b32 s7, 131072 // (op 1311) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1311): s0, s1 + + // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) END + // (op 678) NOP(1303) BEGIN + // (op 1303) generate({}) + // (op 1303) end: generate({}) + // (op 678) NOP(1303) END + // (op 678) Assign VGPR 2:U64(1316) BEGIN + // (op 1316) Assign dim(555) = 2:U64 + // (op 1316) Assign stride expression + // (op 678) Assign VGPR 2:U64(1316) END + // (op 678) StoreTiled Value: Halfx2(37) BEGIN + // (op 37) GEN: storeMacroTileWAVE OP 37 MacroTile 41 WaveTile 215 + // (op 37) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 37) Generate 16:U64 into nullptr + // (op 37) Generate 2:U64 into nullptr + // (op 37) Convert in LSTGen + // (op 37) Generate Convert({DataFlowTag39: v[12:27]:H})2xH into nullptr + // (op 37) reg expression +// Allocated DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 +v_pack_b32_f16 v28, v12, v13 // (op 37) +v_pack_b32_f16 v29, v14, v15 // (op 37) +v_pack_b32_f16 v30, v16, v17 // (op 37) +v_pack_b32_f16 v31, v18, v19 // (op 37) +v_pack_b32_f16 v32, v20, v21 // (op 37) +v_pack_b32_f16 v33, v22, v23 // (op 37) +v_pack_b32_f16 v34, v24, v25 // (op 37) +v_pack_b32_f16 v35, v26, v27 // (op 37) + // (op 37) Dir = Store + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 37) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = DataFlowTag550: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 37) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +buffer_store_dwordx2 v[28:29], v4, s[4:7], 0 offen // (op 37) Store value +// VMEM: Expected complete at 3374 (current 3299) +buffer_store_dwordx2 v[30:31], v4, s[4:7], 0 offen offset:16 // (op 37) Store value +// VMEM: Expected complete at 3375 (current 3300) +buffer_store_dwordx2 v[32:33], v4, s[4:7], 0 offen offset:32 // (op 37) Store value +// VMEM: Expected complete at 3376 (current 3301) +buffer_store_dwordx2 v[34:35], v4, s[4:7], 0 offen offset:48 // (op 37) Store value +// VMEM: Expected complete at 3377 (current 3302) + // Freeing DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 678) Tag 37non referenced extraArgs = {Tensor_15_stride_1_14} + + // (op 678) StoreTiled Value: Halfx2(37) END + // (op 678) Deallocate{}(1763) BEGIN + // (op 1763) Deallocate 551 + // Deleting tag 551 + // (op 1763) Deallocate 555 + // Deleting tag 555 + // (op 1763) Deallocate 554 + // Deleting tag 554 + // (op 1763) Deallocate 41 + // Freeing DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 + + // Deleting tag 41 + // (op 1763) Deallocate 550 + // Freeing DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v4 + + // Deleting tag 550 + // (op 678) Deallocate{}(1763) END + // (op 678) end: generate({681}) + // (op 678) Unlock Scope 678 + // Unlock None + // (op 177) Scope(678) END + // (op 177) end: generate({678}) +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 177) +s_branch RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177 // (op 177) Condition: Done, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177 +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177: + // (op 177) + // (op 177) generate({684}) + // (op 177) Scope(684) BEGIN + // (op 684) Lock Scope 684 + // Lock Branch + // (op 684) generate({687}) + // (op 684) NOP(687) BEGIN + // (op 687) generate({}) + // (op 687) end: generate({}) + // (op 684) NOP(687) END + // (op 684) NOP(185) BEGIN + // (op 185) generate({}) + // (op 185) end: generate({}) + // (op 684) NOP(185) END + // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) BEGIN + // (op 186) Assign dim(295) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA + // (op 186) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr + // (op 186) reg expression + // (op 186) reg expression + // (op 186) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S + // (op 684) Scope(1181) BEGIN + // (op 1181) Lock Scope 1181 + // Lock Branch + // (op 1181) generate({1178}) + // (op 1181) NOP(1178) BEGIN + // (op 1178) generate({}) + // (op 1178) end: generate({}) + // (op 1181) NOP(1178) END + // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) BEGIN + // (op 1186) Assign dim(512) = {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} + // tag 512: v**UNALLOCATED** + // (op 1186) Generate {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} into DataFlowTag512: VGPR Value: UInt32 x 1: (unallocated) + // (op 1186) Get arg Tensor_4_stride_1_13 + // (op 1186) reg expression + // (op 1186) reg expression + // (op 1186) reg expression + // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1186) reg expression +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_lshrrev_b32 v0, 7, v1 // (op 1186) + // (op 1186) convert + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_and_b32 v3, 63, v1 // (op 1186) + // (op 1186) END: Flatten[1] + // (op 1186) LogicalShiftR({Flatten[1]: v3:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_lshrrev_b32 v4, 5, v3 // (op 1186) + // (op 1186) BEGIN: Tile + // (op 1186) {Tile: ShiftL(v4:U32, 2:U32)U32} + // (op 1186) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1186) value (VGPR Value: UInt32 x 1: v4) + // (op 1186) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v5 +v_lshlrev_b32 v5, 2, v4 // (op 1186) + // (op 1186) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_lshl_add_u32 v4, v0, 5, v5 // (op 1186) + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v5 + + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v0 + + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_lshl_add_u32 v0, s2, 6, v4 // (op 1186) + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) LogicalShiftR({Flatten[1]: v3:U32}, 2:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_lshrrev_b32 v4, 2, v3 // (op 1186) + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v3 + + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd(v4:U32, 7:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_and_b32 v3, 7, v4 // (op 1186) + // (op 1186) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_and_b32 v4, 3, v1 // (op 1186) + // (op 1186) END: Flatten[1] + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v5 +v_lshl_add_u32 v5, v3, 2, v4 // (op 1186) + // (op 1186) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v4 + + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v3 + + // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_lshrrev_b32 v3, 6, v1 // (op 1186) + // (op 1186) BEGIN: Tile + // (op 1186) {Tile: BitwiseAnd(v3:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_and_b32 v4, 1, v3 // (op 1186) + // (op 1186) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v3 + + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_lshl_add_u32 v3, v4, 5, v5 // (op 1186) + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v5 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_lshl_add_u32 v4, s3, 6, v3 // (op 1186) + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v3 + + // (op 1186) Multiply({Tile: v4:U32}, { convertForwardSubsetTensor_4_stride_1_13: s24:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_mul_lo_u32 v3, v4, s24 // (op 1186) + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) BEGIN: Split +// Allocated DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v4 +v_add_lshl_u32 v4, v0, v3, 1 // (op 1186) + // (op 1186) END: Split + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v3 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v0 + + // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) END + // (op 1181) Deallocate{}(1911) BEGIN + // (op 1911) Deallocate 305 + // Deleting tag 305 + // (op 1911) Deallocate 174 + // Deleting tag 174 + // (op 1911) Deallocate 307 + // Deleting tag 307 + // (op 1181) Deallocate{}(1911) END + // (op 1181) Assign VGPR 16:U64(1187) BEGIN + // (op 1187) Assign dim(513) = 16:U64 + // (op 1187) Assign stride expression + // (op 1181) Assign VGPR 16:U64(1187) END + // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) BEGIN + // (op 1188) Assign dim(515) = Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 515: s**UNALLOCATED** + // (op 1188) Generate Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag515: SGPR Buffer: None x 1: (unallocated) + // (op 1188) Get arg Tensor_4_pointer + // (op 1188) Get arg Tensor_4_extent_4 + // (op 1188) reg expression + // (op 1188) reg expression + // (op 1188) ShiftL({Tensor_4_extent_4: s[12:13]:I64}, 1:U32)I64 + // (op 1188) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1188) value (Tensor_4_extent_4: SGPR Value: Int64 x 1: s[12:13]) + // (op 1188) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1188): s0, s1 +s_lshl_b64 s[0:1], s[12:13], 1 // (op 1188) + // (op 1188) reg expression +// Allocated DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s8, s9, s10, s11 +s_mov_b32 s8, s14 // (op 1188) reg expression +s_mov_b32 s9, s15 // (op 1188) reg expression +s_mov_b32 s10, s0 // (op 1188) reg expression +s_mov_b32 s11, 131072 // (op 1188) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1188): s0, s1 + + // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) END + // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) BEGIN + // (op 2007) Deallocate Tensor_4_pointer + // Freeing Tensor_4_pointer: 2 SGPRs (Value: Raw32): s14, s15 + + // (op 2007) Deallocate Tensor_4_extent_4 + // Freeing Tensor_4_extent_4: 2 SGPRs (Value: Raw32): s12, s13 + + // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) END + // (op 1181) NOP(1179) BEGIN + // (op 1179) generate({}) + // (op 1179) end: generate({}) + // (op 1181) NOP(1179) END + // (op 1181) Assign VGPR 2:U64(1193) BEGIN + // (op 1193) Assign dim(517) = 2:U64 + // (op 1193) Assign stride expression + // (op 1181) Assign VGPR 2:U64(1193) END + // (op 1181) LoadTiled Value: Halfx2(190) BEGIN + // (op 190) GEN: loadMacroTileWAVECIACCUM OP 190 WaveTile 175 + // (op 190) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 190) Generate 16:U64 into nullptr + // (op 190) Generate 2:U64 into nullptr + // tag 291: v**UNALLOCATED** + // (op 190) Dir = Load + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 8: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 190) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 8: (unallocated) + // info.rowOffsetReg = DataFlowTag512: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 190) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 +buffer_load_dwordx2 v[12:13], v4, s[8:11], 0 offen // (op 190) Load value +// VMEM: Expected stall of 49. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 3450 (current 3375) +buffer_load_dwordx2 v[14:15], v4, s[8:11], 0 offen offset:16 // (op 190) Load value +// VMEM: Expected complete at 3451 (current 3376) +buffer_load_dwordx2 v[16:17], v4, s[8:11], 0 offen offset:32 // (op 190) Load value +// VMEM: Expected complete at 3452 (current 3377) +buffer_load_dwordx2 v[18:19], v4, s[8:11], 0 offen offset:48 // (op 190) Load value +// VMEM: Expected complete at 3453 (current 3378) + // (op 1181) Tag 190non referenced extraArgs = {Tensor_4_stride_1_13} + + // (op 1181) LoadTiled Value: Halfx2(190) END + // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) BEGIN + // (op 1777) Deallocate 3 + // Deleting tag 3 + // (op 1777) Deallocate 513 + // Deleting tag 513 + // (op 1777) Deallocate 515 + // Freeing DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s8, s9, s10, s11 + + // Deleting tag 515 + // (op 1777) Deallocate 512 + // Freeing DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v4 + + // Deleting tag 512 + // (op 1777) Deallocate 516 + // Deleting tag 516 + // (op 1777) Deallocate 517 + // Deleting tag 517 + // (op 1777) Deallocate Tensor_4_stride_1_13 + // Freeing Tensor_4_stride_1_13: 2 SGPRs (Value: Raw32): s24, s25 + + // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) END + // (op 1181) end: generate({1178}) + // (op 1181) Unlock Scope 1181 + // Unlock None + // (op 684) Scope(1181) END +// Allocated : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 +v_accvgpr_read v20, a0 // (op 186) + // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) BEGIN + // (op 191) Assign dim(293) = Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA + // (op 191) Generate Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA into nullptr + // (op 191) reg expression + // (op 191) reg expression + // (op 191) Multiply(v10:S, v[12:19]:2xH)S +v_accvgpr_read v21, a1 // (op 186) +v_accvgpr_read v22, a2 // (op 186) +v_accvgpr_read v23, a3 // (op 186) +v_accvgpr_read v24, a4 // (op 186) +v_accvgpr_read v25, a5 // (op 186) +v_accvgpr_read v26, a6 // (op 186) +v_accvgpr_read v27, a7 // (op 186) +v_accvgpr_read v28, a8 // (op 186) +v_accvgpr_read v29, a9 // (op 186) +v_accvgpr_read v30, a10 // (op 186) +v_accvgpr_read v31, a11 // (op 186) +v_accvgpr_read v32, a12 // (op 186) +v_accvgpr_read v33, a13 // (op 186) +v_accvgpr_read v34, a14 // (op 186) +v_accvgpr_read v35, a15 // (op 186) +// Allocated : 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 +v_mul_f32 v36, v11, v20 // (op 186) +v_mul_f32 v37, v11, v21 // (op 186) +v_mul_f32 v38, v11, v22 // (op 186) +v_mul_f32 v39, v11, v23 // (op 186) +v_mul_f32 v40, v11, v24 // (op 186) +v_mul_f32 v41, v11, v25 // (op 186) +v_mul_f32 v42, v11, v26 // (op 186) +v_mul_f32 v43, v11, v27 // (op 186) +v_mul_f32 v44, v11, v28 // (op 186) +v_mul_f32 v45, v11, v29 // (op 186) +v_mul_f32 v46, v11, v30 // (op 186) +v_mul_f32 v47, v11, v31 // (op 186) +v_mul_f32 v48, v11, v32 // (op 186) +v_mul_f32 v49, v11, v33 // (op 186) +v_mul_f32 v50, v11, v34 // (op 186) +v_mul_f32 v51, v11, v35 // (op 186) + // Freeing : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) END +// Allocated : 2 VGPRs (Value: Float) (op 191): v8, v9 +s_waitcnt vmcnt(3) +v_cvt_f32_f16 v8, v12 // (op 191) +v_lshrrev_b32 v9, 16, v12 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +// Allocated : 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 +v_mul_f32 v20, v10, v8 // (op 191) +v_mul_f32 v21, v10, v9 // (op 191) +v_cvt_f32_f16 v8, v13 // (op 191) +v_lshrrev_b32 v9, 16, v13 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v22, v10, v8 // (op 191) +v_mul_f32 v23, v10, v9 // (op 191) +s_waitcnt vmcnt(2) +v_cvt_f32_f16 v8, v14 // (op 191) +v_lshrrev_b32 v9, 16, v14 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v24, v10, v8 // (op 191) +v_mul_f32 v25, v10, v9 // (op 191) +v_cvt_f32_f16 v8, v15 // (op 191) +v_lshrrev_b32 v9, 16, v15 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v26, v10, v8 // (op 191) +v_mul_f32 v27, v10, v9 // (op 191) +s_waitcnt vmcnt(1) +v_cvt_f32_f16 v8, v16 // (op 191) +v_lshrrev_b32 v9, 16, v16 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v28, v10, v8 // (op 191) +v_mul_f32 v29, v10, v9 // (op 191) +v_cvt_f32_f16 v8, v17 // (op 191) +v_lshrrev_b32 v9, 16, v17 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v30, v10, v8 // (op 191) +v_mul_f32 v31, v10, v9 // (op 191) +s_waitcnt vmcnt(0) +v_cvt_f32_f16 v8, v18 // (op 191) +v_lshrrev_b32 v9, 16, v18 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v32, v10, v8 // (op 191) +v_mul_f32 v33, v10, v9 // (op 191) +v_cvt_f32_f16 v8, v19 // (op 191) +v_lshrrev_b32 v9, 16, v19 // (op 191) +v_cvt_f32_f16 v9, v9 // (op 191) +v_mul_f32 v34, v10, v8 // (op 191) +v_mul_f32 v35, v10, v9 // (op 191) + // Freeing : 2 VGPRs (Value: Float) (op 191): v8, v9 + + // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) END + // (op 684) Deallocate{}(1779) BEGIN + // (op 1779) Deallocate 291 + // Freeing : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 + + // Deleting tag 291 + // (op 684) Deallocate{}(1779) END + // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) BEGIN + // (op 187) Assign dim(297) = Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA + // (op 187) Generate Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA into nullptr + // (op 187) reg expression + // (op 187) reg expression + // (op 187) Add({DataFlowTag293: v[20:35]:S}, {DataFlowTag295: v[36:51]:S})S +// Allocated : 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 +v_add_f32 v52, v20, v36 // (op 187) +v_add_f32 v53, v21, v37 // (op 187) +v_add_f32 v54, v22, v38 // (op 187) +v_add_f32 v55, v23, v39 // (op 187) +v_add_f32 v56, v24, v40 // (op 187) +v_add_f32 v57, v25, v41 // (op 187) +v_add_f32 v58, v26, v42 // (op 187) +v_add_f32 v59, v27, v43 // (op 187) +v_add_f32 v60, v28, v44 // (op 187) +v_add_f32 v61, v29, v45 // (op 187) +v_add_f32 v62, v30, v46 // (op 187) +v_add_f32 v63, v31, v47 // (op 187) +v_add_f32 v64, v32, v48 // (op 187) +v_add_f32 v65, v33, v49 // (op 187) +v_add_f32 v66, v34, v50 // (op 187) +v_add_f32 v67, v35, v51 // (op 187) + // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) END + // (op 684) Deallocate{}(1771) BEGIN + // (op 1771) Deallocate 293 + // Freeing DataFlowTag293: 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 + + // Deleting tag 293 + // (op 1771) Deallocate 295 + // Freeing DataFlowTag295: 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 + + // Deleting tag 295 + // (op 684) Deallocate{}(1771) END + // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) BEGIN + // (op 188) Assign dim(299) = Convert(DataFlowTag(297)NA)H + // (op 188) Generate Convert(DataFlowTag(297)NA)H into nullptr + // (op 188) reg expression +// Allocated DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 +v_cvt_f16_f32 v12, v52 // (op 188) +v_cvt_f16_f32 v13, v53 // (op 188) +v_cvt_f16_f32 v14, v54 // (op 188) +v_cvt_f16_f32 v15, v55 // (op 188) +v_cvt_f16_f32 v16, v56 // (op 188) +v_cvt_f16_f32 v17, v57 // (op 188) +v_cvt_f16_f32 v18, v58 // (op 188) +v_cvt_f16_f32 v19, v59 // (op 188) +v_cvt_f16_f32 v20, v60 // (op 188) +v_cvt_f16_f32 v21, v61 // (op 188) +v_cvt_f16_f32 v22, v62 // (op 188) +v_cvt_f16_f32 v23, v63 // (op 188) +v_cvt_f16_f32 v24, v64 // (op 188) +v_cvt_f16_f32 v25, v65 // (op 188) +v_cvt_f16_f32 v26, v66 // (op 188) +v_cvt_f16_f32 v27, v67 // (op 188) + // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) END + // (op 684) Deallocate{}(1773) BEGIN + // (op 1773) Deallocate 297 + // Freeing DataFlowTag297: 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 + + // Deleting tag 297 + // (op 684) Deallocate{}(1773) END + // (op 684) NOP(1322) BEGIN + // (op 1322) generate({}) + // (op 1322) end: generate({}) + // (op 684) NOP(1322) END + // (op 684) NOP(1319) BEGIN + // (op 1319) generate({}) + // (op 1319) end: generate({}) + // (op 684) NOP(1319) END + // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) BEGIN + // (op 1326) Assign dim(556) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} + // tag 556: v**UNALLOCATED** + // (op 1326) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag556: VGPR Value: UInt32 x 1: (unallocated) + // (op 1326) Get arg Tensor_15_stride_1_14 + // (op 1326) reg expression + // (op 1326) reg expression + // (op 1326) reg expression + // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1326) reg expression +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_lshrrev_b32 v0, 7, v1 // (op 1326) + // (op 1326) convert + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_and_b32 v3, 63, v1 // (op 1326) + // (op 1326) END: Tile[1] + // (op 1326) LogicalShiftR({Tile[1]: v3:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_lshrrev_b32 v4, 5, v3 // (op 1326) + // (op 1326) BEGIN: Flatten + // (op 1326) {Flatten: ShiftL(v4:U32, 2:U32)U32} + // (op 1326) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1326) value (VGPR Value: UInt32 x 1: v4) + // (op 1326) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v5 +v_lshlrev_b32 v5, 2, v4 // (op 1326) + // (op 1326) END: Flatten + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_lshl_add_u32 v4, v0, 5, v5 // (op 1326) + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v5 + + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v0 + + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_lshl_add_u32 v0, s2, 6, v4 // (op 1326) + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) LogicalShiftR({Tile[1]: v3:U32}, 2:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_lshrrev_b32 v4, 2, v3 // (op 1326) + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v3 + + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd(v4:U32, 7:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_and_b32 v3, 7, v4 // (op 1326) + // (op 1326) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_and_b32 v4, 3, v1 // (op 1326) + // (op 1326) END: Tile[1] + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v5 +v_lshl_add_u32 v5, v3, 2, v4 // (op 1326) + // (op 1326) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v4 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v3 + + // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_lshrrev_b32 v3, 6, v1 // (op 1326) + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd(v3:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_and_b32 v4, 1, v3 // (op 1326) + // (op 1326) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v3 + + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_lshl_add_u32 v3, v4, 5, v5 // (op 1326) + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v5 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_lshl_add_u32 v4, s3, 6, v3 // (op 1326) + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v3 + + // (op 1326) Multiply({Flatten: v4:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_mul_lo_u32 v3, v4, s26 // (op 1326) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) BEGIN: Join +// Allocated DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v4 +v_add_lshl_u32 v4, v0, v3, 1 // (op 1326) + // (op 1326) END: Join + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v3 + + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v0 + + // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) END + // (op 684) Assign VGPR 16:U64(1327) BEGIN + // (op 1327) Assign dim(557) = 16:U64 + // (op 1327) Assign stride expression + // (op 684) Assign VGPR 16:U64(1327) END + // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) BEGIN + // (op 1328) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1328) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: s[4:7] + // (op 1328) Get arg Tensor_15_pointer + // (op 1328) Get arg Tensor_15_extent_15 + // (op 1328) reg expression + // (op 1328) reg expression + // (op 1328) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 + // (op 1328) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1328) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) + // (op 1328) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1328): s0, s1 +s_lshl_b64 s[0:1], s[28:29], 1 // (op 1328) + // (op 1328) reg expression +s_mov_b32 s4, s30 // (op 1328) reg expression +s_mov_b32 s5, s31 // (op 1328) reg expression +s_mov_b32 s6, s0 // (op 1328) reg expression +s_mov_b32 s7, 131072 // (op 1328) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1328): s0, s1 + + // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) END + // (op 684) NOP(1320) BEGIN + // (op 1320) generate({}) + // (op 1320) end: generate({}) + // (op 684) NOP(1320) END + // (op 684) Assign VGPR 2:U64(1333) BEGIN + // (op 1333) Assign dim(559) = 2:U64 + // (op 1333) Assign stride expression + // (op 684) Assign VGPR 2:U64(1333) END + // (op 684) StoreTiled Value: Halfx2(189) BEGIN + // (op 189) GEN: storeMacroTileWAVE OP 189 MacroTile 299 WaveTile 215 + // (op 189) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 189) Generate 16:U64 into nullptr + // (op 189) Generate 2:U64 into nullptr + // (op 189) Convert in LSTGen + // (op 189) Generate Convert({DataFlowTag297: v[12:27]:H})2xH into nullptr + // (op 189) reg expression +// Allocated DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 +v_pack_b32_f16 v28, v12, v13 // (op 189) +v_pack_b32_f16 v29, v14, v15 // (op 189) +v_pack_b32_f16 v30, v16, v17 // (op 189) +v_pack_b32_f16 v31, v18, v19 // (op 189) +v_pack_b32_f16 v32, v20, v21 // (op 189) +v_pack_b32_f16 v33, v22, v23 // (op 189) +v_pack_b32_f16 v34, v24, v25 // (op 189) +v_pack_b32_f16 v35, v26, v27 // (op 189) + // (op 189) Dir = Store + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 189) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = DataFlowTag556: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 189) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +buffer_store_dwordx2 v[28:29], v4, s[4:7], 0 offen // (op 189) Store value +// VMEM: Expected complete at 3631 (current 3556) +buffer_store_dwordx2 v[30:31], v4, s[4:7], 0 offen offset:16 // (op 189) Store value +// VMEM: Expected complete at 3632 (current 3557) +buffer_store_dwordx2 v[32:33], v4, s[4:7], 0 offen offset:32 // (op 189) Store value +// VMEM: Expected complete at 3633 (current 3558) +buffer_store_dwordx2 v[34:35], v4, s[4:7], 0 offen offset:48 // (op 189) Store value +// VMEM: Expected complete at 3634 (current 3559) + // Freeing DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 684) Tag 189non referenced extraArgs = {Tensor_15_stride_1_14} + + // (op 684) StoreTiled Value: Halfx2(189) END + // (op 684) Deallocate{}(1775) BEGIN + // (op 1775) Deallocate 558 + // Deleting tag 558 + // (op 1775) Deallocate 557 + // Deleting tag 557 + // (op 1775) Deallocate 559 + // Deleting tag 559 + // (op 1775) Deallocate 556 + // Freeing DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v4 + + // Deleting tag 556 + // (op 1775) Deallocate 299 + // Freeing DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 + + // Deleting tag 299 + // (op 684) Deallocate{}(1775) END + // (op 684) end: generate({687}) + // (op 684) Unlock Scope 684 + // Unlock None + // (op 177) Scope(684) END + // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) BEGIN + // (op 1869) Deallocate 311 + // Deleting tag 311 + // (op 1869) Deallocate 553 + // Freeing DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s4, s5, s6, s7 + + // Deleting tag 553 + // (op 1869) Deallocate 309 + // Deleting tag 309 + // (op 1869) Deallocate 214 + // Deleting tag 214 + // (op 1869) Deallocate Tensor_15_stride_1_14 + // Freeing Tensor_15_stride_1_14: 2 SGPRs (Value: Raw32): s26, s27 + + // (op 1869) Deallocate Tensor_15_extent_15 + // Freeing Tensor_15_extent_15: 2 SGPRs (Value: Raw32): s28, s29 + + // (op 1869) Deallocate Tensor_15_pointer + // Freeing Tensor_15_pointer: 2 SGPRs (Value: Raw32): s30, s31 + + // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) END + // (op 177) end: generate({684}) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177: + // (op 177) + // (op 177) Unlock Conditional + // Unlock None + // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) END + // (op 1) Deallocate{}(1769) BEGIN + // (op 1769) Deallocate 33 + // Freeing : 1 VGPR (Value: Float) (op 24): v11 + + // Deleting tag 33 + // (op 1769) Deallocate 24 + // Freeing : 1 VGPR (Value: Float) (op 2): v10 + + // Deleting tag 24 + // (op 1769) Deallocate 35 + // Freeing DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 + + // Deleting tag 35 + // (op 1) Deallocate{}(1769) END + // (op 1) end: generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) + // Kernel(1) END + // end: generate({1}) + // CodeGeneratorVisitor::generate() end +s_endpgm // End of RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a +.LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_end: + +.size RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a, .LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_end-RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a +.rodata +.p2align 6 +.amdhsa_kernel RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a + // Resource limits + .amdhsa_next_free_vgpr 96 + .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr + .amdhsa_group_segment_fixed_size 65536 // lds bytes + .amdhsa_accum_offset 80 + // Initial kernel state + .amdhsa_user_sgpr_kernarg_segment_ptr 1 +.amdhsa_system_sgpr_workgroup_id_x 1 +.amdhsa_system_sgpr_workgroup_id_y 1 +.amdhsa_system_sgpr_workgroup_id_z 0 +.amdhsa_system_sgpr_workgroup_info 0 +.amdhsa_system_vgpr_workitem_id 1 +.end_amdhsa_kernel + +.amdgpu_metadata +--- +amdhsa.version: [1, 2] +amdhsa.kernels: + - .name: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a + .symbol: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a.kd + .kernarg_segment_size: 112 + .group_segment_fixed_size: 65536 + .private_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .sgpr_count: 50 + .vgpr_count: 78 + .agpr_count: 16 + .max_flat_workgroup_size: 256 + .workgroup_size: [256, 1, 1] + .kernel_dimensions: 2 + .wavefront_size: 64 + .workitem_count: [{type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_0_size_0_8, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 56, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 256}}, {type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_2_size_1_11, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 80, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, {is-null: true}] + .dynamic_sharedmemory_bytes: {type: LiteralValue.UInt32, dataType: UInt32, value: 0} + .args: + - .name: Tensor_0_extent_0 + .size: 8 + .offset: 0 + .expression: {type: CommandArgument, size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_pointer + .size: 8 + .offset: 8 + .expression: {type: CommandArgument, size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: Tensor_2_extent_2 + .size: 8 + .offset: 16 + .expression: {type: CommandArgument, size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_2_pointer + .size: 8 + .offset: 24 + .expression: {type: CommandArgument, size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: Tensor_4_extent_4 + .size: 8 + .offset: 32 + .expression: {type: CommandArgument, size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_4_pointer + .size: 8 + .offset: 40 + .expression: {type: CommandArgument, size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: user_Float_Value_6 + .size: 4 + .offset: 48 + .expression: {type: CommandArgument, size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + .variableType: {dataType: Float, pointerType: Value} + .value_kind: by_value + - .name: user_Float_Value_8 + .size: 4 + .offset: 52 + .expression: {type: CommandArgument, size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + .variableType: {dataType: Float, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_stride_0_9 + .size: 8 + .offset: 56 + .expression: {type: CommandArgument, size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_size_1_10 + .size: 8 + .offset: 64 + .expression: {type: CommandArgument, size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_2_stride_1_12 + .size: 8 + .offset: 72 + .expression: {type: CommandArgument, size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_4_stride_1_13 + .size: 8 + .offset: 80 + .expression: {type: CommandArgument, size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_stride_1_14 + .size: 8 + .offset: 88 + .expression: {type: CommandArgument, size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_extent_15 + .size: 8 + .offset: 96 + .expression: {type: CommandArgument, size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_pointer + .size: 8 + .offset: 104 + .expression: {type: CommandArgument, size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + .kernel_graph_dot: "digraph {\n\"coord1\"[label=\"User{Tensor_0_extent_0:I64}(1)\"];\n\"coord2\"[label=\"User{Tensor_2_extent_2:I64}(2)\"];\n\"coord3\"[label=\"User{Tensor_4_extent_4:I64}(3)\"];\n\"coord4\"[label=\"User{NA}(4)\"];\n\"coord5\"[label=\"User{NA}(5)\"];\n\"coord6\"[label=\"MacroTile{NA}(2/WAVE_Direct2LDS/MATRIX_A){64,64}-(8,2)(6)\"];\n\"coord7\"[label=\"MacroTile{NA}(2/WAVE_Direct2LDS/MATRIX_B){64,64}-(2,8)(7)\"];\n\"coord8\"[label=\"SubDimension{0, Tensor_0_size_0_8:I64}(8)\"];\n\"coord9\"[label=\"SubDimension{1, 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NA}(552)\"];\n\"coord553\"[label=\"Buffer(553)\",shape=box];\n\"coord554\"[label=\"Offset(554)\",shape=box];\n\"coord555\"[label=\"Stride(555)\",shape=box];\n\"coord556\"[label=\"Offset(556)\",shape=box];\n\"coord557\"[label=\"Stride(557)\",shape=box];\n\"coord558\"[label=\"Offset(558)\",shape=box];\n\"coord559\"[label=\"Stride(559)\",shape=box];\n\"coord560\"[label=\"Offset(560)\",shape=box];\n\"coord561\"[label=\"Stride(561)\",shape=box];\n\"coord562\"[label=\"Offset(562)\",shape=box];\n\"coord563\"[label=\"Stride(563)\",shape=box];\n\"coord564\"[label=\"Offset(564)\",shape=box];\n\"coord565\"[label=\"Stride(565)\",shape=box];\n\"coord566\"[label=\"Offset(566)\",shape=box];\n\"coord567\"[label=\"Stride(567)\",shape=box];\n\"coord568\"[label=\"Offset(568)\",shape=box];\n\"coord569\"[label=\"Stride(569)\",shape=box];\n\"coord570\"[label=\"Offset(570)\",shape=box];\n\"coord571\"[label=\"Stride(571)\",shape=box];\n\"coord572\"[label=\"Offset(572)\",shape=box];\n\"coord573\"[label=\"Stride(573)\",shape=box];\n\"coord574\"[label=\"Offset(574)\",shape=box];\n\"coord575\"[label=\"Stride(575)\",shape=box];\n\"coord576\"[label=\"Offset(576)\",shape=box];\n\"coord577\"[label=\"Stride(577)\",shape=box];\n\"coord578\"[label=\"Offset(578)\",shape=box];\n\"coord579\"[label=\"Stride(579)\",shape=box];\n\"coord580\"[label=\"Offset(580)\",shape=box];\n\"coord581\"[label=\"Stride(581)\",shape=box];\n\"coord582\"[label=\"Offset(582)\",shape=box];\n\"coord583\"[label=\"Stride(583)\",shape=box];\n\"coord584\"[label=\"Offset(584)\",shape=box];\n\"coord585\"[label=\"Stride(585)\",shape=box];\n\"coord586\"[label=\"Offset(586)\",shape=box];\n\"coord587\"[label=\"Stride(587)\",shape=box];\n\"coord588\"[label=\"Offset(588)\",shape=box];\n\"coord589\"[label=\"Stride(589)\",shape=box];\n\"coord590\"[label=\"Offset(590)\",shape=box];\n\"coord591\"[label=\"Stride(591)\",shape=box];\n\"coord592\"[label=\"Offset(592)\",shape=box];\n\"coord593\"[label=\"Stride(593)\",shape=box];\n\"coord594\"[label=\"Offset(594)\",shape=box];\n\"coord595\"[label=\"Stride(595)\",shape=box];\n\"coord596\"[label=\"Offset(596)\",shape=box];\n\"coord597\"[label=\"Stride(597)\",shape=box];\n\"coord598\"[label=\"Offset(598)\",shape=box];\n\"coord599\"[label=\"Stride(599)\",shape=box];\n\"coord600\"[label=\"Offset(600)\",shape=box];\n\"coord601\"[label=\"Stride(601)\",shape=box];\n\"coord602\"[label=\"Offset(602)\",shape=box];\n\"coord603\"[label=\"Stride(603)\",shape=box];\n\"coord604\"[label=\"Offset(604)\",shape=box];\n\"coord605\"[label=\"Stride(605)\",shape=box];\n\"coord606\"[label=\"Offset(606)\",shape=box];\n\"coord607\"[label=\"Stride(607)\",shape=box];\n\"coord608\"[label=\"Offset(608)\",shape=box];\n\"coord609\"[label=\"Stride(609)\",shape=box];\n\"coord610\"[label=\"Offset(610)\",shape=box];\n\"coord611\"[label=\"Stride(611)\",shape=box];\n\"coord612\"[label=\"Offset(612)\",shape=box];\n\"coord613\"[label=\"Stride(613)\",shape=box];\n\"coord614\"[label=\"Offset(614)\",shape=box];\n\"coord615\"[label=\"Stride(615)\",shape=box];\n\"coord616\"[label=\"Offset(616)\",shape=box];\n\"coord617\"[label=\"Stride(617)\",shape=box];\n\"coord618\"[label=\"Offset(618)\",shape=box];\n\"coord619\"[label=\"Stride(619)\",shape=box];\n\"coord620\"[label=\"Offset(620)\",shape=box];\n\"coord621\"[label=\"Stride(621)\",shape=box];\n\"coord622\"[label=\"Offset(622)\",shape=box];\n\"coord623\"[label=\"Stride(623)\",shape=box];\n\"coord624\"[label=\"Offset(624)\",shape=box];\n\"coord625\"[label=\"Stride(625)\",shape=box];\n\"coord626\"[label=\"Offset(626)\",shape=box];\n\"coord627\"[label=\"Stride(627)\",shape=box];\n\"coord628\"[label=\"Offset(628)\",shape=box];\n\"coord629\"[label=\"Stride(629)\",shape=box];\n\"coord630\"[label=\"Offset(630)\",shape=box];\n\"coord631\"[label=\"Stride(631)\",shape=box];\n\"coord632\"[label=\"Alias(632)\",shape=box];\n\"coord633\"[label=\"Alias(633)\",shape=box];\n\"coord634\"[label=\"Alias(634)\",shape=box];\n\"coord635\"[label=\"Alias(635)\",shape=box];\n\"coord636\"[label=\"Alias(636)\",shape=box];\n\"coord637\"[label=\"Alias(637)\",shape=box];\n\"coord638\"[label=\"Alias(638)\",shape=box];\n\"coord639\"[label=\"Alias(639)\",shape=box];\n\"coord640\"[label=\"Alias(640)\",shape=box];\n\"coord641\"[label=\"Alias(641)\",shape=box];\n\"coord642\"[label=\"Alias(642)\",shape=box];\n\"coord643\"[label=\"Alias(643)\",shape=box];\n\"coord644\"[label=\"Alias(644)\",shape=box];\n\"coord645\"[label=\"Alias(645)\",shape=box];\n\"coord646\"[label=\"Alias(646)\",shape=box];\n\"coord647\"[label=\"Alias(647)\",shape=box];\n\"coord648\"[label=\"Alias(648)\",shape=box];\n\"coord649\"[label=\"Alias(649)\",shape=box];\n\"coord650\"[label=\"Alias(650)\",shape=box];\n\"coord651\"[label=\"Alias(651)\",shape=box];\n\"coord652\"[label=\"Alias(652)\",shape=box];\n\"coord653\"[label=\"Alias(653)\",shape=box];\n\"coord654\"[label=\"Alias(654)\",shape=box];\n\"coord655\"[label=\"Alias(655)\",shape=box];\n\"coord656\"[label=\"Alias(656)\",shape=box];\n\"coord657\"[label=\"Alias(657)\",shape=box];\n\"coord1\" -> \"coord10\"\n\"coord1\" -> \"coord12\"\n\"coord1\" -> \"coord66\"\n\"coord1\" -> \"coord474\"\n\"coord1\" -> \"coord475\"\n\"coord1\" -> \"coord478\"\n\"coord1\" -> \"coord479\"\n\"coord1\" -> \"coord480\"\n\"coord1\" -> \"coord481\"\n\"coord1\" -> \"coord482\"\n\"coord1\" -> \"coord483\"\n\"coord1\" -> \"coord484\"\n\"coord1\" -> \"coord485\"\n\"coord1\" -> \"coord486\"\n\"coord1\" -> \"coord487\"\n\"coord1\" -> \"coord488\"\n\"coord1\" -> \"coord489\"\n\"coord1\" -> \"coord490\"\n\"coord1\" -> \"coord491\"\n\"coord1\" -> \"coord492\"\n\"coord2\" -> \"coord18\"\n\"coord2\" -> \"coord20\"\n\"coord2\" -> \"coord126\"\n\"coord2\" -> \"coord493\"\n\"coord2\" -> \"coord494\"\n\"coord2\" -> \"coord497\"\n\"coord2\" -> \"coord498\"\n\"coord2\" -> \"coord499\"\n\"coord2\" -> \"coord500\"\n\"coord2\" -> \"coord501\"\n\"coord2\" -> \"coord502\"\n\"coord2\" -> \"coord503\"\n\"coord2\" -> \"coord504\"\n\"coord2\" -> \"coord505\"\n\"coord2\" -> \"coord506\"\n\"coord2\" -> \"coord507\"\n\"coord2\" -> \"coord508\"\n\"coord2\" -> \"coord509\"\n\"coord2\" -> \"coord510\"\n\"coord2\" -> \"coord511\"\n\"coord3\" -> \"coord28\"\n\"coord3\" -> \"coord30\"\n\"coord3\" -> \"coord207\"\n\"coord3\" -> \"coord512\"\n\"coord3\" -> \"coord513\"\n\"coord3\" -> \"coord516\"\n\"coord3\" -> \"coord517\"\n\"coord4\" -> \"coord34\"\n\"coord5\" -> \"coord25\"\n\"coord6\" -> \"coord14\"\n\"coord6\" -> \"coord36\"\n\"coord7\" -> \"coord22\"\n\"coord7\" -> \"coord36\"\n\"coord8\" -> \"coord52\"\n\"coord9\" -> \"coord53\"\n\"coord10\" -> \"coord8\"\n\"coord10\" -> \"coord9\"\n\"coord12\" -> \"coord11\"\n\"coord13\" -> \"coord15\"\n\"coord13\" -> \"coord107\"\n\"coord13\" -> \"coord530\"\n\"coord13\" -> \"coord531\"\n\"coord13\" -> \"coord532\"\n\"coord13\" -> \"coord533\"\n\"coord14\" -> \"coord13\"\n\"coord15\" -> \"coord11\"\n\"coord16\" -> \"coord112\"\n\"coord17\" -> \"coord113\"\n\"coord18\" -> \"coord16\"\n\"coord18\" -> \"coord17\"\n\"coord20\" -> \"coord19\"\n\"coord21\" -> \"coord23\"\n\"coord21\" -> \"coord167\"\n\"coord21\" -> \"coord546\"\n\"coord21\" -> \"coord547\"\n\"coord21\" -> \"coord548\"\n\"coord21\" -> \"coord549\"\n\"coord22\" -> \"coord21\"\n\"coord23\" -> \"coord19\"\n\"coord24\" -> \"coord32\"\n\"coord25\" -> \"coord24\"\n\"coord26\" -> \"coord172\"\n\"coord27\" -> \"coord173\"\n\"coord28\" -> \"coord26\"\n\"coord28\" -> \"coord27\"\n\"coord29\" -> \"coord32\"\n\"coord30\" -> \"coord29\"\n\"coord31\" -> \"coord40\"\n\"coord32\" -> \"coord31\"\n\"coord33\" -> \"coord38\"\n\"coord34\" -> \"coord33\"\n\"coord35\" -> \"coord38\"\n\"coord36\" -> \"coord35\"\n\"coord37\" -> \"coord40\"\n\"coord38\" -> \"coord37\"\n\"coord39\" -> \"coord42\"\n\"coord40\" -> \"coord39\"\n\"coord41\" -> \"coord47\"\n\"coord41\" -> \"coord244\"\n\"coord42\" -> \"coord41\"\n\"coord43\" -> \"coord46\"\n\"coord44\" -> \"coord46\"\n\"coord46\" -> \"coord45\"\n\"coord47\" -> \"coord45\"\n\"coord48\" -> \"coord302\"\n\"coord49\" -> \"coord314\"\n\"coord50\" -> \"coord64\"\n\"coord51\" -> \"coord65\"\n\"coord52\" -> \"coord48\"\n\"coord52\" -> \"coord50\"\n\"coord53\" -> \"coord49\"\n\"coord53\" -> \"coord51\"\n\"coord54\" -> \"coord63\"\n\"coord55\" -> \"coord63\"\n\"coord56\" -> \"coord61\"\n\"coord57\" -> \"coord62\"\n\"coord61\" -> \"coord59\"\n\"coord62\" -> \"coord60\"\n\"coord63\" -> \"coord58\"\n\"coord64\" -> \"coord56\"\n\"coord64\" -> \"coord54\"\n\"coord65\" -> \"coord55\"\n\"coord65\" -> \"coord57\"\n\"coord66\" -> \"coord6\"\n\"coord67\" -> \"coord81\"\n\"coord68\" -> \"coord81\"\n\"coord69\" -> \"coord79\"\n\"coord70\" -> \"coord80\"\n\"coord71\" -> \"coord79\"\n\"coord72\" -> \"coord80\"\n\"coord73\" -> \"coord78\"\n\"coord74\" -> \"coord76\"\n\"coord74\" -> \"coord518\"\n\"coord74\" -> \"coord519\"\n\"coord74\" -> \"coord522\"\n\"coord74\" -> \"coord523\"\n\"coord74\" -> \"coord526\"\n\"coord74\" -> \"coord527\"\n\"coord74\" -> \"coord560\"\n\"coord74\" -> \"coord561\"\n\"coord74\" -> \"coord564\"\n\"coord74\" -> \"coord565\"\n\"coord74\" -> \"coord584\"\n\"coord74\" -> \"coord585\"\n\"coord74\" -> \"coord588\"\n\"coord74\" -> \"coord589\"\n\"coord74\" -> \"coord608\"\n\"coord74\" -> \"coord609\"\n\"coord74\" -> \"coord612\"\n\"coord74\" -> \"coord613\"\n\"coord75\" -> \"coord77\"\n\"coord75\" -> \"coord520\"\n\"coord75\" -> \"coord521\"\n\"coord75\" -> \"coord524\"\n\"coord75\" -> \"coord525\"\n\"coord75\" -> \"coord528\"\n\"coord75\" -> \"coord529\"\n\"coord75\" -> \"coord562\"\n\"coord75\" -> \"coord563\"\n\"coord75\" -> \"coord566\"\n\"coord75\" -> \"coord567\"\n\"coord75\" -> \"coord586\"\n\"coord75\" -> \"coord587\"\n\"coord75\" -> \"coord590\"\n\"coord75\" -> \"coord591\"\n\"coord75\" -> \"coord610\"\n\"coord75\" -> \"coord611\"\n\"coord75\" -> \"coord614\"\n\"coord75\" -> \"coord615\"\n\"coord76\" -> \"coord71\"\n\"coord77\" -> \"coord72\"\n\"coord78\" -> \"coord69\"\n\"coord78\" -> \"coord70\"\n\"coord79\" -> \"coord67\"\n\"coord80\" -> \"coord68\"\n\"coord81\" -> \"coord13\"\n\"coord82\" -> \"coord91\"\n\"coord83\" -> \"coord92\"\n\"coord85\" -> \"coord86\"\n\"coord86\" -> \"coord11\"\n\"coord87\" -> \"coord106\"\n\"coord88\" -> \"coord251\"\n\"coord89\" -> \"coord104\"\n\"coord90\" -> \"coord103\"\n\"coord91\" -> \"coord87\"\n\"coord91\" -> \"coord89\"\n\"coord92\" -> \"coord88\"\n\"coord92\" -> \"coord90\"\n\"coord93\" -> \"coord98\"\n\"coord94\" -> \"coord98\"\n\"coord95\" -> \"coord99\"\n\"coord96\" -> \"coord99\"\n\"coord98\" -> \"coord95\"\n\"coord99\" -> \"coord84\"\n\"coord101\" -> \"coord104\"\n\"coord102\" -> \"coord105\"\n\"coord103\" -> \"coord101\"\n\"coord103\" -> \"coord102\"\n\"coord104\" -> \"coord96\"\n\"coord105\" -> \"coord97\"\n\"coord106\" -> \"coord93\"\n\"coord107\" -> \"coord82\"\n\"coord107\" -> \"coord83\"\n\"coord108\" -> \"coord315\"\n\"coord109\" -> \"coord304\"\n\"coord110\" -> \"coord124\"\n\"coord111\" -> \"coord125\"\n\"coord112\" -> \"coord108\"\n\"coord112\" -> \"coord110\"\n\"coord113\" -> \"coord109\"\n\"coord113\" -> \"coord111\"\n\"coord114\" -> \"coord123\"\n\"coord115\" -> \"coord123\"\n\"coord116\" -> \"coord121\"\n\"coord117\" -> \"coord122\"\n\"coord121\" -> \"coord120\"\n\"coord122\" -> \"coord119\"\n\"coord123\" -> \"coord118\"\n\"coord124\" -> \"coord114\"\n\"coord124\" -> \"coord116\"\n\"coord125\" -> \"coord117\"\n\"coord125\" -> \"coord115\"\n\"coord126\" -> \"coord7\"\n\"coord127\" -> \"coord141\"\n\"coord128\" -> \"coord141\"\n\"coord129\" -> \"coord139\"\n\"coord130\" -> \"coord140\"\n\"coord131\" -> \"coord139\"\n\"coord132\" -> \"coord140\"\n\"coord133\" -> \"coord138\"\n\"coord134\" -> \"coord137\"\n\"coord134\" -> \"coord534\"\n\"coord134\" -> \"coord535\"\n\"coord134\" -> \"coord538\"\n\"coord134\" -> \"coord539\"\n\"coord134\" -> \"coord542\"\n\"coord134\" -> \"coord543\"\n\"coord134\" -> \"coord572\"\n\"coord134\" -> \"coord573\"\n\"coord134\" -> \"coord576\"\n\"coord134\" -> \"coord577\"\n\"coord134\" -> \"coord596\"\n\"coord134\" -> \"coord597\"\n\"coord134\" -> \"coord600\"\n\"coord134\" -> \"coord601\"\n\"coord134\" -> \"coord620\"\n\"coord134\" -> \"coord621\"\n\"coord134\" -> \"coord624\"\n\"coord134\" -> \"coord625\"\n\"coord135\" -> \"coord136\"\n\"coord135\" -> \"coord536\"\n\"coord135\" -> \"coord537\"\n\"coord135\" -> \"coord540\"\n\"coord135\" -> \"coord541\"\n\"coord135\" -> \"coord544\"\n\"coord135\" -> \"coord545\"\n\"coord135\" -> \"coord574\"\n\"coord135\" -> \"coord575\"\n\"coord135\" -> \"coord578\"\n\"coord135\" -> \"coord579\"\n\"coord135\" -> \"coord598\"\n\"coord135\" -> \"coord599\"\n\"coord135\" -> \"coord602\"\n\"coord135\" -> \"coord603\"\n\"coord135\" -> \"coord622\"\n\"coord135\" -> \"coord623\"\n\"coord135\" -> \"coord626\"\n\"coord135\" -> \"coord627\"\n\"coord136\" -> \"coord131\"\n\"coord137\" -> \"coord132\"\n\"coord138\" -> \"coord130\"\n\"coord138\" -> \"coord129\"\n\"coord139\" -> \"coord127\"\n\"coord140\" -> \"coord128\"\n\"coord141\" -> \"coord21\"\n\"coord142\" -> \"coord151\"\n\"coord143\" -> \"coord152\"\n\"coord145\" -> \"coord146\"\n\"coord146\" -> \"coord19\"\n\"coord147\" -> \"coord252\"\n\"coord148\" -> \"coord166\"\n\"coord149\" -> \"coord163\"\n\"coord150\" -> \"coord164\"\n\"coord151\" -> \"coord147\"\n\"coord151\" -> \"coord149\"\n\"coord152\" -> \"coord148\"\n\"coord152\" -> \"coord150\"\n\"coord153\" -> \"coord158\"\n\"coord154\" -> \"coord158\"\n\"coord155\" -> \"coord159\"\n\"coord156\" -> \"coord159\"\n\"coord158\" -> \"coord155\"\n\"coord159\" -> \"coord144\"\n\"coord161\" -> \"coord164\"\n\"coord162\" -> \"coord165\"\n\"coord163\" -> \"coord161\"\n\"coord163\" -> \"coord162\"\n\"coord164\" -> \"coord156\"\n\"coord165\" -> \"coord157\"\n\"coord166\" -> \"coord154\"\n\"coord167\" -> \"coord143\"\n\"coord167\" -> \"coord142\"\n\"coord168\" -> \"coord306\"\n\"coord169\" -> \"coord308\"\n\"coord170\" -> \"coord181\"\n\"coord171\" -> \"coord182\"\n\"coord172\" -> \"coord168\"\n\"coord172\" -> \"coord170\"\n\"coord173\" -> \"coord169\"\n\"coord173\" -> \"coord171\"\n\"coord175\" -> \"coord176\"\n\"coord176\" -> \"coord29\"\n\"coord177\" -> \"coord205\"\n\"coord178\" -> \"coord206\"\n\"coord179\" -> \"coord199\"\n\"coord180\" -> \"coord200\"\n\"coord181\" -> \"coord177\"\n\"coord181\" -> \"coord179\"\n\"coord182\" -> \"coord178\"\n\"coord182\" -> \"coord180\"\n\"coord183\" -> \"coord188\"\n\"coord184\" -> \"coord188\"\n\"coord185\" -> \"coord189\"\n\"coord186\" -> \"coord189\"\n\"coord188\" -> \"coord185\"\n\"coord189\" -> \"coord174\"\n\"coord192\" -> \"coord203\"\n\"coord193\" -> \"coord203\"\n\"coord194\" -> \"coord204\"\n\"coord195\" -> \"coord204\"\n\"coord196\" -> \"coord202\"\n\"coord197\" -> \"coord201\"\n\"coord198\" -> \"coord201\"\n\"coord199\" -> \"coord197\"\n\"coord199\" -> \"coord193\"\n\"coord200\" -> \"coord198\"\n\"coord200\" -> \"coord195\"\n\"coord201\" -> \"coord196\"\n\"coord202\" -> \"coord192\"\n\"coord202\" -> \"coord194\"\n\"coord203\" -> \"coord187\"\n\"coord204\" -> \"coord186\"\n\"coord205\" -> \"coord183\"\n\"coord206\" -> \"coord184\"\n\"coord207\" -> \"coord29\"\n\"coord208\" -> \"coord212\"\n\"coord209\" -> \"coord213\"\n\"coord210\" -> \"coord212\"\n\"coord211\" -> \"coord213\"\n\"coord212\" -> \"coord43\"\n\"coord213\" -> \"coord44\"\n\"coord214\" -> \"coord243\"\n\"coord216\" -> \"coord227\"\n\"coord217\" -> \"coord228\"\n\"coord218\" -> \"coord227\"\n\"coord219\" -> \"coord228\"\n\"coord220\" -> \"coord237\"\n\"coord220\" -> \"coord550\"\n\"coord220\" -> \"coord551\"\n\"coord220\" -> \"coord556\"\n\"coord220\" -> \"coord557\"\n\"coord221\" -> \"coord241\"\n\"coord221\" -> \"coord554\"\n\"coord221\" -> \"coord555\"\n\"coord221\" -> \"coord558\"\n\"coord221\" -> \"coord559\"\n\"coord222\" -> \"coord237\"\n\"coord223\" -> \"coord242\"\n\"coord224\" -> \"coord238\"\n\"coord225\" -> \"coord241\"\n\"coord226\" -> \"coord242\"\n\"coord227\" -> \"coord210\"\n\"coord228\" -> \"coord211\"\n\"coord229\" -> \"coord239\"\n\"coord230\" -> \"coord240\"\n\"coord231\" -> \"coord232\"\n\"coord232\" -> \"coord229\"\n\"coord232\" -> \"coord230\"\n\"coord233\" -> \"coord236\"\n\"coord234\" -> \"coord235\"\n\"coord235\" -> \"coord220\"\n\"coord235\" -> \"coord221\"\n\"coord236\" -> \"coord222\"\n\"coord236\" -> \"coord223\"\n\"coord237\" -> \"coord224\"\n\"coord238\" -> \"coord225\"\n\"coord238\" -> \"coord226\"\n\"coord239\" -> \"coord216\"\n\"coord240\" -> \"coord217\"\n\"coord241\" -> \"coord218\"\n\"coord242\" -> \"coord219\"\n\"coord243\" -> \"coord231\"\n\"coord243\" -> \"coord233\"\n\"coord244\" -> \"coord45\"\n\"coord245\" -> \"coord247\"\n\"coord247\" -> \"coord246\"\n\"coord251\" -> \"coord250\"\n\"coord252\" -> \"coord250\"\n\"coord253\" -> \"coord254\"\n\"coord254\" -> \"coord11\"\n\"coord255\" -> \"coord256\"\n\"coord256\" -> \"coord19\"\n\"coord257\" -> \"coord258\"\n\"coord258\" -> \"coord11\"\n\"coord259\" -> \"coord260\"\n\"coord260\" -> \"coord19\"\n\"coord261\" -> \"coord262\"\n\"coord262\" -> \"coord11\"\n\"coord263\" -> \"coord264\"\n\"coord264\" -> \"coord19\"\n\"coord265\" -> \"coord266\"\n\"coord266\" -> \"coord11\"\n\"coord267\" -> \"coord268\"\n\"coord268\" -> \"coord19\"\n\"coord269\" -> \"coord270\"\n\"coord270\" -> \"coord11\"\n\"coord271\" -> \"coord272\"\n\"coord272\" -> \"coord19\"\n\"coord273\" -> \"coord274\"\n\"coord274\" -> \"coord11\"\n\"coord275\" -> \"coord276\"\n\"coord276\" -> \"coord19\"\n\"coord277\" -> \"coord278\"\n\"coord278\" -> \"coord11\"\n\"coord279\" -> \"coord280\"\n\"coord280\" -> \"coord19\"\n\"coord291\" -> \"coord292\"\n\"coord292\" -> \"coord29\"\n\"coord293\" -> \"coord294\"\n\"coord294\" -> \"coord31\"\n\"coord295\" -> \"coord296\"\n\"coord296\" -> \"coord37\"\n\"coord297\" -> \"coord298\"\n\"coord298\" -> \"coord39\"\n\"coord299\" -> \"coord300\"\n\"coord300\" -> \"coord41\"\n\"coord302\" -> \"coord301\"\n\"coord304\" -> \"coord303\"\n\"coord306\" -> \"coord305\"\n\"coord308\" -> \"coord307\"\n\"coord309\" -> \"coord310\"\n\"coord310\" -> \"coord208\"\n\"coord311\" -> \"coord312\"\n\"coord312\" -> \"coord209\"\n\"coord314\" -> \"coord246\"\n\"coord314\" -> \"coord313\"\n\"coord315\" -> \"coord246\"\n\"coord315\" -> \"coord313\"\n\"coord316\" -> \"coord317\"\n\"coord317\" -> \"coord246\"\n\"coord318\" -> \"coord319\"\n\"coord319\" -> \"coord6\"\n\"coord320\" -> \"coord321\"\n\"coord321\" -> \"coord7\"\n\"coord322\" -> \"coord323\"\n\"coord323\" -> \"coord11\"\n\"coord324\" -> \"coord325\"\n\"coord325\" -> \"coord19\"\n\"coord326\" -> \"coord327\"\n\"coord327\" -> \"coord11\"\n\"coord328\" -> \"coord329\"\n\"coord329\" -> \"coord19\"\n\"coord330\" -> \"coord331\"\n\"coord331\" -> \"coord11\"\n\"coord332\" -> \"coord333\"\n\"coord333\" -> \"coord19\"\n\"coord334\" -> \"coord335\"\n\"coord335\" -> \"coord11\"\n\"coord336\" -> \"coord337\"\n\"coord337\" -> \"coord19\"\n\"coord338\" -> \"coord339\"\n\"coord339\" -> \"coord11\"\n\"coord340\" -> \"coord341\"\n\"coord341\" -> \"coord19\"\n\"coord342\" -> \"coord343\"\n\"coord343\" -> \"coord11\"\n\"coord344\" -> \"coord345\"\n\"coord345\" -> \"coord19\"\n\"coord346\" -> \"coord347\"\n\"coord347\" -> \"coord11\"\n\"coord348\" -> \"coord349\"\n\"coord349\" -> \"coord19\"\n\"coord350\" -> \"coord351\"\n\"coord351\" -> \"coord11\"\n\"coord352\" -> \"coord353\"\n\"coord353\" -> \"coord19\"\n\"coord354\" -> \"coord355\"\n\"coord355\" -> \"coord6\"\n\"coord356\" -> \"coord357\"\n\"coord356\" -> \"coord568\"\n\"coord356\" -> \"coord569\"\n\"coord356\" -> \"coord570\"\n\"coord356\" -> \"coord571\"\n\"coord357\" -> \"coord13\"\n\"coord358\" -> \"coord359\"\n\"coord359\" -> \"coord7\"\n\"coord360\" -> \"coord361\"\n\"coord360\" -> \"coord580\"\n\"coord360\" -> \"coord581\"\n\"coord360\" -> \"coord582\"\n\"coord360\" -> \"coord583\"\n\"coord361\" -> \"coord21\"\n\"coord362\" -> \"coord363\"\n\"coord362\" -> \"coord632\"\n\"coord363\" -> \"coord11\"\n\"coord364\" -> \"coord365\"\n\"coord364\" -> \"coord633\"\n\"coord365\" -> \"coord19\"\n\"coord366\" -> \"coord367\"\n\"coord366\" -> \"coord634\"\n\"coord367\" -> \"coord11\"\n\"coord368\" -> \"coord369\"\n\"coord369\" -> \"coord19\"\n\"coord370\" -> \"coord371\"\n\"coord370\" -> \"coord635\"\n\"coord371\" -> \"coord11\"\n\"coord372\" -> \"coord373\"\n\"coord373\" -> \"coord19\"\n\"coord374\" -> \"coord375\"\n\"coord375\" -> \"coord11\"\n\"coord376\" -> \"coord377\"\n\"coord377\" -> \"coord19\"\n\"coord378\" -> \"coord379\"\n\"coord378\" -> \"coord636\"\n\"coord379\" -> \"coord11\"\n\"coord380\" -> \"coord381\"\n\"coord381\" -> \"coord19\"\n\"coord382\" -> \"coord383\"\n\"coord383\" -> \"coord11\"\n\"coord384\" -> \"coord385\"\n\"coord385\" -> \"coord19\"\n\"coord386\" -> \"coord387\"\n\"coord386\" -> \"coord637\"\n\"coord387\" -> \"coord11\"\n\"coord388\" -> \"coord389\"\n\"coord389\" -> \"coord19\"\n\"coord390\" -> \"coord391\"\n\"coord391\" -> \"coord11\"\n\"coord392\" -> \"coord393\"\n\"coord393\" -> \"coord19\"\n\"coord394\" -> \"coord395\"\n\"coord395\" -> \"coord6\"\n\"coord396\" -> \"coord397\"\n\"coord396\" -> \"coord592\"\n\"coord396\" -> \"coord593\"\n\"coord396\" -> \"coord594\"\n\"coord396\" -> \"coord595\"\n\"coord397\" -> \"coord13\"\n\"coord398\" -> \"coord399\"\n\"coord399\" -> \"coord7\"\n\"coord400\" -> \"coord401\"\n\"coord400\" -> \"coord604\"\n\"coord400\" -> \"coord605\"\n\"coord400\" -> \"coord606\"\n\"coord400\" -> \"coord607\"\n\"coord401\" -> \"coord21\"\n\"coord402\" -> \"coord403\"\n\"coord402\" -> \"coord638\"\n\"coord403\" -> \"coord11\"\n\"coord404\" -> \"coord405\"\n\"coord404\" -> \"coord639\"\n\"coord405\" -> \"coord19\"\n\"coord406\" -> \"coord407\"\n\"coord406\" -> \"coord640\"\n\"coord407\" -> \"coord11\"\n\"coord408\" -> \"coord409\"\n\"coord408\" -> \"coord641\"\n\"coord409\" -> \"coord19\"\n\"coord410\" -> \"coord411\"\n\"coord410\" -> \"coord642\"\n\"coord411\" -> \"coord11\"\n\"coord412\" -> \"coord413\"\n\"coord412\" -> \"coord643\"\n\"coord413\" -> \"coord19\"\n\"coord414\" -> \"coord415\"\n\"coord414\" -> \"coord644\"\n\"coord415\" -> \"coord11\"\n\"coord416\" -> \"coord417\"\n\"coord416\" -> \"coord645\"\n\"coord417\" -> \"coord19\"\n\"coord418\" -> \"coord419\"\n\"coord418\" -> \"coord646\"\n\"coord419\" -> \"coord11\"\n\"coord420\" -> \"coord421\"\n\"coord420\" -> \"coord647\"\n\"coord421\" -> \"coord19\"\n\"coord422\" -> \"coord423\"\n\"coord422\" -> \"coord648\"\n\"coord423\" -> \"coord11\"\n\"coord424\" -> \"coord425\"\n\"coord424\" -> \"coord649\"\n\"coord425\" -> \"coord19\"\n\"coord426\" -> \"coord427\"\n\"coord426\" -> \"coord650\"\n\"coord427\" -> \"coord11\"\n\"coord428\" -> \"coord429\"\n\"coord428\" -> \"coord651\"\n\"coord429\" -> \"coord19\"\n\"coord430\" -> \"coord431\"\n\"coord431\" -> \"coord11\"\n\"coord432\" -> \"coord433\"\n\"coord432\" -> \"coord652\"\n\"coord433\" -> \"coord19\"\n\"coord434\" -> \"coord435\"\n\"coord435\" -> \"coord6\"\n\"coord436\" -> \"coord437\"\n\"coord436\" -> \"coord616\"\n\"coord436\" -> \"coord617\"\n\"coord436\" -> \"coord618\"\n\"coord436\" -> \"coord619\"\n\"coord437\" -> \"coord13\"\n\"coord438\" -> \"coord439\"\n\"coord439\" -> \"coord7\"\n\"coord440\" -> \"coord441\"\n\"coord440\" -> \"coord628\"\n\"coord440\" -> \"coord629\"\n\"coord440\" -> \"coord630\"\n\"coord440\" -> \"coord631\"\n\"coord441\" -> \"coord21\"\n\"coord442\" -> \"coord443\"\n\"coord442\" -> \"coord653\"\n\"coord443\" -> \"coord11\"\n\"coord444\" -> \"coord445\"\n\"coord444\" -> \"coord654\"\n\"coord445\" -> \"coord19\"\n\"coord446\" -> \"coord447\"\n\"coord446\" -> \"coord655\"\n\"coord447\" -> \"coord11\"\n\"coord448\" -> \"coord449\"\n\"coord449\" -> \"coord19\"\n\"coord450\" -> \"coord451\"\n\"coord450\" -> \"coord656\"\n\"coord451\" -> \"coord11\"\n\"coord452\" -> \"coord453\"\n\"coord453\" -> \"coord19\"\n\"coord454\" -> \"coord455\"\n\"coord454\" -> \"coord657\"\n\"coord455\" -> \"coord11\"\n\"coord456\" -> \"coord457\"\n\"coord457\" -> \"coord19\"\n\"coord458\" -> \"coord459\"\n\"coord459\" -> \"coord11\"\n\"coord460\" -> \"coord461\"\n\"coord461\" -> \"coord19\"\n\"coord462\" -> \"coord463\"\n\"coord463\" -> \"coord11\"\n\"coord464\" -> \"coord465\"\n\"coord465\" -> \"coord19\"\n\"coord466\" -> \"coord467\"\n\"coord467\" -> \"coord11\"\n\"coord468\" -> \"coord469\"\n\"coord469\" -> \"coord19\"\n\"coord470\" -> \"coord471\"\n\"coord471\" -> \"coord11\"\n\"coord472\" -> \"coord473\"\n\"coord473\" -> \"coord19\"\n\"coord474\" -> \"coord49\"\n\"coord475\" -> \"coord49\"\n\"coord476\" -> \"coord477\"\n\"coord477\" -> \"coord1\"\n\"coord478\" -> \"coord59\"\n\"coord479\" -> \"coord59\"\n\"coord480\" -> \"coord60\"\n\"coord481\" -> \"coord60\"\n\"coord482\" -> \"coord49\"\n\"coord483\" -> \"coord59\"\n\"coord484\" -> \"coord59\"\n\"coord485\" -> \"coord60\"\n\"coord486\" -> \"coord60\"\n\"coord487\" -> \"coord49\"\n\"coord488\" -> \"coord49\"\n\"coord489\" -> \"coord59\"\n\"coord490\" -> \"coord59\"\n\"coord491\" -> \"coord60\"\n\"coord492\" -> \"coord60\"\n\"coord493\" -> \"coord108\"\n\"coord494\" -> \"coord108\"\n\"coord495\" -> \"coord496\"\n\"coord496\" -> \"coord2\"\n\"coord497\" -> \"coord119\"\n\"coord498\" -> \"coord119\"\n\"coord499\" -> \"coord120\"\n\"coord500\" -> \"coord120\"\n\"coord501\" -> \"coord108\"\n\"coord502\" -> \"coord119\"\n\"coord503\" -> \"coord119\"\n\"coord504\" -> \"coord120\"\n\"coord505\" -> \"coord120\"\n\"coord506\" -> \"coord108\"\n\"coord507\" -> \"coord108\"\n\"coord508\" -> \"coord119\"\n\"coord509\" -> \"coord119\"\n\"coord510\" -> \"coord120\"\n\"coord511\" -> \"coord120\"\n\"coord512\" -> \"coord192\"\n\"coord513\" -> \"coord192\"\n\"coord514\" -> \"coord515\"\n\"coord515\" -> \"coord3\"\n\"coord516\" -> \"coord193\"\n\"coord517\" -> \"coord193\"\n\"coord518\" -> \"coord13\"\n\"coord519\" -> \"coord13\"\n\"coord520\" -> \"coord13\"\n\"coord521\" -> \"coord13\"\n\"coord522\" -> \"coord13\"\n\"coord523\" -> \"coord13\"\n\"coord524\" -> \"coord13\"\n\"coord525\" -> \"coord13\"\n\"coord526\" -> \"coord13\"\n\"coord527\" -> \"coord13\"\n\"coord528\" -> \"coord13\"\n\"coord529\" -> \"coord13\"\n\"coord530\" -> \"coord88\"\n\"coord531\" -> \"coord88\"\n\"coord532\" -> \"coord97\"\n\"coord533\" -> \"coord97\"\n\"coord534\" -> \"coord21\"\n\"coord535\" -> \"coord21\"\n\"coord536\" -> \"coord21\"\n\"coord537\" -> \"coord21\"\n\"coord538\" -> \"coord21\"\n\"coord539\" -> \"coord21\"\n\"coord540\" -> \"coord21\"\n\"coord541\" -> \"coord21\"\n\"coord542\" -> \"coord21\"\n\"coord543\" -> \"coord21\"\n\"coord544\" -> \"coord21\"\n\"coord545\" -> \"coord21\"\n\"coord546\" -> \"coord147\"\n\"coord547\" -> \"coord147\"\n\"coord548\" -> \"coord157\"\n\"coord549\" -> \"coord157\"\n\"coord550\" -> \"coord45\"\n\"coord551\" -> \"coord45\"\n\"coord552\" -> \"coord553\"\n\"coord553\" -> \"coord45\"\n\"coord554\" -> \"coord45\"\n\"coord555\" -> \"coord45\"\n\"coord556\" -> \"coord45\"\n\"coord557\" -> \"coord45\"\n\"coord558\" -> \"coord45\"\n\"coord559\" -> \"coord45\"\n\"coord560\" -> \"coord356\"\n\"coord561\" -> \"coord356\"\n\"coord562\" -> \"coord356\"\n\"coord563\" -> \"coord356\"\n\"coord564\" -> \"coord356\"\n\"coord565\" -> \"coord356\"\n\"coord566\" -> \"coord356\"\n\"coord567\" -> \"coord356\"\n\"coord568\" -> \"coord88\"\n\"coord569\" -> \"coord88\"\n\"coord570\" -> \"coord97\"\n\"coord571\" -> \"coord97\"\n\"coord572\" -> \"coord360\"\n\"coord573\" -> \"coord360\"\n\"coord574\" -> \"coord360\"\n\"coord575\" -> \"coord360\"\n\"coord576\" -> \"coord360\"\n\"coord577\" -> \"coord360\"\n\"coord578\" -> \"coord360\"\n\"coord579\" -> \"coord360\"\n\"coord580\" -> \"coord147\"\n\"coord581\" -> \"coord147\"\n\"coord582\" -> \"coord157\"\n\"coord583\" -> \"coord157\"\n\"coord584\" -> \"coord396\"\n\"coord585\" -> \"coord396\"\n\"coord586\" -> \"coord396\"\n\"coord587\" -> \"coord396\"\n\"coord588\" -> \"coord396\"\n\"coord589\" -> \"coord396\"\n\"coord590\" -> \"coord396\"\n\"coord591\" -> \"coord396\"\n\"coord592\" -> \"coord88\"\n\"coord593\" -> \"coord88\"\n\"coord594\" -> \"coord97\"\n\"coord595\" -> \"coord97\"\n\"coord596\" -> \"coord400\"\n\"coord597\" -> \"coord400\"\n\"coord598\" -> \"coord400\"\n\"coord599\" -> \"coord400\"\n\"coord600\" -> \"coord400\"\n\"coord601\" -> \"coord400\"\n\"coord602\" -> \"coord400\"\n\"coord603\" -> \"coord400\"\n\"coord604\" -> \"coord147\"\n\"coord605\" -> \"coord147\"\n\"coord606\" -> \"coord157\"\n\"coord607\" -> \"coord157\"\n\"coord608\" -> \"coord436\"\n\"coord609\" -> \"coord436\"\n\"coord610\" -> \"coord436\"\n\"coord611\" -> \"coord436\"\n\"coord612\" -> \"coord436\"\n\"coord613\" -> \"coord436\"\n\"coord614\" -> \"coord436\"\n\"coord615\" -> \"coord436\"\n\"coord616\" -> \"coord88\"\n\"coord617\" -> \"coord88\"\n\"coord618\" -> \"coord97\"\n\"coord619\" -> \"coord97\"\n\"coord620\" -> \"coord440\"\n\"coord621\" -> \"coord440\"\n\"coord622\" -> \"coord440\"\n\"coord623\" -> \"coord440\"\n\"coord624\" -> \"coord440\"\n\"coord625\" -> \"coord440\"\n\"coord626\" -> \"coord440\"\n\"coord627\" -> \"coord440\"\n\"coord628\" -> \"coord147\"\n\"coord629\" -> \"coord147\"\n\"coord630\" -> \"coord157\"\n\"coord631\" -> \"coord157\"\n\"coord632\" -> \"coord11\"\n\"coord633\" -> \"coord19\"\n\"coord634\" -> \"coord253\"\n\"coord635\" -> \"coord257\"\n\"coord636\" -> \"coord261\"\n\"coord637\" -> \"coord265\"\n\"coord638\" -> \"coord11\"\n\"coord639\" -> \"coord19\"\n\"coord640\" -> \"coord253\"\n\"coord641\" -> \"coord255\"\n\"coord642\" -> \"coord257\"\n\"coord643\" -> \"coord259\"\n\"coord644\" -> \"coord269\"\n\"coord645\" -> \"coord263\"\n\"coord646\" -> \"coord273\"\n\"coord647\" -> \"coord267\"\n\"coord648\" -> \"coord277\"\n\"coord649\" -> \"coord271\"\n\"coord650\" -> \"coord261\"\n\"coord651\" -> \"coord275\"\n\"coord652\" -> \"coord279\"\n\"coord653\" -> \"coord11\"\n\"coord654\" -> \"coord19\"\n\"coord655\" -> \"coord253\"\n\"coord656\" -> \"coord257\"\n\"coord657\" -> \"coord265\"\n{\nrank=same\n\"coord8\"->\"coord9\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord16\"->\"coord17\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord26\"->\"coord27\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord24\"->\"coord29\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord6\"->\"coord7\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord33\"->\"coord35\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord31\"->\"coord37\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord43\"->\"coord44\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord48\"->\"coord50\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord49\"->\"coord51\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord54\"->\"coord55\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord56\"->\"coord54\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord55\"->\"coord57\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord69\"->\"coord70\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord71\"->\"coord69\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord70\"->\"coord72\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord67\"->\"coord68\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord87\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord88\"->\"coord90\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord93\"->\"coord94\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord95\"->\"coord96\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord102\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord82\"->\"coord83\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord108\"->\"coord110\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord109\"->\"coord111\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord115\"->\"coord114\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord114\"->\"coord116\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord117\"->\"coord115\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord130\"->\"coord129\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord129\"->\"coord131\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord132\"->\"coord130\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord128\"->\"coord127\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord147\"->\"coord149\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord148\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord153\"->\"coord154\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord155\"->\"coord156\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord162\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord143\"->\"coord142\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord168\"->\"coord170\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord169\"->\"coord171\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord177\"->\"coord179\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord178\"->\"coord180\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord183\"->\"coord184\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord185\"->\"coord186\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord198\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord198\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord194\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord194\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord208\"->\"coord210\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord209\"->\"coord211\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord216\"->\"coord218\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord217\"->\"coord219\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord229\"->\"coord230\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord222\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord222\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord226\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord226\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord231\"->\"coord233\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\nsubgraph clusterCF {label = \"Control Graph\";\n\"cntrl1\"[label=\"Kernel(1)\"];\n\"cntrl2\"[label=\"LoadVGPR Value: Float(2)\"];\n\"cntrl24\"[label=\"LoadVGPR Value: Float(24)\"];\n\"cntrl29\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29)\"];\n\"cntrl35\"[label=\"Assign VGPR Convert(DataFlowTag(39)NA)H(35)\"];\n\"cntrl37\"[label=\"StoreTiled Value: Halfx2(37)\"];\n\"cntrl39\"[label=\"ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39)\"];\n\"cntrl40\"[label=\"Assign SGPR 0:U32(40)\"];\n\"cntrl41\"[label=\"Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41)\"];\n\"cntrl42\"[label=\"Initialize(42)\",shape=box];\n\"cntrl44\"[label=\"Assign ACCVGPR 0.00000:S(44)\"];\n\"cntrl47\"[label=\"SetCoordinate(47)\"];\n\"cntrl49\"[label=\"LoadLDSTile{Value: Halfx2}(49)\"];\n\"cntrl50\"[label=\"Body(50)\",shape=box];\n\"cntrl52\"[label=\"SetCoordinate(52)\"];\n\"cntrl54\"[label=\"LoadLDSTile{Value: Halfx2}(54)\"];\n\"cntrl55\"[label=\"Body(55)\",shape=box];\n\"cntrl57\"[label=\"Multiply(57)\"];\n\"cntrl58\"[label=\"SetCoordinate(58)\"];\n\"cntrl60\"[label=\"LoadLDSTile{Value: Halfx2}(60)\"];\n\"cntrl61\"[label=\"Body(61)\",shape=box];\n\"cntrl62\"[label=\"SetCoordinate(62)\"];\n\"cntrl64\"[label=\"LoadLDSTile{Value: Halfx2}(64)\"];\n\"cntrl65\"[label=\"Body(65)\",shape=box];\n\"cntrl66\"[label=\"Multiply(66)\"];\n\"cntrl67\"[label=\"SetCoordinate(67)\"];\n\"cntrl69\"[label=\"LoadLDSTile{Value: Halfx2}(69)\"];\n\"cntrl70\"[label=\"Body(70)\",shape=box];\n\"cntrl71\"[label=\"SetCoordinate(71)\"];\n\"cntrl73\"[label=\"LoadLDSTile{Value: Halfx2}(73)\"];\n\"cntrl74\"[label=\"Body(74)\",shape=box];\n\"cntrl75\"[label=\"Multiply(75)\"];\n\"cntrl76\"[label=\"SetCoordinate(76)\"];\n\"cntrl78\"[label=\"LoadLDSTile{Value: Halfx2}(78)\"];\n\"cntrl79\"[label=\"Body(79)\",shape=box];\n\"cntrl80\"[label=\"SetCoordinate(80)\"];\n\"cntrl82\"[label=\"LoadLDSTile{Value: Halfx2}(82)\"];\n\"cntrl83\"[label=\"Body(83)\",shape=box];\n\"cntrl84\"[label=\"Multiply(84)\"];\n\"cntrl85\"[label=\"SetCoordinate(85)\"];\n\"cntrl87\"[label=\"LoadLDSTile{Value: Halfx2}(87)\"];\n\"cntrl88\"[label=\"Body(88)\",shape=box];\n\"cntrl89\"[label=\"SetCoordinate(89)\"];\n\"cntrl91\"[label=\"LoadLDSTile{Value: Halfx2}(91)\"];\n\"cntrl92\"[label=\"Body(92)\",shape=box];\n\"cntrl93\"[label=\"Multiply(93)\"];\n\"cntrl94\"[label=\"SetCoordinate(94)\"];\n\"cntrl96\"[label=\"LoadLDSTile{Value: Halfx2}(96)\"];\n\"cntrl97\"[label=\"Body(97)\",shape=box];\n\"cntrl98\"[label=\"SetCoordinate(98)\"];\n\"cntrl100\"[label=\"LoadLDSTile{Value: Halfx2}(100)\"];\n\"cntrl101\"[label=\"Body(101)\",shape=box];\n\"cntrl102\"[label=\"Multiply(102)\"];\n\"cntrl103\"[label=\"SetCoordinate(103)\"];\n\"cntrl105\"[label=\"LoadLDSTile{Value: Halfx2}(105)\"];\n\"cntrl106\"[label=\"Body(106)\",shape=box];\n\"cntrl107\"[label=\"SetCoordinate(107)\"];\n\"cntrl109\"[label=\"LoadLDSTile{Value: Halfx2}(109)\"];\n\"cntrl110\"[label=\"Body(110)\",shape=box];\n\"cntrl111\"[label=\"Multiply(111)\"];\n\"cntrl112\"[label=\"SetCoordinate(112)\"];\n\"cntrl114\"[label=\"LoadLDSTile{Value: Halfx2}(114)\"];\n\"cntrl115\"[label=\"Body(115)\",shape=box];\n\"cntrl116\"[label=\"SetCoordinate(116)\"];\n\"cntrl118\"[label=\"LoadLDSTile{Value: Halfx2}(118)\"];\n\"cntrl119\"[label=\"Body(119)\",shape=box];\n\"cntrl120\"[label=\"Multiply(120)\"];\n\"cntrl177\"[label=\"ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177)\"];\n\"cntrl185\"[label=\"NOP(185)\"];\n\"cntrl186\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186)\"];\n\"cntrl187\"[label=\"Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187)\"];\n\"cntrl188\"[label=\"Assign VGPR Convert(DataFlowTag(297)NA)H(188)\"];\n\"cntrl189\"[label=\"StoreTiled Value: Halfx2(189)\"];\n\"cntrl190\"[label=\"LoadTiled Value: Halfx2(190)\"];\n\"cntrl191\"[label=\"Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191)\"];\n\"cntrl194\"[label=\"Sequence(194)\",shape=box];\n\"cntrl203\"[label=\"Sequence(203)\",shape=box];\n\"cntrl217\"[label=\"ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217)\"];\n\"cntrl218\"[label=\"Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218)\"];\n\"cntrl219\"[label=\"Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219)\"];\n\"cntrl220\"[label=\"Initialize(220)\",shape=box];\n\"cntrl224\"[label=\"SetCoordinate(224)\"];\n\"cntrl225\"[label=\"LoadLDSTile{Value: Halfx2}(225)\"];\n\"cntrl226\"[label=\"SetCoordinate(226)\"];\n\"cntrl227\"[label=\"LoadLDSTile{Value: Halfx2}(227)\"];\n\"cntrl228\"[label=\"Multiply(228)\"];\n\"cntrl229\"[label=\"SetCoordinate(229)\"];\n\"cntrl230\"[label=\"LoadLDSTile{Value: Halfx2}(230)\"];\n\"cntrl231\"[label=\"SetCoordinate(231)\"];\n\"cntrl232\"[label=\"LoadLDSTile{Value: Halfx2}(232)\"];\n\"cntrl233\"[label=\"Multiply(233)\"];\n\"cntrl234\"[label=\"SetCoordinate(234)\"];\n\"cntrl235\"[label=\"LoadLDSTile{Value: Halfx2}(235)\"];\n\"cntrl236\"[label=\"SetCoordinate(236)\"];\n\"cntrl237\"[label=\"LoadLDSTile{Value: Halfx2}(237)\"];\n\"cntrl238\"[label=\"Multiply(238)\"];\n\"cntrl239\"[label=\"SetCoordinate(239)\"];\n\"cntrl240\"[label=\"LoadLDSTile{Value: Halfx2}(240)\"];\n\"cntrl241\"[label=\"SetCoordinate(241)\"];\n\"cntrl242\"[label=\"LoadLDSTile{Value: Halfx2}(242)\"];\n\"cntrl243\"[label=\"Multiply(243)\"];\n\"cntrl244\"[label=\"SetCoordinate(244)\"];\n\"cntrl245\"[label=\"LoadLDSTile{Value: Halfx2}(245)\"];\n\"cntrl246\"[label=\"SetCoordinate(246)\"];\n\"cntrl247\"[label=\"LoadLDSTile{Value: Halfx2}(247)\"];\n\"cntrl248\"[label=\"Multiply(248)\"];\n\"cntrl249\"[label=\"SetCoordinate(249)\"];\n\"cntrl250\"[label=\"LoadLDSTile{Value: Halfx2}(250)\"];\n\"cntrl251\"[label=\"SetCoordinate(251)\"];\n\"cntrl252\"[label=\"LoadLDSTile{Value: Halfx2}(252)\"];\n\"cntrl253\"[label=\"Multiply(253)\"];\n\"cntrl254\"[label=\"SetCoordinate(254)\"];\n\"cntrl255\"[label=\"LoadLDSTile{Value: Halfx2}(255)\"];\n\"cntrl256\"[label=\"SetCoordinate(256)\"];\n\"cntrl257\"[label=\"LoadLDSTile{Value: Halfx2}(257)\"];\n\"cntrl258\"[label=\"Multiply(258)\"];\n\"cntrl259\"[label=\"SetCoordinate(259)\"];\n\"cntrl260\"[label=\"LoadLDSTile{Value: Halfx2}(260)\"];\n\"cntrl261\"[label=\"SetCoordinate(261)\"];\n\"cntrl262\"[label=\"LoadLDSTile{Value: Halfx2}(262)\"];\n\"cntrl263\"[label=\"Multiply(263)\"];\n\"cntrl273\"[label=\"Body(273)\",shape=box];\n\"cntrl275\"[label=\"Body(275)\",shape=box];\n\"cntrl276\"[label=\"Sequence(276)\",shape=box];\n\"cntrl278\"[label=\"Body(278)\",shape=box];\n\"cntrl279\"[label=\"Sequence(279)\",shape=box];\n\"cntrl280\"[label=\"Body(280)\",shape=box];\n\"cntrl281\"[label=\"Sequence(281)\",shape=box];\n\"cntrl283\"[label=\"Body(283)\",shape=box];\n\"cntrl284\"[label=\"Sequence(284)\",shape=box];\n\"cntrl285\"[label=\"Body(285)\",shape=box];\n\"cntrl286\"[label=\"Sequence(286)\",shape=box];\n\"cntrl288\"[label=\"Body(288)\",shape=box];\n\"cntrl289\"[label=\"Sequence(289)\",shape=box];\n\"cntrl290\"[label=\"Body(290)\",shape=box];\n\"cntrl291\"[label=\"Sequence(291)\",shape=box];\n\"cntrl293\"[label=\"Body(293)\",shape=box];\n\"cntrl294\"[label=\"Sequence(294)\",shape=box];\n\"cntrl295\"[label=\"Body(295)\",shape=box];\n\"cntrl296\"[label=\"Sequence(296)\",shape=box];\n\"cntrl298\"[label=\"Body(298)\",shape=box];\n\"cntrl299\"[label=\"Sequence(299)\",shape=box];\n\"cntrl300\"[label=\"Body(300)\",shape=box];\n\"cntrl301\"[label=\"Sequence(301)\",shape=box];\n\"cntrl303\"[label=\"Body(303)\",shape=box];\n\"cntrl304\"[label=\"Sequence(304)\",shape=box];\n\"cntrl305\"[label=\"Body(305)\",shape=box];\n\"cntrl306\"[label=\"Sequence(306)\",shape=box];\n\"cntrl308\"[label=\"Body(308)\",shape=box];\n\"cntrl309\"[label=\"Sequence(309)\",shape=box];\n\"cntrl310\"[label=\"Body(310)\",shape=box];\n\"cntrl311\"[label=\"Sequence(311)\",shape=box];\n\"cntrl313\"[label=\"SetCoordinate(313)\"];\n\"cntrl314\"[label=\"SetCoordinate(314)\"];\n\"cntrl315\"[label=\"Body(315)\",shape=box];\n\"cntrl318\"[label=\"SetCoordinate(318)\"];\n\"cntrl323\"[label=\"SetCoordinate(323)\"];\n\"cntrl330\"[label=\"SetCoordinate(330)\"];\n\"cntrl331\"[label=\"LoadLDSTile{Value: Halfx2}(331)\"];\n\"cntrl332\"[label=\"SetCoordinate(332)\"];\n\"cntrl333\"[label=\"LoadLDSTile{Value: Halfx2}(333)\"];\n\"cntrl334\"[label=\"Multiply(334)\"];\n\"cntrl335\"[label=\"SetCoordinate(335)\"];\n\"cntrl336\"[label=\"LoadLDSTile{Value: Halfx2}(336)\"];\n\"cntrl337\"[label=\"SetCoordinate(337)\"];\n\"cntrl338\"[label=\"LoadLDSTile{Value: Halfx2}(338)\"];\n\"cntrl339\"[label=\"Multiply(339)\"];\n\"cntrl340\"[label=\"SetCoordinate(340)\"];\n\"cntrl341\"[label=\"LoadLDSTile{Value: Halfx2}(341)\"];\n\"cntrl342\"[label=\"SetCoordinate(342)\"];\n\"cntrl343\"[label=\"LoadLDSTile{Value: Halfx2}(343)\"];\n\"cntrl344\"[label=\"Multiply(344)\"];\n\"cntrl345\"[label=\"SetCoordinate(345)\"];\n\"cntrl346\"[label=\"LoadLDSTile{Value: Halfx2}(346)\"];\n\"cntrl347\"[label=\"SetCoordinate(347)\"];\n\"cntrl348\"[label=\"LoadLDSTile{Value: Halfx2}(348)\"];\n\"cntrl349\"[label=\"Multiply(349)\"];\n\"cntrl350\"[label=\"SetCoordinate(350)\"];\n\"cntrl351\"[label=\"LoadLDSTile{Value: Halfx2}(351)\"];\n\"cntrl352\"[label=\"SetCoordinate(352)\"];\n\"cntrl353\"[label=\"LoadLDSTile{Value: Halfx2}(353)\"];\n\"cntrl354\"[label=\"Multiply(354)\"];\n\"cntrl355\"[label=\"SetCoordinate(355)\"];\n\"cntrl356\"[label=\"LoadLDSTile{Value: Halfx2}(356)\"];\n\"cntrl357\"[label=\"SetCoordinate(357)\"];\n\"cntrl358\"[label=\"LoadLDSTile{Value: Halfx2}(358)\"];\n\"cntrl359\"[label=\"Multiply(359)\"];\n\"cntrl360\"[label=\"SetCoordinate(360)\"];\n\"cntrl361\"[label=\"LoadLDSTile{Value: Halfx2}(361)\"];\n\"cntrl362\"[label=\"SetCoordinate(362)\"];\n\"cntrl363\"[label=\"LoadLDSTile{Value: Halfx2}(363)\"];\n\"cntrl364\"[label=\"Multiply(364)\"];\n\"cntrl365\"[label=\"SetCoordinate(365)\"];\n\"cntrl366\"[label=\"LoadLDSTile{Value: Halfx2}(366)\"];\n\"cntrl367\"[label=\"SetCoordinate(367)\"];\n\"cntrl368\"[label=\"LoadLDSTile{Value: Halfx2}(368)\"];\n\"cntrl369\"[label=\"Multiply(369)\"];\n\"cntrl379\"[label=\"Body(379)\",shape=box];\n\"cntrl381\"[label=\"Body(381)\",shape=box];\n\"cntrl384\"[label=\"Body(384)\",shape=box];\n\"cntrl386\"[label=\"Body(386)\",shape=box];\n\"cntrl389\"[label=\"Body(389)\",shape=box];\n\"cntrl391\"[label=\"Body(391)\",shape=box];\n\"cntrl394\"[label=\"Body(394)\",shape=box];\n\"cntrl396\"[label=\"Body(396)\",shape=box];\n\"cntrl399\"[label=\"Body(399)\",shape=box];\n\"cntrl401\"[label=\"Body(401)\",shape=box];\n\"cntrl404\"[label=\"Body(404)\",shape=box];\n\"cntrl406\"[label=\"Body(406)\",shape=box];\n\"cntrl409\"[label=\"Body(409)\",shape=box];\n\"cntrl411\"[label=\"Body(411)\",shape=box];\n\"cntrl414\"[label=\"Body(414)\",shape=box];\n\"cntrl416\"[label=\"Body(416)\",shape=box];\n\"cntrl420\"[label=\"SetCoordinate(420)\"];\n\"cntrl421\"[label=\"LoadLDSTile{Value: Halfx2}(421)\"];\n\"cntrl422\"[label=\"SetCoordinate(422)\"];\n\"cntrl423\"[label=\"LoadLDSTile{Value: Halfx2}(423)\"];\n\"cntrl424\"[label=\"Multiply(424)\"];\n\"cntrl425\"[label=\"SetCoordinate(425)\"];\n\"cntrl426\"[label=\"LoadLDSTile{Value: Halfx2}(426)\"];\n\"cntrl427\"[label=\"SetCoordinate(427)\"];\n\"cntrl428\"[label=\"LoadLDSTile{Value: Halfx2}(428)\"];\n\"cntrl429\"[label=\"Multiply(429)\"];\n\"cntrl430\"[label=\"SetCoordinate(430)\"];\n\"cntrl431\"[label=\"LoadLDSTile{Value: Halfx2}(431)\"];\n\"cntrl432\"[label=\"SetCoordinate(432)\"];\n\"cntrl433\"[label=\"LoadLDSTile{Value: Halfx2}(433)\"];\n\"cntrl434\"[label=\"Multiply(434)\"];\n\"cntrl435\"[label=\"SetCoordinate(435)\"];\n\"cntrl436\"[label=\"LoadLDSTile{Value: Halfx2}(436)\"];\n\"cntrl437\"[label=\"SetCoordinate(437)\"];\n\"cntrl438\"[label=\"LoadLDSTile{Value: Halfx2}(438)\"];\n\"cntrl439\"[label=\"Multiply(439)\"];\n\"cntrl440\"[label=\"SetCoordinate(440)\"];\n\"cntrl441\"[label=\"LoadLDSTile{Value: Halfx2}(441)\"];\n\"cntrl442\"[label=\"SetCoordinate(442)\"];\n\"cntrl443\"[label=\"LoadLDSTile{Value: Halfx2}(443)\"];\n\"cntrl444\"[label=\"Multiply(444)\"];\n\"cntrl445\"[label=\"SetCoordinate(445)\"];\n\"cntrl446\"[label=\"LoadLDSTile{Value: Halfx2}(446)\"];\n\"cntrl447\"[label=\"SetCoordinate(447)\"];\n\"cntrl448\"[label=\"LoadLDSTile{Value: Halfx2}(448)\"];\n\"cntrl449\"[label=\"Multiply(449)\"];\n\"cntrl450\"[label=\"SetCoordinate(450)\"];\n\"cntrl451\"[label=\"LoadLDSTile{Value: Halfx2}(451)\"];\n\"cntrl452\"[label=\"SetCoordinate(452)\"];\n\"cntrl453\"[label=\"LoadLDSTile{Value: Halfx2}(453)\"];\n\"cntrl454\"[label=\"Multiply(454)\"];\n\"cntrl455\"[label=\"SetCoordinate(455)\"];\n\"cntrl456\"[label=\"LoadLDSTile{Value: Halfx2}(456)\"];\n\"cntrl457\"[label=\"SetCoordinate(457)\"];\n\"cntrl458\"[label=\"LoadLDSTile{Value: Halfx2}(458)\"];\n\"cntrl459\"[label=\"Multiply(459)\"];\n\"cntrl469\"[label=\"Body(469)\",shape=box];\n\"cntrl471\"[label=\"Body(471)\",shape=box];\n\"cntrl474\"[label=\"Body(474)\",shape=box];\n\"cntrl476\"[label=\"Body(476)\",shape=box];\n\"cntrl479\"[label=\"Body(479)\",shape=box];\n\"cntrl481\"[label=\"Body(481)\",shape=box];\n\"cntrl484\"[label=\"Body(484)\",shape=box];\n\"cntrl486\"[label=\"Body(486)\",shape=box];\n\"cntrl489\"[label=\"Body(489)\",shape=box];\n\"cntrl491\"[label=\"Body(491)\",shape=box];\n\"cntrl494\"[label=\"Body(494)\",shape=box];\n\"cntrl496\"[label=\"Body(496)\",shape=box];\n\"cntrl499\"[label=\"Body(499)\",shape=box];\n\"cntrl501\"[label=\"Body(501)\",shape=box];\n\"cntrl504\"[label=\"Body(504)\",shape=box];\n\"cntrl506\"[label=\"Body(506)\",shape=box];\n\"cntrl510\"[label=\"SetCoordinate(510)\"];\n\"cntrl511\"[label=\"LoadLDSTile{Value: Halfx2}(511)\"];\n\"cntrl512\"[label=\"SetCoordinate(512)\"];\n\"cntrl513\"[label=\"LoadLDSTile{Value: Halfx2}(513)\"];\n\"cntrl514\"[label=\"Multiply(514)\"];\n\"cntrl515\"[label=\"SetCoordinate(515)\"];\n\"cntrl516\"[label=\"LoadLDSTile{Value: Halfx2}(516)\"];\n\"cntrl517\"[label=\"SetCoordinate(517)\"];\n\"cntrl518\"[label=\"LoadLDSTile{Value: Halfx2}(518)\"];\n\"cntrl519\"[label=\"Multiply(519)\"];\n\"cntrl520\"[label=\"SetCoordinate(520)\"];\n\"cntrl521\"[label=\"LoadLDSTile{Value: Halfx2}(521)\"];\n\"cntrl522\"[label=\"SetCoordinate(522)\"];\n\"cntrl523\"[label=\"LoadLDSTile{Value: Halfx2}(523)\"];\n\"cntrl524\"[label=\"Multiply(524)\"];\n\"cntrl525\"[label=\"SetCoordinate(525)\"];\n\"cntrl526\"[label=\"LoadLDSTile{Value: Halfx2}(526)\"];\n\"cntrl527\"[label=\"SetCoordinate(527)\"];\n\"cntrl528\"[label=\"LoadLDSTile{Value: Halfx2}(528)\"];\n\"cntrl529\"[label=\"Multiply(529)\"];\n\"cntrl530\"[label=\"SetCoordinate(530)\"];\n\"cntrl531\"[label=\"LoadLDSTile{Value: Halfx2}(531)\"];\n\"cntrl532\"[label=\"SetCoordinate(532)\"];\n\"cntrl533\"[label=\"LoadLDSTile{Value: Halfx2}(533)\"];\n\"cntrl534\"[label=\"Multiply(534)\"];\n\"cntrl535\"[label=\"SetCoordinate(535)\"];\n\"cntrl536\"[label=\"LoadLDSTile{Value: Halfx2}(536)\"];\n\"cntrl537\"[label=\"SetCoordinate(537)\"];\n\"cntrl538\"[label=\"LoadLDSTile{Value: Halfx2}(538)\"];\n\"cntrl539\"[label=\"Multiply(539)\"];\n\"cntrl540\"[label=\"SetCoordinate(540)\"];\n\"cntrl541\"[label=\"LoadLDSTile{Value: Halfx2}(541)\"];\n\"cntrl542\"[label=\"SetCoordinate(542)\"];\n\"cntrl543\"[label=\"LoadLDSTile{Value: Halfx2}(543)\"];\n\"cntrl544\"[label=\"Multiply(544)\"];\n\"cntrl545\"[label=\"SetCoordinate(545)\"];\n\"cntrl546\"[label=\"LoadLDSTile{Value: Halfx2}(546)\"];\n\"cntrl547\"[label=\"SetCoordinate(547)\"];\n\"cntrl548\"[label=\"LoadLDSTile{Value: Halfx2}(548)\"];\n\"cntrl549\"[label=\"Multiply(549)\"];\n\"cntrl559\"[label=\"Body(559)\",shape=box];\n\"cntrl561\"[label=\"Body(561)\",shape=box];\n\"cntrl564\"[label=\"Body(564)\",shape=box];\n\"cntrl566\"[label=\"Body(566)\",shape=box];\n\"cntrl569\"[label=\"Body(569)\",shape=box];\n\"cntrl571\"[label=\"Body(571)\",shape=box];\n\"cntrl574\"[label=\"Body(574)\",shape=box];\n\"cntrl576\"[label=\"Body(576)\",shape=box];\n\"cntrl579\"[label=\"Body(579)\",shape=box];\n\"cntrl581\"[label=\"Body(581)\",shape=box];\n\"cntrl584\"[label=\"Body(584)\",shape=box];\n\"cntrl586\"[label=\"Body(586)\",shape=box];\n\"cntrl589\"[label=\"Body(589)\",shape=box];\n\"cntrl591\"[label=\"Body(591)\",shape=box];\n\"cntrl594\"[label=\"Body(594)\",shape=box];\n\"cntrl596\"[label=\"Body(596)\",shape=box];\n\"cntrl599\"[label=\"SetCoordinate(599)\"];\n\"cntrl604\"[label=\"SetCoordinate(604)\"];\n\"cntrl610\"[label=\"SetCoordinate(610)\"];\n\"cntrl615\"[label=\"SetCoordinate(615)\"];\n\"cntrl624\"[label=\"SetCoordinate(624)\"];\n\"cntrl629\"[label=\"SetCoordinate(629)\"];\n\"cntrl638\"[label=\"SetCoordinate(638)\"];\n\"cntrl643\"[label=\"SetCoordinate(643)\"];\n\"cntrl668\"[label=\"Sequence(668)\",shape=box];\n\"cntrl670\"[label=\"Scope(670)\"];\n\"cntrl675\"[label=\"NOP(675)\"];\n\"cntrl676\"[label=\"Body(676)\",shape=box];\n\"cntrl677\"[label=\"Sequence(677)\",shape=box];\n\"cntrl678\"[label=\"Scope(678)\"];\n\"cntrl679\"[label=\"Body(679)\",shape=box];\n\"cntrl681\"[label=\"NOP(681)\"];\n\"cntrl682\"[label=\"Body(682)\",shape=box];\n\"cntrl683\"[label=\"Sequence(683)\",shape=box];\n\"cntrl684\"[label=\"Scope(684)\"];\n\"cntrl685\"[label=\"Else(685)\",shape=box];\n\"cntrl687\"[label=\"NOP(687)\"];\n\"cntrl688\"[label=\"Body(688)\",shape=box];\n\"cntrl689\"[label=\"Sequence(689)\",shape=box];\n\"cntrl690\"[label=\"NOP(690)\"];\n\"cntrl693\"[label=\"Barrier(693)\"];\n\"cntrl694\"[label=\"NOP(694)\"];\n\"cntrl696\"[label=\"SetCoordinate(696)\"];\n\"cntrl699\"[label=\"SetCoordinate(699)\"];\n\"cntrl702\"[label=\"SetCoordinate(702)\"];\n\"cntrl705\"[label=\"SetCoordinate(705)\"];\n\"cntrl708\"[label=\"SetCoordinate(708)\"];\n\"cntrl711\"[label=\"SetCoordinate(711)\"];\n\"cntrl714\"[label=\"SetCoordinate(714)\"];\n\"cntrl717\"[label=\"SetCoordinate(717)\"];\n\"cntrl722\"[label=\"Sequence(722)\",shape=box];\n\"cntrl723\"[label=\"Sequence(723)\",shape=box];\n\"cntrl724\"[label=\"Sequence(724)\",shape=box];\n\"cntrl725\"[label=\"Sequence(725)\",shape=box];\n\"cntrl726\"[label=\"Sequence(726)\",shape=box];\n\"cntrl727\"[label=\"Sequence(727)\",shape=box];\n\"cntrl728\"[label=\"Sequence(728)\",shape=box];\n\"cntrl733\"[label=\"SetCoordinate(733)\"];\n\"cntrl734\"[label=\"LoadLDSTile{Value: Halfx2}(734)\"];\n\"cntrl735\"[label=\"Body(735)\",shape=box];\n\"cntrl736\"[label=\"SetCoordinate(736)\"];\n\"cntrl737\"[label=\"LoadLDSTile{Value: Halfx2}(737)\"];\n\"cntrl738\"[label=\"Body(738)\",shape=box];\n\"cntrl739\"[label=\"SetCoordinate(739)\"];\n\"cntrl740\"[label=\"LoadLDSTile{Value: Halfx2}(740)\"];\n\"cntrl741\"[label=\"Body(741)\",shape=box];\n\"cntrl742\"[label=\"SetCoordinate(742)\"];\n\"cntrl743\"[label=\"LoadLDSTile{Value: Halfx2}(743)\"];\n\"cntrl744\"[label=\"Body(744)\",shape=box];\n\"cntrl745\"[label=\"SetCoordinate(745)\"];\n\"cntrl746\"[label=\"LoadLDSTile{Value: Halfx2}(746)\"];\n\"cntrl747\"[label=\"Body(747)\",shape=box];\n\"cntrl748\"[label=\"SetCoordinate(748)\"];\n\"cntrl749\"[label=\"LoadLDSTile{Value: Halfx2}(749)\"];\n\"cntrl750\"[label=\"Body(750)\",shape=box];\n\"cntrl751\"[label=\"SetCoordinate(751)\"];\n\"cntrl752\"[label=\"LoadLDSTile{Value: Halfx2}(752)\"];\n\"cntrl753\"[label=\"Body(753)\",shape=box];\n\"cntrl754\"[label=\"SetCoordinate(754)\"];\n\"cntrl755\"[label=\"LoadLDSTile{Value: Halfx2}(755)\"];\n\"cntrl756\"[label=\"Body(756)\",shape=box];\n\"cntrl757\"[label=\"SetCoordinate(757)\"];\n\"cntrl758\"[label=\"LoadLDSTile{Value: Halfx2}(758)\"];\n\"cntrl759\"[label=\"Body(759)\",shape=box];\n\"cntrl760\"[label=\"SetCoordinate(760)\"];\n\"cntrl761\"[label=\"LoadLDSTile{Value: Halfx2}(761)\"];\n\"cntrl762\"[label=\"Body(762)\",shape=box];\n\"cntrl763\"[label=\"SetCoordinate(763)\"];\n\"cntrl764\"[label=\"LoadLDSTile{Value: Halfx2}(764)\"];\n\"cntrl765\"[label=\"Body(765)\",shape=box];\n\"cntrl766\"[label=\"SetCoordinate(766)\"];\n\"cntrl767\"[label=\"LoadLDSTile{Value: Halfx2}(767)\"];\n\"cntrl768\"[label=\"Body(768)\",shape=box];\n\"cntrl769\"[label=\"SetCoordinate(769)\"];\n\"cntrl770\"[label=\"LoadLDSTile{Value: Halfx2}(770)\"];\n\"cntrl771\"[label=\"Body(771)\",shape=box];\n\"cntrl772\"[label=\"SetCoordinate(772)\"];\n\"cntrl773\"[label=\"LoadLDSTile{Value: Halfx2}(773)\"];\n\"cntrl774\"[label=\"Body(774)\",shape=box];\n\"cntrl775\"[label=\"SetCoordinate(775)\"];\n\"cntrl776\"[label=\"LoadLDSTile{Value: Halfx2}(776)\"];\n\"cntrl777\"[label=\"Body(777)\",shape=box];\n\"cntrl778\"[label=\"SetCoordinate(778)\"];\n\"cntrl779\"[label=\"LoadLDSTile{Value: Halfx2}(779)\"];\n\"cntrl780\"[label=\"Body(780)\",shape=box];\n\"cntrl781\"[label=\"Sequence(781)\",shape=box];\n\"cntrl782\"[label=\"Sequence(782)\",shape=box];\n\"cntrl783\"[label=\"Sequence(783)\",shape=box];\n\"cntrl784\"[label=\"Sequence(784)\",shape=box];\n\"cntrl785\"[label=\"Sequence(785)\",shape=box];\n\"cntrl786\"[label=\"Sequence(786)\",shape=box];\n\"cntrl787\"[label=\"Sequence(787)\",shape=box];\n\"cntrl788\"[label=\"Sequence(788)\",shape=box];\n\"cntrl789\"[label=\"Sequence(789)\",shape=box];\n\"cntrl790\"[label=\"Sequence(790)\",shape=box];\n\"cntrl791\"[label=\"Sequence(791)\",shape=box];\n\"cntrl792\"[label=\"Sequence(792)\",shape=box];\n\"cntrl793\"[label=\"Sequence(793)\",shape=box];\n\"cntrl794\"[label=\"Sequence(794)\",shape=box];\n\"cntrl795\"[label=\"Sequence(795)\",shape=box];\n\"cntrl796\"[label=\"Sequence(796)\",shape=box];\n\"cntrl797\"[label=\"Sequence(797)\",shape=box];\n\"cntrl799\"[label=\"NOP(799)\"];\n\"cntrl800\"[label=\"NOP(800)\"];\n\"cntrl801\"[label=\"NOP(801)\"];\n\"cntrl802\"[label=\"NOP(802)\"];\n\"cntrl810\"[label=\"Body(810)\",shape=box];\n\"cntrl811\"[label=\"Barrier(811)\"];\n\"cntrl816\"[label=\"Body(816)\",shape=box];\n\"cntrl820\"[label=\"Sequence(820)\",shape=box];\n\"cntrl821\"[label=\"Sequence(821)\",shape=box];\n\"cntrl822\"[label=\"Sequence(822)\",shape=box];\n\"cntrl823\"[label=\"Sequence(823)\",shape=box];\n\"cntrl824\"[label=\"Sequence(824)\",shape=box];\n\"cntrl825\"[label=\"Sequence(825)\",shape=box];\n\"cntrl826\"[label=\"Sequence(826)\",shape=box];\n\"cntrl827\"[label=\"Sequence(827)\",shape=box];\n\"cntrl829\"[label=\"Sequence(829)\",shape=box];\n\"cntrl830\"[label=\"Sequence(830)\",shape=box];\n\"cntrl831\"[label=\"Sequence(831)\",shape=box];\n\"cntrl832\"[label=\"Sequence(832)\",shape=box];\n\"cntrl833\"[label=\"Sequence(833)\",shape=box];\n\"cntrl834\"[label=\"Sequence(834)\",shape=box];\n\"cntrl835\"[label=\"Sequence(835)\",shape=box];\n\"cntrl844\"[label=\"Sequence(844)\",shape=box];\n\"cntrl845\"[label=\"Sequence(845)\",shape=box];\n\"cntrl853\"[label=\"Barrier(853)\"];\n\"cntrl858\"[label=\"Sequence(858)\",shape=box];\n\"cntrl862\"[label=\"Sequence(862)\",shape=box];\n\"cntrl863\"[label=\"Sequence(863)\",shape=box];\n\"cntrl864\"[label=\"Sequence(864)\",shape=box];\n\"cntrl865\"[label=\"Sequence(865)\",shape=box];\n\"cntrl866\"[label=\"Sequence(866)\",shape=box];\n\"cntrl867\"[label=\"Sequence(867)\",shape=box];\n\"cntrl868\"[label=\"Sequence(868)\",shape=box];\n\"cntrl869\"[label=\"Sequence(869)\",shape=box];\n\"cntrl871\"[label=\"Sequence(871)\",shape=box];\n\"cntrl872\"[label=\"Sequence(872)\",shape=box];\n\"cntrl873\"[label=\"Sequence(873)\",shape=box];\n\"cntrl874\"[label=\"Sequence(874)\",shape=box];\n\"cntrl875\"[label=\"Sequence(875)\",shape=box];\n\"cntrl876\"[label=\"Sequence(876)\",shape=box];\n\"cntrl877\"[label=\"Sequence(877)\",shape=box];\n\"cntrl887\"[label=\"Sequence(887)\",shape=box];\n\"cntrl895\"[label=\"Barrier(895)\"];\n\"cntrl900\"[label=\"Sequence(900)\",shape=box];\n\"cntrl904\"[label=\"Sequence(904)\",shape=box];\n\"cntrl905\"[label=\"Sequence(905)\",shape=box];\n\"cntrl906\"[label=\"Sequence(906)\",shape=box];\n\"cntrl907\"[label=\"Sequence(907)\",shape=box];\n\"cntrl908\"[label=\"Sequence(908)\",shape=box];\n\"cntrl909\"[label=\"Sequence(909)\",shape=box];\n\"cntrl910\"[label=\"Sequence(910)\",shape=box];\n\"cntrl911\"[label=\"Sequence(911)\",shape=box];\n\"cntrl913\"[label=\"Sequence(913)\",shape=box];\n\"cntrl914\"[label=\"Sequence(914)\",shape=box];\n\"cntrl915\"[label=\"Sequence(915)\",shape=box];\n\"cntrl916\"[label=\"Sequence(916)\",shape=box];\n\"cntrl917\"[label=\"Sequence(917)\",shape=box];\n\"cntrl918\"[label=\"Sequence(918)\",shape=box];\n\"cntrl919\"[label=\"Sequence(919)\",shape=box];\n\"cntrl929\"[label=\"Sequence(929)\",shape=box];\n\"cntrl937\"[label=\"Barrier(937)\"];\n\"cntrl942\"[label=\"Sequence(942)\",shape=box];\n\"cntrl946\"[label=\"Sequence(946)\",shape=box];\n\"cntrl947\"[label=\"Sequence(947)\",shape=box];\n\"cntrl948\"[label=\"Sequence(948)\",shape=box];\n\"cntrl949\"[label=\"Sequence(949)\",shape=box];\n\"cntrl950\"[label=\"Sequence(950)\",shape=box];\n\"cntrl951\"[label=\"Sequence(951)\",shape=box];\n\"cntrl952\"[label=\"Sequence(952)\",shape=box];\n\"cntrl953\"[label=\"Sequence(953)\",shape=box];\n\"cntrl954\"[label=\"Sequence(954)\",shape=box];\n\"cntrl955\"[label=\"Sequence(955)\",shape=box];\n\"cntrl956\"[label=\"Sequence(956)\",shape=box];\n\"cntrl957\"[label=\"Sequence(957)\",shape=box];\n\"cntrl958\"[label=\"Sequence(958)\",shape=box];\n\"cntrl959\"[label=\"Sequence(959)\",shape=box];\n\"cntrl960\"[label=\"Sequence(960)\",shape=box];\n\"cntrl961\"[label=\"Sequence(961)\",shape=box];\n\"cntrl962\"[label=\"Sequence(962)\",shape=box];\n\"cntrl971\"[label=\"LoadTileDirect2LDS Value: Halfx2(971)\"];\n\"cntrl972\"[label=\"Body(972)\",shape=box];\n\"cntrl973\"[label=\"NOP(973)\"];\n\"cntrl975\"[label=\"Sequence(975)\",shape=box];\n\"cntrl976\"[label=\"LoadTileDirect2LDS Value: Halfx2(976)\"];\n\"cntrl977\"[label=\"Body(977)\",shape=box];\n\"cntrl978\"[label=\"NOP(978)\"];\n\"cntrl980\"[label=\"Sequence(980)\",shape=box];\n\"cntrl981\"[label=\"LoadTileDirect2LDS Value: Halfx2(981)\"];\n\"cntrl982\"[label=\"Body(982)\",shape=box];\n\"cntrl983\"[label=\"NOP(983)\"];\n\"cntrl984\"[label=\"Sequence(984)\",shape=box];\n\"cntrl987\"[label=\"LoadTileDirect2LDS Value: Halfx2(987)\"];\n\"cntrl988\"[label=\"Body(988)\",shape=box];\n\"cntrl989\"[label=\"NOP(989)\"];\n\"cntrl990\"[label=\"Sequence(990)\",shape=box];\n\"cntrl991\"[label=\"Sequence(991)\",shape=box];\n\"cntrl993\"[label=\"LoadTileDirect2LDS Value: Halfx2(993)\"];\n\"cntrl994\"[label=\"Body(994)\",shape=box];\n\"cntrl995\"[label=\"NOP(995)\"];\n\"cntrl997\"[label=\"Sequence(997)\",shape=box];\n\"cntrl998\"[label=\"LoadTileDirect2LDS Value: Halfx2(998)\"];\n\"cntrl999\"[label=\"Body(999)\",shape=box];\n\"cntrl1000\"[label=\"NOP(1000)\"];\n\"cntrl1001\"[label=\"Sequence(1001)\",shape=box];\n\"cntrl1002\"[label=\"Sequence(1002)\",shape=box];\n\"cntrl1003\"[label=\"LoadTileDirect2LDS Value: Halfx2(1003)\"];\n\"cntrl1004\"[label=\"Body(1004)\",shape=box];\n\"cntrl1005\"[label=\"NOP(1005)\"];\n\"cntrl1007\"[label=\"Sequence(1007)\",shape=box];\n\"cntrl1008\"[label=\"LoadTileDirect2LDS Value: Halfx2(1008)\"];\n\"cntrl1009\"[label=\"Body(1009)\",shape=box];\n\"cntrl1010\"[label=\"NOP(1010)\"];\n\"cntrl1011\"[label=\"Sequence(1011)\",shape=box];\n\"cntrl1012\"[label=\"Sequence(1012)\",shape=box];\n\"cntrl1013\"[label=\"LoadTileDirect2LDS Value: Halfx2(1013)\"];\n\"cntrl1014\"[label=\"Body(1014)\",shape=box];\n\"cntrl1015\"[label=\"NOP(1015)\"];\n\"cntrl1017\"[label=\"Sequence(1017)\",shape=box];\n\"cntrl1018\"[label=\"LoadTileDirect2LDS Value: Halfx2(1018)\"];\n\"cntrl1019\"[label=\"Body(1019)\",shape=box];\n\"cntrl1020\"[label=\"NOP(1020)\"];\n\"cntrl1021\"[label=\"Sequence(1021)\",shape=box];\n\"cntrl1022\"[label=\"Sequence(1022)\",shape=box];\n\"cntrl1023\"[label=\"LoadTileDirect2LDS Value: Halfx2(1023)\"];\n\"cntrl1025\"[label=\"NOP(1025)\"];\n\"cntrl1028\"[label=\"LoadTileDirect2LDS Value: Halfx2(1028)\"];\n\"cntrl1030\"[label=\"NOP(1030)\"];\n\"cntrl1031\"[label=\"Sequence(1031)\",shape=box];\n\"cntrl1032\"[label=\"Sequence(1032)\",shape=box];\n\"cntrl1033\"[label=\"LoadTileDirect2LDS Value: Halfx2(1033)\"];\n\"cntrl1035\"[label=\"LoadTileDirect2LDS Value: Halfx2(1035)\"];\n\"cntrl1037\"[label=\"LoadTileDirect2LDS Value: Halfx2(1037)\"];\n\"cntrl1039\"[label=\"LoadTileDirect2LDS Value: Halfx2(1039)\"];\n\"cntrl1041\"[label=\"LoadTileDirect2LDS Value: Halfx2(1041)\"];\n\"cntrl1043\"[label=\"LoadTileDirect2LDS Value: Halfx2(1043)\"];\n\"cntrl1045\"[label=\"NOP(1045)\"];\n\"cntrl1046\"[label=\"Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046)\"];\n\"cntrl1047\"[label=\"NOP(1047)\"];\n\"cntrl1048\"[label=\"NOP(1048)\"];\n\"cntrl1051\"[label=\"Scope(1051)\"];\n\"cntrl1052\"[label=\"Body(1052)\",shape=box];\n\"cntrl1053\"[label=\"Body(1053)\",shape=box];\n\"cntrl1056\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056)\"];\n\"cntrl1057\"[label=\"Assign VGPR 128:U64(1057)\"];\n\"cntrl1058\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058)\"];\n\"cntrl1059\"[label=\"Sequence(1059)\",shape=box];\n\"cntrl1060\"[label=\"Sequence(1060)\",shape=box];\n\"cntrl1061\"[label=\"Sequence(1061)\",shape=box];\n\"cntrl1062\"[label=\"Sequence(1062)\",shape=box];\n\"cntrl1063\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063)\"];\n\"cntrl1064\"[label=\"Sequence(1064)\",shape=box];\n\"cntrl1065\"[label=\"Sequence(1065)\",shape=box];\n\"cntrl1066\"[label=\"Assign VGPR 2:U64(1066)\"];\n\"cntrl1067\"[label=\"Sequence(1067)\",shape=box];\n\"cntrl1068\"[label=\"Sequence(1068)\",shape=box];\n\"cntrl1069\"[label=\"NOP(1069)\"];\n\"cntrl1070\"[label=\"NOP(1070)\"];\n\"cntrl1071\"[label=\"NOP(1071)\"];\n\"cntrl1074\"[label=\"Scope(1074)\"];\n\"cntrl1075\"[label=\"Sequence(1075)\",shape=box];\n\"cntrl1076\"[label=\"Sequence(1076)\",shape=box];\n\"cntrl1077\"[label=\"Body(1077)\",shape=box];\n\"cntrl1079\"[label=\"Assign VGPR 128:U64(1079)\"];\n\"cntrl1080\"[label=\"Sequence(1080)\",shape=box];\n\"cntrl1081\"[label=\"Sequence(1081)\",shape=box];\n\"cntrl1082\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082)\"];\n\"cntrl1083\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083)\"];\n\"cntrl1084\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084)\"];\n\"cntrl1085\"[label=\"Sequence(1085)\",shape=box];\n\"cntrl1086\"[label=\"Sequence(1086)\",shape=box];\n\"cntrl1087\"[label=\"Sequence(1087)\",shape=box];\n\"cntrl1088\"[label=\"Sequence(1088)\",shape=box];\n\"cntrl1089\"[label=\"Assign VGPR 2:U64(1089)\"];\n\"cntrl1090\"[label=\"Sequence(1090)\",shape=box];\n\"cntrl1091\"[label=\"Sequence(1091)\",shape=box];\n\"cntrl1092\"[label=\"NOP(1092)\"];\n\"cntrl1093\"[label=\"Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093)\"];\n\"cntrl1094\"[label=\"NOP(1094)\"];\n\"cntrl1095\"[label=\"NOP(1095)\"];\n\"cntrl1098\"[label=\"Sequence(1098)\",shape=box];\n\"cntrl1101\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101)\"];\n\"cntrl1102\"[label=\"Assign VGPR 128:U64(1102)\"];\n\"cntrl1103\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103)\"];\n\"cntrl1104\"[label=\"Sequence(1104)\",shape=box];\n\"cntrl1105\"[label=\"Sequence(1105)\",shape=box];\n\"cntrl1106\"[label=\"Sequence(1106)\",shape=box];\n\"cntrl1107\"[label=\"Sequence(1107)\",shape=box];\n\"cntrl1108\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108)\"];\n\"cntrl1109\"[label=\"Sequence(1109)\",shape=box];\n\"cntrl1110\"[label=\"Sequence(1110)\",shape=box];\n\"cntrl1111\"[label=\"Assign VGPR 2:U64(1111)\"];\n\"cntrl1112\"[label=\"Sequence(1112)\",shape=box];\n\"cntrl1113\"[label=\"Sequence(1113)\",shape=box];\n\"cntrl1114\"[label=\"NOP(1114)\"];\n\"cntrl1115\"[label=\"Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115)\"];\n\"cntrl1116\"[label=\"NOP(1116)\"];\n\"cntrl1117\"[label=\"NOP(1117)\"];\n\"cntrl1120\"[label=\"Sequence(1120)\",shape=box];\n\"cntrl1123\"[label=\"Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123)\"];\n\"cntrl1124\"[label=\"Assign VGPR 128:U64(1124)\"];\n\"cntrl1125\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125)\"];\n\"cntrl1126\"[label=\"Sequence(1126)\",shape=box];\n\"cntrl1127\"[label=\"Sequence(1127)\",shape=box];\n\"cntrl1128\"[label=\"Sequence(1128)\",shape=box];\n\"cntrl1129\"[label=\"Sequence(1129)\",shape=box];\n\"cntrl1130\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130)\"];\n\"cntrl1131\"[label=\"Sequence(1131)\",shape=box];\n\"cntrl1132\"[label=\"Sequence(1132)\",shape=box];\n\"cntrl1133\"[label=\"Assign VGPR 2:U64(1133)\"];\n\"cntrl1134\"[label=\"Sequence(1134)\",shape=box];\n\"cntrl1135\"[label=\"Sequence(1135)\",shape=box];\n\"cntrl1136\"[label=\"NOP(1136)\"];\n\"cntrl1137\"[label=\"NOP(1137)\"];\n\"cntrl1138\"[label=\"NOP(1138)\"];\n\"cntrl1141\"[label=\"Sequence(1141)\",shape=box];\n\"cntrl1143\"[label=\"Assign VGPR 128:U64(1143)\"];\n\"cntrl1144\"[label=\"Sequence(1144)\",shape=box];\n\"cntrl1145\"[label=\"Sequence(1145)\",shape=box];\n\"cntrl1146\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146)\"];\n\"cntrl1147\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147)\"];\n\"cntrl1148\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148)\"];\n\"cntrl1149\"[label=\"Sequence(1149)\",shape=box];\n\"cntrl1150\"[label=\"Sequence(1150)\",shape=box];\n\"cntrl1151\"[label=\"Sequence(1151)\",shape=box];\n\"cntrl1152\"[label=\"Sequence(1152)\",shape=box];\n\"cntrl1153\"[label=\"Assign VGPR 2:U64(1153)\"];\n\"cntrl1154\"[label=\"Sequence(1154)\",shape=box];\n\"cntrl1155\"[label=\"Sequence(1155)\",shape=box];\n\"cntrl1156\"[label=\"NOP(1156)\"];\n\"cntrl1157\"[label=\"Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157)\"];\n\"cntrl1158\"[label=\"NOP(1158)\"];\n\"cntrl1159\"[label=\"NOP(1159)\"];\n\"cntrl1162\"[label=\"Sequence(1162)\",shape=box];\n\"cntrl1165\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165)\"];\n\"cntrl1166\"[label=\"Assign VGPR 128:U64(1166)\"];\n\"cntrl1167\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167)\"];\n\"cntrl1168\"[label=\"Sequence(1168)\",shape=box];\n\"cntrl1169\"[label=\"Sequence(1169)\",shape=box];\n\"cntrl1170\"[label=\"Sequence(1170)\",shape=box];\n\"cntrl1171\"[label=\"Sequence(1171)\",shape=box];\n\"cntrl1172\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172)\"];\n\"cntrl1173\"[label=\"Sequence(1173)\",shape=box];\n\"cntrl1174\"[label=\"Sequence(1174)\",shape=box];\n\"cntrl1175\"[label=\"Assign VGPR 2:U64(1175)\"];\n\"cntrl1176\"[label=\"Sequence(1176)\",shape=box];\n\"cntrl1177\"[label=\"Sequence(1177)\",shape=box];\n\"cntrl1178\"[label=\"NOP(1178)\"];\n\"cntrl1179\"[label=\"NOP(1179)\"];\n\"cntrl1181\"[label=\"Scope(1181)\"];\n\"cntrl1182\"[label=\"Sequence(1182)\",shape=box];\n\"cntrl1183\"[label=\"Sequence(1183)\",shape=box];\n\"cntrl1184\"[label=\"Body(1184)\",shape=box];\n\"cntrl1186\"[label=\"Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186)\"];\n\"cntrl1187\"[label=\"Assign VGPR 16:U64(1187)\"];\n\"cntrl1188\"[label=\"Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188)\"];\n\"cntrl1190\"[label=\"Sequence(1190)\",shape=box];\n\"cntrl1192\"[label=\"Sequence(1192)\",shape=box];\n\"cntrl1193\"[label=\"Assign VGPR 2:U64(1193)\"];\n\"cntrl1194\"[label=\"Sequence(1194)\",shape=box];\n\"cntrl1195\"[label=\"Sequence(1195)\",shape=box];\n\"cntrl1196\"[label=\"NOP(1196)\"];\n\"cntrl1197\"[label=\"NOP(1197)\"];\n\"cntrl1199\"[label=\"NOP(1199)\"];\n\"cntrl1200\"[label=\"Sequence(1200)\",shape=box];\n\"cntrl1201\"[label=\"Sequence(1201)\",shape=box];\n\"cntrl1203\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203)\"];\n\"cntrl1204\"[label=\"Assign VGPR 1024:U32(1204)\"];\n\"cntrl1205\"[label=\"Sequence(1205)\",shape=box];\n\"cntrl1206\"[label=\"Sequence(1206)\",shape=box];\n\"cntrl1207\"[label=\"Sequence(1207)\",shape=box];\n\"cntrl1208\"[label=\"Assign VGPR 2:U32(1208)\"];\n\"cntrl1209\"[label=\"Sequence(1209)\",shape=box];\n\"cntrl1210\"[label=\"Sequence(1210)\",shape=box];\n\"cntrl1211\"[label=\"NOP(1211)\"];\n\"cntrl1212\"[label=\"NOP(1212)\"];\n\"cntrl1214\"[label=\"Sequence(1214)\",shape=box];\n\"cntrl1216\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216)\"];\n\"cntrl1217\"[label=\"Assign VGPR 1024:U32(1217)\"];\n\"cntrl1218\"[label=\"Sequence(1218)\",shape=box];\n\"cntrl1219\"[label=\"Sequence(1219)\",shape=box];\n\"cntrl1220\"[label=\"Sequence(1220)\",shape=box];\n\"cntrl1221\"[label=\"Assign VGPR 2:U32(1221)\"];\n\"cntrl1222\"[label=\"Sequence(1222)\",shape=box];\n\"cntrl1223\"[label=\"Sequence(1223)\",shape=box];\n\"cntrl1224\"[label=\"NOP(1224)\"];\n\"cntrl1225\"[label=\"NOP(1225)\"];\n\"cntrl1227\"[label=\"Scope(1227)\"];\n\"cntrl1228\"[label=\"Body(1228)\",shape=box];\n\"cntrl1229\"[label=\"Body(1229)\",shape=box];\n\"cntrl1231\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231)\"];\n\"cntrl1232\"[label=\"Assign VGPR 1024:U32(1232)\"];\n\"cntrl1233\"[label=\"Sequence(1233)\",shape=box];\n\"cntrl1234\"[label=\"Sequence(1234)\",shape=box];\n\"cntrl1235\"[label=\"Sequence(1235)\",shape=box];\n\"cntrl1236\"[label=\"Assign VGPR 2:U32(1236)\"];\n\"cntrl1237\"[label=\"Sequence(1237)\",shape=box];\n\"cntrl1238\"[label=\"Sequence(1238)\",shape=box];\n\"cntrl1239\"[label=\"NOP(1239)\"];\n\"cntrl1240\"[label=\"NOP(1240)\"];\n\"cntrl1242\"[label=\"Body(1242)\",shape=box];\n\"cntrl1243\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243)\"];\n\"cntrl1244\"[label=\"Assign VGPR 16:U32(1244)\"];\n\"cntrl1245\"[label=\"Sequence(1245)\",shape=box];\n\"cntrl1247\"[label=\"Sequence(1247)\",shape=box];\n\"cntrl1248\"[label=\"Assign VGPR 2:U32(1248)\"];\n\"cntrl1249\"[label=\"Sequence(1249)\",shape=box];\n\"cntrl1250\"[label=\"NOP(1250)\"];\n\"cntrl1251\"[label=\"NOP(1251)\"];\n\"cntrl1253\"[label=\"Sequence(1253)\",shape=box];\n\"cntrl1255\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255)\"];\n\"cntrl1256\"[label=\"Assign VGPR 1024:U32(1256)\"];\n\"cntrl1257\"[label=\"Sequence(1257)\",shape=box];\n\"cntrl1258\"[label=\"Sequence(1258)\",shape=box];\n\"cntrl1259\"[label=\"Sequence(1259)\",shape=box];\n\"cntrl1260\"[label=\"Assign VGPR 2:U32(1260)\"];\n\"cntrl1261\"[label=\"Sequence(1261)\",shape=box];\n\"cntrl1262\"[label=\"Sequence(1262)\",shape=box];\n\"cntrl1263\"[label=\"NOP(1263)\"];\n\"cntrl1264\"[label=\"NOP(1264)\"];\n\"cntrl1266\"[label=\"Sequence(1266)\",shape=box];\n\"cntrl1268\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268)\"];\n\"cntrl1269\"[label=\"Assign VGPR 1024:U32(1269)\"];\n\"cntrl1270\"[label=\"Sequence(1270)\",shape=box];\n\"cntrl1271\"[label=\"Sequence(1271)\",shape=box];\n\"cntrl1272\"[label=\"Sequence(1272)\",shape=box];\n\"cntrl1273\"[label=\"Assign VGPR 2:U32(1273)\"];\n\"cntrl1274\"[label=\"Sequence(1274)\",shape=box];\n\"cntrl1275\"[label=\"Sequence(1275)\",shape=box];\n\"cntrl1276\"[label=\"NOP(1276)\"];\n\"cntrl1277\"[label=\"NOP(1277)\"];\n\"cntrl1279\"[label=\"Scope(1279)\"];\n\"cntrl1280\"[label=\"Body(1280)\",shape=box];\n\"cntrl1281\"[label=\"Body(1281)\",shape=box];\n\"cntrl1283\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283)\"];\n\"cntrl1284\"[label=\"Assign VGPR 1024:U32(1284)\"];\n\"cntrl1285\"[label=\"Sequence(1285)\",shape=box];\n\"cntrl1286\"[label=\"Sequence(1286)\",shape=box];\n\"cntrl1287\"[label=\"Sequence(1287)\",shape=box];\n\"cntrl1288\"[label=\"Assign VGPR 2:U32(1288)\"];\n\"cntrl1289\"[label=\"Sequence(1289)\",shape=box];\n\"cntrl1290\"[label=\"Sequence(1290)\",shape=box];\n\"cntrl1291\"[label=\"NOP(1291)\"];\n\"cntrl1292\"[label=\"NOP(1292)\"];\n\"cntrl1294\"[label=\"Body(1294)\",shape=box];\n\"cntrl1295\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295)\"];\n\"cntrl1296\"[label=\"Assign VGPR 16:U32(1296)\"];\n\"cntrl1297\"[label=\"Sequence(1297)\",shape=box];\n\"cntrl1299\"[label=\"Sequence(1299)\",shape=box];\n\"cntrl1300\"[label=\"Assign VGPR 2:U32(1300)\"];\n\"cntrl1301\"[label=\"Sequence(1301)\",shape=box];\n\"cntrl1302\"[label=\"NOP(1302)\"];\n\"cntrl1303\"[label=\"NOP(1303)\"];\n\"cntrl1305\"[label=\"NOP(1305)\"];\n\"cntrl1307\"[label=\"Sequence(1307)\",shape=box];\n\"cntrl1309\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309)\"];\n\"cntrl1310\"[label=\"Assign VGPR 16:U64(1310)\"];\n\"cntrl1311\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311)\"];\n\"cntrl1312\"[label=\"Sequence(1312)\",shape=box];\n\"cntrl1313\"[label=\"Sequence(1313)\",shape=box];\n\"cntrl1314\"[label=\"Sequence(1314)\",shape=box];\n\"cntrl1315\"[label=\"Sequence(1315)\",shape=box];\n\"cntrl1316\"[label=\"Assign VGPR 2:U64(1316)\"];\n\"cntrl1317\"[label=\"Sequence(1317)\",shape=box];\n\"cntrl1318\"[label=\"Sequence(1318)\",shape=box];\n\"cntrl1319\"[label=\"NOP(1319)\"];\n\"cntrl1320\"[label=\"NOP(1320)\"];\n\"cntrl1322\"[label=\"NOP(1322)\"];\n\"cntrl1324\"[label=\"Sequence(1324)\",shape=box];\n\"cntrl1326\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326)\"];\n\"cntrl1327\"[label=\"Assign VGPR 16:U64(1327)\"];\n\"cntrl1328\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328)\"];\n\"cntrl1329\"[label=\"Sequence(1329)\",shape=box];\n\"cntrl1330\"[label=\"Sequence(1330)\",shape=box];\n\"cntrl1331\"[label=\"Sequence(1331)\",shape=box];\n\"cntrl1332\"[label=\"Sequence(1332)\",shape=box];\n\"cntrl1333\"[label=\"Assign VGPR 2:U64(1333)\"];\n\"cntrl1334\"[label=\"Sequence(1334)\",shape=box];\n\"cntrl1335\"[label=\"Sequence(1335)\",shape=box];\n\"cntrl1336\"[label=\"NOP(1336)\"];\n\"cntrl1337\"[label=\"NOP(1337)\"];\n\"cntrl1339\"[label=\"Sequence(1339)\",shape=box];\n\"cntrl1341\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341)\"];\n\"cntrl1342\"[label=\"Assign VGPR 1024:U32(1342)\"];\n\"cntrl1343\"[label=\"Sequence(1343)\",shape=box];\n\"cntrl1344\"[label=\"Sequence(1344)\",shape=box];\n\"cntrl1345\"[label=\"Sequence(1345)\",shape=box];\n\"cntrl1346\"[label=\"Assign VGPR 2:U32(1346)\"];\n\"cntrl1347\"[label=\"Sequence(1347)\",shape=box];\n\"cntrl1348\"[label=\"Sequence(1348)\",shape=box];\n\"cntrl1349\"[label=\"NOP(1349)\"];\n\"cntrl1350\"[label=\"NOP(1350)\"];\n\"cntrl1352\"[label=\"Scope(1352)\"];\n\"cntrl1353\"[label=\"Body(1353)\",shape=box];\n\"cntrl1354\"[label=\"Body(1354)\",shape=box];\n\"cntrl1356\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356)\"];\n\"cntrl1357\"[label=\"Assign VGPR 1024:U32(1357)\"];\n\"cntrl1358\"[label=\"Sequence(1358)\",shape=box];\n\"cntrl1359\"[label=\"Sequence(1359)\",shape=box];\n\"cntrl1360\"[label=\"Sequence(1360)\",shape=box];\n\"cntrl1361\"[label=\"Assign VGPR 2:U32(1361)\"];\n\"cntrl1362\"[label=\"Sequence(1362)\",shape=box];\n\"cntrl1363\"[label=\"Sequence(1363)\",shape=box];\n\"cntrl1364\"[label=\"NOP(1364)\"];\n\"cntrl1365\"[label=\"NOP(1365)\"];\n\"cntrl1367\"[label=\"Body(1367)\",shape=box];\n\"cntrl1368\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368)\"];\n\"cntrl1369\"[label=\"Assign VGPR 16:U32(1369)\"];\n\"cntrl1370\"[label=\"Sequence(1370)\",shape=box];\n\"cntrl1372\"[label=\"Sequence(1372)\",shape=box];\n\"cntrl1373\"[label=\"Assign VGPR 2:U32(1373)\"];\n\"cntrl1374\"[label=\"Sequence(1374)\",shape=box];\n\"cntrl1375\"[label=\"NOP(1375)\"];\n\"cntrl1376\"[label=\"NOP(1376)\"];\n\"cntrl1378\"[label=\"Sequence(1378)\",shape=box];\n\"cntrl1380\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380)\"];\n\"cntrl1381\"[label=\"Assign VGPR 1024:U32(1381)\"];\n\"cntrl1382\"[label=\"Sequence(1382)\",shape=box];\n\"cntrl1383\"[label=\"Sequence(1383)\",shape=box];\n\"cntrl1384\"[label=\"Sequence(1384)\",shape=box];\n\"cntrl1385\"[label=\"Assign VGPR 2:U32(1385)\"];\n\"cntrl1386\"[label=\"Sequence(1386)\",shape=box];\n\"cntrl1387\"[label=\"Sequence(1387)\",shape=box];\n\"cntrl1388\"[label=\"NOP(1388)\"];\n\"cntrl1389\"[label=\"NOP(1389)\"];\n\"cntrl1391\"[label=\"Scope(1391)\"];\n\"cntrl1392\"[label=\"Body(1392)\",shape=box];\n\"cntrl1393\"[label=\"Body(1393)\",shape=box];\n\"cntrl1395\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395)\"];\n\"cntrl1396\"[label=\"Assign VGPR 1024:U32(1396)\"];\n\"cntrl1397\"[label=\"Sequence(1397)\",shape=box];\n\"cntrl1398\"[label=\"Sequence(1398)\",shape=box];\n\"cntrl1399\"[label=\"Sequence(1399)\",shape=box];\n\"cntrl1400\"[label=\"Assign VGPR 2:U32(1400)\"];\n\"cntrl1401\"[label=\"Sequence(1401)\",shape=box];\n\"cntrl1402\"[label=\"Sequence(1402)\",shape=box];\n\"cntrl1403\"[label=\"NOP(1403)\"];\n\"cntrl1404\"[label=\"NOP(1404)\"];\n\"cntrl1406\"[label=\"Body(1406)\",shape=box];\n\"cntrl1407\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407)\"];\n\"cntrl1408\"[label=\"Assign VGPR 16:U32(1408)\"];\n\"cntrl1409\"[label=\"Sequence(1409)\",shape=box];\n\"cntrl1411\"[label=\"Sequence(1411)\",shape=box];\n\"cntrl1412\"[label=\"Assign VGPR 2:U32(1412)\"];\n\"cntrl1413\"[label=\"Sequence(1413)\",shape=box];\n\"cntrl1414\"[label=\"NOP(1414)\"];\n\"cntrl1415\"[label=\"NOP(1415)\"];\n\"cntrl1417\"[label=\"Sequence(1417)\",shape=box];\n\"cntrl1419\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419)\"];\n\"cntrl1420\"[label=\"Assign VGPR 1024:U32(1420)\"];\n\"cntrl1421\"[label=\"Sequence(1421)\",shape=box];\n\"cntrl1422\"[label=\"Sequence(1422)\",shape=box];\n\"cntrl1423\"[label=\"Sequence(1423)\",shape=box];\n\"cntrl1424\"[label=\"Assign VGPR 2:U32(1424)\"];\n\"cntrl1425\"[label=\"Sequence(1425)\",shape=box];\n\"cntrl1426\"[label=\"Sequence(1426)\",shape=box];\n\"cntrl1427\"[label=\"NOP(1427)\"];\n\"cntrl1428\"[label=\"NOP(1428)\"];\n\"cntrl1430\"[label=\"Scope(1430)\"];\n\"cntrl1431\"[label=\"Body(1431)\",shape=box];\n\"cntrl1432\"[label=\"Body(1432)\",shape=box];\n\"cntrl1434\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434)\"];\n\"cntrl1435\"[label=\"Assign VGPR 1024:U32(1435)\"];\n\"cntrl1436\"[label=\"Sequence(1436)\",shape=box];\n\"cntrl1437\"[label=\"Sequence(1437)\",shape=box];\n\"cntrl1438\"[label=\"Sequence(1438)\",shape=box];\n\"cntrl1439\"[label=\"Assign VGPR 2:U32(1439)\"];\n\"cntrl1440\"[label=\"Sequence(1440)\",shape=box];\n\"cntrl1441\"[label=\"Sequence(1441)\",shape=box];\n\"cntrl1442\"[label=\"NOP(1442)\"];\n\"cntrl1443\"[label=\"NOP(1443)\"];\n\"cntrl1445\"[label=\"Body(1445)\",shape=box];\n\"cntrl1446\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446)\"];\n\"cntrl1447\"[label=\"Assign VGPR 16:U32(1447)\"];\n\"cntrl1448\"[label=\"Sequence(1448)\",shape=box];\n\"cntrl1450\"[label=\"Sequence(1450)\",shape=box];\n\"cntrl1451\"[label=\"Assign VGPR 2:U32(1451)\"];\n\"cntrl1452\"[label=\"Sequence(1452)\",shape=box];\n\"cntrl1453\"[label=\"NOP(1453)\"];\n\"cntrl1454\"[label=\"NOP(1454)\"];\n\"cntrl1456\"[label=\"Sequence(1456)\",shape=box];\n\"cntrl1458\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458)\"];\n\"cntrl1459\"[label=\"Assign VGPR 1024:U32(1459)\"];\n\"cntrl1460\"[label=\"Sequence(1460)\",shape=box];\n\"cntrl1461\"[label=\"Sequence(1461)\",shape=box];\n\"cntrl1462\"[label=\"Sequence(1462)\",shape=box];\n\"cntrl1463\"[label=\"Assign VGPR 2:U32(1463)\"];\n\"cntrl1464\"[label=\"Sequence(1464)\",shape=box];\n\"cntrl1465\"[label=\"Sequence(1465)\",shape=box];\n\"cntrl1466\"[label=\"NOP(1466)\"];\n\"cntrl1467\"[label=\"NOP(1467)\"];\n\"cntrl1469\"[label=\"Scope(1469)\"];\n\"cntrl1470\"[label=\"Body(1470)\",shape=box];\n\"cntrl1471\"[label=\"Body(1471)\",shape=box];\n\"cntrl1473\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473)\"];\n\"cntrl1474\"[label=\"Assign VGPR 1024:U32(1474)\"];\n\"cntrl1475\"[label=\"Sequence(1475)\",shape=box];\n\"cntrl1476\"[label=\"Sequence(1476)\",shape=box];\n\"cntrl1477\"[label=\"Sequence(1477)\",shape=box];\n\"cntrl1478\"[label=\"Assign VGPR 2:U32(1478)\"];\n\"cntrl1479\"[label=\"Sequence(1479)\",shape=box];\n\"cntrl1480\"[label=\"Sequence(1480)\",shape=box];\n\"cntrl1481\"[label=\"NOP(1481)\"];\n\"cntrl1482\"[label=\"NOP(1482)\"];\n\"cntrl1484\"[label=\"Body(1484)\",shape=box];\n\"cntrl1485\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485)\"];\n\"cntrl1486\"[label=\"Assign VGPR 16:U32(1486)\"];\n\"cntrl1487\"[label=\"Sequence(1487)\",shape=box];\n\"cntrl1489\"[label=\"Sequence(1489)\",shape=box];\n\"cntrl1490\"[label=\"Assign VGPR 2:U32(1490)\"];\n\"cntrl1491\"[label=\"Sequence(1491)\",shape=box];\n\"cntrl1492\"[label=\"NOP(1492)\"];\n\"cntrl1493\"[label=\"NOP(1493)\"];\n\"cntrl1495\"[label=\"Sequence(1495)\",shape=box];\n\"cntrl1497\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497)\"];\n\"cntrl1498\"[label=\"Assign VGPR 1024:U32(1498)\"];\n\"cntrl1499\"[label=\"Sequence(1499)\",shape=box];\n\"cntrl1500\"[label=\"Sequence(1500)\",shape=box];\n\"cntrl1501\"[label=\"Sequence(1501)\",shape=box];\n\"cntrl1502\"[label=\"Assign VGPR 2:U32(1502)\"];\n\"cntrl1503\"[label=\"Sequence(1503)\",shape=box];\n\"cntrl1504\"[label=\"Sequence(1504)\",shape=box];\n\"cntrl1505\"[label=\"NOP(1505)\"];\n\"cntrl1506\"[label=\"NOP(1506)\"];\n\"cntrl1508\"[label=\"Scope(1508)\"];\n\"cntrl1509\"[label=\"Body(1509)\",shape=box];\n\"cntrl1510\"[label=\"Body(1510)\",shape=box];\n\"cntrl1512\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512)\"];\n\"cntrl1513\"[label=\"Assign VGPR 1024:U32(1513)\"];\n\"cntrl1514\"[label=\"Sequence(1514)\",shape=box];\n\"cntrl1515\"[label=\"Sequence(1515)\",shape=box];\n\"cntrl1516\"[label=\"Sequence(1516)\",shape=box];\n\"cntrl1517\"[label=\"Assign VGPR 2:U32(1517)\"];\n\"cntrl1518\"[label=\"Sequence(1518)\",shape=box];\n\"cntrl1519\"[label=\"Sequence(1519)\",shape=box];\n\"cntrl1520\"[label=\"NOP(1520)\"];\n\"cntrl1521\"[label=\"NOP(1521)\"];\n\"cntrl1523\"[label=\"Body(1523)\",shape=box];\n\"cntrl1524\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524)\"];\n\"cntrl1525\"[label=\"Assign VGPR 16:U32(1525)\"];\n\"cntrl1526\"[label=\"Sequence(1526)\",shape=box];\n\"cntrl1528\"[label=\"Sequence(1528)\",shape=box];\n\"cntrl1529\"[label=\"Assign VGPR 2:U32(1529)\"];\n\"cntrl1530\"[label=\"Sequence(1530)\",shape=box];\n\"cntrl1531\"[label=\"NOP(1531)\"];\n\"cntrl1532\"[label=\"NOP(1532)\"];\n\"cntrl1534\"[label=\"Sequence(1534)\",shape=box];\n\"cntrl1536\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536)\"];\n\"cntrl1537\"[label=\"Assign VGPR 1024:U32(1537)\"];\n\"cntrl1538\"[label=\"Sequence(1538)\",shape=box];\n\"cntrl1539\"[label=\"Sequence(1539)\",shape=box];\n\"cntrl1540\"[label=\"Sequence(1540)\",shape=box];\n\"cntrl1541\"[label=\"Assign VGPR 2:U32(1541)\"];\n\"cntrl1542\"[label=\"Sequence(1542)\",shape=box];\n\"cntrl1543\"[label=\"Sequence(1543)\",shape=box];\n\"cntrl1544\"[label=\"NOP(1544)\"];\n\"cntrl1545\"[label=\"NOP(1545)\"];\n\"cntrl1547\"[label=\"Scope(1547)\"];\n\"cntrl1548\"[label=\"Body(1548)\",shape=box];\n\"cntrl1549\"[label=\"Body(1549)\",shape=box];\n\"cntrl1551\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551)\"];\n\"cntrl1552\"[label=\"Assign VGPR 1024:U32(1552)\"];\n\"cntrl1553\"[label=\"Sequence(1553)\",shape=box];\n\"cntrl1554\"[label=\"Sequence(1554)\",shape=box];\n\"cntrl1555\"[label=\"Sequence(1555)\",shape=box];\n\"cntrl1556\"[label=\"Assign VGPR 2:U32(1556)\"];\n\"cntrl1557\"[label=\"Sequence(1557)\",shape=box];\n\"cntrl1558\"[label=\"Sequence(1558)\",shape=box];\n\"cntrl1559\"[label=\"NOP(1559)\"];\n\"cntrl1560\"[label=\"NOP(1560)\"];\n\"cntrl1562\"[label=\"Body(1562)\",shape=box];\n\"cntrl1563\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563)\"];\n\"cntrl1564\"[label=\"Assign VGPR 16:U32(1564)\"];\n\"cntrl1565\"[label=\"Sequence(1565)\",shape=box];\n\"cntrl1567\"[label=\"Sequence(1567)\",shape=box];\n\"cntrl1568\"[label=\"Assign VGPR 2:U32(1568)\"];\n\"cntrl1569\"[label=\"Sequence(1569)\",shape=box];\n\"cntrl1570\"[label=\"Sequence(1570)\",shape=box];\n\"cntrl1571\"[label=\"Sequence(1571)\",shape=box];\n\"cntrl1572\"[label=\"Sequence(1572)\",shape=box];\n\"cntrl1573\"[label=\"Sequence(1573)\",shape=box];\n\"cntrl1574\"[label=\"Sequence(1574)\",shape=box];\n\"cntrl1575\"[label=\"Sequence(1575)\",shape=box];\n\"cntrl1576\"[label=\"Sequence(1576)\",shape=box];\n\"cntrl1577\"[label=\"Sequence(1577)\",shape=box];\n\"cntrl1578\"[label=\"Sequence(1578)\",shape=box];\n\"cntrl1579\"[label=\"Sequence(1579)\",shape=box];\n\"cntrl1580\"[label=\"Sequence(1580)\",shape=box];\n\"cntrl1581\"[label=\"Sequence(1581)\",shape=box];\n\"cntrl1582\"[label=\"Sequence(1582)\",shape=box];\n\"cntrl1583\"[label=\"Sequence(1583)\",shape=box];\n\"cntrl1584\"[label=\"Sequence(1584)\",shape=box];\n\"cntrl1585\"[label=\"Sequence(1585)\",shape=box];\n\"cntrl1586\"[label=\"Body(1586)\",shape=box];\n\"cntrl1595\"[label=\"Body(1595)\",shape=box];\n\"cntrl1629\"[label=\"Sequence(1629)\",shape=box];\n\"cntrl1630\"[label=\"Sequence(1630)\",shape=box];\n\"cntrl1631\"[label=\"Sequence(1631)\",shape=box];\n\"cntrl1632\"[label=\"Sequence(1632)\",shape=box];\n\"cntrl1633\"[label=\"Sequence(1633)\",shape=box];\n\"cntrl1634\"[label=\"Sequence(1634)\",shape=box];\n\"cntrl1635\"[label=\"Sequence(1635)\",shape=box];\n\"cntrl1660\"[label=\"Sequence(1660)\",shape=box];\n\"cntrl1668\"[label=\"Sequence(1668)\",shape=box];\n\"cntrl1670\"[label=\"Sequence(1670)\",shape=box];\n\"cntrl1672\"[label=\"Sequence(1672)\",shape=box];\n\"cntrl1674\"[label=\"Sequence(1674)\",shape=box];\n\"cntrl1723\"[label=\"Barrier(1723)\"];\n\"cntrl1724\"[label=\"Sequence(1724)\",shape=box];\n\"cntrl1725\"[label=\"Sequence(1725)\",shape=box];\n\"cntrl1726\"[label=\"Barrier(1726)\"];\n\"cntrl1727\"[label=\"Body(1727)\",shape=box];\n\"cntrl1728\"[label=\"Sequence(1728)\",shape=box];\n\"cntrl1729\"[label=\"Barrier(1729)\"];\n\"cntrl1730\"[label=\"Sequence(1730)\",shape=box];\n\"cntrl1731\"[label=\"Sequence(1731)\",shape=box];\n\"cntrl1732\"[label=\"Sequence(1732)\",shape=box];\n\"cntrl1733\"[label=\"Barrier(1733)\"];\n\"cntrl1734\"[label=\"Body(1734)\",shape=box];\n\"cntrl1735\"[label=\"Sequence(1735)\",shape=box];\n\"cntrl1736\"[label=\"Barrier(1736)\"];\n\"cntrl1737\"[label=\"Sequence(1737)\",shape=box];\n\"cntrl1738\"[label=\"Sequence(1738)\",shape=box];\n\"cntrl1739\"[label=\"Barrier(1739)\"];\n\"cntrl1740\"[label=\"Sequence(1740)\",shape=box];\n\"cntrl1741\"[label=\"Sequence(1741)\",shape=box];\n\"cntrl1742\"[label=\"Sequence(1742)\",shape=box];\n\"cntrl1743\"[label=\"Barrier(1743)\"];\n\"cntrl1744\"[label=\"Sequence(1744)\",shape=box];\n\"cntrl1745\"[label=\"Sequence(1745)\",shape=box];\n\"cntrl1746\"[label=\"Barrier(1746)\"];\n\"cntrl1747\"[label=\"Sequence(1747)\",shape=box];\n\"cntrl1748\"[label=\"Sequence(1748)\",shape=box];\n\"cntrl1749\"[label=\"Barrier(1749)\"];\n\"cntrl1750\"[label=\"Sequence(1750)\",shape=box];\n\"cntrl1751\"[label=\"Sequence(1751)\",shape=box];\n\"cntrl1752\"[label=\"Barrier(1752)\"];\n\"cntrl1753\"[label=\"Sequence(1753)\",shape=box];\n\"cntrl1754\"[label=\"Sequence(1754)\",shape=box];\n\"cntrl1755\"[label=\"Barrier(1755)\"];\n\"cntrl1757\"[label=\"Sequence(1757)\",shape=box];\n\"cntrl1758\"[label=\"Barrier(1758)\"];\n\"cntrl1759\"[label=\"Sequence(1759)\",shape=box];\n\"cntrl1760\"[label=\"Sequence(1760)\",shape=box];\n\"cntrl1761\"[label=\"Deallocate{}(1761)\"];\n\"cntrl1762\"[label=\"Sequence(1762)\",shape=box];\n\"cntrl1763\"[label=\"Deallocate{}(1763)\"];\n\"cntrl1764\"[label=\"Sequence(1764)\",shape=box];\n\"cntrl1765\"[label=\"Deallocate{}(1765)\"];\n\"cntrl1766\"[label=\"Sequence(1766)\",shape=box];\n\"cntrl1767\"[label=\"Barrier(1767)\"];\n\"cntrl1768\"[label=\"Sequence(1768)\",shape=box];\n\"cntrl1769\"[label=\"Deallocate{}(1769)\"];\n\"cntrl1770\"[label=\"Sequence(1770)\",shape=box];\n\"cntrl1771\"[label=\"Deallocate{}(1771)\"];\n\"cntrl1772\"[label=\"Sequence(1772)\",shape=box];\n\"cntrl1773\"[label=\"Deallocate{}(1773)\"];\n\"cntrl1774\"[label=\"Sequence(1774)\",shape=box];\n\"cntrl1775\"[label=\"Deallocate{}(1775)\"];\n\"cntrl1776\"[label=\"Sequence(1776)\",shape=box];\n\"cntrl1777\"[label=\"Deallocate{Tensor_4_stride_1_13}(1777)\"];\n\"cntrl1778\"[label=\"Sequence(1778)\",shape=box];\n\"cntrl1779\"[label=\"Deallocate{}(1779)\"];\n\"cntrl1780\"[label=\"Sequence(1780)\",shape=box];\n\"cntrl1781\"[label=\"Deallocate{}(1781)\"];\n\"cntrl1782\"[label=\"Sequence(1782)\",shape=box];\n\"cntrl1783\"[label=\"Deallocate{}(1783)\"];\n\"cntrl1784\"[label=\"Sequence(1784)\",shape=box];\n\"cntrl1785\"[label=\"Deallocate{}(1785)\"];\n\"cntrl1786\"[label=\"Sequence(1786)\",shape=box];\n\"cntrl1787\"[label=\"Deallocate{}(1787)\"];\n\"cntrl1788\"[label=\"Sequence(1788)\",shape=box];\n\"cntrl1789\"[label=\"Deallocate{}(1789)\"];\n\"cntrl1790\"[label=\"Sequence(1790)\",shape=box];\n\"cntrl1791\"[label=\"Deallocate{}(1791)\"];\n\"cntrl1792\"[label=\"Sequence(1792)\",shape=box];\n\"cntrl1793\"[label=\"Deallocate{}(1793)\"];\n\"cntrl1794\"[label=\"Sequence(1794)\",shape=box];\n\"cntrl1795\"[label=\"Deallocate{}(1795)\"];\n\"cntrl1796\"[label=\"Sequence(1796)\",shape=box];\n\"cntrl1797\"[label=\"Deallocate{}(1797)\"];\n\"cntrl1798\"[label=\"Sequence(1798)\",shape=box];\n\"cntrl1799\"[label=\"Deallocate{}(1799)\"];\n\"cntrl1800\"[label=\"Sequence(1800)\",shape=box];\n\"cntrl1801\"[label=\"Barrier(1801)\"];\n\"cntrl1802\"[label=\"Sequence(1802)\",shape=box];\n\"cntrl1803\"[label=\"Deallocate{}(1803)\"];\n\"cntrl1804\"[label=\"Sequence(1804)\",shape=box];\n\"cntrl1805\"[label=\"Deallocate{}(1805)\"];\n\"cntrl1806\"[label=\"Sequence(1806)\",shape=box];\n\"cntrl1807\"[label=\"Deallocate{}(1807)\"];\n\"cntrl1808\"[label=\"Sequence(1808)\",shape=box];\n\"cntrl1809\"[label=\"Deallocate{}(1809)\"];\n\"cntrl1810\"[label=\"Sequence(1810)\",shape=box];\n\"cntrl1811\"[label=\"Deallocate{}(1811)\"];\n\"cntrl1812\"[label=\"Sequence(1812)\",shape=box];\n\"cntrl1813\"[label=\"Deallocate{}(1813)\"];\n\"cntrl1814\"[label=\"Sequence(1814)\",shape=box];\n\"cntrl1815\"[label=\"Deallocate{}(1815)\"];\n\"cntrl1816\"[label=\"Sequence(1816)\",shape=box];\n\"cntrl1817\"[label=\"Deallocate{}(1817)\"];\n\"cntrl1818\"[label=\"Sequence(1818)\",shape=box];\n\"cntrl1819\"[label=\"Deallocate{}(1819)\"];\n\"cntrl1820\"[label=\"Sequence(1820)\",shape=box];\n\"cntrl1821\"[label=\"Deallocate{}(1821)\"];\n\"cntrl1822\"[label=\"Sequence(1822)\",shape=box];\n\"cntrl1823\"[label=\"Deallocate{}(1823)\"];\n\"cntrl1824\"[label=\"Sequence(1824)\",shape=box];\n\"cntrl1825\"[label=\"Deallocate{}(1825)\"];\n\"cntrl1826\"[label=\"Sequence(1826)\",shape=box];\n\"cntrl1827\"[label=\"Deallocate{}(1827)\"];\n\"cntrl1828\"[label=\"Sequence(1828)\",shape=box];\n\"cntrl1829\"[label=\"Deallocate{}(1829)\"];\n\"cntrl1830\"[label=\"Sequence(1830)\",shape=box];\n\"cntrl1831\"[label=\"Deallocate{}(1831)\"];\n\"cntrl1832\"[label=\"Sequence(1832)\",shape=box];\n\"cntrl1833\"[label=\"Deallocate{}(1833)\"];\n\"cntrl1834\"[label=\"Sequence(1834)\",shape=box];\n\"cntrl1835\"[label=\"Deallocate{}(1835)\"];\n\"cntrl1836\"[label=\"Sequence(1836)\",shape=box];\n\"cntrl1837\"[label=\"Deallocate{}(1837)\"];\n\"cntrl1838\"[label=\"Sequence(1838)\",shape=box];\n\"cntrl1839\"[label=\"Deallocate{}(1839)\"];\n\"cntrl1840\"[label=\"Sequence(1840)\",shape=box];\n\"cntrl1841\"[label=\"Deallocate{}(1841)\"];\n\"cntrl1842\"[label=\"Sequence(1842)\",shape=box];\n\"cntrl1843\"[label=\"Deallocate{}(1843)\"];\n\"cntrl1844\"[label=\"Sequence(1844)\",shape=box];\n\"cntrl1845\"[label=\"Deallocate{}(1845)\"];\n\"cntrl1846\"[label=\"Sequence(1846)\",shape=box];\n\"cntrl1847\"[label=\"Deallocate{}(1847)\"];\n\"cntrl1848\"[label=\"Sequence(1848)\",shape=box];\n\"cntrl1849\"[label=\"Deallocate{}(1849)\"];\n\"cntrl1850\"[label=\"Sequence(1850)\",shape=box];\n\"cntrl1851\"[label=\"Deallocate{}(1851)\"];\n\"cntrl1852\"[label=\"Sequence(1852)\",shape=box];\n\"cntrl1853\"[label=\"Deallocate{}(1853)\"];\n\"cntrl1854\"[label=\"Sequence(1854)\",shape=box];\n\"cntrl1855\"[label=\"Deallocate{}(1855)\"];\n\"cntrl1856\"[label=\"Sequence(1856)\",shape=box];\n\"cntrl1857\"[label=\"Deallocate{}(1857)\"];\n\"cntrl1858\"[label=\"Sequence(1858)\",shape=box];\n\"cntrl1859\"[label=\"Deallocate{}(1859)\"];\n\"cntrl1860\"[label=\"Sequence(1860)\",shape=box];\n\"cntrl1861\"[label=\"Deallocate{}(1861)\"];\n\"cntrl1862\"[label=\"Sequence(1862)\",shape=box];\n\"cntrl1863\"[label=\"Deallocate{}(1863)\"];\n\"cntrl1864\"[label=\"Sequence(1864)\",shape=box];\n\"cntrl1865\"[label=\"Deallocate{}(1865)\"];\n\"cntrl1866\"[label=\"Sequence(1866)\",shape=box];\n\"cntrl1867\"[label=\"Deallocate{}(1867)\"];\n\"cntrl1868\"[label=\"Sequence(1868)\",shape=box];\n\"cntrl1869\"[label=\"Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869)\"];\n\"cntrl1870\"[label=\"Sequence(1870)\",shape=box];\n\"cntrl1871\"[label=\"Deallocate{}(1871)\"];\n\"cntrl1872\"[label=\"Sequence(1872)\",shape=box];\n\"cntrl1873\"[label=\"Deallocate{}(1873)\"];\n\"cntrl1874\"[label=\"Sequence(1874)\",shape=box];\n\"cntrl1875\"[label=\"Deallocate{}(1875)\"];\n\"cntrl1876\"[label=\"Sequence(1876)\",shape=box];\n\"cntrl1877\"[label=\"Deallocate{}(1877)\"];\n\"cntrl1878\"[label=\"Sequence(1878)\",shape=box];\n\"cntrl1879\"[label=\"Deallocate{}(1879)\"];\n\"cntrl1880\"[label=\"Sequence(1880)\",shape=box];\n\"cntrl1881\"[label=\"Deallocate{}(1881)\"];\n\"cntrl1882\"[label=\"Sequence(1882)\",shape=box];\n\"cntrl1883\"[label=\"Deallocate{}(1883)\"];\n\"cntrl1884\"[label=\"Sequence(1884)\",shape=box];\n\"cntrl1885\"[label=\"Deallocate{}(1885)\"];\n\"cntrl1886\"[label=\"Sequence(1886)\",shape=box];\n\"cntrl1887\"[label=\"Deallocate{}(1887)\"];\n\"cntrl1888\"[label=\"Sequence(1888)\",shape=box];\n\"cntrl1889\"[label=\"Deallocate{}(1889)\"];\n\"cntrl1890\"[label=\"Sequence(1890)\",shape=box];\n\"cntrl1891\"[label=\"Deallocate{}(1891)\"];\n\"cntrl1892\"[label=\"Sequence(1892)\",shape=box];\n\"cntrl1893\"[label=\"Deallocate{}(1893)\"];\n\"cntrl1894\"[label=\"Sequence(1894)\",shape=box];\n\"cntrl1895\"[label=\"Deallocate{}(1895)\"];\n\"cntrl1896\"[label=\"Sequence(1896)\",shape=box];\n\"cntrl1897\"[label=\"Deallocate{}(1897)\"];\n\"cntrl1898\"[label=\"Sequence(1898)\",shape=box];\n\"cntrl1899\"[label=\"Deallocate{}(1899)\"];\n\"cntrl1900\"[label=\"Sequence(1900)\",shape=box];\n\"cntrl1901\"[label=\"Deallocate{}(1901)\"];\n\"cntrl1902\"[label=\"Sequence(1902)\",shape=box];\n\"cntrl1903\"[label=\"Deallocate{}(1903)\"];\n\"cntrl1904\"[label=\"Sequence(1904)\",shape=box];\n\"cntrl1905\"[label=\"Deallocate{}(1905)\"];\n\"cntrl1906\"[label=\"Sequence(1906)\",shape=box];\n\"cntrl1907\"[label=\"Deallocate{}(1907)\"];\n\"cntrl1908\"[label=\"Sequence(1908)\",shape=box];\n\"cntrl1909\"[label=\"Deallocate{}(1909)\"];\n\"cntrl1910\"[label=\"Sequence(1910)\",shape=box];\n\"cntrl1911\"[label=\"Deallocate{}(1911)\"];\n\"cntrl1912\"[label=\"Sequence(1912)\",shape=box];\n\"cntrl1913\"[label=\"Deallocate{}(1913)\"];\n\"cntrl1914\"[label=\"Sequence(1914)\",shape=box];\n\"cntrl1915\"[label=\"Sequence(1915)\",shape=box];\n\"cntrl1916\"[label=\"Sequence(1916)\",shape=box];\n\"cntrl1917\"[label=\"Sequence(1917)\",shape=box];\n\"cntrl1918\"[label=\"Deallocate{}(1918)\"];\n\"cntrl1919\"[label=\"Sequence(1919)\",shape=box];\n\"cntrl1920\"[label=\"Sequence(1920)\",shape=box];\n\"cntrl1921\"[label=\"Sequence(1921)\",shape=box];\n\"cntrl1922\"[label=\"Sequence(1922)\",shape=box];\n\"cntrl1923\"[label=\"Sequence(1923)\",shape=box];\n\"cntrl1924\"[label=\"Sequence(1924)\",shape=box];\n\"cntrl1925\"[label=\"Sequence(1925)\",shape=box];\n\"cntrl1926\"[label=\"Sequence(1926)\",shape=box];\n\"cntrl1927\"[label=\"Sequence(1927)\",shape=box];\n\"cntrl1928\"[label=\"Sequence(1928)\",shape=box];\n\"cntrl1929\"[label=\"Sequence(1929)\",shape=box];\n\"cntrl1930\"[label=\"Sequence(1930)\",shape=box];\n\"cntrl1931\"[label=\"Sequence(1931)\",shape=box];\n\"cntrl1932\"[label=\"Sequence(1932)\",shape=box];\n\"cntrl1933\"[label=\"Sequence(1933)\",shape=box];\n\"cntrl1934\"[label=\"Sequence(1934)\",shape=box];\n\"cntrl1935\"[label=\"Sequence(1935)\",shape=box];\n\"cntrl1936\"[label=\"Sequence(1936)\",shape=box];\n\"cntrl1937\"[label=\"Sequence(1937)\",shape=box];\n\"cntrl1938\"[label=\"Sequence(1938)\",shape=box];\n\"cntrl1939\"[label=\"Sequence(1939)\",shape=box];\n\"cntrl1940\"[label=\"Sequence(1940)\",shape=box];\n\"cntrl1941\"[label=\"Sequence(1941)\",shape=box];\n\"cntrl1942\"[label=\"Sequence(1942)\",shape=box];\n\"cntrl1943\"[label=\"Sequence(1943)\",shape=box];\n\"cntrl1944\"[label=\"Sequence(1944)\",shape=box];\n\"cntrl1945\"[label=\"Sequence(1945)\",shape=box];\n\"cntrl1946\"[label=\"Sequence(1946)\",shape=box];\n\"cntrl1947\"[label=\"Sequence(1947)\",shape=box];\n\"cntrl1948\"[label=\"Sequence(1948)\",shape=box];\n\"cntrl1949\"[label=\"Sequence(1949)\",shape=box];\n\"cntrl1950\"[label=\"Sequence(1950)\",shape=box];\n\"cntrl1951\"[label=\"Sequence(1951)\",shape=box];\n\"cntrl1952\"[label=\"Sequence(1952)\",shape=box];\n\"cntrl1953\"[label=\"Sequence(1953)\",shape=box];\n\"cntrl1954\"[label=\"Sequence(1954)\",shape=box];\n\"cntrl1955\"[label=\"Sequence(1955)\",shape=box];\n\"cntrl1956\"[label=\"Sequence(1956)\",shape=box];\n\"cntrl1957\"[label=\"Sequence(1957)\",shape=box];\n\"cntrl1958\"[label=\"Sequence(1958)\",shape=box];\n\"cntrl1959\"[label=\"Sequence(1959)\",shape=box];\n\"cntrl1960\"[label=\"Sequence(1960)\",shape=box];\n\"cntrl1961\"[label=\"Sequence(1961)\",shape=box];\n\"cntrl1962\"[label=\"Sequence(1962)\",shape=box];\n\"cntrl1963\"[label=\"Sequence(1963)\",shape=box];\n\"cntrl1964\"[label=\"Sequence(1964)\",shape=box];\n\"cntrl1965\"[label=\"Sequence(1965)\",shape=box];\n\"cntrl1966\"[label=\"Sequence(1966)\",shape=box];\n\"cntrl1967\"[label=\"Sequence(1967)\",shape=box];\n\"cntrl1968\"[label=\"Sequence(1968)\",shape=box];\n\"cntrl1969\"[label=\"Sequence(1969)\",shape=box];\n\"cntrl1970\"[label=\"Sequence(1970)\",shape=box];\n\"cntrl1971\"[label=\"Sequence(1971)\",shape=box];\n\"cntrl1972\"[label=\"Sequence(1972)\",shape=box];\n\"cntrl1973\"[label=\"Sequence(1973)\",shape=box];\n\"cntrl1974\"[label=\"Sequence(1974)\",shape=box];\n\"cntrl1975\"[label=\"Sequence(1975)\",shape=box];\n\"cntrl1976\"[label=\"Sequence(1976)\",shape=box];\n\"cntrl1977\"[label=\"Sequence(1977)\",shape=box];\n\"cntrl1978\"[label=\"Sequence(1978)\",shape=box];\n\"cntrl1979\"[label=\"Sequence(1979)\",shape=box];\n\"cntrl1980\"[label=\"Sequence(1980)\",shape=box];\n\"cntrl1981\"[label=\"Sequence(1981)\",shape=box];\n\"cntrl1982\"[label=\"Sequence(1982)\",shape=box];\n\"cntrl1983\"[label=\"Sequence(1983)\",shape=box];\n\"cntrl1984\"[label=\"Sequence(1984)\",shape=box];\n\"cntrl1985\"[label=\"Sequence(1985)\",shape=box];\n\"cntrl1986\"[label=\"Sequence(1986)\",shape=box];\n\"cntrl1987\"[label=\"Sequence(1987)\",shape=box];\n\"cntrl1988\"[label=\"Sequence(1988)\",shape=box];\n\"cntrl1989\"[label=\"Sequence(1989)\",shape=box];\n\"cntrl1990\"[label=\"Sequence(1990)\",shape=box];\n\"cntrl1991\"[label=\"Sequence(1991)\",shape=box];\n\"cntrl1992\"[label=\"Sequence(1992)\",shape=box];\n\"cntrl1993\"[label=\"Sequence(1993)\",shape=box];\n\"cntrl1994\"[label=\"Sequence(1994)\",shape=box];\n\"cntrl1995\"[label=\"Sequence(1995)\",shape=box];\n\"cntrl1996\"[label=\"Sequence(1996)\",shape=box];\n\"cntrl1997\"[label=\"Deallocate{user_Float_Value_8}(1997)\"];\n\"cntrl1998\"[label=\"Sequence(1998)\",shape=box];\n\"cntrl1999\"[label=\"Deallocate{user_Float_Value_6}(1999)\"];\n\"cntrl2000\"[label=\"Sequence(2000)\",shape=box];\n\"cntrl2003\"[label=\"Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003)\"];\n\"cntrl2004\"[label=\"Sequence(2004)\",shape=box];\n\"cntrl2007\"[label=\"Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007)\"];\n\"cntrl2008\"[label=\"Sequence(2008)\",shape=box];\n\"cntrl2009\"[label=\"Sequence(2009)\",shape=box];\n\"cntrl2010\"[label=\"Sequence(2010)\",shape=box];\n\"cntrl2011\"[label=\"Sequence(2011)\",shape=box];\n\"cntrl1\" -> \"cntrl1242\"\n\"cntrl1\" -> \"cntrl1294\"\n\"cntrl1\" -> \"cntrl1367\"\n\"cntrl1\" -> \"cntrl1406\"\n\"cntrl1\" -> \"cntrl1445\"\n\"cntrl1\" -> \"cntrl1484\"\n\"cntrl1\" -> \"cntrl1523\"\n\"cntrl1\" -> \"cntrl1562\"\n\"cntrl2\" -> \"cntrl1998\"\n\"cntrl24\" -> \"cntrl2000\"\n\"cntrl29\" -> \"cntrl668\"\n\"cntrl35\" -> \"cntrl1762\"\n\"cntrl37\" -> \"cntrl1764\"\n\"cntrl39\" -> \"cntrl42\"\n\"cntrl39\" -> \"cntrl810\"\n\"cntrl39\" -> \"cntrl816\"\n\"cntrl39\" -> \"cntrl1586\"\n\"cntrl39\" -> \"cntrl1734\"\n\"cntrl39\" -> \"cntrl1766\"\n\"cntrl42\" -> \"cntrl40\"\n\"cntrl44\" -> \"cntrl1075\"\n\"cntrl47\" -> \"cntrl50\"\n\"cntrl47\" -> \"cntrl955\"\n\"cntrl50\" -> \"cntrl49\"\n\"cntrl52\" -> \"cntrl55\"\n\"cntrl52\" -> \"cntrl947\"\n\"cntrl55\" -> \"cntrl54\"\n\"cntrl57\" -> \"cntrl1629\"\n\"cntrl57\" -> \"cntrl1660\"\n\"cntrl58\" -> \"cntrl61\"\n\"cntrl58\" -> \"cntrl956\"\n\"cntrl61\" -> \"cntrl60\"\n\"cntrl62\" -> \"cntrl65\"\n\"cntrl62\" -> \"cntrl948\"\n\"cntrl65\" -> \"cntrl64\"\n\"cntrl66\" -> \"cntrl1630\"\n\"cntrl66\" -> \"cntrl1668\"\n\"cntrl67\" -> \"cntrl70\"\n\"cntrl67\" -> \"cntrl957\"\n\"cntrl70\" -> \"cntrl69\"\n\"cntrl71\" -> \"cntrl74\"\n\"cntrl71\" -> \"cntrl949\"\n\"cntrl74\" -> \"cntrl73\"\n\"cntrl75\" -> \"cntrl1631\"\n\"cntrl75\" -> \"cntrl1670\"\n\"cntrl76\" -> \"cntrl79\"\n\"cntrl76\" -> \"cntrl958\"\n\"cntrl79\" -> \"cntrl78\"\n\"cntrl80\" -> \"cntrl83\"\n\"cntrl80\" -> \"cntrl950\"\n\"cntrl83\" -> \"cntrl82\"\n\"cntrl84\" -> \"cntrl1632\"\n\"cntrl84\" -> \"cntrl1672\"\n\"cntrl85\" -> \"cntrl88\"\n\"cntrl85\" -> \"cntrl959\"\n\"cntrl88\" -> \"cntrl87\"\n\"cntrl89\" -> \"cntrl92\"\n\"cntrl89\" -> \"cntrl951\"\n\"cntrl92\" -> \"cntrl91\"\n\"cntrl93\" -> \"cntrl1633\"\n\"cntrl93\" -> \"cntrl1674\"\n\"cntrl94\" -> \"cntrl97\"\n\"cntrl94\" -> \"cntrl960\"\n\"cntrl97\" -> \"cntrl96\"\n\"cntrl98\" -> \"cntrl101\"\n\"cntrl98\" -> \"cntrl952\"\n\"cntrl101\" -> \"cntrl100\"\n\"cntrl102\" -> \"cntrl1634\"\n\"cntrl103\" -> \"cntrl106\"\n\"cntrl103\" -> \"cntrl961\"\n\"cntrl106\" -> \"cntrl105\"\n\"cntrl107\" -> \"cntrl110\"\n\"cntrl107\" -> \"cntrl953\"\n\"cntrl110\" -> \"cntrl109\"\n\"cntrl111\" -> \"cntrl1635\"\n\"cntrl112\" -> \"cntrl115\"\n\"cntrl112\" -> \"cntrl962\"\n\"cntrl115\" -> \"cntrl114\"\n\"cntrl116\" -> \"cntrl119\"\n\"cntrl116\" -> \"cntrl954\"\n\"cntrl119\" -> \"cntrl118\"\n\"cntrl120\" -> \"cntrl844\"\n\"cntrl177\" -> \"cntrl679\"\n\"cntrl177\" -> \"cntrl685\"\n\"cntrl177\" -> \"cntrl1770\"\n\"cntrl185\" -> \"cntrl203\"\n\"cntrl185\" -> \"cntrl1182\"\n\"cntrl186\" -> \"cntrl194\"\n\"cntrl187\" -> \"cntrl1772\"\n\"cntrl188\" -> \"cntrl1774\"\n\"cntrl189\" -> \"cntrl1776\"\n\"cntrl190\" -> \"cntrl1778\"\n\"cntrl191\" -> \"cntrl1780\"\n\"cntrl194\" -> \"cntrl187\"\n\"cntrl203\" -> \"cntrl186\"\n\"cntrl217\" -> \"cntrl220\"\n\"cntrl217\" -> \"cntrl1595\"\n\"cntrl217\" -> \"cntrl1727\"\n\"cntrl217\" -> \"cntrl1782\"\n\"cntrl220\" -> \"cntrl218\"\n\"cntrl224\" -> \"cntrl273\"\n\"cntrl224\" -> \"cntrl1740\"\n\"cntrl226\" -> \"cntrl275\"\n\"cntrl226\" -> \"cntrl276\"\n\"cntrl228\" -> \"cntrl1784\"\n\"cntrl229\" -> \"cntrl278\"\n\"cntrl229\" -> \"cntrl279\"\n\"cntrl231\" -> \"cntrl280\"\n\"cntrl231\" -> \"cntrl281\"\n\"cntrl233\" -> \"cntrl1786\"\n\"cntrl234\" -> \"cntrl283\"\n\"cntrl234\" -> \"cntrl284\"\n\"cntrl236\" -> \"cntrl285\"\n\"cntrl236\" -> \"cntrl286\"\n\"cntrl238\" -> \"cntrl1788\"\n\"cntrl239\" -> \"cntrl288\"\n\"cntrl239\" -> \"cntrl289\"\n\"cntrl241\" -> \"cntrl290\"\n\"cntrl241\" -> \"cntrl291\"\n\"cntrl243\" -> \"cntrl1790\"\n\"cntrl244\" -> \"cntrl293\"\n\"cntrl244\" -> \"cntrl294\"\n\"cntrl246\" -> \"cntrl295\"\n\"cntrl246\" -> \"cntrl296\"\n\"cntrl248\" -> \"cntrl1792\"\n\"cntrl249\" -> \"cntrl298\"\n\"cntrl249\" -> \"cntrl299\"\n\"cntrl251\" -> \"cntrl300\"\n\"cntrl251\" -> \"cntrl301\"\n\"cntrl253\" -> \"cntrl1794\"\n\"cntrl254\" -> \"cntrl303\"\n\"cntrl254\" -> \"cntrl304\"\n\"cntrl256\" -> \"cntrl305\"\n\"cntrl256\" -> \"cntrl306\"\n\"cntrl258\" -> \"cntrl1796\"\n\"cntrl259\" -> \"cntrl308\"\n\"cntrl259\" -> \"cntrl309\"\n\"cntrl261\" -> \"cntrl310\"\n\"cntrl261\" -> \"cntrl311\"\n\"cntrl263\" -> \"cntrl1798\"\n\"cntrl273\" -> \"cntrl225\"\n\"cntrl275\" -> \"cntrl227\"\n\"cntrl276\" -> \"cntrl228\"\n\"cntrl278\" -> \"cntrl230\"\n\"cntrl279\" -> \"cntrl231\"\n\"cntrl280\" -> \"cntrl232\"\n\"cntrl281\" -> \"cntrl233\"\n\"cntrl283\" -> \"cntrl235\"\n\"cntrl284\" -> \"cntrl236\"\n\"cntrl285\" -> \"cntrl237\"\n\"cntrl286\" -> \"cntrl238\"\n\"cntrl288\" -> \"cntrl240\"\n\"cntrl289\" -> \"cntrl241\"\n\"cntrl290\" -> \"cntrl242\"\n\"cntrl291\" -> \"cntrl243\"\n\"cntrl293\" -> \"cntrl245\"\n\"cntrl294\" -> \"cntrl246\"\n\"cntrl295\" -> \"cntrl247\"\n\"cntrl296\" -> \"cntrl248\"\n\"cntrl298\" -> \"cntrl250\"\n\"cntrl299\" -> \"cntrl251\"\n\"cntrl300\" -> \"cntrl252\"\n\"cntrl301\" -> \"cntrl253\"\n\"cntrl303\" -> \"cntrl255\"\n\"cntrl304\" -> \"cntrl256\"\n\"cntrl305\" -> \"cntrl257\"\n\"cntrl306\" -> \"cntrl258\"\n\"cntrl308\" -> \"cntrl260\"\n\"cntrl309\" -> \"cntrl261\"\n\"cntrl310\" -> \"cntrl262\"\n\"cntrl311\" -> \"cntrl263\"\n\"cntrl313\" -> \"cntrl315\"\n\"cntrl313\" -> \"cntrl1800\"\n\"cntrl313\" -> \"cntrl2004\"\n\"cntrl314\" -> \"cntrl1052\"\n\"cntrl315\" -> \"cntrl314\"\n\"cntrl318\" -> \"cntrl982\"\n\"cntrl318\" -> \"cntrl984\"\n\"cntrl318\" -> \"cntrl1737\"\n\"cntrl323\" -> \"cntrl988\"\n\"cntrl323\" -> \"cntrl990\"\n\"cntrl323\" -> \"cntrl1730\"\n\"cntrl330\" -> \"cntrl379\"\n\"cntrl330\" -> \"cntrl829\"\n\"cntrl332\" -> \"cntrl381\"\n\"cntrl332\" -> \"cntrl821\"\n\"cntrl334\" -> \"cntrl1804\"\n\"cntrl335\" -> \"cntrl384\"\n\"cntrl335\" -> \"cntrl830\"\n\"cntrl337\" -> \"cntrl386\"\n\"cntrl337\" -> \"cntrl822\"\n\"cntrl339\" -> \"cntrl1806\"\n\"cntrl340\" -> \"cntrl389\"\n\"cntrl340\" -> \"cntrl831\"\n\"cntrl342\" -> \"cntrl391\"\n\"cntrl342\" -> \"cntrl823\"\n\"cntrl344\" -> \"cntrl1808\"\n\"cntrl345\" -> \"cntrl394\"\n\"cntrl345\" -> \"cntrl832\"\n\"cntrl347\" -> \"cntrl396\"\n\"cntrl347\" -> \"cntrl824\"\n\"cntrl349\" -> \"cntrl1810\"\n\"cntrl350\" -> \"cntrl399\"\n\"cntrl350\" -> \"cntrl833\"\n\"cntrl352\" -> \"cntrl401\"\n\"cntrl352\" -> \"cntrl825\"\n\"cntrl354\" -> \"cntrl1812\"\n\"cntrl355\" -> \"cntrl404\"\n\"cntrl355\" -> \"cntrl834\"\n\"cntrl357\" -> \"cntrl406\"\n\"cntrl357\" -> \"cntrl826\"\n\"cntrl359\" -> \"cntrl1814\"\n\"cntrl360\" -> \"cntrl409\"\n\"cntrl360\" -> \"cntrl835\"\n\"cntrl362\" -> \"cntrl411\"\n\"cntrl362\" -> \"cntrl827\"\n\"cntrl364\" -> \"cntrl1816\"\n\"cntrl365\" -> \"cntrl414\"\n\"cntrl365\" -> \"cntrl1818\"\n\"cntrl367\" -> \"cntrl416\"\n\"cntrl367\" -> \"cntrl1820\"\n\"cntrl369\" -> \"cntrl1822\"\n\"cntrl379\" -> \"cntrl331\"\n\"cntrl381\" -> \"cntrl333\"\n\"cntrl384\" -> \"cntrl336\"\n\"cntrl386\" -> \"cntrl338\"\n\"cntrl389\" -> \"cntrl341\"\n\"cntrl391\" -> \"cntrl343\"\n\"cntrl394\" -> \"cntrl346\"\n\"cntrl396\" -> \"cntrl348\"\n\"cntrl399\" -> \"cntrl351\"\n\"cntrl401\" -> \"cntrl353\"\n\"cntrl404\" -> \"cntrl356\"\n\"cntrl406\" -> \"cntrl358\"\n\"cntrl409\" -> \"cntrl361\"\n\"cntrl411\" -> \"cntrl363\"\n\"cntrl414\" -> \"cntrl366\"\n\"cntrl416\" -> \"cntrl368\"\n\"cntrl420\" -> \"cntrl469\"\n\"cntrl420\" -> \"cntrl871\"\n\"cntrl422\" -> \"cntrl471\"\n\"cntrl422\" -> \"cntrl863\"\n\"cntrl424\" -> \"cntrl1824\"\n\"cntrl425\" -> \"cntrl474\"\n\"cntrl425\" -> \"cntrl872\"\n\"cntrl427\" -> \"cntrl476\"\n\"cntrl427\" -> \"cntrl864\"\n\"cntrl429\" -> \"cntrl1826\"\n\"cntrl430\" -> \"cntrl479\"\n\"cntrl430\" -> \"cntrl873\"\n\"cntrl432\" -> \"cntrl481\"\n\"cntrl432\" -> \"cntrl865\"\n\"cntrl434\" -> \"cntrl1828\"\n\"cntrl435\" -> \"cntrl484\"\n\"cntrl435\" -> \"cntrl874\"\n\"cntrl437\" -> \"cntrl486\"\n\"cntrl437\" -> \"cntrl866\"\n\"cntrl439\" -> \"cntrl1830\"\n\"cntrl440\" -> \"cntrl489\"\n\"cntrl440\" -> \"cntrl875\"\n\"cntrl442\" -> \"cntrl491\"\n\"cntrl442\" -> \"cntrl867\"\n\"cntrl444\" -> \"cntrl1832\"\n\"cntrl445\" -> \"cntrl494\"\n\"cntrl445\" -> \"cntrl876\"\n\"cntrl447\" -> \"cntrl496\"\n\"cntrl447\" -> \"cntrl868\"\n\"cntrl449\" -> \"cntrl1834\"\n\"cntrl450\" -> \"cntrl499\"\n\"cntrl450\" -> \"cntrl877\"\n\"cntrl452\" -> \"cntrl501\"\n\"cntrl452\" -> \"cntrl869\"\n\"cntrl454\" -> \"cntrl1836\"\n\"cntrl455\" -> \"cntrl504\"\n\"cntrl455\" -> \"cntrl1838\"\n\"cntrl457\" -> \"cntrl506\"\n\"cntrl457\" -> \"cntrl1840\"\n\"cntrl459\" -> \"cntrl1842\"\n\"cntrl469\" -> \"cntrl421\"\n\"cntrl471\" -> \"cntrl423\"\n\"cntrl474\" -> \"cntrl426\"\n\"cntrl476\" -> \"cntrl428\"\n\"cntrl479\" -> \"cntrl431\"\n\"cntrl481\" -> \"cntrl433\"\n\"cntrl484\" -> \"cntrl436\"\n\"cntrl486\" -> \"cntrl438\"\n\"cntrl489\" -> \"cntrl441\"\n\"cntrl491\" -> \"cntrl443\"\n\"cntrl494\" -> \"cntrl446\"\n\"cntrl496\" -> \"cntrl448\"\n\"cntrl499\" -> \"cntrl451\"\n\"cntrl501\" -> \"cntrl453\"\n\"cntrl504\" -> \"cntrl456\"\n\"cntrl506\" -> \"cntrl458\"\n\"cntrl510\" -> \"cntrl559\"\n\"cntrl510\" -> \"cntrl913\"\n\"cntrl512\" -> \"cntrl561\"\n\"cntrl512\" -> \"cntrl905\"\n\"cntrl514\" -> \"cntrl1844\"\n\"cntrl515\" -> \"cntrl564\"\n\"cntrl515\" -> \"cntrl914\"\n\"cntrl517\" -> \"cntrl566\"\n\"cntrl517\" -> \"cntrl906\"\n\"cntrl519\" -> \"cntrl1846\"\n\"cntrl520\" -> \"cntrl569\"\n\"cntrl520\" -> \"cntrl915\"\n\"cntrl522\" -> \"cntrl571\"\n\"cntrl522\" -> \"cntrl907\"\n\"cntrl524\" -> \"cntrl1848\"\n\"cntrl525\" -> \"cntrl574\"\n\"cntrl525\" -> \"cntrl916\"\n\"cntrl527\" -> \"cntrl576\"\n\"cntrl527\" -> \"cntrl908\"\n\"cntrl529\" -> \"cntrl1850\"\n\"cntrl530\" -> \"cntrl579\"\n\"cntrl530\" -> \"cntrl917\"\n\"cntrl532\" -> \"cntrl581\"\n\"cntrl532\" -> \"cntrl909\"\n\"cntrl534\" -> \"cntrl1852\"\n\"cntrl535\" -> \"cntrl584\"\n\"cntrl535\" -> \"cntrl918\"\n\"cntrl537\" -> \"cntrl586\"\n\"cntrl537\" -> \"cntrl910\"\n\"cntrl539\" -> \"cntrl1854\"\n\"cntrl540\" -> \"cntrl589\"\n\"cntrl540\" -> \"cntrl919\"\n\"cntrl542\" -> \"cntrl591\"\n\"cntrl542\" -> \"cntrl911\"\n\"cntrl544\" -> \"cntrl1856\"\n\"cntrl545\" -> \"cntrl594\"\n\"cntrl545\" -> \"cntrl1858\"\n\"cntrl547\" -> \"cntrl596\"\n\"cntrl547\" -> \"cntrl1860\"\n\"cntrl549\" -> \"cntrl1862\"\n\"cntrl559\" -> \"cntrl511\"\n\"cntrl561\" -> \"cntrl513\"\n\"cntrl564\" -> \"cntrl516\"\n\"cntrl566\" -> \"cntrl518\"\n\"cntrl569\" -> \"cntrl521\"\n\"cntrl571\" -> \"cntrl523\"\n\"cntrl574\" -> \"cntrl526\"\n\"cntrl576\" -> \"cntrl528\"\n\"cntrl579\" -> \"cntrl531\"\n\"cntrl581\" -> \"cntrl533\"\n\"cntrl584\" -> \"cntrl536\"\n\"cntrl586\" -> \"cntrl538\"\n\"cntrl589\" -> \"cntrl541\"\n\"cntrl591\" -> \"cntrl543\"\n\"cntrl594\" -> \"cntrl546\"\n\"cntrl596\" -> \"cntrl548\"\n\"cntrl599\" -> \"cntrl972\"\n\"cntrl599\" -> \"cntrl1001\"\n\"cntrl604\" -> \"cntrl977\"\n\"cntrl604\" -> \"cntrl1724\"\n\"cntrl610\" -> \"cntrl994\"\n\"cntrl610\" -> \"cntrl1011\"\n\"cntrl615\" -> \"cntrl999\"\n\"cntrl615\" -> \"cntrl1744\"\n\"cntrl624\" -> \"cntrl1004\"\n\"cntrl624\" -> \"cntrl1021\"\n\"cntrl629\" -> \"cntrl1009\"\n\"cntrl629\" -> \"cntrl1750\"\n\"cntrl638\" -> \"cntrl1014\"\n\"cntrl638\" -> \"cntrl1864\"\n\"cntrl643\" -> \"cntrl1019\"\n\"cntrl643\" -> \"cntrl1866\"\n\"cntrl668\" -> \"cntrl35\"\n\"cntrl670\" -> \"cntrl676\"\n\"cntrl670\" -> \"cntrl1868\"\n\"cntrl675\" -> \"cntrl677\"\n\"cntrl676\" -> \"cntrl675\"\n\"cntrl677\" -> \"cntrl44\"\n\"cntrl678\" -> \"cntrl682\"\n\"cntrl679\" -> \"cntrl678\"\n\"cntrl681\" -> \"cntrl683\"\n\"cntrl682\" -> \"cntrl681\"\n\"cntrl683\" -> \"cntrl29\"\n\"cntrl684\" -> \"cntrl688\"\n\"cntrl684\" -> \"cntrl1870\"\n\"cntrl685\" -> \"cntrl684\"\n\"cntrl687\" -> \"cntrl689\"\n\"cntrl688\" -> \"cntrl687\"\n\"cntrl689\" -> \"cntrl185\"\n\"cntrl690\" -> \"cntrl722\"\n\"cntrl693\" -> \"cntrl781\"\n\"cntrl694\" -> \"cntrl1200\"\n\"cntrl696\" -> \"cntrl723\"\n\"cntrl696\" -> \"cntrl1280\"\n\"cntrl699\" -> \"cntrl724\"\n\"cntrl699\" -> \"cntrl1228\"\n\"cntrl702\" -> \"cntrl725\"\n\"cntrl702\" -> \"cntrl1392\"\n\"cntrl705\" -> \"cntrl726\"\n\"cntrl705\" -> \"cntrl1353\"\n\"cntrl708\" -> \"cntrl727\"\n\"cntrl708\" -> \"cntrl1470\"\n\"cntrl711\" -> \"cntrl728\"\n\"cntrl711\" -> \"cntrl1431\"\n\"cntrl714\" -> \"cntrl1548\"\n\"cntrl714\" -> \"cntrl1872\"\n\"cntrl717\" -> \"cntrl1509\"\n\"cntrl717\" -> \"cntrl1874\"\n\"cntrl722\" -> \"cntrl696\"\n\"cntrl723\" -> \"cntrl699\"\n\"cntrl724\" -> \"cntrl702\"\n\"cntrl725\" -> \"cntrl705\"\n\"cntrl726\" -> \"cntrl708\"\n\"cntrl727\" -> \"cntrl711\"\n\"cntrl728\" -> \"cntrl714\"\n\"cntrl733\" -> \"cntrl735\"\n\"cntrl733\" -> \"cntrl790\"\n\"cntrl735\" -> \"cntrl734\"\n\"cntrl736\" -> \"cntrl738\"\n\"cntrl736\" -> \"cntrl791\"\n\"cntrl738\" -> \"cntrl737\"\n\"cntrl739\" -> \"cntrl741\"\n\"cntrl739\" -> \"cntrl792\"\n\"cntrl741\" -> \"cntrl740\"\n\"cntrl742\" -> \"cntrl744\"\n\"cntrl742\" -> \"cntrl793\"\n\"cntrl744\" -> \"cntrl743\"\n\"cntrl745\" -> \"cntrl747\"\n\"cntrl745\" -> \"cntrl794\"\n\"cntrl747\" -> \"cntrl746\"\n\"cntrl748\" -> \"cntrl750\"\n\"cntrl748\" -> \"cntrl795\"\n\"cntrl750\" -> \"cntrl749\"\n\"cntrl751\" -> \"cntrl753\"\n\"cntrl751\" -> \"cntrl796\"\n\"cntrl753\" -> \"cntrl752\"\n\"cntrl754\" -> \"cntrl756\"\n\"cntrl754\" -> \"cntrl797\"\n\"cntrl756\" -> \"cntrl755\"\n\"cntrl757\" -> \"cntrl759\"\n\"cntrl757\" -> \"cntrl782\"\n\"cntrl759\" -> \"cntrl758\"\n\"cntrl760\" -> \"cntrl762\"\n\"cntrl760\" -> \"cntrl783\"\n\"cntrl762\" -> \"cntrl761\"\n\"cntrl763\" -> \"cntrl765\"\n\"cntrl763\" -> \"cntrl784\"\n\"cntrl765\" -> \"cntrl764\"\n\"cntrl766\" -> \"cntrl768\"\n\"cntrl766\" -> \"cntrl785\"\n\"cntrl768\" -> \"cntrl767\"\n\"cntrl769\" -> \"cntrl771\"\n\"cntrl769\" -> \"cntrl786\"\n\"cntrl771\" -> \"cntrl770\"\n\"cntrl772\" -> \"cntrl774\"\n\"cntrl772\" -> \"cntrl787\"\n\"cntrl774\" -> \"cntrl773\"\n\"cntrl775\" -> \"cntrl777\"\n\"cntrl775\" -> \"cntrl788\"\n\"cntrl777\" -> \"cntrl776\"\n\"cntrl778\" -> \"cntrl780\"\n\"cntrl778\" -> \"cntrl789\"\n\"cntrl780\" -> \"cntrl779\"\n\"cntrl781\" -> \"cntrl757\"\n\"cntrl782\" -> \"cntrl760\"\n\"cntrl783\" -> \"cntrl763\"\n\"cntrl784\" -> \"cntrl766\"\n\"cntrl785\" -> \"cntrl769\"\n\"cntrl786\" -> \"cntrl772\"\n\"cntrl787\" -> \"cntrl775\"\n\"cntrl788\" -> \"cntrl778\"\n\"cntrl789\" -> \"cntrl733\"\n\"cntrl790\" -> \"cntrl736\"\n\"cntrl791\" -> \"cntrl739\"\n\"cntrl792\" -> \"cntrl742\"\n\"cntrl793\" -> \"cntrl745\"\n\"cntrl794\" -> \"cntrl748\"\n\"cntrl795\" -> \"cntrl751\"\n\"cntrl796\" -> \"cntrl754\"\n\"cntrl797\" -> \"cntrl694\"\n\"cntrl799\" -> \"cntrl845\"\n\"cntrl799\" -> \"cntrl858\"\n\"cntrl799\" -> \"cntrl1747\"\n\"cntrl800\" -> \"cntrl887\"\n\"cntrl800\" -> \"cntrl900\"\n\"cntrl800\" -> \"cntrl1753\"\n\"cntrl801\" -> \"cntrl929\"\n\"cntrl801\" -> \"cntrl942\"\n\"cntrl801\" -> \"cntrl1759\"\n\"cntrl810\" -> \"cntrl57\"\n\"cntrl811\" -> \"cntrl820\"\n\"cntrl816\" -> \"cntrl811\"\n\"cntrl820\" -> \"cntrl332\"\n\"cntrl821\" -> \"cntrl337\"\n\"cntrl822\" -> \"cntrl342\"\n\"cntrl823\" -> \"cntrl347\"\n\"cntrl824\" -> \"cntrl352\"\n\"cntrl825\" -> \"cntrl357\"\n\"cntrl826\" -> \"cntrl362\"\n\"cntrl827\" -> \"cntrl367\"\n\"cntrl829\" -> \"cntrl335\"\n\"cntrl830\" -> \"cntrl340\"\n\"cntrl831\" -> \"cntrl345\"\n\"cntrl832\" -> \"cntrl350\"\n\"cntrl833\" -> \"cntrl355\"\n\"cntrl834\" -> \"cntrl360\"\n\"cntrl835\" -> \"cntrl365\"\n\"cntrl844\" -> \"cntrl799\"\n\"cntrl845\" -> \"cntrl334\"\n\"cntrl853\" -> \"cntrl862\"\n\"cntrl858\" -> \"cntrl853\"\n\"cntrl862\" -> \"cntrl422\"\n\"cntrl863\" -> \"cntrl427\"\n\"cntrl864\" -> \"cntrl432\"\n\"cntrl865\" -> \"cntrl437\"\n\"cntrl866\" -> \"cntrl442\"\n\"cntrl867\" -> \"cntrl447\"\n\"cntrl868\" -> \"cntrl452\"\n\"cntrl869\" -> \"cntrl457\"\n\"cntrl871\" -> \"cntrl425\"\n\"cntrl872\" -> \"cntrl430\"\n\"cntrl873\" -> \"cntrl435\"\n\"cntrl874\" -> \"cntrl440\"\n\"cntrl875\" -> \"cntrl445\"\n\"cntrl876\" -> \"cntrl450\"\n\"cntrl877\" -> \"cntrl455\"\n\"cntrl887\" -> \"cntrl424\"\n\"cntrl895\" -> \"cntrl904\"\n\"cntrl900\" -> \"cntrl895\"\n\"cntrl904\" -> \"cntrl512\"\n\"cntrl905\" -> \"cntrl517\"\n\"cntrl906\" -> \"cntrl522\"\n\"cntrl907\" -> \"cntrl527\"\n\"cntrl908\" -> \"cntrl532\"\n\"cntrl909\" -> \"cntrl537\"\n\"cntrl910\" -> \"cntrl542\"\n\"cntrl911\" -> \"cntrl547\"\n\"cntrl913\" -> \"cntrl515\"\n\"cntrl914\" -> \"cntrl520\"\n\"cntrl915\" -> \"cntrl525\"\n\"cntrl916\" -> \"cntrl530\"\n\"cntrl917\" -> \"cntrl535\"\n\"cntrl918\" -> \"cntrl540\"\n\"cntrl919\" -> \"cntrl545\"\n\"cntrl929\" -> \"cntrl514\"\n\"cntrl937\" -> \"cntrl946\"\n\"cntrl942\" -> \"cntrl937\"\n\"cntrl946\" -> \"cntrl52\"\n\"cntrl947\" -> \"cntrl62\"\n\"cntrl948\" -> \"cntrl71\"\n\"cntrl949\" -> \"cntrl80\"\n\"cntrl950\" -> \"cntrl89\"\n\"cntrl951\" -> \"cntrl98\"\n\"cntrl952\" -> \"cntrl107\"\n\"cntrl953\" -> \"cntrl116\"\n\"cntrl954\" -> \"cntrl47\"\n\"cntrl955\" -> \"cntrl58\"\n\"cntrl956\" -> \"cntrl67\"\n\"cntrl957\" -> \"cntrl76\"\n\"cntrl958\" -> \"cntrl85\"\n\"cntrl959\" -> \"cntrl94\"\n\"cntrl960\" -> \"cntrl103\"\n\"cntrl961\" -> \"cntrl112\"\n\"cntrl962\" -> \"cntrl802\"\n\"cntrl971\" -> \"cntrl1876\"\n\"cntrl972\" -> \"cntrl971\"\n\"cntrl973\" -> \"cntrl975\"\n\"cntrl975\" -> \"cntrl802\"\n\"cntrl976\" -> \"cntrl1878\"\n\"cntrl977\" -> \"cntrl976\"\n\"cntrl978\" -> \"cntrl980\"\n\"cntrl980\" -> \"cntrl973\"\n\"cntrl981\" -> \"cntrl1880\"\n\"cntrl982\" -> \"cntrl981\"\n\"cntrl983\" -> \"cntrl991\"\n\"cntrl983\" -> \"cntrl1731\"\n\"cntrl984\" -> \"cntrl983\"\n\"cntrl987\" -> \"cntrl1882\"\n\"cntrl988\" -> \"cntrl987\"\n\"cntrl989\" -> \"cntrl1741\"\n\"cntrl990\" -> \"cntrl989\"\n\"cntrl991\" -> \"cntrl989\"\n\"cntrl993\" -> \"cntrl1884\"\n\"cntrl994\" -> \"cntrl993\"\n\"cntrl995\" -> \"cntrl997\"\n\"cntrl997\" -> \"cntrl799\"\n\"cntrl998\" -> \"cntrl1886\"\n\"cntrl999\" -> \"cntrl998\"\n\"cntrl1000\" -> \"cntrl1002\"\n\"cntrl1001\" -> \"cntrl1000\"\n\"cntrl1002\" -> \"cntrl995\"\n\"cntrl1003\" -> \"cntrl1888\"\n\"cntrl1004\" -> \"cntrl1003\"\n\"cntrl1005\" -> \"cntrl1007\"\n\"cntrl1007\" -> \"cntrl800\"\n\"cntrl1008\" -> \"cntrl1890\"\n\"cntrl1009\" -> \"cntrl1008\"\n\"cntrl1010\" -> \"cntrl1012\"\n\"cntrl1011\" -> \"cntrl1010\"\n\"cntrl1012\" -> \"cntrl1005\"\n\"cntrl1013\" -> \"cntrl1892\"\n\"cntrl1014\" -> \"cntrl1013\"\n\"cntrl1015\" -> \"cntrl1017\"\n\"cntrl1017\" -> \"cntrl801\"\n\"cntrl1018\" -> \"cntrl1894\"\n\"cntrl1019\" -> \"cntrl1018\"\n\"cntrl1020\" -> \"cntrl1022\"\n\"cntrl1021\" -> \"cntrl1020\"\n\"cntrl1022\" -> \"cntrl1015\"\n\"cntrl1023\" -> \"cntrl1896\"\n\"cntrl1025\" -> \"cntrl1031\"\n\"cntrl1028\" -> \"cntrl1898\"\n\"cntrl1030\" -> \"cntrl1032\"\n\"cntrl1031\" -> \"cntrl1030\"\n\"cntrl1032\" -> \"cntrl693\"\n\"cntrl1033\" -> \"cntrl1900\"\n\"cntrl1035\" -> \"cntrl1902\"\n\"cntrl1037\" -> \"cntrl1904\"\n\"cntrl1039\" -> \"cntrl1906\"\n\"cntrl1041\" -> \"cntrl1908\"\n\"cntrl1043\" -> \"cntrl1910\"\n\"cntrl1045\" -> \"cntrl1062\"\n\"cntrl1047\" -> \"cntrl1065\"\n\"cntrl1048\" -> \"cntrl1068\"\n\"cntrl1048\" -> \"cntrl1120\"\n\"cntrl1051\" -> \"cntrl1053\"\n\"cntrl1052\" -> \"cntrl1051\"\n\"cntrl1053\" -> \"cntrl1045\"\n\"cntrl1056\" -> \"cntrl1061\"\n\"cntrl1057\" -> \"cntrl1060\"\n\"cntrl1058\" -> \"cntrl1059\"\n\"cntrl1059\" -> \"cntrl1047\"\n\"cntrl1060\" -> \"cntrl1058\"\n\"cntrl1061\" -> \"cntrl1057\"\n\"cntrl1062\" -> \"cntrl1056\"\n\"cntrl1063\" -> \"cntrl1064\"\n\"cntrl1064\" -> \"cntrl1048\"\n\"cntrl1065\" -> \"cntrl1063\"\n\"cntrl1066\" -> \"cntrl1067\"\n\"cntrl1067\" -> \"cntrl217\"\n\"cntrl1068\" -> \"cntrl1066\"\n\"cntrl1069\" -> \"cntrl1081\"\n\"cntrl1070\" -> \"cntrl1088\"\n\"cntrl1071\" -> \"cntrl1091\"\n\"cntrl1071\" -> \"cntrl1098\"\n\"cntrl1074\" -> \"cntrl1076\"\n\"cntrl1074\" -> \"cntrl1077\"\n\"cntrl1075\" -> \"cntrl1074\"\n\"cntrl1076\" -> \"cntrl313\"\n\"cntrl1077\" -> \"cntrl1069\"\n\"cntrl1079\" -> \"cntrl1080\"\n\"cntrl1080\" -> \"cntrl1070\"\n\"cntrl1081\" -> \"cntrl1079\"\n\"cntrl1082\" -> \"cntrl1087\"\n\"cntrl1083\" -> \"cntrl1086\"\n\"cntrl1084\" -> \"cntrl1085\"\n\"cntrl1085\" -> \"cntrl1071\"\n\"cntrl1086\" -> \"cntrl1084\"\n\"cntrl1087\" -> \"cntrl1083\"\n\"cntrl1088\" -> \"cntrl1082\"\n\"cntrl1089\" -> \"cntrl1090\"\n\"cntrl1090\" -> \"cntrl690\"\n\"cntrl1091\" -> \"cntrl1089\"\n\"cntrl1092\" -> \"cntrl1107\"\n\"cntrl1094\" -> \"cntrl1110\"\n\"cntrl1095\" -> \"cntrl1113\"\n\"cntrl1095\" -> \"cntrl1141\"\n\"cntrl1098\" -> \"cntrl1092\"\n\"cntrl1101\" -> \"cntrl1106\"\n\"cntrl1102\" -> \"cntrl1105\"\n\"cntrl1103\" -> \"cntrl1104\"\n\"cntrl1104\" -> \"cntrl1094\"\n\"cntrl1105\" -> \"cntrl1103\"\n\"cntrl1106\" -> \"cntrl1102\"\n\"cntrl1107\" -> \"cntrl1101\"\n\"cntrl1108\" -> \"cntrl1109\"\n\"cntrl1109\" -> \"cntrl1095\"\n\"cntrl1110\" -> \"cntrl1108\"\n\"cntrl1111\" -> \"cntrl1112\"\n\"cntrl1112\" -> \"cntrl690\"\n\"cntrl1113\" -> \"cntrl1111\"\n\"cntrl1114\" -> \"cntrl1129\"\n\"cntrl1116\" -> \"cntrl1132\"\n\"cntrl1117\" -> \"cntrl1135\"\n\"cntrl1117\" -> \"cntrl1214\"\n\"cntrl1120\" -> \"cntrl1114\"\n\"cntrl1123\" -> \"cntrl1128\"\n\"cntrl1124\" -> \"cntrl1127\"\n\"cntrl1125\" -> \"cntrl1126\"\n\"cntrl1126\" -> \"cntrl1116\"\n\"cntrl1127\" -> \"cntrl1125\"\n\"cntrl1128\" -> \"cntrl1124\"\n\"cntrl1129\" -> \"cntrl1123\"\n\"cntrl1130\" -> \"cntrl1131\"\n\"cntrl1131\" -> \"cntrl1117\"\n\"cntrl1132\" -> \"cntrl1130\"\n\"cntrl1133\" -> \"cntrl1134\"\n\"cntrl1134\" -> \"cntrl217\"\n\"cntrl1135\" -> \"cntrl1133\"\n\"cntrl1136\" -> \"cntrl1145\"\n\"cntrl1137\" -> \"cntrl1152\"\n\"cntrl1138\" -> \"cntrl1155\"\n\"cntrl1138\" -> \"cntrl1162\"\n\"cntrl1141\" -> \"cntrl1136\"\n\"cntrl1143\" -> \"cntrl1144\"\n\"cntrl1144\" -> \"cntrl1137\"\n\"cntrl1145\" -> \"cntrl1143\"\n\"cntrl1146\" -> \"cntrl1151\"\n\"cntrl1147\" -> \"cntrl1150\"\n\"cntrl1148\" -> \"cntrl1149\"\n\"cntrl1149\" -> \"cntrl1138\"\n\"cntrl1150\" -> \"cntrl1148\"\n\"cntrl1151\" -> \"cntrl1147\"\n\"cntrl1152\" -> \"cntrl1146\"\n\"cntrl1153\" -> \"cntrl1154\"\n\"cntrl1154\" -> \"cntrl690\"\n\"cntrl1155\" -> \"cntrl1153\"\n\"cntrl1156\" -> \"cntrl1171\"\n\"cntrl1158\" -> \"cntrl1174\"\n\"cntrl1159\" -> \"cntrl1177\"\n\"cntrl1162\" -> \"cntrl1156\"\n\"cntrl1165\" -> \"cntrl1170\"\n\"cntrl1166\" -> \"cntrl1169\"\n\"cntrl1167\" -> \"cntrl1168\"\n\"cntrl1168\" -> \"cntrl1158\"\n\"cntrl1169\" -> \"cntrl1167\"\n\"cntrl1170\" -> \"cntrl1166\"\n\"cntrl1171\" -> \"cntrl1165\"\n\"cntrl1172\" -> \"cntrl1173\"\n\"cntrl1173\" -> \"cntrl1159\"\n\"cntrl1174\" -> \"cntrl1172\"\n\"cntrl1175\" -> \"cntrl1176\"\n\"cntrl1176\" -> \"cntrl690\"\n\"cntrl1177\" -> \"cntrl1175\"\n\"cntrl1178\" -> \"cntrl1192\"\n\"cntrl1179\" -> \"cntrl1195\"\n\"cntrl1181\" -> \"cntrl1183\"\n\"cntrl1181\" -> \"cntrl1184\"\n\"cntrl1182\" -> \"cntrl1181\"\n\"cntrl1183\" -> \"cntrl191\"\n\"cntrl1184\" -> \"cntrl1178\"\n\"cntrl1186\" -> \"cntrl1912\"\n\"cntrl1187\" -> \"cntrl1190\"\n\"cntrl1188\" -> \"cntrl2008\"\n\"cntrl1190\" -> \"cntrl1188\"\n\"cntrl1192\" -> \"cntrl1186\"\n\"cntrl1193\" -> \"cntrl1194\"\n\"cntrl1194\" -> \"cntrl190\"\n\"cntrl1195\" -> \"cntrl1193\"\n\"cntrl1196\" -> \"cntrl1207\"\n\"cntrl1197\" -> \"cntrl1210\"\n\"cntrl1197\" -> \"cntrl1253\"\n\"cntrl1199\" -> \"cntrl1201\"\n\"cntrl1200\" -> \"cntrl1199\"\n\"cntrl1201\" -> \"cntrl1196\"\n\"cntrl1203\" -> \"cntrl1206\"\n\"cntrl1204\" -> \"cntrl1205\"\n\"cntrl1205\" -> \"cntrl1197\"\n\"cntrl1206\" -> \"cntrl1204\"\n\"cntrl1207\" -> \"cntrl1203\"\n\"cntrl1208\" -> \"cntrl1209\"\n\"cntrl1209\" -> \"cntrl39\"\n\"cntrl1210\" -> \"cntrl1208\"\n\"cntrl1211\" -> \"cntrl1220\"\n\"cntrl1212\" -> \"cntrl1223\"\n\"cntrl1212\" -> \"cntrl1266\"\n\"cntrl1214\" -> \"cntrl1211\"\n\"cntrl1216\" -> \"cntrl1219\"\n\"cntrl1217\" -> \"cntrl1218\"\n\"cntrl1218\" -> \"cntrl1212\"\n\"cntrl1219\" -> \"cntrl1217\"\n\"cntrl1220\" -> \"cntrl1216\"\n\"cntrl1221\" -> \"cntrl1222\"\n\"cntrl1222\" -> \"cntrl217\"\n\"cntrl1223\" -> \"cntrl1221\"\n\"cntrl1224\" -> \"cntrl1235\"\n\"cntrl1225\" -> \"cntrl1238\"\n\"cntrl1227\" -> \"cntrl1229\"\n\"cntrl1228\" -> \"cntrl1227\"\n\"cntrl1229\" -> \"cntrl1224\"\n\"cntrl1231\" -> \"cntrl1234\"\n\"cntrl1232\" -> \"cntrl1233\"\n\"cntrl1233\" -> \"cntrl1225\"\n\"cntrl1234\" -> \"cntrl1232\"\n\"cntrl1235\" -> \"cntrl1231\"\n\"cntrl1236\" -> \"cntrl1237\"\n\"cntrl1237\" -> \"cntrl1028\"\n\"cntrl1238\" -> \"cntrl1236\"\n\"cntrl1239\" -> \"cntrl1247\"\n\"cntrl1240\" -> \"cntrl1249\"\n\"cntrl1242\" -> \"cntrl1239\"\n\"cntrl1243\" -> \"cntrl1914\"\n\"cntrl1244\" -> \"cntrl1245\"\n\"cntrl1245\" -> \"cntrl1240\"\n\"cntrl1247\" -> \"cntrl1243\"\n\"cntrl1248\" -> \"cntrl1584\"\n\"cntrl1248\" -> \"cntrl1585\"\n\"cntrl1249\" -> \"cntrl1248\"\n\"cntrl1250\" -> \"cntrl1259\"\n\"cntrl1251\" -> \"cntrl1262\"\n\"cntrl1251\" -> \"cntrl1339\"\n\"cntrl1253\" -> \"cntrl1250\"\n\"cntrl1255\" -> \"cntrl1258\"\n\"cntrl1256\" -> \"cntrl1257\"\n\"cntrl1257\" -> \"cntrl1251\"\n\"cntrl1258\" -> \"cntrl1256\"\n\"cntrl1259\" -> \"cntrl1255\"\n\"cntrl1260\" -> \"cntrl1261\"\n\"cntrl1261\" -> \"cntrl39\"\n\"cntrl1262\" -> \"cntrl1260\"\n\"cntrl1263\" -> \"cntrl1272\"\n\"cntrl1264\" -> \"cntrl1275\"\n\"cntrl1266\" -> \"cntrl1263\"\n\"cntrl1268\" -> \"cntrl1271\"\n\"cntrl1269\" -> \"cntrl1270\"\n\"cntrl1270\" -> \"cntrl1264\"\n\"cntrl1271\" -> \"cntrl1269\"\n\"cntrl1272\" -> \"cntrl1268\"\n\"cntrl1273\" -> \"cntrl1274\"\n\"cntrl1274\" -> \"cntrl217\"\n\"cntrl1275\" -> \"cntrl1273\"\n\"cntrl1276\" -> \"cntrl1287\"\n\"cntrl1277\" -> \"cntrl1290\"\n\"cntrl1279\" -> \"cntrl1281\"\n\"cntrl1280\" -> \"cntrl1279\"\n\"cntrl1281\" -> \"cntrl1276\"\n\"cntrl1283\" -> \"cntrl1286\"\n\"cntrl1284\" -> \"cntrl1285\"\n\"cntrl1285\" -> \"cntrl1277\"\n\"cntrl1286\" -> \"cntrl1284\"\n\"cntrl1287\" -> \"cntrl1283\"\n\"cntrl1288\" -> \"cntrl1289\"\n\"cntrl1289\" -> \"cntrl1023\"\n\"cntrl1290\" -> \"cntrl1288\"\n\"cntrl1291\" -> \"cntrl1299\"\n\"cntrl1292\" -> \"cntrl1301\"\n\"cntrl1294\" -> \"cntrl1291\"\n\"cntrl1295\" -> \"cntrl1919\"\n\"cntrl1296\" -> \"cntrl1297\"\n\"cntrl1297\" -> \"cntrl1292\"\n\"cntrl1299\" -> \"cntrl1295\"\n\"cntrl1300\" -> \"cntrl1582\"\n\"cntrl1300\" -> \"cntrl1583\"\n\"cntrl1301\" -> \"cntrl1300\"\n\"cntrl1302\" -> \"cntrl1315\"\n\"cntrl1303\" -> \"cntrl1318\"\n\"cntrl1305\" -> \"cntrl1307\"\n\"cntrl1307\" -> \"cntrl1302\"\n\"cntrl1309\" -> \"cntrl1314\"\n\"cntrl1310\" -> \"cntrl1313\"\n\"cntrl1311\" -> \"cntrl1312\"\n\"cntrl1312\" -> \"cntrl1303\"\n\"cntrl1313\" -> \"cntrl1311\"\n\"cntrl1314\" -> \"cntrl1310\"\n\"cntrl1315\" -> \"cntrl1309\"\n\"cntrl1316\" -> \"cntrl1317\"\n\"cntrl1317\" -> \"cntrl37\"\n\"cntrl1318\" -> \"cntrl1316\"\n\"cntrl1319\" -> \"cntrl1332\"\n\"cntrl1320\" -> \"cntrl1335\"\n\"cntrl1322\" -> \"cntrl1324\"\n\"cntrl1324\" -> \"cntrl1319\"\n\"cntrl1326\" -> \"cntrl1331\"\n\"cntrl1327\" -> \"cntrl1330\"\n\"cntrl1328\" -> \"cntrl1329\"\n\"cntrl1329\" -> \"cntrl1320\"\n\"cntrl1330\" -> \"cntrl1328\"\n\"cntrl1331\" -> \"cntrl1327\"\n\"cntrl1332\" -> \"cntrl1326\"\n\"cntrl1333\" -> \"cntrl1334\"\n\"cntrl1334\" -> \"cntrl189\"\n\"cntrl1335\" -> \"cntrl1333\"\n\"cntrl1336\" -> \"cntrl1345\"\n\"cntrl1337\" -> \"cntrl1348\"\n\"cntrl1337\" -> \"cntrl1378\"\n\"cntrl1339\" -> \"cntrl1336\"\n\"cntrl1341\" -> \"cntrl1344\"\n\"cntrl1342\" -> \"cntrl1343\"\n\"cntrl1343\" -> \"cntrl1337\"\n\"cntrl1344\" -> \"cntrl1342\"\n\"cntrl1345\" -> \"cntrl1341\"\n\"cntrl1346\" -> \"cntrl1347\"\n\"cntrl1347\" -> \"cntrl39\"\n\"cntrl1348\" -> \"cntrl1346\"\n\"cntrl1349\" -> \"cntrl1360\"\n\"cntrl1350\" -> \"cntrl1363\"\n\"cntrl1352\" -> \"cntrl1354\"\n\"cntrl1353\" -> \"cntrl1352\"\n\"cntrl1354\" -> \"cntrl1349\"\n\"cntrl1356\" -> \"cntrl1359\"\n\"cntrl1357\" -> \"cntrl1358\"\n\"cntrl1358\" -> \"cntrl1350\"\n\"cntrl1359\" -> \"cntrl1357\"\n\"cntrl1360\" -> \"cntrl1356\"\n\"cntrl1361\" -> \"cntrl1362\"\n\"cntrl1362\" -> \"cntrl1035\"\n\"cntrl1363\" -> \"cntrl1361\"\n\"cntrl1364\" -> \"cntrl1372\"\n\"cntrl1365\" -> \"cntrl1374\"\n\"cntrl1367\" -> \"cntrl1364\"\n\"cntrl1368\" -> \"cntrl1915\"\n\"cntrl1369\" -> \"cntrl1370\"\n\"cntrl1370\" -> \"cntrl1365\"\n\"cntrl1372\" -> \"cntrl1368\"\n\"cntrl1373\" -> \"cntrl1580\"\n\"cntrl1373\" -> \"cntrl1581\"\n\"cntrl1374\" -> \"cntrl1373\"\n\"cntrl1375\" -> \"cntrl1384\"\n\"cntrl1376\" -> \"cntrl1387\"\n\"cntrl1376\" -> \"cntrl1417\"\n\"cntrl1378\" -> \"cntrl1375\"\n\"cntrl1380\" -> \"cntrl1383\"\n\"cntrl1381\" -> \"cntrl1382\"\n\"cntrl1382\" -> \"cntrl1376\"\n\"cntrl1383\" -> \"cntrl1381\"\n\"cntrl1384\" -> \"cntrl1380\"\n\"cntrl1385\" -> \"cntrl1386\"\n\"cntrl1386\" -> \"cntrl39\"\n\"cntrl1387\" -> \"cntrl1385\"\n\"cntrl1388\" -> \"cntrl1399\"\n\"cntrl1389\" -> \"cntrl1402\"\n\"cntrl1391\" -> \"cntrl1393\"\n\"cntrl1392\" -> \"cntrl1391\"\n\"cntrl1393\" -> \"cntrl1388\"\n\"cntrl1395\" -> \"cntrl1398\"\n\"cntrl1396\" -> \"cntrl1397\"\n\"cntrl1397\" -> \"cntrl1389\"\n\"cntrl1398\" -> \"cntrl1396\"\n\"cntrl1399\" -> \"cntrl1395\"\n\"cntrl1400\" -> \"cntrl1401\"\n\"cntrl1401\" -> \"cntrl1033\"\n\"cntrl1402\" -> \"cntrl1400\"\n\"cntrl1403\" -> \"cntrl1411\"\n\"cntrl1404\" -> \"cntrl1413\"\n\"cntrl1406\" -> \"cntrl1403\"\n\"cntrl1407\" -> \"cntrl1920\"\n\"cntrl1408\" -> \"cntrl1409\"\n\"cntrl1409\" -> \"cntrl1404\"\n\"cntrl1411\" -> \"cntrl1407\"\n\"cntrl1412\" -> \"cntrl1578\"\n\"cntrl1412\" -> \"cntrl1579\"\n\"cntrl1413\" -> \"cntrl1412\"\n\"cntrl1414\" -> \"cntrl1423\"\n\"cntrl1415\" -> \"cntrl1426\"\n\"cntrl1415\" -> \"cntrl1456\"\n\"cntrl1417\" -> \"cntrl1414\"\n\"cntrl1419\" -> \"cntrl1422\"\n\"cntrl1420\" -> \"cntrl1421\"\n\"cntrl1421\" -> \"cntrl1415\"\n\"cntrl1422\" -> \"cntrl1420\"\n\"cntrl1423\" -> \"cntrl1419\"\n\"cntrl1424\" -> \"cntrl1425\"\n\"cntrl1425\" -> \"cntrl39\"\n\"cntrl1426\" -> \"cntrl1424\"\n\"cntrl1427\" -> \"cntrl1438\"\n\"cntrl1428\" -> \"cntrl1441\"\n\"cntrl1430\" -> \"cntrl1432\"\n\"cntrl1431\" -> \"cntrl1430\"\n\"cntrl1432\" -> \"cntrl1427\"\n\"cntrl1434\" -> \"cntrl1437\"\n\"cntrl1435\" -> \"cntrl1436\"\n\"cntrl1436\" -> \"cntrl1428\"\n\"cntrl1437\" -> \"cntrl1435\"\n\"cntrl1438\" -> \"cntrl1434\"\n\"cntrl1439\" -> \"cntrl1440\"\n\"cntrl1440\" -> \"cntrl1039\"\n\"cntrl1441\" -> \"cntrl1439\"\n\"cntrl1442\" -> \"cntrl1450\"\n\"cntrl1443\" -> \"cntrl1452\"\n\"cntrl1445\" -> \"cntrl1442\"\n\"cntrl1446\" -> \"cntrl1916\"\n\"cntrl1447\" -> \"cntrl1448\"\n\"cntrl1448\" -> \"cntrl1443\"\n\"cntrl1450\" -> \"cntrl1446\"\n\"cntrl1451\" -> \"cntrl1576\"\n\"cntrl1451\" -> \"cntrl1577\"\n\"cntrl1452\" -> \"cntrl1451\"\n\"cntrl1453\" -> \"cntrl1462\"\n\"cntrl1454\" -> \"cntrl1465\"\n\"cntrl1454\" -> \"cntrl1495\"\n\"cntrl1456\" -> \"cntrl1453\"\n\"cntrl1458\" -> \"cntrl1461\"\n\"cntrl1459\" -> \"cntrl1460\"\n\"cntrl1460\" -> \"cntrl1454\"\n\"cntrl1461\" -> \"cntrl1459\"\n\"cntrl1462\" -> \"cntrl1458\"\n\"cntrl1463\" -> \"cntrl1464\"\n\"cntrl1464\" -> \"cntrl39\"\n\"cntrl1465\" -> \"cntrl1463\"\n\"cntrl1466\" -> \"cntrl1477\"\n\"cntrl1467\" -> \"cntrl1480\"\n\"cntrl1469\" -> \"cntrl1471\"\n\"cntrl1470\" -> \"cntrl1469\"\n\"cntrl1471\" -> \"cntrl1466\"\n\"cntrl1473\" -> \"cntrl1476\"\n\"cntrl1474\" -> \"cntrl1475\"\n\"cntrl1475\" -> \"cntrl1467\"\n\"cntrl1476\" -> \"cntrl1474\"\n\"cntrl1477\" -> \"cntrl1473\"\n\"cntrl1478\" -> \"cntrl1479\"\n\"cntrl1479\" -> \"cntrl1037\"\n\"cntrl1480\" -> \"cntrl1478\"\n\"cntrl1481\" -> \"cntrl1489\"\n\"cntrl1482\" -> \"cntrl1491\"\n\"cntrl1484\" -> \"cntrl1481\"\n\"cntrl1485\" -> \"cntrl1921\"\n\"cntrl1486\" -> \"cntrl1487\"\n\"cntrl1487\" -> \"cntrl1482\"\n\"cntrl1489\" -> \"cntrl1485\"\n\"cntrl1490\" -> \"cntrl1574\"\n\"cntrl1490\" -> \"cntrl1575\"\n\"cntrl1491\" -> \"cntrl1490\"\n\"cntrl1492\" -> \"cntrl1501\"\n\"cntrl1493\" -> \"cntrl1504\"\n\"cntrl1493\" -> \"cntrl1534\"\n\"cntrl1495\" -> \"cntrl1492\"\n\"cntrl1497\" -> \"cntrl1500\"\n\"cntrl1498\" -> \"cntrl1499\"\n\"cntrl1499\" -> \"cntrl1493\"\n\"cntrl1500\" -> \"cntrl1498\"\n\"cntrl1501\" -> \"cntrl1497\"\n\"cntrl1502\" -> \"cntrl1503\"\n\"cntrl1503\" -> \"cntrl39\"\n\"cntrl1504\" -> \"cntrl1502\"\n\"cntrl1505\" -> \"cntrl1516\"\n\"cntrl1506\" -> \"cntrl1519\"\n\"cntrl1508\" -> \"cntrl1510\"\n\"cntrl1509\" -> \"cntrl1508\"\n\"cntrl1510\" -> \"cntrl1505\"\n\"cntrl1512\" -> \"cntrl1515\"\n\"cntrl1513\" -> \"cntrl1514\"\n\"cntrl1514\" -> \"cntrl1506\"\n\"cntrl1515\" -> \"cntrl1513\"\n\"cntrl1516\" -> \"cntrl1512\"\n\"cntrl1517\" -> \"cntrl1518\"\n\"cntrl1518\" -> \"cntrl1043\"\n\"cntrl1519\" -> \"cntrl1517\"\n\"cntrl1520\" -> \"cntrl1528\"\n\"cntrl1521\" -> \"cntrl1530\"\n\"cntrl1523\" -> \"cntrl1520\"\n\"cntrl1524\" -> \"cntrl1917\"\n\"cntrl1525\" -> \"cntrl1526\"\n\"cntrl1526\" -> \"cntrl1521\"\n\"cntrl1528\" -> \"cntrl1524\"\n\"cntrl1529\" -> \"cntrl1572\"\n\"cntrl1529\" -> \"cntrl1573\"\n\"cntrl1530\" -> \"cntrl1529\"\n\"cntrl1531\" -> \"cntrl1540\"\n\"cntrl1532\" -> \"cntrl1543\"\n\"cntrl1534\" -> \"cntrl1531\"\n\"cntrl1536\" -> \"cntrl1539\"\n\"cntrl1537\" -> \"cntrl1538\"\n\"cntrl1538\" -> \"cntrl1532\"\n\"cntrl1539\" -> \"cntrl1537\"\n\"cntrl1540\" -> \"cntrl1536\"\n\"cntrl1541\" -> \"cntrl1542\"\n\"cntrl1542\" -> \"cntrl39\"\n\"cntrl1543\" -> \"cntrl1541\"\n\"cntrl1544\" -> \"cntrl1555\"\n\"cntrl1545\" -> \"cntrl1558\"\n\"cntrl1547\" -> \"cntrl1549\"\n\"cntrl1548\" -> \"cntrl1547\"\n\"cntrl1549\" -> \"cntrl1544\"\n\"cntrl1551\" -> \"cntrl1554\"\n\"cntrl1552\" -> \"cntrl1553\"\n\"cntrl1553\" -> \"cntrl1545\"\n\"cntrl1554\" -> \"cntrl1552\"\n\"cntrl1555\" -> \"cntrl1551\"\n\"cntrl1556\" -> \"cntrl1557\"\n\"cntrl1557\" -> \"cntrl1041\"\n\"cntrl1558\" -> \"cntrl1556\"\n\"cntrl1559\" -> \"cntrl1567\"\n\"cntrl1560\" -> \"cntrl1569\"\n\"cntrl1562\" -> \"cntrl1559\"\n\"cntrl1563\" -> \"cntrl1922\"\n\"cntrl1564\" -> \"cntrl1565\"\n\"cntrl1565\" -> \"cntrl1560\"\n\"cntrl1567\" -> \"cntrl1563\"\n\"cntrl1568\" -> \"cntrl1570\"\n\"cntrl1568\" -> \"cntrl1571\"\n\"cntrl1569\" -> \"cntrl1568\"\n\"cntrl1570\" -> \"cntrl24\"\n\"cntrl1571\" -> \"cntrl2\"\n\"cntrl1572\" -> \"cntrl24\"\n\"cntrl1573\" -> \"cntrl2\"\n\"cntrl1574\" -> \"cntrl24\"\n\"cntrl1575\" -> \"cntrl2\"\n\"cntrl1576\" -> \"cntrl24\"\n\"cntrl1577\" -> \"cntrl2\"\n\"cntrl1578\" -> \"cntrl24\"\n\"cntrl1579\" -> \"cntrl2\"\n\"cntrl1580\" -> \"cntrl24\"\n\"cntrl1581\" -> \"cntrl2\"\n\"cntrl1582\" -> \"cntrl24\"\n\"cntrl1583\" -> \"cntrl2\"\n\"cntrl1584\" -> \"cntrl24\"\n\"cntrl1585\" -> \"cntrl2\"\n\"cntrl1586\" -> \"cntrl41\"\n\"cntrl1595\" -> \"cntrl219\"\n\"cntrl1629\" -> \"cntrl66\"\n\"cntrl1630\" -> \"cntrl75\"\n\"cntrl1631\" -> \"cntrl84\"\n\"cntrl1632\" -> \"cntrl93\"\n\"cntrl1633\" -> \"cntrl102\"\n\"cntrl1634\" -> \"cntrl111\"\n\"cntrl1635\" -> \"cntrl120\"\n\"cntrl1660\" -> \"cntrl332\"\n\"cntrl1668\" -> \"cntrl330\"\n\"cntrl1670\" -> \"cntrl340\"\n\"cntrl1672\" -> \"cntrl350\"\n\"cntrl1674\" -> \"cntrl360\"\n\"cntrl1723\" -> \"cntrl1725\"\n\"cntrl1724\" -> \"cntrl1723\"\n\"cntrl1725\" -> \"cntrl599\"\n\"cntrl1726\" -> \"cntrl1728\"\n\"cntrl1727\" -> \"cntrl1726\"\n\"cntrl1728\" -> \"cntrl318\"\n\"cntrl1729\" -> \"cntrl1732\"\n\"cntrl1730\" -> \"cntrl1729\"\n\"cntrl1731\" -> \"cntrl1729\"\n\"cntrl1732\" -> \"cntrl224\"\n\"cntrl1733\" -> \"cntrl1735\"\n\"cntrl1734\" -> \"cntrl1733\"\n\"cntrl1735\" -> \"cntrl604\"\n\"cntrl1736\" -> \"cntrl1738\"\n\"cntrl1737\" -> \"cntrl1736\"\n\"cntrl1738\" -> \"cntrl323\"\n\"cntrl1739\" -> \"cntrl1742\"\n\"cntrl1740\" -> \"cntrl1739\"\n\"cntrl1741\" -> \"cntrl1739\"\n\"cntrl1742\" -> \"cntrl226\"\n\"cntrl1743\" -> \"cntrl1745\"\n\"cntrl1744\" -> \"cntrl1743\"\n\"cntrl1745\" -> \"cntrl610\"\n\"cntrl1746\" -> \"cntrl1748\"\n\"cntrl1747\" -> \"cntrl1746\"\n\"cntrl1748\" -> \"cntrl615\"\n\"cntrl1749\" -> \"cntrl1751\"\n\"cntrl1750\" -> \"cntrl1749\"\n\"cntrl1751\" -> \"cntrl624\"\n\"cntrl1752\" -> \"cntrl1754\"\n\"cntrl1753\" -> \"cntrl1752\"\n\"cntrl1754\" -> \"cntrl629\"\n\"cntrl1755\" -> \"cntrl1757\"\n\"cntrl1757\" -> \"cntrl638\"\n\"cntrl1758\" -> \"cntrl1760\"\n\"cntrl1759\" -> \"cntrl1758\"\n\"cntrl1760\" -> \"cntrl643\"\n\"cntrl1761\" -> \"cntrl1923\"\n\"cntrl1762\" -> \"cntrl1761\"\n\"cntrl1764\" -> \"cntrl1763\"\n\"cntrl1765\" -> \"cntrl1768\"\n\"cntrl1766\" -> \"cntrl1765\"\n\"cntrl1768\" -> \"cntrl1767\"\n\"cntrl1770\" -> \"cntrl1769\"\n\"cntrl1771\" -> \"cntrl1924\"\n\"cntrl1772\" -> \"cntrl1771\"\n\"cntrl1773\" -> \"cntrl1925\"\n\"cntrl1774\" -> \"cntrl1773\"\n\"cntrl1776\" -> \"cntrl1775\"\n\"cntrl1778\" -> \"cntrl1777\"\n\"cntrl1779\" -> \"cntrl1926\"\n\"cntrl1780\" -> \"cntrl1779\"\n\"cntrl1782\" -> \"cntrl1781\"\n\"cntrl1783\" -> \"cntrl1927\"\n\"cntrl1784\" -> \"cntrl1783\"\n\"cntrl1785\" -> \"cntrl1928\"\n\"cntrl1786\" -> \"cntrl1785\"\n\"cntrl1787\" -> \"cntrl1929\"\n\"cntrl1788\" -> \"cntrl1787\"\n\"cntrl1789\" -> \"cntrl1930\"\n\"cntrl1790\" -> \"cntrl1789\"\n\"cntrl1791\" -> \"cntrl1931\"\n\"cntrl1792\" -> \"cntrl1791\"\n\"cntrl1793\" -> \"cntrl1932\"\n\"cntrl1794\" -> \"cntrl1793\"\n\"cntrl1795\" -> \"cntrl1933\"\n\"cntrl1796\" -> \"cntrl1795\"\n\"cntrl1798\" -> \"cntrl1797\"\n\"cntrl1799\" -> \"cntrl1802\"\n\"cntrl1800\" -> \"cntrl1799\"\n\"cntrl1802\" -> \"cntrl1801\"\n\"cntrl1803\" -> \"cntrl1934\"\n\"cntrl1803\" -> \"cntrl1935\"\n\"cntrl1804\" -> \"cntrl1803\"\n\"cntrl1805\" -> \"cntrl1936\"\n\"cntrl1805\" -> \"cntrl1937\"\n\"cntrl1806\" -> \"cntrl1805\"\n\"cntrl1807\" -> \"cntrl1938\"\n\"cntrl1807\" -> \"cntrl1939\"\n\"cntrl1808\" -> \"cntrl1807\"\n\"cntrl1809\" -> \"cntrl1940\"\n\"cntrl1809\" -> \"cntrl1941\"\n\"cntrl1810\" -> \"cntrl1809\"\n\"cntrl1811\" -> \"cntrl1942\"\n\"cntrl1811\" -> \"cntrl1943\"\n\"cntrl1812\" -> \"cntrl1811\"\n\"cntrl1813\" -> \"cntrl1944\"\n\"cntrl1814\" -> \"cntrl1813\"\n\"cntrl1815\" -> \"cntrl1945\"\n\"cntrl1816\" -> \"cntrl1815\"\n\"cntrl1817\" -> \"cntrl1946\"\n\"cntrl1818\" -> \"cntrl1817\"\n\"cntrl1819\" -> \"cntrl1947\"\n\"cntrl1820\" -> \"cntrl1819\"\n\"cntrl1821\" -> \"cntrl1948\"\n\"cntrl1822\" -> \"cntrl1821\"\n\"cntrl1823\" -> \"cntrl1949\"\n\"cntrl1823\" -> \"cntrl1950\"\n\"cntrl1824\" -> \"cntrl1823\"\n\"cntrl1825\" -> \"cntrl1951\"\n\"cntrl1825\" -> \"cntrl1952\"\n\"cntrl1826\" -> \"cntrl1825\"\n\"cntrl1827\" -> \"cntrl1953\"\n\"cntrl1827\" -> \"cntrl1954\"\n\"cntrl1828\" -> \"cntrl1827\"\n\"cntrl1829\" -> \"cntrl1955\"\n\"cntrl1829\" -> \"cntrl1956\"\n\"cntrl1830\" -> \"cntrl1829\"\n\"cntrl1831\" -> \"cntrl1957\"\n\"cntrl1831\" -> \"cntrl1958\"\n\"cntrl1832\" -> \"cntrl1831\"\n\"cntrl1833\" -> \"cntrl1959\"\n\"cntrl1834\" -> \"cntrl1833\"\n\"cntrl1835\" -> \"cntrl1960\"\n\"cntrl1836\" -> \"cntrl1835\"\n\"cntrl1837\" -> \"cntrl1961\"\n\"cntrl1838\" -> \"cntrl1837\"\n\"cntrl1839\" -> \"cntrl1962\"\n\"cntrl1840\" -> \"cntrl1839\"\n\"cntrl1841\" -> \"cntrl1963\"\n\"cntrl1842\" -> \"cntrl1841\"\n\"cntrl1843\" -> \"cntrl1964\"\n\"cntrl1843\" -> \"cntrl1965\"\n\"cntrl1844\" -> \"cntrl1843\"\n\"cntrl1845\" -> \"cntrl1966\"\n\"cntrl1845\" -> \"cntrl1967\"\n\"cntrl1846\" -> \"cntrl1845\"\n\"cntrl1847\" -> \"cntrl1968\"\n\"cntrl1847\" -> \"cntrl1969\"\n\"cntrl1848\" -> \"cntrl1847\"\n\"cntrl1849\" -> \"cntrl1970\"\n\"cntrl1849\" -> \"cntrl1971\"\n\"cntrl1850\" -> \"cntrl1849\"\n\"cntrl1851\" -> \"cntrl1972\"\n\"cntrl1851\" -> \"cntrl1973\"\n\"cntrl1852\" -> \"cntrl1851\"\n\"cntrl1853\" -> \"cntrl1974\"\n\"cntrl1854\" -> \"cntrl1853\"\n\"cntrl1855\" -> \"cntrl1975\"\n\"cntrl1856\" -> \"cntrl1855\"\n\"cntrl1857\" -> \"cntrl1976\"\n\"cntrl1858\" -> \"cntrl1857\"\n\"cntrl1859\" -> \"cntrl1977\"\n\"cntrl1860\" -> \"cntrl1859\"\n\"cntrl1861\" -> \"cntrl1978\"\n\"cntrl1862\" -> \"cntrl1861\"\n\"cntrl1863\" -> \"cntrl1979\"\n\"cntrl1863\" -> \"cntrl1980\"\n\"cntrl1864\" -> \"cntrl1863\"\n\"cntrl1865\" -> \"cntrl1981\"\n\"cntrl1865\" -> \"cntrl1982\"\n\"cntrl1866\" -> \"cntrl1865\"\n\"cntrl1867\" -> \"cntrl1983\"\n\"cntrl1868\" -> \"cntrl1867\"\n\"cntrl1870\" -> \"cntrl1869\"\n\"cntrl1871\" -> \"cntrl1984\"\n\"cntrl1872\" -> \"cntrl1871\"\n\"cntrl1873\" -> \"cntrl1985\"\n\"cntrl1874\" -> \"cntrl1873\"\n\"cntrl1876\" -> \"cntrl1875\"\n\"cntrl1878\" -> \"cntrl1877\"\n\"cntrl1879\" -> \"cntrl1986\"\n\"cntrl1880\" -> \"cntrl1879\"\n\"cntrl1881\" -> \"cntrl1987\"\n\"cntrl1882\" -> \"cntrl1881\"\n\"cntrl1884\" -> \"cntrl1883\"\n\"cntrl1886\" -> \"cntrl1885\"\n\"cntrl1888\" -> \"cntrl1887\"\n\"cntrl1890\" -> \"cntrl1889\"\n\"cntrl1892\" -> \"cntrl1891\"\n\"cntrl1894\" -> \"cntrl1893\"\n\"cntrl1896\" -> \"cntrl1895\"\n\"cntrl1898\" -> \"cntrl1897\"\n\"cntrl1900\" -> \"cntrl1899\"\n\"cntrl1902\" -> \"cntrl1901\"\n\"cntrl1904\" -> \"cntrl1903\"\n\"cntrl1906\" -> \"cntrl1905\"\n\"cntrl1908\" -> \"cntrl1907\"\n\"cntrl1910\" -> \"cntrl1909\"\n\"cntrl1911\" -> \"cntrl1988\"\n\"cntrl1912\" -> \"cntrl1911\"\n\"cntrl1913\" -> \"cntrl1989\"\n\"cntrl1913\" -> \"cntrl1990\"\n\"cntrl1913\" -> \"cntrl1991\"\n\"cntrl1913\" -> \"cntrl1992\"\n\"cntrl1914\" -> \"cntrl1913\"\n\"cntrl1915\" -> \"cntrl1913\"\n\"cntrl1916\" -> \"cntrl1913\"\n\"cntrl1917\" -> \"cntrl1913\"\n\"cntrl1918\" -> \"cntrl1993\"\n\"cntrl1918\" -> \"cntrl1994\"\n\"cntrl1918\" -> \"cntrl1995\"\n\"cntrl1918\" -> \"cntrl1996\"\n\"cntrl1919\" -> \"cntrl1918\"\n\"cntrl1920\" -> \"cntrl1918\"\n\"cntrl1921\" -> \"cntrl1918\"\n\"cntrl1922\" -> \"cntrl1918\"\n\"cntrl1923\" -> \"cntrl1305\"\n\"cntrl1924\" -> \"cntrl188\"\n\"cntrl1925\" -> \"cntrl1322\"\n\"cntrl1926\" -> \"cntrl187\"\n\"cntrl1927\" -> \"cntrl229\"\n\"cntrl1928\" -> \"cntrl234\"\n\"cntrl1929\" -> \"cntrl239\"\n\"cntrl1930\" -> \"cntrl244\"\n\"cntrl1931\" -> \"cntrl249\"\n\"cntrl1932\" -> \"cntrl254\"\n\"cntrl1933\" -> \"cntrl259\"\n\"cntrl1934\" -> \"cntrl339\"\n\"cntrl1935\" -> \"cntrl422\"\n\"cntrl1936\" -> \"cntrl344\"\n\"cntrl1937\" -> \"cntrl420\"\n\"cntrl1938\" -> \"cntrl349\"\n\"cntrl1939\" -> \"cntrl430\"\n\"cntrl1940\" -> \"cntrl354\"\n\"cntrl1941\" -> \"cntrl440\"\n\"cntrl1942\" -> \"cntrl359\"\n\"cntrl1943\" -> \"cntrl450\"\n\"cntrl1944\" -> \"cntrl364\"\n\"cntrl1945\" -> \"cntrl369\"\n\"cntrl1946\" -> \"cntrl799\"\n\"cntrl1947\" -> \"cntrl330\"\n\"cntrl1948\" -> \"cntrl800\"\n\"cntrl1949\" -> \"cntrl429\"\n\"cntrl1950\" -> \"cntrl512\"\n\"cntrl1951\" -> \"cntrl434\"\n\"cntrl1952\" -> \"cntrl510\"\n\"cntrl1953\" -> \"cntrl439\"\n\"cntrl1954\" -> \"cntrl520\"\n\"cntrl1955\" -> \"cntrl444\"\n\"cntrl1956\" -> \"cntrl530\"\n\"cntrl1957\" -> \"cntrl449\"\n\"cntrl1958\" -> \"cntrl540\"\n\"cntrl1959\" -> \"cntrl454\"\n\"cntrl1960\" -> \"cntrl459\"\n\"cntrl1961\" -> \"cntrl800\"\n\"cntrl1962\" -> \"cntrl420\"\n\"cntrl1963\" -> \"cntrl801\"\n\"cntrl1964\" -> \"cntrl519\"\n\"cntrl1965\" -> \"cntrl52\"\n\"cntrl1966\" -> \"cntrl524\"\n\"cntrl1967\" -> \"cntrl47\"\n\"cntrl1968\" -> \"cntrl529\"\n\"cntrl1969\" -> \"cntrl67\"\n\"cntrl1970\" -> \"cntrl534\"\n\"cntrl1971\" -> \"cntrl85\"\n\"cntrl1972\" -> \"cntrl539\"\n\"cntrl1973\" -> \"cntrl103\"\n\"cntrl1974\" -> \"cntrl544\"\n\"cntrl1975\" -> \"cntrl549\"\n\"cntrl1976\" -> \"cntrl801\"\n\"cntrl1977\" -> \"cntrl510\"\n\"cntrl1978\" -> \"cntrl802\"\n\"cntrl1979\" -> \"cntrl978\"\n\"cntrl1980\" -> \"cntrl1093\"\n\"cntrl1981\" -> \"cntrl1157\"\n\"cntrl1982\" -> \"cntrl1755\"\n\"cntrl1983\" -> \"cntrl177\"\n\"cntrl1984\" -> \"cntrl717\"\n\"cntrl1985\" -> \"cntrl1025\"\n\"cntrl1986\" -> \"cntrl1046\"\n\"cntrl1987\" -> \"cntrl1115\"\n\"cntrl1988\" -> \"cntrl1187\"\n\"cntrl1989\" -> \"cntrl1244\"\n\"cntrl1990\" -> \"cntrl1369\"\n\"cntrl1991\" -> \"cntrl1447\"\n\"cntrl1992\" -> \"cntrl1525\"\n\"cntrl1993\" -> \"cntrl1296\"\n\"cntrl1994\" -> \"cntrl1408\"\n\"cntrl1995\" -> \"cntrl1486\"\n\"cntrl1996\" -> \"cntrl1564\"\n\"cntrl1997\" -> \"cntrl2009\"\n\"cntrl1998\" -> \"cntrl1997\"\n\"cntrl1999\" -> \"cntrl2010\"\n\"cntrl2000\" -> \"cntrl1999\"\n\"cntrl2004\" -> \"cntrl2003\"\n\"cntrl2007\" -> \"cntrl2011\"\n\"cntrl2008\" -> \"cntrl2007\"\n\"cntrl2009\" -> \"cntrl670\"\n\"cntrl2010\" -> \"cntrl670\"\n\"cntrl2011\" -> \"cntrl1179\"\n}\n}\n" + .command: + sync: false + operations: + - type: Tensor + tag: 0 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 0 + - 1 + - type: T_Load_Tiled + tag: 1 + tensorTag: -1 + - type: Tensor + tag: 2 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Load_Tiled + tag: 3 + tensorTag: -1 + - type: Tensor + tag: 4 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Load_Tiled + tag: 5 + tensorTag: -1 + - type: Scalar + tag: 6 + variableType: {dataType: Float, pointerType: Value} + pointer: {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - type: T_Load_Scalar + tag: 7 + scalarTag: -1 + - type: Scalar + tag: 8 + variableType: {dataType: Float, pointerType: Value} + pointer: {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - type: T_Load_Scalar + tag: 9 + scalarTag: -1 + - type: T_Mul + tag: 10 + a: 1 + b: 3 + - type: T_Execute + tag: 14 + xops: + - type: E_Mul + dest: 11 + a: 9 + b: 5 + - type: E_Mul + dest: 12 + a: 7 + b: 10 + - type: E_Add + dest: 13 + a: 11 + b: 12 + nextTag: 14 + inputs: [7, 10, 9, 5] + outputs: [13, 12, 11] + - type: Tensor + tag: 15 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Execute + tag: 17 + xops: + - type: E_Cvt + dest: 16 + a: 13 + nextTag: 17 + inputs: [13] + outputs: [16] + - type: T_Store_Tiled + tag: 18 + srcTag: 16 + dstTag: 15 + argOffsetMap: + 15 Stride 1: 192 + 15 Stride 0: 184 + 15 Size 1: 176 + 15 Size 0: 168 + 15 Limit -1: 160 + 8 Value -1: 148 + 4 Stride 0: 128 + 6 Value -1: 144 + 4 Limit -1: 104 + 0 Value -1: 0 + 0 Limit -1: 8 + 2 Value -1: 48 + 0 Size 0: 16 + 4 Size 1: 120 + 0 Size 1: 24 + 2 Size 1: 72 + 15 Value -1: 152 + 2 Stride 0: 80 + 4 Stride 1: 136 + 0 Stride 0: 32 + 0 Stride 1: 40 + 4 Size 0: 112 + 2 Limit -1: 56 + 2 Stride 1: 88 + 2 Size 0: 64 + 4 Value -1: 96 + commandArgs: + - {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + nextTag: 19 + runtimeArgsOffset: 200 +... + +.end_amdgpu_metadata + diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml new file mode 100644 index 000000000000..ad433fda3052 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -0,0 +1,97 @@ +TestParameters: + marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + + # PrintTensorA: 1 + # PrintTensorB: 1 + # PrintTensorD: 2 + # PrintTensorRef: 2 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + + - # BenchmarkProblemSizeGroup - Standard - All problem + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942" + args: [AddressA, Extent0, SizeFree3, SizeFree0, StrideA0, StrideA1, AddressB, ExtentB, SizeFree3, SizeFree1, StrideB0, StrideB1, AddressC, ExtentC, SizeFree0, SizeFree1, StrideC0, StrideC1, AddressD, ExtentD, SizeFree0, SizeFree1, StrideD0, StrideD1] + - MatrixInstruction: + - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 + - PreloadKernArgs: [False] + # - PrefetchGlobalRead: [2] + # - PrefetchLocalRead: [1] + - DepthU: [64] + - VectorWidthA: [-1] + - VectorWidthB: [-1] + - GlobalReadVectorWidthA: [-1] + - GlobalReadVectorWidthB: [-1] + - LocalReadVectorWidth: [-1] + - TransposeLDS: [-1] + - LdsBlockSizePerPadA: [-1] + - LdsBlockSizePerPadB: [-1] + - LdsPadA: [-1] + - LdsPadB: [-1] + - StaggerU: [16] + - StaggerUStride: [-1] + - WorkGroupMapping: [1] + - StaggerUMapping: [0] + - 1LDSBuffer: [-1] + - WorkGroupMappingXCC: [8] + - WorkGroupMappingXCCGroup: [-1] + - GlobalSplitU: [1] + - GlobalSplitUAlgorithm: ["MultipleBuffer"] + - GlobalReadPerMfma: [1] + - LocalWritePerMfma: [-1] + - StoreRemapVectorWidth: [0] + - StoreVectorWidth: [-1] + - SourceSwap: [1] + - NumElementsPerBatchStore: [16] + - ClusterLocalRead: [1] + - NonTemporalA: [0] + - NonTemporalB: [0] + - DirectToVgprA: [1] + - DirectToVgprB: [0] + # - WorkGroup: [[32,4,4]] + + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] + # - Exact: [256, 256, 1, 256] + - Exact: [2048, 4096, 1, 1024] + # - Exact: [3328, 4096, 1, 4096] + +LibraryLogic: + ScheduleName: "aquavanjaram" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx942" + LibraryType: "GridBased" \ No newline at end of file diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index a5dc602e011e..dfc2ca387b61 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -71,7 +71,11 @@ namespace TensileLite Alpha, // 16 Beta, // 17 DebugPattern, // 18 - Count, // 19 + ExtentA, // 19 + ExtentB, // 20 + ExtentC, // 21 + ExtentD, // 22 + Count, // 23 }; std::string toString(KernelArgumentType arg); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 4313a00c6111..791620c0136c 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -96,6 +96,14 @@ namespace TensileLite return "Beta"; case KernelArgumentType::DebugPattern: return "DebugPattern"; + case KernelArgumentType::ExtentA: + return "ExtentA"; + case KernelArgumentType::ExtentB: + return "ExtentB"; + case KernelArgumentType::ExtentC: + return "ExtentC"; + case KernelArgumentType::ExtentD: + return "ExtentD"; case KernelArgumentType::Count: break; } @@ -189,6 +197,22 @@ namespace TensileLite { t = KernelArgumentType::DebugPattern; } + else if(strValue == toString(KernelArgumentType::ExtentA)) + { + t = KernelArgumentType::ExtentA; + } + else if(strValue == toString(KernelArgumentType::ExtentB)) + { + t = KernelArgumentType::ExtentB; + } + else if(strValue == toString(KernelArgumentType::ExtentC)) + { + t = KernelArgumentType::ExtentC; + } + else if(strValue == toString(KernelArgumentType::ExtentD)) + { + t = KernelArgumentType::ExtentD; + } else { throw std::runtime_error(concatenate("Invalid argument type: ", strValue)); @@ -1637,6 +1661,121 @@ namespace TensileLite return rv; } + template + KernelInvocation ContractionSolution::generateRocRollerCall(ContractionSolution::Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk) const + { + KernelInvocation rv; + rv.isSingleCall = true; + rv.args = KernelArguments(T_Debug); + rv.args.reserve(1024, 128); + rv.kernelName = kernelName; + + calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); + rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + rv.numWorkGroups.y = 1; + rv.numWorkGroups.z = 1; + + rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; + rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; + rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; + + // Temporarily set internal args manually + // uint32_t gemmCount = 1; + // gemmCount = gemmCount & 0x3FFFFFFF; + // rv.args.template append("gemm_count", gemmCount); + // uint32_t internalArg0 = 1048577; + // rv.args.template append("internalArgs", internalArg0); + // int32_t internalArg1 = 436731905; + // rv.args.template append("internalArgs1", internalArg1); + + // uint32_t numWorkGroups = getNumWorkGroups(rv); + // rv.args.template append("numWorkGroups", numWorkGroups); + + // uint32_t debugPattern = 0xDB000001; + + for(auto arg : sizeMapping.customKernel.args) + { + switch(arg) + { + case KernelArgumentType::SizeFree0: + rv.args.template append("SizeFree0", problem.problemSizes()[0]); + break; + case KernelArgumentType::SizeFree1: + rv.args.template append("SizeFree1", problem.problemSizes()[1]); + break; + case KernelArgumentType::SizeFree2: + rv.args.template append("SizeFree2", problem.problemSizes()[2]); + break; + case KernelArgumentType::SizeSum: + rv.args.template append("SizeSum", problem.problemSizes()[3]); + break; + case KernelArgumentType::AddressA: + rv.args.template append("AddressA", inputs.a); + break; + case KernelArgumentType::AddressB: + rv.args.template append("AddressB", inputs.b); + break; + case KernelArgumentType::AddressC: + rv.args.template append("AddressC", inputs.c); + break; + case KernelArgumentType::AddressD: + rv.args.template append("AddressD", inputs.d); + break; + case KernelArgumentType::StrideA0: + rv.args.template append("StrideA0", problem.a().strides()[1]); + break; + case KernelArgumentType::StrideA1: + rv.args.template append("StrideA1", problem.a().strides()[2]); + break; + case KernelArgumentType::StrideB0: + rv.args.template append("StrideB0", problem.b().strides()[1]); + break; + case KernelArgumentType::StrideB1: + rv.args.template append("StrideB1", problem.b().strides()[2]); + break; + case KernelArgumentType::StrideC0: + rv.args.template append("StrideC0", problem.c().strides()[1]); + break; + case KernelArgumentType::StrideC1: + rv.args.template append("StrideC1", problem.c().strides()[2]); + break; + case KernelArgumentType::StrideD0: + rv.args.template append("StrideD0", problem.d().strides()[1]); + break; + case KernelArgumentType::StrideD1: + rv.args.template append("StrideD1", problem.d().strides()[2]); + break; + case KernelArgumentType::Alpha: + rv.args.append("Alpha", inputs.alpha, problem.alphaType()); + break; + case KernelArgumentType::Beta: + rv.args.append("Beta", inputs.beta, problem.betaType()); + break; + case KernelArgumentType::ExtentA: + rv.args.template append("ExtentA", problem.problemSizes()[0] * problem.problemSizes()[3]); + break; + case KernelArgumentType::ExtentB: + rv.args.template append("ExtentB", problem.problemSizes()[1] * problem.problemSizes()[3]); + break; + case KernelArgumentType::ExtentC: + rv.args.template append("ExtentC", problem.problemSizes()[0] * problem.problemSizes()[1]); + break; + case KernelArgumentType::ExtentD: + rv.args.template append("ExtentD", problem.problemSizes()[1] * problem.problemSizes()[1]); + break; + case KernelArgumentType::DebugPattern: + // N/A + break; + default: + throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); + } + } + return rv; + } + template KernelInvocation ContractionSolution::generateSingleCall(ContractionSolution::Problem const& problem, @@ -3024,6 +3163,14 @@ namespace TensileLite else rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); } + else if(sizeMapping.customKernel.name.contains("RRGEMM_")) + { + // RocRoller kernel + if(debug) + rv.push_back(generateRocRollerCall(problem, inputs, hardware, sk)); + else + rv.push_back(generateRocRollerCall(problem, inputs, hardware, sk)); + } else { // Custom kernel From 46457122d528d7bd8987921ef3dfd405561824f7 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Thu, 26 Feb 2026 22:44:49 +0000 Subject: [PATCH 05/58] Fixes --- .../tensilelite/include/Tensile/ContractionSolution.hpp | 6 ++++++ .../tensilelite/include/Tensile/Serialization/Base.hpp | 1 + projects/hipblaslt/tensilelite/src/ContractionSolution.cpp | 2 +- 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index dfc2ca387b61..436b71bb7e26 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -494,6 +494,12 @@ namespace TensileLite Hardware const& hardware, StreamKSettings const& sk) const; + template + KernelInvocation generateRocRollerCall(ContractionSolution::Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk) const; + template KernelInvocation generateSingleCall(Problem const& problem, ContractionInputs const& inputs, diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index 823d028d3138..d4c9f85b7c02 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -34,6 +34,7 @@ #include #include +#include #include #include #include diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 791620c0136c..00b874ae2ab9 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -3163,7 +3163,7 @@ namespace TensileLite else rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); } - else if(sizeMapping.customKernel.name.contains("RRGEMM_")) + else if(sizeMapping.customKernel.name.find("RRGEMM_") != std::string::npos) { // RocRoller kernel if(debug) From 85c38f484959a244e2ce5e677597b5a18fbb5348 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Thu, 26 Feb 2026 23:10:39 +0000 Subject: [PATCH 06/58] YAML typo fix --- .../hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index ad433fda3052..9a0a56950d35 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -43,7 +43,7 @@ BenchmarkProblems: ForkParameters: - CustomKernel: - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942" - args: [AddressA, Extent0, SizeFree3, SizeFree0, StrideA0, StrideA1, AddressB, ExtentB, SizeFree3, SizeFree1, StrideB0, StrideB1, AddressC, ExtentC, SizeFree0, SizeFree1, StrideC0, StrideC1, AddressD, ExtentD, SizeFree0, SizeFree1, StrideD0, StrideD1] + args: [AddressA, ExtentA, SizeFree3, SizeFree0, StrideA0, StrideA1, AddressB, ExtentB, SizeFree3, SizeFree1, StrideB0, StrideB1, AddressC, ExtentC, SizeFree0, SizeFree1, StrideC0, StrideC1, AddressD, ExtentD, SizeFree0, SizeFree1, StrideD0, StrideD1] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] From c95ece55fee62f3c92c745a430e2ff3170cf488c Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Fri, 27 Feb 2026 00:34:01 +0000 Subject: [PATCH 07/58] Explicit RR kernel sizes --- .../Tensile/Tests/custom/custom_rr.yaml | 4 +- .../include/Tensile/ContractionSolution.hpp | 10 +- .../tensilelite/src/ContractionSolution.cpp | 104 ++++++++++++++---- 3 files changed, 93 insertions(+), 25 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index 9a0a56950d35..e43fd18fd415 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -42,8 +42,8 @@ BenchmarkProblems: - KernelLanguage: ["Assembly"] ForkParameters: - CustomKernel: - - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942" - args: [AddressA, ExtentA, SizeFree3, SizeFree0, StrideA0, StrideA1, AddressB, ExtentB, SizeFree3, SizeFree1, StrideB0, StrideB1, AddressC, ExtentC, SizeFree0, SizeFree1, StrideC0, StrideC1, AddressD, ExtentD, SizeFree0, SizeFree1, StrideD0, StrideD1] + - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a" + args: [AddressA, ExtentA, SizeA0, SizeA1, StrideA0, StrideA1, AddressB, ExtentB, SizeB0, SizeB1, StrideB0, StrideB1, AddressC, ExtentC, SizeC0, SizeC1, StrideC0, StrideC1, AddressD, ExtentD, SizeD0, SizeD1, StrideD0, StrideD1] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 436b71bb7e26..7e1d96e72a07 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -75,7 +75,15 @@ namespace TensileLite ExtentB, // 20 ExtentC, // 21 ExtentD, // 22 - Count, // 23 + SizeA0, // 23 + SizeA1, // 24 + SizeB0, // 25 + SizeB1, // 26 + SizeC0, // 27 + SizeC1, // 28 + SizeD0, // 29 + SizeD1, // 30 + Count, // 31 }; std::string toString(KernelArgumentType arg); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 00b874ae2ab9..800461774418 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -104,6 +104,22 @@ namespace TensileLite return "ExtentC"; case KernelArgumentType::ExtentD: return "ExtentD"; + case KernelArgumentType::SizeA0: + return "SizeA0"; + case KernelArgumentType::SizeA1: + return "SizeA1"; + case KernelArgumentType::SizeB0: + return "SizeB0"; + case KernelArgumentType::SizeB1: + return "SizeB1"; + case KernelArgumentType::SizeC0: + return "SizeC0"; + case KernelArgumentType::SizeC1: + return "SizeC1"; + case KernelArgumentType::SizeD0: + return "SizeD0"; + case KernelArgumentType::SizeD1: + return "SizeD1"; case KernelArgumentType::Count: break; } @@ -212,7 +228,39 @@ namespace TensileLite else if(strValue == toString(KernelArgumentType::ExtentD)) { t = KernelArgumentType::ExtentD; - } + } + else if(strValue == toString(KernelArgumentType::SizeA0)) + { + t = KernelArgumentType::SizeA0; + } + else if(strValue == toString(KernelArgumentType::SizeA1)) + { + t = KernelArgumentType::SizeA1; + } + else if(strValue == toString(KernelArgumentType::SizeB0)) + { + t = KernelArgumentType::SizeB0; + } + else if(strValue == toString(KernelArgumentType::SizeB1)) + { + t = KernelArgumentType::SizeB1; + } + else if(strValue == toString(KernelArgumentType::SizeC0)) + { + t = KernelArgumentType::SizeC0; + } + else if(strValue == toString(KernelArgumentType::SizeC1)) + { + t = KernelArgumentType::SizeC1; + } + else if(strValue == toString(KernelArgumentType::SizeD0)) + { + t = KernelArgumentType::SizeD0; + } + else if(strValue == toString(KernelArgumentType::SizeD1)) + { + t = KernelArgumentType::SizeD1; + } else { throw std::runtime_error(concatenate("Invalid argument type: ", strValue)); @@ -1700,17 +1748,29 @@ namespace TensileLite { switch(arg) { - case KernelArgumentType::SizeFree0: - rv.args.template append("SizeFree0", problem.problemSizes()[0]); + case KernelArgumentType::SizeA0: + rv.args.template append("SizeA0", problem.a()[0]); break; - case KernelArgumentType::SizeFree1: - rv.args.template append("SizeFree1", problem.problemSizes()[1]); + case KernelArgumentType::SizeA1: + rv.args.template append("SizeA1", problem.a()[1]); break; - case KernelArgumentType::SizeFree2: - rv.args.template append("SizeFree2", problem.problemSizes()[2]); + case KernelArgumentType::SizeB0: + rv.args.template append("SizeB0", problem.b()[0]); break; - case KernelArgumentType::SizeSum: - rv.args.template append("SizeSum", problem.problemSizes()[3]); + case KernelArgumentType::SizeB1: + rv.args.template append("SizeB1", problem.b()[1]); + break; + case KernelArgumentType::SizeC0: + rv.args.template append("SizeC0", problem.c()[0]); + break; + case KernelArgumentType::SizeC1: + rv.args.template append("SizeC1", problem.c()[1]); + break; + case KernelArgumentType::SizeD0: + rv.args.template append("SizeD0", problem.d()[0]); + break; + case KernelArgumentType::SizeD1: + rv.args.template append("SizeD1", problem.d()[1]); break; case KernelArgumentType::AddressA: rv.args.template append("AddressA", inputs.a); @@ -1725,28 +1785,28 @@ namespace TensileLite rv.args.template append("AddressD", inputs.d); break; case KernelArgumentType::StrideA0: - rv.args.template append("StrideA0", problem.a().strides()[1]); + rv.args.template append("StrideA0", problem.a().strides()[0]); break; case KernelArgumentType::StrideA1: - rv.args.template append("StrideA1", problem.a().strides()[2]); + rv.args.template append("StrideA1", problem.a().strides()[1]); break; case KernelArgumentType::StrideB0: - rv.args.template append("StrideB0", problem.b().strides()[1]); + rv.args.template append("StrideB0", problem.b().strides()[0]); break; case KernelArgumentType::StrideB1: - rv.args.template append("StrideB1", problem.b().strides()[2]); + rv.args.template append("StrideB1", problem.b().strides()[1]); break; case KernelArgumentType::StrideC0: - rv.args.template append("StrideC0", problem.c().strides()[1]); + rv.args.template append("StrideC0", problem.c().strides()[0]); break; case KernelArgumentType::StrideC1: - rv.args.template append("StrideC1", problem.c().strides()[2]); + rv.args.template append("StrideC1", problem.c().strides()[1]); break; case KernelArgumentType::StrideD0: - rv.args.template append("StrideD0", problem.d().strides()[1]); + rv.args.template append("StrideD0", problem.d().strides()[0]); break; case KernelArgumentType::StrideD1: - rv.args.template append("StrideD1", problem.d().strides()[2]); + rv.args.template append("StrideD1", problem.d().strides()[1]); break; case KernelArgumentType::Alpha: rv.args.append("Alpha", inputs.alpha, problem.alphaType()); @@ -1755,22 +1815,22 @@ namespace TensileLite rv.args.append("Beta", inputs.beta, problem.betaType()); break; case KernelArgumentType::ExtentA: - rv.args.template append("ExtentA", problem.problemSizes()[0] * problem.problemSizes()[3]); + rv.args.template append("ExtentA", problem.a().totalLogicalElements()); break; case KernelArgumentType::ExtentB: - rv.args.template append("ExtentB", problem.problemSizes()[1] * problem.problemSizes()[3]); + rv.args.template append("ExtentB", problem.b().totalLogicalElements()); break; case KernelArgumentType::ExtentC: - rv.args.template append("ExtentC", problem.problemSizes()[0] * problem.problemSizes()[1]); + rv.args.template append("ExtentC", problem.c().totalLogicalElements()); break; case KernelArgumentType::ExtentD: - rv.args.template append("ExtentD", problem.problemSizes()[1] * problem.problemSizes()[1]); + rv.args.template append("ExtentD", problem.d().totalLogicalElements()); break; case KernelArgumentType::DebugPattern: // N/A break; default: - throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); + throw std::runtime_error(concatenate("Invalid kernel argument type for rocroller kernel: ", arg)); } } return rv; From 2648f2f3cface0234c9e239cdfa03c3842216e50 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Fri, 27 Feb 2026 00:35:35 +0000 Subject: [PATCH 08/58] Sizes typo fix --- .../tensilelite/src/ContractionSolution.cpp | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 800461774418..e94893af0ece 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1749,28 +1749,28 @@ namespace TensileLite switch(arg) { case KernelArgumentType::SizeA0: - rv.args.template append("SizeA0", problem.a()[0]); + rv.args.template append("SizeA0", problem.a().sizes()[0]); break; case KernelArgumentType::SizeA1: - rv.args.template append("SizeA1", problem.a()[1]); + rv.args.template append("SizeA1", problem.a().sizes()[1]); break; case KernelArgumentType::SizeB0: - rv.args.template append("SizeB0", problem.b()[0]); + rv.args.template append("SizeB0", problem.b().sizes()[0]); break; case KernelArgumentType::SizeB1: - rv.args.template append("SizeB1", problem.b()[1]); + rv.args.template append("SizeB1", problem.b().sizes()[1]); break; case KernelArgumentType::SizeC0: - rv.args.template append("SizeC0", problem.c()[0]); + rv.args.template append("SizeC0", problem.c().sizes()[0]); break; case KernelArgumentType::SizeC1: - rv.args.template append("SizeC1", problem.c()[1]); + rv.args.template append("SizeC1", problem.c().sizes()[1]); break; case KernelArgumentType::SizeD0: - rv.args.template append("SizeD0", problem.d()[0]); + rv.args.template append("SizeD0", problem.d().sizes()[0]); break; case KernelArgumentType::SizeD1: - rv.args.template append("SizeD1", problem.d()[1]); + rv.args.template append("SizeD1", problem.d().sizes()[1]); break; case KernelArgumentType::AddressA: rv.args.template append("AddressA", inputs.a); From f3b0faa5854aca5859d5cd175ed54679154e4b83 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Fri, 27 Feb 2026 03:40:45 +0000 Subject: [PATCH 09/58] Working RR kernel launch --- ...leSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s | 80805 ++++++++++++++++ ..._SwizzleTileSize_8fd6cc113dd5231a_gfx942.s | 20177 ---- .../Tensile/Tests/custom/custom_rr.yaml | 4 +- .../tensilelite/src/ContractionSolution.cpp | 41 +- 4 files changed, 80843 insertions(+), 20184 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s delete mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s new file mode 100644 index 000000000000..c6c34d8f0397 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s @@ -0,0 +1,80805 @@ + // Tensor.Half.d2 0, (base=&0, lim=&8, sizes={&16 &24 }, strides={&32 &40 }) + // T_LOAD_TILED 1 Source 0 + // Tensor.Half.d2 2, (base=&48, lim=&56, sizes={&64 &72 }, strides={&80 &88 }) + // T_LOAD_TILED 3 Source 2 + // Tensor.Half.d2 4, (base=&96, lim=&104, sizes={&112 &120 }, strides={&128 &136 }) + // T_LOAD_TILED 5 Source 4 + // Scalar.Float.6 + // T_LOAD_SCALAR 7Source 6 + // Scalar.Float.8 + // T_LOAD_SCALAR 9Source 8 + // T_Mul 1 3 Value: Float + // T_EXECUTE 7 10 9 5 + // E_Mul 11, 9, 5 + // E_Mul 12, 7, 10 + // E_Add 13, 11, 12 + // Tensor.Half.d2 15, (base=&152, lim=&160, sizes={&168 &176 }, strides={&184 &192 }) + // T_EXECUTE 13 + // E_Cvt 16, 13 + // T_STORE_TILED 18 Source 16 Dest 15 + + // Tensor_0_pointer: PointerGlobal: Half(offset: 0, size: 8, read_write) + // Tensor_0_extent: Value: Int64(offset: 8, size: 8, read_only) + // Tensor_0_size_0: Value: Int64(offset: 16, size: 8, read_only) + // Tensor_0_size_1: Value: Int64(offset: 24, size: 8, read_only) + // Tensor_0_stride_0: Value: Int64(offset: 32, size: 8, read_only) + // Tensor_0_stride_1: Value: Int64(offset: 40, size: 8, read_only) + // Tensor_2_pointer: PointerGlobal: Half(offset: 48, size: 8, read_write) + // Tensor_2_extent: Value: Int64(offset: 56, size: 8, read_only) + // Tensor_2_size_0: Value: Int64(offset: 64, size: 8, read_only) + // Tensor_2_size_1: Value: Int64(offset: 72, size: 8, read_only) + // Tensor_2_stride_0: Value: Int64(offset: 80, size: 8, read_only) + // Tensor_2_stride_1: Value: Int64(offset: 88, size: 8, read_only) + // Tensor_4_pointer: PointerGlobal: Half(offset: 96, size: 8, read_write) + // Tensor_4_extent: Value: Int64(offset: 104, size: 8, read_only) + // Tensor_4_size_0: Value: Int64(offset: 112, size: 8, read_only) + // Tensor_4_size_1: Value: Int64(offset: 120, size: 8, read_only) + // Tensor_4_stride_0: Value: Int64(offset: 128, size: 8, read_only) + // Tensor_4_stride_1: Value: Int64(offset: 136, size: 8, read_only) + // user_Float_Value_6: Value: Float(offset: 144, size: 4, read_only) + // user_Float_Value_8: Value: Float(offset: 148, size: 4, read_only) + // Tensor_15_pointer: PointerGlobal: Half(offset: 152, size: 8, read_write) + // Tensor_15_extent: Value: Int64(offset: 160, size: 8, read_only) + // Tensor_15_size_0: Value: Int64(offset: 168, size: 8, read_only) + // Tensor_15_size_1: Value: Int64(offset: 176, size: 8, read_only) + // Tensor_15_stride_0: Value: Int64(offset: 184, size: 8, read_only) + // Tensor_15_stride_1: Value: Int64(offset: 192, size: 8, read_only) + +.amdgcn_target "amdgcn-amd-amdhsa--gfx942" +.set .amdgcn.next_free_vgpr, 0 +.set .amdgcn.next_free_sgpr, 0 +.text +.globl RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e +.p2align 8 +.type RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e,@function +// Allocated Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 +// Allocated Workgroup Index X: 1 SGPR (Value: UInt32): s2 +// Allocated Workgroup Index Y: 1 SGPR (Value: UInt32): s3 +// Allocated Packed Workitem Index: 1 VGPR (Value: Raw32): v0 +// Allocated Workitem Index X: 1 VGPR (Value: UInt32): v1 +// Allocated Workitem Index Y: 1 VGPR (Value: UInt32): v2 +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e: + + // Kernel Options: + // logLevel: Verbose + // alwaysWaitAfterLoad: false + // alwaysWaitAfterStore: false + // alwaysWaitBeforeBranch: false + // alwaysWaitZeroBeforeBarrier: false + // preloadKernelArguments: true + // maxACCVGPRs: 256 + // maxSGPRs: 102 + // maxVGPRs: 256 + // loadLocalWidth: 4 + // loadGlobalWidth: 8 + // storeLocalWidth: 4 + // storeGlobalWidth: 4 + // assertWaitCntState: true + // setNextFreeVGPRToMax: false + // deduplicateArguments: true + // lazyAddArguments: true + // minLaunchTimeExpressionComplexity: 20 + // maxConcurrentSubExpressions: 2 + // maxConcurrentControlOps: none + // enableFullDivision: false + // scaleSkipPermlane: false + // assertOpKind: NoOp + // removeSetCoordinate: false + + // Loading Kernel Arguments: + // KernelArg{Tensor_0_extent_0, Value: Int64, CommandArgument(Tensor_0_extent)I64(c 0), o:0, s:8} + // KernelArg{Tensor_0_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_0_pointer)PG(c 0), o:8, s:8} + // KernelArg{Tensor_2_extent_2, Value: Int64, CommandArgument(Tensor_2_extent)I64(c 0), o:16, s:8} + // KernelArg{Tensor_2_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_2_pointer)PG(c 0), o:24, s:8} + // KernelArg{Tensor_4_extent_4, Value: Int64, CommandArgument(Tensor_4_extent)I64(c 0), o:32, s:8} + // KernelArg{Tensor_4_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_4_pointer)PG(c 0), o:40, s:8} + // KernelArg{user_Float_Value_6, Value: Float, CommandArgument(user_Float_Value_6)S(c 0), o:48, s:4} + // KernelArg{user_Float_Value_8, Value: Float, CommandArgument(user_Float_Value_8)S(c 0), o:52, s:4} + // KernelArg{Tensor_0_stride_0_9, Value: Int64, CommandArgument(Tensor_0_stride_0)I64(c 0), o:56, s:8} + // KernelArg{Tensor_0_size_1_10, Value: Int64, CommandArgument(Tensor_0_size_1)I64(c 0), o:64, s:8} + // KernelArg{Tensor_2_stride_1_12, Value: Int64, CommandArgument(Tensor_2_stride_1)I64(c 0), o:72, s:8} + // KernelArg{Tensor_4_stride_1_13, Value: Int64, CommandArgument(Tensor_4_stride_1)I64(c 0), o:80, s:8} + // KernelArg{Tensor_15_stride_1_14, Value: Int64, CommandArgument(Tensor_15_stride_1)I64(c 0), o:88, s:8} + // KernelArg{Tensor_15_extent_15, Value: Int64, CommandArgument(Tensor_15_extent)I64(c 0), o:96, s:8} + // KernelArg{Tensor_15_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_15_pointer)PG(c 0), o:104, s:8} + +s_load_dwordx2 s[4:5], s[0:1], 0 // Load scalar value +s_load_dwordx2 s[6:7], s[0:1], 8 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +s_load_dwordx2 s[8:9], s[0:1], 16 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +s_load_dwordx2 s[10:11], s[0:1], 24 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +s_load_dwordx2 s[12:13], s[0:1], 32 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +s_load_dwordx2 s[14:15], s[0:1], 40 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +s_load_dword s16, s[0:1], 48 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +s_load_dword s17, s[0:1], 52 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +s_load_dwordx2 s[18:19], s[0:1], 56 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +s_load_dwordx2 s[20:21], s[0:1], 64 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +s_load_dwordx2 s[22:23], s[0:1], 72 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +s_load_dwordx2 s[24:25], s[0:1], 80 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +// ------Dst: {s[22:23], } +s_load_dwordx2 s[26:27], s[0:1], 88 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +// ------Dst: {s[22:23], } +// ------Dst: {s[24:25], } +s_load_dwordx2 s[28:29], s[0:1], 96 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +// ------Dst: {s[22:23], } +// ------Dst: {s[24:25], } +// ------Dst: {s[26:27], } +s_load_dwordx2 s[30:31], s[0:1], 104 // Load scalar value +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +// ------Dst: {s[22:23], } +// ------Dst: {s[24:25], } +// ------Dst: {s[26:27], } +// ------Dst: {s[28:29], } + // Extract 10 bit X coordinate +v_bfe_u32 v1, v0, 0, 10 // + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Generate {Workitem Index X: v1:U32} into Workitem Index X: VGPR Value: UInt32 x 1: v1 + // Omitting copy to same register: v1, v1 + // reg expression + // Extract 10 bit Y coordinate +v_bfe_u32 v2, v0, 10, 10 // + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Generate {Workitem Index Y: v2:U32} into Workitem Index Y: VGPR Value: UInt32 x 1: v2 + // Omitting copy to same register: v2, v2 + // reg expression + // Freeing Packed Workitem Index: 1 VGPR (Value: Raw32): v0 + + // Freeing Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 + + // Marking Workgroup Index X: SGPR Value: UInt32 x 1: s2 as read-only + // Marking Workgroup Index Y: SGPR Value: UInt32 x 1: s3 as read-only + // Marking Workitem Index X: VGPR Value: UInt32 x 1: v1 as read-only + // Marking Workitem Index Y: VGPR Value: UInt32 x 1: v2 as read-only + // CodeGeneratorVisitor::generate() begin + // IdentifyParallelDimensions + // OrderMemory + // UpdateParameters + // AddLDS + // LowerLinear + // LowerTile + // LowerTensorContraction + // Simplify + // AddLDSPadding + // ConstantPropagation + // FuseExpressions + // ConnectWorkgroups + // WorkgroupRemapXCC + // UnrollLoops + // FuseLoops + // RemoveDuplicates + // OrderEpilogueBlocks + // Simplify + // CleanLoops + // SwizzleScale + // AddPrefetch + // AddF6LDSPadding + // AddDirect2LDS + // Simplify + // AddPRNG + // UpdateWavefrontParameters + // AssignIndexExpressions + // LoadPacked + // AddConvert + // NopExtraScopes + // InlineInits + // InlineIncrements + // RemoveImplicitScheduling + // OrderMultiplyNodes + // Simplify + // ScheduleMultiplyAndLDS + // Simplify + // OrderExchangeNodes + // AliasDataFlowTags + // AddLDSBarriers + // AddDeallocateDataFlow + // CleanArguments + // AddDeallocateArguments + // MergeAdjacentDeallocates + // Simplify + // SetWorkitemCount + // generate({1}) + // Kernel(1) BEGIN + // (op 1) generate({}) + // (op 1) end: generate({}) + // (op 1) generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) + // (op 1) NOP(1239) BEGIN + // (op 1239) generate({}) + // (op 1239) end: generate({}) + // (op 1) NOP(1239) END + // (op 1) NOP(1291) BEGIN + // (op 1291) generate({}) + // (op 1291) end: generate({}) + // (op 1) NOP(1291) END + // (op 1) NOP(1364) BEGIN + // (op 1364) generate({}) + // (op 1364) end: generate({}) + // (op 1) NOP(1364) END + // (op 1) NOP(1403) BEGIN + // (op 1403) generate({}) + // (op 1403) end: generate({}) + // (op 1) NOP(1403) END + // (op 1) NOP(1442) BEGIN + // (op 1442) generate({}) + // (op 1442) end: generate({}) + // (op 1) NOP(1442) END + // (op 1) NOP(1481) BEGIN + // (op 1481) generate({}) + // (op 1481) end: generate({}) + // (op 1) NOP(1481) END + // (op 1) NOP(1520) BEGIN + // (op 1520) generate({}) + // (op 1520) end: generate({}) + // (op 1) NOP(1520) END + // (op 1) NOP(1559) BEGIN + // (op 1559) generate({}) + // (op 1559) end: generate({}) + // (op 1) NOP(1559) END + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) BEGIN + // (op 1243) Assign dim(530) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 530: v**UNALLOCATED** + // (op 1243) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag530: VGPR Value: UInt32 x 1: (unallocated) + // (op 1243) Omitting copy to same register: v1, v1 + // (op 1243) reg expression + // (op 1243) BEGIN: Flatten[1] + // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1243) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) BEGIN + // (op 1295) Assign dim(546) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 546: v**UNALLOCATED** + // (op 1295) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag546: VGPR Value: UInt32 x 1: (unallocated) + // (op 1295) Omitting copy to same register: v1, v1 + // (op 1295) reg expression + // (op 1295) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1295) BEGIN: Flatten[1] + // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) BEGIN + // (op 1368) Assign dim(568) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 568: v**UNALLOCATED** + // (op 1368) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag568: VGPR Value: UInt32 x 1: (unallocated) + // (op 1368) Omitting copy to same register: v1, v1 + // (op 1368) reg expression + // (op 1368) BEGIN: Flatten[1] + // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1368) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) BEGIN + // (op 1407) Assign dim(580) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 580: v**UNALLOCATED** + // (op 1407) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag580: VGPR Value: UInt32 x 1: (unallocated) + // (op 1407) Omitting copy to same register: v1, v1 + // (op 1407) reg expression + // (op 1407) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1407) BEGIN: Flatten[1] + // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) BEGIN + // (op 1446) Assign dim(592) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 592: v**UNALLOCATED** + // (op 1446) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag592: VGPR Value: UInt32 x 1: (unallocated) + // (op 1446) Omitting copy to same register: v1, v1 + // (op 1446) reg expression + // (op 1446) BEGIN: Flatten[1] + // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1446) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) BEGIN + // (op 1485) Assign dim(604) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 604: v**UNALLOCATED** + // (op 1485) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag604: VGPR Value: UInt32 x 1: (unallocated) + // (op 1485) Omitting copy to same register: v1, v1 + // (op 1485) reg expression + // (op 1485) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1485) BEGIN: Flatten[1] + // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) BEGIN + // (op 1524) Assign dim(616) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 616: v**UNALLOCATED** + // (op 1524) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag616: VGPR Value: UInt32 x 1: (unallocated) + // (op 1524) Omitting copy to same register: v1, v1 + // (op 1524) reg expression + // (op 1524) BEGIN: Flatten[1] + // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1524) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) BEGIN + // (op 1563) Assign dim(628) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 + // tag 628: v**UNALLOCATED** + // (op 1563) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag628: VGPR Value: UInt32 x 1: (unallocated) + // (op 1563) Omitting copy to same register: v1, v1 + // (op 1563) reg expression + // (op 1563) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 + // (op 1563) BEGIN: Flatten[1] + // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 +v_and_b32 v0, 63, v1 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 +v_lshrrev_b32 v3, 7, v1 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) BEGIN: Flatten[1] + // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1243) LogicalShiftR({Flatten[1]: v0:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v4 +v_and_b32 v4, 31, v1 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v5 +v_lshrrev_b32 v5, 5, v0 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v0 + + // (op 1243) BEGIN: Tile + // (op 1243) BEGIN: TileTile + // (op 1243) {TileTile: ShiftL(v5:U32, 2:U32)U32} + // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1243) value (VGPR Value: UInt32 x 1: v5) + // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 +v_lshl_add_u32 v0, v3, 5, v4 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v4 + + // Freeing : 1 VGPR (Value: UInt32) (op 1243): v3 + +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v4 +v_lshlrev_b32 v4, 2, v5 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1243): v5 + + // (op 1243) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 +v_lshl_add_u32 v3, v0, 6, v4 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1243) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1243): v4 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v0 + + // (op 1243) ShiftL({Tile: v3:U32}, 1:U32)U32 + // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1243) value (Tile: VGPR Value: UInt32 x 1: v3) + // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 +v_lshlrev_b32 v0, 1, v3 // (op 1243) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v3 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) END +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_lshrrev_b32 v3, 6, v1 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 +v_and_b32 v4, 63, v1 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: Flatten[1] + // (op 1295) BEGIN: Tile + // (op 1295) {Tile: BitwiseAnd(v3:U32, 1:U32)U32} + // (op 1295) BEGIN: Flatten[1] + // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v5 +v_and_b32 v5, 1, v3 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1295): v3 + +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_and_b32 v3, 31, v1 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: Flatten[1] + // (op 1295) LogicalShiftR({Flatten[1]: v4:U32}, 5:U32)U32 + // (op 1295) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v6 +v_lshrrev_b32 v6, 5, v4 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v4 + +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 +v_lshl_add_u32 v4, v5, 5, v3 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v3 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v5 + + // (op 1295) BEGIN: TileTile + // (op 1295) {TileTile: ShiftL(v6:U32, 2:U32)U32} + // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1295) value (VGPR Value: UInt32 x 1: v6) + // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 +v_lshlrev_b32 v3, 2, v6 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1295): v6 + + // (op 1295) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1295): v5 +v_lshl_add_u32 v5, v4, 6, v3 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1295) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1295): v3 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v4 + + // (op 1295) ShiftL({Tile: v5:U32}, 1:U32)U32 + // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1295) value (Tile: VGPR Value: UInt32 x 1: v5) + // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v4 +v_lshlrev_b32 v4, 1, v5 // (op 1295) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v5 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) END +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v3 +v_and_b32 v3, 63, v1 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 +v_lshrrev_b32 v5, 7, v1 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) BEGIN: Flatten[1] + // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1368) LogicalShiftR({Flatten[1]: v3:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v6 +v_and_b32 v6, 31, v1 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v7 +v_lshrrev_b32 v7, 5, v3 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v3 + + // (op 1368) BEGIN: Tile + // (op 1368) BEGIN: TileTile + // (op 1368) {TileTile: ShiftL(v7:U32, 2:U32)U32} + // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1368) value (VGPR Value: UInt32 x 1: v7) + // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v3 +v_lshl_add_u32 v3, v5, 5, v6 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v6 + + // Freeing : 1 VGPR (Value: UInt32) (op 1368): v5 + +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v6 +v_lshlrev_b32 v6, 2, v7 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1368): v7 + + // (op 1368) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 +v_lshl_add_u32 v5, v3, 6, v6 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1368) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1368): v6 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v3 + + // (op 1368) ShiftL({Tile: v5:U32}, 1:U32)U32 + // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1368) value (Tile: VGPR Value: UInt32 x 1: v5) + // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v3 +v_lshlrev_b32 v3, 1, v5 // (op 1368) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v5 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) END +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_lshrrev_b32 v5, 6, v1 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 +v_and_b32 v6, 63, v1 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: Flatten[1] + // (op 1407) BEGIN: Tile + // (op 1407) {Tile: BitwiseAnd(v5:U32, 1:U32)U32} + // (op 1407) BEGIN: Flatten[1] + // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v7 +v_and_b32 v7, 1, v5 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1407): v5 + +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_and_b32 v5, 31, v1 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: Flatten[1] + // (op 1407) LogicalShiftR({Flatten[1]: v6:U32}, 5:U32)U32 + // (op 1407) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v8 +v_lshrrev_b32 v8, 5, v6 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v6 + +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 +v_lshl_add_u32 v6, v7, 5, v5 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v5 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v7 + + // (op 1407) BEGIN: TileTile + // (op 1407) {TileTile: ShiftL(v8:U32, 2:U32)U32} + // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1407) value (VGPR Value: UInt32 x 1: v8) + // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 +v_lshlrev_b32 v5, 2, v8 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1407): v8 + + // (op 1407) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1407): v7 +v_lshl_add_u32 v7, v6, 6, v5 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1407) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1407): v5 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v6 + + // (op 1407) ShiftL({Tile: v7:U32}, 1:U32)U32 + // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1407) value (Tile: VGPR Value: UInt32 x 1: v7) + // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v6 +v_lshlrev_b32 v6, 1, v7 // (op 1407) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v7 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) END +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v5 +v_and_b32 v5, 63, v1 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 +v_lshrrev_b32 v7, 7, v1 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) BEGIN: Flatten[1] + // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1446) LogicalShiftR({Flatten[1]: v5:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v8 +v_and_b32 v8, 31, v1 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v9 +v_lshrrev_b32 v9, 5, v5 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v5 + + // (op 1446) BEGIN: Tile + // (op 1446) BEGIN: TileTile + // (op 1446) {TileTile: ShiftL(v9:U32, 2:U32)U32} + // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1446) value (VGPR Value: UInt32 x 1: v9) + // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v5 +v_lshl_add_u32 v5, v7, 5, v8 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v8 + + // Freeing : 1 VGPR (Value: UInt32) (op 1446): v7 + +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v8 +v_lshlrev_b32 v8, 2, v9 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1446): v9 + + // (op 1446) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 +v_lshl_add_u32 v7, v5, 6, v8 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1446) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1446): v8 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v5 + + // (op 1446) ShiftL({Tile: v7:U32}, 1:U32)U32 + // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1446) value (Tile: VGPR Value: UInt32 x 1: v7) + // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v5 +v_lshlrev_b32 v5, 1, v7 // (op 1446) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v7 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) END +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_lshrrev_b32 v7, 6, v1 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 +v_and_b32 v8, 63, v1 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: Flatten[1] + // (op 1485) BEGIN: Tile + // (op 1485) {Tile: BitwiseAnd(v7:U32, 1:U32)U32} + // (op 1485) BEGIN: Flatten[1] + // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v9 +v_and_b32 v9, 1, v7 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1485): v7 + +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_and_b32 v7, 31, v1 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: Flatten[1] + // (op 1485) LogicalShiftR({Flatten[1]: v8:U32}, 5:U32)U32 + // (op 1485) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v10 +v_lshrrev_b32 v10, 5, v8 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 +v_lshl_add_u32 v8, v9, 5, v7 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v7 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v9 + + // (op 1485) BEGIN: TileTile + // (op 1485) {TileTile: ShiftL(v10:U32, 2:U32)U32} + // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1485) value (VGPR Value: UInt32 x 1: v10) + // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 +v_lshlrev_b32 v7, 2, v10 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1485): v10 + + // (op 1485) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1485): v9 +v_lshl_add_u32 v9, v8, 6, v7 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1485) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1485): v7 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v8 + + // (op 1485) ShiftL({Tile: v9:U32}, 1:U32)U32 + // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1485) value (Tile: VGPR Value: UInt32 x 1: v9) + // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v8 +v_lshlrev_b32 v8, 1, v9 // (op 1485) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v9 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) END +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v7 +v_and_b32 v7, 63, v1 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 +v_lshrrev_b32 v9, 7, v1 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) BEGIN: Flatten[1] + // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1524) LogicalShiftR({Flatten[1]: v7:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v10 +v_and_b32 v10, 31, v1 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v11 +v_lshrrev_b32 v11, 5, v7 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v7 + + // (op 1524) BEGIN: Tile + // (op 1524) BEGIN: TileTile + // (op 1524) {TileTile: ShiftL(v11:U32, 2:U32)U32} + // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1524) value (VGPR Value: UInt32 x 1: v11) + // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v7 +v_lshl_add_u32 v7, v9, 5, v10 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v10 + + // Freeing : 1 VGPR (Value: UInt32) (op 1524): v9 + +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v10 +v_lshlrev_b32 v10, 2, v11 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1524): v11 + + // (op 1524) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 +v_lshl_add_u32 v9, v7, 6, v10 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1524) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1524): v10 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v7 + + // (op 1524) ShiftL({Tile: v9:U32}, 1:U32)U32 + // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1524) value (Tile: VGPR Value: UInt32 x 1: v9) + // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v7 +v_lshlrev_b32 v7, 1, v9 // (op 1524) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v9 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_lshrrev_b32 v9, 6, v1 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1) Deallocate{}(1913) BEGIN + // (op 1913) Deallocate 84 + // Deleting tag 84 + // (op 1) Deallocate{}(1913) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 +v_and_b32 v10, 63, v1 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: Flatten[1] + // (op 1563) BEGIN: Tile + // (op 1563) {Tile: BitwiseAnd(v9:U32, 1:U32)U32} + // (op 1563) BEGIN: Flatten[1] + // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} + // (op 1) Assign VGPR 16:U32(1244) BEGIN + // (op 1244) Assign dim(531) = 16:U32 + // (op 1244) Assign stride expression + // (op 1) Assign VGPR 16:U32(1244) END + // (op 1) Assign VGPR 16:U32(1369) BEGIN + // (op 1369) Assign dim(569) = 16:U32 + // (op 1369) Assign stride expression + // (op 1) Assign VGPR 16:U32(1369) END + // (op 1) Assign VGPR 16:U32(1447) BEGIN + // (op 1447) Assign dim(593) = 16:U32 + // (op 1447) Assign stride expression + // (op 1) Assign VGPR 16:U32(1447) END + // (op 1) Assign VGPR 16:U32(1525) BEGIN + // (op 1525) Assign dim(617) = 16:U32 + // (op 1525) Assign stride expression + // (op 1) Assign VGPR 16:U32(1525) END + // (op 1) NOP(1240) BEGIN + // (op 1240) generate({}) + // (op 1240) end: generate({}) + // (op 1) NOP(1240) END + // (op 1) NOP(1365) BEGIN + // (op 1365) generate({}) + // (op 1365) end: generate({}) + // (op 1) NOP(1365) END + // (op 1) NOP(1443) BEGIN + // (op 1443) generate({}) + // (op 1443) end: generate({}) + // (op 1) NOP(1443) END + // (op 1) NOP(1521) BEGIN + // (op 1521) generate({}) + // (op 1521) end: generate({}) + // (op 1) NOP(1521) END + // (op 1) Assign VGPR 2:U32(1248) BEGIN + // (op 1248) Assign dim(533) = 2:U32 + // (op 1248) Assign stride expression + // (op 1) Assign VGPR 2:U32(1248) END + // (op 1) Assign VGPR 2:U32(1373) BEGIN + // (op 1373) Assign dim(571) = 2:U32 + // (op 1373) Assign stride expression + // (op 1) Assign VGPR 2:U32(1373) END + // (op 1) Assign VGPR 2:U32(1451) BEGIN + // (op 1451) Assign dim(595) = 2:U32 + // (op 1451) Assign stride expression + // (op 1) Assign VGPR 2:U32(1451) END + // (op 1) Assign VGPR 2:U32(1529) BEGIN + // (op 1529) Assign dim(619) = 2:U32 + // (op 1529) Assign stride expression + // (op 1) Assign VGPR 2:U32(1529) END +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v11 +v_and_b32 v11, 1, v9 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1563): v9 + +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_and_b32 v9, 31, v1 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: Flatten[1] + // (op 1563) LogicalShiftR({Flatten[1]: v10:U32}, 5:U32)U32 + // (op 1563) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v12 +v_lshrrev_b32 v12, 5, v10 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v10 + +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 +v_lshl_add_u32 v10, v11, 5, v9 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v9 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v11 + + // (op 1563) BEGIN: TileTile + // (op 1563) {TileTile: ShiftL(v12:U32, 2:U32)U32} + // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1563) value (VGPR Value: UInt32 x 1: v12) + // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 2) +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 +v_lshlrev_b32 v9, 2, v12 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: TileTile + // Freeing : 1 VGPR (Value: UInt32) (op 1563): v12 + + // (op 1563) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1563): v11 +v_lshl_add_u32 v11, v10, 6, v9 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // (op 1563) END: Tile + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1563): v9 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v10 + + // (op 1563) ShiftL({Tile: v11:U32}, 1:U32)U32 + // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1563) value (Tile: VGPR Value: UInt32 x 1: v11) + // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v10 +v_lshlrev_b32 v10, 1, v11 // (op 1563) + // Wait Queue State: + // --Queue: KMQueue + // ----Needs Wait Zero: True + // ----Type In Queue : SMemQueue + // ----Registers : + // ------Dst: {s[4:5], } + // ------Dst: {s[6:7], } + // ------Dst: {s[8:9], } + // ------Dst: {s[10:11], } + // ------Dst: {s[12:13], } + // ------Dst: {s[14:15], } + // ------Dst: {s16, } + // ------Dst: {s17, } + // ------Dst: {s[18:19], } + // ------Dst: {s[20:21], } + // ------Dst: {s[22:23], } + // ------Dst: {s[24:25], } + // ------Dst: {s[26:27], } + // ------Dst: {s[28:29], } + // ------Dst: {s[30:31], } + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v11 + + // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) END + // (op 1) Deallocate{}(1918) BEGIN + // (op 1918) Deallocate 144 + // Deleting tag 144 + // (op 1) Deallocate{}(1918) END + // (op 1) Assign VGPR 16:U32(1296) BEGIN + // (op 1296) Assign dim(547) = 16:U32 + // (op 1296) Assign stride expression + // (op 1) Assign VGPR 16:U32(1296) END + // (op 1) Assign VGPR 16:U32(1408) BEGIN + // (op 1408) Assign dim(581) = 16:U32 + // (op 1408) Assign stride expression + // (op 1) Assign VGPR 16:U32(1408) END + // (op 1) Assign VGPR 16:U32(1486) BEGIN + // (op 1486) Assign dim(605) = 16:U32 + // (op 1486) Assign stride expression + // (op 1) Assign VGPR 16:U32(1486) END + // (op 1) Assign VGPR 16:U32(1564) BEGIN + // (op 1564) Assign dim(629) = 16:U32 + // (op 1564) Assign stride expression + // (op 1) Assign VGPR 16:U32(1564) END + // (op 1) NOP(1292) BEGIN + // (op 1292) generate({}) + // (op 1292) end: generate({}) + // (op 1) NOP(1292) END + // (op 1) NOP(1404) BEGIN + // (op 1404) generate({}) + // (op 1404) end: generate({}) + // (op 1) NOP(1404) END + // (op 1) NOP(1482) BEGIN + // (op 1482) generate({}) + // (op 1482) end: generate({}) + // (op 1) NOP(1482) END + // (op 1) NOP(1560) BEGIN + // (op 1560) generate({}) + // (op 1560) end: generate({}) + // (op 1) NOP(1560) END + // (op 1) Assign VGPR 2:U32(1300) BEGIN + // (op 1300) Assign dim(549) = 2:U32 + // (op 1300) Assign stride expression + // (op 1) Assign VGPR 2:U32(1300) END + // (op 1) Assign VGPR 2:U32(1412) BEGIN + // (op 1412) Assign dim(583) = 2:U32 + // (op 1412) Assign stride expression + // (op 1) Assign VGPR 2:U32(1412) END + // (op 1) Assign VGPR 2:U32(1490) BEGIN + // (op 1490) Assign dim(607) = 2:U32 + // (op 1490) Assign stride expression + // (op 1) Assign VGPR 2:U32(1490) END + // (op 1) Assign VGPR 2:U32(1568) BEGIN + // (op 1568) Assign dim(631) = 2:U32 + // (op 1568) Assign stride expression + // (op 1) Assign VGPR 2:U32(1568) END + // (op 1) LoadVGPR Value: Float(2) BEGIN + // tag 24: v**UNALLOCATED** + // (op 2) GEN: LoadVGPR; scalar value + // (op 1) LoadVGPR Value: Float(24) BEGIN + // tag 33: v**UNALLOCATED** + // (op 24) GEN: LoadVGPR; scalar value +// Allocated : 1 VGPR (Value: Float) (op 2): v9 +s_waitcnt lgkmcnt(0) +v_mov_b32 v9, s17 // (op 2) Move value +// WaitCnt Needed: Intersects with registers in 'KMQueue', which needs a wait zero. + +// +// Wait Queue State: +// --Queue: KMQueue +// ----Needs Wait Zero: True +// ----Type In Queue : SMemQueue +// ----Registers : +// ------Dst: {s[4:5], } +// ------Dst: {s[6:7], } +// ------Dst: {s[8:9], } +// ------Dst: {s[10:11], } +// ------Dst: {s[12:13], } +// ------Dst: {s[14:15], } +// ------Dst: {s16, } +// ------Dst: {s17, } +// ------Dst: {s[18:19], } +// ------Dst: {s[20:21], } +// ------Dst: {s[22:23], } +// ------Dst: {s[24:25], } +// ------Dst: {s[26:27], } +// ------Dst: {s[28:29], } +// ------Dst: {s[30:31], } + // (op 1) LoadVGPR Value: Float(2) END +// Allocated : 1 VGPR (Value: Float) (op 24): v11 +v_mov_b32 v11, s16 // (op 24) Move value + // (op 1) LoadVGPR Value: Float(24) END + // (op 1) Deallocate{user_Float_Value_8}(1997) BEGIN + // (op 1997) Deallocate user_Float_Value_8 + // Freeing user_Float_Value_8: 1 SGPR (Value: Raw32): s17 + + // (op 1) Deallocate{user_Float_Value_8}(1997) END + // (op 1) Deallocate{user_Float_Value_6}(1999) BEGIN + // (op 1999) Deallocate user_Float_Value_6 + // Freeing user_Float_Value_6: 1 SGPR (Value: Raw32): s16 + + // (op 1) Deallocate{user_Float_Value_6}(1999) END + // (op 1) Scope(670) BEGIN + // (op 670) Lock Scope 670 + // Lock Branch + // (op 670) generate({675}) + // (op 670) NOP(675) BEGIN + // (op 675) generate({}) + // (op 675) end: generate({}) + // (op 670) NOP(675) END + // (op 670) Assign ACCVGPR 0.00000:S(44) BEGIN + // (op 44) Assign dim(35) = 0.00000:S + // tag 35: a**UNALLOCATED** + // (op 44) Generate 0.00000:S into DataFlowTag35: ACCVGPR Value: Float x 16: (unallocated) +// Allocated DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 +v_accvgpr_write a0, 0.00000 // (op 44) call() +v_accvgpr_write a1, 0.00000 // (op 44) call() +v_accvgpr_write a2, 0.00000 // (op 44) call() +v_accvgpr_write a3, 0.00000 // (op 44) call() +v_accvgpr_write a4, 0.00000 // (op 44) call() +v_accvgpr_write a5, 0.00000 // (op 44) call() +v_accvgpr_write a6, 0.00000 // (op 44) call() +v_accvgpr_write a7, 0.00000 // (op 44) call() +v_accvgpr_write a8, 0.00000 // (op 44) call() +v_accvgpr_write a9, 0.00000 // (op 44) call() +v_accvgpr_write a10, 0.00000 // (op 44) call() +v_accvgpr_write a11, 0.00000 // (op 44) call() +v_accvgpr_write a12, 0.00000 // (op 44) call() +v_accvgpr_write a13, 0.00000 // (op 44) call() +v_accvgpr_write a14, 0.00000 // (op 44) call() +v_accvgpr_write a15, 0.00000 // (op 44) call() + // (op 670) Assign ACCVGPR 0.00000:S(44) END + // (op 670) Scope(1074) BEGIN + // (op 1074) Lock Scope 1074 + // Lock Branch + // (op 1074) generate({1069}) + // (op 1074) NOP(1069) BEGIN + // (op 1069) generate({}) + // (op 1069) end: generate({}) + // (op 1074) NOP(1069) END + // (op 1074) Assign VGPR 128:U64(1079) BEGIN + // (op 1079) Assign dim(482) = 128:U64 + // (op 1079) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1079) END + // (op 1074) NOP(1070) BEGIN + // (op 1070) generate({}) + // (op 1070) end: generate({}) + // (op 1074) NOP(1070) END + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) BEGIN + // (op 1082) Assign dim(483) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 + // tag 483: v**UNALLOCATED** + // (op 1082) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag483: VGPR Value: UInt64 x 1: (unallocated) + // (op 1082) Omitting copy to same register: s2, s2 + // (op 1082) reg expression + // (op 1082) Omitting copy to same register: s[18:19], s[18:19] + // (op 1082) reg expression + // (op 1082) Omitting copy to same register: v1, v1 + // (op 1082) reg expression + // (op 1082) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1082) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 +v_and_b32 v12, -32, v1 // (op 1082) +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v13 +v_lshrrev_b32 v13, 5, v1 // (op 1082) + // (op 1082) BEGIN: Flatten[1] + // (op 1082) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} + // (op 1082) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v14 +v_sub_u32 v14, v1, v12 // (op 1082) + // (op 1082) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1082): v12 + +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 +v_lshl_add_u32 v12, s2, 6, v13 // (op 1082) + // (op 1082) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1082): v13 + + // (op 1082) BEGIN: TileTile + // (op 1082) {TileTile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} + // (op 1082) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1082) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) + // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1082): v13 +v_lshlrev_b32 v13, 1, v14 // (op 1082) + // (op 1082) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1082): v14 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 +v_mov_b32 v15, 0 // (op 1082) convert +v_mov_b32 v14, v13 // (op 1082) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1082): v13 + + // (op 1082) BEGIN: Split + // (op 1082) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1082) lhs (Tile: VGPR Value: UInt32 x 1: v12) + // (op 1082) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1082): v16, v17 +v_mul_lo_u32 v17, v12, s19 // (op 1082) most significant: low of low * high + // (op 1082) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1082): v13 +v_mul_hi_u32 v13, v12, s18 // (op 1082) most significant: high of low * low +v_mul_lo_u32 v16, v12, s18 // (op 1082) least significant: low of low * low +v_add_u32 v17, v17, v13 // (op 1082) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1082): v13 + + // (op 1082) Add: dest (VGPR Value: UInt64 x 1: v[16:17]) = + // (op 1082) lhs (VGPR Value: UInt64 x 1: v[16:17]) + // (op 1082) rhs (TileTile: VGPR Value: UInt64 x 1: v[14:15]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 +v_add_co_u32 v16, s[0:1], v16, v14 // (op 1082) least significant half +v_addc_co_u32 v17, s[0:1], v17, v15, s[0:1] // (op 1082) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 + + // (op 1082) END: Split + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1082): v12 + + // (op 1082) ShiftL({Split: v[16:17]:U64}, 1:U32)U64 + // (op 1082) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1082) value (Split: VGPR Value: UInt64 x 1: v[16:17]) + // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 +v_lshlrev_b64 v[14:15], 1, v[16:17] // (op 1082) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1082): v16, v17 + + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) BEGIN + // (op 1083) Assign dim(484) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1083) Assign stride expression + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) END + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) BEGIN + // (op 1084) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 477: s**UNALLOCATED** + // (op 1084) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: (unallocated) + // (op 1084) Omitting copy to same register: s[4:5], s[4:5] + // (op 1084) reg expression + // (op 1084) Omitting copy to same register: s[6:7], s[6:7] + // (op 1084) reg expression + // (op 1084) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1084) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1084) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1084) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1084): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1084) + // (op 1084) Omitting copy to same register: s0, s0 + // (op 1084) reg expression +// Allocated DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 +s_mov_b32 s32, s6 // (op 1084) reg expression +s_mov_b32 s33, s7 // (op 1084) reg expression +s_mov_b32 s34, s0 // (op 1084) reg expression +s_mov_b32 s35, 131072 // (op 1084) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1084): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) END + // (op 1074) NOP(1071) BEGIN + // (op 1071) generate({}) + // (op 1071) end: generate({}) + // (op 1074) NOP(1071) END + // (op 1074) Assign VGPR 2:U64(1089) BEGIN + // (op 1089) Assign dim(486) = 2:U64 + // (op 1089) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1089) END + // (op 1074) NOP(1092) BEGIN + // (op 1092) generate({}) + // (op 1092) end: generate({}) + // (op 1074) NOP(1092) END + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) BEGIN + // (op 1101) Assign dim(487) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 + // tag 487: v**UNALLOCATED** + // (op 1101) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: (unallocated) + // (op 1101) Omitting copy to same register: s2, s2 + // (op 1101) reg expression + // (op 1101) Omitting copy to same register: s[18:19], s[18:19] + // (op 1101) reg expression + // (op 1101) Omitting copy to same register: v1, v1 + // (op 1101) reg expression + // (op 1101) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1101) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v13 +v_and_b32 v13, -32, v1 // (op 1101) +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v12 +v_lshrrev_b32 v12, 5, v1 // (op 1101) + // (op 1101) BEGIN: Flatten[1] + // (op 1101) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v13:U32)U32} + // (op 1101) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v16 +v_sub_u32 v16, v1, v13 // (op 1101) + // (op 1101) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1101): v13 + +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v13 +v_lshl_add_u32 v13, s2, 6, v12 // (op 1101) + // (op 1101) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1101): v12 + + // (op 1101) BEGIN: TileTile + // (op 1101) {TileTile: ShiftL({Flatten[1]: v16:U32}, 1:U32)U32} + // (op 1101) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1101) value (Flatten[1]: VGPR Value: UInt32 x 1: v16) + // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1101): v12 +v_lshlrev_b32 v12, 1, v16 // (op 1101) + // (op 1101) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1101): v16 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 +v_mov_b32 v17, 0 // (op 1101) convert +v_mov_b32 v16, v12 // (op 1101) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1101): v12 + + // (op 1101) BEGIN: Split + // (op 1101) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1101) lhs (Tile: VGPR Value: UInt32 x 1: v13) + // (op 1101) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1101): v18, v19 +v_mul_lo_u32 v19, v13, s19 // (op 1101) most significant: low of low * high + // (op 1101) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1101): v12 +v_mul_hi_u32 v12, v13, s18 // (op 1101) most significant: high of low * low +v_mul_lo_u32 v18, v13, s18 // (op 1101) least significant: low of low * low +v_add_u32 v19, v19, v12 // (op 1101) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1101): v12 + + // (op 1101) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1101) lhs (VGPR Value: UInt64 x 1: v[18:19]) + // (op 1101) rhs (TileTile: VGPR Value: UInt64 x 1: v[16:17]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 +v_add_co_u32 v18, s[0:1], v18, v16 // (op 1101) least significant half +v_addc_co_u32 v19, s[0:1], v19, v17, s[0:1] // (op 1101) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 + + // (op 1101) END: Split + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1101): v13 + + // (op 1101) ShiftL({Split: v[18:19]:U64}, 1:U32)U64 + // (op 1101) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1101) value (Split: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v12, v13 +v_lshlrev_b64 v[12:13], 1, v[18:19] // (op 1101) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1101): v18, v19 + + // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) END + // (op 1074) Assign VGPR 128:U64(1102) BEGIN + // (op 1102) Assign dim(488) = 128:U64 + // (op 1102) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1102) END + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) BEGIN + // (op 1103) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1103) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // (op 1103) Omitting copy to same register: s[4:5], s[4:5] + // (op 1103) reg expression + // (op 1103) Omitting copy to same register: s[6:7], s[6:7] + // (op 1103) reg expression + // (op 1103) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1103) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1103) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1103) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1103): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1103) + // (op 1103) Omitting copy to same register: s0, s0 + // (op 1103) reg expression +s_mov_b32 s32, s6 // (op 1103) reg expression +s_mov_b32 s33, s7 // (op 1103) reg expression +s_mov_b32 s34, s0 // (op 1103) reg expression +s_mov_b32 s35, 131072 // (op 1103) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1103): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) END + // (op 1074) NOP(1094) BEGIN + // (op 1094) generate({}) + // (op 1094) end: generate({}) + // (op 1074) NOP(1094) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) BEGIN + // (op 1108) Assign dim(490) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1108) Assign stride expression + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) END + // (op 1074) NOP(1095) BEGIN + // (op 1095) generate({}) + // (op 1095) end: generate({}) + // (op 1074) NOP(1095) END + // (op 1074) Assign VGPR 2:U64(1111) BEGIN + // (op 1111) Assign dim(492) = 2:U64 + // (op 1111) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1111) END + // (op 1074) NOP(1136) BEGIN + // (op 1136) generate({}) + // (op 1136) end: generate({}) + // (op 1074) NOP(1136) END + // (op 1074) Assign VGPR 128:U64(1143) BEGIN + // (op 1143) Assign dim(501) = 128:U64 + // (op 1143) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1143) END + // (op 1074) NOP(1137) BEGIN + // (op 1137) generate({}) + // (op 1137) end: generate({}) + // (op 1074) NOP(1137) END + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) BEGIN + // (op 1146) Assign dim(502) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 502: v**UNALLOCATED** + // (op 1146) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag502: VGPR Value: UInt64 x 1: (unallocated) + // (op 1146) Omitting copy to same register: s3, s3 + // (op 1146) reg expression + // (op 1146) Omitting copy to same register: s[22:23], s[22:23] + // (op 1146) reg expression + // (op 1146) Omitting copy to same register: v1, v1 + // (op 1146) reg expression + // (op 1146) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1146) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 +v_and_b32 v16, -32, v1 // (op 1146) +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1146) + // (op 1146) BEGIN: Flatten[1] + // (op 1146) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} + // (op 1146) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v18 +v_sub_u32 v18, v1, v16 // (op 1146) + // (op 1146) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1146): v16 + +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 +v_lshl_add_u32 v16, s3, 6, v17 // (op 1146) + // (op 1146) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1146): v17 + + // (op 1146) BEGIN: TileTile + // (op 1146) {TileTile: ShiftL({Flatten[1]: v18:U32}, 1:U32)U32} + // (op 1146) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1146) value (Flatten[1]: VGPR Value: UInt32 x 1: v18) + // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 1146) Multiply({Tile: v16:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1146) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1146) lhs (Tile: VGPR Value: UInt32 x 1: v16) + // (op 1146) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 +v_lshlrev_b32 v17, 1, v18 // (op 1146) + // (op 1146) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1146): v18 + +// Allocated : 2 VGPRs (Value: Int64) (op 1146): v18, v19 +v_mul_lo_u32 v19, v16, s23 // (op 1146) most significant: low of low * high + // (op 1146) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1146): v20 +v_mul_hi_u32 v20, v16, s22 // (op 1146) most significant: high of low * low +v_mul_lo_u32 v18, v16, s22 // (op 1146) least significant: low of low * low +v_add_u32 v19, v19, v20 // (op 1146) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1146): v20 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1146): v16 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1146): v20, v21 +v_mov_b32 v21, 0 // (op 1146) convert +v_mov_b32 v20, v17 // (op 1146) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1146): v17 + + // (op 1146) BEGIN: Split + // (op 1146) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1146) lhs (TileTile: VGPR Value: UInt64 x 1: v[20:21]) + // (op 1146) rhs (VGPR Value: Int64 x 1: v[18:19]) +// Allocated DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 +// Allocated : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 +v_add_co_u32 v16, s[0:1], v20, v18 // (op 1146) least significant half +v_addc_co_u32 v17, s[0:1], v21, v19, s[0:1] // (op 1146) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 + + // (op 1146) ShiftL: dest (VGPR Value: UInt64 x 1: v[16:17]) = + // (op 1146) value (VGPR Value: UInt64 x 1: v[16:17]) + // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[16:17], 1, v[16:17] // (op 1146) + // (op 1146) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1146): v18, v19 + + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1146): v20, v21 + + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) BEGIN + // (op 1147) Assign dim(503) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1147) Assign stride expression + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) END + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) BEGIN + // (op 1148) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 496: s**UNALLOCATED** + // (op 1148) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: (unallocated) + // (op 1148) Omitting copy to same register: s[8:9], s[8:9] + // (op 1148) reg expression + // (op 1148) Omitting copy to same register: s[10:11], s[10:11] + // (op 1148) reg expression + // (op 1148) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1148) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1148) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1148) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1148): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1148) + // (op 1148) Omitting copy to same register: s0, s0 + // (op 1148) reg expression +// Allocated DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 +s_mov_b32 s36, s10 // (op 1148) reg expression +s_mov_b32 s37, s11 // (op 1148) reg expression +s_mov_b32 s38, s0 // (op 1148) reg expression +s_mov_b32 s39, 131072 // (op 1148) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1148): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) END + // (op 1074) NOP(1138) BEGIN + // (op 1138) generate({}) + // (op 1138) end: generate({}) + // (op 1074) NOP(1138) END + // (op 1074) Assign VGPR 2:U64(1153) BEGIN + // (op 1153) Assign dim(505) = 2:U64 + // (op 1153) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1153) END + // (op 1074) NOP(1156) BEGIN + // (op 1156) generate({}) + // (op 1156) end: generate({}) + // (op 1074) NOP(1156) END + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) BEGIN + // (op 1165) Assign dim(506) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 506: v**UNALLOCATED** + // (op 1165) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag506: VGPR Value: UInt64 x 1: (unallocated) + // (op 1165) Omitting copy to same register: s3, s3 + // (op 1165) reg expression + // (op 1165) Omitting copy to same register: s[22:23], s[22:23] + // (op 1165) reg expression + // (op 1165) Omitting copy to same register: v1, v1 + // (op 1165) reg expression + // (op 1165) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1165) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 +v_and_b32 v18, -32, v1 // (op 1165) +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 +v_lshrrev_b32 v19, 5, v1 // (op 1165) + // (op 1165) BEGIN: Flatten[1] + // (op 1165) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v18:U32)U32} + // (op 1165) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v20 +v_sub_u32 v20, v1, v18 // (op 1165) + // (op 1165) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1165): v18 + +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 +v_lshl_add_u32 v18, s3, 6, v19 // (op 1165) + // (op 1165) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1165): v19 + + // (op 1165) BEGIN: TileTile + // (op 1165) {TileTile: ShiftL({Flatten[1]: v20:U32}, 1:U32)U32} + // (op 1165) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1165) value (Flatten[1]: VGPR Value: UInt32 x 1: v20) + // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 1165) Multiply({Tile: v18:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1165) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1165) lhs (Tile: VGPR Value: UInt32 x 1: v18) + // (op 1165) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 +v_lshlrev_b32 v19, 1, v20 // (op 1165) + // (op 1165) END: TileTile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1165): v20 + +// Allocated : 2 VGPRs (Value: Int64) (op 1165): v20, v21 +v_mul_lo_u32 v21, v18, s23 // (op 1165) most significant: low of low * high + // (op 1165) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1165): v22 +v_mul_hi_u32 v22, v18, s22 // (op 1165) most significant: high of low * low +v_mul_lo_u32 v20, v18, s22 // (op 1165) least significant: low of low * low +v_add_u32 v21, v21, v22 // (op 1165) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1165): v22 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1165): v18 + +// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1165): v22, v23 +v_mov_b32 v23, 0 // (op 1165) convert +v_mov_b32 v22, v19 // (op 1165) convert + // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1165): v19 + + // (op 1165) BEGIN: Split + // (op 1165) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1165) lhs (TileTile: VGPR Value: UInt64 x 1: v[22:23]) + // (op 1165) rhs (VGPR Value: Int64 x 1: v[20:21]) +// Allocated DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 +// Allocated : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 +v_add_co_u32 v18, s[0:1], v22, v20 // (op 1165) least significant half +v_addc_co_u32 v19, s[0:1], v23, v21, s[0:1] // (op 1165) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 + + // (op 1165) ShiftL: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1165) value (VGPR Value: UInt64 x 1: v[18:19]) + // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[18:19], 1, v[18:19] // (op 1165) + // (op 1165) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1165): v20, v21 + + // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1165): v22, v23 + + // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) END + // (op 1074) Assign VGPR 128:U64(1166) BEGIN + // (op 1166) Assign dim(507) = 128:U64 + // (op 1166) Assign stride expression + // (op 1074) Assign VGPR 128:U64(1166) END + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) BEGIN + // (op 1167) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1167) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // (op 1167) Omitting copy to same register: s[8:9], s[8:9] + // (op 1167) reg expression + // (op 1167) Omitting copy to same register: s[10:11], s[10:11] + // (op 1167) reg expression + // (op 1167) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1167) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1167) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1167) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1167): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1167) + // (op 1167) Omitting copy to same register: s0, s0 + // (op 1167) reg expression +s_mov_b32 s36, s10 // (op 1167) reg expression +s_mov_b32 s37, s11 // (op 1167) reg expression +s_mov_b32 s38, s0 // (op 1167) reg expression +s_mov_b32 s39, 131072 // (op 1167) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1167): s0, s1 + + // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) END + // (op 1074) NOP(1158) BEGIN + // (op 1158) generate({}) + // (op 1158) end: generate({}) + // (op 1074) NOP(1158) END + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) BEGIN + // (op 1172) Assign dim(509) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1172) Assign stride expression + // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) END + // (op 1074) NOP(1159) BEGIN + // (op 1159) generate({}) + // (op 1159) end: generate({}) + // (op 1074) NOP(1159) END + // (op 1074) Assign VGPR 2:U64(1175) BEGIN + // (op 1175) Assign dim(511) = 2:U64 + // (op 1175) Assign stride expression + // (op 1074) Assign VGPR 2:U64(1175) END + // (op 1074) NOP(690) BEGIN + // (op 690) generate({}) + // (op 690) end: generate({}) + // (op 1074) NOP(690) END + // (op 1074) SetCoordinate(696) BEGIN + // (op 696) generate({}) + // (op 696) end: generate({}) + // (op 696) generate({1279}) + // (op 696) Scope(1279) BEGIN + // (op 1279) Lock Scope 1279 + // Lock Branch + // (op 1279) generate({1276}) + // (op 1279) NOP(1276) BEGIN + // (op 1276) generate({}) + // (op 1276) end: generate({}) + // (op 1279) NOP(1276) END + // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) BEGIN + // (op 1283) Assign dim(542) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 542: s**UNALLOCATED** + // (op 1283) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag542: SGPR Value: UInt32 x 1: (unallocated) + // (op 1283) Omitting copy to same register: v1, v1 + // (op 1283) reg expression + // (op 1283) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1283) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 +v_and_b32 v20, -32, v1 // (op 1283) +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1283) + // (op 1283) BEGIN: Tile[1] + // (op 1283) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v22 +v_sub_u32 v22, v1, v20 // (op 1283) + // (op 1283) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v20 + + // (op 1283) BEGIN: Flatten + // (op 1283) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1283) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1283) + // (op 1283) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1283): v22 + + // (op 1283) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1283) + // (op 1283) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v21 + + // (op 1283) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1283) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1283) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v22 + +// Allocated DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1283) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1283): v21 + + // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) END + // (op 1279) Assign VGPR 1024:U32(1284) BEGIN + // (op 1284) Assign dim(543) = 1024:U32 + // (op 1284) Assign stride expression + // (op 1279) Assign VGPR 1024:U32(1284) END + // (op 1279) NOP(1277) BEGIN + // (op 1277) generate({}) + // (op 1277) end: generate({}) + // (op 1279) NOP(1277) END + // (op 1279) Assign VGPR 2:U32(1288) BEGIN + // (op 1288) Assign dim(545) = 2:U32 + // (op 1288) Assign stride expression + // (op 1279) Assign VGPR 2:U32(1288) END + // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) BEGIN + // (op 1023) GEN: LoadTileDirect2LDS + // (op 1023) GEN: loadMacroTileDirect2LDS OP 1023 LDS 21 MacroTile 7 + // (op 1023) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1023) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1023) Omitting copy to same register: s[22:23], s[22:23] + // (op 1023) reg expression + // (op 1023) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1023) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1023) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1023) + // (op 1023) Omitting copy to same register: s[16:17], s[16:17] + // (op 1023) convert + // (op 1023) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1023) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1023) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1023) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 + + // (op 1023) Generate 2:U64 into nullptr + // (op 1023) Generate 1024:U32 into nullptr + // (op 1023) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1023) + // (op 1023) Generate Add(0:U32, {DataFlowTag542: s1:U32})U32 into nullptr + // (op 1023) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1023) Generate {DataFlowTag542: s1:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s1 // (op 1023) reg expression +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// VMEM: Expected complete at 268 (current 193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 272 (current 197) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 276 (current 201) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 280 (current 205) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 344 (current 269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 348 (current 273) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 352 (current 277) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1023) Omitting copy to same register: v[22:23], v[22:23] + // (op 1023) reg expression + // (op 1023) Omitting copy to same register: v20, v20 + // (op 1023) reg expression + // (op 1023) Add(v[22:23]:U64, v20:R)U64 + // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 + + // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1023) Omitting copy to same register: m0, m0 + // (op 1023) reg expression + // (op 1023) Add(m0:U32, 1024:U32)U32 + // (op 1023) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1023) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1023) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 356 (current 281) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 + + // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) END + // (op 1279) Deallocate{}(1895) BEGIN + // (op 1895) Deallocate 544 + // Deleting tag 544 + // (op 1895) Deallocate 543 + // Deleting tag 543 + // (op 1895) Deallocate 542 + // Freeing DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s1 + + // Deleting tag 542 + // (op 1895) Deallocate 545 + // Deleting tag 545 + // (op 1279) Deallocate{}(1895) END + // (op 1279) end: generate({1276}) + // (op 1279) Unlock Scope 1279 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 696) Scope(1279) END + // (op 696) end: generate({1279}) + // (op 1074) SetCoordinate(696) END + // (op 1074) SetCoordinate(699) BEGIN + // (op 699) generate({}) + // (op 699) end: generate({}) + // (op 699) generate({1227}) + // (op 699) Scope(1227) BEGIN + // (op 1227) Lock Scope 1227 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1227) generate({1224}) + // (op 1227) NOP(1224) BEGIN + // (op 1224) generate({}) + // (op 1224) end: generate({}) + // (op 1227) NOP(1224) END + // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) BEGIN + // (op 1231) Assign dim(526) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 526: s**UNALLOCATED** + // (op 1231) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag526: SGPR Value: UInt32 x 1: (unallocated) + // (op 1231) Omitting copy to same register: v1, v1 + // (op 1231) reg expression + // (op 1231) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1231) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 +v_and_b32 v20, -32, v1 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1231) BEGIN: Tile[1] + // (op 1231) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v22 +v_sub_u32 v22, v1, v20 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1231) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v20 + + // (op 1231) BEGIN: Flatten + // (op 1231) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1231) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1231) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1231): v22 + + // (op 1231) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1231) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v21 + + // (op 1231) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1231) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v22 + +// Allocated DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1231) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1231): v21 + + // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) END + // (op 1227) Assign VGPR 1024:U32(1232) BEGIN + // (op 1232) Assign dim(527) = 1024:U32 + // (op 1232) Assign stride expression + // (op 1227) Assign VGPR 1024:U32(1232) END + // (op 1227) NOP(1225) BEGIN + // (op 1225) generate({}) + // (op 1225) end: generate({}) + // (op 1227) NOP(1225) END + // (op 1227) Assign VGPR 2:U32(1236) BEGIN + // (op 1236) Assign dim(529) = 2:U32 + // (op 1236) Assign stride expression + // (op 1227) Assign VGPR 2:U32(1236) END + // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) BEGIN + // (op 1028) GEN: LoadTileDirect2LDS + // (op 1028) GEN: loadMacroTileDirect2LDS OP 1028 LDS 13 MacroTile 6 + // (op 1028) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1028) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1028) Omitting copy to same register: s[18:19], s[18:19] + // (op 1028) reg expression + // (op 1028) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1028) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1028) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1028) Omitting copy to same register: s[16:17], s[16:17] + // (op 1028) convert + // (op 1028) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1028) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1028) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 + + // (op 1028) Generate 2:U64 into nullptr + // (op 1028) Generate 1024:U32 into nullptr + // (op 1028) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 +v_mov_b64 v[22:23], v[14:15] // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1028) Generate Add(8192:U32, {DataFlowTag526: s1:U32})U32 into nullptr + // (op 1028) Omitting copy to same register: s1, s1 + // (op 1028) reg expression + // (op 1028) Add(8192:U32, {DataFlowTag526: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1028): s0 +s_add_u32 s0, 8192, s1 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 1028) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1028) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1028) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected stall of 50. CBNW: 4, Inc: 4 +// VMEM: Expected complete at 420 (current 345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 424 (current 349) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 428 (current 353) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 432 (current 357) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 +// VMEM: Expected complete at 496 (current 421) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 500 (current 425) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 504 (current 429) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1028) Omitting copy to same register: v[22:23], v[22:23] + // (op 1028) reg expression + // (op 1028) Omitting copy to same register: v20, v20 + // (op 1028) reg expression + // (op 1028) Add(v[22:23]:U64, v20:R)U64 + // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 +v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 + + // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1028) Omitting copy to same register: m0, m0 + // (op 1028) reg expression + // (op 1028) Add(m0:U32, 1024:U32)U32 + // (op 1028) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1028) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1028) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 508 (current 433) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1028): s0 + + // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) END + // (op 1227) Deallocate{}(1897) BEGIN + // (op 1897) Deallocate 529 + // Deleting tag 529 + // (op 1897) Deallocate 526 + // Freeing DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s1 + + // Deleting tag 526 + // (op 1897) Deallocate 528 + // Deleting tag 528 + // (op 1897) Deallocate 527 + // Deleting tag 527 + // (op 1227) Deallocate{}(1897) END + // (op 1227) end: generate({1224}) + // (op 1227) Unlock Scope 1227 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 699) Scope(1227) END + // (op 699) end: generate({1227}) + // (op 1074) SetCoordinate(699) END + // (op 1074) SetCoordinate(702) BEGIN + // (op 702) generate({}) + // (op 702) end: generate({}) + // (op 702) generate({1391}) + // (op 702) Scope(1391) BEGIN + // (op 1391) Lock Scope 1391 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1391) generate({1388}) + // (op 1391) NOP(1388) BEGIN + // (op 1388) generate({}) + // (op 1388) end: generate({}) + // (op 1391) NOP(1388) END + // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) BEGIN + // (op 1395) Assign dim(576) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 576: s**UNALLOCATED** + // (op 1395) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag576: SGPR Value: UInt32 x 1: (unallocated) + // (op 1395) Omitting copy to same register: v1, v1 + // (op 1395) reg expression + // (op 1395) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1395) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 +v_and_b32 v20, -32, v1 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1395) BEGIN: Tile[1] + // (op 1395) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v22 +v_sub_u32 v22, v1, v20 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1395) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v20 + + // (op 1395) BEGIN: Flatten + // (op 1395) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1395) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1395) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1395): v22 + + // (op 1395) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1395) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v21 + + // (op 1395) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1395) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v22 + +// Allocated DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1395) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1395): v21 + + // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) END + // (op 1391) Assign VGPR 1024:U32(1396) BEGIN + // (op 1396) Assign dim(577) = 1024:U32 + // (op 1396) Assign stride expression + // (op 1391) Assign VGPR 1024:U32(1396) END + // (op 1391) NOP(1389) BEGIN + // (op 1389) generate({}) + // (op 1389) end: generate({}) + // (op 1391) NOP(1389) END + // (op 1391) Assign VGPR 2:U32(1400) BEGIN + // (op 1400) Assign dim(579) = 2:U32 + // (op 1400) Assign stride expression + // (op 1391) Assign VGPR 2:U32(1400) END + // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) BEGIN + // (op 1033) GEN: LoadTileDirect2LDS + // (op 1033) GEN: loadMacroTileDirect2LDS OP 1033 LDS 360 MacroTile 358 + // (op 1033) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1033) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1033) Omitting copy to same register: s[22:23], s[22:23] + // (op 1033) reg expression + // (op 1033) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1033) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1033) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1033) Omitting copy to same register: s[16:17], s[16:17] + // (op 1033) convert + // (op 1033) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1033) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1033) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 + + // (op 1033) Generate 2:U64 into nullptr + // (op 1033) Generate 1024:U32 into nullptr + // (op 1033) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 16384 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1033) Generate Add(16384:U32, {DataFlowTag576: s1:U32})U32 into nullptr + // (op 1033) Omitting copy to same register: s1, s1 + // (op 1033) reg expression + // (op 1033) Add(16384:U32, {DataFlowTag576: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1033): s0 +s_add_u32 s0, 16384, s1 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1033) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1033) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1033) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 1033) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 128 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s17 +s_mov_b32 s17, 128 // (op 1033) call() +// 128 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 12, Inc: 4 +// VMEM: Expected complete at 572 (current 497) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 576 (current 501) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 580 (current 505) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 584 (current 509) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 16, Inc: 4 +// VMEM: Expected complete at 648 (current 573) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 652 (current 577) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 656 (current 581) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1033) Omitting copy to same register: v[22:23], v[22:23] + // (op 1033) reg expression + // (op 1033) Omitting copy to same register: v20, v20 + // (op 1033) reg expression + // (op 1033) Add(v[22:23]:U64, v20:R)U64 + // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 + + // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1033) Omitting copy to same register: m0, m0 + // (op 1033) reg expression + // (op 1033) Add(m0:U32, 1024:U32)U32 + // (op 1033) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1033) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1033) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1033) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 660 (current 585) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s17 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1033): s0 + + // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) END + // (op 1391) Deallocate{}(1899) BEGIN + // (op 1899) Deallocate 578 + // Deleting tag 578 + // (op 1899) Deallocate 579 + // Deleting tag 579 + // (op 1899) Deallocate 576 + // Freeing DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s1 + + // Deleting tag 576 + // (op 1899) Deallocate 577 + // Deleting tag 577 + // (op 1391) Deallocate{}(1899) END + // (op 1391) end: generate({1388}) + // (op 1391) Unlock Scope 1391 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 702) Scope(1391) END + // (op 702) end: generate({1391}) + // (op 1074) SetCoordinate(702) END + // (op 1074) SetCoordinate(705) BEGIN + // (op 705) generate({}) + // (op 705) end: generate({}) + // (op 705) generate({1352}) + // (op 705) Scope(1352) BEGIN + // (op 1352) Lock Scope 1352 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1352) generate({1349}) + // (op 1352) NOP(1349) BEGIN + // (op 1349) generate({}) + // (op 1349) end: generate({}) + // (op 1352) NOP(1349) END + // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) BEGIN + // (op 1356) Assign dim(564) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 564: s**UNALLOCATED** + // (op 1356) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag564: SGPR Value: UInt32 x 1: (unallocated) + // (op 1356) Omitting copy to same register: v1, v1 + // (op 1356) reg expression + // (op 1356) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1356) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 +v_and_b32 v20, -32, v1 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1356) BEGIN: Tile[1] + // (op 1356) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v22 +v_sub_u32 v22, v1, v20 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1356) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v20 + + // (op 1356) BEGIN: Flatten + // (op 1356) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1356) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1356) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1356): v22 + + // (op 1356) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1356) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v21 + + // (op 1356) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1356) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v22 + +// Allocated DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1356) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1356): v21 + + // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) END + // (op 1352) Assign VGPR 1024:U32(1357) BEGIN + // (op 1357) Assign dim(565) = 1024:U32 + // (op 1357) Assign stride expression + // (op 1352) Assign VGPR 1024:U32(1357) END + // (op 1352) NOP(1350) BEGIN + // (op 1350) generate({}) + // (op 1350) end: generate({}) + // (op 1352) NOP(1350) END + // (op 1352) Assign VGPR 2:U32(1361) BEGIN + // (op 1361) Assign dim(567) = 2:U32 + // (op 1361) Assign stride expression + // (op 1352) Assign VGPR 2:U32(1361) END + // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) BEGIN + // (op 1035) GEN: LoadTileDirect2LDS + // (op 1035) GEN: loadMacroTileDirect2LDS OP 1035 LDS 356 MacroTile 354 + // (op 1035) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1035) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1035) Omitting copy to same register: s[18:19], s[18:19] + // (op 1035) reg expression + // (op 1035) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1035) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1035) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1035) Omitting copy to same register: s[16:17], s[16:17] + // (op 1035) convert + // (op 1035) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1035) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1035) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 + + // (op 1035) Generate 2:U64 into nullptr + // (op 1035) Generate 1024:U32 into nullptr + // (op 1035) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 24576 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 +v_mov_b64 v[22:23], v[14:15] // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1035) Generate Add(24576:U32, {DataFlowTag564: s1:U32})U32 into nullptr + // (op 1035) Omitting copy to same register: s1, s1 + // (op 1035) reg expression + // (op 1035) Add(24576:U32, {DataFlowTag564: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1035): s0 +s_add_u32 s0, 24576, s1 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1035) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1035) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1035) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // (op 1035) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 128 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s17 +s_mov_b32 s17, 128 // (op 1035) call() +// 128 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 20, Inc: 4 +// VMEM: Expected complete at 724 (current 649) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 728 (current 653) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 732 (current 657) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 736 (current 661) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 24, Inc: 4 +// VMEM: Expected complete at 800 (current 725) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 804 (current 729) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 808 (current 733) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1035) Omitting copy to same register: v[22:23], v[22:23] + // (op 1035) reg expression + // (op 1035) Omitting copy to same register: v20, v20 + // (op 1035) reg expression + // (op 1035) Add(v[22:23]:U64, v20:R)U64 + // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 + + // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1035) Omitting copy to same register: m0, m0 + // (op 1035) reg expression + // (op 1035) Add(m0:U32, 1024:U32)U32 + // (op 1035) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1035) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1035) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1035) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 812 (current 737) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s17 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1035): s0 + + // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) END + // (op 1352) Deallocate{}(1901) BEGIN + // (op 1901) Deallocate 565 + // Deleting tag 565 + // (op 1901) Deallocate 567 + // Deleting tag 567 + // (op 1901) Deallocate 564 + // Freeing DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s1 + + // Deleting tag 564 + // (op 1901) Deallocate 566 + // Deleting tag 566 + // (op 1352) Deallocate{}(1901) END + // (op 1352) end: generate({1349}) + // (op 1352) Unlock Scope 1352 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 705) Scope(1352) END + // (op 705) end: generate({1352}) + // (op 1074) SetCoordinate(705) END + // (op 1074) SetCoordinate(708) BEGIN + // (op 708) generate({}) + // (op 708) end: generate({}) + // (op 708) generate({1469}) + // (op 708) Scope(1469) BEGIN + // (op 1469) Lock Scope 1469 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1469) generate({1466}) + // (op 1469) NOP(1466) BEGIN + // (op 1466) generate({}) + // (op 1466) end: generate({}) + // (op 1469) NOP(1466) END + // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) BEGIN + // (op 1473) Assign dim(600) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 600: s**UNALLOCATED** + // (op 1473) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag600: SGPR Value: UInt32 x 1: (unallocated) + // (op 1473) Omitting copy to same register: v1, v1 + // (op 1473) reg expression + // (op 1473) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1473) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 +v_and_b32 v20, -32, v1 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1473) BEGIN: Tile[1] + // (op 1473) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v22 +v_sub_u32 v22, v1, v20 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1473) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v20 + + // (op 1473) BEGIN: Flatten + // (op 1473) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1473) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1473) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1473): v22 + + // (op 1473) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1473) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v21 + + // (op 1473) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1473) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v22 + +// Allocated DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1473) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1473): v21 + + // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) END + // (op 1469) Assign VGPR 1024:U32(1474) BEGIN + // (op 1474) Assign dim(601) = 1024:U32 + // (op 1474) Assign stride expression + // (op 1469) Assign VGPR 1024:U32(1474) END + // (op 1469) NOP(1467) BEGIN + // (op 1467) generate({}) + // (op 1467) end: generate({}) + // (op 1469) NOP(1467) END + // (op 1469) Assign VGPR 2:U32(1478) BEGIN + // (op 1478) Assign dim(603) = 2:U32 + // (op 1478) Assign stride expression + // (op 1469) Assign VGPR 2:U32(1478) END + // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) BEGIN + // (op 1037) GEN: LoadTileDirect2LDS + // (op 1037) GEN: loadMacroTileDirect2LDS OP 1037 LDS 400 MacroTile 398 + // (op 1037) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1037) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1037) Omitting copy to same register: s[22:23], s[22:23] + // (op 1037) reg expression + // (op 1037) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1037) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1037) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1037) Omitting copy to same register: s[16:17], s[16:17] + // (op 1037) convert + // (op 1037) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1037) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1037) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 + + // (op 1037) Generate 2:U64 into nullptr + // (op 1037) Generate 1024:U32 into nullptr + // (op 1037) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 32768 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1037) Generate Add(32768:U32, {DataFlowTag600: s1:U32})U32 into nullptr + // (op 1037) Omitting copy to same register: s1, s1 + // (op 1037) reg expression + // (op 1037) Add(32768:U32, {DataFlowTag600: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1037): s0 +s_add_u32 s0, 32768, s1 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1037) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1037) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1037) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // (op 1037) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 256 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s17 +s_mov_b32 s17, 256 // (op 1037) call() +// 256 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 28, Inc: 4 +// VMEM: Expected complete at 876 (current 801) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 880 (current 805) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 884 (current 809) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 888 (current 813) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 952 (current 877) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 956 (current 881) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 960 (current 885) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1037) Omitting copy to same register: v[22:23], v[22:23] + // (op 1037) reg expression + // (op 1037) Omitting copy to same register: v20, v20 + // (op 1037) reg expression + // (op 1037) Add(v[22:23]:U64, v20:R)U64 + // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 + + // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1037) Omitting copy to same register: m0, m0 + // (op 1037) reg expression + // (op 1037) Add(m0:U32, 1024:U32)U32 + // (op 1037) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1037) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1037) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1037) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected complete at 964 (current 889) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s17 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1037): s0 + + // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) END + // (op 1469) Deallocate{}(1903) BEGIN + // (op 1903) Deallocate 600 + // Freeing DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s1 + + // Deleting tag 600 + // (op 1903) Deallocate 603 + // Deleting tag 603 + // (op 1903) Deallocate 601 + // Deleting tag 601 + // (op 1903) Deallocate 602 + // Deleting tag 602 + // (op 1469) Deallocate{}(1903) END + // (op 1469) end: generate({1466}) + // (op 1469) Unlock Scope 1469 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 708) Scope(1469) END + // (op 708) end: generate({1469}) + // (op 1074) SetCoordinate(708) END + // (op 1074) SetCoordinate(711) BEGIN + // (op 711) generate({}) + // (op 711) end: generate({}) + // (op 711) generate({1430}) + // (op 711) Scope(1430) BEGIN + // (op 1430) Lock Scope 1430 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1430) generate({1427}) + // (op 1430) NOP(1427) BEGIN + // (op 1427) generate({}) + // (op 1427) end: generate({}) + // (op 1430) NOP(1427) END + // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) BEGIN + // (op 1434) Assign dim(588) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 588: s**UNALLOCATED** + // (op 1434) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag588: SGPR Value: UInt32 x 1: (unallocated) + // (op 1434) Omitting copy to same register: v1, v1 + // (op 1434) reg expression + // (op 1434) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1434) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 +v_and_b32 v20, -32, v1 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1434) BEGIN: Tile[1] + // (op 1434) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v22 +v_sub_u32 v22, v1, v20 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1434) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v20 + + // (op 1434) BEGIN: Flatten + // (op 1434) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1434) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1434) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1434): v22 + + // (op 1434) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1434) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v21 + + // (op 1434) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1434) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v22 + +// Allocated DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1434) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1434): v21 + + // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) END + // (op 1430) Assign VGPR 1024:U32(1435) BEGIN + // (op 1435) Assign dim(589) = 1024:U32 + // (op 1435) Assign stride expression + // (op 1430) Assign VGPR 1024:U32(1435) END + // (op 1430) NOP(1428) BEGIN + // (op 1428) generate({}) + // (op 1428) end: generate({}) + // (op 1430) NOP(1428) END + // (op 1430) Assign VGPR 2:U32(1439) BEGIN + // (op 1439) Assign dim(591) = 2:U32 + // (op 1439) Assign stride expression + // (op 1430) Assign VGPR 2:U32(1439) END + // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) BEGIN + // (op 1039) GEN: LoadTileDirect2LDS + // (op 1039) GEN: loadMacroTileDirect2LDS OP 1039 LDS 396 MacroTile 394 + // (op 1039) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1039) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1039) Omitting copy to same register: s[18:19], s[18:19] + // (op 1039) reg expression + // (op 1039) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1039) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1039) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1039) Omitting copy to same register: s[16:17], s[16:17] + // (op 1039) convert + // (op 1039) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1039) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1039) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 + + // (op 1039) Generate 2:U64 into nullptr + // (op 1039) Generate 1024:U32 into nullptr + // (op 1039) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 40960 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 +v_mov_b64 v[22:23], v[14:15] // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1039) Generate Add(40960:U32, {DataFlowTag588: s1:U32})U32 into nullptr + // (op 1039) Omitting copy to same register: s1, s1 + // (op 1039) reg expression + // (op 1039) Add(40960:U32, {DataFlowTag588: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1039): s0 +s_add_u32 s0, 40960, s1 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1039) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1039) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1039) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // (op 1039) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 256 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s17 +s_mov_b32 s17, 256 // (op 1039) call() +// 256 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 1028 (current 953) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1032 (current 957) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1036 (current 961) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1040 (current 965) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 1104 (current 1029) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1108 (current 1033) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1112 (current 1037) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1039) Omitting copy to same register: v[22:23], v[22:23] + // (op 1039) reg expression + // (op 1039) Omitting copy to same register: v20, v20 + // (op 1039) reg expression + // (op 1039) Add(v[22:23]:U64, v20:R)U64 + // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 + + // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1039) Omitting copy to same register: m0, m0 + // (op 1039) reg expression + // (op 1039) Add(m0:U32, 1024:U32)U32 + // (op 1039) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1039) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1039) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[32:35], s17 offen offset: 0 lds // (op 1039) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected complete at 1116 (current 1041) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s17 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1039): s0 + + // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) END + // (op 1430) Deallocate{}(1905) BEGIN + // (op 1905) Deallocate 588 + // Freeing DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s1 + + // Deleting tag 588 + // (op 1905) Deallocate 591 + // Deleting tag 591 + // (op 1905) Deallocate 589 + // Deleting tag 589 + // (op 1905) Deallocate 590 + // Deleting tag 590 + // (op 1430) Deallocate{}(1905) END + // (op 1430) end: generate({1427}) + // (op 1430) Unlock Scope 1430 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 711) Scope(1430) END + // (op 711) end: generate({1430}) + // (op 1074) SetCoordinate(711) END + // (op 1074) SetCoordinate(714) BEGIN + // (op 714) generate({}) + // (op 714) end: generate({}) + // (op 714) generate({1547}) + // (op 714) Scope(1547) BEGIN + // (op 1547) Lock Scope 1547 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1547) generate({1544}) + // (op 1547) NOP(1544) BEGIN + // (op 1544) generate({}) + // (op 1544) end: generate({}) + // (op 1547) NOP(1544) END + // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) BEGIN + // (op 1551) Assign dim(624) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 624: s**UNALLOCATED** + // (op 1551) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag624: SGPR Value: UInt32 x 1: (unallocated) + // (op 1551) Omitting copy to same register: v1, v1 + // (op 1551) reg expression + // (op 1551) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1551) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 +v_and_b32 v20, -32, v1 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 +v_lshrrev_b32 v21, 5, v1 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1551) BEGIN: Tile[1] + // (op 1551) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v22 +v_sub_u32 v22, v1, v20 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1551) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v20 + + // (op 1551) BEGIN: Flatten + // (op 1551) {Flatten: ShiftL({Tile[1]: v22:U32}, 1:U32)U32} + // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1551) value (Tile[1]: VGPR Value: UInt32 x 1: v22) + // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 +v_lshlrev_b32 v20, 1, v22 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1551) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1551): v22 + + // (op 1551) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v22 +v_lshl_add_u32 v22, v21, 6, v20 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1551) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v20 + + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v21 + + // (op 1551) ShiftL({Flatten: v22:U32}, 1:U32)U32 + // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1551) value (Flatten: VGPR Value: UInt32 x 1: v22) + // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 +v_lshlrev_b32 v21, 1, v22 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v22 + +// Allocated DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s1 +s_nop 0 +v_readfirstlane_b32 s1, v21 // (op 1551) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1551): v21 + + // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) END + // (op 1547) Assign VGPR 1024:U32(1552) BEGIN + // (op 1552) Assign dim(625) = 1024:U32 + // (op 1552) Assign stride expression + // (op 1547) Assign VGPR 1024:U32(1552) END + // (op 1547) NOP(1545) BEGIN + // (op 1545) generate({}) + // (op 1545) end: generate({}) + // (op 1547) NOP(1545) END + // (op 1547) Assign VGPR 2:U32(1556) BEGIN + // (op 1556) Assign dim(627) = 2:U32 + // (op 1556) Assign stride expression + // (op 1547) Assign VGPR 2:U32(1556) END + // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) BEGIN + // (op 1041) GEN: LoadTileDirect2LDS + // (op 1041) GEN: loadMacroTileDirect2LDS OP 1041 LDS 440 MacroTile 438 + // (op 1041) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1041) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) + // (op 1041) Omitting copy to same register: s[22:23], s[22:23] + // (op 1041) reg expression + // (op 1041) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1041) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1041) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1041) Omitting copy to same register: s[16:17], s[16:17] + // (op 1041) convert + // (op 1041) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1041) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1041) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 +v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 + + // (op 1041) Generate 2:U64 into nullptr + // (op 1041) Generate 1024:U32 into nullptr + // (op 1041) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 49152 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 +v_mov_b64 v[22:23], v[16:17] // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1041) Generate Add(49152:U32, {DataFlowTag624: s1:U32})U32 into nullptr + // (op 1041) Omitting copy to same register: s1, s1 + // (op 1041) reg expression + // (op 1041) Add(49152:U32, {DataFlowTag624: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1041): s0 +s_add_u32 s0, 49152, s1 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1041) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1041) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1041) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // (op 1041) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 384 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s17 +s_mov_b32 s17, 384 // (op 1041) call() +// 384 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 44, Inc: 4 +// VMEM: Expected complete at 1180 (current 1105) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1184 (current 1109) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1188 (current 1113) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1192 (current 1117) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 48, Inc: 4 +// VMEM: Expected complete at 1256 (current 1181) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1260 (current 1185) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1264 (current 1189) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] + // (op 1041) Omitting copy to same register: v[22:23], v[22:23] + // (op 1041) reg expression + // (op 1041) Omitting copy to same register: v20, v20 + // (op 1041) reg expression + // (op 1041) Add(v[22:23]:U64, v20:R)U64 + // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = + // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) + // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) +// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 +v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 + + // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1041) Omitting copy to same register: m0, m0 + // (op 1041) reg expression + // (op 1041) Add(m0:U32, 1024:U32)U32 + // (op 1041) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1041) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1041) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v22, s[36:39], s17 offen offset: 0 lds // (op 1041) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected complete at 1268 (current 1193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s17 + + // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 + + // Freeing : 1 SGPR (Value: UInt32) (op 1041): s0 + + // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) END + // (op 1547) Deallocate{}(1907) BEGIN + // (op 1907) Deallocate 626 + // Deleting tag 626 + // (op 1907) Deallocate 624 + // Freeing DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s1 + + // Deleting tag 624 + // (op 1907) Deallocate 627 + // Deleting tag 627 + // (op 1907) Deallocate 625 + // Deleting tag 625 + // (op 1547) Deallocate{}(1907) END + // (op 1547) end: generate({1544}) + // (op 1547) Unlock Scope 1547 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 714) Scope(1547) END + // (op 714) end: generate({1547}) + // (op 1074) SetCoordinate(714) END + // (op 1074) Deallocate{}(1871) BEGIN + // (op 1871) Deallocate 504 + // Deleting tag 504 + // (op 1871) Deallocate 503 + // Deleting tag 503 + // (op 1871) Deallocate 502 + // Freeing DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 + + // Deleting tag 502 + // (op 1871) Deallocate 505 + // Deleting tag 505 + // (op 1871) Deallocate 501 + // Deleting tag 501 + // (op 1074) Deallocate{}(1871) END + // (op 1074) SetCoordinate(717) BEGIN + // (op 717) generate({}) + // (op 717) end: generate({}) + // (op 717) generate({1508}) + // (op 717) Scope(1508) BEGIN + // (op 1508) Lock Scope 1508 + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1508) generate({1505}) + // (op 1508) NOP(1505) BEGIN + // (op 1505) generate({}) + // (op 1505) end: generate({}) + // (op 1508) NOP(1505) END + // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) BEGIN + // (op 1512) Assign dim(612) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 612: s**UNALLOCATED** + // (op 1512) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag612: SGPR Value: UInt32 x 1: (unallocated) + // (op 1512) Omitting copy to same register: v1, v1 + // (op 1512) reg expression + // (op 1512) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1512) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 +v_and_b32 v17, -32, v1 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 +v_lshrrev_b32 v16, 5, v1 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1512) BEGIN: Tile[1] + // (op 1512) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v17:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v20 +v_sub_u32 v20, v1, v17 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1512) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v17 + + // (op 1512) BEGIN: Flatten + // (op 1512) {Flatten: ShiftL({Tile[1]: v20:U32}, 1:U32)U32} + // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1512) value (Tile[1]: VGPR Value: UInt32 x 1: v20) + // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 +v_lshlrev_b32 v17, 1, v20 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1512) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1512): v20 + + // (op 1512) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v20 +v_lshl_add_u32 v20, v16, 6, v17 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1512) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v17 + + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v16 + + // (op 1512) ShiftL({Flatten: v20:U32}, 1:U32)U32 + // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1512) value (Flatten: VGPR Value: UInt32 x 1: v20) + // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 +v_lshlrev_b32 v17, 1, v20 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v20 + +// Allocated DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s1 +s_nop 0 +v_readfirstlane_b32 s1, v17 // (op 1512) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1512): v17 + + // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) END + // (op 1508) Assign VGPR 1024:U32(1513) BEGIN + // (op 1513) Assign dim(613) = 1024:U32 + // (op 1513) Assign stride expression + // (op 1508) Assign VGPR 1024:U32(1513) END + // (op 1508) NOP(1506) BEGIN + // (op 1506) generate({}) + // (op 1506) end: generate({}) + // (op 1508) NOP(1506) END + // (op 1508) Assign VGPR 2:U32(1517) BEGIN + // (op 1517) Assign dim(615) = 2:U32 + // (op 1517) Assign stride expression + // (op 1508) Assign VGPR 2:U32(1517) END + // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) BEGIN + // (op 1043) GEN: LoadTileDirect2LDS + // (op 1043) GEN: loadMacroTileDirect2LDS OP 1043 LDS 436 MacroTile 434 + // (op 1043) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1043) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) + // (op 1043) Omitting copy to same register: s[18:19], s[18:19] + // (op 1043) reg expression + // (op 1043) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1043) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1043) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1043) Omitting copy to same register: s[16:17], s[16:17] + // (op 1043) convert + // (op 1043) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 1043) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1043) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 + + // (op 1043) Generate 2:U64 into nullptr + // (op 1043) Generate 1024:U32 into nullptr + // (op 1043) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 57344 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 +v_mov_b64 v[20:21], v[14:15] // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1043) Generate Add(57344:U32, {DataFlowTag612: s1:U32})U32 into nullptr + // (op 1043) Omitting copy to same register: s1, s1 + // (op 1043) reg expression + // (op 1043) Add(57344:U32, {DataFlowTag612: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1043): s0 +s_add_u32 s0, 57344, s1 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1043) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1043) Generate s0:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 1043) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // (op 1043) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 384 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s17 +s_mov_b32 s17, 384 // (op 1043) call() +// 384 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// VMEM: Expected stall of 49. CBNW: 52, Inc: 4 +// VMEM: Expected complete at 1332 (current 1257) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1336 (current 1261) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1340 (current 1265) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1344 (current 1269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 56, Inc: 4 +// VMEM: Expected complete at 1408 (current 1333) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1412 (current 1337) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1416 (current 1341) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 1043) Omitting copy to same register: v[20:21], v[20:21] + // (op 1043) reg expression + // (op 1043) Omitting copy to same register: v16, v16 + // (op 1043) reg expression + // (op 1043) Add(v[20:21]:U64, v16:R)U64 + // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 +v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 + + // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1043) Omitting copy to same register: m0, m0 + // (op 1043) reg expression + // (op 1043) Add(m0:U32, 1024:U32)U32 + // (op 1043) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1043) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 1043) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v20, s[32:35], s17 offen offset: 0 lds // (op 1043) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 1420 (current 1345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s17 + + // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 + + // Freeing : 1 SGPR (Value: UInt32) (op 1043): s0 + + // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) END + // (op 1508) Deallocate{}(1909) BEGIN + // (op 1909) Deallocate 613 + // Deleting tag 613 + // (op 1909) Deallocate 614 + // Deleting tag 614 + // (op 1909) Deallocate 612 + // Freeing DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s1 + + // Deleting tag 612 + // (op 1909) Deallocate 615 + // Deleting tag 615 + // (op 1508) Deallocate{}(1909) END + // (op 1508) end: generate({1505}) + // (op 1508) Unlock Scope 1508 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // (op 717) Scope(1508) END + // (op 717) end: generate({1508}) + // (op 1074) SetCoordinate(717) END + // (op 1074) Deallocate{}(1873) BEGIN + // (op 1873) Deallocate 484 + // Deleting tag 484 + // (op 1873) Deallocate 483 + // Freeing DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 + + // Deleting tag 483 + // (op 1873) Deallocate 482 + // Deleting tag 482 + // (op 1873) Deallocate 486 + // Deleting tag 486 + // (op 1873) Deallocate 485 + // Deleting tag 485 + // (op 1074) Deallocate{}(1873) END + // (op 1074) NOP(1025) BEGIN + // (op 1025) generate({}) + // (op 1025) end: generate({}) + // (op 1074) NOP(1025) END + // (op 1074) NOP(1030) BEGIN + // (op 1030) generate({}) + // (op 1030) end: generate({}) + // (op 1074) NOP(1030) END + // (op 1074) Barrier(693) BEGIN +s_waitcnt vmcnt(48) +s_barrier // (op 693) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 15 and the queue size is 64, so a waitcnt of 48 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 1074) Barrier(693) END + // (op 1074) SetCoordinate(757) BEGIN + // (op 757) generate({}) + // (op 757) end: generate({}) + // (op 757) generate({758}) + // (op 757) LoadLDSTile{Value: Halfx2}(758) BEGIN + // (op 758) GEN: loadMacroTileWAVELDS OP 758 LDS 21 WaveTile 145 + // (op 758) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 758) Generate 2:U32 into nullptr + // tag 19: v**UNALLOCATED** + // (op 758) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 758) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 758) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 758): v16, v17 +ds_read_b64 v[16:17], v4 // (op 758) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// DSMEM: Expected complete at 1368 (current 1348) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 757) LoadLDSTile{Value: Halfx2}(758) END + // (op 757) end: generate({758}) + // (op 1074) SetCoordinate(757) END + // (op 1074) SetCoordinate(760) BEGIN + // (op 760) generate({}) + // (op 760) end: generate({}) + // (op 760) generate({761}) + // (op 760) LoadLDSTile{Value: Halfx2}(761) BEGIN + // (op 761) GEN: loadMacroTileWAVELDS OP 761 LDS 21 WaveTile 145 + // (op 761) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 761) Generate 2:U32 into nullptr + // tag 255: v**UNALLOCATED** + // (op 761) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 761) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 761) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 761): v14, v15 +ds_read_b64 v[14:15], v4 offset:16 // (op 761) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1369 (current 1349) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 760) LoadLDSTile{Value: Halfx2}(761) END + // (op 760) end: generate({761}) + // (op 1074) SetCoordinate(760) END + // (op 1074) SetCoordinate(763) BEGIN + // (op 763) generate({}) + // (op 763) end: generate({}) + // (op 763) generate({764}) + // (op 763) LoadLDSTile{Value: Halfx2}(764) BEGIN + // (op 764) GEN: loadMacroTileWAVELDS OP 764 LDS 21 WaveTile 145 + // (op 764) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 764) Generate 2:U32 into nullptr + // tag 259: v**UNALLOCATED** + // (op 764) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 764) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 764) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 +ds_read_b64 v[20:21], v4 offset:32 // (op 764) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1370 (current 1350) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 763) LoadLDSTile{Value: Halfx2}(764) END + // (op 763) end: generate({764}) + // (op 1074) SetCoordinate(763) END + // (op 1074) SetCoordinate(766) BEGIN + // (op 766) generate({}) + // (op 766) end: generate({}) + // (op 766) generate({767}) + // (op 766) LoadLDSTile{Value: Halfx2}(767) BEGIN + // (op 767) GEN: loadMacroTileWAVELDS OP 767 LDS 21 WaveTile 145 + // (op 767) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 767) Generate 2:U32 into nullptr + // tag 263: v**UNALLOCATED** + // (op 767) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 767) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 767) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 +ds_read_b64 v[22:23], v4 offset:48 // (op 767) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1371 (current 1351) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 766) LoadLDSTile{Value: Halfx2}(767) END + // (op 766) end: generate({767}) + // (op 1074) SetCoordinate(766) END + // (op 1074) SetCoordinate(769) BEGIN + // (op 769) generate({}) + // (op 769) end: generate({}) + // (op 769) generate({770}) + // (op 769) LoadLDSTile{Value: Halfx2}(770) BEGIN + // (op 770) GEN: loadMacroTileWAVELDS OP 770 LDS 21 WaveTile 145 + // (op 770) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 770) Generate 2:U32 into nullptr + // tag 267: v**UNALLOCATED** + // (op 770) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 770) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 770) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 +ds_read_b64 v[24:25], v4 offset:64 // (op 770) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected stall of 17. CBNW: 0, Inc: 4 +// DSMEM: Expected complete at 1389 (current 1369) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 769) LoadLDSTile{Value: Halfx2}(770) END + // (op 769) end: generate({770}) + // (op 1074) SetCoordinate(769) END + // (op 1074) SetCoordinate(772) BEGIN + // (op 772) generate({}) + // (op 772) end: generate({}) + // (op 772) generate({773}) + // (op 772) LoadLDSTile{Value: Halfx2}(773) BEGIN + // (op 773) GEN: loadMacroTileWAVELDS OP 773 LDS 21 WaveTile 145 + // (op 773) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 773) Generate 2:U32 into nullptr + // tag 271: v**UNALLOCATED** + // (op 773) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 773) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 773) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 +ds_read_b64 v[26:27], v4 offset:80 // (op 773) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1390 (current 1370) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 772) LoadLDSTile{Value: Halfx2}(773) END + // (op 772) end: generate({773}) + // (op 1074) SetCoordinate(772) END + // (op 1074) SetCoordinate(775) BEGIN + // (op 775) generate({}) + // (op 775) end: generate({}) + // (op 775) generate({776}) + // (op 775) LoadLDSTile{Value: Halfx2}(776) BEGIN + // (op 776) GEN: loadMacroTileWAVELDS OP 776 LDS 21 WaveTile 145 + // (op 776) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 776) Generate 2:U32 into nullptr + // tag 275: v**UNALLOCATED** + // (op 776) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 776) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 776) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 +ds_read_b64 v[28:29], v4 offset:96 // (op 776) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1391 (current 1371) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 775) LoadLDSTile{Value: Halfx2}(776) END + // (op 775) end: generate({776}) + // (op 1074) SetCoordinate(775) END + // (op 1074) SetCoordinate(778) BEGIN + // (op 778) generate({}) + // (op 778) end: generate({}) + // (op 778) generate({779}) + // (op 778) LoadLDSTile{Value: Halfx2}(779) BEGIN + // (op 779) GEN: loadMacroTileWAVELDS OP 779 LDS 21 WaveTile 145 + // (op 779) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 779) Generate 2:U32 into nullptr + // tag 279: v**UNALLOCATED** + // (op 779) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 779) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 779) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 +ds_read_b64 v[30:31], v4 offset:112 // (op 779) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 1392 (current 1372) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 778) LoadLDSTile{Value: Halfx2}(779) END + // (op 778) end: generate({779}) + // (op 1074) SetCoordinate(778) END + // (op 1074) SetCoordinate(733) BEGIN + // (op 733) generate({}) + // (op 733) end: generate({}) + // (op 733) generate({734}) + // (op 733) LoadLDSTile{Value: Halfx2}(734) BEGIN + // (op 734) GEN: loadMacroTileWAVELDS OP 734 LDS 13 WaveTile 85 + // (op 734) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 734) Generate 2:U32 into nullptr + // tag 11: v**UNALLOCATED** + // (op 734) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 734) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 734) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 +ds_read_b64 v[32:33], v0 offset:8192 // (op 734) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected stall of 17. CBNW: 4, Inc: 4 +// DSMEM: Expected complete at 1410 (current 1390) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 733) LoadLDSTile{Value: Halfx2}(734) END + // (op 733) end: generate({734}) + // (op 1074) SetCoordinate(733) END + // (op 1074) SetCoordinate(736) BEGIN + // (op 736) generate({}) + // (op 736) end: generate({}) + // (op 736) generate({737}) + // (op 736) LoadLDSTile{Value: Halfx2}(737) BEGIN + // (op 737) GEN: loadMacroTileWAVELDS OP 737 LDS 13 WaveTile 85 + // (op 737) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 737) Generate 2:U32 into nullptr + // tag 253: v**UNALLOCATED** + // (op 737) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 737) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 737) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 +ds_read_b64 v[34:35], v0 offset:8208 // (op 737) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1411 (current 1391) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 736) LoadLDSTile{Value: Halfx2}(737) END + // (op 736) end: generate({737}) + // (op 1074) SetCoordinate(736) END + // (op 1074) SetCoordinate(739) BEGIN + // (op 739) generate({}) + // (op 739) end: generate({}) + // (op 739) generate({740}) + // (op 739) LoadLDSTile{Value: Halfx2}(740) BEGIN + // (op 740) GEN: loadMacroTileWAVELDS OP 740 LDS 13 WaveTile 85 + // (op 740) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 740) Generate 2:U32 into nullptr + // tag 257: v**UNALLOCATED** + // (op 740) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 740) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 740) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 +ds_read_b64 v[36:37], v0 offset:8224 // (op 740) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1412 (current 1392) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 739) LoadLDSTile{Value: Halfx2}(740) END + // (op 739) end: generate({740}) + // (op 1074) SetCoordinate(739) END + // (op 1074) SetCoordinate(742) BEGIN + // (op 742) generate({}) + // (op 742) end: generate({}) + // (op 742) generate({743}) + // (op 742) LoadLDSTile{Value: Halfx2}(743) BEGIN + // (op 743) GEN: loadMacroTileWAVELDS OP 743 LDS 13 WaveTile 85 + // (op 743) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 743) Generate 2:U32 into nullptr + // tag 261: v**UNALLOCATED** + // (op 743) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 743) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 743) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 +ds_read_b64 v[38:39], v0 offset:8240 // (op 743) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1413 (current 1393) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 742) LoadLDSTile{Value: Halfx2}(743) END + // (op 742) end: generate({743}) + // (op 1074) SetCoordinate(742) END + // (op 1074) SetCoordinate(745) BEGIN + // (op 745) generate({}) + // (op 745) end: generate({}) + // (op 745) generate({746}) + // (op 745) LoadLDSTile{Value: Halfx2}(746) BEGIN + // (op 746) GEN: loadMacroTileWAVELDS OP 746 LDS 13 WaveTile 85 + // (op 746) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 746) Generate 2:U32 into nullptr + // tag 265: v**UNALLOCATED** + // (op 746) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 746) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 746) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 +ds_read_b64 v[40:41], v0 offset:8256 // (op 746) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected stall of 17. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 1431 (current 1411) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 745) LoadLDSTile{Value: Halfx2}(746) END + // (op 745) end: generate({746}) + // (op 1074) SetCoordinate(745) END + // (op 1074) SetCoordinate(748) BEGIN + // (op 748) generate({}) + // (op 748) end: generate({}) + // (op 748) generate({749}) + // (op 748) LoadLDSTile{Value: Halfx2}(749) BEGIN + // (op 749) GEN: loadMacroTileWAVELDS OP 749 LDS 13 WaveTile 85 + // (op 749) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 749) Generate 2:U32 into nullptr + // tag 269: v**UNALLOCATED** + // (op 749) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 749) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 749) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 +ds_read_b64 v[42:43], v0 offset:8272 // (op 749) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1432 (current 1412) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 748) LoadLDSTile{Value: Halfx2}(749) END + // (op 748) end: generate({749}) + // (op 1074) SetCoordinate(748) END + // (op 1074) SetCoordinate(751) BEGIN + // (op 751) generate({}) + // (op 751) end: generate({}) + // (op 751) generate({752}) + // (op 751) LoadLDSTile{Value: Halfx2}(752) BEGIN + // (op 752) GEN: loadMacroTileWAVELDS OP 752 LDS 13 WaveTile 85 + // (op 752) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 752) Generate 2:U32 into nullptr + // tag 273: v**UNALLOCATED** + // (op 752) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 752) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 752) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 +ds_read_b64 v[44:45], v0 offset:8288 // (op 752) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1433 (current 1413) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 751) LoadLDSTile{Value: Halfx2}(752) END + // (op 751) end: generate({752}) + // (op 1074) SetCoordinate(751) END + // (op 1074) SetCoordinate(754) BEGIN + // (op 754) generate({}) + // (op 754) end: generate({}) + // (op 754) generate({755}) + // (op 754) LoadLDSTile{Value: Halfx2}(755) BEGIN + // (op 755) GEN: loadMacroTileWAVELDS OP 755 LDS 13 WaveTile 85 + // (op 755) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 755) Generate 2:U32 into nullptr + // tag 277: v**UNALLOCATED** + // (op 755) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 755) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 755) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 +ds_read_b64 v[46:47], v0 offset:8304 // (op 755) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 1434 (current 1414) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 754) LoadLDSTile{Value: Halfx2}(755) END + // (op 754) end: generate({755}) + // (op 1074) SetCoordinate(754) END + // (op 1074) NOP(694) BEGIN + // (op 694) generate({}) + // (op 694) end: generate({}) + // (op 1074) NOP(694) END + // (op 1074) NOP(1199) BEGIN + // (op 1199) generate({}) + // (op 1199) end: generate({}) + // (op 1074) NOP(1199) END + // (op 1074) NOP(1196) BEGIN + // (op 1196) generate({}) + // (op 1196) end: generate({}) + // (op 1074) NOP(1196) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) BEGIN + // (op 1203) Assign dim(518) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 518: s**UNALLOCATED** + // (op 1203) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag518: SGPR Value: UInt32 x 1: (unallocated) + // (op 1203) Omitting copy to same register: v1, v1 + // (op 1203) reg expression + // (op 1203) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1203) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 +v_and_b32 v48, -32, v1 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1203) BEGIN: Tile[1] + // (op 1203) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v50 +v_sub_u32 v50, v1, v48 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1203) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v48 + + // (op 1203) BEGIN: Flatten + // (op 1203) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1203) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1203) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1203): v50 + + // (op 1203) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1203) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v49 + + // (op 1203) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1203) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v50 + +// Allocated DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s1 +s_nop 0 +v_readfirstlane_b32 s1, v49 // (op 1203) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1203): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) END + // (op 1074) Assign VGPR 1024:U32(1204) BEGIN + // (op 1204) Assign dim(519) = 1024:U32 + // (op 1204) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1204) END + // (op 1074) NOP(1197) BEGIN + // (op 1197) generate({}) + // (op 1197) end: generate({}) + // (op 1074) NOP(1197) END + // (op 1074) Assign VGPR 2:U32(1208) BEGIN + // (op 1208) Assign dim(521) = 2:U32 + // (op 1208) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1208) END + // (op 1074) NOP(1250) BEGIN + // (op 1250) generate({}) + // (op 1250) end: generate({}) + // (op 1074) NOP(1250) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) BEGIN + // (op 1255) Assign dim(534) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 534: s**UNALLOCATED** + // (op 1255) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag534: SGPR Value: UInt32 x 1: (unallocated) + // (op 1255) Omitting copy to same register: v1, v1 + // (op 1255) reg expression + // (op 1255) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1255) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 +v_and_b32 v48, -32, v1 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1255) BEGIN: Tile[1] + // (op 1255) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v50 +v_sub_u32 v50, v1, v48 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1255) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v48 + + // (op 1255) BEGIN: Flatten + // (op 1255) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1255) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1255) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1255): v50 + + // (op 1255) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1255) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v49 + + // (op 1255) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1255) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v50 + +// Allocated DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s0 +s_nop 0 +v_readfirstlane_b32 s0, v49 // (op 1255) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1255): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) END + // (op 1074) Assign VGPR 1024:U32(1256) BEGIN + // (op 1256) Assign dim(535) = 1024:U32 + // (op 1256) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1256) END + // (op 1074) NOP(1251) BEGIN + // (op 1251) generate({}) + // (op 1251) end: generate({}) + // (op 1074) NOP(1251) END + // (op 1074) Assign VGPR 2:U32(1260) BEGIN + // (op 1260) Assign dim(537) = 2:U32 + // (op 1260) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1260) END + // (op 1074) NOP(1336) BEGIN + // (op 1336) generate({}) + // (op 1336) end: generate({}) + // (op 1074) NOP(1336) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) BEGIN + // (op 1341) Assign dim(560) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 560: s**UNALLOCATED** + // (op 1341) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag560: SGPR Value: UInt32 x 1: (unallocated) + // (op 1341) Omitting copy to same register: v1, v1 + // (op 1341) reg expression + // (op 1341) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1341) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 +v_and_b32 v48, -32, v1 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1341) BEGIN: Tile[1] + // (op 1341) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v50 +v_sub_u32 v50, v1, v48 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1341) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v48 + + // (op 1341) BEGIN: Flatten + // (op 1341) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1341) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1341) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1341): v50 + + // (op 1341) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1341) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v49 + + // (op 1341) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1341) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v50 + +// Allocated DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s17 +s_nop 0 +v_readfirstlane_b32 s17, v49 // (op 1341) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1341): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) END + // (op 1074) Assign VGPR 1024:U32(1342) BEGIN + // (op 1342) Assign dim(561) = 1024:U32 + // (op 1342) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1342) END + // (op 1074) NOP(1337) BEGIN + // (op 1337) generate({}) + // (op 1337) end: generate({}) + // (op 1074) NOP(1337) END + // (op 1074) Assign VGPR 2:U32(1346) BEGIN + // (op 1346) Assign dim(563) = 2:U32 + // (op 1346) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1346) END + // (op 1074) NOP(1375) BEGIN + // (op 1375) generate({}) + // (op 1375) end: generate({}) + // (op 1074) NOP(1375) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) BEGIN + // (op 1380) Assign dim(572) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 572: s**UNALLOCATED** + // (op 1380) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag572: SGPR Value: UInt32 x 1: (unallocated) + // (op 1380) Omitting copy to same register: v1, v1 + // (op 1380) reg expression + // (op 1380) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1380) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 +v_and_b32 v48, -32, v1 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1380) BEGIN: Tile[1] + // (op 1380) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v50 +v_sub_u32 v50, v1, v48 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1380) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v48 + + // (op 1380) BEGIN: Flatten + // (op 1380) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1380) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1380) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1380): v50 + + // (op 1380) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1380) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v49 + + // (op 1380) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1380) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v50 + +// Allocated DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s16 +s_nop 0 +v_readfirstlane_b32 s16, v49 // (op 1380) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1380): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) END + // (op 1074) Assign VGPR 1024:U32(1381) BEGIN + // (op 1381) Assign dim(573) = 1024:U32 + // (op 1381) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1381) END + // (op 1074) NOP(1376) BEGIN + // (op 1376) generate({}) + // (op 1376) end: generate({}) + // (op 1074) NOP(1376) END + // (op 1074) Assign VGPR 2:U32(1385) BEGIN + // (op 1385) Assign dim(575) = 2:U32 + // (op 1385) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1385) END + // (op 1074) NOP(1414) BEGIN + // (op 1414) generate({}) + // (op 1414) end: generate({}) + // (op 1074) NOP(1414) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) BEGIN + // (op 1419) Assign dim(584) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 584: s**UNALLOCATED** + // (op 1419) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag584: SGPR Value: UInt32 x 1: (unallocated) + // (op 1419) Omitting copy to same register: v1, v1 + // (op 1419) reg expression + // (op 1419) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1419) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 +v_and_b32 v48, -32, v1 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1419) BEGIN: Tile[1] + // (op 1419) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v50 +v_sub_u32 v50, v1, v48 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1419) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v48 + + // (op 1419) BEGIN: Flatten + // (op 1419) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1419) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1419) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1419): v50 + + // (op 1419) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1419) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v49 + + // (op 1419) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1419) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v50 + +// Allocated DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 +s_nop 0 +v_readfirstlane_b32 s40, v49 // (op 1419) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1419): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) END + // (op 1074) Assign VGPR 1024:U32(1420) BEGIN + // (op 1420) Assign dim(585) = 1024:U32 + // (op 1420) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1420) END + // (op 1074) NOP(1415) BEGIN + // (op 1415) generate({}) + // (op 1415) end: generate({}) + // (op 1074) NOP(1415) END + // (op 1074) Assign VGPR 2:U32(1424) BEGIN + // (op 1424) Assign dim(587) = 2:U32 + // (op 1424) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1424) END + // (op 1074) NOP(1453) BEGIN + // (op 1453) generate({}) + // (op 1453) end: generate({}) + // (op 1074) NOP(1453) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) BEGIN + // (op 1458) Assign dim(596) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 596: s**UNALLOCATED** + // (op 1458) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag596: SGPR Value: UInt32 x 1: (unallocated) + // (op 1458) Omitting copy to same register: v1, v1 + // (op 1458) reg expression + // (op 1458) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1458) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 +v_and_b32 v48, -32, v1 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1458) BEGIN: Tile[1] + // (op 1458) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v50 +v_sub_u32 v50, v1, v48 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1458) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v48 + + // (op 1458) BEGIN: Flatten + // (op 1458) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1458) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1458) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1458): v50 + + // (op 1458) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1458) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v49 + + // (op 1458) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1458) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v50 + +// Allocated DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 +s_nop 0 +v_readfirstlane_b32 s41, v49 // (op 1458) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1458): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) END + // (op 1074) Assign VGPR 1024:U32(1459) BEGIN + // (op 1459) Assign dim(597) = 1024:U32 + // (op 1459) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1459) END + // (op 1074) NOP(1454) BEGIN + // (op 1454) generate({}) + // (op 1454) end: generate({}) + // (op 1074) NOP(1454) END + // (op 1074) Assign VGPR 2:U32(1463) BEGIN + // (op 1463) Assign dim(599) = 2:U32 + // (op 1463) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1463) END + // (op 1074) NOP(1492) BEGIN + // (op 1492) generate({}) + // (op 1492) end: generate({}) + // (op 1074) NOP(1492) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) BEGIN + // (op 1497) Assign dim(608) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 608: s**UNALLOCATED** + // (op 1497) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag608: SGPR Value: UInt32 x 1: (unallocated) + // (op 1497) Omitting copy to same register: v1, v1 + // (op 1497) reg expression + // (op 1497) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1497) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 +v_and_b32 v48, -32, v1 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1497) BEGIN: Tile[1] + // (op 1497) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v50 +v_sub_u32 v50, v1, v48 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1497) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v48 + + // (op 1497) BEGIN: Flatten + // (op 1497) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1497) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1497) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1497): v50 + + // (op 1497) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1497) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v49 + + // (op 1497) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1497) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v50 + +// Allocated DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 +s_nop 0 +v_readfirstlane_b32 s42, v49 // (op 1497) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1497): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) END + // (op 1074) Assign VGPR 1024:U32(1498) BEGIN + // (op 1498) Assign dim(609) = 1024:U32 + // (op 1498) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1498) END + // (op 1074) NOP(1493) BEGIN + // (op 1493) generate({}) + // (op 1493) end: generate({}) + // (op 1074) NOP(1493) END + // (op 1074) Assign VGPR 2:U32(1502) BEGIN + // (op 1502) Assign dim(611) = 2:U32 + // (op 1502) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1502) END + // (op 1074) NOP(1531) BEGIN + // (op 1531) generate({}) + // (op 1531) end: generate({}) + // (op 1074) NOP(1531) END + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) BEGIN + // (op 1536) Assign dim(620) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 620: s**UNALLOCATED** + // (op 1536) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag620: SGPR Value: UInt32 x 1: (unallocated) + // (op 1536) Omitting copy to same register: v1, v1 + // (op 1536) reg expression + // (op 1536) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1536) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 +v_and_b32 v48, -32, v1 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 +v_lshrrev_b32 v49, 5, v1 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1536) BEGIN: Tile[1] + // (op 1536) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v50 +v_sub_u32 v50, v1, v48 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1536) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v48 + + // (op 1536) BEGIN: Flatten + // (op 1536) {Flatten: ShiftL({Tile[1]: v50:U32}, 1:U32)U32} + // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1536) value (Tile[1]: VGPR Value: UInt32 x 1: v50) + // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 +v_lshlrev_b32 v48, 1, v50 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1536) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1536): v50 + + // (op 1536) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v50 +v_lshl_add_u32 v50, v49, 6, v48 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1536) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v48 + + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v49 + + // (op 1536) ShiftL({Flatten: v50:U32}, 1:U32)U32 + // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1536) value (Flatten: VGPR Value: UInt32 x 1: v50) + // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 +v_lshlrev_b32 v49, 1, v50 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v50 + +// Allocated DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 +s_nop 0 +v_readfirstlane_b32 s43, v49 // (op 1536) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1536): v49 + + // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) END + // (op 1074) Assign VGPR 1024:U32(1537) BEGIN + // (op 1537) Assign dim(621) = 1024:U32 + // (op 1537) Assign stride expression + // (op 1074) Assign VGPR 1024:U32(1537) END + // (op 1074) NOP(1532) BEGIN + // (op 1532) generate({}) + // (op 1532) end: generate({}) + // (op 1074) NOP(1532) END + // (op 1074) Assign VGPR 2:U32(1541) BEGIN + // (op 1541) Assign dim(623) = 2:U32 + // (op 1541) Assign stride expression + // (op 1074) Assign VGPR 2:U32(1541) END + // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) BEGIN + // (op 39) Initialize For Loop + // (op 39) generate({40}) + // (op 39) Assign SGPR 0:U32(40) BEGIN + // (op 40) Assign dim(245) = 0:U32 + // tag 245: s**UNALLOCATED** + // (op 40) Generate 0:U32 into DataFlowTag245: SGPR Value: UInt32 x 1: (unallocated) +// Allocated DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 +s_mov_b32 s44, 0 // (op 40) call() +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Assign SGPR 0:U32(40) END + // (op 39) end: generate({40}) + // (op 39) Lock For Loop + // Lock Branch +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc + // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL + // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 + // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 +s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 +s_mov_b32 s45, s46 // (op 39) convert +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 + +// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 +s_and_b32 s46, s45, 4294967292 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 + +s_cmp_lt_u32 s44, s46 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoop_39 // (op 39) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoop_39 if false) +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoop_39: + // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) generate({41, 57, 811, 1733}) + // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) BEGIN + // (op 41) Assign dim(245) = Add(DataFlowTag(245)U32, 4:U32)U32 + // (op 41) Generate Add(DataFlowTag(245)U32, 4:U32)U32 into DataFlowTag245: SGPR Value: UInt32 x 1: s44 + // (op 41) Omitting copy to same register: s44, s44 + // (op 41) reg expression + // (op 41) Add({DataFlowTag245: s44:U32}, 4:U32)U32 + // (op 39) Multiply(57) BEGIN + // (op 57) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(811) BEGIN + // (op 39) Barrier(1733) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 811) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 15 and the queue size is 48, so a waitcnt of 32 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 39) Barrier(811) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[16:17], a[0:15] // (op 57) WaitCnt Needed: Intersects with registers in 'DSQueue', at 7 and the queue size is 15, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Multiply(57) END +s_barrier // (op 1733) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 8 +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 39) Barrier(1733) END + // (op 39) Multiply(66) BEGIN + // (op 66) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(332) BEGIN + // (op 332) generate({}) + // (op 332) end: generate({}) + // (op 332) generate({333}) + // (op 332) LoadLDSTile{Value: Halfx2}(333) BEGIN + // (op 333) GEN: loadMacroTileWAVELDS OP 333 LDS 360 WaveTile 145 + // (op 333) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 333) Generate 2:U32 into nullptr + // tag 364: v[16:17] alias 364 -> 19 + // (op 333) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 333) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 333) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) SetCoordinate(604) BEGIN + // (op 604) generate({}) + // (op 604) end: generate({}) + // (op 604) generate({976}) + // (op 604) LoadTileDirect2LDS Value: Halfx2(976) BEGIN + // (op 976) GEN: LoadTileDirect2LDS + // (op 976) GEN: loadMacroTileDirect2LDS OP 976 LDS 21 MacroTile 7 + // (op 976) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 976) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 976) Omitting copy to same register: s[22:23], s[22:23] + // (op 976) reg expression + // (op 976) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 976) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 976) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 976) shiftAmount (Literal Value: UInt32 x 0: 3) +ds_read_b64 v[16:17], v6 offset:16384 // (op 333) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 1511 (current 1491) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 332) LoadLDSTile{Value: Halfx2}(333) END + // (op 332) end: generate({333}) + // (op 39) SetCoordinate(332) END +s_add_u32 s44, s44, 4 // (op 41) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 6 + // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) END + // (op 39) SetCoordinate(337) BEGIN + // (op 337) generate({}) + // (op 337) end: generate({}) + // (op 337) generate({338}) + // (op 337) LoadLDSTile{Value: Halfx2}(338) BEGIN + // (op 338) GEN: loadMacroTileWAVELDS OP 338 LDS 360 WaveTile 145 + // (op 338) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 338) Generate 2:U32 into nullptr + // tag 368: v**UNALLOCATED** + // (op 338) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 338) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16400 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 338) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 +ds_read_b64 v[48:49], v6 offset:16400 // (op 338) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected complete at 1513 (current 1493) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 337) LoadLDSTile{Value: Halfx2}(338) END + // (op 337) end: generate({338}) + // (op 39) SetCoordinate(337) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 4 + // (op 976) Omitting copy to same register: s[46:47], s[46:47] + // (op 976) convert + // (op 976) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 976) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 976) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 976) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(342) BEGIN + // (op 342) generate({}) + // (op 342) end: generate({}) + // (op 342) generate({343}) + // (op 342) LoadLDSTile{Value: Halfx2}(343) BEGIN + // (op 343) GEN: loadMacroTileWAVELDS OP 343 LDS 360 WaveTile 145 + // (op 343) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 343) Generate 2:U32 into nullptr + // tag 372: v**UNALLOCATED** + // (op 343) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 343) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16416 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 343) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 +v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 3 + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 + + // (op 976) Generate 2:U64 into nullptr + // (op 976) Generate 1024:U32 into nullptr + // (op 976) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 508: v**UNALLOCATED** +// Allocated Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 +v_mov_b64 v[52:53], v[18:19] // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 2 +// Allocated : 2 VGPRs (Value: UInt64) (op 976): v54, v55 +v_mov_b64 v[54:55], v[52:53] // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 1 + // (op 976) Generate Add(0:U32, {DataFlowTag534: s0:U32})U32 into nullptr + // (op 976) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 976) Generate {DataFlowTag534: s0:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 976) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // (op 976) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 512 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 +s_mov_b32 s45, 512 // (op 976) call() +// 512 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +s_waitcnt lgkmcnt(8) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[14:15], a[0:15] // (op 66) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 9, so a waitcnt of 8 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // (op 39) Multiply(66) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// VMEM: Expected complete at 1577 (current 1502) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Multiply(75) BEGIN + // (op 75) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 6 + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 5 +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 5 + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 4 +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 4 +// VMEM: Expected complete at 1581 (current 1506) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 3 +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 2 + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 1 +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 1 + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// VMEM: Expected complete at 1585 (current 1510) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 75) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // (op 39) Multiply(75) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 + // (op 39) Multiply(84) BEGIN + // (op 84) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 6 +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 6 + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 5 +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 5 +// VMEM: Expected complete at 1591 (current 1516) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 4 +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 3 + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 2 +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 2 + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 1 +// Allocated : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 +ds_read_b64 v[56:57], v6 offset:16416 // (op 343) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 1 +// DSMEM: Expected complete at 1540 (current 1520) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 342) LoadLDSTile{Value: Halfx2}(343) END + // (op 342) end: generate({343}) + // (op 39) SetCoordinate(342) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[22:23], a[0:15] // (op 84) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // (op 39) Multiply(84) END + // (op 39) SetCoordinate(347) BEGIN + // (op 347) generate({}) + // (op 347) end: generate({}) + // (op 347) generate({348}) + // (op 347) LoadLDSTile{Value: Halfx2}(348) BEGIN + // (op 348) GEN: loadMacroTileWAVELDS OP 348 LDS 360 WaveTile 145 + // (op 348) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 348) Generate 2:U32 into nullptr + // tag 376: v**UNALLOCATED** + // (op 348) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 348) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16432 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 348) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(93) BEGIN + // (op 93) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 +ds_read_b64 v[58:59], v6 offset:16432 // (op 348) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1543 (current 1523) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 347) LoadLDSTile{Value: Halfx2}(348) END + // (op 347) end: generate({348}) + // (op 39) SetCoordinate(347) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[24:25], a[0:15] // (op 93) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 + // (op 39) Multiply(93) END + // (op 39) SetCoordinate(352) BEGIN + // (op 352) generate({}) + // (op 352) end: generate({}) + // (op 352) generate({353}) + // (op 352) LoadLDSTile{Value: Halfx2}(353) BEGIN + // (op 353) GEN: loadMacroTileWAVELDS OP 353 LDS 360 WaveTile 145 + // (op 353) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 353) Generate 2:U32 into nullptr + // tag 380: v**UNALLOCATED** + // (op 353) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 353) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16448 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 353) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(102) BEGIN + // (op 102) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 +ds_read_b64 v[60:61], v6 offset:16448 // (op 353) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1553 (current 1533) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 352) LoadLDSTile{Value: Halfx2}(353) END + // (op 352) end: generate({353}) + // (op 39) SetCoordinate(352) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[26:27], a[0:15] // (op 102) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 + // (op 39) Multiply(102) END + // (op 39) SetCoordinate(357) BEGIN + // (op 357) generate({}) + // (op 357) end: generate({}) + // (op 357) generate({358}) + // (op 357) LoadLDSTile{Value: Halfx2}(358) BEGIN + // (op 358) GEN: loadMacroTileWAVELDS OP 358 LDS 360 WaveTile 145 + // (op 358) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 358) Generate 2:U32 into nullptr + // tag 384: v**UNALLOCATED** + // (op 358) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 358) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16464 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 358) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(111) BEGIN + // (op 111) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 +ds_read_b64 v[62:63], v6 offset:16464 // (op 358) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1563 (current 1543) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 357) LoadLDSTile{Value: Halfx2}(358) END + // (op 357) end: generate({358}) + // (op 39) SetCoordinate(357) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[28:29], a[0:15] // (op 111) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 + // (op 39) Multiply(111) END + // (op 39) SetCoordinate(362) BEGIN + // (op 362) generate({}) + // (op 362) end: generate({}) + // (op 362) generate({363}) + // (op 362) LoadLDSTile{Value: Halfx2}(363) BEGIN + // (op 363) GEN: loadMacroTileWAVELDS OP 363 LDS 360 WaveTile 145 + // (op 363) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 363) Generate 2:U32 into nullptr + // tag 388: v**UNALLOCATED** + // (op 363) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 363) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16480 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 363) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(120) BEGIN + // (op 120) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 +ds_read_b64 v[64:65], v6 offset:16480 // (op 363) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1573 (current 1553) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 362) LoadLDSTile{Value: Halfx2}(363) END + // (op 362) end: generate({363}) + // (op 39) SetCoordinate(362) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[30:31], a[0:15] // (op 120) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 8, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 + // (op 39) Multiply(120) END + // (op 39) SetCoordinate(367) BEGIN + // (op 367) generate({}) + // (op 367) end: generate({}) + // (op 367) generate({368}) + // (op 367) LoadLDSTile{Value: Halfx2}(368) BEGIN + // (op 368) GEN: loadMacroTileWAVELDS OP 368 LDS 360 WaveTile 145 + // (op 368) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 368) Generate 2:U32 into nullptr + // tag 392: v**UNALLOCATED** + // (op 368) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16384 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 368) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v6 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16496 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 368) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 +ds_read_b64 v[66:67], v6 offset:16496 // (op 368) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1583 (current 1563) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 367) LoadLDSTile{Value: Halfx2}(368) END + // (op 367) end: generate({368}) + // (op 39) SetCoordinate(367) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// MFMA remaining: 7 +// VMEM: Expected stall of 14. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 1653 (current 1578) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) Deallocate{}(1819) BEGIN + // (op 1819) Deallocate 582 + // Deleting tag 582 + // (op 39) Deallocate{}(1819) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // (op 39) SetCoordinate(330) BEGIN + // (op 330) generate({}) + // (op 330) end: generate({}) + // (op 330) generate({331}) + // (op 330) LoadLDSTile{Value: Halfx2}(331) BEGIN + // (op 331) GEN: loadMacroTileWAVELDS OP 331 LDS 356 WaveTile 85 + // (op 331) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 331) Generate 2:U32 into nullptr + // tag 362: v[32:33] alias 362 -> 11 + // (op 331) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 331) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 331) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +ds_read_b64 v[32:33], v3 offset:24576 // (op 331) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// DSMEM: Expected complete at 1601 (current 1581) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 330) LoadLDSTile{Value: Halfx2}(331) END + // (op 330) end: generate({331}) + // (op 39) SetCoordinate(330) END +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // (op 39) SetCoordinate(335) BEGIN + // (op 335) generate({}) + // (op 335) end: generate({}) + // (op 335) generate({336}) + // (op 335) LoadLDSTile{Value: Halfx2}(336) BEGIN + // (op 336) GEN: loadMacroTileWAVELDS OP 336 LDS 356 WaveTile 85 + // (op 336) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 336) Generate 2:U32 into nullptr + // tag 366: v[34:35] alias 366 -> 253 + // (op 336) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 336) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24592 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 336) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +ds_read_b64 v[34:35], v3 offset:24592 // (op 336) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1603 (current 1583) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 335) LoadLDSTile{Value: Halfx2}(336) END + // (op 335) end: generate({336}) + // (op 39) SetCoordinate(335) END +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1659 (current 1584) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) + // (op 39) SetCoordinate(340) BEGIN + // (op 340) generate({}) + // (op 340) end: generate({}) + // (op 340) generate({341}) + // (op 340) LoadLDSTile{Value: Halfx2}(341) BEGIN + // (op 341) GEN: loadMacroTileWAVELDS OP 341 LDS 356 WaveTile 85 + // (op 341) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 341) Generate 2:U32 into nullptr + // tag 370: v[36:37] alias 370 -> 257 + // (op 341) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 341) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24608 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 341) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v3 offset:24608 // (op 341) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1605 (current 1585) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 340) LoadLDSTile{Value: Halfx2}(341) END + // (op 340) end: generate({341}) + // (op 39) SetCoordinate(340) END +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // (op 39) SetCoordinate(345) BEGIN + // (op 345) generate({}) + // (op 345) end: generate({}) + // (op 345) generate({346}) + // (op 345) LoadLDSTile{Value: Halfx2}(346) BEGIN + // (op 346) GEN: loadMacroTileWAVELDS OP 346 LDS 356 WaveTile 85 + // (op 346) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 346) Generate 2:U32 into nullptr + // tag 374: v**UNALLOCATED** + // (op 346) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 346) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24624 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 346) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1664 (current 1589) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] + // (op 976) Omitting copy to same register: v[54:55], v[54:55] + // (op 976) reg expression + // (op 976) Omitting copy to same register: v50, v50 + // (op 976) reg expression + // (op 976) Add(v[54:55]:U64, v50:R)U64 + // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = + // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) + // (op 976) rhs (VGPR Value: Raw32 x 1: v50) +// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 +v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 + + // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 976) Omitting copy to same register: m0, m0 + // (op 976) reg expression + // (op 976) Add(m0:U32, 1024:U32)U32 + // (op 976) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 976) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // (op 976) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1668 (current 1593) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 + + // Freeing : 2 VGPRs (Value: UInt64) (op 976): v54, v55 + + // (op 604) LoadTileDirect2LDS Value: Halfx2(976) END + // (op 604) Deallocate{}(1877) BEGIN + // (op 1877) Deallocate 536 + // Deleting tag 536 + // (op 604) Deallocate{}(1877) END + // (op 604) end: generate({976}) + // (op 39) SetCoordinate(604) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 +ds_read_b64 v[50:51], v3 offset:24624 // (op 346) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1614 (current 1594) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 345) LoadLDSTile{Value: Halfx2}(346) END + // (op 345) end: generate({346}) + // (op 39) SetCoordinate(345) END + // (op 39) Barrier(1723) BEGIN + // (op 39) SetCoordinate(350) BEGIN + // (op 350) generate({}) + // (op 350) end: generate({}) + // (op 350) generate({351}) + // (op 350) LoadLDSTile{Value: Halfx2}(351) BEGIN + // (op 351) GEN: loadMacroTileWAVELDS OP 351 LDS 356 WaveTile 85 + // (op 351) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 351) Generate 2:U32 into nullptr + // tag 378: v[38:39] alias 378 -> 261 + // (op 351) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 351) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24640 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 351) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_barrier // (op 1723) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 39) Barrier(1723) END +ds_read_b64 v[38:39], v3 offset:24640 // (op 351) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected stall of 6. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 1622 (current 1602) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 350) LoadLDSTile{Value: Halfx2}(351) END + // (op 350) end: generate({351}) + // (op 39) SetCoordinate(350) END + // (op 39) SetCoordinate(599) BEGIN + // (op 599) generate({}) + // (op 599) end: generate({}) + // (op 599) generate({971}) + // (op 599) LoadTileDirect2LDS Value: Halfx2(971) BEGIN + // (op 971) GEN: LoadTileDirect2LDS + // (op 971) GEN: loadMacroTileDirect2LDS OP 971 LDS 13 MacroTile 6 + // (op 971) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 971) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 971) Omitting copy to same register: s[18:19], s[18:19] + // (op 971) reg expression + // (op 971) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 971) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 971) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 971) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) SetCoordinate(355) BEGIN + // (op 355) generate({}) + // (op 355) end: generate({}) + // (op 355) generate({356}) + // (op 355) LoadLDSTile{Value: Halfx2}(356) BEGIN + // (op 356) GEN: loadMacroTileWAVELDS OP 356 LDS 356 WaveTile 85 + // (op 356) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 356) Generate 2:U32 into nullptr + // tag 382: v**UNALLOCATED** + // (op 356) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 356) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24656 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 356) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Omitting copy to same register: s[46:47], s[46:47] + // (op 971) convert + // (op 971) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 971) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 971) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 971) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 +v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 + + // (op 971) Generate 2:U64 into nullptr + // (op 971) Generate 1024:U32 into nullptr + // (op 971) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[54:55] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 489: v**UNALLOCATED** +// Allocated Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 +v_mov_b64 v[68:69], v[12:13] // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// Allocated : 2 VGPRs (Value: UInt64) (op 971): v70, v71 +v_mov_b64 v[70:71], v[68:69] // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Generate Add(8192:U32, {DataFlowTag518: s1:U32})U32 into nullptr + // (op 971) Omitting copy to same register: s1, s1 + // (op 971) reg expression + // (op 971) Add(8192:U32, {DataFlowTag518: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 971): s45 +s_add_u32 s45, 8192, s1 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // (op 971) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 971) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 971) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 512 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 +s_mov_b32 s46, 512 // (op 971) call() +// 512 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// Allocated : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 +ds_read_b64 v[72:73], v3 offset:24656 // (op 356) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1630 (current 1610) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 355) LoadLDSTile{Value: Halfx2}(356) END + // (op 355) end: generate({356}) + // (op 39) SetCoordinate(355) END +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 43. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 1729 (current 1654) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) SetCoordinate(360) BEGIN + // (op 360) generate({}) + // (op 360) end: generate({}) + // (op 360) generate({361}) + // (op 360) LoadLDSTile{Value: Halfx2}(361) BEGIN + // (op 361) GEN: loadMacroTileWAVELDS OP 361 LDS 356 WaveTile 85 + // (op 361) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 361) Generate 2:U32 into nullptr + // tag 386: v[40:41] alias 386 -> 265 + // (op 361) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 361) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24672 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 361) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[40:41], v3 offset:24672 // (op 361) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1675 (current 1655) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 360) LoadLDSTile{Value: Halfx2}(361) END + // (op 360) end: generate({361}) + // (op 39) SetCoordinate(360) END +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // (op 39) SetCoordinate(365) BEGIN + // (op 365) generate({}) + // (op 365) end: generate({}) + // (op 365) generate({366}) + // (op 365) LoadLDSTile{Value: Halfx2}(366) BEGIN + // (op 366) GEN: loadMacroTileWAVELDS OP 366 LDS 356 WaveTile 85 + // (op 366) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 366) Generate 2:U32 into nullptr + // tag 390: v**UNALLOCATED** + // (op 366) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24576 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 366) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v3 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 24688 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 366) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// Allocated : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 +ds_read_b64 v[74:75], v3 offset:24688 // (op 366) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// DSMEM: Expected complete at 1679 (current 1659) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 365) LoadLDSTile{Value: Halfx2}(366) END + // (op 365) end: generate({366}) + // (op 39) SetCoordinate(365) END +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1735 (current 1660) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1817) BEGIN + // (op 1817) Deallocate 570 + // Deleting tag 570 + // (op 39) Deallocate{}(1817) END +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 1740 (current 1665) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1744 (current 1669) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 57. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 1805 (current 1730) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 1811 (current 1736) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 1816 (current 1741) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 971) Omitting copy to same register: v[70:71], v[70:71] + // (op 971) reg expression + // (op 971) Omitting copy to same register: v54, v54 + // (op 971) reg expression + // (op 971) Add(v[70:71]:U64, v54:R)U64 + // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 971) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 + + // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 971) Omitting copy to same register: m0, m0 + // (op 971) reg expression + // (op 971) Add(m0:U32, 1024:U32)U32 + // (op 971) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 971) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 971) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// VMEM: Expected complete at 1820 (current 1745) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 + + // Freeing : 2 VGPRs (Value: UInt64) (op 971): v70, v71 + + // Freeing : 1 SGPR (Value: UInt32) (op 971): s45 + + // (op 599) LoadTileDirect2LDS Value: Halfx2(971) END + // (op 599) Deallocate{}(1875) BEGIN + // (op 1875) Deallocate 520 + // Deleting tag 520 + // (op 599) Deallocate{}(1875) END + // (op 599) end: generate({971}) + // (op 39) SetCoordinate(599) END + // (op 39) NOP(1000) BEGIN + // (op 1000) generate({}) + // (op 1000) end: generate({}) + // (op 39) NOP(1000) END + // (op 39) NOP(995) BEGIN + // (op 995) generate({}) + // (op 995) end: generate({}) + // (op 39) NOP(995) END + // (op 39) NOP(799) BEGIN + // (op 799) generate({}) + // (op 799) end: generate({}) + // (op 39) NOP(799) END + // (op 39) Multiply(334) BEGIN + // (op 334) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(853) BEGIN + // (op 39) Barrier(1746) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 853) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 15 and the queue size is 48, so a waitcnt of 32 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 39) Barrier(853) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[16:17], a[0:15] // (op 334) WaitCnt Needed: Intersects with registers in 'DSQueue', at 8 and the queue size is 16, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[48:49], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[66:67], LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // (op 39) Multiply(334) END +s_barrier // (op 1746) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// MFMA remaining: 8 +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 39) Barrier(1746) END + // (op 39) Deallocate{}(1803) BEGIN + // (op 1803) Deallocate 364 + // Deleting tag 364alias (-> 19) + // (op 1803) Deallocate 362 + // Deleting tag 362alias (-> 11) + // (op 39) Deallocate{}(1803) END + // (op 39) SetCoordinate(615) BEGIN + // (op 615) generate({}) + // (op 615) end: generate({}) + // (op 615) generate({998}) + // (op 615) LoadTileDirect2LDS Value: Halfx2(998) BEGIN + // (op 998) GEN: LoadTileDirect2LDS + // (op 998) GEN: loadMacroTileDirect2LDS OP 998 LDS 360 MacroTile 358 + // (op 998) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 998) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 998) Omitting copy to same register: s[22:23], s[22:23] + // (op 998) reg expression + // (op 998) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 998) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 998) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 998) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) Multiply(339) BEGIN + // (op 339) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(422) BEGIN + // (op 422) generate({}) + // (op 422) end: generate({}) + // (op 422) generate({423}) + // (op 422) LoadLDSTile{Value: Halfx2}(423) BEGIN + // (op 423) GEN: loadMacroTileWAVELDS OP 423 LDS 400 WaveTile 145 + // (op 423) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 423) Generate 2:U32 into nullptr + // tag 404: v[16:17] alias 404 -> 19 + // (op 423) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 423) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 423) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[16:17], v8 offset:32768 // (op 423) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 1771 (current 1751) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 422) LoadLDSTile{Value: Halfx2}(423) END + // (op 422) end: generate({423}) + // (op 39) SetCoordinate(422) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 6 + // (op 998) Omitting copy to same register: s[46:47], s[46:47] + // (op 998) convert + // (op 998) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 998) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 998) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 998) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(427) BEGIN + // (op 427) generate({}) + // (op 427) end: generate({}) + // (op 427) generate({428}) + // (op 427) LoadLDSTile{Value: Halfx2}(428) BEGIN + // (op 428) GEN: loadMacroTileWAVELDS OP 428 LDS 400 WaveTile 145 + // (op 428) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 428) Generate 2:U32 into nullptr + // tag 408: v[14:15] alias 408 -> 255 + // (op 428) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[14:15] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 428) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[14:15] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32784 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 428) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[14:15], v8 offset:32784 // (op 428) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected complete at 1773 (current 1753) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 427) LoadLDSTile{Value: Halfx2}(428) END + // (op 427) end: generate({428}) + // (op 39) SetCoordinate(427) END +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 +v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 4 + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 + + // (op 998) Generate 2:U64 into nullptr + // (op 998) Generate 1024:U32 into nullptr + // (op 998) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 16384 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[54:55] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // (op 39) SetCoordinate(432) BEGIN + // (op 432) generate({}) + // (op 432) end: generate({}) + // (op 432) generate({433}) + // (op 432) LoadLDSTile{Value: Halfx2}(433) BEGIN + // (op 433) GEN: loadMacroTileWAVELDS OP 433 LDS 400 WaveTile 145 + // (op 433) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 433) Generate 2:U32 into nullptr + // tag 412: v[20:21] alias 412 -> 259 + // (op 433) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 433) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32800 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 433) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[20:21], v8 offset:32800 // (op 433) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 3 +// DSMEM: Expected complete at 1775 (current 1755) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 432) LoadLDSTile{Value: Halfx2}(433) END + // (op 432) end: generate({433}) + // (op 39) SetCoordinate(432) END +// Allocated : 2 VGPRs (Value: UInt64) (op 998): v70, v71 +v_mov_b64 v[70:71], v[52:53] // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 2 + // (op 998) Generate Add(16384:U32, {DataFlowTag572: s16:U32})U32 into nullptr + // (op 998) Omitting copy to same register: s16, s16 + // (op 998) reg expression + // (op 998) Add(16384:U32, {DataFlowTag572: s16:U32})U32 + // (op 39) SetCoordinate(437) BEGIN + // (op 437) generate({}) + // (op 437) end: generate({}) + // (op 437) generate({438}) + // (op 437) LoadLDSTile{Value: Halfx2}(438) BEGIN + // (op 438) GEN: loadMacroTileWAVELDS OP 438 LDS 400 WaveTile 145 + // (op 438) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 438) Generate 2:U32 into nullptr + // tag 416: v[22:23] alias 416 -> 263 + // (op 438) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 438) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32816 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 438) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[22:23], v8 offset:32816 // (op 438) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 1 +// DSMEM: Expected complete at 1777 (current 1757) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 437) LoadLDSTile{Value: Halfx2}(438) END + // (op 437) end: generate({438}) + // (op 39) SetCoordinate(437) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[48:49], a[0:15] // (op 339) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 11, so a waitcnt of 10 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // (op 39) Multiply(339) END + // (op 39) SetCoordinate(442) BEGIN + // (op 442) generate({}) + // (op 442) end: generate({}) + // (op 442) generate({443}) + // (op 442) LoadLDSTile{Value: Halfx2}(443) BEGIN + // (op 443) GEN: loadMacroTileWAVELDS OP 443 LDS 400 WaveTile 145 + // (op 443) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 443) Generate 2:U32 into nullptr + // tag 420: v[24:25] alias 420 -> 267 + // (op 443) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 443) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32832 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 443) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1805) BEGIN + // (op 1805) Deallocate 366 + // Deleting tag 366alias (-> 253) + // (op 1805) Deallocate 368 + // Freeing : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 + + // Deleting tag 368 + // (op 39) Deallocate{}(1805) END +// Allocated : 1 SGPR (Value: UInt32) (op 998): s45 +s_add_u32 s45, 16384, s16 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 8 + // (op 998) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 998) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) Multiply(344) BEGIN + // (op 344) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_mov_b32 m0, s45 // (op 998) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 7 + // (op 998) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 640 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 +s_mov_b32 s46, 640 // (op 998) call() +// 640 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 6 +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[56:57], a[0:15] // (op 344) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 10, so a waitcnt of 9 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 5 + // (op 39) Multiply(344) END +ds_read_b64 v[24:25], v8 offset:32832 // (op 443) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 1792 (current 1772) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 442) LoadLDSTile{Value: Halfx2}(443) END + // (op 442) end: generate({443}) + // (op 39) SetCoordinate(442) END + // (op 39) Deallocate{}(1807) BEGIN + // (op 1807) Deallocate 372 + // Freeing : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 + + // Deleting tag 372 + // (op 1807) Deallocate 370 + // Deleting tag 370alias (-> 257) + // (op 39) Deallocate{}(1807) END + // (op 39) SetCoordinate(447) BEGIN + // (op 447) generate({}) + // (op 447) end: generate({}) + // (op 447) generate({448}) + // (op 447) LoadLDSTile{Value: Halfx2}(448) BEGIN + // (op 448) GEN: loadMacroTileWAVELDS OP 448 LDS 400 WaveTile 145 + // (op 448) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 448) Generate 2:U32 into nullptr + // tag 424: v[26:27] alias 424 -> 271 + // (op 448) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 448) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32848 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 448) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(349) BEGIN + // (op 349) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[26:27], v8 offset:32848 // (op 448) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 1794 (current 1774) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 447) LoadLDSTile{Value: Halfx2}(448) END + // (op 447) end: generate({448}) + // (op 39) SetCoordinate(447) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[50:51], v[58:59], a[0:15] // (op 349) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 11, so a waitcnt of 10 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 3 + // (op 39) Multiply(349) END + // (op 39) SetCoordinate(452) BEGIN + // (op 452) generate({}) + // (op 452) end: generate({}) + // (op 452) generate({453}) + // (op 452) LoadLDSTile{Value: Halfx2}(453) BEGIN + // (op 453) GEN: loadMacroTileWAVELDS OP 453 LDS 400 WaveTile 145 + // (op 453) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 453) Generate 2:U32 into nullptr + // tag 428: v[28:29] alias 428 -> 275 + // (op 453) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 453) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32864 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 453) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1809) BEGIN + // (op 1809) Deallocate 376 + // Freeing : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 + + // Deleting tag 376 + // (op 1809) Deallocate 374 + // Freeing : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 + + // Deleting tag 374 + // (op 39) Deallocate{}(1809) END +ds_read_b64 v[28:29], v8 offset:32864 // (op 453) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1800 (current 1780) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 452) LoadLDSTile{Value: Halfx2}(453) END + // (op 452) end: generate({453}) + // (op 39) SetCoordinate(452) END + // (op 39) Multiply(354) BEGIN + // (op 354) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(457) BEGIN + // (op 457) generate({}) + // (op 457) end: generate({}) + // (op 457) generate({458}) + // (op 457) LoadLDSTile{Value: Halfx2}(458) BEGIN + // (op 458) GEN: loadMacroTileWAVELDS OP 458 LDS 400 WaveTile 145 + // (op 458) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 458) Generate 2:U32 into nullptr + // tag 432: v[30:31] alias 432 -> 279 + // (op 458) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32768 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 458) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v8 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32880 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 458) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[30:31], v8 offset:32880 // (op 458) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 1801 (current 1781) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 457) LoadLDSTile{Value: Halfx2}(458) END + // (op 457) end: generate({458}) + // (op 39) SetCoordinate(457) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[60:61], a[0:15] // (op 354) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 12, so a waitcnt of 11 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 6 + // (op 39) Multiply(354) END + // (op 39) Deallocate{}(1839) BEGIN + // (op 1839) Deallocate 606 + // Deleting tag 606 + // (op 39) Deallocate{}(1839) END + // (op 39) Deallocate{}(1811) BEGIN + // (op 1811) Deallocate 378 + // Deleting tag 378alias (-> 261) + // (op 1811) Deallocate 380 + // Freeing : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 + + // Deleting tag 380 + // (op 39) Deallocate{}(1811) END + // (op 39) SetCoordinate(420) BEGIN + // (op 420) generate({}) + // (op 420) end: generate({}) + // (op 420) generate({421}) + // (op 420) LoadLDSTile{Value: Halfx2}(421) BEGIN + // (op 421) GEN: loadMacroTileWAVELDS OP 421 LDS 396 WaveTile 85 + // (op 421) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 421) Generate 2:U32 into nullptr + // tag 402: v[32:33] alias 402 -> 11 + // (op 421) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 421) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 421) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(359) BEGIN + // (op 359) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[32:33], v5 offset:40960 // (op 421) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 1813 (current 1793) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 420) LoadLDSTile{Value: Halfx2}(421) END + // (op 420) end: generate({421}) + // (op 39) SetCoordinate(420) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[62:63], a[0:15] // (op 359) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 12, so a waitcnt of 11 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[72:73], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 4 + // (op 39) Multiply(359) END + // (op 39) SetCoordinate(425) BEGIN + // (op 425) generate({}) + // (op 425) end: generate({}) + // (op 425) generate({426}) + // (op 425) LoadLDSTile{Value: Halfx2}(426) BEGIN + // (op 426) GEN: loadMacroTileWAVELDS OP 426 LDS 396 WaveTile 85 + // (op 426) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 426) Generate 2:U32 into nullptr + // tag 406: v[34:35] alias 406 -> 253 + // (op 426) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 426) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40976 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 426) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1813) BEGIN + // (op 1813) Deallocate 382 + // Freeing : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 + + // Deleting tag 382 + // (op 1813) Deallocate 384 + // Freeing : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 + + // Deleting tag 384 + // (op 39) Deallocate{}(1813) END +ds_read_b64 v[34:35], v5 offset:40976 // (op 426) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 1820 (current 1800) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 425) LoadLDSTile{Value: Halfx2}(426) END + // (op 425) end: generate({426}) + // (op 39) SetCoordinate(425) END + // (op 39) Multiply(364) BEGIN + // (op 364) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(430) BEGIN + // (op 430) generate({}) + // (op 430) end: generate({}) + // (op 430) generate({431}) + // (op 430) LoadLDSTile{Value: Halfx2}(431) BEGIN + // (op 431) GEN: loadMacroTileWAVELDS OP 431 LDS 396 WaveTile 85 + // (op 431) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 431) Generate 2:U32 into nullptr + // tag 410: v[36:37] alias 410 -> 257 + // (op 431) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 431) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40992 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 431) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v5 offset:40992 // (op 431) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 1821 (current 1801) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 430) LoadLDSTile{Value: Halfx2}(431) END + // (op 430) end: generate({431}) + // (op 39) SetCoordinate(430) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 6 +// VMEM: Expected stall of 4. CBNW: 28, Inc: 4 +// VMEM: Expected complete at 1881 (current 1806) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) SetCoordinate(435) BEGIN + // (op 435) generate({}) + // (op 435) end: generate({}) + // (op 435) generate({436}) + // (op 435) LoadLDSTile{Value: Halfx2}(436) BEGIN + // (op 436) GEN: loadMacroTileWAVELDS OP 436 LDS 396 WaveTile 85 + // (op 436) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 436) Generate 2:U32 into nullptr + // tag 414: v[42:43] alias 414 -> 269 + // (op 436) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 436) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41008 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 436) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[42:43], v5 offset:41008 // (op 436) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 1 +// DSMEM: Expected complete at 1827 (current 1807) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 435) LoadLDSTile{Value: Halfx2}(436) END + // (op 435) end: generate({436}) + // (op 39) SetCoordinate(435) END +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[64:65], a[0:15] // (op 364) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 14, so a waitcnt of 13 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // (op 39) Multiply(364) END + // (op 39) SetCoordinate(440) BEGIN + // (op 440) generate({}) + // (op 440) end: generate({}) + // (op 440) generate({441}) + // (op 440) LoadLDSTile{Value: Halfx2}(441) BEGIN + // (op 441) GEN: loadMacroTileWAVELDS OP 441 LDS 396 WaveTile 85 + // (op 441) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 441) Generate 2:U32 into nullptr + // tag 418: v[44:45] alias 418 -> 273 + // (op 441) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 441) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41024 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 441) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1815) BEGIN + // (op 1815) Deallocate 386 + // Deleting tag 386alias (-> 265) + // (op 1815) Deallocate 388 + // Freeing : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 + + // Deleting tag 388 + // (op 39) Deallocate{}(1815) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 8 + // (op 39) Multiply(369) BEGIN + // (op 369) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 7 + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 6 +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 6 + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 5 +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 5 +// VMEM: Expected complete at 1888 (current 1813) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +ds_read_b64 v[44:45], v5 offset:41024 // (op 441) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 4 +// DSMEM: Expected complete at 1834 (current 1814) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 440) LoadLDSTile{Value: Halfx2}(441) END + // (op 440) end: generate({441}) + // (op 39) SetCoordinate(440) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 3 + // (op 39) SetCoordinate(445) BEGIN + // (op 445) generate({}) + // (op 445) end: generate({}) + // (op 445) generate({446}) + // (op 445) LoadLDSTile{Value: Halfx2}(446) BEGIN + // (op 446) GEN: loadMacroTileWAVELDS OP 446 LDS 396 WaveTile 85 + // (op 446) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 446) Generate 2:U32 into nullptr + // tag 422: v[46:47] alias 422 -> 277 + // (op 446) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 446) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41040 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 446) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 2 + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 1 +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 1 + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[66:67], a[0:15] // (op 369) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 14, so a waitcnt of 13 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // (op 39) Multiply(369) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 8 +// VMEM: Expected complete at 1895 (current 1820) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1821) BEGIN + // (op 1821) Deallocate 392 + // Freeing : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 + + // Deleting tag 392 + // (op 1821) Deallocate 390 + // Freeing : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 + + // Deleting tag 390 + // (op 39) Deallocate{}(1821) END +ds_read_b64 v[46:47], v5 offset:41040 // (op 446) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 1841 (current 1821) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 445) LoadLDSTile{Value: Halfx2}(446) END + // (op 445) end: generate({446}) + // (op 39) SetCoordinate(445) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 6 + // (op 39) SetCoordinate(450) BEGIN + // (op 450) generate({}) + // (op 450) end: generate({}) + // (op 450) generate({451}) + // (op 450) LoadLDSTile{Value: Halfx2}(451) BEGIN + // (op 451) GEN: loadMacroTileWAVELDS OP 451 LDS 396 WaveTile 85 + // (op 451) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 451) Generate 2:U32 into nullptr + // tag 426: v[38:39] alias 426 -> 261 + // (op 451) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 451) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41056 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 451) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 5 + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 4 +ds_read_b64 v[38:39], v5 offset:41056 // (op 451) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 4 +// DSMEM: Expected complete at 1844 (current 1824) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 450) LoadLDSTile{Value: Halfx2}(451) END + // (op 450) end: generate({451}) + // (op 39) SetCoordinate(450) END +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 3 + // (op 39) SetCoordinate(455) BEGIN + // (op 455) generate({}) + // (op 455) end: generate({}) + // (op 455) generate({456}) + // (op 455) LoadLDSTile{Value: Halfx2}(456) BEGIN + // (op 456) GEN: loadMacroTileWAVELDS OP 456 LDS 396 WaveTile 85 + // (op 456) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 456) Generate 2:U32 into nullptr + // tag 430: v**UNALLOCATED** + // (op 456) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 40960 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 456) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v5 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 41072 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 456) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 2 +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 2 +// VMEM: Expected complete at 1901 (current 1826) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 1 +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// Allocated : 2 VGPRs (Value: Halfx2) (op 456): v50, v51 +ds_read_b64 v[50:51], v5 offset:41072 // (op 456) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// DSMEM: Expected complete at 1850 (current 1830) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 455) LoadLDSTile{Value: Halfx2}(456) END + // (op 455) end: generate({456}) + // (op 39) SetCoordinate(455) END +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 1957 (current 1882) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) + // (op 39) Deallocate{}(1837) BEGIN + // (op 1837) Deallocate 594 + // Deleting tag 594 + // (op 39) Deallocate{}(1837) END +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 +// VMEM: Expected complete at 1964 (current 1889) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 1971 (current 1896) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] + // (op 998) Omitting copy to same register: v[70:71], v[70:71] + // (op 998) reg expression + // (op 998) Omitting copy to same register: v54, v54 + // (op 998) reg expression + // (op 998) Add(v[70:71]:U64, v54:R)U64 + // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = + // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) + // (op 998) rhs (VGPR Value: Raw32 x 1: v54) +// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 +v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 + + // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 998) Omitting copy to same register: m0, m0 + // (op 998) reg expression + // (op 998) Add(m0:U32, 1024:U32)U32 + // (op 998) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 998) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 998) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 1977 (current 1902) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 + + // Freeing : 2 VGPRs (Value: UInt64) (op 998): v70, v71 + + // Freeing : 1 SGPR (Value: UInt32) (op 998): s45 + + // (op 615) LoadTileDirect2LDS Value: Halfx2(998) END + // (op 615) Deallocate{}(1885) BEGIN + // (op 1885) Deallocate 574 + // Deleting tag 574 + // (op 615) Deallocate{}(1885) END + // (op 615) end: generate({998}) + // (op 39) SetCoordinate(615) END + // (op 39) Barrier(1743) BEGIN +s_barrier // (op 1743) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 39) Barrier(1743) END + // (op 39) SetCoordinate(610) BEGIN + // (op 610) generate({}) + // (op 610) end: generate({}) + // (op 610) generate({993}) + // (op 610) LoadTileDirect2LDS Value: Halfx2(993) BEGIN + // (op 993) GEN: LoadTileDirect2LDS + // (op 993) GEN: loadMacroTileDirect2LDS OP 993 LDS 356 MacroTile 354 + // (op 993) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 993) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 993) Omitting copy to same register: s[18:19], s[18:19] + // (op 993) reg expression + // (op 993) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 993) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 993) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 993) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Omitting copy to same register: s[46:47], s[46:47] + // (op 993) convert + // (op 993) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 993) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 993) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 993) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 993): v48, v49 +v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 + + // (op 993) Generate 2:U64 into nullptr + // (op 993) Generate 1024:U32 into nullptr + // (op 993) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 24576 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[48:49] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 993): v66, v67 +v_mov_b64 v[66:67], v[68:69] // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Generate Add(24576:U32, {DataFlowTag560: s17:U32})U32 into nullptr + // (op 993) Omitting copy to same register: s17, s17 + // (op 993) reg expression + // (op 993) Add(24576:U32, {DataFlowTag560: s17:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 993): s45 +s_add_u32 s45, 24576, s17 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 993) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 993) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 640 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 +s_mov_b32 s46, 640 // (op 993) call() +// 640 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 48. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2033 (current 1958) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2040 (current 1965) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2047 (current 1972) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2053 (current 1978) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2109 (current 2034) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2116 (current 2041) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2123 (current 2048) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // (op 993) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 993) Omitting copy to same register: v[66:67], v[66:67] + // (op 993) reg expression + // (op 993) Omitting copy to same register: v48, v48 + // (op 993) reg expression + // (op 993) Add(v[66:67]:U64, v48:R)U64 + // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 993) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 993) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 993) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 993) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 + + // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 993) Omitting copy to same register: m0, m0 + // (op 993) reg expression + // (op 993) Add(m0:U32, 1024:U32)U32 + // (op 993) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 993) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 993) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2129 (current 2054) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 993): v48, v49 + + // Freeing : 2 VGPRs (Value: UInt64) (op 993): v66, v67 + + // Freeing : 1 SGPR (Value: UInt32) (op 993): s45 + + // (op 610) LoadTileDirect2LDS Value: Halfx2(993) END + // (op 610) Deallocate{}(1883) BEGIN + // (op 1883) Deallocate 562 + // Deleting tag 562 + // (op 610) Deallocate{}(1883) END + // (op 610) end: generate({993}) + // (op 39) SetCoordinate(610) END + // (op 39) NOP(1010) BEGIN + // (op 1010) generate({}) + // (op 1010) end: generate({}) + // (op 39) NOP(1010) END + // (op 39) NOP(1005) BEGIN + // (op 1005) generate({}) + // (op 1005) end: generate({}) + // (op 39) NOP(1005) END + // (op 39) NOP(800) BEGIN + // (op 800) generate({}) + // (op 800) end: generate({}) + // (op 39) NOP(800) END + // (op 39) Multiply(424) BEGIN + // (op 424) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(895) BEGIN + // (op 39) Barrier(1752) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 895) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 15 and the queue size is 48, so a waitcnt of 32 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 39) Barrier(895) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[16:17], a[0:15] // (op 424) WaitCnt Needed: Intersects with registers in 'DSQueue', at 8 and the queue size is 16, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // (op 39) Multiply(424) END +s_barrier // (op 1752) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 8 +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 39) Barrier(1752) END + // (op 39) Deallocate{}(1823) BEGIN + // (op 1823) Deallocate 402 + // Deleting tag 402alias (-> 11) + // (op 1823) Deallocate 404 + // Deleting tag 404alias (-> 19) + // (op 39) Deallocate{}(1823) END + // (op 39) SetCoordinate(629) BEGIN + // (op 629) generate({}) + // (op 629) end: generate({}) + // (op 629) generate({1008}) + // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) BEGIN + // (op 1008) GEN: LoadTileDirect2LDS + // (op 1008) GEN: loadMacroTileDirect2LDS OP 1008 LDS 400 MacroTile 398 + // (op 1008) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1008) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 1008) Omitting copy to same register: s[22:23], s[22:23] + // (op 1008) reg expression + // (op 1008) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1008) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1008) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) Multiply(429) BEGIN + // (op 429) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(512) BEGIN + // (op 512) generate({}) + // (op 512) end: generate({}) + // (op 512) generate({513}) + // (op 512) LoadLDSTile{Value: Halfx2}(513) BEGIN + // (op 513) GEN: loadMacroTileWAVELDS OP 513 LDS 440 WaveTile 145 + // (op 513) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 513) Generate 2:U32 into nullptr + // tag 444: v[16:17] alias 444 -> 19 + // (op 513) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 513) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 513) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[16:17], v10 offset:49152 // (op 513) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2080 (current 2060) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 512) LoadLDSTile{Value: Halfx2}(513) END + // (op 512) end: generate({513}) + // (op 39) SetCoordinate(512) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 6 + // (op 1008) Omitting copy to same register: s[46:47], s[46:47] + // (op 1008) convert + // (op 1008) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1008) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1008) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(517) BEGIN + // (op 517) generate({}) + // (op 517) end: generate({}) + // (op 517) generate({518}) + // (op 517) LoadLDSTile{Value: Halfx2}(518) BEGIN + // (op 518) GEN: loadMacroTileWAVELDS OP 518 LDS 440 WaveTile 145 + // (op 518) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 518) Generate 2:U32 into nullptr + // tag 448: v**UNALLOCATED** + // (op 518) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 518) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49168 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 518) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1008): v48, v49 +v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 5 + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 + + // (op 1008) Generate 2:U64 into nullptr + // (op 1008) Generate 1024:U32 into nullptr + // (op 1008) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 32768 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[48:49] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1008): v66, v67 +v_mov_b64 v[66:67], v[52:53] // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 4 + // (op 1008) Generate Add(32768:U32, {DataFlowTag596: s41:U32})U32 into nullptr + // (op 1008) Omitting copy to same register: s41, s41 + // (op 1008) reg expression + // (op 1008) Add(32768:U32, {DataFlowTag596: s41:U32})U32 +// Allocated : 2 VGPRs (Value: Halfx2) (op 518): v64, v65 +ds_read_b64 v[64:65], v10 offset:49168 // (op 518) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 3 +// DSMEM: Expected complete at 2084 (current 2064) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 517) LoadLDSTile{Value: Halfx2}(518) END + // (op 517) end: generate({518}) + // (op 39) SetCoordinate(517) END +// Allocated : 1 SGPR (Value: UInt32) (op 1008): s45 +s_add_u32 s45, 32768, s41 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 2 + // (op 1008) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1008) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) SetCoordinate(522) BEGIN + // (op 522) generate({}) + // (op 522) end: generate({}) + // (op 522) generate({523}) + // (op 522) LoadLDSTile{Value: Halfx2}(523) BEGIN + // (op 523) GEN: loadMacroTileWAVELDS OP 523 LDS 440 WaveTile 145 + // (op 523) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 523) Generate 2:U32 into nullptr + // tag 452: v**UNALLOCATED** + // (op 523) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 523) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49184 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 523) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_mov_b32 m0, s45 // (op 1008) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 1 + // (op 1008) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 768 is not a supported value! +// Allocated : 2 VGPRs (Value: Halfx2) (op 523): v62, v63 +ds_read_b64 v[62:63], v10 offset:49184 // (op 523) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// DSMEM: Expected complete at 2087 (current 2067) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 522) LoadLDSTile{Value: Halfx2}(523) END + // (op 522) end: generate({523}) + // (op 39) SetCoordinate(522) END +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[14:15], a[0:15] // (op 429) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 10, so a waitcnt of 9 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // (op 39) Multiply(429) END + // (op 39) SetCoordinate(527) BEGIN + // (op 527) generate({}) + // (op 527) end: generate({}) + // (op 527) generate({528}) + // (op 527) LoadLDSTile{Value: Halfx2}(528) BEGIN + // (op 528) GEN: loadMacroTileWAVELDS OP 528 LDS 440 WaveTile 145 + // (op 528) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 528) Generate 2:U32 into nullptr + // tag 456: v**UNALLOCATED** + // (op 528) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 528) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49200 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 528) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1825) BEGIN + // (op 1825) Deallocate 406 + // Deleting tag 406alias (-> 253) + // (op 1825) Deallocate 408 + // Deleting tag 408alias (-> 255) + // (op 39) Deallocate{}(1825) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 +ds_read_b64 v[60:61], v10 offset:49200 // (op 528) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 2090 (current 2070) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 527) LoadLDSTile{Value: Halfx2}(528) END + // (op 527) end: generate({528}) + // (op 39) SetCoordinate(527) END + // (op 39) Multiply(434) BEGIN + // (op 434) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(532) BEGIN + // (op 532) generate({}) + // (op 532) end: generate({}) + // (op 532) generate({533}) + // (op 532) LoadLDSTile{Value: Halfx2}(533) BEGIN + // (op 533) GEN: loadMacroTileWAVELDS OP 533 LDS 440 WaveTile 145 + // (op 533) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 533) Generate 2:U32 into nullptr + // tag 460: v**UNALLOCATED** + // (op 533) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 533) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49216 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 533) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 +s_mov_b32 s46, 768 // (op 1008) call() +// 768 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 7 +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 434) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 10, so a waitcnt of 9 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 6 + // (op 39) Multiply(434) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 533): v58, v59 +ds_read_b64 v[58:59], v10 offset:49216 // (op 533) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 1. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 2101 (current 2081) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 532) LoadLDSTile{Value: Halfx2}(533) END + // (op 532) end: generate({533}) + // (op 39) SetCoordinate(532) END + // (op 39) Deallocate{}(1827) BEGIN + // (op 1827) Deallocate 410 + // Deleting tag 410alias (-> 257) + // (op 1827) Deallocate 412 + // Deleting tag 412alias (-> 259) + // (op 39) Deallocate{}(1827) END + // (op 39) SetCoordinate(537) BEGIN + // (op 537) generate({}) + // (op 537) end: generate({}) + // (op 537) generate({538}) + // (op 537) LoadLDSTile{Value: Halfx2}(538) BEGIN + // (op 538) GEN: loadMacroTileWAVELDS OP 538 LDS 440 WaveTile 145 + // (op 538) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 538) Generate 2:U32 into nullptr + // tag 464: v**UNALLOCATED** + // (op 538) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 538) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49232 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 538) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(439) BEGIN + // (op 439) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +// Allocated : 2 VGPRs (Value: Halfx2) (op 538): v56, v57 +ds_read_b64 v[56:57], v10 offset:49232 // (op 538) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 6 +// DSMEM: Expected stall of 3. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 2105 (current 2085) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 537) LoadLDSTile{Value: Halfx2}(538) END + // (op 537) end: generate({538}) + // (op 39) SetCoordinate(537) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[22:23], a[0:15] // (op 439) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 11, so a waitcnt of 10 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[42:43], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 2 + // (op 39) Multiply(439) END + // (op 39) SetCoordinate(542) BEGIN + // (op 542) generate({}) + // (op 542) end: generate({}) + // (op 542) generate({543}) + // (op 542) LoadLDSTile{Value: Halfx2}(543) BEGIN + // (op 543) GEN: loadMacroTileWAVELDS OP 543 LDS 440 WaveTile 145 + // (op 543) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 543) Generate 2:U32 into nullptr + // tag 468: v**UNALLOCATED** + // (op 543) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 543) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49248 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 543) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1829) BEGIN + // (op 1829) Deallocate 414 + // Deleting tag 414alias (-> 269) + // (op 1829) Deallocate 416 + // Deleting tag 416alias (-> 263) + // (op 39) Deallocate{}(1829) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 543): v54, v55 +ds_read_b64 v[54:55], v10 offset:49248 // (op 543) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 2110 (current 2090) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 542) LoadLDSTile{Value: Halfx2}(543) END + // (op 542) end: generate({543}) + // (op 39) SetCoordinate(542) END + // (op 39) Multiply(444) BEGIN + // (op 444) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(547) BEGIN + // (op 547) generate({}) + // (op 547) end: generate({}) + // (op 547) generate({548}) + // (op 547) LoadLDSTile{Value: Halfx2}(548) BEGIN + // (op 548) GEN: loadMacroTileWAVELDS OP 548 LDS 440 WaveTile 145 + // (op 548) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 548) Generate 2:U32 into nullptr + // tag 472: v**UNALLOCATED** + // (op 548) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49152 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 548) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 49264 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 548) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 +ds_read_b64 v[70:71], v10 offset:49264 // (op 548) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2111 (current 2091) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 547) LoadLDSTile{Value: Halfx2}(548) END + // (op 547) end: generate({548}) + // (op 39) SetCoordinate(547) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[24:25], a[0:15] // (op 444) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 12, so a waitcnt of 11 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[44:45], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 6 + // (op 39) Multiply(444) END + // (op 39) Deallocate{}(1859) BEGIN + // (op 1859) Deallocate 630 + // Deleting tag 630 + // (op 39) Deallocate{}(1859) END + // (op 39) Deallocate{}(1831) BEGIN + // (op 1831) Deallocate 418 + // Deleting tag 418alias (-> 273) + // (op 1831) Deallocate 420 + // Deleting tag 420alias (-> 267) + // (op 39) Deallocate{}(1831) END + // (op 39) SetCoordinate(510) BEGIN + // (op 510) generate({}) + // (op 510) end: generate({}) + // (op 510) generate({511}) + // (op 510) LoadLDSTile{Value: Halfx2}(511) BEGIN + // (op 511) GEN: loadMacroTileWAVELDS OP 511 LDS 436 WaveTile 85 + // (op 511) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 511) Generate 2:U32 into nullptr + // tag 442: v[32:33] alias 442 -> 11 + // (op 511) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 511) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 511) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(449) BEGIN + // (op 449) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[32:33], v7 offset:57344 // (op 511) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 2. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 2122 (current 2102) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 510) LoadLDSTile{Value: Halfx2}(511) END + // (op 510) end: generate({511}) + // (op 39) SetCoordinate(510) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[26:27], a[0:15] // (op 449) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 12, so a waitcnt of 11 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[46:47], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 5 + // (op 39) Multiply(449) END + // (op 39) SetCoordinate(515) BEGIN + // (op 515) generate({}) + // (op 515) end: generate({}) + // (op 515) generate({516}) + // (op 515) LoadLDSTile{Value: Halfx2}(516) BEGIN + // (op 516) GEN: loadMacroTileWAVELDS OP 516 LDS 436 WaveTile 85 + // (op 516) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 516) Generate 2:U32 into nullptr + // tag 446: v[34:35] alias 446 -> 253 + // (op 516) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 516) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57360 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 516) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1833) BEGIN + // (op 1833) Deallocate 422 + // Deleting tag 422alias (-> 277) + // (op 1833) Deallocate 424 + // Deleting tag 424alias (-> 271) + // (op 39) Deallocate{}(1833) END +ds_read_b64 v[34:35], v7 offset:57360 // (op 516) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 2130 (current 2110) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 515) LoadLDSTile{Value: Halfx2}(516) END + // (op 515) end: generate({516}) + // (op 39) SetCoordinate(515) END + // (op 39) Multiply(454) BEGIN + // (op 454) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(520) BEGIN + // (op 520) generate({}) + // (op 520) end: generate({}) + // (op 520) generate({521}) + // (op 520) LoadLDSTile{Value: Halfx2}(521) BEGIN + // (op 521) GEN: loadMacroTileWAVELDS OP 521 LDS 436 WaveTile 85 + // (op 521) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 521) Generate 2:U32 into nullptr + // tag 450: v[36:37] alias 450 -> 257 + // (op 521) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 521) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57376 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 521) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[36:37], v7 offset:57376 // (op 521) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2131 (current 2111) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 520) LoadLDSTile{Value: Halfx2}(521) END + // (op 520) end: generate({521}) + // (op 39) SetCoordinate(520) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 6 +// VMEM: Expected complete at 2187 (current 2112) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(525) BEGIN + // (op 525) generate({}) + // (op 525) end: generate({}) + // (op 525) generate({526}) + // (op 525) LoadLDSTile{Value: Halfx2}(526) BEGIN + // (op 526) GEN: loadMacroTileWAVELDS OP 526 LDS 436 WaveTile 85 + // (op 526) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 526) Generate 2:U32 into nullptr + // tag 454: v[40:41] alias 454 -> 265 + // (op 526) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 526) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57392 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 526) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[40:41], v7 offset:57392 // (op 526) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected complete at 2133 (current 2113) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 525) LoadLDSTile{Value: Halfx2}(526) END + // (op 525) end: generate({526}) + // (op 39) SetCoordinate(525) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 4 + // (op 39) SetCoordinate(530) BEGIN + // (op 530) generate({}) + // (op 530) end: generate({}) + // (op 530) generate({531}) + // (op 530) LoadLDSTile{Value: Halfx2}(531) BEGIN + // (op 531) GEN: loadMacroTileWAVELDS OP 531 LDS 436 WaveTile 85 + // (op 531) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 531) Generate 2:U32 into nullptr + // tag 458: v**UNALLOCATED** + // (op 531) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 531) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57408 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 531) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 3 + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 2 +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 2 + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 1 +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 1 +// VMEM: Expected complete at 2192 (current 2117) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[28:29], a[0:15] // (op 454) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 14, so a waitcnt of 13 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[38:39], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // (op 39) Multiply(454) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 8 + // (op 39) Deallocate{}(1835) BEGIN + // (op 1835) Deallocate 426 + // Deleting tag 426alias (-> 261) + // (op 1835) Deallocate 428 + // Deleting tag 428alias (-> 275) + // (op 39) Deallocate{}(1835) END +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 7 + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 39) Multiply(459) BEGIN + // (op 459) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 6 +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 6 + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 5 +// Allocated : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 +ds_read_b64 v[72:73], v7 offset:57408 // (op 531) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected complete at 2143 (current 2123) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 530) LoadLDSTile{Value: Halfx2}(531) END + // (op 530) end: generate({531}) + // (op 39) SetCoordinate(530) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 4 +// VMEM: Expected complete at 2199 (current 2124) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(535) BEGIN + // (op 535) generate({}) + // (op 535) end: generate({}) + // (op 535) generate({536}) + // (op 535) LoadLDSTile{Value: Halfx2}(536) BEGIN + // (op 536) GEN: loadMacroTileWAVELDS OP 536 LDS 436 WaveTile 85 + // (op 536) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 536) Generate 2:U32 into nullptr + // tag 462: v**UNALLOCATED** + // (op 536) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 536) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57424 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 536) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 3 +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 2 + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 1 +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 1 + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[50:51], v[30:31], a[0:15] // (op 459) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 14, so a waitcnt of 13 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // (op 39) Multiply(459) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 8 +// VMEM: Expected complete at 2205 (current 2130) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) Deallocate{}(1841) BEGIN + // (op 1841) Deallocate 430 + // Freeing : 2 VGPRs (Value: Halfx2) (op 456): v50, v51 + + // Deleting tag 430 + // (op 1841) Deallocate 432 + // Deleting tag 432alias (-> 279) + // (op 39) Deallocate{}(1841) END +// Allocated : 2 VGPRs (Value: Halfx2) (op 536): v50, v51 +ds_read_b64 v[50:51], v7 offset:57424 // (op 536) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2151 (current 2131) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 535) LoadLDSTile{Value: Halfx2}(536) END + // (op 535) end: generate({536}) + // (op 39) SetCoordinate(535) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 6 + // (op 39) SetCoordinate(540) BEGIN + // (op 540) generate({}) + // (op 540) end: generate({}) + // (op 540) generate({541}) + // (op 540) LoadLDSTile{Value: Halfx2}(541) BEGIN + // (op 541) GEN: loadMacroTileWAVELDS OP 541 LDS 436 WaveTile 85 + // (op 541) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 541) Generate 2:U32 into nullptr + // tag 466: v**UNALLOCATED** + // (op 541) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 541) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57440 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 541) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 5 + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 4 +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 4 + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 3 +// Allocated : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 +ds_read_b64 v[74:75], v7 offset:57440 // (op 541) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 3 +// DSMEM: Expected complete at 2155 (current 2135) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 540) LoadLDSTile{Value: Halfx2}(541) END + // (op 540) end: generate({541}) + // (op 39) SetCoordinate(540) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 2 +// VMEM: Expected stall of 52. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 2263 (current 2188) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(545) BEGIN + // (op 545) generate({}) + // (op 545) end: generate({}) + // (op 545) generate({546}) + // (op 545) LoadLDSTile{Value: Halfx2}(546) BEGIN + // (op 546) GEN: loadMacroTileWAVELDS OP 546 LDS 436 WaveTile 85 + // (op 546) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 546) Generate 2:U32 into nullptr + // tag 470: v**UNALLOCATED** + // (op 546) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57344 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 546) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v7 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 57456 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 546) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// Allocated : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 +ds_read_b64 v[76:77], v7 offset:57456 // (op 546) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// DSMEM: Expected complete at 2212 (current 2192) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 545) LoadLDSTile{Value: Halfx2}(546) END + // (op 545) end: generate({546}) + // (op 39) SetCoordinate(545) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected complete at 2268 (current 2193) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) Deallocate{}(1857) BEGIN + // (op 1857) Deallocate 618 + // Deleting tag 618 + // (op 39) Deallocate{}(1857) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 2275 (current 2200) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // (op 1008) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1008) Omitting copy to same register: v[66:67], v[66:67] + // (op 1008) reg expression + // (op 1008) Omitting copy to same register: v48, v48 + // (op 1008) reg expression + // (op 1008) Add(v[66:67]:U64, v48:R)U64 + // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1008) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1008) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1008) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1008) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 + + // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1008) Omitting copy to same register: m0, m0 + // (op 1008) reg expression + // (op 1008) Add(m0:U32, 1024:U32)U32 + // (op 1008) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1008) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1008) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 2281 (current 2206) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1008): v48, v49 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1008): v66, v67 + + // Freeing : 1 SGPR (Value: UInt32) (op 1008): s45 + + // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) END + // (op 629) Deallocate{}(1889) BEGIN + // (op 1889) Deallocate 598 + // Deleting tag 598 + // (op 629) Deallocate{}(1889) END + // (op 629) end: generate({1008}) + // (op 39) SetCoordinate(629) END + // (op 39) Barrier(1749) BEGIN +s_barrier // (op 1749) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 39) Barrier(1749) END + // (op 39) SetCoordinate(624) BEGIN + // (op 624) generate({}) + // (op 624) end: generate({}) + // (op 624) generate({1003}) + // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) BEGIN + // (op 1003) GEN: LoadTileDirect2LDS + // (op 1003) GEN: loadMacroTileDirect2LDS OP 1003 LDS 396 MacroTile 394 + // (op 1003) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1003) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 1003) Omitting copy to same register: s[18:19], s[18:19] + // (op 1003) reg expression + // (op 1003) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1003) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1003) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Omitting copy to same register: s[46:47], s[46:47] + // (op 1003) convert + // (op 1003) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1003) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1003) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1003): v48, v49 +v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 + + // (op 1003) Generate 2:U64 into nullptr + // (op 1003) Generate 1024:U32 into nullptr + // (op 1003) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 40960 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[48:49] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1003): v66, v67 +v_mov_b64 v[66:67], v[68:69] // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Generate Add(40960:U32, {DataFlowTag584: s40:U32})U32 into nullptr + // (op 1003) Omitting copy to same register: s40, s40 + // (op 1003) reg expression + // (op 1003) Add(40960:U32, {DataFlowTag584: s40:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1003): s45 +s_add_u32 s45, 40960, s40 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1003) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 1003) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 768 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 +s_mov_b32 s46, 768 // (op 1003) call() +// 768 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 50. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2339 (current 2264) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2344 (current 2269) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2351 (current 2276) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2357 (current 2282) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 54. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2415 (current 2340) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2420 (current 2345) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2427 (current 2352) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // (op 1003) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1003) Omitting copy to same register: v[66:67], v[66:67] + // (op 1003) reg expression + // (op 1003) Omitting copy to same register: v48, v48 + // (op 1003) reg expression + // (op 1003) Add(v[66:67]:U64, v48:R)U64 + // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1003) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1003) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1003) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1003) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 + + // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1003) Omitting copy to same register: m0, m0 + // (op 1003) reg expression + // (op 1003) Add(m0:U32, 1024:U32)U32 + // (op 1003) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1003) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 1003) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +buffer_load_dword v66, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2433 (current 2358) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1003): v48, v49 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1003): v66, v67 + + // Freeing : 1 SGPR (Value: UInt32) (op 1003): s45 + + // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) END + // (op 624) Deallocate{}(1887) BEGIN + // (op 1887) Deallocate 586 + // Deleting tag 586 + // (op 624) Deallocate{}(1887) END + // (op 624) end: generate({1003}) + // (op 39) SetCoordinate(624) END + // (op 39) NOP(1020) BEGIN + // (op 1020) generate({}) + // (op 1020) end: generate({}) + // (op 39) NOP(1020) END + // (op 39) NOP(1015) BEGIN + // (op 1015) generate({}) + // (op 1015) end: generate({}) + // (op 39) NOP(1015) END + // (op 39) NOP(801) BEGIN + // (op 801) generate({}) + // (op 801) end: generate({}) + // (op 39) NOP(801) END + // (op 39) Multiply(514) BEGIN + // (op 514) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) Barrier(937) BEGIN + // (op 39) Barrier(1758) BEGIN +s_waitcnt vmcnt(32) +s_barrier // (op 937) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 15 and the queue size is 48, so a waitcnt of 32 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 39) Barrier(937) END +s_waitcnt lgkmcnt(7) +v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[16:17], a[0:15] // (op 514) WaitCnt Needed: Intersects with registers in 'DSQueue', at 8 and the queue size is 16, so a waitcnt of 7 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[64:65], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[62:63], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[60:61], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[58:59], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[56:57], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[54:55], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[70:71], LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // (op 39) Multiply(514) END +s_barrier // (op 1758) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 8 +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 39) Barrier(1758) END + // (op 39) Deallocate{}(1843) BEGIN + // (op 1843) Deallocate 442 + // Deleting tag 442alias (-> 11) + // (op 1843) Deallocate 444 + // Deleting tag 444alias (-> 19) + // (op 39) Deallocate{}(1843) END + // (op 39) SetCoordinate(643) BEGIN + // (op 643) generate({}) + // (op 643) end: generate({}) + // (op 643) generate({1018}) + // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) BEGIN + // (op 1018) GEN: LoadTileDirect2LDS + // (op 1018) GEN: loadMacroTileDirect2LDS OP 1018 LDS 440 MacroTile 438 + // (op 1018) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1018) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) + // (op 1018) Omitting copy to same register: s[22:23], s[22:23] + // (op 1018) reg expression + // (op 1018) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 1018) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1018) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 3) + // (op 39) SetCoordinate(52) BEGIN + // (op 52) generate({}) + // (op 52) end: generate({}) + // (op 52) generate({54}) + // (op 52) LoadLDSTile{Value: Halfx2}(54) BEGIN + // (op 54) GEN: loadMacroTileWAVELDS OP 54 LDS 21 WaveTile 145 + // (op 54) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 54) Generate 2:U32 into nullptr + // (op 54) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 54) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[16:17] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 54) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(519) BEGIN + // (op 519) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[16:17], v4 // (op 54) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2384 (current 2364) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 52) LoadLDSTile{Value: Halfx2}(54) END + // (op 52) end: generate({54}) + // (op 39) SetCoordinate(52) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 +s_lshl_b64 s[46:47], s[22:23], 3 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 1018) Omitting copy to same register: s[46:47], s[46:47] + // (op 1018) convert + // (op 1018) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1018) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1018) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 39) SetCoordinate(62) BEGIN + // (op 62) generate({}) + // (op 62) end: generate({}) + // (op 62) generate({64}) + // (op 62) LoadLDSTile{Value: Halfx2}(64) BEGIN + // (op 64) GEN: loadMacroTileWAVELDS OP 64 LDS 21 WaveTile 145 + // (op 64) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 64) Generate 2:U32 into nullptr + // (op 64) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[14:15] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 64) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[14:15] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 64) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[14:15], v4 offset:16 // (op 64) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected complete at 2386 (current 2366) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 62) LoadLDSTile{Value: Halfx2}(64) END + // (op 62) end: generate({64}) + // (op 39) SetCoordinate(62) END +// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1018): v48, v49 +v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 4 + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 + + // (op 1018) Generate 2:U64 into nullptr + // (op 1018) Generate 1024:U32 into nullptr + // (op 1018) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 49152 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[48:49] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // (op 39) SetCoordinate(71) BEGIN + // (op 71) generate({}) + // (op 71) end: generate({}) + // (op 71) generate({73}) + // (op 71) LoadLDSTile{Value: Halfx2}(73) BEGIN + // (op 73) GEN: loadMacroTileWAVELDS OP 73 LDS 21 WaveTile 145 + // (op 73) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 73) Generate 2:U32 into nullptr + // (op 73) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 73) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[20:21] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 73) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[20:21], v4 offset:32 // (op 73) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 3 +// DSMEM: Expected complete at 2388 (current 2368) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 71) LoadLDSTile{Value: Halfx2}(73) END + // (op 71) end: generate({73}) + // (op 39) SetCoordinate(71) END +// Allocated : 2 VGPRs (Value: UInt64) (op 1018): v66, v67 +v_mov_b64 v[66:67], v[52:53] // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 2 + // (op 1018) Generate Add(49152:U32, {DataFlowTag620: s43:U32})U32 into nullptr + // (op 1018) Omitting copy to same register: s43, s43 + // (op 1018) reg expression + // (op 1018) Add(49152:U32, {DataFlowTag620: s43:U32})U32 + // (op 39) SetCoordinate(80) BEGIN + // (op 80) generate({}) + // (op 80) end: generate({}) + // (op 80) generate({82}) + // (op 80) LoadLDSTile{Value: Halfx2}(82) BEGIN + // (op 82) GEN: loadMacroTileWAVELDS OP 82 LDS 21 WaveTile 145 + // (op 82) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 82) Generate 2:U32 into nullptr + // (op 82) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 82) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[22:23] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 82) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[22:23], v4 offset:48 // (op 82) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 1 +// DSMEM: Expected complete at 2390 (current 2370) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 80) LoadLDSTile{Value: Halfx2}(82) END + // (op 80) end: generate({82}) + // (op 39) SetCoordinate(80) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[64:65], a[0:15] // (op 519) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 11, so a waitcnt of 10 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[34:35], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // (op 39) Multiply(519) END + // (op 39) SetCoordinate(89) BEGIN + // (op 89) generate({}) + // (op 89) end: generate({}) + // (op 89) generate({91}) + // (op 89) LoadLDSTile{Value: Halfx2}(91) BEGIN + // (op 91) GEN: loadMacroTileWAVELDS OP 91 LDS 21 WaveTile 145 + // (op 91) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 91) Generate 2:U32 into nullptr + // (op 91) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 91) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[24:25] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 91) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1845) BEGIN + // (op 1845) Deallocate 446 + // Deleting tag 446alias (-> 253) + // (op 1845) Deallocate 448 + // Freeing : 2 VGPRs (Value: Halfx2) (op 518): v64, v65 + + // Deleting tag 448 + // (op 39) Deallocate{}(1845) END +// Allocated : 1 SGPR (Value: UInt32) (op 1018): s45 +s_add_u32 s45, 49152, s43 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 8 + // (op 1018) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1018) Generate s45:U32 into M0 Value: UInt32 x 1: m0 + // (op 39) Multiply(524) BEGIN + // (op 524) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_mov_b32 m0, s45 // (op 1018) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 7 + // (op 1018) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 896 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 +s_mov_b32 s46, 896 // (op 1018) call() +// 896 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 +s_waitcnt lgkmcnt(9) +v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[62:63], a[0:15] // (op 524) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 10, so a waitcnt of 9 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[36:37], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 5 + // (op 39) Multiply(524) END +ds_read_b64 v[24:25], v4 offset:64 // (op 91) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 +// DSMEM: Expected complete at 2405 (current 2385) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 89) LoadLDSTile{Value: Halfx2}(91) END + // (op 89) end: generate({91}) + // (op 39) SetCoordinate(89) END + // (op 39) Deallocate{}(1847) BEGIN + // (op 1847) Deallocate 450 + // Deleting tag 450alias (-> 257) + // (op 1847) Deallocate 452 + // Freeing : 2 VGPRs (Value: Halfx2) (op 523): v62, v63 + + // Deleting tag 452 + // (op 39) Deallocate{}(1847) END + // (op 39) SetCoordinate(98) BEGIN + // (op 98) generate({}) + // (op 98) end: generate({}) + // (op 98) generate({100}) + // (op 98) LoadLDSTile{Value: Halfx2}(100) BEGIN + // (op 100) GEN: loadMacroTileWAVELDS OP 100 LDS 21 WaveTile 145 + // (op 100) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 100) Generate 2:U32 into nullptr + // (op 100) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 100) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[26:27] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 100) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Multiply(529) BEGIN + // (op 529) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +ds_read_b64 v[26:27], v4 offset:80 // (op 100) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 5 +// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 +// DSMEM: Expected complete at 2407 (current 2387) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 98) LoadLDSTile{Value: Halfx2}(100) END + // (op 98) end: generate({100}) + // (op 39) SetCoordinate(98) END +s_waitcnt lgkmcnt(10) +v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[60:61], a[0:15] // (op 529) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 11, so a waitcnt of 10 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[40:41], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 3 + // (op 39) Multiply(529) END + // (op 39) SetCoordinate(107) BEGIN + // (op 107) generate({}) + // (op 107) end: generate({}) + // (op 107) generate({109}) + // (op 107) LoadLDSTile{Value: Halfx2}(109) BEGIN + // (op 109) GEN: loadMacroTileWAVELDS OP 109 LDS 21 WaveTile 145 + // (op 109) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 109) Generate 2:U32 into nullptr + // (op 109) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 109) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[28:29] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 109) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1849) BEGIN + // (op 1849) Deallocate 454 + // Deleting tag 454alias (-> 265) + // (op 1849) Deallocate 456 + // Freeing : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 + + // Deleting tag 456 + // (op 39) Deallocate{}(1849) END +ds_read_b64 v[28:29], v4 offset:96 // (op 109) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected complete at 2413 (current 2393) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 107) LoadLDSTile{Value: Halfx2}(109) END + // (op 107) end: generate({109}) + // (op 39) SetCoordinate(107) END + // (op 39) Multiply(534) BEGIN + // (op 534) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(116) BEGIN + // (op 116) generate({}) + // (op 116) end: generate({}) + // (op 116) generate({118}) + // (op 116) LoadLDSTile{Value: Halfx2}(118) BEGIN + // (op 118) GEN: loadMacroTileWAVELDS OP 118 LDS 21 WaveTile 145 + // (op 118) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 118) Generate 2:U32 into nullptr + // (op 118) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 118) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[30:31] + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 118) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[30:31], v4 offset:112 // (op 118) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 2414 (current 2394) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 116) LoadLDSTile{Value: Halfx2}(118) END + // (op 116) end: generate({118}) + // (op 39) SetCoordinate(116) END +s_waitcnt lgkmcnt(11) +v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[58:59], a[0:15] // (op 534) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 12, so a waitcnt of 11 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[72:73], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 39) Multiply(534) END + // (op 39) SetCoordinate(47) BEGIN + // (op 47) generate({}) + // (op 47) end: generate({}) + // (op 47) generate({49}) + // (op 47) LoadLDSTile{Value: Halfx2}(49) BEGIN + // (op 49) GEN: loadMacroTileWAVELDS OP 49 LDS 13 WaveTile 85 + // (op 49) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 49) Generate 2:U32 into nullptr + // (op 49) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 49) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[32:33] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 49) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1851) BEGIN + // (op 1851) Deallocate 458 + // Freeing : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 + + // Deleting tag 458 + // (op 1851) Deallocate 460 + // Freeing : 2 VGPRs (Value: Halfx2) (op 533): v58, v59 + + // Deleting tag 460 + // (op 39) Deallocate{}(1851) END +ds_read_b64 v[32:33], v0 offset:8192 // (op 49) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 +// DSMEM: Expected complete at 2426 (current 2406) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 47) LoadLDSTile{Value: Halfx2}(49) END + // (op 47) end: generate({49}) + // (op 39) SetCoordinate(47) END + // (op 39) Multiply(539) BEGIN + // (op 539) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(58) BEGIN + // (op 58) generate({}) + // (op 58) end: generate({}) + // (op 58) generate({60}) + // (op 58) LoadLDSTile{Value: Halfx2}(60) BEGIN + // (op 60) GEN: loadMacroTileWAVELDS OP 60 LDS 13 WaveTile 85 + // (op 60) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 60) Generate 2:U32 into nullptr + // (op 60) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 60) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[34:35] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 60) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[34:35], v0 offset:8208 // (op 60) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 4 +// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 2428 (current 2408) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 58) LoadLDSTile{Value: Halfx2}(60) END + // (op 58) end: generate({60}) + // (op 39) SetCoordinate(58) END +s_waitcnt lgkmcnt(12) +v_mfma_f32_32x32x8f16 a[0:15], v[50:51], v[56:57], a[0:15] // (op 539) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 13, so a waitcnt of 12 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[50:51], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 2 + // (op 39) Multiply(539) END + // (op 39) SetCoordinate(67) BEGIN + // (op 67) generate({}) + // (op 67) end: generate({}) + // (op 67) generate({69}) + // (op 67) LoadLDSTile{Value: Halfx2}(69) BEGIN + // (op 69) GEN: loadMacroTileWAVELDS OP 69 LDS 13 WaveTile 85 + // (op 69) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 69) Generate 2:U32 into nullptr + // (op 69) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 69) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[36:37] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 69) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + + // (op 39) Deallocate{}(1853) BEGIN + // (op 1853) Deallocate 462 + // Freeing : 2 VGPRs (Value: Halfx2) (op 536): v50, v51 + + // Deleting tag 462 + // (op 1853) Deallocate 464 + // Freeing : 2 VGPRs (Value: Halfx2) (op 538): v56, v57 + + // Deleting tag 464 + // (op 39) Deallocate{}(1853) END +ds_read_b64 v[36:37], v0 offset:8224 // (op 69) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 8 +// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 +// DSMEM: Expected complete at 2434 (current 2414) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 67) LoadLDSTile{Value: Halfx2}(69) END + // (op 67) end: generate({69}) + // (op 39) SetCoordinate(67) END + // (op 39) Multiply(544) BEGIN + // (op 544) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] + // (op 39) SetCoordinate(76) BEGIN + // (op 76) generate({}) + // (op 76) end: generate({}) + // (op 76) generate({78}) + // (op 76) LoadLDSTile{Value: Halfx2}(78) BEGIN + // (op 78) GEN: loadMacroTileWAVELDS OP 78 LDS 13 WaveTile 85 + // (op 78) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 78) Generate 2:U32 into nullptr + // (op 78) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 78) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[38:39] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 78) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[38:39], v0 offset:8240 // (op 78) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 6 +// DSMEM: Expected complete at 2435 (current 2415) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 76) LoadLDSTile{Value: Halfx2}(78) END + // (op 76) end: generate({78}) + // (op 39) SetCoordinate(76) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 5 +// VMEM: Expected complete at 2491 (current 2416) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(85) BEGIN + // (op 85) generate({}) + // (op 85) end: generate({}) + // (op 85) generate({87}) + // (op 85) LoadLDSTile{Value: Halfx2}(87) BEGIN + // (op 87) GEN: loadMacroTileWAVELDS OP 87 LDS 13 WaveTile 85 + // (op 87) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 87) Generate 2:U32 into nullptr + // (op 87) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 87) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[40:41] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 87) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 4 +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 3 + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 2 +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 2 + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 1 +s_waitcnt lgkmcnt(13) +v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[54:55], a[0:15] // (op 544) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 14, so a waitcnt of 13 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[74:75], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 1 + // (op 39) Multiply(544) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 8 +// VMEM: Expected complete at 2498 (current 2423) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) Deallocate{}(1855) BEGIN + // (op 1855) Deallocate 466 + // Freeing : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 + + // Deleting tag 466 + // (op 1855) Deallocate 468 + // Freeing : 2 VGPRs (Value: Halfx2) (op 543): v54, v55 + + // Deleting tag 468 + // (op 39) Deallocate{}(1855) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 + // (op 39) Multiply(549) BEGIN + // (op 549) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 6 + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 5 +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 5 + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 4 +ds_read_b64 v[40:41], v0 offset:8256 // (op 87) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 4 +// DSMEM: Expected complete at 2447 (current 2427) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 85) LoadLDSTile{Value: Halfx2}(87) END + // (op 85) end: generate({87}) + // (op 39) SetCoordinate(85) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 3 +// VMEM: Expected complete at 2503 (current 2428) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(94) BEGIN + // (op 94) generate({}) + // (op 94) end: generate({}) + // (op 94) generate({96}) + // (op 94) LoadLDSTile{Value: Halfx2}(96) BEGIN + // (op 96) GEN: loadMacroTileWAVELDS OP 96 LDS 13 WaveTile 85 + // (op 96) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 96) Generate 2:U32 into nullptr + // (op 96) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 96) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[42:43] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 96) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[42:43], v0 offset:8272 // (op 96) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 2 +// DSMEM: Expected complete at 2449 (current 2429) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 94) LoadLDSTile{Value: Halfx2}(96) END + // (op 94) end: generate({96}) + // (op 39) SetCoordinate(94) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 1 + // (op 39) SetCoordinate(103) BEGIN + // (op 103) generate({}) + // (op 103) end: generate({}) + // (op 103) generate({105}) + // (op 103) LoadLDSTile{Value: Halfx2}(105) BEGIN + // (op 105) GEN: loadMacroTileWAVELDS OP 105 LDS 13 WaveTile 85 + // (op 105) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 105) Generate 2:U32 into nullptr + // (op 105) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 105) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[44:45] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 105) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +s_waitcnt lgkmcnt(14) +v_mfma_f32_32x32x8f16 a[0:15], v[76:77], v[70:71], a[0:15] // (op 549) WaitCnt Needed: Intersects with registers in 'DSQueue', at 0 and the queue size is 15, so a waitcnt of 14 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[76:77], LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Multiply(549) END +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 8 + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 39) Deallocate{}(1861) BEGIN + // (op 1861) Deallocate 470 + // Freeing : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 + + // Deleting tag 470 + // (op 1861) Deallocate 472 + // Freeing : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 + + // Deleting tag 472 + // (op 39) Deallocate{}(1861) END + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 6 +ds_read_b64 v[44:45], v0 offset:8288 // (op 105) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 6 +// DSMEM: Expected complete at 2455 (current 2435) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 103) LoadLDSTile{Value: Halfx2}(105) END + // (op 103) end: generate({105}) + // (op 39) SetCoordinate(103) END +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 5 +// VMEM: Expected complete at 2511 (current 2436) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) + // (op 39) SetCoordinate(112) BEGIN + // (op 112) generate({}) + // (op 112) end: generate({}) + // (op 112) generate({114}) + // (op 112) LoadLDSTile{Value: Halfx2}(114) BEGIN + // (op 114) GEN: loadMacroTileWAVELDS OP 114 LDS 13 WaveTile 85 + // (op 114) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 114) Generate 2:U32 into nullptr + // (op 114) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 114) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: v[46:47] + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 114) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +ds_read_b64 v[46:47], v0 offset:8304 // (op 114) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 4 +// DSMEM: Expected complete at 2457 (current 2437) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 112) LoadLDSTile{Value: Halfx2}(114) END + // (op 112) end: generate({114}) + // (op 39) SetCoordinate(112) END +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 3 +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 2 + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 1 +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 1 + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 +// VMEM: Expected complete at 2567 (current 2492) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 +// VMEM: Expected complete at 2574 (current 2499) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 34, Inc: 4 +// VMEM: Expected complete at 2579 (current 2504) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // (op 1018) Generate Add(v[66:67]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[66:67] + // (op 1018) Omitting copy to same register: v[66:67], v[66:67] + // (op 1018) reg expression + // (op 1018) Omitting copy to same register: v48, v48 + // (op 1018) reg expression + // (op 1018) Add(v[66:67]:U64, v48:R)U64 + // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[66:67]) = + // (op 1018) lhs (VGPR Value: UInt64 x 1: v[66:67]) + // (op 1018) rhs (VGPR Value: Raw32 x 1: v48) +// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 +v_add_co_u32 v66, s[48:49], v66, v48 // (op 1018) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v67, s[48:49], 0, v67, s[48:49] // (op 1018) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 + + // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1018) Omitting copy to same register: m0, m0 + // (op 1018) reg expression + // (op 1018) Add(m0:U32, 1024:U32)U32 + // (op 1018) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1018) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1018) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v66, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 4. CBNW: 35, Inc: 4 +// VMEM: Expected complete at 2587 (current 2512) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 + + // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1018): v48, v49 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1018): v66, v67 + + // Freeing : 1 SGPR (Value: UInt32) (op 1018): s45 + + // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) END + // (op 643) Deallocate{}(1893) BEGIN + // (op 1893) Deallocate 622 + // Deleting tag 622 + // (op 643) Deallocate{}(1893) END + // (op 643) end: generate({1018}) + // (op 39) SetCoordinate(643) END + // (op 39) Deallocate{}(1865) BEGIN + // (op 1865) Deallocate 508 + // Freeing Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 + + // Deleting tag 508 + // (op 1865) Deallocate 510 + // Deleting tag 510 + // (op 39) Deallocate{}(1865) END + // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) BEGIN + // (op 1157) Assign dim(506) = Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 + // (op 1157) Generate Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 into DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19] + // (op 1157) Omitting copy to same register: v[18:19], v[18:19] + // (op 1157) reg expression + // (op 1157) Add({DataFlowTag506: v[18:19]:U64}, 512:U64)U64 + // (op 1157) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = + // (op 1157) lhs (DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1157) rhs (Literal Value: UInt64 x 0: 512) + // (op 39) Barrier(1755) BEGIN +s_barrier // (op 1755) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 39) Barrier(1755) END +v_add_co_u32 v18, vcc, 512, v18 // (op 1157) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) SetCoordinate(638) BEGIN + // (op 638) generate({}) + // (op 638) end: generate({}) + // (op 638) generate({1013}) + // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) BEGIN + // (op 1013) GEN: LoadTileDirect2LDS + // (op 1013) GEN: loadMacroTileDirect2LDS OP 1013 LDS 436 MacroTile 434 + // (op 1013) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 1013) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) + // (op 1013) Omitting copy to same register: s[18:19], s[18:19] + // (op 1013) reg expression + // (op 1013) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 1013) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1013) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 3) +v_addc_co_u32 v19, vcc, 0, v19, vcc // (op 1157) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) END +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 +s_lshl_b64 s[46:47], s[18:19], 3 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Omitting copy to same register: s[46:47], s[46:47] + // (op 1013) convert + // (op 1013) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 + // (op 1013) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1013) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) + // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1013): v66, v67 +v_lshlrev_b64 v[66:67], 1, s[46:47] // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 + + // (op 1013) Generate 2:U64 into nullptr + // (op 1013) Generate 1024:U32 into nullptr + // (op 1013) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 57344 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[66:67] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + +// Allocated : 2 VGPRs (Value: UInt64) (op 1013): v64, v65 +v_mov_b64 v[64:65], v[68:69] // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Generate Add(57344:U32, {DataFlowTag608: s42:U32})U32 into nullptr + // (op 1013) Omitting copy to same register: s42, s42 + // (op 1013) reg expression + // (op 1013) Add(57344:U32, {DataFlowTag608: s42:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1013): s45 +s_add_u32 s45, 57344, s42 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[66:67]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 1013) Generate s45:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s45 // (op 1013) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) +// 896 is not a supported value! +// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 +s_mov_b32 s46, 896 // (op 1013) call() +// 896 is not a supported value! +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 46. CBNW: 36, Inc: 4 +// VMEM: Expected complete at 2643 (current 2568) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 +// VMEM: Expected complete at 2650 (current 2575) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 +// VMEM: Expected complete at 2655 (current 2580) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 4. CBNW: 39, Inc: 4 +// VMEM: Expected complete at 2663 (current 2588) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 +// VMEM: Expected complete at 2719 (current 2644) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 +// VMEM: Expected complete at 2726 (current 2651) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 +// VMEM: Expected complete at 2731 (current 2656) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // (op 1013) Generate Add(v[64:65]:U64, v66:R)U64 into VGPR Value: UInt64 x 1: v[64:65] + // (op 1013) Omitting copy to same register: v[64:65], v[64:65] + // (op 1013) reg expression + // (op 1013) Omitting copy to same register: v66, v66 + // (op 1013) reg expression + // (op 1013) Add(v[64:65]:U64, v66:R)U64 + // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[64:65]) = + // (op 1013) lhs (VGPR Value: UInt64 x 1: v[64:65]) + // (op 1013) rhs (VGPR Value: Raw32 x 1: v66) +// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 +v_add_co_u32 v64, s[48:49], v64, v66 // (op 1013) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v65, s[48:49], 0, v65, s[48:49] // (op 1013) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 + + // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 1013) Omitting copy to same register: m0, m0 + // (op 1013) reg expression + // (op 1013) Add(m0:U32, 1024:U32)U32 + // (op 1013) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 1013) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 1013) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v64, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 4. CBNW: 43, Inc: 4 +// VMEM: Expected complete at 2739 (current 2664) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) + // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 + + // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1013): v66, v67 + + // Freeing : 2 VGPRs (Value: UInt64) (op 1013): v64, v65 + + // Freeing : 1 SGPR (Value: UInt32) (op 1013): s45 + + // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) END + // (op 638) Deallocate{}(1891) BEGIN + // (op 1891) Deallocate 610 + // Deleting tag 610 + // (op 638) Deallocate{}(1891) END + // (op 638) end: generate({1013}) + // (op 39) SetCoordinate(638) END + // (op 39) Deallocate{}(1863) BEGIN + // (op 1863) Deallocate 491 + // Deleting tag 491 + // (op 1863) Deallocate 489 + // Freeing Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 + + // Deleting tag 489 + // (op 39) Deallocate{}(1863) END + // (op 39) NOP(978) BEGIN + // (op 978) generate({}) + // (op 978) end: generate({}) + // (op 39) NOP(978) END + // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) BEGIN + // (op 1093) Assign dim(487) = Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 + // (op 1093) Generate Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: v[12:13] + // (op 1093) Omitting copy to same register: v[12:13], v[12:13] + // (op 1093) reg expression + // (op 1093) Add({DataFlowTag487: v[12:13]:U64}, 512:U64)U64 + // (op 1093) Add: dest (VGPR Value: UInt64 x 1: v[12:13]) = + // (op 1093) lhs (DataFlowTag487: VGPR Value: UInt64 x 1: v[12:13]) + // (op 1093) rhs (Literal Value: UInt64 x 0: 512) + // (op 39) NOP(973) BEGIN + // (op 973) generate({}) + // (op 973) end: generate({}) + // (op 39) NOP(973) END +v_add_co_u32 v12, vcc, 512, v12 // (op 1093) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) NOP(802) BEGIN + // (op 802) generate({}) + // (op 802) end: generate({}) + // (op 39) NOP(802) END +v_addc_co_u32 v13, vcc, 0, v13, vcc // (op 1093) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) END + // (op 39) end: generate({41, 57, 811, 1733}) + // (op 39) For Loop Increment + // (op 39) generate({}) + // (op 39) end: generate({}) + // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoop_39 if true) + // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc + // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL + // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 + // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 +s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 +s_mov_b32 s45, s46 // (op 39) convert +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 + +// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 +s_and_b32 s46, s45, 4294967292 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 + +s_cmp_lt_u32 s44, s46 // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[16:17], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoop_39 // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoop_39 if true) +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 16384, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 24576, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 32768, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 40960, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 49152, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// ------Dst: {LDS:(Offset: 57344, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } +// ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoop_39: + // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } +s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch + // (op 39) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 16384, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 24576, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 32768, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 40960, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 49152, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // ------Dst: {LDS:(Offset: 57344, Size: 8192), } + // --Queue: DSQueue + // ----Needs Wait Zero: False + // ----Type In Queue : DSQueue + // ----Registers : + // ------Dst: {v[14:15], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[20:21], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[22:23], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[24:25], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[26:27], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[28:29], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[30:31], LDS:(Offset: 0, Size: 8192), } + // ------Dst: {v[32:33], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[34:35], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[36:37], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[38:39], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[40:41], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[42:43], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[44:45], LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {v[46:47], LDS:(Offset: 8192, Size: 8192), } + // (op 39) Unlock For Loop + // Unlock None + // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) END + // (op 1074) Deallocate{}(1765) BEGIN + // (op 1765) Deallocate 623 + // Deleting tag 623 + // (op 1765) Deallocate 621 + // Deleting tag 621 + // (op 1765) Deallocate 620 + // Freeing DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 + + // Deleting tag 620 + // (op 1765) Deallocate 609 + // Deleting tag 609 + // (op 1765) Deallocate 6 + // Deleting tag 6 + // (op 1765) Deallocate 611 + // Deleting tag 611 + // (op 1765) Deallocate 354 + // Deleting tag 354 + // (op 1765) Deallocate 537 + // Deleting tag 537 + // (op 1765) Deallocate 265 + // Freeing : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 + + // Deleting tag 265 + // (op 1765) Deallocate 535 + // Deleting tag 535 + // (op 1765) Deallocate 534 + // Freeing DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s0 + + // Deleting tag 534 + // (op 1765) Deallocate 277 + // Freeing : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 + + // Deleting tag 277 + // (op 1765) Deallocate 261 + // Freeing : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 + + // Deleting tag 261 + // (op 1765) Deallocate 518 + // Freeing DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s1 + + // Deleting tag 518 + // (op 1765) Deallocate 438 + // Deleting tag 438 + // (op 1765) Deallocate 358 + // Deleting tag 358 + // (op 1765) Deallocate 271 + // Freeing : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 + + // Deleting tag 271 + // (op 1765) Deallocate 7 + // Deleting tag 7 + // (op 1765) Deallocate 521 + // Deleting tag 521 + // (op 1765) Deallocate 394 + // Deleting tag 394 + // (op 1765) Deallocate 572 + // Freeing DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s16 + + // Deleting tag 572 + // (op 1765) Deallocate 360 + // Deleting tag 360 + // (op 1765) Deallocate 490 + // Deleting tag 490 + // (op 1765) Deallocate 587 + // Deleting tag 587 + // (op 1765) Deallocate 511 + // Deleting tag 511 + // (op 1765) Deallocate 257 + // Freeing : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 + + // Deleting tag 257 + // (op 1765) Deallocate 279 + // Freeing : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 + + // Deleting tag 279 + // (op 1765) Deallocate 263 + // Freeing : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 + + // Deleting tag 263 + // (op 1765) Deallocate 253 + // Freeing : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 + + // Deleting tag 253 + // (op 1765) Deallocate 507 + // Deleting tag 507 + // (op 1765) Deallocate 273 + // Freeing : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 + + // Deleting tag 273 + // (op 1765) Deallocate 400 + // Deleting tag 400 + // (op 1765) Deallocate 267 + // Freeing : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 + + // Deleting tag 267 + // (op 1765) Deallocate 259 + // Freeing : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 + + // Deleting tag 259 + // (op 1765) Deallocate 255 + // Freeing : 2 VGPRs (Value: Halfx2) (op 761): v14, v15 + + // Deleting tag 255 + // (op 1765) Deallocate 519 + // Deleting tag 519 + // (op 1765) Deallocate 11 + // Freeing : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 + + // Deleting tag 11 + // (op 1765) Deallocate 398 + // Deleting tag 398 + // (op 1765) Deallocate 436 + // Deleting tag 436 + // (op 1765) Deallocate 434 + // Deleting tag 434 + // (op 1765) Deallocate 269 + // Freeing : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 + + // Deleting tag 269 + // (op 1765) Deallocate 396 + // Deleting tag 396 + // (op 1765) Deallocate 440 + // Deleting tag 440 + // (op 1765) Deallocate 487 + // Freeing DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v12, v13 + + // Deleting tag 487 + // (op 1765) Deallocate 488 + // Deleting tag 488 + // (op 1765) Deallocate 275 + // Freeing : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 + + // Deleting tag 275 + // (op 1765) Deallocate 356 + // Deleting tag 356 + // (op 1765) Deallocate 509 + // Deleting tag 509 + // (op 1765) Deallocate 492 + // Deleting tag 492 + // (op 1765) Deallocate 19 + // Freeing : 2 VGPRs (Value: Halfx2) (op 758): v16, v17 + + // Deleting tag 19 + // (op 1765) Deallocate 560 + // Freeing DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s17 + + // Deleting tag 560 + // (op 1765) Deallocate 245 + // Freeing DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 + + // Deleting tag 245 + // (op 1765) Deallocate 506 + // Freeing DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 + + // Deleting tag 506 + // (op 1765) Deallocate 561 + // Deleting tag 561 + // (op 1765) Deallocate 563 + // Deleting tag 563 + // (op 1765) Deallocate 573 + // Deleting tag 573 + // (op 1765) Deallocate 575 + // Deleting tag 575 + // (op 1765) Deallocate 584 + // Freeing DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 + + // Deleting tag 584 + // (op 1765) Deallocate 585 + // Deleting tag 585 + // (op 1765) Deallocate 596 + // Freeing DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 + + // Deleting tag 596 + // (op 1765) Deallocate 597 + // Deleting tag 597 + // (op 1765) Deallocate 599 + // Deleting tag 599 + // (op 1765) Deallocate 608 + // Freeing DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 + + // Deleting tag 608 + // (op 1074) Deallocate{}(1765) END + // (op 1074) Barrier(1767) BEGIN +s_barrier // (op 1767) + // (op 1074) Barrier(1767) END + // (op 1074) end: generate({1069}) + // (op 1074) Unlock Scope 1074 + // Unlock None + // (op 670) Scope(1074) END + // (op 670) SetCoordinate(313) BEGIN + // (op 313) generate({}) + // (op 313) end: generate({}) + // (op 313) generate({314}) + // (op 313) SetCoordinate(314) BEGIN + // (op 314) generate({}) + // (op 314) end: generate({}) + // (op 314) generate({1051}) + // (op 314) Scope(1051) BEGIN + // (op 1051) Lock Scope 1051 + // Lock Branch + // (op 1051) generate({1045}) + // (op 1051) NOP(1045) BEGIN + // (op 1045) generate({}) + // (op 1045) end: generate({}) + // (op 1051) NOP(1045) END + // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) BEGIN + // (op 1056) Assign dim(474) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 + // tag 474: v**UNALLOCATED** + // (op 1056) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: (unallocated) + // (op 1056) Omitting copy to same register: s[20:21], s[20:21] + // (op 1056) reg expression + // (op 1056) Omitting copy to same register: s2, s2 + // (op 1056) reg expression + // (op 1056) Omitting copy to same register: v1, v1 + // (op 1056) reg expression + // (op 1056) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 + // (op 1056) Omitting copy to same register: s[18:19], s[18:19] + // (op 1056) reg expression + // (op 1056) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1056) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 +v_and_b32 v12, -32, v1 // (op 1056) +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v13 +v_lshrrev_b32 v13, 5, v1 // (op 1056) + // (op 1056) BEGIN: Flatten[1] + // (op 1056) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} + // (op 1056) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 +v_sub_u32 v14, v1, v12 // (op 1056) + // (op 1056) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1056): v12 + +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 +v_lshl_add_u32 v12, s2, 6, v13 // (op 1056) + // (op 1056) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1056): v13 + + // (op 1056) BEGIN: Tile + // (op 1056) {Tile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} + // (op 1056) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1056) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) + // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v13 +v_lshlrev_b32 v13, 1, v14 // (op 1056) + // (op 1056) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1056): v14 + +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 +s_ashr_i64 s[0:1], s[20:21], 6 // (op 1056) + // (op 1056) Omitting copy to same register: s0, s0 + // (op 1056) convert + // (op 1056) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1056): s17 +s_lshr_b32 s17, s0, 2 // (op 1056) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 + + // (op 1056) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 +v_lshl_add_u32 v14, s17, 8, v13 // (op 1056) + // (op 1056) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v13 + + // Freeing : 1 SGPR (Value: UInt32) (op 1056): s17 + +// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 +v_mov_b32 v17, 0 // (op 1056) convert +v_mov_b32 v16, v14 // (op 1056) convert + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v14 + + // (op 1056) BEGIN: Split + // (op 1056) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1056) lhs (Tile: VGPR Value: UInt32 x 1: v12) + // (op 1056) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) +// Allocated : 2 VGPRs (Value: UInt64) (op 1056): v14, v15 +v_mul_lo_u32 v15, v12, s19 // (op 1056) most significant: low of low * high + // (op 1056) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1056): v13 +v_mul_hi_u32 v13, v12, s18 // (op 1056) most significant: high of low * low +v_mul_lo_u32 v14, v12, s18 // (op 1056) least significant: low of low * low +v_add_u32 v15, v15, v13 // (op 1056) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1056): v13 + + // (op 1056) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1056) lhs (VGPR Value: UInt64 x 1: v[14:15]) + // (op 1056) rhs (Tile: VGPR Value: UInt64 x 1: v[16:17]) +// Allocated : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 +v_add_co_u32 v14, s[0:1], v14, v16 // (op 1056) least significant half +v_addc_co_u32 v15, s[0:1], v15, v17, s[0:1] // (op 1056) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 + + // (op 1056) END: Split + // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v12 + + // (op 1056) ShiftL({Split: v[14:15]:U64}, 1:U32)U64 + // (op 1056) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1056) value (Split: VGPR Value: UInt64 x 1: v[14:15]) + // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 +v_lshlrev_b64 v[12:13], 1, v[14:15] // (op 1056) + // Freeing Split: 2 VGPRs (Value: UInt64) (op 1056): v14, v15 + + // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) END + // (op 1051) Assign VGPR 128:U64(1057) BEGIN + // (op 1057) Assign dim(475) = 128:U64 + // (op 1057) Assign stride expression + // (op 1051) Assign VGPR 128:U64(1057) END + // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) BEGIN + // (op 1058) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1058) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // (op 1058) Omitting copy to same register: s[4:5], s[4:5] + // (op 1058) reg expression + // (op 1058) Omitting copy to same register: s[6:7], s[6:7] + // (op 1058) reg expression + // (op 1058) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 + // (op 1058) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1058) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) + // (op 1058) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1058): s0, s1 +s_lshl_b64 s[0:1], s[4:5], 1 // (op 1058) + // (op 1058) Omitting copy to same register: s0, s0 + // (op 1058) reg expression +s_mov_b32 s32, s6 // (op 1058) reg expression +s_mov_b32 s33, s7 // (op 1058) reg expression +s_mov_b32 s34, s0 // (op 1058) reg expression +s_mov_b32 s35, 131072 // (op 1058) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1058): s0, s1 + + // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) END + // (op 1051) NOP(1047) BEGIN + // (op 1047) generate({}) + // (op 1047) end: generate({}) + // (op 1051) NOP(1047) END + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) BEGIN + // (op 1063) Assign dim(479) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1063) Assign stride expression + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) END + // (op 1051) NOP(1048) BEGIN + // (op 1048) generate({}) + // (op 1048) end: generate({}) + // (op 1051) NOP(1048) END + // (op 1051) Assign VGPR 2:U64(1066) BEGIN + // (op 1066) Assign dim(481) = 2:U64 + // (op 1066) Assign stride expression + // (op 1051) Assign VGPR 2:U64(1066) END + // (op 1051) NOP(1114) BEGIN + // (op 1114) generate({}) + // (op 1114) end: generate({}) + // (op 1051) NOP(1114) END + // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) BEGIN + // (op 1123) Assign dim(493) = {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} + // tag 493: v**UNALLOCATED** + // (op 1123) Generate {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag493: VGPR Value: UInt64 x 1: (unallocated) + // (op 1123) Omitting copy to same register: s[20:21], s[20:21] + // (op 1123) reg expression + // (op 1123) Omitting copy to same register: s3, s3 + // (op 1123) reg expression + // (op 1123) Omitting copy to same register: v1, v1 + // (op 1123) reg expression + // (op 1123) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 + // (op 1123) Omitting copy to same register: s[22:23], s[22:23] + // (op 1123) reg expression + // (op 1123) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1123) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_and_b32 v14, -32, v1 // (op 1123) +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 +v_lshrrev_b32 v15, 5, v1 // (op 1123) + // (op 1123) BEGIN: Flatten[1] + // (op 1123) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v14:U32)U32} + // (op 1123) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v16 +v_sub_u32 v16, v1, v14 // (op 1123) + // (op 1123) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1123): v14 + +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_lshl_add_u32 v14, s3, 6, v15 // (op 1123) + // (op 1123) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1123): v15 + + // (op 1123) BEGIN: Tile + // (op 1123) {Tile: ShiftL({Flatten[1]: v16:U32}, 1:U32)U32} + // (op 1123) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1123) value (Flatten[1]: VGPR Value: UInt32 x 1: v16) + // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) + // (op 1123) Multiply({Tile: v14:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 + // (op 1123) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = + // (op 1123) lhs (Tile: VGPR Value: UInt32 x 1: v14) + // (op 1123) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 +v_lshlrev_b32 v15, 1, v16 // (op 1123) + // (op 1123) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1123): v16 + +// Allocated : 2 VGPRs (Value: Int64) (op 1123): v16, v17 +v_mul_lo_u32 v17, v14, s23 // (op 1123) most significant: low of low * high + // (op 1123) low of high * low omitted due to zero input. +// Allocated : 1 VGPR (Value: Int32) (op 1123): v18 +v_mul_hi_u32 v18, v14, s22 // (op 1123) most significant: high of low * low +v_mul_lo_u32 v16, v14, s22 // (op 1123) least significant: low of low * low +v_add_u32 v17, v17, v18 // (op 1123) most significant: sum + // Freeing : 1 VGPR (Value: Int32) (op 1123): v18 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 + +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 +s_ashr_i64 s[0:1], s[20:21], 6 // (op 1123) + // (op 1123) Omitting copy to same register: s0, s0 + // (op 1123) convert + // (op 1123) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 +// Allocated : 1 SGPR (Value: UInt32) (op 1123): s17 +s_lshr_b32 s17, s0, 2 // (op 1123) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 + + // (op 1123) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 +v_lshl_add_u32 v14, s17, 8, v15 // (op 1123) + // (op 1123) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v15 + + // Freeing : 1 SGPR (Value: UInt32) (op 1123): s17 + +// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 +v_mov_b32 v19, 0 // (op 1123) convert +v_mov_b32 v18, v14 // (op 1123) convert + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 + + // (op 1123) BEGIN: Split + // (op 1123) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 1123) lhs (Tile: VGPR Value: UInt64 x 1: v[18:19]) + // (op 1123) rhs (VGPR Value: Int64 x 1: v[16:17]) +// Allocated DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 +// Allocated : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 +v_add_co_u32 v14, s[0:1], v18, v16 // (op 1123) least significant half +v_addc_co_u32 v15, s[0:1], v19, v17, s[0:1] // (op 1123) most significant half + // Freeing : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 + + // (op 1123) ShiftL: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1123) value (VGPR Value: UInt64 x 1: v[14:15]) + // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) +v_lshlrev_b64 v[14:15], 1, v[14:15] // (op 1123) + // (op 1123) END: Split + // Freeing : 2 VGPRs (Value: Int64) (op 1123): v16, v17 + + // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 + + // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) END + // (op 1051) Assign VGPR 128:U64(1124) BEGIN + // (op 1124) Assign dim(494) = 128:U64 + // (op 1124) Assign stride expression + // (op 1051) Assign VGPR 128:U64(1124) END + // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) BEGIN + // (op 1125) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1125) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // (op 1125) Omitting copy to same register: s[8:9], s[8:9] + // (op 1125) reg expression + // (op 1125) Omitting copy to same register: s[10:11], s[10:11] + // (op 1125) reg expression + // (op 1125) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 + // (op 1125) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1125) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) + // (op 1125) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1125): s0, s1 +s_lshl_b64 s[0:1], s[8:9], 1 // (op 1125) + // (op 1125) Omitting copy to same register: s0, s0 + // (op 1125) reg expression +s_mov_b32 s36, s10 // (op 1125) reg expression +s_mov_b32 s37, s11 // (op 1125) reg expression +s_mov_b32 s38, s0 // (op 1125) reg expression +s_mov_b32 s39, 131072 // (op 1125) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1125): s0, s1 + + // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) END + // (op 1051) NOP(1116) BEGIN + // (op 1116) generate({}) + // (op 1116) end: generate({}) + // (op 1051) NOP(1116) END + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) BEGIN + // (op 1130) Assign dim(498) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 + // (op 1130) Assign stride expression + // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) END + // (op 1051) NOP(1117) BEGIN + // (op 1117) generate({}) + // (op 1117) end: generate({}) + // (op 1051) NOP(1117) END + // (op 1051) Assign VGPR 2:U64(1133) BEGIN + // (op 1133) Assign dim(500) = 2:U64 + // (op 1133) Assign stride expression + // (op 1051) Assign VGPR 2:U64(1133) END + // (op 1051) NOP(1211) BEGIN + // (op 1211) generate({}) + // (op 1211) end: generate({}) + // (op 1051) NOP(1211) END + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) BEGIN + // (op 1216) Assign dim(522) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 522: s**UNALLOCATED** + // (op 1216) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag522: SGPR Value: UInt32 x 1: (unallocated) + // (op 1216) Omitting copy to same register: v1, v1 + // (op 1216) reg expression + // (op 1216) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1216) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 +v_and_b32 v16, -32, v1 // (op 1216) +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1216) + // (op 1216) BEGIN: Tile[1] + // (op 1216) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v18 +v_sub_u32 v18, v1, v16 // (op 1216) + // (op 1216) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v16 + + // (op 1216) BEGIN: Flatten + // (op 1216) {Flatten: ShiftL({Tile[1]: v18:U32}, 1:U32)U32} + // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1216) value (Tile[1]: VGPR Value: UInt32 x 1: v18) + // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 +v_lshlrev_b32 v16, 1, v18 // (op 1216) + // (op 1216) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1216): v18 + + // (op 1216) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v18 +v_lshl_add_u32 v18, v17, 6, v16 // (op 1216) + // (op 1216) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v16 + + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v17 + + // (op 1216) ShiftL({Flatten: v18:U32}, 1:U32)U32 + // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1216) value (Flatten: VGPR Value: UInt32 x 1: v18) + // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 +v_lshlrev_b32 v17, 1, v18 // (op 1216) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v18 + +// Allocated DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s1 +s_nop 0 +v_readfirstlane_b32 s1, v17 // (op 1216) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1216): v17 + + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) END + // (op 1051) Assign VGPR 1024:U32(1217) BEGIN + // (op 1217) Assign dim(523) = 1024:U32 + // (op 1217) Assign stride expression + // (op 1051) Assign VGPR 1024:U32(1217) END + // (op 1051) NOP(1212) BEGIN + // (op 1212) generate({}) + // (op 1212) end: generate({}) + // (op 1051) NOP(1212) END + // (op 1051) Assign VGPR 2:U32(1221) BEGIN + // (op 1221) Assign dim(525) = 2:U32 + // (op 1221) Assign stride expression + // (op 1051) Assign VGPR 2:U32(1221) END + // (op 1051) NOP(1263) BEGIN + // (op 1263) generate({}) + // (op 1263) end: generate({}) + // (op 1051) NOP(1263) END + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) BEGIN + // (op 1268) Assign dim(538) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 + // tag 538: s**UNALLOCATED** + // (op 1268) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag538: SGPR Value: UInt32 x 1: (unallocated) + // (op 1268) Omitting copy to same register: v1, v1 + // (op 1268) reg expression + // (op 1268) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 + // (op 1268) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 +v_and_b32 v16, -32, v1 // (op 1268) +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 +v_lshrrev_b32 v17, 5, v1 // (op 1268) + // (op 1268) BEGIN: Tile[1] + // (op 1268) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v18 +v_sub_u32 v18, v1, v16 // (op 1268) + // (op 1268) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v16 + + // (op 1268) BEGIN: Flatten + // (op 1268) {Flatten: ShiftL({Tile[1]: v18:U32}, 1:U32)U32} + // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1268) value (Tile[1]: VGPR Value: UInt32 x 1: v18) + // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 +v_lshlrev_b32 v16, 1, v18 // (op 1268) + // (op 1268) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1268): v18 + + // (op 1268) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v18 +v_lshl_add_u32 v18, v17, 6, v16 // (op 1268) + // (op 1268) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v16 + + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v17 + + // (op 1268) ShiftL({Flatten: v18:U32}, 1:U32)U32 + // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1268) value (Flatten: VGPR Value: UInt32 x 1: v18) + // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 +v_lshlrev_b32 v17, 1, v18 // (op 1268) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v18 + +// Allocated DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s0 +s_nop 0 +v_readfirstlane_b32 s0, v17 // (op 1268) Wait state hazard: VALU Write Readlane Hazard + // Freeing : 1 VGPR (Value: UInt32) (op 1268): v17 + + // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) END + // (op 1051) Assign VGPR 1024:U32(1269) BEGIN + // (op 1269) Assign dim(539) = 1024:U32 + // (op 1269) Assign stride expression + // (op 1051) Assign VGPR 1024:U32(1269) END + // (op 1051) NOP(1264) BEGIN + // (op 1264) generate({}) + // (op 1264) end: generate({}) + // (op 1051) NOP(1264) END + // (op 1051) Assign VGPR 2:U32(1273) BEGIN + // (op 1273) Assign dim(541) = 2:U32 + // (op 1273) Assign stride expression + // (op 1051) Assign VGPR 2:U32(1273) END + // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) BEGIN + // (op 217) Initialize For Loop + // (op 217) generate({218}) + // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) BEGIN + // (op 218) Assign dim(316) = BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 + // tag 316: s**UNALLOCATED** + // (op 218) Generate BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: (unallocated) + // (op 218) Omitting copy to same register: s[20:21], s[20:21] + // (op 218) reg expression + // (op 218) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 218) + // (op 218) Omitting copy to same register: s16, s16 + // (op 218) convert + // (op 218) BitwiseAnd({ convertForwardSubset: s16:U32}, 4294967292:U32)U32 +// Allocated DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 +s_and_b32 s40, s16, 4294967292 // (op 218) + // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 + + // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) END + // (op 217) end: generate({218}) + // (op 217) Lock For Loop + // Lock Branch + // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc + // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL + // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) +// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 +s_mov_b32 s41, s16 // (op 217) convert + // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 + +s_cmp_lt_u32 s40, s41 // (op 217) + // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 217) +s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoopTail_217 // (op 217) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoopTail_217 if false) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoopTail_217: + // (op 217) + // (op 217) generate({219, 1726}) + // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) BEGIN + // (op 219) Assign dim(316) = Add(DataFlowTag(316)U32, 1:U32)U32 + // (op 219) Generate Add(DataFlowTag(316)U32, 1:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: s40 + // (op 219) Omitting copy to same register: s40, s40 + // (op 219) reg expression + // (op 219) Add({DataFlowTag316: s40:U32}, 1:U32)U32 + // (op 217) Barrier(1726) BEGIN +s_barrier // (op 1726) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 217) Barrier(1726) END +s_add_u32 s40, s40, 1 // (op 219) + // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) END + // (op 217) SetCoordinate(318) BEGIN + // (op 318) generate({}) + // (op 318) end: generate({}) + // (op 318) generate({981}) + // (op 318) LoadTileDirect2LDS Value: Halfx2(981) BEGIN + // (op 981) GEN: LoadTileDirect2LDS + // (op 981) GEN: loadMacroTileDirect2LDS OP 981 LDS 13 MacroTile 318 + // (op 981) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 981) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride479: VGPR Value: UInt64 x 1: (unallocated) + // (op 981) Omitting copy to same register: s[18:19], s[18:19] + // (op 981) reg expression + // (op 981) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 + // (op 981) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 981) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) + // (op 981) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 +s_lshl_b64 s[16:17], s[18:19], 3 // (op 981) + // (op 981) Omitting copy to same register: s[16:17], s[16:17] + // (op 981) convert + // (op 981) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 981) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 981) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 981) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 981) + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 + + // (op 981) Generate 2:U64 into nullptr + // (op 981) Generate 1024:U32 into nullptr + // (op 981) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 8192 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride479: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 478: v**UNALLOCATED** +// Allocated Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 +v_mov_b64 v[18:19], v[12:13] // (op 981) +// Allocated : 2 VGPRs (Value: UInt64) (op 981): v20, v21 +v_mov_b64 v[20:21], v[18:19] // (op 981) + // (op 981) Generate Add(8192:U32, {DataFlowTag522: s1:U32})U32 into nullptr + // (op 981) Omitting copy to same register: s1, s1 + // (op 981) reg expression + // (op 981) Add(8192:U32, {DataFlowTag522: s1:U32})U32 +// Allocated : 1 SGPR (Value: UInt32) (op 981): s17 +s_add_u32 s17, 8192, s1 // (op 981) + // (op 981) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride479: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 981) Generate s17:U32 into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s17 // (op 981) reg expression +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// VMEM: Expected complete at 2892 (current 2817) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2896 (current 2821) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2900 (current 2825) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2904 (current 2829) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 2968 (current 2893) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2972 (current 2897) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2976 (current 2901) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 981) Omitting copy to same register: v[20:21], v[20:21] + // (op 981) reg expression + // (op 981) Omitting copy to same register: v16, v16 + // (op 981) reg expression + // (op 981) Add(v[20:21]:U64, v16:R)U64 + // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 981) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 +v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 + + // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 981) Omitting copy to same register: m0, m0 + // (op 981) reg expression + // (op 981) Add(m0:U32, 1024:U32)U32 + // (op 981) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 981) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 981) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected complete at 2980 (current 2905) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // Freeing Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 981): v20, v21 + + // Freeing : 1 SGPR (Value: UInt32) (op 981): s17 + + // (op 318) LoadTileDirect2LDS Value: Halfx2(981) END + // (op 318) Deallocate{}(1879) BEGIN + // (op 1879) Deallocate 318 + // Deleting tag 318 + // (op 1879) Deallocate 524 + // Deleting tag 524 + // (op 1879) Deallocate 478 + // Freeing Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 + + // Deleting tag 478 + // (op 1879) Deallocate 480 + // Deleting tag 480 + // (op 318) Deallocate{}(1879) END + // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) BEGIN + // (op 1046) Assign dim(474) = Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 + // (op 1046) Generate Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13] + // (op 1046) Omitting copy to same register: v[12:13], v[12:13] + // (op 1046) reg expression + // (op 1046) Add({DataFlowTag474: v[12:13]:U64}, 128:U64)U64 + // (op 1046) Add: dest (VGPR Value: UInt64 x 1: v[12:13]) = + // (op 1046) lhs (DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13]) + // (op 1046) rhs (Literal Value: UInt64 x 0: 128) +v_add_co_u32 v12, vcc, 128, v12 // (op 1046) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +v_addc_co_u32 v13, vcc, 0, v13, vcc // (op 1046) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) END + // (op 318) end: generate({981}) + // (op 217) SetCoordinate(318) END + // (op 217) NOP(983) BEGIN + // (op 983) generate({}) + // (op 983) end: generate({}) + // (op 217) NOP(983) END + // (op 217) Barrier(1736) BEGIN +s_barrier // (op 1736) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 217) Barrier(1736) END + // (op 217) SetCoordinate(323) BEGIN + // (op 323) generate({}) + // (op 323) end: generate({}) + // (op 323) generate({987}) + // (op 323) LoadTileDirect2LDS Value: Halfx2(987) BEGIN + // (op 987) GEN: LoadTileDirect2LDS + // (op 987) GEN: loadMacroTileDirect2LDS OP 987 LDS 21 MacroTile 320 + // (op 987) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 987) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride498: VGPR Value: UInt64 x 1: (unallocated) + // (op 987) Omitting copy to same register: s[22:23], s[22:23] + // (op 987) reg expression + // (op 987) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 + // (op 987) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 987) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) + // (op 987) shiftAmount (Literal Value: UInt32 x 0: 3) +// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 +s_lshl_b64 s[16:17], s[22:23], 3 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 987) Omitting copy to same register: s[16:17], s[16:17] + // (op 987) convert + // (op 987) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 + // (op 987) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = + // (op 987) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) + // (op 987) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 +v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 + + // (op 987) Generate 2:U64 into nullptr + // (op 987) Generate 1024:U32 into nullptr + // (op 987) Dir = Load + // LSTInfo { + // info.kind = Buffer2LDS + // info.m = 8 + // info.n = 1 + // info.elementBits = 32 + // info.packedAmount = 1 + // info.ldsWriteStride = 1024 + // info.data = Literal Value: UInt32 x 0: 0 + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Stride498: VGPR Value: UInt64 x 1: v[16:17] + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 1 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 0 + // colStrideIsOne = 1 + + // tag 497: v**UNALLOCATED** +// Allocated Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 +v_mov_b64 v[18:19], v[14:15] // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// Allocated : 2 VGPRs (Value: UInt64) (op 987): v20, v21 +v_mov_b64 v[20:21], v[18:19] // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // (op 987) Generate Add(0:U32, {DataFlowTag538: s0:U32})U32 into nullptr + // (op 987) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride498: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 + // (op 987) Generate {DataFlowTag538: s0:U32} into M0 Value: UInt32 x 1: m0 +s_mov_b32 m0, s0 // (op 987) reg expression +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// VMEM: Expected stall of 55. CBNW: 4, Inc: 4 +// VMEM: Expected complete at 3044 (current 2969) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3048 (current 2973) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3052 (current 2977) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3056 (current 2981) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 +// VMEM: Expected complete at 3120 (current 3045) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3124 (current 3049) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3128 (current 3053) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] + // (op 987) Omitting copy to same register: v[20:21], v[20:21] + // (op 987) reg expression + // (op 987) Omitting copy to same register: v16, v16 + // (op 987) reg expression + // (op 987) Add(v[20:21]:U64, v16:R)U64 + // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = + // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) + // (op 987) rhs (VGPR Value: Raw32 x 1: v16) +// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 +v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 + + // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 + // (op 987) Omitting copy to same register: m0, m0 + // (op 987) reg expression + // (op 987) Add(m0:U32, 1024:U32)U32 + // (op 987) Expression temporary in special register (M0) + // Lock M0 +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +s_add_u32 m0, m0, 1024 // (op 987) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 8192, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 987) Expression temporary in special register + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// VMEM: Expected complete at 3132 (current 3057) +// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // Freeing Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 + + // Freeing : 2 VGPRs (Value: UInt64) (op 987): v20, v21 + + // (op 323) LoadTileDirect2LDS Value: Halfx2(987) END + // (op 323) Deallocate{}(1881) BEGIN + // (op 1881) Deallocate 320 + // Deleting tag 320 + // (op 1881) Deallocate 497 + // Freeing Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 + + // Deleting tag 497 + // (op 1881) Deallocate 540 + // Deleting tag 540 + // (op 1881) Deallocate 499 + // Deleting tag 499 + // (op 323) Deallocate{}(1881) END + // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) BEGIN + // (op 1115) Assign dim(493) = Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 + // (op 1115) Generate Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 into DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15] + // (op 1115) Omitting copy to same register: v[14:15], v[14:15] + // (op 1115) reg expression + // (op 1115) Add({DataFlowTag493: v[14:15]:U64}, 128:U64)U64 + // (op 1115) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = + // (op 1115) lhs (DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15]) + // (op 1115) rhs (Literal Value: UInt64 x 0: 128) +v_add_co_u32 v14, vcc, 128, v14 // (op 1115) least significant half + // Lock VCC +// Start of Int64 add, locking VCC +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +v_addc_co_u32 v15, vcc, 0, v15, vcc // (op 1115) most significant half + // Unlock VCC +// End of Int64 add, Unlocking VCC. +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } + // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) END + // (op 323) end: generate({987}) + // (op 217) SetCoordinate(323) END + // (op 217) NOP(989) BEGIN + // (op 989) generate({}) + // (op 989) end: generate({}) + // (op 217) NOP(989) END + // (op 217) Barrier(1729) BEGIN +s_waitcnt vmcnt(8) +s_barrier // (op 1729) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 7 and the queue size is 16, so a waitcnt of 8 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 217) Barrier(1729) END + // (op 217) SetCoordinate(224) BEGIN + // (op 224) generate({}) + // (op 224) end: generate({}) + // (op 224) generate({225}) + // (op 224) LoadLDSTile{Value: Halfx2}(225) BEGIN + // (op 225) GEN: loadMacroTileWAVELDS OP 225 LDS 13 WaveTile 85 + // (op 225) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 225) Generate 2:U32 into nullptr + // tag 322: v**UNALLOCATED** + // (op 225) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 225) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 225) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 +ds_read_b64 v[16:17], v0 offset:8192 // (op 225) Load local data +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// DSMEM: Expected complete at 3015 (current 2995) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 224) LoadLDSTile{Value: Halfx2}(225) END + // (op 224) end: generate({225}) + // (op 217) SetCoordinate(224) END + // (op 217) Barrier(1739) BEGIN +s_waitcnt vmcnt(0) +s_barrier // (op 1739) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 7 and the queue size is 8, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// ------Dst: {LDS:(Offset: 0, Size: 8192), } +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 217) Barrier(1739) END + // (op 217) SetCoordinate(226) BEGIN + // (op 226) generate({}) + // (op 226) end: generate({}) + // (op 226) generate({227}) + // (op 226) LoadLDSTile{Value: Halfx2}(227) BEGIN + // (op 227) GEN: loadMacroTileWAVELDS OP 227 LDS 21 WaveTile 145 + // (op 227) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 227) Generate 2:U32 into nullptr + // tag 324: v**UNALLOCATED** + // (op 227) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 227) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 227) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 +ds_read_b64 v[18:19], v4 // (op 227) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// DSMEM: Expected complete at 3018 (current 2998) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 226) LoadLDSTile{Value: Halfx2}(227) END + // (op 226) end: generate({227}) + // (op 217) SetCoordinate(226) END + // (op 217) Multiply(228) BEGIN + // (op 228) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 228) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } + // (op 217) Multiply(228) END + // (op 217) Deallocate{}(1783) BEGIN + // (op 1783) Deallocate 322 + // Freeing : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 + + // Deleting tag 322 + // (op 1783) Deallocate 324 + // Freeing : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 + + // Deleting tag 324 + // (op 217) Deallocate{}(1783) END + // (op 217) SetCoordinate(229) BEGIN + // (op 229) generate({}) + // (op 229) end: generate({}) + // (op 229) generate({230}) + // (op 229) LoadLDSTile{Value: Halfx2}(230) BEGIN + // (op 230) GEN: loadMacroTileWAVELDS OP 230 LDS 13 WaveTile 85 + // (op 230) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 230) Generate 2:U32 into nullptr + // tag 326: v**UNALLOCATED** + // (op 230) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 230) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8208 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 230) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 +ds_read_b64 v[16:17], v0 offset:8208 // (op 230) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3041 (current 3021) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 229) LoadLDSTile{Value: Halfx2}(230) END + // (op 229) end: generate({230}) + // (op 217) SetCoordinate(229) END + // (op 217) SetCoordinate(231) BEGIN + // (op 231) generate({}) + // (op 231) end: generate({}) + // (op 231) generate({232}) + // (op 231) LoadLDSTile{Value: Halfx2}(232) BEGIN + // (op 232) GEN: loadMacroTileWAVELDS OP 232 LDS 21 WaveTile 145 + // (op 232) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 232) Generate 2:U32 into nullptr + // tag 328: v**UNALLOCATED** + // (op 232) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 232) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 16 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 232) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 +ds_read_b64 v[18:19], v4 offset:16 // (op 232) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3042 (current 3022) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 231) LoadLDSTile{Value: Halfx2}(232) END + // (op 231) end: generate({232}) + // (op 217) SetCoordinate(231) END + // (op 217) Multiply(233) BEGIN + // (op 233) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 233) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(233) END + // (op 217) Deallocate{}(1785) BEGIN + // (op 1785) Deallocate 328 + // Freeing : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 + + // Deleting tag 328 + // (op 1785) Deallocate 326 + // Freeing : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 + + // Deleting tag 326 + // (op 217) Deallocate{}(1785) END + // (op 217) SetCoordinate(234) BEGIN + // (op 234) generate({}) + // (op 234) end: generate({}) + // (op 234) generate({235}) + // (op 234) LoadLDSTile{Value: Halfx2}(235) BEGIN + // (op 235) GEN: loadMacroTileWAVELDS OP 235 LDS 13 WaveTile 85 + // (op 235) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 235) Generate 2:U32 into nullptr + // tag 330: v**UNALLOCATED** + // (op 235) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 235) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8224 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 235) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 +ds_read_b64 v[16:17], v0 offset:8224 // (op 235) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3071 (current 3051) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 234) LoadLDSTile{Value: Halfx2}(235) END + // (op 234) end: generate({235}) + // (op 217) SetCoordinate(234) END + // (op 217) SetCoordinate(236) BEGIN + // (op 236) generate({}) + // (op 236) end: generate({}) + // (op 236) generate({237}) + // (op 236) LoadLDSTile{Value: Halfx2}(237) BEGIN + // (op 237) GEN: loadMacroTileWAVELDS OP 237 LDS 21 WaveTile 145 + // (op 237) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 237) Generate 2:U32 into nullptr + // tag 332: v**UNALLOCATED** + // (op 237) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 237) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 32 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 237) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 +ds_read_b64 v[18:19], v4 offset:32 // (op 237) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3072 (current 3052) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 236) LoadLDSTile{Value: Halfx2}(237) END + // (op 236) end: generate({237}) + // (op 217) SetCoordinate(236) END + // (op 217) Multiply(238) BEGIN + // (op 238) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 238) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(238) END + // (op 217) Deallocate{}(1787) BEGIN + // (op 1787) Deallocate 332 + // Freeing : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 + + // Deleting tag 332 + // (op 1787) Deallocate 330 + // Freeing : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 + + // Deleting tag 330 + // (op 217) Deallocate{}(1787) END + // (op 217) SetCoordinate(239) BEGIN + // (op 239) generate({}) + // (op 239) end: generate({}) + // (op 239) generate({240}) + // (op 239) LoadLDSTile{Value: Halfx2}(240) BEGIN + // (op 240) GEN: loadMacroTileWAVELDS OP 240 LDS 13 WaveTile 85 + // (op 240) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 240) Generate 2:U32 into nullptr + // tag 334: v**UNALLOCATED** + // (op 240) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 240) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8240 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 240) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 +ds_read_b64 v[16:17], v0 offset:8240 // (op 240) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3101 (current 3081) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 239) LoadLDSTile{Value: Halfx2}(240) END + // (op 239) end: generate({240}) + // (op 217) SetCoordinate(239) END + // (op 217) SetCoordinate(241) BEGIN + // (op 241) generate({}) + // (op 241) end: generate({}) + // (op 241) generate({242}) + // (op 241) LoadLDSTile{Value: Halfx2}(242) BEGIN + // (op 242) GEN: loadMacroTileWAVELDS OP 242 LDS 21 WaveTile 145 + // (op 242) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 242) Generate 2:U32 into nullptr + // tag 336: v**UNALLOCATED** + // (op 242) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 242) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 48 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 242) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 +ds_read_b64 v[18:19], v4 offset:48 // (op 242) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3102 (current 3082) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 241) LoadLDSTile{Value: Halfx2}(242) END + // (op 241) end: generate({242}) + // (op 217) SetCoordinate(241) END + // (op 217) Multiply(243) BEGIN + // (op 243) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 243) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(243) END + // (op 217) Deallocate{}(1789) BEGIN + // (op 1789) Deallocate 334 + // Freeing : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 + + // Deleting tag 334 + // (op 1789) Deallocate 336 + // Freeing : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 + + // Deleting tag 336 + // (op 217) Deallocate{}(1789) END + // (op 217) SetCoordinate(244) BEGIN + // (op 244) generate({}) + // (op 244) end: generate({}) + // (op 244) generate({245}) + // (op 244) LoadLDSTile{Value: Halfx2}(245) BEGIN + // (op 245) GEN: loadMacroTileWAVELDS OP 245 LDS 13 WaveTile 85 + // (op 245) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 245) Generate 2:U32 into nullptr + // tag 338: v**UNALLOCATED** + // (op 245) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 245) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8256 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 245) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 +ds_read_b64 v[16:17], v0 offset:8256 // (op 245) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3131 (current 3111) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 244) LoadLDSTile{Value: Halfx2}(245) END + // (op 244) end: generate({245}) + // (op 217) SetCoordinate(244) END + // (op 217) SetCoordinate(246) BEGIN + // (op 246) generate({}) + // (op 246) end: generate({}) + // (op 246) generate({247}) + // (op 246) LoadLDSTile{Value: Halfx2}(247) BEGIN + // (op 247) GEN: loadMacroTileWAVELDS OP 247 LDS 21 WaveTile 145 + // (op 247) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 247) Generate 2:U32 into nullptr + // tag 340: v**UNALLOCATED** + // (op 247) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 247) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 64 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 247) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 +ds_read_b64 v[18:19], v4 offset:64 // (op 247) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3132 (current 3112) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 246) LoadLDSTile{Value: Halfx2}(247) END + // (op 246) end: generate({247}) + // (op 217) SetCoordinate(246) END + // (op 217) Multiply(248) BEGIN + // (op 248) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 248) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(248) END + // (op 217) Deallocate{}(1791) BEGIN + // (op 1791) Deallocate 340 + // Freeing : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 + + // Deleting tag 340 + // (op 1791) Deallocate 338 + // Freeing : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 + + // Deleting tag 338 + // (op 217) Deallocate{}(1791) END + // (op 217) SetCoordinate(249) BEGIN + // (op 249) generate({}) + // (op 249) end: generate({}) + // (op 249) generate({250}) + // (op 249) LoadLDSTile{Value: Halfx2}(250) BEGIN + // (op 250) GEN: loadMacroTileWAVELDS OP 250 LDS 13 WaveTile 85 + // (op 250) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 250) Generate 2:U32 into nullptr + // tag 342: v**UNALLOCATED** + // (op 250) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 250) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8272 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 250) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 +ds_read_b64 v[16:17], v0 offset:8272 // (op 250) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3161 (current 3141) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 249) LoadLDSTile{Value: Halfx2}(250) END + // (op 249) end: generate({250}) + // (op 217) SetCoordinate(249) END + // (op 217) SetCoordinate(251) BEGIN + // (op 251) generate({}) + // (op 251) end: generate({}) + // (op 251) generate({252}) + // (op 251) LoadLDSTile{Value: Halfx2}(252) BEGIN + // (op 252) GEN: loadMacroTileWAVELDS OP 252 LDS 21 WaveTile 145 + // (op 252) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 252) Generate 2:U32 into nullptr + // tag 344: v**UNALLOCATED** + // (op 252) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 252) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 80 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 252) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 +ds_read_b64 v[18:19], v4 offset:80 // (op 252) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3162 (current 3142) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 251) LoadLDSTile{Value: Halfx2}(252) END + // (op 251) end: generate({252}) + // (op 217) SetCoordinate(251) END + // (op 217) Multiply(253) BEGIN + // (op 253) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 253) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(253) END + // (op 217) Deallocate{}(1793) BEGIN + // (op 1793) Deallocate 342 + // Freeing : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 + + // Deleting tag 342 + // (op 1793) Deallocate 344 + // Freeing : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 + + // Deleting tag 344 + // (op 217) Deallocate{}(1793) END + // (op 217) SetCoordinate(254) BEGIN + // (op 254) generate({}) + // (op 254) end: generate({}) + // (op 254) generate({255}) + // (op 254) LoadLDSTile{Value: Halfx2}(255) BEGIN + // (op 255) GEN: loadMacroTileWAVELDS OP 255 LDS 13 WaveTile 85 + // (op 255) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 255) Generate 2:U32 into nullptr + // tag 346: v**UNALLOCATED** + // (op 255) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 255) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8288 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 255) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 +ds_read_b64 v[16:17], v0 offset:8288 // (op 255) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3191 (current 3171) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 254) LoadLDSTile{Value: Halfx2}(255) END + // (op 254) end: generate({255}) + // (op 217) SetCoordinate(254) END + // (op 217) SetCoordinate(256) BEGIN + // (op 256) generate({}) + // (op 256) end: generate({}) + // (op 256) generate({257}) + // (op 256) LoadLDSTile{Value: Halfx2}(257) BEGIN + // (op 257) GEN: loadMacroTileWAVELDS OP 257 LDS 21 WaveTile 145 + // (op 257) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 257) Generate 2:U32 into nullptr + // tag 348: v**UNALLOCATED** + // (op 257) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 257) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 96 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 257) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 +ds_read_b64 v[18:19], v4 offset:96 // (op 257) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3192 (current 3172) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 256) LoadLDSTile{Value: Halfx2}(257) END + // (op 256) end: generate({257}) + // (op 217) SetCoordinate(256) END + // (op 217) Multiply(258) BEGIN + // (op 258) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 258) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(258) END + // (op 217) Deallocate{}(1795) BEGIN + // (op 1795) Deallocate 348 + // Freeing : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 + + // Deleting tag 348 + // (op 1795) Deallocate 346 + // Freeing : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 + + // Deleting tag 346 + // (op 217) Deallocate{}(1795) END + // (op 217) SetCoordinate(259) BEGIN + // (op 259) generate({}) + // (op 259) end: generate({}) + // (op 259) generate({260}) + // (op 259) LoadLDSTile{Value: Halfx2}(260) BEGIN + // (op 260) GEN: loadMacroTileWAVELDS OP 260 LDS 13 WaveTile 85 + // (op 260) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 260) Generate 2:U32 into nullptr + // tag 350: v**UNALLOCATED** + // (op 260) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8192 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 260) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 8304 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 260) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 +ds_read_b64 v[16:17], v0 offset:8304 // (op 260) Load local data +// MFMA remaining: 8 +// DSMEM: Expected complete at 3221 (current 3201) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) + // (op 259) LoadLDSTile{Value: Halfx2}(260) END + // (op 259) end: generate({260}) + // (op 217) SetCoordinate(259) END + // (op 217) SetCoordinate(261) BEGIN + // (op 261) generate({}) + // (op 261) end: generate({}) + // (op 261) generate({262}) + // (op 261) LoadLDSTile{Value: Halfx2}(262) BEGIN + // (op 262) GEN: loadMacroTileWAVELDS OP 262 LDS 21 WaveTile 145 + // (op 262) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 262) Generate 2:U32 into nullptr + // tag 352: v**UNALLOCATED** + // (op 262) Dir = Load + // LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 262) LSTInfo { + // info.kind = Local + // info.m = 1 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 2: (unallocated) + // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v4 + // info.rowStrideReg = Literal Value: UInt32 x 0: 0 + // info.rowStrideAttributes = { + // t.dataType = None + // t.unitStride = 0 + // t.elementBlockSize = 0 + // t.elementBlockStride = nullptr + // t.trLoadPairStride = nullptr + // } + // info.colStrideReg = Literal Value: UInt32 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 + // } + // info.offset = Literal Value: UInt32 x 0: 112 + // info.bufDesc = (nullptr) + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 262) info.m = 1 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 0 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 +ds_read_b64 v[18:19], v4 offset:112 // (op 262) Load local data +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// MFMA remaining: 7 +// DSMEM: Expected complete at 3222 (current 3202) +// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) + // (op 261) LoadLDSTile{Value: Halfx2}(262) END + // (op 261) end: generate({262}) + // (op 217) SetCoordinate(261) END + // (op 217) Multiply(263) BEGIN + // (op 263) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] +s_waitcnt lgkmcnt(0) +v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 263) WaitCnt Needed: Intersects with registers in 'DSQueue', at 1 and the queue size is 2, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: DSQueue +// ----Needs Wait Zero: False +// ----Type In Queue : DSQueue +// ----Registers : +// ------Dst: {v[16:17], LDS:(Offset: 8192, Size: 8192), } +// ------Dst: {v[18:19], LDS:(Offset: 0, Size: 8192), } +// MFMA remaining: 6 + // (op 217) Multiply(263) END + // (op 217) Deallocate{}(1797) BEGIN + // (op 1797) Deallocate 352 + // Freeing : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 + + // Deleting tag 352 + // (op 1797) Deallocate 350 + // Freeing : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 + + // Deleting tag 350 + // (op 217) Deallocate{}(1797) END + // (op 217) end: generate({219, 1726}) + // (op 217) For Loop Increment + // (op 217) generate({}) + // (op 217) end: generate({}) + // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoopTail_217 if true) + // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc + // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL + // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 +// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 +s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) MFMA remaining: 8 +// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 +s_mov_b32 s41, s16 // (op 217) convert +// MFMA remaining: 7 + // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 + +s_cmp_lt_u32 s40, s41 // (op 217) MFMA remaining: 6 + // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 + +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 217) MFMA remaining: 5 +s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoopTail_217 // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopTop_KLoopTail_217 if true) +// MFMA remaining: 4 +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ForLoopBottom_KLoopTail_217: + // (op 217) MFMA remaining: 3 +s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch + // (op 217) MFMA remaining: 3 + // (op 217) Unlock For Loop + // Unlock None +// MFMA remaining: 2 + // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) END + // (op 1051) Deallocate{}(1781) BEGIN + // (op 1781) Deallocate 316 + // Freeing DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 + + // Deleting tag 316 + // (op 1781) Deallocate 538 + // Freeing DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s0 + + // Deleting tag 538 + // (op 1781) Deallocate 541 + // Deleting tag 541 + // (op 1781) Deallocate 539 + // Deleting tag 539 + // (op 1781) Deallocate 523 + // Deleting tag 523 + // (op 1781) Deallocate 500 + // Deleting tag 500 + // (op 1781) Deallocate 498 + // Deleting tag 498 + // (op 1781) Deallocate 494 + // Deleting tag 494 + // (op 1781) Deallocate 493 + // Freeing DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 + + // Deleting tag 493 + // (op 1781) Deallocate 481 + // Deleting tag 481 + // (op 1781) Deallocate 479 + // Deleting tag 479 + // (op 1781) Deallocate 475 + // Deleting tag 475 + // (op 1781) Deallocate 474 + // Freeing DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 + + // Deleting tag 474 + // (op 1781) Deallocate 522 + // Freeing DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s1 + + // Deleting tag 522 + // (op 1781) Deallocate 525 + // Deleting tag 525 + // (op 1051) Deallocate{}(1781) END + // (op 1051) end: generate({1045}) + // (op 1051) Unlock Scope 1051 + // Unlock None +// MFMA remaining: 2 + // (op 314) Scope(1051) END + // (op 314) end: generate({1051}) + // (op 313) SetCoordinate(314) END + // (op 313) end: generate({314}) + // (op 670) SetCoordinate(313) END + // (op 670) Deallocate{}(1799) BEGIN + // (op 1799) Deallocate 58 + // Deleting tag 58 + // (op 1799) Deallocate 303 + // Deleting tag 303 + // (op 1799) Deallocate 118 + // Deleting tag 118 + // (op 1799) Deallocate 477 + // Freeing DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 + + // Deleting tag 477 + // (op 1799) Deallocate 496 + // Freeing DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 + + // Deleting tag 496 + // (op 1799) Deallocate 532 + // Deleting tag 532 + // (op 1799) Deallocate 133 + // Deleting tag 133 + // (op 1799) Deallocate 73 + // Deleting tag 73 + // (op 1799) Deallocate 301 + // Deleting tag 301 + // (op 1799) Deallocate 21 + // Deleting tag 21 + // (op 1799) Deallocate 548 + // Deleting tag 548 + // (op 1799) Deallocate 13 + // Deleting tag 13 + // (op 670) Deallocate{}(1799) END + // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) BEGIN + // (op 2003) Deallocate Tensor_2_pointer + // Freeing Tensor_2_pointer: 2 SGPRs (Value: Raw32): s10, s11 + + // (op 2003) Deallocate Tensor_0_pointer + // Freeing Tensor_0_pointer: 2 SGPRs (Value: Raw32): s6, s7 + + // (op 2003) Deallocate Tensor_0_extent_0 + // Freeing Tensor_0_extent_0: 2 SGPRs (Value: Raw32): s4, s5 + + // (op 2003) Deallocate Tensor_2_stride_1_12 + // Freeing Tensor_2_stride_1_12: 2 SGPRs (Value: Raw32): s22, s23 + + // (op 2003) Deallocate Tensor_0_stride_0_9 + // Freeing Tensor_0_stride_0_9: 2 SGPRs (Value: Raw32): s18, s19 + + // (op 2003) Deallocate Tensor_2_extent_2 + // Freeing Tensor_2_extent_2: 2 SGPRs (Value: Raw32): s8, s9 + + // (op 2003) Deallocate Tensor_0_size_1_10 + // Freeing Tensor_0_size_1_10: 2 SGPRs (Value: Raw32): s20, s21 + + // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) END + // (op 670) Barrier(1801) BEGIN +s_barrier // (op 1801) MFMA remaining: 2 + // (op 670) Barrier(1801) END + // (op 670) end: generate({675}) + // (op 670) Unlock Scope 670 + // Unlock None +// MFMA remaining: 1 + // (op 1) Scope(670) END + // (op 1) Deallocate{}(1867) BEGIN + // (op 1867) Deallocate 631 + // Deleting tag 631 + // (op 1867) Deallocate 629 + // Deleting tag 629 + // (op 1867) Deallocate 619 + // Deleting tag 619 + // (op 1867) Deallocate 531 + // Deleting tag 531 + // (op 1867) Deallocate 568 + // Freeing DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v3 + + // Deleting tag 568 + // (op 1867) Deallocate 604 + // Freeing DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v8 + + // Deleting tag 604 + // (op 1867) Deallocate 546 + // Freeing DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v4 + + // Deleting tag 546 + // (op 1867) Deallocate 605 + // Deleting tag 605 + // (op 1867) Deallocate 547 + // Deleting tag 547 + // (op 1867) Deallocate 530 + // Freeing DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 + + // Deleting tag 530 + // (op 1867) Deallocate 533 + // Deleting tag 533 + // (op 1867) Deallocate 580 + // Freeing DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v6 + + // Deleting tag 580 + // (op 1867) Deallocate 616 + // Freeing DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v7 + + // Deleting tag 616 + // (op 1867) Deallocate 628 + // Freeing DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v10 + + // Deleting tag 628 + // (op 1867) Deallocate 569 + // Deleting tag 569 + // (op 1867) Deallocate 617 + // Deleting tag 617 + // (op 1867) Deallocate 581 + // Deleting tag 581 + // (op 1867) Deallocate 593 + // Deleting tag 593 + // (op 1867) Deallocate 571 + // Deleting tag 571 + // (op 1867) Deallocate 549 + // Deleting tag 549 + // (op 1867) Deallocate 607 + // Deleting tag 607 + // (op 1867) Deallocate 583 + // Deleting tag 583 + // (op 1867) Deallocate 592 + // Freeing DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v5 + + // Deleting tag 592 + // (op 1867) Deallocate 595 + // Deleting tag 595 + // (op 1) Deallocate{}(1867) END + // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) BEGIN + // (op 177) Lock for Conditional + // Lock Branch +// MFMA remaining: 1 + // (op 177) Generate Equal(0.00000:S, DataFlowTag(24)S)BL into VCC Value: Bool64 x 1: vcc + // (op 177) Omitting copy to same register: v9, v9 + // (op 177) reg expression + // (op 177) Equal(0.00000:S, v9:S)BL64 +v_cmp_eq_f32 vcc, 0.00000, v9 // (op 177) MFMA remaining: 1 +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 177) +s_cbranch_vccz RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalFalse_0_beta_177 // (op 177) Condition: False, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalFalse_0_beta_177 + // (op 177) generate({678}) + // (op 177) Scope(678) BEGIN + // (op 678) Lock Scope 678 + // Lock Branch + // (op 678) generate({681}) + // (op 678) NOP(681) BEGIN + // (op 681) generate({}) + // (op 681) end: generate({}) + // (op 678) NOP(681) END + // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) BEGIN + // (op 29) Assign dim(39) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA + // (op 29) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr + // (op 29) Omitting copy to same register: v11, v11 + // (op 29) reg expression + // (op 29) Omitting copy to same register: a[0:15], a[0:15] + // (op 29) reg expression + // (op 29) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S +// Allocated : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 +s_nop 3 +v_accvgpr_read v12, a0 // (op 29) Wait state hazard: XDL Write Hazard +v_accvgpr_read v13, a1 // (op 29) +v_accvgpr_read v14, a2 // (op 29) +v_accvgpr_read v15, a3 // (op 29) +v_accvgpr_read v16, a4 // (op 29) +v_accvgpr_read v17, a5 // (op 29) +v_accvgpr_read v18, a6 // (op 29) +v_accvgpr_read v19, a7 // (op 29) +v_accvgpr_read v20, a8 // (op 29) +v_accvgpr_read v21, a9 // (op 29) +v_accvgpr_read v22, a10 // (op 29) +v_accvgpr_read v23, a11 // (op 29) +v_accvgpr_read v24, a12 // (op 29) +v_accvgpr_read v25, a13 // (op 29) +v_accvgpr_read v26, a14 // (op 29) +v_accvgpr_read v27, a15 // (op 29) +// Allocated : 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 +v_mul_f32 v28, v11, v12 // (op 29) +v_mul_f32 v29, v11, v13 // (op 29) +v_mul_f32 v30, v11, v14 // (op 29) +v_mul_f32 v31, v11, v15 // (op 29) +v_mul_f32 v32, v11, v16 // (op 29) +v_mul_f32 v33, v11, v17 // (op 29) +v_mul_f32 v34, v11, v18 // (op 29) +v_mul_f32 v35, v11, v19 // (op 29) +v_mul_f32 v36, v11, v20 // (op 29) +v_mul_f32 v37, v11, v21 // (op 29) +v_mul_f32 v38, v11, v22 // (op 29) +v_mul_f32 v39, v11, v23 // (op 29) +v_mul_f32 v40, v11, v24 // (op 29) +v_mul_f32 v41, v11, v25 // (op 29) +v_mul_f32 v42, v11, v26 // (op 29) +v_mul_f32 v43, v11, v27 // (op 29) + // Freeing : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 + + // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) END + // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) BEGIN + // (op 35) Assign dim(41) = Convert(DataFlowTag(39)NA)H + // (op 35) Generate Convert(DataFlowTag(39)NA)H into nullptr + // (op 35) Omitting copy to same register: v[28:43], v[28:43] + // (op 35) reg expression +// Allocated DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 +v_cvt_f16_f32 v12, v28 // (op 35) +v_cvt_f16_f32 v13, v29 // (op 35) +v_cvt_f16_f32 v14, v30 // (op 35) +v_cvt_f16_f32 v15, v31 // (op 35) +v_cvt_f16_f32 v16, v32 // (op 35) +v_cvt_f16_f32 v17, v33 // (op 35) +v_cvt_f16_f32 v18, v34 // (op 35) +v_cvt_f16_f32 v19, v35 // (op 35) +v_cvt_f16_f32 v20, v36 // (op 35) +v_cvt_f16_f32 v21, v37 // (op 35) +v_cvt_f16_f32 v22, v38 // (op 35) +v_cvt_f16_f32 v23, v39 // (op 35) +v_cvt_f16_f32 v24, v40 // (op 35) +v_cvt_f16_f32 v25, v41 // (op 35) +v_cvt_f16_f32 v26, v42 // (op 35) +v_cvt_f16_f32 v27, v43 // (op 35) + // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) END + // (op 678) Deallocate{}(1761) BEGIN + // (op 1761) Deallocate 39 + // Freeing DataFlowTag39: 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 + + // Deleting tag 39 + // (op 678) Deallocate{}(1761) END + // (op 678) NOP(1305) BEGIN + // (op 1305) generate({}) + // (op 1305) end: generate({}) + // (op 678) NOP(1305) END + // (op 678) NOP(1302) BEGIN + // (op 1302) generate({}) + // (op 1302) end: generate({}) + // (op 678) NOP(1302) END + // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) BEGIN + // (op 1309) Assign dim(550) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} + // tag 550: v**UNALLOCATED** + // (op 1309) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag550: VGPR Value: UInt32 x 1: (unallocated) + // (op 1309) Omitting copy to same register: s3, s3 + // (op 1309) reg expression + // (op 1309) Omitting copy to same register: s[26:27], s[26:27] + // (op 1309) reg expression + // (op 1309) Omitting copy to same register: v1, v1 + // (op 1309) reg expression + // (op 1309) Omitting copy to same register: s2, s2 + // (op 1309) reg expression + // (op 1309) Omitting copy to same register: s26, s26 + // (op 1309) convert + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_and_b32 v0, 63, v1 // (op 1309) + // (op 1309) END: Tile[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v10 +v_lshrrev_b32 v10, 6, v1 // (op 1309) + // (op 1309) LogicalShiftR({Tile[1]: v0:U32}, 2:U32)U32 + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v8 +v_lshrrev_b32 v8, 2, v0 // (op 1309) +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v7 +v_and_b32 v7, 3, v1 // (op 1309) + // (op 1309) END: Tile[1] + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd(v8:U32, 7:U32)U32} + // (op 1309) LogicalShiftR({Tile[1]: v0:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v6 +v_and_b32 v6, 7, v8 // (op 1309) + // (op 1309) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v8 +v_lshrrev_b32 v8, 5, v0 // (op 1309) + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v0 + + // (op 1309) BEGIN: Flatten + // (op 1309) BEGIN: Tile[1] + // (op 1309) {Tile[1]: BitwiseAnd(v10:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_lshl_add_u32 v0, v6, 2, v7 // (op 1309) + // (op 1309) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v7 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v6 + +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v7 +v_and_b32 v7, 1, v10 // (op 1309) + // (op 1309) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v10 + + // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v10 +v_lshrrev_b32 v10, 7, v1 // (op 1309) +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v6 +v_lshl_add_u32 v6, v7, 5, v0 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v0 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v7 + + // (op 1309) BEGIN: Flatten + // (op 1309) {Flatten: ShiftL(v8:U32, 2:U32)U32} + // (op 1309) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1309) value (VGPR Value: UInt32 x 1: v8) + // (op 1309) shiftAmount (Literal Value: UInt32 x 0: 2) + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_lshlrev_b32 v0, 2, v8 // (op 1309) + // (op 1309) END: Flatten + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v5 +v_lshl_add_u32 v5, s3, 6, v6 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v6 + + // (op 1309) BEGIN: Flatten + // (op 1309) Multiply({Flatten: v5:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 +v_lshl_add_u32 v4, v10, 5, v0 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v0 + + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v10 + +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 +v_mul_lo_u32 v0, v5, s26 // (op 1309) + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v5 + + // (op 1309) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 +v_lshl_add_u32 v3, s2, 6, v4 // (op 1309) + // (op 1309) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v4 + + // (op 1309) BEGIN: Join +// Allocated DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v10 +v_add_lshl_u32 v10, v3, v0, 1 // (op 1309) + // (op 1309) END: Join + // Freeing : 1 VGPR (Value: UInt32) (op 1309): v0 + + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v3 + + // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) END + // (op 678) Assign VGPR 16:U64(1310) BEGIN + // (op 1310) Assign dim(551) = 16:U64 + // (op 1310) Assign stride expression + // (op 678) Assign VGPR 16:U64(1310) END + // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) BEGIN + // (op 1311) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 553: s**UNALLOCATED** + // (op 1311) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: (unallocated) + // (op 1311) Omitting copy to same register: s[28:29], s[28:29] + // (op 1311) reg expression + // (op 1311) Omitting copy to same register: s[30:31], s[30:31] + // (op 1311) reg expression + // (op 1311) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 + // (op 1311) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1311) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) + // (op 1311) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1311): s0, s1 +s_lshl_b64 s[0:1], s[28:29], 1 // (op 1311) + // (op 1311) Omitting copy to same register: s0, s0 + // (op 1311) reg expression +// Allocated DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s8, s9, s10, s11 +s_mov_b32 s8, s30 // (op 1311) reg expression +s_mov_b32 s9, s31 // (op 1311) reg expression +s_mov_b32 s10, s0 // (op 1311) reg expression +s_mov_b32 s11, 131072 // (op 1311) call() + // Freeing : 2 SGPRs (Value: Int64) (op 1311): s0, s1 + + // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) END + // (op 678) NOP(1303) BEGIN + // (op 1303) generate({}) + // (op 1303) end: generate({}) + // (op 678) NOP(1303) END + // (op 678) Assign VGPR 2:U64(1316) BEGIN + // (op 1316) Assign dim(555) = 2:U64 + // (op 1316) Assign stride expression + // (op 678) Assign VGPR 2:U64(1316) END + // (op 678) StoreTiled Value: Halfx2(37) BEGIN + // (op 37) GEN: storeMacroTileWAVE OP 37 MacroTile 41 WaveTile 215 + // (op 37) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 37) Generate 16:U64 into nullptr + // (op 37) Generate 2:U64 into nullptr + // (op 37) Convert in LSTGen + // (op 37) Generate Convert({DataFlowTag39: v[12:27]:H})2xH into nullptr + // (op 37) Omitting copy to same register: v[12:27], v[12:27] + // (op 37) reg expression +// Allocated DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 +v_pack_b32_f16 v28, v12, v13 // (op 37) +v_pack_b32_f16 v29, v14, v15 // (op 37) +v_pack_b32_f16 v30, v16, v17 // (op 37) +v_pack_b32_f16 v31, v18, v19 // (op 37) +v_pack_b32_f16 v32, v20, v21 // (op 37) +v_pack_b32_f16 v33, v22, v23 // (op 37) +v_pack_b32_f16 v34, v24, v25 // (op 37) +v_pack_b32_f16 v35, v26, v27 // (op 37) + // (op 37) Dir = Store + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 37) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = DataFlowTag550: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 37) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +buffer_store_dwordx2 v[28:29], v10, s[8:11], 0 offen // (op 37) Store value +// VMEM: Expected complete at 3374 (current 3299) +buffer_store_dwordx2 v[30:31], v10, s[8:11], 0 offen offset:16 // (op 37) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// VMEM: Expected complete at 3375 (current 3300) +buffer_store_dwordx2 v[32:33], v10, s[8:11], 0 offen offset:32 // (op 37) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3376 (current 3301) +buffer_store_dwordx2 v[34:35], v10, s[8:11], 0 offen offset:48 // (op 37) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3377 (current 3302) + // Freeing DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 678) StoreTiled Value: Halfx2(37) END + // (op 678) Deallocate{}(1763) BEGIN + // (op 1763) Deallocate 551 + // Deleting tag 551 + // (op 1763) Deallocate 555 + // Deleting tag 555 + // (op 1763) Deallocate 554 + // Deleting tag 554 + // (op 1763) Deallocate 41 + // Freeing DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 + + // Deleting tag 41 + // (op 1763) Deallocate 550 + // Freeing DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v10 + + // Deleting tag 550 + // (op 678) Deallocate{}(1763) END + // (op 678) end: generate({681}) + // (op 678) Unlock Scope 678 + // Unlock None +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 177) Scope(678) END + // (op 177) end: generate({678}) +s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit + // (op 177) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +s_branch RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalBottom_0_beta_177 // (op 177) Condition: Done, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalBottom_0_beta_177 +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalFalse_0_beta_177: + // (op 177) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 177) generate({684}) + // (op 177) Scope(684) BEGIN + // (op 684) Lock Scope 684 + // Lock Branch +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 684) generate({687}) + // (op 684) NOP(687) BEGIN + // (op 687) generate({}) + // (op 687) end: generate({}) + // (op 684) NOP(687) END + // (op 684) NOP(185) BEGIN + // (op 185) generate({}) + // (op 185) end: generate({}) + // (op 684) NOP(185) END + // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) BEGIN + // (op 186) Assign dim(295) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA + // (op 186) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr + // (op 186) Omitting copy to same register: v11, v11 + // (op 186) reg expression + // (op 186) Omitting copy to same register: a[0:15], a[0:15] + // (op 186) reg expression + // (op 186) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S + // (op 684) Scope(1181) BEGIN + // (op 1181) Lock Scope 1181 + // Lock Branch +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 1181) generate({1178}) + // (op 1181) NOP(1178) BEGIN + // (op 1178) generate({}) + // (op 1178) end: generate({}) + // (op 1181) NOP(1178) END + // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) BEGIN + // (op 1186) Assign dim(512) = {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} + // tag 512: v**UNALLOCATED** + // (op 1186) Generate {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} into DataFlowTag512: VGPR Value: UInt32 x 1: (unallocated) + // (op 1186) Omitting copy to same register: s3, s3 + // (op 1186) reg expression + // (op 1186) Omitting copy to same register: s[24:25], s[24:25] + // (op 1186) reg expression + // (op 1186) Omitting copy to same register: v1, v1 + // (op 1186) reg expression + // (op 1186) Omitting copy to same register: s2, s2 + // (op 1186) reg expression + // (op 1186) Omitting copy to same register: s24, s24 + // (op 1186) convert + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_and_b32 v0, 63, v1 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Flatten[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v10 +v_lshrrev_b32 v10, 6, v1 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) LogicalShiftR({Flatten[1]: v0:U32}, 2:U32)U32 + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v8 +v_lshrrev_b32 v8, 2, v0 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v7 +v_and_b32 v7, 3, v1 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Flatten[1] + // (op 1186) BEGIN: Flatten[1] + // (op 1186) {Flatten[1]: BitwiseAnd(v8:U32, 7:U32)U32} + // (op 1186) LogicalShiftR({Flatten[1]: v0:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v6 +v_and_b32 v6, 7, v8 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Flatten[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v8 +v_lshrrev_b32 v8, 5, v0 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v0 + + // (op 1186) BEGIN: Tile + // (op 1186) BEGIN: Tile + // (op 1186) {Tile: BitwiseAnd(v10:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_lshl_add_u32 v0, v6, 2, v7 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v7 + + // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v6 + +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v7 +v_and_b32 v7, 1, v10 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v10 + + // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v10 +v_lshrrev_b32 v10, 7, v1 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v6 +v_lshl_add_u32 v6, v7, 5, v0 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v0 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v7 + + // (op 1186) BEGIN: Tile + // (op 1186) {Tile: ShiftL(v8:U32, 2:U32)U32} + // (op 1186) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1186) value (VGPR Value: UInt32 x 1: v8) + // (op 1186) shiftAmount (Literal Value: UInt32 x 0: 2) + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_lshlrev_b32 v0, 2, v8 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v5 +v_lshl_add_u32 v5, s3, 6, v6 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v6 + + // (op 1186) BEGIN: Tile + // (op 1186) Multiply({Tile: v5:U32}, { convertForwardSubsetTensor_4_stride_1_13: s24:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 +v_lshl_add_u32 v4, v10, 5, v0 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v0 + + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v10 + +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 +v_mul_lo_u32 v0, v5, s24 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v5 + + // (op 1186) BEGIN: Tile +// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 +v_lshl_add_u32 v3, s2, 6, v4 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Tile + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 + + // (op 1186) BEGIN: Split +// Allocated DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v10 +v_add_lshl_u32 v10, v3, v0, 1 // (op 1186) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1186) END: Split + // Freeing : 1 VGPR (Value: UInt32) (op 1186): v0 + + // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v3 + + // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) END + // (op 1181) Deallocate{}(1911) BEGIN + // (op 1911) Deallocate 305 + // Deleting tag 305 + // (op 1911) Deallocate 174 + // Deleting tag 174 + // (op 1911) Deallocate 307 + // Deleting tag 307 + // (op 1181) Deallocate{}(1911) END + // (op 1181) Assign VGPR 16:U64(1187) BEGIN + // (op 1187) Assign dim(513) = 16:U64 + // (op 1187) Assign stride expression + // (op 1181) Assign VGPR 16:U64(1187) END + // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) BEGIN + // (op 1188) Assign dim(515) = Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // tag 515: s**UNALLOCATED** + // (op 1188) Generate Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag515: SGPR Buffer: None x 1: (unallocated) + // (op 1188) Omitting copy to same register: s[12:13], s[12:13] + // (op 1188) reg expression + // (op 1188) Omitting copy to same register: s[14:15], s[14:15] + // (op 1188) reg expression + // (op 1188) ShiftL({Tensor_4_extent_4: s[12:13]:I64}, 1:U32)I64 + // (op 1188) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1188) value (Tensor_4_extent_4: SGPR Value: Int64 x 1: s[12:13]) + // (op 1188) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1188): s0, s1 +s_lshl_b64 s[0:1], s[12:13], 1 // (op 1188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1188) Omitting copy to same register: s0, s0 + // (op 1188) reg expression +// Allocated DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s4, s5, s6, s7 +s_mov_b32 s4, s14 // (op 1188) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s5, s15 // (op 1188) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s6, s0 // (op 1188) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s7, 131072 // (op 1188) call() +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // Freeing : 2 SGPRs (Value: Int64) (op 1188): s0, s1 + + // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) END + // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) BEGIN + // (op 2007) Deallocate Tensor_4_pointer + // Freeing Tensor_4_pointer: 2 SGPRs (Value: Raw32): s14, s15 + + // (op 2007) Deallocate Tensor_4_extent_4 + // Freeing Tensor_4_extent_4: 2 SGPRs (Value: Raw32): s12, s13 + + // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) END + // (op 1181) NOP(1179) BEGIN + // (op 1179) generate({}) + // (op 1179) end: generate({}) + // (op 1181) NOP(1179) END + // (op 1181) Assign VGPR 2:U64(1193) BEGIN + // (op 1193) Assign dim(517) = 2:U64 + // (op 1193) Assign stride expression + // (op 1181) Assign VGPR 2:U64(1193) END + // (op 1181) LoadTiled Value: Halfx2(190) BEGIN + // (op 190) GEN: loadMacroTileWAVECIACCUM OP 190 WaveTile 175 + // (op 190) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 190) Generate 16:U64 into nullptr + // (op 190) Generate 2:U64 into nullptr + // tag 291: v**UNALLOCATED** + // (op 190) Dir = Load + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 8: (unallocated) + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 190) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = VGPR Value: Halfx2 x 8: (unallocated) + // info.rowOffsetReg = DataFlowTag512: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[4:7] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 190) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +// Allocated : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 +buffer_load_dwordx2 v[12:13], v10, s[4:7], 0 offen // (op 190) Load value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected stall of 49. CBNW: 0, Inc: 4 +// VMEM: Expected complete at 3450 (current 3375) +buffer_load_dwordx2 v[14:15], v10, s[4:7], 0 offen offset:16 // (op 190) Load value +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[12:13], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3451 (current 3376) +buffer_load_dwordx2 v[16:17], v10, s[4:7], 0 offen offset:32 // (op 190) Load value +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[12:13], } +// ------Dst: {v[14:15], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3452 (current 3377) +buffer_load_dwordx2 v[18:19], v10, s[4:7], 0 offen offset:48 // (op 190) Load value +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[12:13], } +// ------Dst: {v[14:15], } +// ------Dst: {v[16:17], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3453 (current 3378) + // (op 1181) LoadTiled Value: Halfx2(190) END + // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) BEGIN + // (op 1777) Deallocate 3 + // Deleting tag 3 + // (op 1777) Deallocate 513 + // Deleting tag 513 + // (op 1777) Deallocate 515 + // Freeing DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s4, s5, s6, s7 + + // Deleting tag 515 + // (op 1777) Deallocate 512 + // Freeing DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v10 + + // Deleting tag 512 + // (op 1777) Deallocate 516 + // Deleting tag 516 + // (op 1777) Deallocate 517 + // Deleting tag 517 + // (op 1777) Deallocate Tensor_4_stride_1_13 + // Freeing Tensor_4_stride_1_13: 2 SGPRs (Value: Raw32): s24, s25 + + // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) END + // (op 1181) end: generate({1178}) + // (op 1181) Unlock Scope 1181 + // Unlock None +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[12:13], } +// ------Dst: {v[14:15], } +// ------Dst: {v[16:17], } +// ------Dst: {v[18:19], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 684) Scope(1181) END +// Allocated : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 +v_accvgpr_read v20, a0 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) BEGIN + // (op 191) Assign dim(293) = Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA + // (op 191) Generate Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA into nullptr + // (op 191) Omitting copy to same register: v9, v9 + // (op 191) reg expression + // (op 191) Omitting copy to same register: v[12:19], v[12:19] + // (op 191) reg expression + // (op 191) Multiply(v9:S, v[12:19]:2xH)S +v_accvgpr_read v21, a1 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v22, a2 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v23, a3 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v24, a4 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v25, a5 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v26, a6 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v27, a7 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v28, a8 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v29, a9 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v30, a10 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v31, a11 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v32, a12 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v33, a13 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v34, a14 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_accvgpr_read v35, a15 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 +v_mul_f32 v36, v11, v20 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v37, v11, v21 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v38, v11, v22 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v39, v11, v23 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v40, v11, v24 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v41, v11, v25 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v42, v11, v26 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v43, v11, v27 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v44, v11, v28 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v45, v11, v29 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v46, v11, v30 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v47, v11, v31 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v48, v11, v32 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v49, v11, v33 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v50, v11, v34 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v51, v11, v35 // (op 186) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[12:13], } + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) END +// Allocated : 2 VGPRs (Value: Float) (op 191): v4, v5 +s_waitcnt vmcnt(3) +v_cvt_f32_f16 v4, v12 // (op 191) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 0 and the queue size is 4, so a waitcnt of 3 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[12:13], } +// ------Dst: {v[14:15], } +// ------Dst: {v[16:17], } +// ------Dst: {v[18:19], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +v_lshrrev_b32 v5, 16, v12 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 +v_mul_f32 v20, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v21, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v4, v13 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_lshrrev_b32 v5, 16, v13 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v22, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v23, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[14:15], } + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +s_waitcnt vmcnt(2) +v_cvt_f32_f16 v4, v14 // (op 191) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 0 and the queue size is 3, so a waitcnt of 2 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[14:15], } +// ------Dst: {v[16:17], } +// ------Dst: {v[18:19], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +v_lshrrev_b32 v5, 16, v14 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v24, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v25, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v4, v15 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_lshrrev_b32 v5, 16, v15 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v26, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v27, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[16:17], } + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +s_waitcnt vmcnt(1) +v_cvt_f32_f16 v4, v16 // (op 191) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 0 and the queue size is 2, so a waitcnt of 1 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[16:17], } +// ------Dst: {v[18:19], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +v_lshrrev_b32 v5, 16, v16 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v28, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v29, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v4, v17 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_lshrrev_b32 v5, 16, v17 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v30, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v31, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: LoadQueue + // ----Needs Wait Zero: False + // ----Type In Queue : LoadQueue + // ----Registers : + // ------Dst: {v[18:19], } + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +s_waitcnt vmcnt(0) +v_cvt_f32_f16 v4, v18 // (op 191) WaitCnt Needed: Intersects with registers in 'LoadQueue', at 0 and the queue size is 1, so a waitcnt of 0 is required. + +// +// Wait Queue State: +// --Queue: LoadQueue +// ----Needs Wait Zero: False +// ----Type In Queue : LoadQueue +// ----Registers : +// ------Dst: {v[18:19], } +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +v_lshrrev_b32 v5, 16, v18 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v32, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v33, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v4, v19 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_lshrrev_b32 v5, 16, v19 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f32_f16 v5, v5 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v34, v9, v4 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_mul_f32 v35, v9, v5 // (op 191) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing : 2 VGPRs (Value: Float) (op 191): v4, v5 + + // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) END + // (op 684) Deallocate{}(1779) BEGIN + // (op 1779) Deallocate 291 + // Freeing : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 + + // Deleting tag 291 + // (op 684) Deallocate{}(1779) END + // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) BEGIN + // (op 187) Assign dim(297) = Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA + // (op 187) Generate Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA into nullptr + // (op 187) Omitting copy to same register: v[20:35], v[20:35] + // (op 187) reg expression + // (op 187) Omitting copy to same register: v[36:51], v[36:51] + // (op 187) reg expression + // (op 187) Add({DataFlowTag293: v[20:35]:S}, {DataFlowTag295: v[36:51]:S})S +// Allocated : 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 +v_add_f32 v52, v20, v36 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v53, v21, v37 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v54, v22, v38 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v55, v23, v39 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v56, v24, v40 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v57, v25, v41 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v58, v26, v42 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v59, v27, v43 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v60, v28, v44 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v61, v29, v45 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v62, v30, v46 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v63, v31, v47 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v64, v32, v48 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v65, v33, v49 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v66, v34, v50 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_add_f32 v67, v35, v51 // (op 187) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) END + // (op 684) Deallocate{}(1771) BEGIN + // (op 1771) Deallocate 293 + // Freeing DataFlowTag293: 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 + + // Deleting tag 293 + // (op 1771) Deallocate 295 + // Freeing DataFlowTag295: 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 + + // Deleting tag 295 + // (op 684) Deallocate{}(1771) END + // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) BEGIN + // (op 188) Assign dim(299) = Convert(DataFlowTag(297)NA)H + // (op 188) Generate Convert(DataFlowTag(297)NA)H into nullptr + // (op 188) Omitting copy to same register: v[52:67], v[52:67] + // (op 188) reg expression +// Allocated DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 +v_cvt_f16_f32 v36, v52 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v37, v53 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v38, v54 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v39, v55 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v40, v56 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v41, v57 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v42, v58 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v43, v59 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v44, v60 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v45, v61 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v46, v62 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v47, v63 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v48, v64 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v49, v65 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v50, v66 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_cvt_f16_f32 v51, v67 // (op 188) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) END + // (op 684) Deallocate{}(1773) BEGIN + // (op 1773) Deallocate 297 + // Freeing DataFlowTag297: 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 + + // Deleting tag 297 + // (op 684) Deallocate{}(1773) END + // (op 684) NOP(1322) BEGIN + // (op 1322) generate({}) + // (op 1322) end: generate({}) + // (op 684) NOP(1322) END + // (op 684) NOP(1319) BEGIN + // (op 1319) generate({}) + // (op 1319) end: generate({}) + // (op 684) NOP(1319) END + // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) BEGIN + // (op 1326) Assign dim(556) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} + // tag 556: v**UNALLOCATED** + // (op 1326) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag556: VGPR Value: UInt32 x 1: (unallocated) + // (op 1326) Omitting copy to same register: s3, s3 + // (op 1326) reg expression + // (op 1326) Omitting copy to same register: s[26:27], s[26:27] + // (op 1326) reg expression + // (op 1326) Omitting copy to same register: v1, v1 + // (op 1326) reg expression + // (op 1326) Omitting copy to same register: s2, s2 + // (op 1326) reg expression + // (op 1326) Omitting copy to same register: s26, s26 + // (op 1326) convert + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} + // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_and_b32 v0, 63, v1 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Tile[1] +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v10 +v_lshrrev_b32 v10, 6, v1 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) LogicalShiftR({Tile[1]: v0:U32}, 2:U32)U32 + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v8 +v_lshrrev_b32 v8, 2, v0 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v7 +v_and_b32 v7, 3, v1 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Tile[1] + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd(v8:U32, 7:U32)U32} + // (op 1326) LogicalShiftR({Tile[1]: v0:U32}, 5:U32)U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v6 +v_and_b32 v6, 7, v8 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v8 +v_lshrrev_b32 v8, 5, v0 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v0 + + // (op 1326) BEGIN: Flatten + // (op 1326) BEGIN: Tile[1] + // (op 1326) {Tile[1]: BitwiseAnd(v10:U32, 1:U32)U32} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_lshl_add_u32 v0, v6, 2, v7 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v7 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v6 + +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v7 +v_and_b32 v7, 1, v10 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Tile[1] + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v10 + + // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v10 +v_lshrrev_b32 v10, 7, v1 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v6 +v_lshl_add_u32 v6, v7, 5, v0 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v0 + + // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v7 + + // (op 1326) BEGIN: Flatten + // (op 1326) {Flatten: ShiftL(v8:U32, 2:U32)U32} + // (op 1326) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = + // (op 1326) value (VGPR Value: UInt32 x 1: v8) + // (op 1326) shiftAmount (Literal Value: UInt32 x 0: 2) + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_lshlrev_b32 v0, 2, v8 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v8 + +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v5 +v_lshl_add_u32 v5, s3, 6, v6 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v6 + + // (op 1326) BEGIN: Flatten + // (op 1326) Multiply({Flatten: v5:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 +v_lshl_add_u32 v4, v10, 5, v0 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v0 + + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v10 + +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 +v_mul_lo_u32 v0, v5, s26 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v5 + + // (op 1326) BEGIN: Flatten +// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 +v_lshl_add_u32 v3, s2, 6, v4 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Flatten + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v4 + + // (op 1326) BEGIN: Join +// Allocated DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v10 +v_add_lshl_u32 v10, v3, v0, 1 // (op 1326) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1326) END: Join + // Freeing : 1 VGPR (Value: UInt32) (op 1326): v0 + + // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v3 + + // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) END + // (op 684) Assign VGPR 16:U64(1327) BEGIN + // (op 1327) Assign dim(557) = 16:U64 + // (op 1327) Assign stride expression + // (op 684) Assign VGPR 16:U64(1327) END + // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) BEGIN + // (op 1328) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB + // (op 1328) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: s[8:11] + // (op 1328) Omitting copy to same register: s[28:29], s[28:29] + // (op 1328) reg expression + // (op 1328) Omitting copy to same register: s[30:31], s[30:31] + // (op 1328) reg expression + // (op 1328) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 + // (op 1328) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = + // (op 1328) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) + // (op 1328) shiftAmount (Literal Value: UInt32 x 0: 1) +// Allocated : 2 SGPRs (Value: Int64) (op 1328): s0, s1 +s_lshl_b64 s[0:1], s[28:29], 1 // (op 1328) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 1328) Omitting copy to same register: s0, s0 + // (op 1328) reg expression +s_mov_b32 s8, s30 // (op 1328) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s9, s31 // (op 1328) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s10, s0 // (op 1328) reg expression +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +s_mov_b32 s11, 131072 // (op 1328) call() +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // Freeing : 2 SGPRs (Value: Int64) (op 1328): s0, s1 + + // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) END + // (op 684) NOP(1320) BEGIN + // (op 1320) generate({}) + // (op 1320) end: generate({}) + // (op 684) NOP(1320) END + // (op 684) Assign VGPR 2:U64(1333) BEGIN + // (op 1333) Assign dim(559) = 2:U64 + // (op 1333) Assign stride expression + // (op 684) Assign VGPR 2:U64(1333) END + // (op 684) StoreTiled Value: Halfx2(189) BEGIN + // (op 189) GEN: storeMacroTileWAVE OP 189 MacroTile 299 WaveTile 215 + // (op 189) varTypeInfo.elementBits = 32 + // varTypeInfo.packing = 2 + + // (op 189) Generate 16:U64 into nullptr + // (op 189) Generate 2:U64 into nullptr + // (op 189) Convert in LSTGen + // (op 189) Generate Convert({DataFlowTag297: v[36:51]:H})2xH into nullptr + // (op 189) Omitting copy to same register: v[36:51], v[36:51] + // (op 189) reg expression +// Allocated DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 +v_pack_b32_f16 v28, v36, v37 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v29, v38, v39 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v30, v40, v41 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v31, v42, v43 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v32, v44, v45 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v33, v46, v47 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v34, v48, v49 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} +v_pack_b32_f16 v35, v50, v51 // (op 189) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 189) Dir = Store + // LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = (nullptr) + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } allStridesAreLiteral = 1 + // colStrideIsOne = 1 + + // (op 189) LSTInfo { + // info.kind = Buffer + // info.m = 4 + // info.n = 2 + // info.elementBits = 32 + // info.packedAmount = 2 + // info.ldsWriteStride = 0 + // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] + // info.rowOffsetReg = DataFlowTag556: VGPR Value: UInt32 x 1: v10 + // info.rowStrideReg = Literal Value: UInt64 x 0: 16 + // info.rowStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 0 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 + // } + // info.colStrideReg = Literal Value: UInt64 x 0: 2 + // info.colStrideAttributes = { + // t.dataType = UInt64 + // t.unitStride = 1 + // t.elementBlockSize = 8 + // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 + // } + // info.offset = Literal Value: UInt32 x 0: 0 + // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[8:11] + // info.bufOpts = { options.offen = 0 + // options.glc = 0 + // options.slc = 0 + // options.sc1 = 0 + // options.lds = 0 + // } + // info.isTransposedTile = 0 + // } + // (op 189) info.m = 4 + // info.n = 2 + // elementsPerMove = 2 + // bytesPerMove = 8 + // rowStride = 16 + // colStride = 2 + // info.colStrideAttributes.elementBlockSize = 8 + // numVGPRBlocks = 1 + // elementBlockStride = 0 + +buffer_store_dwordx2 v[28:29], v10, s[8:11], 0 offen // (op 189) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3631 (current 3556) +buffer_store_dwordx2 v[30:31], v10, s[8:11], 0 offen offset:16 // (op 189) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3632 (current 3557) +buffer_store_dwordx2 v[32:33], v10, s[8:11], 0 offen offset:32 // (op 189) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3633 (current 3558) +buffer_store_dwordx2 v[34:35], v10, s[8:11], 0 offen offset:48 // (op 189) Store value +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// VMEM: Expected complete at 3634 (current 3559) + // Freeing DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 + + // (op 684) StoreTiled Value: Halfx2(189) END + // (op 684) Deallocate{}(1775) BEGIN + // (op 1775) Deallocate 558 + // Deleting tag 558 + // (op 1775) Deallocate 557 + // Deleting tag 557 + // (op 1775) Deallocate 559 + // Deleting tag 559 + // (op 1775) Deallocate 556 + // Freeing DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v10 + + // Deleting tag 556 + // (op 1775) Deallocate 299 + // Freeing DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 + + // Deleting tag 299 + // (op 684) Deallocate{}(1775) END + // (op 684) end: generate({687}) + // (op 684) Unlock Scope 684 + // Unlock None +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 177) Scope(684) END + // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) BEGIN + // (op 1869) Deallocate 311 + // Deleting tag 311 + // (op 1869) Deallocate 553 + // Freeing DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s8, s9, s10, s11 + + // Deleting tag 553 + // (op 1869) Deallocate 309 + // Deleting tag 309 + // (op 1869) Deallocate 214 + // Deleting tag 214 + // (op 1869) Deallocate Tensor_15_stride_1_14 + // Freeing Tensor_15_stride_1_14: 2 SGPRs (Value: Raw32): s26, s27 + + // (op 1869) Deallocate Tensor_15_extent_15 + // Freeing Tensor_15_extent_15: 2 SGPRs (Value: Raw32): s28, s29 + + // (op 1869) Deallocate Tensor_15_pointer + // Freeing Tensor_15_pointer: 2 SGPRs (Value: Raw32): s30, s31 + + // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) END + // (op 177) end: generate({684}) +RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_ConditionalBottom_0_beta_177: + // (op 177) + // Wait Queue State: + // --Queue: StoreQueue + // ----Needs Wait Zero: False + // ----Type In Queue : StoreQueue + // ----Registers : + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // ------Dst: {} + // (op 177) Unlock Conditional + // Unlock None +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} + // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) END + // (op 1) Deallocate{}(1769) BEGIN + // (op 1769) Deallocate 33 + // Freeing : 1 VGPR (Value: Float) (op 24): v11 + + // Deleting tag 33 + // (op 1769) Deallocate 24 + // Freeing : 1 VGPR (Value: Float) (op 2): v9 + + // Deleting tag 24 + // (op 1769) Deallocate 35 + // Freeing DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 + + // Deleting tag 35 + // (op 1) Deallocate{}(1769) END + // (op 1) end: generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) + // Kernel(1) END + // end: generate({1}) + // CodeGeneratorVisitor::generate() end +s_endpgm // End of RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e +// +// Wait Queue State: +// --Queue: StoreQueue +// ----Needs Wait Zero: False +// ----Type In Queue : StoreQueue +// ----Registers : +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +// ------Dst: {} +.LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_end: + +.size RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e, .LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e_end-RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e +.rodata +.p2align 6 +.amdhsa_kernel RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e + // Resource limits + .amdhsa_next_free_vgpr 96 + .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr + .amdhsa_group_segment_fixed_size 65536 // lds bytes + .amdhsa_accum_offset 80 + // Initial kernel state + .amdhsa_user_sgpr_kernarg_segment_ptr 1 +.amdhsa_system_sgpr_workgroup_id_x 1 +.amdhsa_system_sgpr_workgroup_id_y 1 +.amdhsa_system_sgpr_workgroup_id_z 0 +.amdhsa_system_sgpr_workgroup_info 0 +.amdhsa_system_vgpr_workitem_id 1 +.end_amdhsa_kernel + +.amdgpu_metadata +--- +amdhsa.version: [1, 2] +amdhsa.kernels: + - .name: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e + .symbol: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.kd + .kernarg_segment_size: 112 + .group_segment_fixed_size: 65536 + .private_segment_fixed_size: 0 + .kernarg_segment_align: 8 + .sgpr_count: 50 + .vgpr_count: 78 + .agpr_count: 16 + .max_flat_workgroup_size: 256 + .workgroup_size: [256, 1, 1] + .kernel_dimensions: 2 + .wavefront_size: 64 + .workitem_count: [{type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_0_size_0_8, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 56, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 256}}, {type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_2_size_1_11, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 80, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, {is-null: true}] + .dynamic_sharedmemory_bytes: {type: LiteralValue.UInt32, dataType: UInt32, value: 0} + .args: + - .name: Tensor_0_extent_0 + .size: 8 + .offset: 0 + .expression: {type: CommandArgument, size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_pointer + .size: 8 + .offset: 8 + .expression: {type: CommandArgument, size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: Tensor_2_extent_2 + .size: 8 + .offset: 16 + .expression: {type: CommandArgument, size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_2_pointer + .size: 8 + .offset: 24 + .expression: {type: CommandArgument, size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: Tensor_4_extent_4 + .size: 8 + .offset: 32 + .expression: {type: CommandArgument, size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_4_pointer + .size: 8 + .offset: 40 + .expression: {type: CommandArgument, size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + - .name: user_Float_Value_6 + .size: 4 + .offset: 48 + .expression: {type: CommandArgument, size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + .variableType: {dataType: Float, pointerType: Value} + .value_kind: by_value + - .name: user_Float_Value_8 + .size: 4 + .offset: 52 + .expression: {type: CommandArgument, size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + .variableType: {dataType: Float, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_stride_0_9 + .size: 8 + .offset: 56 + .expression: {type: CommandArgument, size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_0_size_1_10 + .size: 8 + .offset: 64 + .expression: {type: CommandArgument, size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_2_stride_1_12 + .size: 8 + .offset: 72 + .expression: {type: CommandArgument, size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_4_stride_1_13 + .size: 8 + .offset: 80 + .expression: {type: CommandArgument, size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_stride_1_14 + .size: 8 + .offset: 88 + .expression: {type: CommandArgument, size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_extent_15 + .size: 8 + .offset: 96 + .expression: {type: CommandArgument, size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + .variableType: {dataType: Int64, pointerType: Value} + .value_kind: by_value + - .name: Tensor_15_pointer + .size: 8 + .offset: 104 + .expression: {type: CommandArgument, size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + .variableType: {dataType: Half, pointerType: PointerGlobal} + .address_space: global + .actual_access: read_write + .value_kind: global_buffer + .kernel_graph_dot: "digraph {\n\"coord1\"[label=\"User{Tensor_0_extent_0:I64}(1)\"];\n\"coord2\"[label=\"User{Tensor_2_extent_2:I64}(2)\"];\n\"coord3\"[label=\"User{Tensor_4_extent_4:I64}(3)\"];\n\"coord4\"[label=\"User{NA}(4)\"];\n\"coord5\"[label=\"User{NA}(5)\"];\n\"coord6\"[label=\"MacroTile{NA}(2/WAVE_Direct2LDS/MATRIX_A){64,64}-(8,2)(6)\"];\n\"coord7\"[label=\"MacroTile{NA}(2/WAVE_Direct2LDS/MATRIX_B){64,64}-(2,8)(7)\"];\n\"coord8\"[label=\"SubDimension{0, Tensor_0_size_0_8:I64}(8)\"];\n\"coord9\"[label=\"SubDimension{1, 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NA}(552)\"];\n\"coord553\"[label=\"Buffer(553)\",shape=box];\n\"coord554\"[label=\"Offset(554)\",shape=box];\n\"coord555\"[label=\"Stride(555)\",shape=box];\n\"coord556\"[label=\"Offset(556)\",shape=box];\n\"coord557\"[label=\"Stride(557)\",shape=box];\n\"coord558\"[label=\"Offset(558)\",shape=box];\n\"coord559\"[label=\"Stride(559)\",shape=box];\n\"coord560\"[label=\"Offset(560)\",shape=box];\n\"coord561\"[label=\"Stride(561)\",shape=box];\n\"coord562\"[label=\"Offset(562)\",shape=box];\n\"coord563\"[label=\"Stride(563)\",shape=box];\n\"coord564\"[label=\"Offset(564)\",shape=box];\n\"coord565\"[label=\"Stride(565)\",shape=box];\n\"coord566\"[label=\"Offset(566)\",shape=box];\n\"coord567\"[label=\"Stride(567)\",shape=box];\n\"coord568\"[label=\"Offset(568)\",shape=box];\n\"coord569\"[label=\"Stride(569)\",shape=box];\n\"coord570\"[label=\"Offset(570)\",shape=box];\n\"coord571\"[label=\"Stride(571)\",shape=box];\n\"coord572\"[label=\"Offset(572)\",shape=box];\n\"coord573\"[label=\"Stride(573)\",shape=box];\n\"coord574\"[label=\"Offset(574)\",shape=box];\n\"coord575\"[label=\"Stride(575)\",shape=box];\n\"coord576\"[label=\"Offset(576)\",shape=box];\n\"coord577\"[label=\"Stride(577)\",shape=box];\n\"coord578\"[label=\"Offset(578)\",shape=box];\n\"coord579\"[label=\"Stride(579)\",shape=box];\n\"coord580\"[label=\"Offset(580)\",shape=box];\n\"coord581\"[label=\"Stride(581)\",shape=box];\n\"coord582\"[label=\"Offset(582)\",shape=box];\n\"coord583\"[label=\"Stride(583)\",shape=box];\n\"coord584\"[label=\"Offset(584)\",shape=box];\n\"coord585\"[label=\"Stride(585)\",shape=box];\n\"coord586\"[label=\"Offset(586)\",shape=box];\n\"coord587\"[label=\"Stride(587)\",shape=box];\n\"coord588\"[label=\"Offset(588)\",shape=box];\n\"coord589\"[label=\"Stride(589)\",shape=box];\n\"coord590\"[label=\"Offset(590)\",shape=box];\n\"coord591\"[label=\"Stride(591)\",shape=box];\n\"coord592\"[label=\"Offset(592)\",shape=box];\n\"coord593\"[label=\"Stride(593)\",shape=box];\n\"coord594\"[label=\"Offset(594)\",shape=box];\n\"coord595\"[label=\"Stride(595)\",shape=box];\n\"coord596\"[label=\"Offset(596)\",shape=box];\n\"coord597\"[label=\"Stride(597)\",shape=box];\n\"coord598\"[label=\"Offset(598)\",shape=box];\n\"coord599\"[label=\"Stride(599)\",shape=box];\n\"coord600\"[label=\"Offset(600)\",shape=box];\n\"coord601\"[label=\"Stride(601)\",shape=box];\n\"coord602\"[label=\"Offset(602)\",shape=box];\n\"coord603\"[label=\"Stride(603)\",shape=box];\n\"coord604\"[label=\"Offset(604)\",shape=box];\n\"coord605\"[label=\"Stride(605)\",shape=box];\n\"coord606\"[label=\"Offset(606)\",shape=box];\n\"coord607\"[label=\"Stride(607)\",shape=box];\n\"coord608\"[label=\"Offset(608)\",shape=box];\n\"coord609\"[label=\"Stride(609)\",shape=box];\n\"coord610\"[label=\"Offset(610)\",shape=box];\n\"coord611\"[label=\"Stride(611)\",shape=box];\n\"coord612\"[label=\"Offset(612)\",shape=box];\n\"coord613\"[label=\"Stride(613)\",shape=box];\n\"coord614\"[label=\"Offset(614)\",shape=box];\n\"coord615\"[label=\"Stride(615)\",shape=box];\n\"coord616\"[label=\"Offset(616)\",shape=box];\n\"coord617\"[label=\"Stride(617)\",shape=box];\n\"coord618\"[label=\"Offset(618)\",shape=box];\n\"coord619\"[label=\"Stride(619)\",shape=box];\n\"coord620\"[label=\"Offset(620)\",shape=box];\n\"coord621\"[label=\"Stride(621)\",shape=box];\n\"coord622\"[label=\"Offset(622)\",shape=box];\n\"coord623\"[label=\"Stride(623)\",shape=box];\n\"coord624\"[label=\"Offset(624)\",shape=box];\n\"coord625\"[label=\"Stride(625)\",shape=box];\n\"coord626\"[label=\"Offset(626)\",shape=box];\n\"coord627\"[label=\"Stride(627)\",shape=box];\n\"coord628\"[label=\"Offset(628)\",shape=box];\n\"coord629\"[label=\"Stride(629)\",shape=box];\n\"coord630\"[label=\"Offset(630)\",shape=box];\n\"coord631\"[label=\"Stride(631)\",shape=box];\n\"coord632\"[label=\"Alias(632)\",shape=box];\n\"coord633\"[label=\"Alias(633)\",shape=box];\n\"coord634\"[label=\"Alias(634)\",shape=box];\n\"coord635\"[label=\"Alias(635)\",shape=box];\n\"coord636\"[label=\"Alias(636)\",shape=box];\n\"coord637\"[label=\"Alias(637)\",shape=box];\n\"coord638\"[label=\"Alias(638)\",shape=box];\n\"coord639\"[label=\"Alias(639)\",shape=box];\n\"coord640\"[label=\"Alias(640)\",shape=box];\n\"coord641\"[label=\"Alias(641)\",shape=box];\n\"coord642\"[label=\"Alias(642)\",shape=box];\n\"coord643\"[label=\"Alias(643)\",shape=box];\n\"coord644\"[label=\"Alias(644)\",shape=box];\n\"coord645\"[label=\"Alias(645)\",shape=box];\n\"coord646\"[label=\"Alias(646)\",shape=box];\n\"coord647\"[label=\"Alias(647)\",shape=box];\n\"coord648\"[label=\"Alias(648)\",shape=box];\n\"coord649\"[label=\"Alias(649)\",shape=box];\n\"coord650\"[label=\"Alias(650)\",shape=box];\n\"coord651\"[label=\"Alias(651)\",shape=box];\n\"coord652\"[label=\"Alias(652)\",shape=box];\n\"coord653\"[label=\"Alias(653)\",shape=box];\n\"coord654\"[label=\"Alias(654)\",shape=box];\n\"coord655\"[label=\"Alias(655)\",shape=box];\n\"coord656\"[label=\"Alias(656)\",shape=box];\n\"coord657\"[label=\"Alias(657)\",shape=box];\n\"coord1\" -> \"coord10\"\n\"coord1\" -> \"coord12\"\n\"coord1\" -> \"coord66\"\n\"coord1\" -> \"coord474\"\n\"coord1\" -> \"coord475\"\n\"coord1\" -> \"coord478\"\n\"coord1\" -> \"coord479\"\n\"coord1\" -> \"coord480\"\n\"coord1\" -> \"coord481\"\n\"coord1\" -> \"coord482\"\n\"coord1\" -> \"coord483\"\n\"coord1\" -> \"coord484\"\n\"coord1\" -> \"coord485\"\n\"coord1\" -> \"coord486\"\n\"coord1\" -> \"coord487\"\n\"coord1\" -> \"coord488\"\n\"coord1\" -> \"coord489\"\n\"coord1\" -> \"coord490\"\n\"coord1\" -> \"coord491\"\n\"coord1\" -> \"coord492\"\n\"coord2\" -> \"coord18\"\n\"coord2\" -> \"coord20\"\n\"coord2\" -> \"coord126\"\n\"coord2\" -> \"coord493\"\n\"coord2\" -> \"coord494\"\n\"coord2\" -> \"coord497\"\n\"coord2\" -> \"coord498\"\n\"coord2\" -> \"coord499\"\n\"coord2\" -> \"coord500\"\n\"coord2\" -> \"coord501\"\n\"coord2\" -> \"coord502\"\n\"coord2\" -> \"coord503\"\n\"coord2\" -> \"coord504\"\n\"coord2\" -> \"coord505\"\n\"coord2\" -> \"coord506\"\n\"coord2\" -> \"coord507\"\n\"coord2\" -> \"coord508\"\n\"coord2\" -> \"coord509\"\n\"coord2\" -> \"coord510\"\n\"coord2\" -> \"coord511\"\n\"coord3\" -> \"coord28\"\n\"coord3\" -> \"coord30\"\n\"coord3\" -> \"coord207\"\n\"coord3\" -> \"coord512\"\n\"coord3\" -> \"coord513\"\n\"coord3\" -> \"coord516\"\n\"coord3\" -> \"coord517\"\n\"coord4\" -> \"coord34\"\n\"coord5\" -> \"coord25\"\n\"coord6\" -> \"coord14\"\n\"coord6\" -> \"coord36\"\n\"coord7\" -> \"coord22\"\n\"coord7\" -> \"coord36\"\n\"coord8\" -> \"coord52\"\n\"coord9\" -> \"coord53\"\n\"coord10\" -> \"coord8\"\n\"coord10\" -> \"coord9\"\n\"coord12\" -> \"coord11\"\n\"coord13\" -> \"coord15\"\n\"coord13\" -> \"coord107\"\n\"coord13\" -> \"coord530\"\n\"coord13\" -> \"coord531\"\n\"coord13\" -> \"coord532\"\n\"coord13\" -> \"coord533\"\n\"coord14\" -> \"coord13\"\n\"coord15\" -> \"coord11\"\n\"coord16\" -> \"coord112\"\n\"coord17\" -> \"coord113\"\n\"coord18\" -> \"coord16\"\n\"coord18\" -> \"coord17\"\n\"coord20\" -> \"coord19\"\n\"coord21\" -> \"coord23\"\n\"coord21\" -> \"coord167\"\n\"coord21\" -> \"coord546\"\n\"coord21\" -> \"coord547\"\n\"coord21\" -> \"coord548\"\n\"coord21\" -> \"coord549\"\n\"coord22\" -> \"coord21\"\n\"coord23\" -> \"coord19\"\n\"coord24\" -> \"coord32\"\n\"coord25\" -> \"coord24\"\n\"coord26\" -> \"coord172\"\n\"coord27\" -> \"coord173\"\n\"coord28\" -> \"coord26\"\n\"coord28\" -> \"coord27\"\n\"coord29\" -> \"coord32\"\n\"coord30\" -> \"coord29\"\n\"coord31\" -> \"coord40\"\n\"coord32\" -> \"coord31\"\n\"coord33\" -> \"coord38\"\n\"coord34\" -> \"coord33\"\n\"coord35\" -> \"coord38\"\n\"coord36\" -> \"coord35\"\n\"coord37\" -> \"coord40\"\n\"coord38\" -> \"coord37\"\n\"coord39\" -> \"coord42\"\n\"coord40\" -> \"coord39\"\n\"coord41\" -> \"coord47\"\n\"coord41\" -> \"coord244\"\n\"coord42\" -> \"coord41\"\n\"coord43\" -> \"coord46\"\n\"coord44\" -> \"coord46\"\n\"coord46\" -> \"coord45\"\n\"coord47\" -> \"coord45\"\n\"coord48\" -> \"coord302\"\n\"coord49\" -> \"coord314\"\n\"coord50\" -> \"coord64\"\n\"coord51\" -> \"coord65\"\n\"coord52\" -> \"coord48\"\n\"coord52\" -> \"coord50\"\n\"coord53\" -> \"coord49\"\n\"coord53\" -> \"coord51\"\n\"coord54\" -> \"coord63\"\n\"coord55\" -> \"coord63\"\n\"coord56\" -> \"coord61\"\n\"coord57\" -> \"coord62\"\n\"coord61\" -> \"coord59\"\n\"coord62\" -> \"coord60\"\n\"coord63\" -> \"coord58\"\n\"coord64\" -> \"coord56\"\n\"coord64\" -> \"coord54\"\n\"coord65\" -> \"coord55\"\n\"coord65\" -> \"coord57\"\n\"coord66\" -> \"coord6\"\n\"coord67\" -> \"coord81\"\n\"coord68\" -> \"coord81\"\n\"coord69\" -> \"coord79\"\n\"coord70\" -> \"coord80\"\n\"coord71\" -> \"coord79\"\n\"coord72\" -> \"coord80\"\n\"coord73\" -> \"coord78\"\n\"coord74\" -> \"coord76\"\n\"coord74\" -> \"coord518\"\n\"coord74\" -> \"coord519\"\n\"coord74\" -> \"coord522\"\n\"coord74\" -> \"coord523\"\n\"coord74\" -> \"coord526\"\n\"coord74\" -> \"coord527\"\n\"coord74\" -> \"coord560\"\n\"coord74\" -> \"coord561\"\n\"coord74\" -> \"coord564\"\n\"coord74\" -> \"coord565\"\n\"coord74\" -> \"coord584\"\n\"coord74\" -> \"coord585\"\n\"coord74\" -> \"coord588\"\n\"coord74\" -> \"coord589\"\n\"coord74\" -> \"coord608\"\n\"coord74\" -> \"coord609\"\n\"coord74\" -> \"coord612\"\n\"coord74\" -> \"coord613\"\n\"coord75\" -> \"coord77\"\n\"coord75\" -> \"coord520\"\n\"coord75\" -> \"coord521\"\n\"coord75\" -> \"coord524\"\n\"coord75\" -> \"coord525\"\n\"coord75\" -> \"coord528\"\n\"coord75\" -> \"coord529\"\n\"coord75\" -> \"coord562\"\n\"coord75\" -> \"coord563\"\n\"coord75\" -> \"coord566\"\n\"coord75\" -> \"coord567\"\n\"coord75\" -> \"coord586\"\n\"coord75\" -> \"coord587\"\n\"coord75\" -> \"coord590\"\n\"coord75\" -> \"coord591\"\n\"coord75\" -> \"coord610\"\n\"coord75\" -> \"coord611\"\n\"coord75\" -> \"coord614\"\n\"coord75\" -> \"coord615\"\n\"coord76\" -> \"coord71\"\n\"coord77\" -> \"coord72\"\n\"coord78\" -> \"coord69\"\n\"coord78\" -> \"coord70\"\n\"coord79\" -> \"coord67\"\n\"coord80\" -> \"coord68\"\n\"coord81\" -> \"coord13\"\n\"coord82\" -> \"coord91\"\n\"coord83\" -> \"coord92\"\n\"coord85\" -> \"coord86\"\n\"coord86\" -> \"coord11\"\n\"coord87\" -> \"coord106\"\n\"coord88\" -> \"coord251\"\n\"coord89\" -> \"coord104\"\n\"coord90\" -> \"coord103\"\n\"coord91\" -> \"coord87\"\n\"coord91\" -> \"coord89\"\n\"coord92\" -> \"coord88\"\n\"coord92\" -> \"coord90\"\n\"coord93\" -> \"coord98\"\n\"coord94\" -> \"coord98\"\n\"coord95\" -> \"coord99\"\n\"coord96\" -> \"coord99\"\n\"coord98\" -> \"coord95\"\n\"coord99\" -> \"coord84\"\n\"coord101\" -> \"coord104\"\n\"coord102\" -> \"coord105\"\n\"coord103\" -> \"coord101\"\n\"coord103\" -> \"coord102\"\n\"coord104\" -> \"coord96\"\n\"coord105\" -> \"coord97\"\n\"coord106\" -> \"coord93\"\n\"coord107\" -> \"coord82\"\n\"coord107\" -> \"coord83\"\n\"coord108\" -> \"coord315\"\n\"coord109\" -> \"coord304\"\n\"coord110\" -> \"coord124\"\n\"coord111\" -> \"coord125\"\n\"coord112\" -> \"coord108\"\n\"coord112\" -> \"coord110\"\n\"coord113\" -> \"coord109\"\n\"coord113\" -> \"coord111\"\n\"coord114\" -> \"coord123\"\n\"coord115\" -> \"coord123\"\n\"coord116\" -> \"coord121\"\n\"coord117\" -> \"coord122\"\n\"coord121\" -> \"coord120\"\n\"coord122\" -> \"coord119\"\n\"coord123\" -> \"coord118\"\n\"coord124\" -> \"coord114\"\n\"coord124\" -> \"coord116\"\n\"coord125\" -> \"coord117\"\n\"coord125\" -> \"coord115\"\n\"coord126\" -> \"coord7\"\n\"coord127\" -> \"coord141\"\n\"coord128\" -> \"coord141\"\n\"coord129\" -> \"coord139\"\n\"coord130\" -> \"coord140\"\n\"coord131\" -> \"coord139\"\n\"coord132\" -> \"coord140\"\n\"coord133\" -> \"coord138\"\n\"coord134\" -> \"coord137\"\n\"coord134\" -> \"coord534\"\n\"coord134\" -> \"coord535\"\n\"coord134\" -> \"coord538\"\n\"coord134\" -> \"coord539\"\n\"coord134\" -> \"coord542\"\n\"coord134\" -> \"coord543\"\n\"coord134\" -> \"coord572\"\n\"coord134\" -> \"coord573\"\n\"coord134\" -> \"coord576\"\n\"coord134\" -> \"coord577\"\n\"coord134\" -> \"coord596\"\n\"coord134\" -> \"coord597\"\n\"coord134\" -> \"coord600\"\n\"coord134\" -> \"coord601\"\n\"coord134\" -> \"coord620\"\n\"coord134\" -> \"coord621\"\n\"coord134\" -> \"coord624\"\n\"coord134\" -> \"coord625\"\n\"coord135\" -> \"coord136\"\n\"coord135\" -> \"coord536\"\n\"coord135\" -> \"coord537\"\n\"coord135\" -> \"coord540\"\n\"coord135\" -> \"coord541\"\n\"coord135\" -> \"coord544\"\n\"coord135\" -> \"coord545\"\n\"coord135\" -> \"coord574\"\n\"coord135\" -> \"coord575\"\n\"coord135\" -> \"coord578\"\n\"coord135\" -> \"coord579\"\n\"coord135\" -> \"coord598\"\n\"coord135\" -> \"coord599\"\n\"coord135\" -> \"coord602\"\n\"coord135\" -> \"coord603\"\n\"coord135\" -> \"coord622\"\n\"coord135\" -> \"coord623\"\n\"coord135\" -> \"coord626\"\n\"coord135\" -> \"coord627\"\n\"coord136\" -> \"coord131\"\n\"coord137\" -> \"coord132\"\n\"coord138\" -> \"coord130\"\n\"coord138\" -> \"coord129\"\n\"coord139\" -> \"coord127\"\n\"coord140\" -> \"coord128\"\n\"coord141\" -> \"coord21\"\n\"coord142\" -> \"coord151\"\n\"coord143\" -> \"coord152\"\n\"coord145\" -> \"coord146\"\n\"coord146\" -> \"coord19\"\n\"coord147\" -> \"coord252\"\n\"coord148\" -> \"coord166\"\n\"coord149\" -> \"coord163\"\n\"coord150\" -> \"coord164\"\n\"coord151\" -> \"coord147\"\n\"coord151\" -> \"coord149\"\n\"coord152\" -> \"coord148\"\n\"coord152\" -> \"coord150\"\n\"coord153\" -> \"coord158\"\n\"coord154\" -> \"coord158\"\n\"coord155\" -> \"coord159\"\n\"coord156\" -> \"coord159\"\n\"coord158\" -> \"coord155\"\n\"coord159\" -> \"coord144\"\n\"coord161\" -> \"coord164\"\n\"coord162\" -> \"coord165\"\n\"coord163\" -> \"coord161\"\n\"coord163\" -> \"coord162\"\n\"coord164\" -> \"coord156\"\n\"coord165\" -> \"coord157\"\n\"coord166\" -> \"coord154\"\n\"coord167\" -> \"coord143\"\n\"coord167\" -> \"coord142\"\n\"coord168\" -> \"coord306\"\n\"coord169\" -> \"coord308\"\n\"coord170\" -> \"coord181\"\n\"coord171\" -> \"coord182\"\n\"coord172\" -> \"coord168\"\n\"coord172\" -> \"coord170\"\n\"coord173\" -> \"coord169\"\n\"coord173\" -> \"coord171\"\n\"coord175\" -> \"coord176\"\n\"coord176\" -> \"coord29\"\n\"coord177\" -> \"coord205\"\n\"coord178\" -> \"coord206\"\n\"coord179\" -> \"coord199\"\n\"coord180\" -> \"coord200\"\n\"coord181\" -> \"coord177\"\n\"coord181\" -> \"coord179\"\n\"coord182\" -> \"coord178\"\n\"coord182\" -> \"coord180\"\n\"coord183\" -> \"coord188\"\n\"coord184\" -> \"coord188\"\n\"coord185\" -> \"coord189\"\n\"coord186\" -> \"coord189\"\n\"coord188\" -> \"coord185\"\n\"coord189\" -> \"coord174\"\n\"coord192\" -> \"coord203\"\n\"coord193\" -> \"coord203\"\n\"coord194\" -> \"coord204\"\n\"coord195\" -> \"coord204\"\n\"coord196\" -> \"coord202\"\n\"coord197\" -> \"coord201\"\n\"coord198\" -> \"coord201\"\n\"coord199\" -> \"coord197\"\n\"coord199\" -> \"coord193\"\n\"coord200\" -> \"coord198\"\n\"coord200\" -> \"coord195\"\n\"coord201\" -> \"coord196\"\n\"coord202\" -> \"coord192\"\n\"coord202\" -> \"coord194\"\n\"coord203\" -> \"coord187\"\n\"coord204\" -> \"coord186\"\n\"coord205\" -> \"coord183\"\n\"coord206\" -> \"coord184\"\n\"coord207\" -> \"coord29\"\n\"coord208\" -> \"coord212\"\n\"coord209\" -> \"coord213\"\n\"coord210\" -> \"coord212\"\n\"coord211\" -> \"coord213\"\n\"coord212\" -> \"coord43\"\n\"coord213\" -> \"coord44\"\n\"coord214\" -> \"coord243\"\n\"coord216\" -> \"coord227\"\n\"coord217\" -> \"coord228\"\n\"coord218\" -> \"coord227\"\n\"coord219\" -> \"coord228\"\n\"coord220\" -> \"coord237\"\n\"coord220\" -> \"coord550\"\n\"coord220\" -> \"coord551\"\n\"coord220\" -> \"coord556\"\n\"coord220\" -> \"coord557\"\n\"coord221\" -> \"coord241\"\n\"coord221\" -> \"coord554\"\n\"coord221\" -> \"coord555\"\n\"coord221\" -> \"coord558\"\n\"coord221\" -> \"coord559\"\n\"coord222\" -> \"coord237\"\n\"coord223\" -> \"coord242\"\n\"coord224\" -> \"coord238\"\n\"coord225\" -> \"coord241\"\n\"coord226\" -> \"coord242\"\n\"coord227\" -> \"coord210\"\n\"coord228\" -> \"coord211\"\n\"coord229\" -> \"coord239\"\n\"coord230\" -> \"coord240\"\n\"coord231\" -> \"coord232\"\n\"coord232\" -> \"coord229\"\n\"coord232\" -> \"coord230\"\n\"coord233\" -> \"coord236\"\n\"coord234\" -> \"coord235\"\n\"coord235\" -> \"coord220\"\n\"coord235\" -> \"coord221\"\n\"coord236\" -> \"coord222\"\n\"coord236\" -> \"coord223\"\n\"coord237\" -> \"coord224\"\n\"coord238\" -> \"coord225\"\n\"coord238\" -> \"coord226\"\n\"coord239\" -> \"coord216\"\n\"coord240\" -> \"coord217\"\n\"coord241\" -> \"coord218\"\n\"coord242\" -> \"coord219\"\n\"coord243\" -> \"coord231\"\n\"coord243\" -> \"coord233\"\n\"coord244\" -> \"coord45\"\n\"coord245\" -> \"coord247\"\n\"coord247\" -> \"coord246\"\n\"coord251\" -> \"coord250\"\n\"coord252\" -> \"coord250\"\n\"coord253\" -> \"coord254\"\n\"coord254\" -> \"coord11\"\n\"coord255\" -> \"coord256\"\n\"coord256\" -> \"coord19\"\n\"coord257\" -> \"coord258\"\n\"coord258\" -> \"coord11\"\n\"coord259\" -> \"coord260\"\n\"coord260\" -> \"coord19\"\n\"coord261\" -> \"coord262\"\n\"coord262\" -> \"coord11\"\n\"coord263\" -> \"coord264\"\n\"coord264\" -> \"coord19\"\n\"coord265\" -> \"coord266\"\n\"coord266\" -> \"coord11\"\n\"coord267\" -> \"coord268\"\n\"coord268\" -> \"coord19\"\n\"coord269\" -> \"coord270\"\n\"coord270\" -> \"coord11\"\n\"coord271\" -> \"coord272\"\n\"coord272\" -> \"coord19\"\n\"coord273\" -> \"coord274\"\n\"coord274\" -> \"coord11\"\n\"coord275\" -> \"coord276\"\n\"coord276\" -> \"coord19\"\n\"coord277\" -> \"coord278\"\n\"coord278\" -> \"coord11\"\n\"coord279\" -> \"coord280\"\n\"coord280\" -> \"coord19\"\n\"coord291\" -> \"coord292\"\n\"coord292\" -> \"coord29\"\n\"coord293\" -> \"coord294\"\n\"coord294\" -> \"coord31\"\n\"coord295\" -> \"coord296\"\n\"coord296\" -> \"coord37\"\n\"coord297\" -> \"coord298\"\n\"coord298\" -> \"coord39\"\n\"coord299\" -> \"coord300\"\n\"coord300\" -> \"coord41\"\n\"coord302\" -> \"coord301\"\n\"coord304\" -> \"coord303\"\n\"coord306\" -> \"coord305\"\n\"coord308\" -> \"coord307\"\n\"coord309\" -> \"coord310\"\n\"coord310\" -> \"coord208\"\n\"coord311\" -> \"coord312\"\n\"coord312\" -> \"coord209\"\n\"coord314\" -> \"coord246\"\n\"coord314\" -> \"coord313\"\n\"coord315\" -> \"coord246\"\n\"coord315\" -> \"coord313\"\n\"coord316\" -> \"coord317\"\n\"coord317\" -> \"coord246\"\n\"coord318\" -> \"coord319\"\n\"coord319\" -> \"coord6\"\n\"coord320\" -> \"coord321\"\n\"coord321\" -> \"coord7\"\n\"coord322\" -> \"coord323\"\n\"coord323\" -> \"coord11\"\n\"coord324\" -> \"coord325\"\n\"coord325\" -> \"coord19\"\n\"coord326\" -> \"coord327\"\n\"coord327\" -> \"coord11\"\n\"coord328\" -> \"coord329\"\n\"coord329\" -> \"coord19\"\n\"coord330\" -> \"coord331\"\n\"coord331\" -> \"coord11\"\n\"coord332\" -> \"coord333\"\n\"coord333\" -> \"coord19\"\n\"coord334\" -> \"coord335\"\n\"coord335\" -> \"coord11\"\n\"coord336\" -> \"coord337\"\n\"coord337\" -> \"coord19\"\n\"coord338\" -> \"coord339\"\n\"coord339\" -> \"coord11\"\n\"coord340\" -> \"coord341\"\n\"coord341\" -> \"coord19\"\n\"coord342\" -> \"coord343\"\n\"coord343\" -> \"coord11\"\n\"coord344\" -> \"coord345\"\n\"coord345\" -> \"coord19\"\n\"coord346\" -> \"coord347\"\n\"coord347\" -> \"coord11\"\n\"coord348\" -> \"coord349\"\n\"coord349\" -> \"coord19\"\n\"coord350\" -> \"coord351\"\n\"coord351\" -> \"coord11\"\n\"coord352\" -> \"coord353\"\n\"coord353\" -> \"coord19\"\n\"coord354\" -> \"coord355\"\n\"coord355\" -> \"coord6\"\n\"coord356\" -> \"coord357\"\n\"coord356\" -> \"coord568\"\n\"coord356\" -> \"coord569\"\n\"coord356\" -> \"coord570\"\n\"coord356\" -> \"coord571\"\n\"coord357\" -> \"coord13\"\n\"coord358\" -> \"coord359\"\n\"coord359\" -> \"coord7\"\n\"coord360\" -> \"coord361\"\n\"coord360\" -> \"coord580\"\n\"coord360\" -> \"coord581\"\n\"coord360\" -> \"coord582\"\n\"coord360\" -> \"coord583\"\n\"coord361\" -> \"coord21\"\n\"coord362\" -> \"coord363\"\n\"coord362\" -> \"coord632\"\n\"coord363\" -> \"coord11\"\n\"coord364\" -> \"coord365\"\n\"coord364\" -> \"coord633\"\n\"coord365\" -> \"coord19\"\n\"coord366\" -> \"coord367\"\n\"coord366\" -> \"coord634\"\n\"coord367\" -> \"coord11\"\n\"coord368\" -> \"coord369\"\n\"coord369\" -> \"coord19\"\n\"coord370\" -> \"coord371\"\n\"coord370\" -> \"coord635\"\n\"coord371\" -> \"coord11\"\n\"coord372\" -> \"coord373\"\n\"coord373\" -> \"coord19\"\n\"coord374\" -> \"coord375\"\n\"coord375\" -> \"coord11\"\n\"coord376\" -> \"coord377\"\n\"coord377\" -> \"coord19\"\n\"coord378\" -> \"coord379\"\n\"coord378\" -> \"coord636\"\n\"coord379\" -> \"coord11\"\n\"coord380\" -> \"coord381\"\n\"coord381\" -> \"coord19\"\n\"coord382\" -> \"coord383\"\n\"coord383\" -> \"coord11\"\n\"coord384\" -> \"coord385\"\n\"coord385\" -> \"coord19\"\n\"coord386\" -> \"coord387\"\n\"coord386\" -> \"coord637\"\n\"coord387\" -> \"coord11\"\n\"coord388\" -> \"coord389\"\n\"coord389\" -> \"coord19\"\n\"coord390\" -> \"coord391\"\n\"coord391\" -> \"coord11\"\n\"coord392\" -> \"coord393\"\n\"coord393\" -> \"coord19\"\n\"coord394\" -> \"coord395\"\n\"coord395\" -> \"coord6\"\n\"coord396\" -> \"coord397\"\n\"coord396\" -> \"coord592\"\n\"coord396\" -> \"coord593\"\n\"coord396\" -> \"coord594\"\n\"coord396\" -> \"coord595\"\n\"coord397\" -> \"coord13\"\n\"coord398\" -> \"coord399\"\n\"coord399\" -> \"coord7\"\n\"coord400\" -> \"coord401\"\n\"coord400\" -> \"coord604\"\n\"coord400\" -> \"coord605\"\n\"coord400\" -> \"coord606\"\n\"coord400\" -> \"coord607\"\n\"coord401\" -> \"coord21\"\n\"coord402\" -> \"coord403\"\n\"coord402\" -> \"coord638\"\n\"coord403\" -> \"coord11\"\n\"coord404\" -> \"coord405\"\n\"coord404\" -> \"coord639\"\n\"coord405\" -> \"coord19\"\n\"coord406\" -> \"coord407\"\n\"coord406\" -> \"coord640\"\n\"coord407\" -> \"coord11\"\n\"coord408\" -> \"coord409\"\n\"coord408\" -> \"coord641\"\n\"coord409\" -> \"coord19\"\n\"coord410\" -> \"coord411\"\n\"coord410\" -> \"coord642\"\n\"coord411\" -> \"coord11\"\n\"coord412\" -> \"coord413\"\n\"coord412\" -> \"coord643\"\n\"coord413\" -> \"coord19\"\n\"coord414\" -> \"coord415\"\n\"coord414\" -> \"coord644\"\n\"coord415\" -> \"coord11\"\n\"coord416\" -> \"coord417\"\n\"coord416\" -> \"coord645\"\n\"coord417\" -> \"coord19\"\n\"coord418\" -> \"coord419\"\n\"coord418\" -> \"coord646\"\n\"coord419\" -> \"coord11\"\n\"coord420\" -> \"coord421\"\n\"coord420\" -> \"coord647\"\n\"coord421\" -> \"coord19\"\n\"coord422\" -> \"coord423\"\n\"coord422\" -> \"coord648\"\n\"coord423\" -> \"coord11\"\n\"coord424\" -> \"coord425\"\n\"coord424\" -> \"coord649\"\n\"coord425\" -> \"coord19\"\n\"coord426\" -> \"coord427\"\n\"coord426\" -> \"coord650\"\n\"coord427\" -> \"coord11\"\n\"coord428\" -> \"coord429\"\n\"coord428\" -> \"coord651\"\n\"coord429\" -> \"coord19\"\n\"coord430\" -> \"coord431\"\n\"coord431\" -> \"coord11\"\n\"coord432\" -> \"coord433\"\n\"coord432\" -> \"coord652\"\n\"coord433\" -> \"coord19\"\n\"coord434\" -> \"coord435\"\n\"coord435\" -> \"coord6\"\n\"coord436\" -> \"coord437\"\n\"coord436\" -> \"coord616\"\n\"coord436\" -> \"coord617\"\n\"coord436\" -> \"coord618\"\n\"coord436\" -> \"coord619\"\n\"coord437\" -> \"coord13\"\n\"coord438\" -> \"coord439\"\n\"coord439\" -> \"coord7\"\n\"coord440\" -> \"coord441\"\n\"coord440\" -> \"coord628\"\n\"coord440\" -> \"coord629\"\n\"coord440\" -> \"coord630\"\n\"coord440\" -> \"coord631\"\n\"coord441\" -> \"coord21\"\n\"coord442\" -> \"coord443\"\n\"coord442\" -> \"coord653\"\n\"coord443\" -> \"coord11\"\n\"coord444\" -> \"coord445\"\n\"coord444\" -> \"coord654\"\n\"coord445\" -> \"coord19\"\n\"coord446\" -> \"coord447\"\n\"coord446\" -> \"coord655\"\n\"coord447\" -> \"coord11\"\n\"coord448\" -> \"coord449\"\n\"coord449\" -> \"coord19\"\n\"coord450\" -> \"coord451\"\n\"coord450\" -> \"coord656\"\n\"coord451\" -> \"coord11\"\n\"coord452\" -> \"coord453\"\n\"coord453\" -> \"coord19\"\n\"coord454\" -> \"coord455\"\n\"coord454\" -> \"coord657\"\n\"coord455\" -> \"coord11\"\n\"coord456\" -> \"coord457\"\n\"coord457\" -> \"coord19\"\n\"coord458\" -> \"coord459\"\n\"coord459\" -> \"coord11\"\n\"coord460\" -> \"coord461\"\n\"coord461\" -> \"coord19\"\n\"coord462\" -> \"coord463\"\n\"coord463\" -> \"coord11\"\n\"coord464\" -> \"coord465\"\n\"coord465\" -> \"coord19\"\n\"coord466\" -> \"coord467\"\n\"coord467\" -> \"coord11\"\n\"coord468\" -> \"coord469\"\n\"coord469\" -> \"coord19\"\n\"coord470\" -> \"coord471\"\n\"coord471\" -> \"coord11\"\n\"coord472\" -> \"coord473\"\n\"coord473\" -> \"coord19\"\n\"coord474\" -> \"coord49\"\n\"coord475\" -> \"coord49\"\n\"coord476\" -> \"coord477\"\n\"coord477\" -> \"coord1\"\n\"coord478\" -> \"coord59\"\n\"coord479\" -> \"coord59\"\n\"coord480\" -> \"coord60\"\n\"coord481\" -> \"coord60\"\n\"coord482\" -> \"coord49\"\n\"coord483\" -> \"coord59\"\n\"coord484\" -> \"coord59\"\n\"coord485\" -> \"coord60\"\n\"coord486\" -> \"coord60\"\n\"coord487\" -> \"coord49\"\n\"coord488\" -> \"coord49\"\n\"coord489\" -> \"coord59\"\n\"coord490\" -> \"coord59\"\n\"coord491\" -> \"coord60\"\n\"coord492\" -> \"coord60\"\n\"coord493\" -> \"coord108\"\n\"coord494\" -> \"coord108\"\n\"coord495\" -> \"coord496\"\n\"coord496\" -> \"coord2\"\n\"coord497\" -> \"coord119\"\n\"coord498\" -> \"coord119\"\n\"coord499\" -> \"coord120\"\n\"coord500\" -> \"coord120\"\n\"coord501\" -> \"coord108\"\n\"coord502\" -> \"coord119\"\n\"coord503\" -> \"coord119\"\n\"coord504\" -> \"coord120\"\n\"coord505\" -> \"coord120\"\n\"coord506\" -> \"coord108\"\n\"coord507\" -> \"coord108\"\n\"coord508\" -> \"coord119\"\n\"coord509\" -> \"coord119\"\n\"coord510\" -> \"coord120\"\n\"coord511\" -> \"coord120\"\n\"coord512\" -> \"coord192\"\n\"coord513\" -> \"coord192\"\n\"coord514\" -> \"coord515\"\n\"coord515\" -> \"coord3\"\n\"coord516\" -> \"coord193\"\n\"coord517\" -> \"coord193\"\n\"coord518\" -> \"coord13\"\n\"coord519\" -> \"coord13\"\n\"coord520\" -> \"coord13\"\n\"coord521\" -> \"coord13\"\n\"coord522\" -> \"coord13\"\n\"coord523\" -> \"coord13\"\n\"coord524\" -> \"coord13\"\n\"coord525\" -> \"coord13\"\n\"coord526\" -> \"coord13\"\n\"coord527\" -> \"coord13\"\n\"coord528\" -> \"coord13\"\n\"coord529\" -> \"coord13\"\n\"coord530\" -> \"coord88\"\n\"coord531\" -> \"coord88\"\n\"coord532\" -> \"coord97\"\n\"coord533\" -> \"coord97\"\n\"coord534\" -> \"coord21\"\n\"coord535\" -> \"coord21\"\n\"coord536\" -> \"coord21\"\n\"coord537\" -> \"coord21\"\n\"coord538\" -> \"coord21\"\n\"coord539\" -> \"coord21\"\n\"coord540\" -> \"coord21\"\n\"coord541\" -> \"coord21\"\n\"coord542\" -> \"coord21\"\n\"coord543\" -> \"coord21\"\n\"coord544\" -> \"coord21\"\n\"coord545\" -> \"coord21\"\n\"coord546\" -> \"coord147\"\n\"coord547\" -> \"coord147\"\n\"coord548\" -> \"coord157\"\n\"coord549\" -> \"coord157\"\n\"coord550\" -> \"coord45\"\n\"coord551\" -> \"coord45\"\n\"coord552\" -> \"coord553\"\n\"coord553\" -> \"coord45\"\n\"coord554\" -> \"coord45\"\n\"coord555\" -> \"coord45\"\n\"coord556\" -> \"coord45\"\n\"coord557\" -> \"coord45\"\n\"coord558\" -> \"coord45\"\n\"coord559\" -> \"coord45\"\n\"coord560\" -> \"coord356\"\n\"coord561\" -> \"coord356\"\n\"coord562\" -> \"coord356\"\n\"coord563\" -> \"coord356\"\n\"coord564\" -> \"coord356\"\n\"coord565\" -> \"coord356\"\n\"coord566\" -> \"coord356\"\n\"coord567\" -> \"coord356\"\n\"coord568\" -> \"coord88\"\n\"coord569\" -> \"coord88\"\n\"coord570\" -> \"coord97\"\n\"coord571\" -> \"coord97\"\n\"coord572\" -> \"coord360\"\n\"coord573\" -> \"coord360\"\n\"coord574\" -> \"coord360\"\n\"coord575\" -> \"coord360\"\n\"coord576\" -> \"coord360\"\n\"coord577\" -> \"coord360\"\n\"coord578\" -> \"coord360\"\n\"coord579\" -> \"coord360\"\n\"coord580\" -> \"coord147\"\n\"coord581\" -> \"coord147\"\n\"coord582\" -> \"coord157\"\n\"coord583\" -> \"coord157\"\n\"coord584\" -> \"coord396\"\n\"coord585\" -> \"coord396\"\n\"coord586\" -> \"coord396\"\n\"coord587\" -> \"coord396\"\n\"coord588\" -> \"coord396\"\n\"coord589\" -> \"coord396\"\n\"coord590\" -> \"coord396\"\n\"coord591\" -> \"coord396\"\n\"coord592\" -> \"coord88\"\n\"coord593\" -> \"coord88\"\n\"coord594\" -> \"coord97\"\n\"coord595\" -> \"coord97\"\n\"coord596\" -> \"coord400\"\n\"coord597\" -> \"coord400\"\n\"coord598\" -> \"coord400\"\n\"coord599\" -> \"coord400\"\n\"coord600\" -> \"coord400\"\n\"coord601\" -> \"coord400\"\n\"coord602\" -> \"coord400\"\n\"coord603\" -> \"coord400\"\n\"coord604\" -> \"coord147\"\n\"coord605\" -> \"coord147\"\n\"coord606\" -> \"coord157\"\n\"coord607\" -> \"coord157\"\n\"coord608\" -> \"coord436\"\n\"coord609\" -> \"coord436\"\n\"coord610\" -> \"coord436\"\n\"coord611\" -> \"coord436\"\n\"coord612\" -> \"coord436\"\n\"coord613\" -> \"coord436\"\n\"coord614\" -> \"coord436\"\n\"coord615\" -> \"coord436\"\n\"coord616\" -> \"coord88\"\n\"coord617\" -> \"coord88\"\n\"coord618\" -> \"coord97\"\n\"coord619\" -> \"coord97\"\n\"coord620\" -> \"coord440\"\n\"coord621\" -> \"coord440\"\n\"coord622\" -> \"coord440\"\n\"coord623\" -> \"coord440\"\n\"coord624\" -> \"coord440\"\n\"coord625\" -> \"coord440\"\n\"coord626\" -> \"coord440\"\n\"coord627\" -> \"coord440\"\n\"coord628\" -> \"coord147\"\n\"coord629\" -> \"coord147\"\n\"coord630\" -> \"coord157\"\n\"coord631\" -> \"coord157\"\n\"coord632\" -> \"coord11\"\n\"coord633\" -> \"coord19\"\n\"coord634\" -> \"coord253\"\n\"coord635\" -> \"coord257\"\n\"coord636\" -> \"coord261\"\n\"coord637\" -> \"coord265\"\n\"coord638\" -> \"coord11\"\n\"coord639\" -> \"coord19\"\n\"coord640\" -> \"coord253\"\n\"coord641\" -> \"coord255\"\n\"coord642\" -> \"coord257\"\n\"coord643\" -> \"coord259\"\n\"coord644\" -> \"coord269\"\n\"coord645\" -> \"coord263\"\n\"coord646\" -> \"coord273\"\n\"coord647\" -> \"coord267\"\n\"coord648\" -> \"coord277\"\n\"coord649\" -> \"coord271\"\n\"coord650\" -> \"coord261\"\n\"coord651\" -> \"coord275\"\n\"coord652\" -> \"coord279\"\n\"coord653\" -> \"coord11\"\n\"coord654\" -> \"coord19\"\n\"coord655\" -> \"coord253\"\n\"coord656\" -> \"coord257\"\n\"coord657\" -> \"coord265\"\n{\nrank=same\n\"coord8\"->\"coord9\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord16\"->\"coord17\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord26\"->\"coord27\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord24\"->\"coord29\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord6\"->\"coord7\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord33\"->\"coord35\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord31\"->\"coord37\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord43\"->\"coord44\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord48\"->\"coord50\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord49\"->\"coord51\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord54\"->\"coord55\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord56\"->\"coord54\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord55\"->\"coord57\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord69\"->\"coord70\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord71\"->\"coord69\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord70\"->\"coord72\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord67\"->\"coord68\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord87\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord88\"->\"coord90\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord93\"->\"coord94\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord95\"->\"coord96\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord102\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord82\"->\"coord83\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord108\"->\"coord110\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord109\"->\"coord111\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord115\"->\"coord114\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord114\"->\"coord116\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord117\"->\"coord115\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord130\"->\"coord129\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord129\"->\"coord131\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord132\"->\"coord130\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord128\"->\"coord127\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord147\"->\"coord149\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord148\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord153\"->\"coord154\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord155\"->\"coord156\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord162\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord143\"->\"coord142\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord168\"->\"coord170\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord169\"->\"coord171\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord177\"->\"coord179\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord178\"->\"coord180\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord183\"->\"coord184\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord185\"->\"coord186\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord198\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord198\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord194\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord194\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord208\"->\"coord210\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord209\"->\"coord211\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord216\"->\"coord218\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord217\"->\"coord219\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord229\"->\"coord230\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord222\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord222\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord226\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord226\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord231\"->\"coord233\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\nsubgraph clusterCF {label = \"Control Graph\";\n\"cntrl1\"[label=\"Kernel(1)\"];\n\"cntrl2\"[label=\"LoadVGPR Value: Float(2)\"];\n\"cntrl24\"[label=\"LoadVGPR Value: Float(24)\"];\n\"cntrl29\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29)\"];\n\"cntrl35\"[label=\"Assign VGPR Convert(DataFlowTag(39)NA)H(35)\"];\n\"cntrl37\"[label=\"StoreTiled Value: Halfx2(37)\"];\n\"cntrl39\"[label=\"ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39)\"];\n\"cntrl40\"[label=\"Assign SGPR 0:U32(40)\"];\n\"cntrl41\"[label=\"Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41)\"];\n\"cntrl42\"[label=\"Initialize(42)\",shape=box];\n\"cntrl44\"[label=\"Assign ACCVGPR 0.00000:S(44)\"];\n\"cntrl47\"[label=\"SetCoordinate(47)\"];\n\"cntrl49\"[label=\"LoadLDSTile{Value: Halfx2}(49)\"];\n\"cntrl50\"[label=\"Body(50)\",shape=box];\n\"cntrl52\"[label=\"SetCoordinate(52)\"];\n\"cntrl54\"[label=\"LoadLDSTile{Value: Halfx2}(54)\"];\n\"cntrl55\"[label=\"Body(55)\",shape=box];\n\"cntrl57\"[label=\"Multiply(57)\"];\n\"cntrl58\"[label=\"SetCoordinate(58)\"];\n\"cntrl60\"[label=\"LoadLDSTile{Value: Halfx2}(60)\"];\n\"cntrl61\"[label=\"Body(61)\",shape=box];\n\"cntrl62\"[label=\"SetCoordinate(62)\"];\n\"cntrl64\"[label=\"LoadLDSTile{Value: Halfx2}(64)\"];\n\"cntrl65\"[label=\"Body(65)\",shape=box];\n\"cntrl66\"[label=\"Multiply(66)\"];\n\"cntrl67\"[label=\"SetCoordinate(67)\"];\n\"cntrl69\"[label=\"LoadLDSTile{Value: Halfx2}(69)\"];\n\"cntrl70\"[label=\"Body(70)\",shape=box];\n\"cntrl71\"[label=\"SetCoordinate(71)\"];\n\"cntrl73\"[label=\"LoadLDSTile{Value: Halfx2}(73)\"];\n\"cntrl74\"[label=\"Body(74)\",shape=box];\n\"cntrl75\"[label=\"Multiply(75)\"];\n\"cntrl76\"[label=\"SetCoordinate(76)\"];\n\"cntrl78\"[label=\"LoadLDSTile{Value: Halfx2}(78)\"];\n\"cntrl79\"[label=\"Body(79)\",shape=box];\n\"cntrl80\"[label=\"SetCoordinate(80)\"];\n\"cntrl82\"[label=\"LoadLDSTile{Value: Halfx2}(82)\"];\n\"cntrl83\"[label=\"Body(83)\",shape=box];\n\"cntrl84\"[label=\"Multiply(84)\"];\n\"cntrl85\"[label=\"SetCoordinate(85)\"];\n\"cntrl87\"[label=\"LoadLDSTile{Value: Halfx2}(87)\"];\n\"cntrl88\"[label=\"Body(88)\",shape=box];\n\"cntrl89\"[label=\"SetCoordinate(89)\"];\n\"cntrl91\"[label=\"LoadLDSTile{Value: Halfx2}(91)\"];\n\"cntrl92\"[label=\"Body(92)\",shape=box];\n\"cntrl93\"[label=\"Multiply(93)\"];\n\"cntrl94\"[label=\"SetCoordinate(94)\"];\n\"cntrl96\"[label=\"LoadLDSTile{Value: Halfx2}(96)\"];\n\"cntrl97\"[label=\"Body(97)\",shape=box];\n\"cntrl98\"[label=\"SetCoordinate(98)\"];\n\"cntrl100\"[label=\"LoadLDSTile{Value: Halfx2}(100)\"];\n\"cntrl101\"[label=\"Body(101)\",shape=box];\n\"cntrl102\"[label=\"Multiply(102)\"];\n\"cntrl103\"[label=\"SetCoordinate(103)\"];\n\"cntrl105\"[label=\"LoadLDSTile{Value: Halfx2}(105)\"];\n\"cntrl106\"[label=\"Body(106)\",shape=box];\n\"cntrl107\"[label=\"SetCoordinate(107)\"];\n\"cntrl109\"[label=\"LoadLDSTile{Value: Halfx2}(109)\"];\n\"cntrl110\"[label=\"Body(110)\",shape=box];\n\"cntrl111\"[label=\"Multiply(111)\"];\n\"cntrl112\"[label=\"SetCoordinate(112)\"];\n\"cntrl114\"[label=\"LoadLDSTile{Value: Halfx2}(114)\"];\n\"cntrl115\"[label=\"Body(115)\",shape=box];\n\"cntrl116\"[label=\"SetCoordinate(116)\"];\n\"cntrl118\"[label=\"LoadLDSTile{Value: Halfx2}(118)\"];\n\"cntrl119\"[label=\"Body(119)\",shape=box];\n\"cntrl120\"[label=\"Multiply(120)\"];\n\"cntrl177\"[label=\"ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177)\"];\n\"cntrl185\"[label=\"NOP(185)\"];\n\"cntrl186\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186)\"];\n\"cntrl187\"[label=\"Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187)\"];\n\"cntrl188\"[label=\"Assign VGPR Convert(DataFlowTag(297)NA)H(188)\"];\n\"cntrl189\"[label=\"StoreTiled Value: Halfx2(189)\"];\n\"cntrl190\"[label=\"LoadTiled Value: Halfx2(190)\"];\n\"cntrl191\"[label=\"Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191)\"];\n\"cntrl194\"[label=\"Sequence(194)\",shape=box];\n\"cntrl203\"[label=\"Sequence(203)\",shape=box];\n\"cntrl217\"[label=\"ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217)\"];\n\"cntrl218\"[label=\"Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218)\"];\n\"cntrl219\"[label=\"Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219)\"];\n\"cntrl220\"[label=\"Initialize(220)\",shape=box];\n\"cntrl224\"[label=\"SetCoordinate(224)\"];\n\"cntrl225\"[label=\"LoadLDSTile{Value: Halfx2}(225)\"];\n\"cntrl226\"[label=\"SetCoordinate(226)\"];\n\"cntrl227\"[label=\"LoadLDSTile{Value: Halfx2}(227)\"];\n\"cntrl228\"[label=\"Multiply(228)\"];\n\"cntrl229\"[label=\"SetCoordinate(229)\"];\n\"cntrl230\"[label=\"LoadLDSTile{Value: Halfx2}(230)\"];\n\"cntrl231\"[label=\"SetCoordinate(231)\"];\n\"cntrl232\"[label=\"LoadLDSTile{Value: Halfx2}(232)\"];\n\"cntrl233\"[label=\"Multiply(233)\"];\n\"cntrl234\"[label=\"SetCoordinate(234)\"];\n\"cntrl235\"[label=\"LoadLDSTile{Value: Halfx2}(235)\"];\n\"cntrl236\"[label=\"SetCoordinate(236)\"];\n\"cntrl237\"[label=\"LoadLDSTile{Value: Halfx2}(237)\"];\n\"cntrl238\"[label=\"Multiply(238)\"];\n\"cntrl239\"[label=\"SetCoordinate(239)\"];\n\"cntrl240\"[label=\"LoadLDSTile{Value: Halfx2}(240)\"];\n\"cntrl241\"[label=\"SetCoordinate(241)\"];\n\"cntrl242\"[label=\"LoadLDSTile{Value: Halfx2}(242)\"];\n\"cntrl243\"[label=\"Multiply(243)\"];\n\"cntrl244\"[label=\"SetCoordinate(244)\"];\n\"cntrl245\"[label=\"LoadLDSTile{Value: Halfx2}(245)\"];\n\"cntrl246\"[label=\"SetCoordinate(246)\"];\n\"cntrl247\"[label=\"LoadLDSTile{Value: Halfx2}(247)\"];\n\"cntrl248\"[label=\"Multiply(248)\"];\n\"cntrl249\"[label=\"SetCoordinate(249)\"];\n\"cntrl250\"[label=\"LoadLDSTile{Value: Halfx2}(250)\"];\n\"cntrl251\"[label=\"SetCoordinate(251)\"];\n\"cntrl252\"[label=\"LoadLDSTile{Value: Halfx2}(252)\"];\n\"cntrl253\"[label=\"Multiply(253)\"];\n\"cntrl254\"[label=\"SetCoordinate(254)\"];\n\"cntrl255\"[label=\"LoadLDSTile{Value: Halfx2}(255)\"];\n\"cntrl256\"[label=\"SetCoordinate(256)\"];\n\"cntrl257\"[label=\"LoadLDSTile{Value: Halfx2}(257)\"];\n\"cntrl258\"[label=\"Multiply(258)\"];\n\"cntrl259\"[label=\"SetCoordinate(259)\"];\n\"cntrl260\"[label=\"LoadLDSTile{Value: Halfx2}(260)\"];\n\"cntrl261\"[label=\"SetCoordinate(261)\"];\n\"cntrl262\"[label=\"LoadLDSTile{Value: Halfx2}(262)\"];\n\"cntrl263\"[label=\"Multiply(263)\"];\n\"cntrl273\"[label=\"Body(273)\",shape=box];\n\"cntrl275\"[label=\"Body(275)\",shape=box];\n\"cntrl276\"[label=\"Sequence(276)\",shape=box];\n\"cntrl278\"[label=\"Body(278)\",shape=box];\n\"cntrl279\"[label=\"Sequence(279)\",shape=box];\n\"cntrl280\"[label=\"Body(280)\",shape=box];\n\"cntrl281\"[label=\"Sequence(281)\",shape=box];\n\"cntrl283\"[label=\"Body(283)\",shape=box];\n\"cntrl284\"[label=\"Sequence(284)\",shape=box];\n\"cntrl285\"[label=\"Body(285)\",shape=box];\n\"cntrl286\"[label=\"Sequence(286)\",shape=box];\n\"cntrl288\"[label=\"Body(288)\",shape=box];\n\"cntrl289\"[label=\"Sequence(289)\",shape=box];\n\"cntrl290\"[label=\"Body(290)\",shape=box];\n\"cntrl291\"[label=\"Sequence(291)\",shape=box];\n\"cntrl293\"[label=\"Body(293)\",shape=box];\n\"cntrl294\"[label=\"Sequence(294)\",shape=box];\n\"cntrl295\"[label=\"Body(295)\",shape=box];\n\"cntrl296\"[label=\"Sequence(296)\",shape=box];\n\"cntrl298\"[label=\"Body(298)\",shape=box];\n\"cntrl299\"[label=\"Sequence(299)\",shape=box];\n\"cntrl300\"[label=\"Body(300)\",shape=box];\n\"cntrl301\"[label=\"Sequence(301)\",shape=box];\n\"cntrl303\"[label=\"Body(303)\",shape=box];\n\"cntrl304\"[label=\"Sequence(304)\",shape=box];\n\"cntrl305\"[label=\"Body(305)\",shape=box];\n\"cntrl306\"[label=\"Sequence(306)\",shape=box];\n\"cntrl308\"[label=\"Body(308)\",shape=box];\n\"cntrl309\"[label=\"Sequence(309)\",shape=box];\n\"cntrl310\"[label=\"Body(310)\",shape=box];\n\"cntrl311\"[label=\"Sequence(311)\",shape=box];\n\"cntrl313\"[label=\"SetCoordinate(313)\"];\n\"cntrl314\"[label=\"SetCoordinate(314)\"];\n\"cntrl315\"[label=\"Body(315)\",shape=box];\n\"cntrl318\"[label=\"SetCoordinate(318)\"];\n\"cntrl323\"[label=\"SetCoordinate(323)\"];\n\"cntrl330\"[label=\"SetCoordinate(330)\"];\n\"cntrl331\"[label=\"LoadLDSTile{Value: Halfx2}(331)\"];\n\"cntrl332\"[label=\"SetCoordinate(332)\"];\n\"cntrl333\"[label=\"LoadLDSTile{Value: Halfx2}(333)\"];\n\"cntrl334\"[label=\"Multiply(334)\"];\n\"cntrl335\"[label=\"SetCoordinate(335)\"];\n\"cntrl336\"[label=\"LoadLDSTile{Value: Halfx2}(336)\"];\n\"cntrl337\"[label=\"SetCoordinate(337)\"];\n\"cntrl338\"[label=\"LoadLDSTile{Value: Halfx2}(338)\"];\n\"cntrl339\"[label=\"Multiply(339)\"];\n\"cntrl340\"[label=\"SetCoordinate(340)\"];\n\"cntrl341\"[label=\"LoadLDSTile{Value: Halfx2}(341)\"];\n\"cntrl342\"[label=\"SetCoordinate(342)\"];\n\"cntrl343\"[label=\"LoadLDSTile{Value: Halfx2}(343)\"];\n\"cntrl344\"[label=\"Multiply(344)\"];\n\"cntrl345\"[label=\"SetCoordinate(345)\"];\n\"cntrl346\"[label=\"LoadLDSTile{Value: Halfx2}(346)\"];\n\"cntrl347\"[label=\"SetCoordinate(347)\"];\n\"cntrl348\"[label=\"LoadLDSTile{Value: Halfx2}(348)\"];\n\"cntrl349\"[label=\"Multiply(349)\"];\n\"cntrl350\"[label=\"SetCoordinate(350)\"];\n\"cntrl351\"[label=\"LoadLDSTile{Value: Halfx2}(351)\"];\n\"cntrl352\"[label=\"SetCoordinate(352)\"];\n\"cntrl353\"[label=\"LoadLDSTile{Value: Halfx2}(353)\"];\n\"cntrl354\"[label=\"Multiply(354)\"];\n\"cntrl355\"[label=\"SetCoordinate(355)\"];\n\"cntrl356\"[label=\"LoadLDSTile{Value: Halfx2}(356)\"];\n\"cntrl357\"[label=\"SetCoordinate(357)\"];\n\"cntrl358\"[label=\"LoadLDSTile{Value: Halfx2}(358)\"];\n\"cntrl359\"[label=\"Multiply(359)\"];\n\"cntrl360\"[label=\"SetCoordinate(360)\"];\n\"cntrl361\"[label=\"LoadLDSTile{Value: Halfx2}(361)\"];\n\"cntrl362\"[label=\"SetCoordinate(362)\"];\n\"cntrl363\"[label=\"LoadLDSTile{Value: Halfx2}(363)\"];\n\"cntrl364\"[label=\"Multiply(364)\"];\n\"cntrl365\"[label=\"SetCoordinate(365)\"];\n\"cntrl366\"[label=\"LoadLDSTile{Value: Halfx2}(366)\"];\n\"cntrl367\"[label=\"SetCoordinate(367)\"];\n\"cntrl368\"[label=\"LoadLDSTile{Value: Halfx2}(368)\"];\n\"cntrl369\"[label=\"Multiply(369)\"];\n\"cntrl379\"[label=\"Body(379)\",shape=box];\n\"cntrl381\"[label=\"Body(381)\",shape=box];\n\"cntrl384\"[label=\"Body(384)\",shape=box];\n\"cntrl386\"[label=\"Body(386)\",shape=box];\n\"cntrl389\"[label=\"Body(389)\",shape=box];\n\"cntrl391\"[label=\"Body(391)\",shape=box];\n\"cntrl394\"[label=\"Body(394)\",shape=box];\n\"cntrl396\"[label=\"Body(396)\",shape=box];\n\"cntrl399\"[label=\"Body(399)\",shape=box];\n\"cntrl401\"[label=\"Body(401)\",shape=box];\n\"cntrl404\"[label=\"Body(404)\",shape=box];\n\"cntrl406\"[label=\"Body(406)\",shape=box];\n\"cntrl409\"[label=\"Body(409)\",shape=box];\n\"cntrl411\"[label=\"Body(411)\",shape=box];\n\"cntrl414\"[label=\"Body(414)\",shape=box];\n\"cntrl416\"[label=\"Body(416)\",shape=box];\n\"cntrl420\"[label=\"SetCoordinate(420)\"];\n\"cntrl421\"[label=\"LoadLDSTile{Value: Halfx2}(421)\"];\n\"cntrl422\"[label=\"SetCoordinate(422)\"];\n\"cntrl423\"[label=\"LoadLDSTile{Value: Halfx2}(423)\"];\n\"cntrl424\"[label=\"Multiply(424)\"];\n\"cntrl425\"[label=\"SetCoordinate(425)\"];\n\"cntrl426\"[label=\"LoadLDSTile{Value: Halfx2}(426)\"];\n\"cntrl427\"[label=\"SetCoordinate(427)\"];\n\"cntrl428\"[label=\"LoadLDSTile{Value: Halfx2}(428)\"];\n\"cntrl429\"[label=\"Multiply(429)\"];\n\"cntrl430\"[label=\"SetCoordinate(430)\"];\n\"cntrl431\"[label=\"LoadLDSTile{Value: Halfx2}(431)\"];\n\"cntrl432\"[label=\"SetCoordinate(432)\"];\n\"cntrl433\"[label=\"LoadLDSTile{Value: Halfx2}(433)\"];\n\"cntrl434\"[label=\"Multiply(434)\"];\n\"cntrl435\"[label=\"SetCoordinate(435)\"];\n\"cntrl436\"[label=\"LoadLDSTile{Value: Halfx2}(436)\"];\n\"cntrl437\"[label=\"SetCoordinate(437)\"];\n\"cntrl438\"[label=\"LoadLDSTile{Value: Halfx2}(438)\"];\n\"cntrl439\"[label=\"Multiply(439)\"];\n\"cntrl440\"[label=\"SetCoordinate(440)\"];\n\"cntrl441\"[label=\"LoadLDSTile{Value: Halfx2}(441)\"];\n\"cntrl442\"[label=\"SetCoordinate(442)\"];\n\"cntrl443\"[label=\"LoadLDSTile{Value: Halfx2}(443)\"];\n\"cntrl444\"[label=\"Multiply(444)\"];\n\"cntrl445\"[label=\"SetCoordinate(445)\"];\n\"cntrl446\"[label=\"LoadLDSTile{Value: Halfx2}(446)\"];\n\"cntrl447\"[label=\"SetCoordinate(447)\"];\n\"cntrl448\"[label=\"LoadLDSTile{Value: Halfx2}(448)\"];\n\"cntrl449\"[label=\"Multiply(449)\"];\n\"cntrl450\"[label=\"SetCoordinate(450)\"];\n\"cntrl451\"[label=\"LoadLDSTile{Value: Halfx2}(451)\"];\n\"cntrl452\"[label=\"SetCoordinate(452)\"];\n\"cntrl453\"[label=\"LoadLDSTile{Value: Halfx2}(453)\"];\n\"cntrl454\"[label=\"Multiply(454)\"];\n\"cntrl455\"[label=\"SetCoordinate(455)\"];\n\"cntrl456\"[label=\"LoadLDSTile{Value: Halfx2}(456)\"];\n\"cntrl457\"[label=\"SetCoordinate(457)\"];\n\"cntrl458\"[label=\"LoadLDSTile{Value: Halfx2}(458)\"];\n\"cntrl459\"[label=\"Multiply(459)\"];\n\"cntrl469\"[label=\"Body(469)\",shape=box];\n\"cntrl471\"[label=\"Body(471)\",shape=box];\n\"cntrl474\"[label=\"Body(474)\",shape=box];\n\"cntrl476\"[label=\"Body(476)\",shape=box];\n\"cntrl479\"[label=\"Body(479)\",shape=box];\n\"cntrl481\"[label=\"Body(481)\",shape=box];\n\"cntrl484\"[label=\"Body(484)\",shape=box];\n\"cntrl486\"[label=\"Body(486)\",shape=box];\n\"cntrl489\"[label=\"Body(489)\",shape=box];\n\"cntrl491\"[label=\"Body(491)\",shape=box];\n\"cntrl494\"[label=\"Body(494)\",shape=box];\n\"cntrl496\"[label=\"Body(496)\",shape=box];\n\"cntrl499\"[label=\"Body(499)\",shape=box];\n\"cntrl501\"[label=\"Body(501)\",shape=box];\n\"cntrl504\"[label=\"Body(504)\",shape=box];\n\"cntrl506\"[label=\"Body(506)\",shape=box];\n\"cntrl510\"[label=\"SetCoordinate(510)\"];\n\"cntrl511\"[label=\"LoadLDSTile{Value: Halfx2}(511)\"];\n\"cntrl512\"[label=\"SetCoordinate(512)\"];\n\"cntrl513\"[label=\"LoadLDSTile{Value: Halfx2}(513)\"];\n\"cntrl514\"[label=\"Multiply(514)\"];\n\"cntrl515\"[label=\"SetCoordinate(515)\"];\n\"cntrl516\"[label=\"LoadLDSTile{Value: Halfx2}(516)\"];\n\"cntrl517\"[label=\"SetCoordinate(517)\"];\n\"cntrl518\"[label=\"LoadLDSTile{Value: Halfx2}(518)\"];\n\"cntrl519\"[label=\"Multiply(519)\"];\n\"cntrl520\"[label=\"SetCoordinate(520)\"];\n\"cntrl521\"[label=\"LoadLDSTile{Value: Halfx2}(521)\"];\n\"cntrl522\"[label=\"SetCoordinate(522)\"];\n\"cntrl523\"[label=\"LoadLDSTile{Value: Halfx2}(523)\"];\n\"cntrl524\"[label=\"Multiply(524)\"];\n\"cntrl525\"[label=\"SetCoordinate(525)\"];\n\"cntrl526\"[label=\"LoadLDSTile{Value: Halfx2}(526)\"];\n\"cntrl527\"[label=\"SetCoordinate(527)\"];\n\"cntrl528\"[label=\"LoadLDSTile{Value: Halfx2}(528)\"];\n\"cntrl529\"[label=\"Multiply(529)\"];\n\"cntrl530\"[label=\"SetCoordinate(530)\"];\n\"cntrl531\"[label=\"LoadLDSTile{Value: Halfx2}(531)\"];\n\"cntrl532\"[label=\"SetCoordinate(532)\"];\n\"cntrl533\"[label=\"LoadLDSTile{Value: Halfx2}(533)\"];\n\"cntrl534\"[label=\"Multiply(534)\"];\n\"cntrl535\"[label=\"SetCoordinate(535)\"];\n\"cntrl536\"[label=\"LoadLDSTile{Value: Halfx2}(536)\"];\n\"cntrl537\"[label=\"SetCoordinate(537)\"];\n\"cntrl538\"[label=\"LoadLDSTile{Value: Halfx2}(538)\"];\n\"cntrl539\"[label=\"Multiply(539)\"];\n\"cntrl540\"[label=\"SetCoordinate(540)\"];\n\"cntrl541\"[label=\"LoadLDSTile{Value: Halfx2}(541)\"];\n\"cntrl542\"[label=\"SetCoordinate(542)\"];\n\"cntrl543\"[label=\"LoadLDSTile{Value: Halfx2}(543)\"];\n\"cntrl544\"[label=\"Multiply(544)\"];\n\"cntrl545\"[label=\"SetCoordinate(545)\"];\n\"cntrl546\"[label=\"LoadLDSTile{Value: Halfx2}(546)\"];\n\"cntrl547\"[label=\"SetCoordinate(547)\"];\n\"cntrl548\"[label=\"LoadLDSTile{Value: Halfx2}(548)\"];\n\"cntrl549\"[label=\"Multiply(549)\"];\n\"cntrl559\"[label=\"Body(559)\",shape=box];\n\"cntrl561\"[label=\"Body(561)\",shape=box];\n\"cntrl564\"[label=\"Body(564)\",shape=box];\n\"cntrl566\"[label=\"Body(566)\",shape=box];\n\"cntrl569\"[label=\"Body(569)\",shape=box];\n\"cntrl571\"[label=\"Body(571)\",shape=box];\n\"cntrl574\"[label=\"Body(574)\",shape=box];\n\"cntrl576\"[label=\"Body(576)\",shape=box];\n\"cntrl579\"[label=\"Body(579)\",shape=box];\n\"cntrl581\"[label=\"Body(581)\",shape=box];\n\"cntrl584\"[label=\"Body(584)\",shape=box];\n\"cntrl586\"[label=\"Body(586)\",shape=box];\n\"cntrl589\"[label=\"Body(589)\",shape=box];\n\"cntrl591\"[label=\"Body(591)\",shape=box];\n\"cntrl594\"[label=\"Body(594)\",shape=box];\n\"cntrl596\"[label=\"Body(596)\",shape=box];\n\"cntrl599\"[label=\"SetCoordinate(599)\"];\n\"cntrl604\"[label=\"SetCoordinate(604)\"];\n\"cntrl610\"[label=\"SetCoordinate(610)\"];\n\"cntrl615\"[label=\"SetCoordinate(615)\"];\n\"cntrl624\"[label=\"SetCoordinate(624)\"];\n\"cntrl629\"[label=\"SetCoordinate(629)\"];\n\"cntrl638\"[label=\"SetCoordinate(638)\"];\n\"cntrl643\"[label=\"SetCoordinate(643)\"];\n\"cntrl668\"[label=\"Sequence(668)\",shape=box];\n\"cntrl670\"[label=\"Scope(670)\"];\n\"cntrl675\"[label=\"NOP(675)\"];\n\"cntrl676\"[label=\"Body(676)\",shape=box];\n\"cntrl677\"[label=\"Sequence(677)\",shape=box];\n\"cntrl678\"[label=\"Scope(678)\"];\n\"cntrl679\"[label=\"Body(679)\",shape=box];\n\"cntrl681\"[label=\"NOP(681)\"];\n\"cntrl682\"[label=\"Body(682)\",shape=box];\n\"cntrl683\"[label=\"Sequence(683)\",shape=box];\n\"cntrl684\"[label=\"Scope(684)\"];\n\"cntrl685\"[label=\"Else(685)\",shape=box];\n\"cntrl687\"[label=\"NOP(687)\"];\n\"cntrl688\"[label=\"Body(688)\",shape=box];\n\"cntrl689\"[label=\"Sequence(689)\",shape=box];\n\"cntrl690\"[label=\"NOP(690)\"];\n\"cntrl693\"[label=\"Barrier(693)\"];\n\"cntrl694\"[label=\"NOP(694)\"];\n\"cntrl696\"[label=\"SetCoordinate(696)\"];\n\"cntrl699\"[label=\"SetCoordinate(699)\"];\n\"cntrl702\"[label=\"SetCoordinate(702)\"];\n\"cntrl705\"[label=\"SetCoordinate(705)\"];\n\"cntrl708\"[label=\"SetCoordinate(708)\"];\n\"cntrl711\"[label=\"SetCoordinate(711)\"];\n\"cntrl714\"[label=\"SetCoordinate(714)\"];\n\"cntrl717\"[label=\"SetCoordinate(717)\"];\n\"cntrl722\"[label=\"Sequence(722)\",shape=box];\n\"cntrl723\"[label=\"Sequence(723)\",shape=box];\n\"cntrl724\"[label=\"Sequence(724)\",shape=box];\n\"cntrl725\"[label=\"Sequence(725)\",shape=box];\n\"cntrl726\"[label=\"Sequence(726)\",shape=box];\n\"cntrl727\"[label=\"Sequence(727)\",shape=box];\n\"cntrl728\"[label=\"Sequence(728)\",shape=box];\n\"cntrl733\"[label=\"SetCoordinate(733)\"];\n\"cntrl734\"[label=\"LoadLDSTile{Value: Halfx2}(734)\"];\n\"cntrl735\"[label=\"Body(735)\",shape=box];\n\"cntrl736\"[label=\"SetCoordinate(736)\"];\n\"cntrl737\"[label=\"LoadLDSTile{Value: Halfx2}(737)\"];\n\"cntrl738\"[label=\"Body(738)\",shape=box];\n\"cntrl739\"[label=\"SetCoordinate(739)\"];\n\"cntrl740\"[label=\"LoadLDSTile{Value: Halfx2}(740)\"];\n\"cntrl741\"[label=\"Body(741)\",shape=box];\n\"cntrl742\"[label=\"SetCoordinate(742)\"];\n\"cntrl743\"[label=\"LoadLDSTile{Value: Halfx2}(743)\"];\n\"cntrl744\"[label=\"Body(744)\",shape=box];\n\"cntrl745\"[label=\"SetCoordinate(745)\"];\n\"cntrl746\"[label=\"LoadLDSTile{Value: Halfx2}(746)\"];\n\"cntrl747\"[label=\"Body(747)\",shape=box];\n\"cntrl748\"[label=\"SetCoordinate(748)\"];\n\"cntrl749\"[label=\"LoadLDSTile{Value: Halfx2}(749)\"];\n\"cntrl750\"[label=\"Body(750)\",shape=box];\n\"cntrl751\"[label=\"SetCoordinate(751)\"];\n\"cntrl752\"[label=\"LoadLDSTile{Value: Halfx2}(752)\"];\n\"cntrl753\"[label=\"Body(753)\",shape=box];\n\"cntrl754\"[label=\"SetCoordinate(754)\"];\n\"cntrl755\"[label=\"LoadLDSTile{Value: Halfx2}(755)\"];\n\"cntrl756\"[label=\"Body(756)\",shape=box];\n\"cntrl757\"[label=\"SetCoordinate(757)\"];\n\"cntrl758\"[label=\"LoadLDSTile{Value: Halfx2}(758)\"];\n\"cntrl759\"[label=\"Body(759)\",shape=box];\n\"cntrl760\"[label=\"SetCoordinate(760)\"];\n\"cntrl761\"[label=\"LoadLDSTile{Value: Halfx2}(761)\"];\n\"cntrl762\"[label=\"Body(762)\",shape=box];\n\"cntrl763\"[label=\"SetCoordinate(763)\"];\n\"cntrl764\"[label=\"LoadLDSTile{Value: Halfx2}(764)\"];\n\"cntrl765\"[label=\"Body(765)\",shape=box];\n\"cntrl766\"[label=\"SetCoordinate(766)\"];\n\"cntrl767\"[label=\"LoadLDSTile{Value: Halfx2}(767)\"];\n\"cntrl768\"[label=\"Body(768)\",shape=box];\n\"cntrl769\"[label=\"SetCoordinate(769)\"];\n\"cntrl770\"[label=\"LoadLDSTile{Value: Halfx2}(770)\"];\n\"cntrl771\"[label=\"Body(771)\",shape=box];\n\"cntrl772\"[label=\"SetCoordinate(772)\"];\n\"cntrl773\"[label=\"LoadLDSTile{Value: Halfx2}(773)\"];\n\"cntrl774\"[label=\"Body(774)\",shape=box];\n\"cntrl775\"[label=\"SetCoordinate(775)\"];\n\"cntrl776\"[label=\"LoadLDSTile{Value: Halfx2}(776)\"];\n\"cntrl777\"[label=\"Body(777)\",shape=box];\n\"cntrl778\"[label=\"SetCoordinate(778)\"];\n\"cntrl779\"[label=\"LoadLDSTile{Value: Halfx2}(779)\"];\n\"cntrl780\"[label=\"Body(780)\",shape=box];\n\"cntrl781\"[label=\"Sequence(781)\",shape=box];\n\"cntrl782\"[label=\"Sequence(782)\",shape=box];\n\"cntrl783\"[label=\"Sequence(783)\",shape=box];\n\"cntrl784\"[label=\"Sequence(784)\",shape=box];\n\"cntrl785\"[label=\"Sequence(785)\",shape=box];\n\"cntrl786\"[label=\"Sequence(786)\",shape=box];\n\"cntrl787\"[label=\"Sequence(787)\",shape=box];\n\"cntrl788\"[label=\"Sequence(788)\",shape=box];\n\"cntrl789\"[label=\"Sequence(789)\",shape=box];\n\"cntrl790\"[label=\"Sequence(790)\",shape=box];\n\"cntrl791\"[label=\"Sequence(791)\",shape=box];\n\"cntrl792\"[label=\"Sequence(792)\",shape=box];\n\"cntrl793\"[label=\"Sequence(793)\",shape=box];\n\"cntrl794\"[label=\"Sequence(794)\",shape=box];\n\"cntrl795\"[label=\"Sequence(795)\",shape=box];\n\"cntrl796\"[label=\"Sequence(796)\",shape=box];\n\"cntrl797\"[label=\"Sequence(797)\",shape=box];\n\"cntrl799\"[label=\"NOP(799)\"];\n\"cntrl800\"[label=\"NOP(800)\"];\n\"cntrl801\"[label=\"NOP(801)\"];\n\"cntrl802\"[label=\"NOP(802)\"];\n\"cntrl810\"[label=\"Body(810)\",shape=box];\n\"cntrl811\"[label=\"Barrier(811)\"];\n\"cntrl816\"[label=\"Body(816)\",shape=box];\n\"cntrl820\"[label=\"Sequence(820)\",shape=box];\n\"cntrl821\"[label=\"Sequence(821)\",shape=box];\n\"cntrl822\"[label=\"Sequence(822)\",shape=box];\n\"cntrl823\"[label=\"Sequence(823)\",shape=box];\n\"cntrl824\"[label=\"Sequence(824)\",shape=box];\n\"cntrl825\"[label=\"Sequence(825)\",shape=box];\n\"cntrl826\"[label=\"Sequence(826)\",shape=box];\n\"cntrl827\"[label=\"Sequence(827)\",shape=box];\n\"cntrl829\"[label=\"Sequence(829)\",shape=box];\n\"cntrl830\"[label=\"Sequence(830)\",shape=box];\n\"cntrl831\"[label=\"Sequence(831)\",shape=box];\n\"cntrl832\"[label=\"Sequence(832)\",shape=box];\n\"cntrl833\"[label=\"Sequence(833)\",shape=box];\n\"cntrl834\"[label=\"Sequence(834)\",shape=box];\n\"cntrl835\"[label=\"Sequence(835)\",shape=box];\n\"cntrl844\"[label=\"Sequence(844)\",shape=box];\n\"cntrl845\"[label=\"Sequence(845)\",shape=box];\n\"cntrl853\"[label=\"Barrier(853)\"];\n\"cntrl858\"[label=\"Sequence(858)\",shape=box];\n\"cntrl862\"[label=\"Sequence(862)\",shape=box];\n\"cntrl863\"[label=\"Sequence(863)\",shape=box];\n\"cntrl864\"[label=\"Sequence(864)\",shape=box];\n\"cntrl865\"[label=\"Sequence(865)\",shape=box];\n\"cntrl866\"[label=\"Sequence(866)\",shape=box];\n\"cntrl867\"[label=\"Sequence(867)\",shape=box];\n\"cntrl868\"[label=\"Sequence(868)\",shape=box];\n\"cntrl869\"[label=\"Sequence(869)\",shape=box];\n\"cntrl871\"[label=\"Sequence(871)\",shape=box];\n\"cntrl872\"[label=\"Sequence(872)\",shape=box];\n\"cntrl873\"[label=\"Sequence(873)\",shape=box];\n\"cntrl874\"[label=\"Sequence(874)\",shape=box];\n\"cntrl875\"[label=\"Sequence(875)\",shape=box];\n\"cntrl876\"[label=\"Sequence(876)\",shape=box];\n\"cntrl877\"[label=\"Sequence(877)\",shape=box];\n\"cntrl887\"[label=\"Sequence(887)\",shape=box];\n\"cntrl895\"[label=\"Barrier(895)\"];\n\"cntrl900\"[label=\"Sequence(900)\",shape=box];\n\"cntrl904\"[label=\"Sequence(904)\",shape=box];\n\"cntrl905\"[label=\"Sequence(905)\",shape=box];\n\"cntrl906\"[label=\"Sequence(906)\",shape=box];\n\"cntrl907\"[label=\"Sequence(907)\",shape=box];\n\"cntrl908\"[label=\"Sequence(908)\",shape=box];\n\"cntrl909\"[label=\"Sequence(909)\",shape=box];\n\"cntrl910\"[label=\"Sequence(910)\",shape=box];\n\"cntrl911\"[label=\"Sequence(911)\",shape=box];\n\"cntrl913\"[label=\"Sequence(913)\",shape=box];\n\"cntrl914\"[label=\"Sequence(914)\",shape=box];\n\"cntrl915\"[label=\"Sequence(915)\",shape=box];\n\"cntrl916\"[label=\"Sequence(916)\",shape=box];\n\"cntrl917\"[label=\"Sequence(917)\",shape=box];\n\"cntrl918\"[label=\"Sequence(918)\",shape=box];\n\"cntrl919\"[label=\"Sequence(919)\",shape=box];\n\"cntrl929\"[label=\"Sequence(929)\",shape=box];\n\"cntrl937\"[label=\"Barrier(937)\"];\n\"cntrl942\"[label=\"Sequence(942)\",shape=box];\n\"cntrl946\"[label=\"Sequence(946)\",shape=box];\n\"cntrl947\"[label=\"Sequence(947)\",shape=box];\n\"cntrl948\"[label=\"Sequence(948)\",shape=box];\n\"cntrl949\"[label=\"Sequence(949)\",shape=box];\n\"cntrl950\"[label=\"Sequence(950)\",shape=box];\n\"cntrl951\"[label=\"Sequence(951)\",shape=box];\n\"cntrl952\"[label=\"Sequence(952)\",shape=box];\n\"cntrl953\"[label=\"Sequence(953)\",shape=box];\n\"cntrl954\"[label=\"Sequence(954)\",shape=box];\n\"cntrl955\"[label=\"Sequence(955)\",shape=box];\n\"cntrl956\"[label=\"Sequence(956)\",shape=box];\n\"cntrl957\"[label=\"Sequence(957)\",shape=box];\n\"cntrl958\"[label=\"Sequence(958)\",shape=box];\n\"cntrl959\"[label=\"Sequence(959)\",shape=box];\n\"cntrl960\"[label=\"Sequence(960)\",shape=box];\n\"cntrl961\"[label=\"Sequence(961)\",shape=box];\n\"cntrl962\"[label=\"Sequence(962)\",shape=box];\n\"cntrl971\"[label=\"LoadTileDirect2LDS Value: Halfx2(971)\"];\n\"cntrl972\"[label=\"Body(972)\",shape=box];\n\"cntrl973\"[label=\"NOP(973)\"];\n\"cntrl975\"[label=\"Sequence(975)\",shape=box];\n\"cntrl976\"[label=\"LoadTileDirect2LDS Value: Halfx2(976)\"];\n\"cntrl977\"[label=\"Body(977)\",shape=box];\n\"cntrl978\"[label=\"NOP(978)\"];\n\"cntrl980\"[label=\"Sequence(980)\",shape=box];\n\"cntrl981\"[label=\"LoadTileDirect2LDS Value: Halfx2(981)\"];\n\"cntrl982\"[label=\"Body(982)\",shape=box];\n\"cntrl983\"[label=\"NOP(983)\"];\n\"cntrl984\"[label=\"Sequence(984)\",shape=box];\n\"cntrl987\"[label=\"LoadTileDirect2LDS Value: Halfx2(987)\"];\n\"cntrl988\"[label=\"Body(988)\",shape=box];\n\"cntrl989\"[label=\"NOP(989)\"];\n\"cntrl990\"[label=\"Sequence(990)\",shape=box];\n\"cntrl991\"[label=\"Sequence(991)\",shape=box];\n\"cntrl993\"[label=\"LoadTileDirect2LDS Value: Halfx2(993)\"];\n\"cntrl994\"[label=\"Body(994)\",shape=box];\n\"cntrl995\"[label=\"NOP(995)\"];\n\"cntrl997\"[label=\"Sequence(997)\",shape=box];\n\"cntrl998\"[label=\"LoadTileDirect2LDS Value: Halfx2(998)\"];\n\"cntrl999\"[label=\"Body(999)\",shape=box];\n\"cntrl1000\"[label=\"NOP(1000)\"];\n\"cntrl1001\"[label=\"Sequence(1001)\",shape=box];\n\"cntrl1002\"[label=\"Sequence(1002)\",shape=box];\n\"cntrl1003\"[label=\"LoadTileDirect2LDS Value: Halfx2(1003)\"];\n\"cntrl1004\"[label=\"Body(1004)\",shape=box];\n\"cntrl1005\"[label=\"NOP(1005)\"];\n\"cntrl1007\"[label=\"Sequence(1007)\",shape=box];\n\"cntrl1008\"[label=\"LoadTileDirect2LDS Value: Halfx2(1008)\"];\n\"cntrl1009\"[label=\"Body(1009)\",shape=box];\n\"cntrl1010\"[label=\"NOP(1010)\"];\n\"cntrl1011\"[label=\"Sequence(1011)\",shape=box];\n\"cntrl1012\"[label=\"Sequence(1012)\",shape=box];\n\"cntrl1013\"[label=\"LoadTileDirect2LDS Value: Halfx2(1013)\"];\n\"cntrl1014\"[label=\"Body(1014)\",shape=box];\n\"cntrl1015\"[label=\"NOP(1015)\"];\n\"cntrl1017\"[label=\"Sequence(1017)\",shape=box];\n\"cntrl1018\"[label=\"LoadTileDirect2LDS Value: Halfx2(1018)\"];\n\"cntrl1019\"[label=\"Body(1019)\",shape=box];\n\"cntrl1020\"[label=\"NOP(1020)\"];\n\"cntrl1021\"[label=\"Sequence(1021)\",shape=box];\n\"cntrl1022\"[label=\"Sequence(1022)\",shape=box];\n\"cntrl1023\"[label=\"LoadTileDirect2LDS Value: Halfx2(1023)\"];\n\"cntrl1025\"[label=\"NOP(1025)\"];\n\"cntrl1028\"[label=\"LoadTileDirect2LDS Value: Halfx2(1028)\"];\n\"cntrl1030\"[label=\"NOP(1030)\"];\n\"cntrl1031\"[label=\"Sequence(1031)\",shape=box];\n\"cntrl1032\"[label=\"Sequence(1032)\",shape=box];\n\"cntrl1033\"[label=\"LoadTileDirect2LDS Value: Halfx2(1033)\"];\n\"cntrl1035\"[label=\"LoadTileDirect2LDS Value: Halfx2(1035)\"];\n\"cntrl1037\"[label=\"LoadTileDirect2LDS Value: Halfx2(1037)\"];\n\"cntrl1039\"[label=\"LoadTileDirect2LDS Value: Halfx2(1039)\"];\n\"cntrl1041\"[label=\"LoadTileDirect2LDS Value: Halfx2(1041)\"];\n\"cntrl1043\"[label=\"LoadTileDirect2LDS Value: Halfx2(1043)\"];\n\"cntrl1045\"[label=\"NOP(1045)\"];\n\"cntrl1046\"[label=\"Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046)\"];\n\"cntrl1047\"[label=\"NOP(1047)\"];\n\"cntrl1048\"[label=\"NOP(1048)\"];\n\"cntrl1051\"[label=\"Scope(1051)\"];\n\"cntrl1052\"[label=\"Body(1052)\",shape=box];\n\"cntrl1053\"[label=\"Body(1053)\",shape=box];\n\"cntrl1056\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056)\"];\n\"cntrl1057\"[label=\"Assign VGPR 128:U64(1057)\"];\n\"cntrl1058\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058)\"];\n\"cntrl1059\"[label=\"Sequence(1059)\",shape=box];\n\"cntrl1060\"[label=\"Sequence(1060)\",shape=box];\n\"cntrl1061\"[label=\"Sequence(1061)\",shape=box];\n\"cntrl1062\"[label=\"Sequence(1062)\",shape=box];\n\"cntrl1063\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063)\"];\n\"cntrl1064\"[label=\"Sequence(1064)\",shape=box];\n\"cntrl1065\"[label=\"Sequence(1065)\",shape=box];\n\"cntrl1066\"[label=\"Assign VGPR 2:U64(1066)\"];\n\"cntrl1067\"[label=\"Sequence(1067)\",shape=box];\n\"cntrl1068\"[label=\"Sequence(1068)\",shape=box];\n\"cntrl1069\"[label=\"NOP(1069)\"];\n\"cntrl1070\"[label=\"NOP(1070)\"];\n\"cntrl1071\"[label=\"NOP(1071)\"];\n\"cntrl1074\"[label=\"Scope(1074)\"];\n\"cntrl1075\"[label=\"Sequence(1075)\",shape=box];\n\"cntrl1076\"[label=\"Sequence(1076)\",shape=box];\n\"cntrl1077\"[label=\"Body(1077)\",shape=box];\n\"cntrl1079\"[label=\"Assign VGPR 128:U64(1079)\"];\n\"cntrl1080\"[label=\"Sequence(1080)\",shape=box];\n\"cntrl1081\"[label=\"Sequence(1081)\",shape=box];\n\"cntrl1082\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082)\"];\n\"cntrl1083\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083)\"];\n\"cntrl1084\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084)\"];\n\"cntrl1085\"[label=\"Sequence(1085)\",shape=box];\n\"cntrl1086\"[label=\"Sequence(1086)\",shape=box];\n\"cntrl1087\"[label=\"Sequence(1087)\",shape=box];\n\"cntrl1088\"[label=\"Sequence(1088)\",shape=box];\n\"cntrl1089\"[label=\"Assign VGPR 2:U64(1089)\"];\n\"cntrl1090\"[label=\"Sequence(1090)\",shape=box];\n\"cntrl1091\"[label=\"Sequence(1091)\",shape=box];\n\"cntrl1092\"[label=\"NOP(1092)\"];\n\"cntrl1093\"[label=\"Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093)\"];\n\"cntrl1094\"[label=\"NOP(1094)\"];\n\"cntrl1095\"[label=\"NOP(1095)\"];\n\"cntrl1098\"[label=\"Sequence(1098)\",shape=box];\n\"cntrl1101\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101)\"];\n\"cntrl1102\"[label=\"Assign VGPR 128:U64(1102)\"];\n\"cntrl1103\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103)\"];\n\"cntrl1104\"[label=\"Sequence(1104)\",shape=box];\n\"cntrl1105\"[label=\"Sequence(1105)\",shape=box];\n\"cntrl1106\"[label=\"Sequence(1106)\",shape=box];\n\"cntrl1107\"[label=\"Sequence(1107)\",shape=box];\n\"cntrl1108\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108)\"];\n\"cntrl1109\"[label=\"Sequence(1109)\",shape=box];\n\"cntrl1110\"[label=\"Sequence(1110)\",shape=box];\n\"cntrl1111\"[label=\"Assign VGPR 2:U64(1111)\"];\n\"cntrl1112\"[label=\"Sequence(1112)\",shape=box];\n\"cntrl1113\"[label=\"Sequence(1113)\",shape=box];\n\"cntrl1114\"[label=\"NOP(1114)\"];\n\"cntrl1115\"[label=\"Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115)\"];\n\"cntrl1116\"[label=\"NOP(1116)\"];\n\"cntrl1117\"[label=\"NOP(1117)\"];\n\"cntrl1120\"[label=\"Sequence(1120)\",shape=box];\n\"cntrl1123\"[label=\"Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123)\"];\n\"cntrl1124\"[label=\"Assign VGPR 128:U64(1124)\"];\n\"cntrl1125\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125)\"];\n\"cntrl1126\"[label=\"Sequence(1126)\",shape=box];\n\"cntrl1127\"[label=\"Sequence(1127)\",shape=box];\n\"cntrl1128\"[label=\"Sequence(1128)\",shape=box];\n\"cntrl1129\"[label=\"Sequence(1129)\",shape=box];\n\"cntrl1130\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130)\"];\n\"cntrl1131\"[label=\"Sequence(1131)\",shape=box];\n\"cntrl1132\"[label=\"Sequence(1132)\",shape=box];\n\"cntrl1133\"[label=\"Assign VGPR 2:U64(1133)\"];\n\"cntrl1134\"[label=\"Sequence(1134)\",shape=box];\n\"cntrl1135\"[label=\"Sequence(1135)\",shape=box];\n\"cntrl1136\"[label=\"NOP(1136)\"];\n\"cntrl1137\"[label=\"NOP(1137)\"];\n\"cntrl1138\"[label=\"NOP(1138)\"];\n\"cntrl1141\"[label=\"Sequence(1141)\",shape=box];\n\"cntrl1143\"[label=\"Assign VGPR 128:U64(1143)\"];\n\"cntrl1144\"[label=\"Sequence(1144)\",shape=box];\n\"cntrl1145\"[label=\"Sequence(1145)\",shape=box];\n\"cntrl1146\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146)\"];\n\"cntrl1147\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147)\"];\n\"cntrl1148\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148)\"];\n\"cntrl1149\"[label=\"Sequence(1149)\",shape=box];\n\"cntrl1150\"[label=\"Sequence(1150)\",shape=box];\n\"cntrl1151\"[label=\"Sequence(1151)\",shape=box];\n\"cntrl1152\"[label=\"Sequence(1152)\",shape=box];\n\"cntrl1153\"[label=\"Assign VGPR 2:U64(1153)\"];\n\"cntrl1154\"[label=\"Sequence(1154)\",shape=box];\n\"cntrl1155\"[label=\"Sequence(1155)\",shape=box];\n\"cntrl1156\"[label=\"NOP(1156)\"];\n\"cntrl1157\"[label=\"Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157)\"];\n\"cntrl1158\"[label=\"NOP(1158)\"];\n\"cntrl1159\"[label=\"NOP(1159)\"];\n\"cntrl1162\"[label=\"Sequence(1162)\",shape=box];\n\"cntrl1165\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165)\"];\n\"cntrl1166\"[label=\"Assign VGPR 128:U64(1166)\"];\n\"cntrl1167\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167)\"];\n\"cntrl1168\"[label=\"Sequence(1168)\",shape=box];\n\"cntrl1169\"[label=\"Sequence(1169)\",shape=box];\n\"cntrl1170\"[label=\"Sequence(1170)\",shape=box];\n\"cntrl1171\"[label=\"Sequence(1171)\",shape=box];\n\"cntrl1172\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172)\"];\n\"cntrl1173\"[label=\"Sequence(1173)\",shape=box];\n\"cntrl1174\"[label=\"Sequence(1174)\",shape=box];\n\"cntrl1175\"[label=\"Assign VGPR 2:U64(1175)\"];\n\"cntrl1176\"[label=\"Sequence(1176)\",shape=box];\n\"cntrl1177\"[label=\"Sequence(1177)\",shape=box];\n\"cntrl1178\"[label=\"NOP(1178)\"];\n\"cntrl1179\"[label=\"NOP(1179)\"];\n\"cntrl1181\"[label=\"Scope(1181)\"];\n\"cntrl1182\"[label=\"Sequence(1182)\",shape=box];\n\"cntrl1183\"[label=\"Sequence(1183)\",shape=box];\n\"cntrl1184\"[label=\"Body(1184)\",shape=box];\n\"cntrl1186\"[label=\"Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186)\"];\n\"cntrl1187\"[label=\"Assign VGPR 16:U64(1187)\"];\n\"cntrl1188\"[label=\"Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188)\"];\n\"cntrl1190\"[label=\"Sequence(1190)\",shape=box];\n\"cntrl1192\"[label=\"Sequence(1192)\",shape=box];\n\"cntrl1193\"[label=\"Assign VGPR 2:U64(1193)\"];\n\"cntrl1194\"[label=\"Sequence(1194)\",shape=box];\n\"cntrl1195\"[label=\"Sequence(1195)\",shape=box];\n\"cntrl1196\"[label=\"NOP(1196)\"];\n\"cntrl1197\"[label=\"NOP(1197)\"];\n\"cntrl1199\"[label=\"NOP(1199)\"];\n\"cntrl1200\"[label=\"Sequence(1200)\",shape=box];\n\"cntrl1201\"[label=\"Sequence(1201)\",shape=box];\n\"cntrl1203\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203)\"];\n\"cntrl1204\"[label=\"Assign VGPR 1024:U32(1204)\"];\n\"cntrl1205\"[label=\"Sequence(1205)\",shape=box];\n\"cntrl1206\"[label=\"Sequence(1206)\",shape=box];\n\"cntrl1207\"[label=\"Sequence(1207)\",shape=box];\n\"cntrl1208\"[label=\"Assign VGPR 2:U32(1208)\"];\n\"cntrl1209\"[label=\"Sequence(1209)\",shape=box];\n\"cntrl1210\"[label=\"Sequence(1210)\",shape=box];\n\"cntrl1211\"[label=\"NOP(1211)\"];\n\"cntrl1212\"[label=\"NOP(1212)\"];\n\"cntrl1214\"[label=\"Sequence(1214)\",shape=box];\n\"cntrl1216\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216)\"];\n\"cntrl1217\"[label=\"Assign VGPR 1024:U32(1217)\"];\n\"cntrl1218\"[label=\"Sequence(1218)\",shape=box];\n\"cntrl1219\"[label=\"Sequence(1219)\",shape=box];\n\"cntrl1220\"[label=\"Sequence(1220)\",shape=box];\n\"cntrl1221\"[label=\"Assign VGPR 2:U32(1221)\"];\n\"cntrl1222\"[label=\"Sequence(1222)\",shape=box];\n\"cntrl1223\"[label=\"Sequence(1223)\",shape=box];\n\"cntrl1224\"[label=\"NOP(1224)\"];\n\"cntrl1225\"[label=\"NOP(1225)\"];\n\"cntrl1227\"[label=\"Scope(1227)\"];\n\"cntrl1228\"[label=\"Body(1228)\",shape=box];\n\"cntrl1229\"[label=\"Body(1229)\",shape=box];\n\"cntrl1231\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231)\"];\n\"cntrl1232\"[label=\"Assign VGPR 1024:U32(1232)\"];\n\"cntrl1233\"[label=\"Sequence(1233)\",shape=box];\n\"cntrl1234\"[label=\"Sequence(1234)\",shape=box];\n\"cntrl1235\"[label=\"Sequence(1235)\",shape=box];\n\"cntrl1236\"[label=\"Assign VGPR 2:U32(1236)\"];\n\"cntrl1237\"[label=\"Sequence(1237)\",shape=box];\n\"cntrl1238\"[label=\"Sequence(1238)\",shape=box];\n\"cntrl1239\"[label=\"NOP(1239)\"];\n\"cntrl1240\"[label=\"NOP(1240)\"];\n\"cntrl1242\"[label=\"Body(1242)\",shape=box];\n\"cntrl1243\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243)\"];\n\"cntrl1244\"[label=\"Assign VGPR 16:U32(1244)\"];\n\"cntrl1245\"[label=\"Sequence(1245)\",shape=box];\n\"cntrl1247\"[label=\"Sequence(1247)\",shape=box];\n\"cntrl1248\"[label=\"Assign VGPR 2:U32(1248)\"];\n\"cntrl1249\"[label=\"Sequence(1249)\",shape=box];\n\"cntrl1250\"[label=\"NOP(1250)\"];\n\"cntrl1251\"[label=\"NOP(1251)\"];\n\"cntrl1253\"[label=\"Sequence(1253)\",shape=box];\n\"cntrl1255\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255)\"];\n\"cntrl1256\"[label=\"Assign VGPR 1024:U32(1256)\"];\n\"cntrl1257\"[label=\"Sequence(1257)\",shape=box];\n\"cntrl1258\"[label=\"Sequence(1258)\",shape=box];\n\"cntrl1259\"[label=\"Sequence(1259)\",shape=box];\n\"cntrl1260\"[label=\"Assign VGPR 2:U32(1260)\"];\n\"cntrl1261\"[label=\"Sequence(1261)\",shape=box];\n\"cntrl1262\"[label=\"Sequence(1262)\",shape=box];\n\"cntrl1263\"[label=\"NOP(1263)\"];\n\"cntrl1264\"[label=\"NOP(1264)\"];\n\"cntrl1266\"[label=\"Sequence(1266)\",shape=box];\n\"cntrl1268\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268)\"];\n\"cntrl1269\"[label=\"Assign VGPR 1024:U32(1269)\"];\n\"cntrl1270\"[label=\"Sequence(1270)\",shape=box];\n\"cntrl1271\"[label=\"Sequence(1271)\",shape=box];\n\"cntrl1272\"[label=\"Sequence(1272)\",shape=box];\n\"cntrl1273\"[label=\"Assign VGPR 2:U32(1273)\"];\n\"cntrl1274\"[label=\"Sequence(1274)\",shape=box];\n\"cntrl1275\"[label=\"Sequence(1275)\",shape=box];\n\"cntrl1276\"[label=\"NOP(1276)\"];\n\"cntrl1277\"[label=\"NOP(1277)\"];\n\"cntrl1279\"[label=\"Scope(1279)\"];\n\"cntrl1280\"[label=\"Body(1280)\",shape=box];\n\"cntrl1281\"[label=\"Body(1281)\",shape=box];\n\"cntrl1283\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283)\"];\n\"cntrl1284\"[label=\"Assign VGPR 1024:U32(1284)\"];\n\"cntrl1285\"[label=\"Sequence(1285)\",shape=box];\n\"cntrl1286\"[label=\"Sequence(1286)\",shape=box];\n\"cntrl1287\"[label=\"Sequence(1287)\",shape=box];\n\"cntrl1288\"[label=\"Assign VGPR 2:U32(1288)\"];\n\"cntrl1289\"[label=\"Sequence(1289)\",shape=box];\n\"cntrl1290\"[label=\"Sequence(1290)\",shape=box];\n\"cntrl1291\"[label=\"NOP(1291)\"];\n\"cntrl1292\"[label=\"NOP(1292)\"];\n\"cntrl1294\"[label=\"Body(1294)\",shape=box];\n\"cntrl1295\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295)\"];\n\"cntrl1296\"[label=\"Assign VGPR 16:U32(1296)\"];\n\"cntrl1297\"[label=\"Sequence(1297)\",shape=box];\n\"cntrl1299\"[label=\"Sequence(1299)\",shape=box];\n\"cntrl1300\"[label=\"Assign VGPR 2:U32(1300)\"];\n\"cntrl1301\"[label=\"Sequence(1301)\",shape=box];\n\"cntrl1302\"[label=\"NOP(1302)\"];\n\"cntrl1303\"[label=\"NOP(1303)\"];\n\"cntrl1305\"[label=\"NOP(1305)\"];\n\"cntrl1307\"[label=\"Sequence(1307)\",shape=box];\n\"cntrl1309\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309)\"];\n\"cntrl1310\"[label=\"Assign VGPR 16:U64(1310)\"];\n\"cntrl1311\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311)\"];\n\"cntrl1312\"[label=\"Sequence(1312)\",shape=box];\n\"cntrl1313\"[label=\"Sequence(1313)\",shape=box];\n\"cntrl1314\"[label=\"Sequence(1314)\",shape=box];\n\"cntrl1315\"[label=\"Sequence(1315)\",shape=box];\n\"cntrl1316\"[label=\"Assign VGPR 2:U64(1316)\"];\n\"cntrl1317\"[label=\"Sequence(1317)\",shape=box];\n\"cntrl1318\"[label=\"Sequence(1318)\",shape=box];\n\"cntrl1319\"[label=\"NOP(1319)\"];\n\"cntrl1320\"[label=\"NOP(1320)\"];\n\"cntrl1322\"[label=\"NOP(1322)\"];\n\"cntrl1324\"[label=\"Sequence(1324)\",shape=box];\n\"cntrl1326\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326)\"];\n\"cntrl1327\"[label=\"Assign VGPR 16:U64(1327)\"];\n\"cntrl1328\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328)\"];\n\"cntrl1329\"[label=\"Sequence(1329)\",shape=box];\n\"cntrl1330\"[label=\"Sequence(1330)\",shape=box];\n\"cntrl1331\"[label=\"Sequence(1331)\",shape=box];\n\"cntrl1332\"[label=\"Sequence(1332)\",shape=box];\n\"cntrl1333\"[label=\"Assign VGPR 2:U64(1333)\"];\n\"cntrl1334\"[label=\"Sequence(1334)\",shape=box];\n\"cntrl1335\"[label=\"Sequence(1335)\",shape=box];\n\"cntrl1336\"[label=\"NOP(1336)\"];\n\"cntrl1337\"[label=\"NOP(1337)\"];\n\"cntrl1339\"[label=\"Sequence(1339)\",shape=box];\n\"cntrl1341\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341)\"];\n\"cntrl1342\"[label=\"Assign VGPR 1024:U32(1342)\"];\n\"cntrl1343\"[label=\"Sequence(1343)\",shape=box];\n\"cntrl1344\"[label=\"Sequence(1344)\",shape=box];\n\"cntrl1345\"[label=\"Sequence(1345)\",shape=box];\n\"cntrl1346\"[label=\"Assign VGPR 2:U32(1346)\"];\n\"cntrl1347\"[label=\"Sequence(1347)\",shape=box];\n\"cntrl1348\"[label=\"Sequence(1348)\",shape=box];\n\"cntrl1349\"[label=\"NOP(1349)\"];\n\"cntrl1350\"[label=\"NOP(1350)\"];\n\"cntrl1352\"[label=\"Scope(1352)\"];\n\"cntrl1353\"[label=\"Body(1353)\",shape=box];\n\"cntrl1354\"[label=\"Body(1354)\",shape=box];\n\"cntrl1356\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356)\"];\n\"cntrl1357\"[label=\"Assign VGPR 1024:U32(1357)\"];\n\"cntrl1358\"[label=\"Sequence(1358)\",shape=box];\n\"cntrl1359\"[label=\"Sequence(1359)\",shape=box];\n\"cntrl1360\"[label=\"Sequence(1360)\",shape=box];\n\"cntrl1361\"[label=\"Assign VGPR 2:U32(1361)\"];\n\"cntrl1362\"[label=\"Sequence(1362)\",shape=box];\n\"cntrl1363\"[label=\"Sequence(1363)\",shape=box];\n\"cntrl1364\"[label=\"NOP(1364)\"];\n\"cntrl1365\"[label=\"NOP(1365)\"];\n\"cntrl1367\"[label=\"Body(1367)\",shape=box];\n\"cntrl1368\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368)\"];\n\"cntrl1369\"[label=\"Assign VGPR 16:U32(1369)\"];\n\"cntrl1370\"[label=\"Sequence(1370)\",shape=box];\n\"cntrl1372\"[label=\"Sequence(1372)\",shape=box];\n\"cntrl1373\"[label=\"Assign VGPR 2:U32(1373)\"];\n\"cntrl1374\"[label=\"Sequence(1374)\",shape=box];\n\"cntrl1375\"[label=\"NOP(1375)\"];\n\"cntrl1376\"[label=\"NOP(1376)\"];\n\"cntrl1378\"[label=\"Sequence(1378)\",shape=box];\n\"cntrl1380\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380)\"];\n\"cntrl1381\"[label=\"Assign VGPR 1024:U32(1381)\"];\n\"cntrl1382\"[label=\"Sequence(1382)\",shape=box];\n\"cntrl1383\"[label=\"Sequence(1383)\",shape=box];\n\"cntrl1384\"[label=\"Sequence(1384)\",shape=box];\n\"cntrl1385\"[label=\"Assign VGPR 2:U32(1385)\"];\n\"cntrl1386\"[label=\"Sequence(1386)\",shape=box];\n\"cntrl1387\"[label=\"Sequence(1387)\",shape=box];\n\"cntrl1388\"[label=\"NOP(1388)\"];\n\"cntrl1389\"[label=\"NOP(1389)\"];\n\"cntrl1391\"[label=\"Scope(1391)\"];\n\"cntrl1392\"[label=\"Body(1392)\",shape=box];\n\"cntrl1393\"[label=\"Body(1393)\",shape=box];\n\"cntrl1395\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395)\"];\n\"cntrl1396\"[label=\"Assign VGPR 1024:U32(1396)\"];\n\"cntrl1397\"[label=\"Sequence(1397)\",shape=box];\n\"cntrl1398\"[label=\"Sequence(1398)\",shape=box];\n\"cntrl1399\"[label=\"Sequence(1399)\",shape=box];\n\"cntrl1400\"[label=\"Assign VGPR 2:U32(1400)\"];\n\"cntrl1401\"[label=\"Sequence(1401)\",shape=box];\n\"cntrl1402\"[label=\"Sequence(1402)\",shape=box];\n\"cntrl1403\"[label=\"NOP(1403)\"];\n\"cntrl1404\"[label=\"NOP(1404)\"];\n\"cntrl1406\"[label=\"Body(1406)\",shape=box];\n\"cntrl1407\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407)\"];\n\"cntrl1408\"[label=\"Assign VGPR 16:U32(1408)\"];\n\"cntrl1409\"[label=\"Sequence(1409)\",shape=box];\n\"cntrl1411\"[label=\"Sequence(1411)\",shape=box];\n\"cntrl1412\"[label=\"Assign VGPR 2:U32(1412)\"];\n\"cntrl1413\"[label=\"Sequence(1413)\",shape=box];\n\"cntrl1414\"[label=\"NOP(1414)\"];\n\"cntrl1415\"[label=\"NOP(1415)\"];\n\"cntrl1417\"[label=\"Sequence(1417)\",shape=box];\n\"cntrl1419\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419)\"];\n\"cntrl1420\"[label=\"Assign VGPR 1024:U32(1420)\"];\n\"cntrl1421\"[label=\"Sequence(1421)\",shape=box];\n\"cntrl1422\"[label=\"Sequence(1422)\",shape=box];\n\"cntrl1423\"[label=\"Sequence(1423)\",shape=box];\n\"cntrl1424\"[label=\"Assign VGPR 2:U32(1424)\"];\n\"cntrl1425\"[label=\"Sequence(1425)\",shape=box];\n\"cntrl1426\"[label=\"Sequence(1426)\",shape=box];\n\"cntrl1427\"[label=\"NOP(1427)\"];\n\"cntrl1428\"[label=\"NOP(1428)\"];\n\"cntrl1430\"[label=\"Scope(1430)\"];\n\"cntrl1431\"[label=\"Body(1431)\",shape=box];\n\"cntrl1432\"[label=\"Body(1432)\",shape=box];\n\"cntrl1434\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434)\"];\n\"cntrl1435\"[label=\"Assign VGPR 1024:U32(1435)\"];\n\"cntrl1436\"[label=\"Sequence(1436)\",shape=box];\n\"cntrl1437\"[label=\"Sequence(1437)\",shape=box];\n\"cntrl1438\"[label=\"Sequence(1438)\",shape=box];\n\"cntrl1439\"[label=\"Assign VGPR 2:U32(1439)\"];\n\"cntrl1440\"[label=\"Sequence(1440)\",shape=box];\n\"cntrl1441\"[label=\"Sequence(1441)\",shape=box];\n\"cntrl1442\"[label=\"NOP(1442)\"];\n\"cntrl1443\"[label=\"NOP(1443)\"];\n\"cntrl1445\"[label=\"Body(1445)\",shape=box];\n\"cntrl1446\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446)\"];\n\"cntrl1447\"[label=\"Assign VGPR 16:U32(1447)\"];\n\"cntrl1448\"[label=\"Sequence(1448)\",shape=box];\n\"cntrl1450\"[label=\"Sequence(1450)\",shape=box];\n\"cntrl1451\"[label=\"Assign VGPR 2:U32(1451)\"];\n\"cntrl1452\"[label=\"Sequence(1452)\",shape=box];\n\"cntrl1453\"[label=\"NOP(1453)\"];\n\"cntrl1454\"[label=\"NOP(1454)\"];\n\"cntrl1456\"[label=\"Sequence(1456)\",shape=box];\n\"cntrl1458\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458)\"];\n\"cntrl1459\"[label=\"Assign VGPR 1024:U32(1459)\"];\n\"cntrl1460\"[label=\"Sequence(1460)\",shape=box];\n\"cntrl1461\"[label=\"Sequence(1461)\",shape=box];\n\"cntrl1462\"[label=\"Sequence(1462)\",shape=box];\n\"cntrl1463\"[label=\"Assign VGPR 2:U32(1463)\"];\n\"cntrl1464\"[label=\"Sequence(1464)\",shape=box];\n\"cntrl1465\"[label=\"Sequence(1465)\",shape=box];\n\"cntrl1466\"[label=\"NOP(1466)\"];\n\"cntrl1467\"[label=\"NOP(1467)\"];\n\"cntrl1469\"[label=\"Scope(1469)\"];\n\"cntrl1470\"[label=\"Body(1470)\",shape=box];\n\"cntrl1471\"[label=\"Body(1471)\",shape=box];\n\"cntrl1473\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473)\"];\n\"cntrl1474\"[label=\"Assign VGPR 1024:U32(1474)\"];\n\"cntrl1475\"[label=\"Sequence(1475)\",shape=box];\n\"cntrl1476\"[label=\"Sequence(1476)\",shape=box];\n\"cntrl1477\"[label=\"Sequence(1477)\",shape=box];\n\"cntrl1478\"[label=\"Assign VGPR 2:U32(1478)\"];\n\"cntrl1479\"[label=\"Sequence(1479)\",shape=box];\n\"cntrl1480\"[label=\"Sequence(1480)\",shape=box];\n\"cntrl1481\"[label=\"NOP(1481)\"];\n\"cntrl1482\"[label=\"NOP(1482)\"];\n\"cntrl1484\"[label=\"Body(1484)\",shape=box];\n\"cntrl1485\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485)\"];\n\"cntrl1486\"[label=\"Assign VGPR 16:U32(1486)\"];\n\"cntrl1487\"[label=\"Sequence(1487)\",shape=box];\n\"cntrl1489\"[label=\"Sequence(1489)\",shape=box];\n\"cntrl1490\"[label=\"Assign VGPR 2:U32(1490)\"];\n\"cntrl1491\"[label=\"Sequence(1491)\",shape=box];\n\"cntrl1492\"[label=\"NOP(1492)\"];\n\"cntrl1493\"[label=\"NOP(1493)\"];\n\"cntrl1495\"[label=\"Sequence(1495)\",shape=box];\n\"cntrl1497\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497)\"];\n\"cntrl1498\"[label=\"Assign VGPR 1024:U32(1498)\"];\n\"cntrl1499\"[label=\"Sequence(1499)\",shape=box];\n\"cntrl1500\"[label=\"Sequence(1500)\",shape=box];\n\"cntrl1501\"[label=\"Sequence(1501)\",shape=box];\n\"cntrl1502\"[label=\"Assign VGPR 2:U32(1502)\"];\n\"cntrl1503\"[label=\"Sequence(1503)\",shape=box];\n\"cntrl1504\"[label=\"Sequence(1504)\",shape=box];\n\"cntrl1505\"[label=\"NOP(1505)\"];\n\"cntrl1506\"[label=\"NOP(1506)\"];\n\"cntrl1508\"[label=\"Scope(1508)\"];\n\"cntrl1509\"[label=\"Body(1509)\",shape=box];\n\"cntrl1510\"[label=\"Body(1510)\",shape=box];\n\"cntrl1512\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512)\"];\n\"cntrl1513\"[label=\"Assign VGPR 1024:U32(1513)\"];\n\"cntrl1514\"[label=\"Sequence(1514)\",shape=box];\n\"cntrl1515\"[label=\"Sequence(1515)\",shape=box];\n\"cntrl1516\"[label=\"Sequence(1516)\",shape=box];\n\"cntrl1517\"[label=\"Assign VGPR 2:U32(1517)\"];\n\"cntrl1518\"[label=\"Sequence(1518)\",shape=box];\n\"cntrl1519\"[label=\"Sequence(1519)\",shape=box];\n\"cntrl1520\"[label=\"NOP(1520)\"];\n\"cntrl1521\"[label=\"NOP(1521)\"];\n\"cntrl1523\"[label=\"Body(1523)\",shape=box];\n\"cntrl1524\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524)\"];\n\"cntrl1525\"[label=\"Assign VGPR 16:U32(1525)\"];\n\"cntrl1526\"[label=\"Sequence(1526)\",shape=box];\n\"cntrl1528\"[label=\"Sequence(1528)\",shape=box];\n\"cntrl1529\"[label=\"Assign VGPR 2:U32(1529)\"];\n\"cntrl1530\"[label=\"Sequence(1530)\",shape=box];\n\"cntrl1531\"[label=\"NOP(1531)\"];\n\"cntrl1532\"[label=\"NOP(1532)\"];\n\"cntrl1534\"[label=\"Sequence(1534)\",shape=box];\n\"cntrl1536\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536)\"];\n\"cntrl1537\"[label=\"Assign VGPR 1024:U32(1537)\"];\n\"cntrl1538\"[label=\"Sequence(1538)\",shape=box];\n\"cntrl1539\"[label=\"Sequence(1539)\",shape=box];\n\"cntrl1540\"[label=\"Sequence(1540)\",shape=box];\n\"cntrl1541\"[label=\"Assign VGPR 2:U32(1541)\"];\n\"cntrl1542\"[label=\"Sequence(1542)\",shape=box];\n\"cntrl1543\"[label=\"Sequence(1543)\",shape=box];\n\"cntrl1544\"[label=\"NOP(1544)\"];\n\"cntrl1545\"[label=\"NOP(1545)\"];\n\"cntrl1547\"[label=\"Scope(1547)\"];\n\"cntrl1548\"[label=\"Body(1548)\",shape=box];\n\"cntrl1549\"[label=\"Body(1549)\",shape=box];\n\"cntrl1551\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551)\"];\n\"cntrl1552\"[label=\"Assign VGPR 1024:U32(1552)\"];\n\"cntrl1553\"[label=\"Sequence(1553)\",shape=box];\n\"cntrl1554\"[label=\"Sequence(1554)\",shape=box];\n\"cntrl1555\"[label=\"Sequence(1555)\",shape=box];\n\"cntrl1556\"[label=\"Assign VGPR 2:U32(1556)\"];\n\"cntrl1557\"[label=\"Sequence(1557)\",shape=box];\n\"cntrl1558\"[label=\"Sequence(1558)\",shape=box];\n\"cntrl1559\"[label=\"NOP(1559)\"];\n\"cntrl1560\"[label=\"NOP(1560)\"];\n\"cntrl1562\"[label=\"Body(1562)\",shape=box];\n\"cntrl1563\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563)\"];\n\"cntrl1564\"[label=\"Assign VGPR 16:U32(1564)\"];\n\"cntrl1565\"[label=\"Sequence(1565)\",shape=box];\n\"cntrl1567\"[label=\"Sequence(1567)\",shape=box];\n\"cntrl1568\"[label=\"Assign VGPR 2:U32(1568)\"];\n\"cntrl1569\"[label=\"Sequence(1569)\",shape=box];\n\"cntrl1570\"[label=\"Sequence(1570)\",shape=box];\n\"cntrl1571\"[label=\"Sequence(1571)\",shape=box];\n\"cntrl1572\"[label=\"Sequence(1572)\",shape=box];\n\"cntrl1573\"[label=\"Sequence(1573)\",shape=box];\n\"cntrl1574\"[label=\"Sequence(1574)\",shape=box];\n\"cntrl1575\"[label=\"Sequence(1575)\",shape=box];\n\"cntrl1576\"[label=\"Sequence(1576)\",shape=box];\n\"cntrl1577\"[label=\"Sequence(1577)\",shape=box];\n\"cntrl1578\"[label=\"Sequence(1578)\",shape=box];\n\"cntrl1579\"[label=\"Sequence(1579)\",shape=box];\n\"cntrl1580\"[label=\"Sequence(1580)\",shape=box];\n\"cntrl1581\"[label=\"Sequence(1581)\",shape=box];\n\"cntrl1582\"[label=\"Sequence(1582)\",shape=box];\n\"cntrl1583\"[label=\"Sequence(1583)\",shape=box];\n\"cntrl1584\"[label=\"Sequence(1584)\",shape=box];\n\"cntrl1585\"[label=\"Sequence(1585)\",shape=box];\n\"cntrl1586\"[label=\"Body(1586)\",shape=box];\n\"cntrl1595\"[label=\"Body(1595)\",shape=box];\n\"cntrl1629\"[label=\"Sequence(1629)\",shape=box];\n\"cntrl1630\"[label=\"Sequence(1630)\",shape=box];\n\"cntrl1631\"[label=\"Sequence(1631)\",shape=box];\n\"cntrl1632\"[label=\"Sequence(1632)\",shape=box];\n\"cntrl1633\"[label=\"Sequence(1633)\",shape=box];\n\"cntrl1634\"[label=\"Sequence(1634)\",shape=box];\n\"cntrl1635\"[label=\"Sequence(1635)\",shape=box];\n\"cntrl1660\"[label=\"Sequence(1660)\",shape=box];\n\"cntrl1668\"[label=\"Sequence(1668)\",shape=box];\n\"cntrl1670\"[label=\"Sequence(1670)\",shape=box];\n\"cntrl1672\"[label=\"Sequence(1672)\",shape=box];\n\"cntrl1674\"[label=\"Sequence(1674)\",shape=box];\n\"cntrl1723\"[label=\"Barrier(1723)\"];\n\"cntrl1724\"[label=\"Sequence(1724)\",shape=box];\n\"cntrl1725\"[label=\"Sequence(1725)\",shape=box];\n\"cntrl1726\"[label=\"Barrier(1726)\"];\n\"cntrl1727\"[label=\"Body(1727)\",shape=box];\n\"cntrl1728\"[label=\"Sequence(1728)\",shape=box];\n\"cntrl1729\"[label=\"Barrier(1729)\"];\n\"cntrl1730\"[label=\"Sequence(1730)\",shape=box];\n\"cntrl1731\"[label=\"Sequence(1731)\",shape=box];\n\"cntrl1732\"[label=\"Sequence(1732)\",shape=box];\n\"cntrl1733\"[label=\"Barrier(1733)\"];\n\"cntrl1734\"[label=\"Body(1734)\",shape=box];\n\"cntrl1735\"[label=\"Sequence(1735)\",shape=box];\n\"cntrl1736\"[label=\"Barrier(1736)\"];\n\"cntrl1737\"[label=\"Sequence(1737)\",shape=box];\n\"cntrl1738\"[label=\"Sequence(1738)\",shape=box];\n\"cntrl1739\"[label=\"Barrier(1739)\"];\n\"cntrl1740\"[label=\"Sequence(1740)\",shape=box];\n\"cntrl1741\"[label=\"Sequence(1741)\",shape=box];\n\"cntrl1742\"[label=\"Sequence(1742)\",shape=box];\n\"cntrl1743\"[label=\"Barrier(1743)\"];\n\"cntrl1744\"[label=\"Sequence(1744)\",shape=box];\n\"cntrl1745\"[label=\"Sequence(1745)\",shape=box];\n\"cntrl1746\"[label=\"Barrier(1746)\"];\n\"cntrl1747\"[label=\"Sequence(1747)\",shape=box];\n\"cntrl1748\"[label=\"Sequence(1748)\",shape=box];\n\"cntrl1749\"[label=\"Barrier(1749)\"];\n\"cntrl1750\"[label=\"Sequence(1750)\",shape=box];\n\"cntrl1751\"[label=\"Sequence(1751)\",shape=box];\n\"cntrl1752\"[label=\"Barrier(1752)\"];\n\"cntrl1753\"[label=\"Sequence(1753)\",shape=box];\n\"cntrl1754\"[label=\"Sequence(1754)\",shape=box];\n\"cntrl1755\"[label=\"Barrier(1755)\"];\n\"cntrl1757\"[label=\"Sequence(1757)\",shape=box];\n\"cntrl1758\"[label=\"Barrier(1758)\"];\n\"cntrl1759\"[label=\"Sequence(1759)\",shape=box];\n\"cntrl1760\"[label=\"Sequence(1760)\",shape=box];\n\"cntrl1761\"[label=\"Deallocate{}(1761)\"];\n\"cntrl1762\"[label=\"Sequence(1762)\",shape=box];\n\"cntrl1763\"[label=\"Deallocate{}(1763)\"];\n\"cntrl1764\"[label=\"Sequence(1764)\",shape=box];\n\"cntrl1765\"[label=\"Deallocate{}(1765)\"];\n\"cntrl1766\"[label=\"Sequence(1766)\",shape=box];\n\"cntrl1767\"[label=\"Barrier(1767)\"];\n\"cntrl1768\"[label=\"Sequence(1768)\",shape=box];\n\"cntrl1769\"[label=\"Deallocate{}(1769)\"];\n\"cntrl1770\"[label=\"Sequence(1770)\",shape=box];\n\"cntrl1771\"[label=\"Deallocate{}(1771)\"];\n\"cntrl1772\"[label=\"Sequence(1772)\",shape=box];\n\"cntrl1773\"[label=\"Deallocate{}(1773)\"];\n\"cntrl1774\"[label=\"Sequence(1774)\",shape=box];\n\"cntrl1775\"[label=\"Deallocate{}(1775)\"];\n\"cntrl1776\"[label=\"Sequence(1776)\",shape=box];\n\"cntrl1777\"[label=\"Deallocate{Tensor_4_stride_1_13}(1777)\"];\n\"cntrl1778\"[label=\"Sequence(1778)\",shape=box];\n\"cntrl1779\"[label=\"Deallocate{}(1779)\"];\n\"cntrl1780\"[label=\"Sequence(1780)\",shape=box];\n\"cntrl1781\"[label=\"Deallocate{}(1781)\"];\n\"cntrl1782\"[label=\"Sequence(1782)\",shape=box];\n\"cntrl1783\"[label=\"Deallocate{}(1783)\"];\n\"cntrl1784\"[label=\"Sequence(1784)\",shape=box];\n\"cntrl1785\"[label=\"Deallocate{}(1785)\"];\n\"cntrl1786\"[label=\"Sequence(1786)\",shape=box];\n\"cntrl1787\"[label=\"Deallocate{}(1787)\"];\n\"cntrl1788\"[label=\"Sequence(1788)\",shape=box];\n\"cntrl1789\"[label=\"Deallocate{}(1789)\"];\n\"cntrl1790\"[label=\"Sequence(1790)\",shape=box];\n\"cntrl1791\"[label=\"Deallocate{}(1791)\"];\n\"cntrl1792\"[label=\"Sequence(1792)\",shape=box];\n\"cntrl1793\"[label=\"Deallocate{}(1793)\"];\n\"cntrl1794\"[label=\"Sequence(1794)\",shape=box];\n\"cntrl1795\"[label=\"Deallocate{}(1795)\"];\n\"cntrl1796\"[label=\"Sequence(1796)\",shape=box];\n\"cntrl1797\"[label=\"Deallocate{}(1797)\"];\n\"cntrl1798\"[label=\"Sequence(1798)\",shape=box];\n\"cntrl1799\"[label=\"Deallocate{}(1799)\"];\n\"cntrl1800\"[label=\"Sequence(1800)\",shape=box];\n\"cntrl1801\"[label=\"Barrier(1801)\"];\n\"cntrl1802\"[label=\"Sequence(1802)\",shape=box];\n\"cntrl1803\"[label=\"Deallocate{}(1803)\"];\n\"cntrl1804\"[label=\"Sequence(1804)\",shape=box];\n\"cntrl1805\"[label=\"Deallocate{}(1805)\"];\n\"cntrl1806\"[label=\"Sequence(1806)\",shape=box];\n\"cntrl1807\"[label=\"Deallocate{}(1807)\"];\n\"cntrl1808\"[label=\"Sequence(1808)\",shape=box];\n\"cntrl1809\"[label=\"Deallocate{}(1809)\"];\n\"cntrl1810\"[label=\"Sequence(1810)\",shape=box];\n\"cntrl1811\"[label=\"Deallocate{}(1811)\"];\n\"cntrl1812\"[label=\"Sequence(1812)\",shape=box];\n\"cntrl1813\"[label=\"Deallocate{}(1813)\"];\n\"cntrl1814\"[label=\"Sequence(1814)\",shape=box];\n\"cntrl1815\"[label=\"Deallocate{}(1815)\"];\n\"cntrl1816\"[label=\"Sequence(1816)\",shape=box];\n\"cntrl1817\"[label=\"Deallocate{}(1817)\"];\n\"cntrl1818\"[label=\"Sequence(1818)\",shape=box];\n\"cntrl1819\"[label=\"Deallocate{}(1819)\"];\n\"cntrl1820\"[label=\"Sequence(1820)\",shape=box];\n\"cntrl1821\"[label=\"Deallocate{}(1821)\"];\n\"cntrl1822\"[label=\"Sequence(1822)\",shape=box];\n\"cntrl1823\"[label=\"Deallocate{}(1823)\"];\n\"cntrl1824\"[label=\"Sequence(1824)\",shape=box];\n\"cntrl1825\"[label=\"Deallocate{}(1825)\"];\n\"cntrl1826\"[label=\"Sequence(1826)\",shape=box];\n\"cntrl1827\"[label=\"Deallocate{}(1827)\"];\n\"cntrl1828\"[label=\"Sequence(1828)\",shape=box];\n\"cntrl1829\"[label=\"Deallocate{}(1829)\"];\n\"cntrl1830\"[label=\"Sequence(1830)\",shape=box];\n\"cntrl1831\"[label=\"Deallocate{}(1831)\"];\n\"cntrl1832\"[label=\"Sequence(1832)\",shape=box];\n\"cntrl1833\"[label=\"Deallocate{}(1833)\"];\n\"cntrl1834\"[label=\"Sequence(1834)\",shape=box];\n\"cntrl1835\"[label=\"Deallocate{}(1835)\"];\n\"cntrl1836\"[label=\"Sequence(1836)\",shape=box];\n\"cntrl1837\"[label=\"Deallocate{}(1837)\"];\n\"cntrl1838\"[label=\"Sequence(1838)\",shape=box];\n\"cntrl1839\"[label=\"Deallocate{}(1839)\"];\n\"cntrl1840\"[label=\"Sequence(1840)\",shape=box];\n\"cntrl1841\"[label=\"Deallocate{}(1841)\"];\n\"cntrl1842\"[label=\"Sequence(1842)\",shape=box];\n\"cntrl1843\"[label=\"Deallocate{}(1843)\"];\n\"cntrl1844\"[label=\"Sequence(1844)\",shape=box];\n\"cntrl1845\"[label=\"Deallocate{}(1845)\"];\n\"cntrl1846\"[label=\"Sequence(1846)\",shape=box];\n\"cntrl1847\"[label=\"Deallocate{}(1847)\"];\n\"cntrl1848\"[label=\"Sequence(1848)\",shape=box];\n\"cntrl1849\"[label=\"Deallocate{}(1849)\"];\n\"cntrl1850\"[label=\"Sequence(1850)\",shape=box];\n\"cntrl1851\"[label=\"Deallocate{}(1851)\"];\n\"cntrl1852\"[label=\"Sequence(1852)\",shape=box];\n\"cntrl1853\"[label=\"Deallocate{}(1853)\"];\n\"cntrl1854\"[label=\"Sequence(1854)\",shape=box];\n\"cntrl1855\"[label=\"Deallocate{}(1855)\"];\n\"cntrl1856\"[label=\"Sequence(1856)\",shape=box];\n\"cntrl1857\"[label=\"Deallocate{}(1857)\"];\n\"cntrl1858\"[label=\"Sequence(1858)\",shape=box];\n\"cntrl1859\"[label=\"Deallocate{}(1859)\"];\n\"cntrl1860\"[label=\"Sequence(1860)\",shape=box];\n\"cntrl1861\"[label=\"Deallocate{}(1861)\"];\n\"cntrl1862\"[label=\"Sequence(1862)\",shape=box];\n\"cntrl1863\"[label=\"Deallocate{}(1863)\"];\n\"cntrl1864\"[label=\"Sequence(1864)\",shape=box];\n\"cntrl1865\"[label=\"Deallocate{}(1865)\"];\n\"cntrl1866\"[label=\"Sequence(1866)\",shape=box];\n\"cntrl1867\"[label=\"Deallocate{}(1867)\"];\n\"cntrl1868\"[label=\"Sequence(1868)\",shape=box];\n\"cntrl1869\"[label=\"Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869)\"];\n\"cntrl1870\"[label=\"Sequence(1870)\",shape=box];\n\"cntrl1871\"[label=\"Deallocate{}(1871)\"];\n\"cntrl1872\"[label=\"Sequence(1872)\",shape=box];\n\"cntrl1873\"[label=\"Deallocate{}(1873)\"];\n\"cntrl1874\"[label=\"Sequence(1874)\",shape=box];\n\"cntrl1875\"[label=\"Deallocate{}(1875)\"];\n\"cntrl1876\"[label=\"Sequence(1876)\",shape=box];\n\"cntrl1877\"[label=\"Deallocate{}(1877)\"];\n\"cntrl1878\"[label=\"Sequence(1878)\",shape=box];\n\"cntrl1879\"[label=\"Deallocate{}(1879)\"];\n\"cntrl1880\"[label=\"Sequence(1880)\",shape=box];\n\"cntrl1881\"[label=\"Deallocate{}(1881)\"];\n\"cntrl1882\"[label=\"Sequence(1882)\",shape=box];\n\"cntrl1883\"[label=\"Deallocate{}(1883)\"];\n\"cntrl1884\"[label=\"Sequence(1884)\",shape=box];\n\"cntrl1885\"[label=\"Deallocate{}(1885)\"];\n\"cntrl1886\"[label=\"Sequence(1886)\",shape=box];\n\"cntrl1887\"[label=\"Deallocate{}(1887)\"];\n\"cntrl1888\"[label=\"Sequence(1888)\",shape=box];\n\"cntrl1889\"[label=\"Deallocate{}(1889)\"];\n\"cntrl1890\"[label=\"Sequence(1890)\",shape=box];\n\"cntrl1891\"[label=\"Deallocate{}(1891)\"];\n\"cntrl1892\"[label=\"Sequence(1892)\",shape=box];\n\"cntrl1893\"[label=\"Deallocate{}(1893)\"];\n\"cntrl1894\"[label=\"Sequence(1894)\",shape=box];\n\"cntrl1895\"[label=\"Deallocate{}(1895)\"];\n\"cntrl1896\"[label=\"Sequence(1896)\",shape=box];\n\"cntrl1897\"[label=\"Deallocate{}(1897)\"];\n\"cntrl1898\"[label=\"Sequence(1898)\",shape=box];\n\"cntrl1899\"[label=\"Deallocate{}(1899)\"];\n\"cntrl1900\"[label=\"Sequence(1900)\",shape=box];\n\"cntrl1901\"[label=\"Deallocate{}(1901)\"];\n\"cntrl1902\"[label=\"Sequence(1902)\",shape=box];\n\"cntrl1903\"[label=\"Deallocate{}(1903)\"];\n\"cntrl1904\"[label=\"Sequence(1904)\",shape=box];\n\"cntrl1905\"[label=\"Deallocate{}(1905)\"];\n\"cntrl1906\"[label=\"Sequence(1906)\",shape=box];\n\"cntrl1907\"[label=\"Deallocate{}(1907)\"];\n\"cntrl1908\"[label=\"Sequence(1908)\",shape=box];\n\"cntrl1909\"[label=\"Deallocate{}(1909)\"];\n\"cntrl1910\"[label=\"Sequence(1910)\",shape=box];\n\"cntrl1911\"[label=\"Deallocate{}(1911)\"];\n\"cntrl1912\"[label=\"Sequence(1912)\",shape=box];\n\"cntrl1913\"[label=\"Deallocate{}(1913)\"];\n\"cntrl1914\"[label=\"Sequence(1914)\",shape=box];\n\"cntrl1915\"[label=\"Sequence(1915)\",shape=box];\n\"cntrl1916\"[label=\"Sequence(1916)\",shape=box];\n\"cntrl1917\"[label=\"Sequence(1917)\",shape=box];\n\"cntrl1918\"[label=\"Deallocate{}(1918)\"];\n\"cntrl1919\"[label=\"Sequence(1919)\",shape=box];\n\"cntrl1920\"[label=\"Sequence(1920)\",shape=box];\n\"cntrl1921\"[label=\"Sequence(1921)\",shape=box];\n\"cntrl1922\"[label=\"Sequence(1922)\",shape=box];\n\"cntrl1923\"[label=\"Sequence(1923)\",shape=box];\n\"cntrl1924\"[label=\"Sequence(1924)\",shape=box];\n\"cntrl1925\"[label=\"Sequence(1925)\",shape=box];\n\"cntrl1926\"[label=\"Sequence(1926)\",shape=box];\n\"cntrl1927\"[label=\"Sequence(1927)\",shape=box];\n\"cntrl1928\"[label=\"Sequence(1928)\",shape=box];\n\"cntrl1929\"[label=\"Sequence(1929)\",shape=box];\n\"cntrl1930\"[label=\"Sequence(1930)\",shape=box];\n\"cntrl1931\"[label=\"Sequence(1931)\",shape=box];\n\"cntrl1932\"[label=\"Sequence(1932)\",shape=box];\n\"cntrl1933\"[label=\"Sequence(1933)\",shape=box];\n\"cntrl1934\"[label=\"Sequence(1934)\",shape=box];\n\"cntrl1935\"[label=\"Sequence(1935)\",shape=box];\n\"cntrl1936\"[label=\"Sequence(1936)\",shape=box];\n\"cntrl1937\"[label=\"Sequence(1937)\",shape=box];\n\"cntrl1938\"[label=\"Sequence(1938)\",shape=box];\n\"cntrl1939\"[label=\"Sequence(1939)\",shape=box];\n\"cntrl1940\"[label=\"Sequence(1940)\",shape=box];\n\"cntrl1941\"[label=\"Sequence(1941)\",shape=box];\n\"cntrl1942\"[label=\"Sequence(1942)\",shape=box];\n\"cntrl1943\"[label=\"Sequence(1943)\",shape=box];\n\"cntrl1944\"[label=\"Sequence(1944)\",shape=box];\n\"cntrl1945\"[label=\"Sequence(1945)\",shape=box];\n\"cntrl1946\"[label=\"Sequence(1946)\",shape=box];\n\"cntrl1947\"[label=\"Sequence(1947)\",shape=box];\n\"cntrl1948\"[label=\"Sequence(1948)\",shape=box];\n\"cntrl1949\"[label=\"Sequence(1949)\",shape=box];\n\"cntrl1950\"[label=\"Sequence(1950)\",shape=box];\n\"cntrl1951\"[label=\"Sequence(1951)\",shape=box];\n\"cntrl1952\"[label=\"Sequence(1952)\",shape=box];\n\"cntrl1953\"[label=\"Sequence(1953)\",shape=box];\n\"cntrl1954\"[label=\"Sequence(1954)\",shape=box];\n\"cntrl1955\"[label=\"Sequence(1955)\",shape=box];\n\"cntrl1956\"[label=\"Sequence(1956)\",shape=box];\n\"cntrl1957\"[label=\"Sequence(1957)\",shape=box];\n\"cntrl1958\"[label=\"Sequence(1958)\",shape=box];\n\"cntrl1959\"[label=\"Sequence(1959)\",shape=box];\n\"cntrl1960\"[label=\"Sequence(1960)\",shape=box];\n\"cntrl1961\"[label=\"Sequence(1961)\",shape=box];\n\"cntrl1962\"[label=\"Sequence(1962)\",shape=box];\n\"cntrl1963\"[label=\"Sequence(1963)\",shape=box];\n\"cntrl1964\"[label=\"Sequence(1964)\",shape=box];\n\"cntrl1965\"[label=\"Sequence(1965)\",shape=box];\n\"cntrl1966\"[label=\"Sequence(1966)\",shape=box];\n\"cntrl1967\"[label=\"Sequence(1967)\",shape=box];\n\"cntrl1968\"[label=\"Sequence(1968)\",shape=box];\n\"cntrl1969\"[label=\"Sequence(1969)\",shape=box];\n\"cntrl1970\"[label=\"Sequence(1970)\",shape=box];\n\"cntrl1971\"[label=\"Sequence(1971)\",shape=box];\n\"cntrl1972\"[label=\"Sequence(1972)\",shape=box];\n\"cntrl1973\"[label=\"Sequence(1973)\",shape=box];\n\"cntrl1974\"[label=\"Sequence(1974)\",shape=box];\n\"cntrl1975\"[label=\"Sequence(1975)\",shape=box];\n\"cntrl1976\"[label=\"Sequence(1976)\",shape=box];\n\"cntrl1977\"[label=\"Sequence(1977)\",shape=box];\n\"cntrl1978\"[label=\"Sequence(1978)\",shape=box];\n\"cntrl1979\"[label=\"Sequence(1979)\",shape=box];\n\"cntrl1980\"[label=\"Sequence(1980)\",shape=box];\n\"cntrl1981\"[label=\"Sequence(1981)\",shape=box];\n\"cntrl1982\"[label=\"Sequence(1982)\",shape=box];\n\"cntrl1983\"[label=\"Sequence(1983)\",shape=box];\n\"cntrl1984\"[label=\"Sequence(1984)\",shape=box];\n\"cntrl1985\"[label=\"Sequence(1985)\",shape=box];\n\"cntrl1986\"[label=\"Sequence(1986)\",shape=box];\n\"cntrl1987\"[label=\"Sequence(1987)\",shape=box];\n\"cntrl1988\"[label=\"Sequence(1988)\",shape=box];\n\"cntrl1989\"[label=\"Sequence(1989)\",shape=box];\n\"cntrl1990\"[label=\"Sequence(1990)\",shape=box];\n\"cntrl1991\"[label=\"Sequence(1991)\",shape=box];\n\"cntrl1992\"[label=\"Sequence(1992)\",shape=box];\n\"cntrl1993\"[label=\"Sequence(1993)\",shape=box];\n\"cntrl1994\"[label=\"Sequence(1994)\",shape=box];\n\"cntrl1995\"[label=\"Sequence(1995)\",shape=box];\n\"cntrl1996\"[label=\"Sequence(1996)\",shape=box];\n\"cntrl1997\"[label=\"Deallocate{user_Float_Value_8}(1997)\"];\n\"cntrl1998\"[label=\"Sequence(1998)\",shape=box];\n\"cntrl1999\"[label=\"Deallocate{user_Float_Value_6}(1999)\"];\n\"cntrl2000\"[label=\"Sequence(2000)\",shape=box];\n\"cntrl2003\"[label=\"Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003)\"];\n\"cntrl2004\"[label=\"Sequence(2004)\",shape=box];\n\"cntrl2007\"[label=\"Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007)\"];\n\"cntrl2008\"[label=\"Sequence(2008)\",shape=box];\n\"cntrl2009\"[label=\"Sequence(2009)\",shape=box];\n\"cntrl2010\"[label=\"Sequence(2010)\",shape=box];\n\"cntrl2011\"[label=\"Sequence(2011)\",shape=box];\n\"cntrl1\" -> \"cntrl1242\"\n\"cntrl1\" -> \"cntrl1294\"\n\"cntrl1\" -> \"cntrl1367\"\n\"cntrl1\" -> \"cntrl1406\"\n\"cntrl1\" -> \"cntrl1445\"\n\"cntrl1\" -> \"cntrl1484\"\n\"cntrl1\" -> \"cntrl1523\"\n\"cntrl1\" -> \"cntrl1562\"\n\"cntrl2\" -> \"cntrl1998\"\n\"cntrl24\" -> \"cntrl2000\"\n\"cntrl29\" -> \"cntrl668\"\n\"cntrl35\" -> \"cntrl1762\"\n\"cntrl37\" -> \"cntrl1764\"\n\"cntrl39\" -> \"cntrl42\"\n\"cntrl39\" -> \"cntrl810\"\n\"cntrl39\" -> \"cntrl816\"\n\"cntrl39\" -> \"cntrl1586\"\n\"cntrl39\" -> \"cntrl1734\"\n\"cntrl39\" -> \"cntrl1766\"\n\"cntrl42\" -> \"cntrl40\"\n\"cntrl44\" -> \"cntrl1075\"\n\"cntrl47\" -> \"cntrl50\"\n\"cntrl47\" -> \"cntrl955\"\n\"cntrl50\" -> \"cntrl49\"\n\"cntrl52\" -> \"cntrl55\"\n\"cntrl52\" -> \"cntrl947\"\n\"cntrl55\" -> \"cntrl54\"\n\"cntrl57\" -> \"cntrl1629\"\n\"cntrl57\" -> \"cntrl1660\"\n\"cntrl58\" -> \"cntrl61\"\n\"cntrl58\" -> \"cntrl956\"\n\"cntrl61\" -> \"cntrl60\"\n\"cntrl62\" -> \"cntrl65\"\n\"cntrl62\" -> \"cntrl948\"\n\"cntrl65\" -> \"cntrl64\"\n\"cntrl66\" -> \"cntrl1630\"\n\"cntrl66\" -> \"cntrl1668\"\n\"cntrl67\" -> \"cntrl70\"\n\"cntrl67\" -> \"cntrl957\"\n\"cntrl70\" -> \"cntrl69\"\n\"cntrl71\" -> \"cntrl74\"\n\"cntrl71\" -> \"cntrl949\"\n\"cntrl74\" -> \"cntrl73\"\n\"cntrl75\" -> \"cntrl1631\"\n\"cntrl75\" -> \"cntrl1670\"\n\"cntrl76\" -> \"cntrl79\"\n\"cntrl76\" -> \"cntrl958\"\n\"cntrl79\" -> \"cntrl78\"\n\"cntrl80\" -> \"cntrl83\"\n\"cntrl80\" -> \"cntrl950\"\n\"cntrl83\" -> \"cntrl82\"\n\"cntrl84\" -> \"cntrl1632\"\n\"cntrl84\" -> \"cntrl1672\"\n\"cntrl85\" -> \"cntrl88\"\n\"cntrl85\" -> \"cntrl959\"\n\"cntrl88\" -> \"cntrl87\"\n\"cntrl89\" -> \"cntrl92\"\n\"cntrl89\" -> \"cntrl951\"\n\"cntrl92\" -> \"cntrl91\"\n\"cntrl93\" -> \"cntrl1633\"\n\"cntrl93\" -> \"cntrl1674\"\n\"cntrl94\" -> \"cntrl97\"\n\"cntrl94\" -> \"cntrl960\"\n\"cntrl97\" -> \"cntrl96\"\n\"cntrl98\" -> \"cntrl101\"\n\"cntrl98\" -> \"cntrl952\"\n\"cntrl101\" -> \"cntrl100\"\n\"cntrl102\" -> \"cntrl1634\"\n\"cntrl103\" -> \"cntrl106\"\n\"cntrl103\" -> \"cntrl961\"\n\"cntrl106\" -> \"cntrl105\"\n\"cntrl107\" -> \"cntrl110\"\n\"cntrl107\" -> \"cntrl953\"\n\"cntrl110\" -> \"cntrl109\"\n\"cntrl111\" -> \"cntrl1635\"\n\"cntrl112\" -> \"cntrl115\"\n\"cntrl112\" -> \"cntrl962\"\n\"cntrl115\" -> \"cntrl114\"\n\"cntrl116\" -> \"cntrl119\"\n\"cntrl116\" -> \"cntrl954\"\n\"cntrl119\" -> \"cntrl118\"\n\"cntrl120\" -> \"cntrl844\"\n\"cntrl177\" -> \"cntrl679\"\n\"cntrl177\" -> \"cntrl685\"\n\"cntrl177\" -> \"cntrl1770\"\n\"cntrl185\" -> \"cntrl203\"\n\"cntrl185\" -> \"cntrl1182\"\n\"cntrl186\" -> \"cntrl194\"\n\"cntrl187\" -> \"cntrl1772\"\n\"cntrl188\" -> \"cntrl1774\"\n\"cntrl189\" -> \"cntrl1776\"\n\"cntrl190\" -> \"cntrl1778\"\n\"cntrl191\" -> \"cntrl1780\"\n\"cntrl194\" -> \"cntrl187\"\n\"cntrl203\" -> \"cntrl186\"\n\"cntrl217\" -> \"cntrl220\"\n\"cntrl217\" -> \"cntrl1595\"\n\"cntrl217\" -> \"cntrl1727\"\n\"cntrl217\" -> \"cntrl1782\"\n\"cntrl220\" -> \"cntrl218\"\n\"cntrl224\" -> \"cntrl273\"\n\"cntrl224\" -> \"cntrl1740\"\n\"cntrl226\" -> \"cntrl275\"\n\"cntrl226\" -> \"cntrl276\"\n\"cntrl228\" -> \"cntrl1784\"\n\"cntrl229\" -> \"cntrl278\"\n\"cntrl229\" -> \"cntrl279\"\n\"cntrl231\" -> \"cntrl280\"\n\"cntrl231\" -> \"cntrl281\"\n\"cntrl233\" -> \"cntrl1786\"\n\"cntrl234\" -> \"cntrl283\"\n\"cntrl234\" -> \"cntrl284\"\n\"cntrl236\" -> \"cntrl285\"\n\"cntrl236\" -> \"cntrl286\"\n\"cntrl238\" -> \"cntrl1788\"\n\"cntrl239\" -> \"cntrl288\"\n\"cntrl239\" -> \"cntrl289\"\n\"cntrl241\" -> \"cntrl290\"\n\"cntrl241\" -> \"cntrl291\"\n\"cntrl243\" -> \"cntrl1790\"\n\"cntrl244\" -> \"cntrl293\"\n\"cntrl244\" -> \"cntrl294\"\n\"cntrl246\" -> \"cntrl295\"\n\"cntrl246\" -> \"cntrl296\"\n\"cntrl248\" -> \"cntrl1792\"\n\"cntrl249\" -> \"cntrl298\"\n\"cntrl249\" -> \"cntrl299\"\n\"cntrl251\" -> \"cntrl300\"\n\"cntrl251\" -> \"cntrl301\"\n\"cntrl253\" -> \"cntrl1794\"\n\"cntrl254\" -> \"cntrl303\"\n\"cntrl254\" -> \"cntrl304\"\n\"cntrl256\" -> \"cntrl305\"\n\"cntrl256\" -> \"cntrl306\"\n\"cntrl258\" -> \"cntrl1796\"\n\"cntrl259\" -> \"cntrl308\"\n\"cntrl259\" -> \"cntrl309\"\n\"cntrl261\" -> \"cntrl310\"\n\"cntrl261\" -> \"cntrl311\"\n\"cntrl263\" -> \"cntrl1798\"\n\"cntrl273\" -> \"cntrl225\"\n\"cntrl275\" -> \"cntrl227\"\n\"cntrl276\" -> \"cntrl228\"\n\"cntrl278\" -> \"cntrl230\"\n\"cntrl279\" -> \"cntrl231\"\n\"cntrl280\" -> \"cntrl232\"\n\"cntrl281\" -> \"cntrl233\"\n\"cntrl283\" -> \"cntrl235\"\n\"cntrl284\" -> \"cntrl236\"\n\"cntrl285\" -> \"cntrl237\"\n\"cntrl286\" -> \"cntrl238\"\n\"cntrl288\" -> \"cntrl240\"\n\"cntrl289\" -> \"cntrl241\"\n\"cntrl290\" -> \"cntrl242\"\n\"cntrl291\" -> \"cntrl243\"\n\"cntrl293\" -> \"cntrl245\"\n\"cntrl294\" -> \"cntrl246\"\n\"cntrl295\" -> \"cntrl247\"\n\"cntrl296\" -> \"cntrl248\"\n\"cntrl298\" -> \"cntrl250\"\n\"cntrl299\" -> \"cntrl251\"\n\"cntrl300\" -> \"cntrl252\"\n\"cntrl301\" -> \"cntrl253\"\n\"cntrl303\" -> \"cntrl255\"\n\"cntrl304\" -> \"cntrl256\"\n\"cntrl305\" -> \"cntrl257\"\n\"cntrl306\" -> \"cntrl258\"\n\"cntrl308\" -> \"cntrl260\"\n\"cntrl309\" -> \"cntrl261\"\n\"cntrl310\" -> \"cntrl262\"\n\"cntrl311\" -> \"cntrl263\"\n\"cntrl313\" -> \"cntrl315\"\n\"cntrl313\" -> \"cntrl1800\"\n\"cntrl313\" -> \"cntrl2004\"\n\"cntrl314\" -> \"cntrl1052\"\n\"cntrl315\" -> \"cntrl314\"\n\"cntrl318\" -> \"cntrl982\"\n\"cntrl318\" -> \"cntrl984\"\n\"cntrl318\" -> \"cntrl1737\"\n\"cntrl323\" -> \"cntrl988\"\n\"cntrl323\" -> \"cntrl990\"\n\"cntrl323\" -> \"cntrl1730\"\n\"cntrl330\" -> \"cntrl379\"\n\"cntrl330\" -> \"cntrl829\"\n\"cntrl332\" -> \"cntrl381\"\n\"cntrl332\" -> \"cntrl821\"\n\"cntrl334\" -> \"cntrl1804\"\n\"cntrl335\" -> \"cntrl384\"\n\"cntrl335\" -> \"cntrl830\"\n\"cntrl337\" -> \"cntrl386\"\n\"cntrl337\" -> \"cntrl822\"\n\"cntrl339\" -> \"cntrl1806\"\n\"cntrl340\" -> \"cntrl389\"\n\"cntrl340\" -> \"cntrl831\"\n\"cntrl342\" -> \"cntrl391\"\n\"cntrl342\" -> \"cntrl823\"\n\"cntrl344\" -> \"cntrl1808\"\n\"cntrl345\" -> \"cntrl394\"\n\"cntrl345\" -> \"cntrl832\"\n\"cntrl347\" -> \"cntrl396\"\n\"cntrl347\" -> \"cntrl824\"\n\"cntrl349\" -> \"cntrl1810\"\n\"cntrl350\" -> \"cntrl399\"\n\"cntrl350\" -> \"cntrl833\"\n\"cntrl352\" -> \"cntrl401\"\n\"cntrl352\" -> \"cntrl825\"\n\"cntrl354\" -> \"cntrl1812\"\n\"cntrl355\" -> \"cntrl404\"\n\"cntrl355\" -> \"cntrl834\"\n\"cntrl357\" -> \"cntrl406\"\n\"cntrl357\" -> \"cntrl826\"\n\"cntrl359\" -> \"cntrl1814\"\n\"cntrl360\" -> \"cntrl409\"\n\"cntrl360\" -> \"cntrl835\"\n\"cntrl362\" -> \"cntrl411\"\n\"cntrl362\" -> \"cntrl827\"\n\"cntrl364\" -> \"cntrl1816\"\n\"cntrl365\" -> \"cntrl414\"\n\"cntrl365\" -> \"cntrl1818\"\n\"cntrl367\" -> \"cntrl416\"\n\"cntrl367\" -> \"cntrl1820\"\n\"cntrl369\" -> \"cntrl1822\"\n\"cntrl379\" -> \"cntrl331\"\n\"cntrl381\" -> \"cntrl333\"\n\"cntrl384\" -> \"cntrl336\"\n\"cntrl386\" -> \"cntrl338\"\n\"cntrl389\" -> \"cntrl341\"\n\"cntrl391\" -> \"cntrl343\"\n\"cntrl394\" -> \"cntrl346\"\n\"cntrl396\" -> \"cntrl348\"\n\"cntrl399\" -> \"cntrl351\"\n\"cntrl401\" -> \"cntrl353\"\n\"cntrl404\" -> \"cntrl356\"\n\"cntrl406\" -> \"cntrl358\"\n\"cntrl409\" -> \"cntrl361\"\n\"cntrl411\" -> \"cntrl363\"\n\"cntrl414\" -> \"cntrl366\"\n\"cntrl416\" -> \"cntrl368\"\n\"cntrl420\" -> \"cntrl469\"\n\"cntrl420\" -> \"cntrl871\"\n\"cntrl422\" -> \"cntrl471\"\n\"cntrl422\" -> \"cntrl863\"\n\"cntrl424\" -> \"cntrl1824\"\n\"cntrl425\" -> \"cntrl474\"\n\"cntrl425\" -> \"cntrl872\"\n\"cntrl427\" -> \"cntrl476\"\n\"cntrl427\" -> \"cntrl864\"\n\"cntrl429\" -> \"cntrl1826\"\n\"cntrl430\" -> \"cntrl479\"\n\"cntrl430\" -> \"cntrl873\"\n\"cntrl432\" -> \"cntrl481\"\n\"cntrl432\" -> \"cntrl865\"\n\"cntrl434\" -> \"cntrl1828\"\n\"cntrl435\" -> \"cntrl484\"\n\"cntrl435\" -> \"cntrl874\"\n\"cntrl437\" -> \"cntrl486\"\n\"cntrl437\" -> \"cntrl866\"\n\"cntrl439\" -> \"cntrl1830\"\n\"cntrl440\" -> \"cntrl489\"\n\"cntrl440\" -> \"cntrl875\"\n\"cntrl442\" -> \"cntrl491\"\n\"cntrl442\" -> \"cntrl867\"\n\"cntrl444\" -> \"cntrl1832\"\n\"cntrl445\" -> \"cntrl494\"\n\"cntrl445\" -> \"cntrl876\"\n\"cntrl447\" -> \"cntrl496\"\n\"cntrl447\" -> \"cntrl868\"\n\"cntrl449\" -> \"cntrl1834\"\n\"cntrl450\" -> \"cntrl499\"\n\"cntrl450\" -> \"cntrl877\"\n\"cntrl452\" -> \"cntrl501\"\n\"cntrl452\" -> \"cntrl869\"\n\"cntrl454\" -> \"cntrl1836\"\n\"cntrl455\" -> \"cntrl504\"\n\"cntrl455\" -> \"cntrl1838\"\n\"cntrl457\" -> \"cntrl506\"\n\"cntrl457\" -> \"cntrl1840\"\n\"cntrl459\" -> \"cntrl1842\"\n\"cntrl469\" -> \"cntrl421\"\n\"cntrl471\" -> \"cntrl423\"\n\"cntrl474\" -> \"cntrl426\"\n\"cntrl476\" -> \"cntrl428\"\n\"cntrl479\" -> \"cntrl431\"\n\"cntrl481\" -> \"cntrl433\"\n\"cntrl484\" -> \"cntrl436\"\n\"cntrl486\" -> \"cntrl438\"\n\"cntrl489\" -> \"cntrl441\"\n\"cntrl491\" -> \"cntrl443\"\n\"cntrl494\" -> \"cntrl446\"\n\"cntrl496\" -> \"cntrl448\"\n\"cntrl499\" -> \"cntrl451\"\n\"cntrl501\" -> \"cntrl453\"\n\"cntrl504\" -> \"cntrl456\"\n\"cntrl506\" -> \"cntrl458\"\n\"cntrl510\" -> \"cntrl559\"\n\"cntrl510\" -> \"cntrl913\"\n\"cntrl512\" -> \"cntrl561\"\n\"cntrl512\" -> \"cntrl905\"\n\"cntrl514\" -> \"cntrl1844\"\n\"cntrl515\" -> \"cntrl564\"\n\"cntrl515\" -> \"cntrl914\"\n\"cntrl517\" -> \"cntrl566\"\n\"cntrl517\" -> \"cntrl906\"\n\"cntrl519\" -> \"cntrl1846\"\n\"cntrl520\" -> \"cntrl569\"\n\"cntrl520\" -> \"cntrl915\"\n\"cntrl522\" -> \"cntrl571\"\n\"cntrl522\" -> \"cntrl907\"\n\"cntrl524\" -> \"cntrl1848\"\n\"cntrl525\" -> \"cntrl574\"\n\"cntrl525\" -> \"cntrl916\"\n\"cntrl527\" -> \"cntrl576\"\n\"cntrl527\" -> \"cntrl908\"\n\"cntrl529\" -> \"cntrl1850\"\n\"cntrl530\" -> \"cntrl579\"\n\"cntrl530\" -> \"cntrl917\"\n\"cntrl532\" -> \"cntrl581\"\n\"cntrl532\" -> \"cntrl909\"\n\"cntrl534\" -> \"cntrl1852\"\n\"cntrl535\" -> \"cntrl584\"\n\"cntrl535\" -> \"cntrl918\"\n\"cntrl537\" -> \"cntrl586\"\n\"cntrl537\" -> \"cntrl910\"\n\"cntrl539\" -> \"cntrl1854\"\n\"cntrl540\" -> \"cntrl589\"\n\"cntrl540\" -> \"cntrl919\"\n\"cntrl542\" -> \"cntrl591\"\n\"cntrl542\" -> \"cntrl911\"\n\"cntrl544\" -> \"cntrl1856\"\n\"cntrl545\" -> \"cntrl594\"\n\"cntrl545\" -> \"cntrl1858\"\n\"cntrl547\" -> \"cntrl596\"\n\"cntrl547\" -> \"cntrl1860\"\n\"cntrl549\" -> \"cntrl1862\"\n\"cntrl559\" -> \"cntrl511\"\n\"cntrl561\" -> \"cntrl513\"\n\"cntrl564\" -> \"cntrl516\"\n\"cntrl566\" -> \"cntrl518\"\n\"cntrl569\" -> \"cntrl521\"\n\"cntrl571\" -> \"cntrl523\"\n\"cntrl574\" -> \"cntrl526\"\n\"cntrl576\" -> \"cntrl528\"\n\"cntrl579\" -> \"cntrl531\"\n\"cntrl581\" -> \"cntrl533\"\n\"cntrl584\" -> \"cntrl536\"\n\"cntrl586\" -> \"cntrl538\"\n\"cntrl589\" -> \"cntrl541\"\n\"cntrl591\" -> \"cntrl543\"\n\"cntrl594\" -> \"cntrl546\"\n\"cntrl596\" -> \"cntrl548\"\n\"cntrl599\" -> \"cntrl972\"\n\"cntrl599\" -> \"cntrl1001\"\n\"cntrl604\" -> \"cntrl977\"\n\"cntrl604\" -> \"cntrl1724\"\n\"cntrl610\" -> \"cntrl994\"\n\"cntrl610\" -> \"cntrl1011\"\n\"cntrl615\" -> \"cntrl999\"\n\"cntrl615\" -> \"cntrl1744\"\n\"cntrl624\" -> \"cntrl1004\"\n\"cntrl624\" -> \"cntrl1021\"\n\"cntrl629\" -> \"cntrl1009\"\n\"cntrl629\" -> \"cntrl1750\"\n\"cntrl638\" -> \"cntrl1014\"\n\"cntrl638\" -> \"cntrl1864\"\n\"cntrl643\" -> \"cntrl1019\"\n\"cntrl643\" -> \"cntrl1866\"\n\"cntrl668\" -> \"cntrl35\"\n\"cntrl670\" -> \"cntrl676\"\n\"cntrl670\" -> \"cntrl1868\"\n\"cntrl675\" -> \"cntrl677\"\n\"cntrl676\" -> \"cntrl675\"\n\"cntrl677\" -> \"cntrl44\"\n\"cntrl678\" -> \"cntrl682\"\n\"cntrl679\" -> \"cntrl678\"\n\"cntrl681\" -> \"cntrl683\"\n\"cntrl682\" -> \"cntrl681\"\n\"cntrl683\" -> \"cntrl29\"\n\"cntrl684\" -> \"cntrl688\"\n\"cntrl684\" -> \"cntrl1870\"\n\"cntrl685\" -> \"cntrl684\"\n\"cntrl687\" -> \"cntrl689\"\n\"cntrl688\" -> \"cntrl687\"\n\"cntrl689\" -> \"cntrl185\"\n\"cntrl690\" -> \"cntrl722\"\n\"cntrl693\" -> \"cntrl781\"\n\"cntrl694\" -> \"cntrl1200\"\n\"cntrl696\" -> \"cntrl723\"\n\"cntrl696\" -> \"cntrl1280\"\n\"cntrl699\" -> \"cntrl724\"\n\"cntrl699\" -> \"cntrl1228\"\n\"cntrl702\" -> \"cntrl725\"\n\"cntrl702\" -> \"cntrl1392\"\n\"cntrl705\" -> \"cntrl726\"\n\"cntrl705\" -> \"cntrl1353\"\n\"cntrl708\" -> \"cntrl727\"\n\"cntrl708\" -> \"cntrl1470\"\n\"cntrl711\" -> \"cntrl728\"\n\"cntrl711\" -> \"cntrl1431\"\n\"cntrl714\" -> \"cntrl1548\"\n\"cntrl714\" -> \"cntrl1872\"\n\"cntrl717\" -> \"cntrl1509\"\n\"cntrl717\" -> \"cntrl1874\"\n\"cntrl722\" -> \"cntrl696\"\n\"cntrl723\" -> \"cntrl699\"\n\"cntrl724\" -> \"cntrl702\"\n\"cntrl725\" -> \"cntrl705\"\n\"cntrl726\" -> \"cntrl708\"\n\"cntrl727\" -> \"cntrl711\"\n\"cntrl728\" -> \"cntrl714\"\n\"cntrl733\" -> \"cntrl735\"\n\"cntrl733\" -> \"cntrl790\"\n\"cntrl735\" -> \"cntrl734\"\n\"cntrl736\" -> \"cntrl738\"\n\"cntrl736\" -> \"cntrl791\"\n\"cntrl738\" -> \"cntrl737\"\n\"cntrl739\" -> \"cntrl741\"\n\"cntrl739\" -> \"cntrl792\"\n\"cntrl741\" -> \"cntrl740\"\n\"cntrl742\" -> \"cntrl744\"\n\"cntrl742\" -> \"cntrl793\"\n\"cntrl744\" -> \"cntrl743\"\n\"cntrl745\" -> \"cntrl747\"\n\"cntrl745\" -> \"cntrl794\"\n\"cntrl747\" -> \"cntrl746\"\n\"cntrl748\" -> \"cntrl750\"\n\"cntrl748\" -> \"cntrl795\"\n\"cntrl750\" -> \"cntrl749\"\n\"cntrl751\" -> \"cntrl753\"\n\"cntrl751\" -> \"cntrl796\"\n\"cntrl753\" -> \"cntrl752\"\n\"cntrl754\" -> \"cntrl756\"\n\"cntrl754\" -> \"cntrl797\"\n\"cntrl756\" -> \"cntrl755\"\n\"cntrl757\" -> \"cntrl759\"\n\"cntrl757\" -> \"cntrl782\"\n\"cntrl759\" -> \"cntrl758\"\n\"cntrl760\" -> \"cntrl762\"\n\"cntrl760\" -> \"cntrl783\"\n\"cntrl762\" -> \"cntrl761\"\n\"cntrl763\" -> \"cntrl765\"\n\"cntrl763\" -> \"cntrl784\"\n\"cntrl765\" -> \"cntrl764\"\n\"cntrl766\" -> \"cntrl768\"\n\"cntrl766\" -> \"cntrl785\"\n\"cntrl768\" -> \"cntrl767\"\n\"cntrl769\" -> \"cntrl771\"\n\"cntrl769\" -> \"cntrl786\"\n\"cntrl771\" -> \"cntrl770\"\n\"cntrl772\" -> \"cntrl774\"\n\"cntrl772\" -> \"cntrl787\"\n\"cntrl774\" -> \"cntrl773\"\n\"cntrl775\" -> \"cntrl777\"\n\"cntrl775\" -> \"cntrl788\"\n\"cntrl777\" -> \"cntrl776\"\n\"cntrl778\" -> \"cntrl780\"\n\"cntrl778\" -> \"cntrl789\"\n\"cntrl780\" -> \"cntrl779\"\n\"cntrl781\" -> \"cntrl757\"\n\"cntrl782\" -> \"cntrl760\"\n\"cntrl783\" -> \"cntrl763\"\n\"cntrl784\" -> \"cntrl766\"\n\"cntrl785\" -> \"cntrl769\"\n\"cntrl786\" -> \"cntrl772\"\n\"cntrl787\" -> \"cntrl775\"\n\"cntrl788\" -> \"cntrl778\"\n\"cntrl789\" -> \"cntrl733\"\n\"cntrl790\" -> \"cntrl736\"\n\"cntrl791\" -> \"cntrl739\"\n\"cntrl792\" -> \"cntrl742\"\n\"cntrl793\" -> \"cntrl745\"\n\"cntrl794\" -> \"cntrl748\"\n\"cntrl795\" -> \"cntrl751\"\n\"cntrl796\" -> \"cntrl754\"\n\"cntrl797\" -> \"cntrl694\"\n\"cntrl799\" -> \"cntrl845\"\n\"cntrl799\" -> \"cntrl858\"\n\"cntrl799\" -> \"cntrl1747\"\n\"cntrl800\" -> \"cntrl887\"\n\"cntrl800\" -> \"cntrl900\"\n\"cntrl800\" -> \"cntrl1753\"\n\"cntrl801\" -> \"cntrl929\"\n\"cntrl801\" -> \"cntrl942\"\n\"cntrl801\" -> \"cntrl1759\"\n\"cntrl810\" -> \"cntrl57\"\n\"cntrl811\" -> \"cntrl820\"\n\"cntrl816\" -> \"cntrl811\"\n\"cntrl820\" -> \"cntrl332\"\n\"cntrl821\" -> \"cntrl337\"\n\"cntrl822\" -> \"cntrl342\"\n\"cntrl823\" -> \"cntrl347\"\n\"cntrl824\" -> \"cntrl352\"\n\"cntrl825\" -> \"cntrl357\"\n\"cntrl826\" -> \"cntrl362\"\n\"cntrl827\" -> \"cntrl367\"\n\"cntrl829\" -> \"cntrl335\"\n\"cntrl830\" -> \"cntrl340\"\n\"cntrl831\" -> \"cntrl345\"\n\"cntrl832\" -> \"cntrl350\"\n\"cntrl833\" -> \"cntrl355\"\n\"cntrl834\" -> \"cntrl360\"\n\"cntrl835\" -> \"cntrl365\"\n\"cntrl844\" -> \"cntrl799\"\n\"cntrl845\" -> \"cntrl334\"\n\"cntrl853\" -> \"cntrl862\"\n\"cntrl858\" -> \"cntrl853\"\n\"cntrl862\" -> \"cntrl422\"\n\"cntrl863\" -> \"cntrl427\"\n\"cntrl864\" -> \"cntrl432\"\n\"cntrl865\" -> \"cntrl437\"\n\"cntrl866\" -> \"cntrl442\"\n\"cntrl867\" -> \"cntrl447\"\n\"cntrl868\" -> \"cntrl452\"\n\"cntrl869\" -> \"cntrl457\"\n\"cntrl871\" -> \"cntrl425\"\n\"cntrl872\" -> \"cntrl430\"\n\"cntrl873\" -> \"cntrl435\"\n\"cntrl874\" -> \"cntrl440\"\n\"cntrl875\" -> \"cntrl445\"\n\"cntrl876\" -> \"cntrl450\"\n\"cntrl877\" -> \"cntrl455\"\n\"cntrl887\" -> \"cntrl424\"\n\"cntrl895\" -> \"cntrl904\"\n\"cntrl900\" -> \"cntrl895\"\n\"cntrl904\" -> \"cntrl512\"\n\"cntrl905\" -> \"cntrl517\"\n\"cntrl906\" -> \"cntrl522\"\n\"cntrl907\" -> \"cntrl527\"\n\"cntrl908\" -> \"cntrl532\"\n\"cntrl909\" -> \"cntrl537\"\n\"cntrl910\" -> \"cntrl542\"\n\"cntrl911\" -> \"cntrl547\"\n\"cntrl913\" -> \"cntrl515\"\n\"cntrl914\" -> \"cntrl520\"\n\"cntrl915\" -> \"cntrl525\"\n\"cntrl916\" -> \"cntrl530\"\n\"cntrl917\" -> \"cntrl535\"\n\"cntrl918\" -> \"cntrl540\"\n\"cntrl919\" -> \"cntrl545\"\n\"cntrl929\" -> \"cntrl514\"\n\"cntrl937\" -> \"cntrl946\"\n\"cntrl942\" -> \"cntrl937\"\n\"cntrl946\" -> \"cntrl52\"\n\"cntrl947\" -> \"cntrl62\"\n\"cntrl948\" -> \"cntrl71\"\n\"cntrl949\" -> \"cntrl80\"\n\"cntrl950\" -> \"cntrl89\"\n\"cntrl951\" -> \"cntrl98\"\n\"cntrl952\" -> \"cntrl107\"\n\"cntrl953\" -> \"cntrl116\"\n\"cntrl954\" -> \"cntrl47\"\n\"cntrl955\" -> \"cntrl58\"\n\"cntrl956\" -> \"cntrl67\"\n\"cntrl957\" -> \"cntrl76\"\n\"cntrl958\" -> \"cntrl85\"\n\"cntrl959\" -> \"cntrl94\"\n\"cntrl960\" -> \"cntrl103\"\n\"cntrl961\" -> \"cntrl112\"\n\"cntrl962\" -> \"cntrl802\"\n\"cntrl971\" -> \"cntrl1876\"\n\"cntrl972\" -> \"cntrl971\"\n\"cntrl973\" -> \"cntrl975\"\n\"cntrl975\" -> \"cntrl802\"\n\"cntrl976\" -> \"cntrl1878\"\n\"cntrl977\" -> \"cntrl976\"\n\"cntrl978\" -> \"cntrl980\"\n\"cntrl980\" -> \"cntrl973\"\n\"cntrl981\" -> \"cntrl1880\"\n\"cntrl982\" -> \"cntrl981\"\n\"cntrl983\" -> \"cntrl991\"\n\"cntrl983\" -> \"cntrl1731\"\n\"cntrl984\" -> \"cntrl983\"\n\"cntrl987\" -> \"cntrl1882\"\n\"cntrl988\" -> \"cntrl987\"\n\"cntrl989\" -> \"cntrl1741\"\n\"cntrl990\" -> \"cntrl989\"\n\"cntrl991\" -> \"cntrl989\"\n\"cntrl993\" -> \"cntrl1884\"\n\"cntrl994\" -> \"cntrl993\"\n\"cntrl995\" -> \"cntrl997\"\n\"cntrl997\" -> \"cntrl799\"\n\"cntrl998\" -> \"cntrl1886\"\n\"cntrl999\" -> \"cntrl998\"\n\"cntrl1000\" -> \"cntrl1002\"\n\"cntrl1001\" -> \"cntrl1000\"\n\"cntrl1002\" -> \"cntrl995\"\n\"cntrl1003\" -> \"cntrl1888\"\n\"cntrl1004\" -> \"cntrl1003\"\n\"cntrl1005\" -> \"cntrl1007\"\n\"cntrl1007\" -> \"cntrl800\"\n\"cntrl1008\" -> \"cntrl1890\"\n\"cntrl1009\" -> \"cntrl1008\"\n\"cntrl1010\" -> \"cntrl1012\"\n\"cntrl1011\" -> \"cntrl1010\"\n\"cntrl1012\" -> \"cntrl1005\"\n\"cntrl1013\" -> \"cntrl1892\"\n\"cntrl1014\" -> \"cntrl1013\"\n\"cntrl1015\" -> \"cntrl1017\"\n\"cntrl1017\" -> \"cntrl801\"\n\"cntrl1018\" -> \"cntrl1894\"\n\"cntrl1019\" -> \"cntrl1018\"\n\"cntrl1020\" -> \"cntrl1022\"\n\"cntrl1021\" -> \"cntrl1020\"\n\"cntrl1022\" -> \"cntrl1015\"\n\"cntrl1023\" -> \"cntrl1896\"\n\"cntrl1025\" -> \"cntrl1031\"\n\"cntrl1028\" -> \"cntrl1898\"\n\"cntrl1030\" -> \"cntrl1032\"\n\"cntrl1031\" -> \"cntrl1030\"\n\"cntrl1032\" -> \"cntrl693\"\n\"cntrl1033\" -> \"cntrl1900\"\n\"cntrl1035\" -> \"cntrl1902\"\n\"cntrl1037\" -> \"cntrl1904\"\n\"cntrl1039\" -> \"cntrl1906\"\n\"cntrl1041\" -> \"cntrl1908\"\n\"cntrl1043\" -> \"cntrl1910\"\n\"cntrl1045\" -> \"cntrl1062\"\n\"cntrl1047\" -> \"cntrl1065\"\n\"cntrl1048\" -> \"cntrl1068\"\n\"cntrl1048\" -> \"cntrl1120\"\n\"cntrl1051\" -> \"cntrl1053\"\n\"cntrl1052\" -> \"cntrl1051\"\n\"cntrl1053\" -> \"cntrl1045\"\n\"cntrl1056\" -> \"cntrl1061\"\n\"cntrl1057\" -> \"cntrl1060\"\n\"cntrl1058\" -> \"cntrl1059\"\n\"cntrl1059\" -> \"cntrl1047\"\n\"cntrl1060\" -> \"cntrl1058\"\n\"cntrl1061\" -> \"cntrl1057\"\n\"cntrl1062\" -> \"cntrl1056\"\n\"cntrl1063\" -> \"cntrl1064\"\n\"cntrl1064\" -> \"cntrl1048\"\n\"cntrl1065\" -> \"cntrl1063\"\n\"cntrl1066\" -> \"cntrl1067\"\n\"cntrl1067\" -> \"cntrl217\"\n\"cntrl1068\" -> \"cntrl1066\"\n\"cntrl1069\" -> \"cntrl1081\"\n\"cntrl1070\" -> \"cntrl1088\"\n\"cntrl1071\" -> \"cntrl1091\"\n\"cntrl1071\" -> \"cntrl1098\"\n\"cntrl1074\" -> \"cntrl1076\"\n\"cntrl1074\" -> \"cntrl1077\"\n\"cntrl1075\" -> \"cntrl1074\"\n\"cntrl1076\" -> \"cntrl313\"\n\"cntrl1077\" -> \"cntrl1069\"\n\"cntrl1079\" -> \"cntrl1080\"\n\"cntrl1080\" -> \"cntrl1070\"\n\"cntrl1081\" -> \"cntrl1079\"\n\"cntrl1082\" -> \"cntrl1087\"\n\"cntrl1083\" -> \"cntrl1086\"\n\"cntrl1084\" -> \"cntrl1085\"\n\"cntrl1085\" -> \"cntrl1071\"\n\"cntrl1086\" -> \"cntrl1084\"\n\"cntrl1087\" -> \"cntrl1083\"\n\"cntrl1088\" -> \"cntrl1082\"\n\"cntrl1089\" -> \"cntrl1090\"\n\"cntrl1090\" -> \"cntrl690\"\n\"cntrl1091\" -> \"cntrl1089\"\n\"cntrl1092\" -> \"cntrl1107\"\n\"cntrl1094\" -> \"cntrl1110\"\n\"cntrl1095\" -> \"cntrl1113\"\n\"cntrl1095\" -> \"cntrl1141\"\n\"cntrl1098\" -> \"cntrl1092\"\n\"cntrl1101\" -> \"cntrl1106\"\n\"cntrl1102\" -> \"cntrl1105\"\n\"cntrl1103\" -> \"cntrl1104\"\n\"cntrl1104\" -> \"cntrl1094\"\n\"cntrl1105\" -> \"cntrl1103\"\n\"cntrl1106\" -> \"cntrl1102\"\n\"cntrl1107\" -> \"cntrl1101\"\n\"cntrl1108\" -> \"cntrl1109\"\n\"cntrl1109\" -> \"cntrl1095\"\n\"cntrl1110\" -> \"cntrl1108\"\n\"cntrl1111\" -> \"cntrl1112\"\n\"cntrl1112\" -> \"cntrl690\"\n\"cntrl1113\" -> \"cntrl1111\"\n\"cntrl1114\" -> \"cntrl1129\"\n\"cntrl1116\" -> \"cntrl1132\"\n\"cntrl1117\" -> \"cntrl1135\"\n\"cntrl1117\" -> \"cntrl1214\"\n\"cntrl1120\" -> \"cntrl1114\"\n\"cntrl1123\" -> \"cntrl1128\"\n\"cntrl1124\" -> \"cntrl1127\"\n\"cntrl1125\" -> \"cntrl1126\"\n\"cntrl1126\" -> \"cntrl1116\"\n\"cntrl1127\" -> \"cntrl1125\"\n\"cntrl1128\" -> \"cntrl1124\"\n\"cntrl1129\" -> \"cntrl1123\"\n\"cntrl1130\" -> \"cntrl1131\"\n\"cntrl1131\" -> \"cntrl1117\"\n\"cntrl1132\" -> \"cntrl1130\"\n\"cntrl1133\" -> \"cntrl1134\"\n\"cntrl1134\" -> \"cntrl217\"\n\"cntrl1135\" -> \"cntrl1133\"\n\"cntrl1136\" -> \"cntrl1145\"\n\"cntrl1137\" -> \"cntrl1152\"\n\"cntrl1138\" -> \"cntrl1155\"\n\"cntrl1138\" -> \"cntrl1162\"\n\"cntrl1141\" -> \"cntrl1136\"\n\"cntrl1143\" -> \"cntrl1144\"\n\"cntrl1144\" -> \"cntrl1137\"\n\"cntrl1145\" -> \"cntrl1143\"\n\"cntrl1146\" -> \"cntrl1151\"\n\"cntrl1147\" -> \"cntrl1150\"\n\"cntrl1148\" -> \"cntrl1149\"\n\"cntrl1149\" -> \"cntrl1138\"\n\"cntrl1150\" -> \"cntrl1148\"\n\"cntrl1151\" -> \"cntrl1147\"\n\"cntrl1152\" -> \"cntrl1146\"\n\"cntrl1153\" -> \"cntrl1154\"\n\"cntrl1154\" -> \"cntrl690\"\n\"cntrl1155\" -> \"cntrl1153\"\n\"cntrl1156\" -> \"cntrl1171\"\n\"cntrl1158\" -> \"cntrl1174\"\n\"cntrl1159\" -> \"cntrl1177\"\n\"cntrl1162\" -> \"cntrl1156\"\n\"cntrl1165\" -> \"cntrl1170\"\n\"cntrl1166\" -> \"cntrl1169\"\n\"cntrl1167\" -> \"cntrl1168\"\n\"cntrl1168\" -> \"cntrl1158\"\n\"cntrl1169\" -> \"cntrl1167\"\n\"cntrl1170\" -> \"cntrl1166\"\n\"cntrl1171\" -> \"cntrl1165\"\n\"cntrl1172\" -> \"cntrl1173\"\n\"cntrl1173\" -> \"cntrl1159\"\n\"cntrl1174\" -> \"cntrl1172\"\n\"cntrl1175\" -> \"cntrl1176\"\n\"cntrl1176\" -> \"cntrl690\"\n\"cntrl1177\" -> \"cntrl1175\"\n\"cntrl1178\" -> \"cntrl1192\"\n\"cntrl1179\" -> \"cntrl1195\"\n\"cntrl1181\" -> \"cntrl1183\"\n\"cntrl1181\" -> \"cntrl1184\"\n\"cntrl1182\" -> \"cntrl1181\"\n\"cntrl1183\" -> \"cntrl191\"\n\"cntrl1184\" -> \"cntrl1178\"\n\"cntrl1186\" -> \"cntrl1912\"\n\"cntrl1187\" -> \"cntrl1190\"\n\"cntrl1188\" -> \"cntrl2008\"\n\"cntrl1190\" -> \"cntrl1188\"\n\"cntrl1192\" -> \"cntrl1186\"\n\"cntrl1193\" -> \"cntrl1194\"\n\"cntrl1194\" -> \"cntrl190\"\n\"cntrl1195\" -> \"cntrl1193\"\n\"cntrl1196\" -> \"cntrl1207\"\n\"cntrl1197\" -> \"cntrl1210\"\n\"cntrl1197\" -> \"cntrl1253\"\n\"cntrl1199\" -> \"cntrl1201\"\n\"cntrl1200\" -> \"cntrl1199\"\n\"cntrl1201\" -> \"cntrl1196\"\n\"cntrl1203\" -> \"cntrl1206\"\n\"cntrl1204\" -> \"cntrl1205\"\n\"cntrl1205\" -> \"cntrl1197\"\n\"cntrl1206\" -> \"cntrl1204\"\n\"cntrl1207\" -> \"cntrl1203\"\n\"cntrl1208\" -> \"cntrl1209\"\n\"cntrl1209\" -> \"cntrl39\"\n\"cntrl1210\" -> \"cntrl1208\"\n\"cntrl1211\" -> \"cntrl1220\"\n\"cntrl1212\" -> \"cntrl1223\"\n\"cntrl1212\" -> \"cntrl1266\"\n\"cntrl1214\" -> \"cntrl1211\"\n\"cntrl1216\" -> \"cntrl1219\"\n\"cntrl1217\" -> \"cntrl1218\"\n\"cntrl1218\" -> \"cntrl1212\"\n\"cntrl1219\" -> \"cntrl1217\"\n\"cntrl1220\" -> \"cntrl1216\"\n\"cntrl1221\" -> \"cntrl1222\"\n\"cntrl1222\" -> \"cntrl217\"\n\"cntrl1223\" -> \"cntrl1221\"\n\"cntrl1224\" -> \"cntrl1235\"\n\"cntrl1225\" -> \"cntrl1238\"\n\"cntrl1227\" -> \"cntrl1229\"\n\"cntrl1228\" -> \"cntrl1227\"\n\"cntrl1229\" -> \"cntrl1224\"\n\"cntrl1231\" -> \"cntrl1234\"\n\"cntrl1232\" -> \"cntrl1233\"\n\"cntrl1233\" -> \"cntrl1225\"\n\"cntrl1234\" -> \"cntrl1232\"\n\"cntrl1235\" -> \"cntrl1231\"\n\"cntrl1236\" -> \"cntrl1237\"\n\"cntrl1237\" -> \"cntrl1028\"\n\"cntrl1238\" -> \"cntrl1236\"\n\"cntrl1239\" -> \"cntrl1247\"\n\"cntrl1240\" -> \"cntrl1249\"\n\"cntrl1242\" -> \"cntrl1239\"\n\"cntrl1243\" -> \"cntrl1914\"\n\"cntrl1244\" -> \"cntrl1245\"\n\"cntrl1245\" -> \"cntrl1240\"\n\"cntrl1247\" -> \"cntrl1243\"\n\"cntrl1248\" -> \"cntrl1584\"\n\"cntrl1248\" -> \"cntrl1585\"\n\"cntrl1249\" -> \"cntrl1248\"\n\"cntrl1250\" -> \"cntrl1259\"\n\"cntrl1251\" -> \"cntrl1262\"\n\"cntrl1251\" -> \"cntrl1339\"\n\"cntrl1253\" -> \"cntrl1250\"\n\"cntrl1255\" -> \"cntrl1258\"\n\"cntrl1256\" -> \"cntrl1257\"\n\"cntrl1257\" -> \"cntrl1251\"\n\"cntrl1258\" -> \"cntrl1256\"\n\"cntrl1259\" -> \"cntrl1255\"\n\"cntrl1260\" -> \"cntrl1261\"\n\"cntrl1261\" -> \"cntrl39\"\n\"cntrl1262\" -> \"cntrl1260\"\n\"cntrl1263\" -> \"cntrl1272\"\n\"cntrl1264\" -> \"cntrl1275\"\n\"cntrl1266\" -> \"cntrl1263\"\n\"cntrl1268\" -> \"cntrl1271\"\n\"cntrl1269\" -> \"cntrl1270\"\n\"cntrl1270\" -> \"cntrl1264\"\n\"cntrl1271\" -> \"cntrl1269\"\n\"cntrl1272\" -> \"cntrl1268\"\n\"cntrl1273\" -> \"cntrl1274\"\n\"cntrl1274\" -> \"cntrl217\"\n\"cntrl1275\" -> \"cntrl1273\"\n\"cntrl1276\" -> \"cntrl1287\"\n\"cntrl1277\" -> \"cntrl1290\"\n\"cntrl1279\" -> \"cntrl1281\"\n\"cntrl1280\" -> \"cntrl1279\"\n\"cntrl1281\" -> \"cntrl1276\"\n\"cntrl1283\" -> \"cntrl1286\"\n\"cntrl1284\" -> \"cntrl1285\"\n\"cntrl1285\" -> \"cntrl1277\"\n\"cntrl1286\" -> \"cntrl1284\"\n\"cntrl1287\" -> \"cntrl1283\"\n\"cntrl1288\" -> \"cntrl1289\"\n\"cntrl1289\" -> \"cntrl1023\"\n\"cntrl1290\" -> \"cntrl1288\"\n\"cntrl1291\" -> \"cntrl1299\"\n\"cntrl1292\" -> \"cntrl1301\"\n\"cntrl1294\" -> \"cntrl1291\"\n\"cntrl1295\" -> \"cntrl1919\"\n\"cntrl1296\" -> \"cntrl1297\"\n\"cntrl1297\" -> \"cntrl1292\"\n\"cntrl1299\" -> \"cntrl1295\"\n\"cntrl1300\" -> \"cntrl1582\"\n\"cntrl1300\" -> \"cntrl1583\"\n\"cntrl1301\" -> \"cntrl1300\"\n\"cntrl1302\" -> \"cntrl1315\"\n\"cntrl1303\" -> \"cntrl1318\"\n\"cntrl1305\" -> \"cntrl1307\"\n\"cntrl1307\" -> \"cntrl1302\"\n\"cntrl1309\" -> \"cntrl1314\"\n\"cntrl1310\" -> \"cntrl1313\"\n\"cntrl1311\" -> \"cntrl1312\"\n\"cntrl1312\" -> \"cntrl1303\"\n\"cntrl1313\" -> \"cntrl1311\"\n\"cntrl1314\" -> \"cntrl1310\"\n\"cntrl1315\" -> \"cntrl1309\"\n\"cntrl1316\" -> \"cntrl1317\"\n\"cntrl1317\" -> \"cntrl37\"\n\"cntrl1318\" -> \"cntrl1316\"\n\"cntrl1319\" -> \"cntrl1332\"\n\"cntrl1320\" -> \"cntrl1335\"\n\"cntrl1322\" -> \"cntrl1324\"\n\"cntrl1324\" -> \"cntrl1319\"\n\"cntrl1326\" -> \"cntrl1331\"\n\"cntrl1327\" -> \"cntrl1330\"\n\"cntrl1328\" -> \"cntrl1329\"\n\"cntrl1329\" -> \"cntrl1320\"\n\"cntrl1330\" -> \"cntrl1328\"\n\"cntrl1331\" -> \"cntrl1327\"\n\"cntrl1332\" -> \"cntrl1326\"\n\"cntrl1333\" -> \"cntrl1334\"\n\"cntrl1334\" -> \"cntrl189\"\n\"cntrl1335\" -> \"cntrl1333\"\n\"cntrl1336\" -> \"cntrl1345\"\n\"cntrl1337\" -> \"cntrl1348\"\n\"cntrl1337\" -> \"cntrl1378\"\n\"cntrl1339\" -> \"cntrl1336\"\n\"cntrl1341\" -> \"cntrl1344\"\n\"cntrl1342\" -> \"cntrl1343\"\n\"cntrl1343\" -> \"cntrl1337\"\n\"cntrl1344\" -> \"cntrl1342\"\n\"cntrl1345\" -> \"cntrl1341\"\n\"cntrl1346\" -> \"cntrl1347\"\n\"cntrl1347\" -> \"cntrl39\"\n\"cntrl1348\" -> \"cntrl1346\"\n\"cntrl1349\" -> \"cntrl1360\"\n\"cntrl1350\" -> \"cntrl1363\"\n\"cntrl1352\" -> \"cntrl1354\"\n\"cntrl1353\" -> \"cntrl1352\"\n\"cntrl1354\" -> \"cntrl1349\"\n\"cntrl1356\" -> \"cntrl1359\"\n\"cntrl1357\" -> \"cntrl1358\"\n\"cntrl1358\" -> \"cntrl1350\"\n\"cntrl1359\" -> \"cntrl1357\"\n\"cntrl1360\" -> \"cntrl1356\"\n\"cntrl1361\" -> \"cntrl1362\"\n\"cntrl1362\" -> \"cntrl1035\"\n\"cntrl1363\" -> \"cntrl1361\"\n\"cntrl1364\" -> \"cntrl1372\"\n\"cntrl1365\" -> \"cntrl1374\"\n\"cntrl1367\" -> \"cntrl1364\"\n\"cntrl1368\" -> \"cntrl1915\"\n\"cntrl1369\" -> \"cntrl1370\"\n\"cntrl1370\" -> \"cntrl1365\"\n\"cntrl1372\" -> \"cntrl1368\"\n\"cntrl1373\" -> \"cntrl1580\"\n\"cntrl1373\" -> \"cntrl1581\"\n\"cntrl1374\" -> \"cntrl1373\"\n\"cntrl1375\" -> \"cntrl1384\"\n\"cntrl1376\" -> \"cntrl1387\"\n\"cntrl1376\" -> \"cntrl1417\"\n\"cntrl1378\" -> \"cntrl1375\"\n\"cntrl1380\" -> \"cntrl1383\"\n\"cntrl1381\" -> \"cntrl1382\"\n\"cntrl1382\" -> \"cntrl1376\"\n\"cntrl1383\" -> \"cntrl1381\"\n\"cntrl1384\" -> \"cntrl1380\"\n\"cntrl1385\" -> \"cntrl1386\"\n\"cntrl1386\" -> \"cntrl39\"\n\"cntrl1387\" -> \"cntrl1385\"\n\"cntrl1388\" -> \"cntrl1399\"\n\"cntrl1389\" -> \"cntrl1402\"\n\"cntrl1391\" -> \"cntrl1393\"\n\"cntrl1392\" -> \"cntrl1391\"\n\"cntrl1393\" -> \"cntrl1388\"\n\"cntrl1395\" -> \"cntrl1398\"\n\"cntrl1396\" -> \"cntrl1397\"\n\"cntrl1397\" -> \"cntrl1389\"\n\"cntrl1398\" -> \"cntrl1396\"\n\"cntrl1399\" -> \"cntrl1395\"\n\"cntrl1400\" -> \"cntrl1401\"\n\"cntrl1401\" -> \"cntrl1033\"\n\"cntrl1402\" -> \"cntrl1400\"\n\"cntrl1403\" -> \"cntrl1411\"\n\"cntrl1404\" -> \"cntrl1413\"\n\"cntrl1406\" -> \"cntrl1403\"\n\"cntrl1407\" -> \"cntrl1920\"\n\"cntrl1408\" -> \"cntrl1409\"\n\"cntrl1409\" -> \"cntrl1404\"\n\"cntrl1411\" -> \"cntrl1407\"\n\"cntrl1412\" -> \"cntrl1578\"\n\"cntrl1412\" -> \"cntrl1579\"\n\"cntrl1413\" -> \"cntrl1412\"\n\"cntrl1414\" -> \"cntrl1423\"\n\"cntrl1415\" -> \"cntrl1426\"\n\"cntrl1415\" -> \"cntrl1456\"\n\"cntrl1417\" -> \"cntrl1414\"\n\"cntrl1419\" -> \"cntrl1422\"\n\"cntrl1420\" -> \"cntrl1421\"\n\"cntrl1421\" -> \"cntrl1415\"\n\"cntrl1422\" -> \"cntrl1420\"\n\"cntrl1423\" -> \"cntrl1419\"\n\"cntrl1424\" -> \"cntrl1425\"\n\"cntrl1425\" -> \"cntrl39\"\n\"cntrl1426\" -> \"cntrl1424\"\n\"cntrl1427\" -> \"cntrl1438\"\n\"cntrl1428\" -> \"cntrl1441\"\n\"cntrl1430\" -> \"cntrl1432\"\n\"cntrl1431\" -> \"cntrl1430\"\n\"cntrl1432\" -> \"cntrl1427\"\n\"cntrl1434\" -> \"cntrl1437\"\n\"cntrl1435\" -> \"cntrl1436\"\n\"cntrl1436\" -> \"cntrl1428\"\n\"cntrl1437\" -> \"cntrl1435\"\n\"cntrl1438\" -> \"cntrl1434\"\n\"cntrl1439\" -> \"cntrl1440\"\n\"cntrl1440\" -> \"cntrl1039\"\n\"cntrl1441\" -> \"cntrl1439\"\n\"cntrl1442\" -> \"cntrl1450\"\n\"cntrl1443\" -> \"cntrl1452\"\n\"cntrl1445\" -> \"cntrl1442\"\n\"cntrl1446\" -> \"cntrl1916\"\n\"cntrl1447\" -> \"cntrl1448\"\n\"cntrl1448\" -> \"cntrl1443\"\n\"cntrl1450\" -> \"cntrl1446\"\n\"cntrl1451\" -> \"cntrl1576\"\n\"cntrl1451\" -> \"cntrl1577\"\n\"cntrl1452\" -> \"cntrl1451\"\n\"cntrl1453\" -> \"cntrl1462\"\n\"cntrl1454\" -> \"cntrl1465\"\n\"cntrl1454\" -> \"cntrl1495\"\n\"cntrl1456\" -> \"cntrl1453\"\n\"cntrl1458\" -> \"cntrl1461\"\n\"cntrl1459\" -> \"cntrl1460\"\n\"cntrl1460\" -> \"cntrl1454\"\n\"cntrl1461\" -> \"cntrl1459\"\n\"cntrl1462\" -> \"cntrl1458\"\n\"cntrl1463\" -> \"cntrl1464\"\n\"cntrl1464\" -> \"cntrl39\"\n\"cntrl1465\" -> \"cntrl1463\"\n\"cntrl1466\" -> \"cntrl1477\"\n\"cntrl1467\" -> \"cntrl1480\"\n\"cntrl1469\" -> \"cntrl1471\"\n\"cntrl1470\" -> \"cntrl1469\"\n\"cntrl1471\" -> \"cntrl1466\"\n\"cntrl1473\" -> \"cntrl1476\"\n\"cntrl1474\" -> \"cntrl1475\"\n\"cntrl1475\" -> \"cntrl1467\"\n\"cntrl1476\" -> \"cntrl1474\"\n\"cntrl1477\" -> \"cntrl1473\"\n\"cntrl1478\" -> \"cntrl1479\"\n\"cntrl1479\" -> \"cntrl1037\"\n\"cntrl1480\" -> \"cntrl1478\"\n\"cntrl1481\" -> \"cntrl1489\"\n\"cntrl1482\" -> \"cntrl1491\"\n\"cntrl1484\" -> \"cntrl1481\"\n\"cntrl1485\" -> \"cntrl1921\"\n\"cntrl1486\" -> \"cntrl1487\"\n\"cntrl1487\" -> \"cntrl1482\"\n\"cntrl1489\" -> \"cntrl1485\"\n\"cntrl1490\" -> \"cntrl1574\"\n\"cntrl1490\" -> \"cntrl1575\"\n\"cntrl1491\" -> \"cntrl1490\"\n\"cntrl1492\" -> \"cntrl1501\"\n\"cntrl1493\" -> \"cntrl1504\"\n\"cntrl1493\" -> \"cntrl1534\"\n\"cntrl1495\" -> \"cntrl1492\"\n\"cntrl1497\" -> \"cntrl1500\"\n\"cntrl1498\" -> \"cntrl1499\"\n\"cntrl1499\" -> \"cntrl1493\"\n\"cntrl1500\" -> \"cntrl1498\"\n\"cntrl1501\" -> \"cntrl1497\"\n\"cntrl1502\" -> \"cntrl1503\"\n\"cntrl1503\" -> \"cntrl39\"\n\"cntrl1504\" -> \"cntrl1502\"\n\"cntrl1505\" -> \"cntrl1516\"\n\"cntrl1506\" -> \"cntrl1519\"\n\"cntrl1508\" -> \"cntrl1510\"\n\"cntrl1509\" -> \"cntrl1508\"\n\"cntrl1510\" -> \"cntrl1505\"\n\"cntrl1512\" -> \"cntrl1515\"\n\"cntrl1513\" -> \"cntrl1514\"\n\"cntrl1514\" -> \"cntrl1506\"\n\"cntrl1515\" -> \"cntrl1513\"\n\"cntrl1516\" -> \"cntrl1512\"\n\"cntrl1517\" -> \"cntrl1518\"\n\"cntrl1518\" -> \"cntrl1043\"\n\"cntrl1519\" -> \"cntrl1517\"\n\"cntrl1520\" -> \"cntrl1528\"\n\"cntrl1521\" -> \"cntrl1530\"\n\"cntrl1523\" -> \"cntrl1520\"\n\"cntrl1524\" -> \"cntrl1917\"\n\"cntrl1525\" -> \"cntrl1526\"\n\"cntrl1526\" -> \"cntrl1521\"\n\"cntrl1528\" -> \"cntrl1524\"\n\"cntrl1529\" -> \"cntrl1572\"\n\"cntrl1529\" -> \"cntrl1573\"\n\"cntrl1530\" -> \"cntrl1529\"\n\"cntrl1531\" -> \"cntrl1540\"\n\"cntrl1532\" -> \"cntrl1543\"\n\"cntrl1534\" -> \"cntrl1531\"\n\"cntrl1536\" -> \"cntrl1539\"\n\"cntrl1537\" -> \"cntrl1538\"\n\"cntrl1538\" -> \"cntrl1532\"\n\"cntrl1539\" -> \"cntrl1537\"\n\"cntrl1540\" -> \"cntrl1536\"\n\"cntrl1541\" -> \"cntrl1542\"\n\"cntrl1542\" -> \"cntrl39\"\n\"cntrl1543\" -> \"cntrl1541\"\n\"cntrl1544\" -> \"cntrl1555\"\n\"cntrl1545\" -> \"cntrl1558\"\n\"cntrl1547\" -> \"cntrl1549\"\n\"cntrl1548\" -> \"cntrl1547\"\n\"cntrl1549\" -> \"cntrl1544\"\n\"cntrl1551\" -> \"cntrl1554\"\n\"cntrl1552\" -> \"cntrl1553\"\n\"cntrl1553\" -> \"cntrl1545\"\n\"cntrl1554\" -> \"cntrl1552\"\n\"cntrl1555\" -> \"cntrl1551\"\n\"cntrl1556\" -> \"cntrl1557\"\n\"cntrl1557\" -> \"cntrl1041\"\n\"cntrl1558\" -> \"cntrl1556\"\n\"cntrl1559\" -> \"cntrl1567\"\n\"cntrl1560\" -> \"cntrl1569\"\n\"cntrl1562\" -> \"cntrl1559\"\n\"cntrl1563\" -> \"cntrl1922\"\n\"cntrl1564\" -> \"cntrl1565\"\n\"cntrl1565\" -> \"cntrl1560\"\n\"cntrl1567\" -> \"cntrl1563\"\n\"cntrl1568\" -> \"cntrl1570\"\n\"cntrl1568\" -> \"cntrl1571\"\n\"cntrl1569\" -> \"cntrl1568\"\n\"cntrl1570\" -> \"cntrl24\"\n\"cntrl1571\" -> \"cntrl2\"\n\"cntrl1572\" -> \"cntrl24\"\n\"cntrl1573\" -> \"cntrl2\"\n\"cntrl1574\" -> \"cntrl24\"\n\"cntrl1575\" -> \"cntrl2\"\n\"cntrl1576\" -> \"cntrl24\"\n\"cntrl1577\" -> \"cntrl2\"\n\"cntrl1578\" -> \"cntrl24\"\n\"cntrl1579\" -> \"cntrl2\"\n\"cntrl1580\" -> \"cntrl24\"\n\"cntrl1581\" -> \"cntrl2\"\n\"cntrl1582\" -> \"cntrl24\"\n\"cntrl1583\" -> \"cntrl2\"\n\"cntrl1584\" -> \"cntrl24\"\n\"cntrl1585\" -> \"cntrl2\"\n\"cntrl1586\" -> \"cntrl41\"\n\"cntrl1595\" -> \"cntrl219\"\n\"cntrl1629\" -> \"cntrl66\"\n\"cntrl1630\" -> \"cntrl75\"\n\"cntrl1631\" -> \"cntrl84\"\n\"cntrl1632\" -> \"cntrl93\"\n\"cntrl1633\" -> \"cntrl102\"\n\"cntrl1634\" -> \"cntrl111\"\n\"cntrl1635\" -> \"cntrl120\"\n\"cntrl1660\" -> \"cntrl332\"\n\"cntrl1668\" -> \"cntrl330\"\n\"cntrl1670\" -> \"cntrl340\"\n\"cntrl1672\" -> \"cntrl350\"\n\"cntrl1674\" -> \"cntrl360\"\n\"cntrl1723\" -> \"cntrl1725\"\n\"cntrl1724\" -> \"cntrl1723\"\n\"cntrl1725\" -> \"cntrl599\"\n\"cntrl1726\" -> \"cntrl1728\"\n\"cntrl1727\" -> \"cntrl1726\"\n\"cntrl1728\" -> \"cntrl318\"\n\"cntrl1729\" -> \"cntrl1732\"\n\"cntrl1730\" -> \"cntrl1729\"\n\"cntrl1731\" -> \"cntrl1729\"\n\"cntrl1732\" -> \"cntrl224\"\n\"cntrl1733\" -> \"cntrl1735\"\n\"cntrl1734\" -> \"cntrl1733\"\n\"cntrl1735\" -> \"cntrl604\"\n\"cntrl1736\" -> \"cntrl1738\"\n\"cntrl1737\" -> \"cntrl1736\"\n\"cntrl1738\" -> \"cntrl323\"\n\"cntrl1739\" -> \"cntrl1742\"\n\"cntrl1740\" -> \"cntrl1739\"\n\"cntrl1741\" -> \"cntrl1739\"\n\"cntrl1742\" -> \"cntrl226\"\n\"cntrl1743\" -> \"cntrl1745\"\n\"cntrl1744\" -> \"cntrl1743\"\n\"cntrl1745\" -> \"cntrl610\"\n\"cntrl1746\" -> \"cntrl1748\"\n\"cntrl1747\" -> \"cntrl1746\"\n\"cntrl1748\" -> \"cntrl615\"\n\"cntrl1749\" -> \"cntrl1751\"\n\"cntrl1750\" -> \"cntrl1749\"\n\"cntrl1751\" -> \"cntrl624\"\n\"cntrl1752\" -> \"cntrl1754\"\n\"cntrl1753\" -> \"cntrl1752\"\n\"cntrl1754\" -> \"cntrl629\"\n\"cntrl1755\" -> \"cntrl1757\"\n\"cntrl1757\" -> \"cntrl638\"\n\"cntrl1758\" -> \"cntrl1760\"\n\"cntrl1759\" -> \"cntrl1758\"\n\"cntrl1760\" -> \"cntrl643\"\n\"cntrl1761\" -> \"cntrl1923\"\n\"cntrl1762\" -> \"cntrl1761\"\n\"cntrl1764\" -> \"cntrl1763\"\n\"cntrl1765\" -> \"cntrl1768\"\n\"cntrl1766\" -> \"cntrl1765\"\n\"cntrl1768\" -> \"cntrl1767\"\n\"cntrl1770\" -> \"cntrl1769\"\n\"cntrl1771\" -> \"cntrl1924\"\n\"cntrl1772\" -> \"cntrl1771\"\n\"cntrl1773\" -> \"cntrl1925\"\n\"cntrl1774\" -> \"cntrl1773\"\n\"cntrl1776\" -> \"cntrl1775\"\n\"cntrl1778\" -> \"cntrl1777\"\n\"cntrl1779\" -> \"cntrl1926\"\n\"cntrl1780\" -> \"cntrl1779\"\n\"cntrl1782\" -> \"cntrl1781\"\n\"cntrl1783\" -> \"cntrl1927\"\n\"cntrl1784\" -> \"cntrl1783\"\n\"cntrl1785\" -> \"cntrl1928\"\n\"cntrl1786\" -> \"cntrl1785\"\n\"cntrl1787\" -> \"cntrl1929\"\n\"cntrl1788\" -> \"cntrl1787\"\n\"cntrl1789\" -> \"cntrl1930\"\n\"cntrl1790\" -> \"cntrl1789\"\n\"cntrl1791\" -> \"cntrl1931\"\n\"cntrl1792\" -> \"cntrl1791\"\n\"cntrl1793\" -> \"cntrl1932\"\n\"cntrl1794\" -> \"cntrl1793\"\n\"cntrl1795\" -> \"cntrl1933\"\n\"cntrl1796\" -> \"cntrl1795\"\n\"cntrl1798\" -> \"cntrl1797\"\n\"cntrl1799\" -> \"cntrl1802\"\n\"cntrl1800\" -> \"cntrl1799\"\n\"cntrl1802\" -> \"cntrl1801\"\n\"cntrl1803\" -> \"cntrl1934\"\n\"cntrl1803\" -> \"cntrl1935\"\n\"cntrl1804\" -> \"cntrl1803\"\n\"cntrl1805\" -> \"cntrl1936\"\n\"cntrl1805\" -> \"cntrl1937\"\n\"cntrl1806\" -> \"cntrl1805\"\n\"cntrl1807\" -> \"cntrl1938\"\n\"cntrl1807\" -> \"cntrl1939\"\n\"cntrl1808\" -> \"cntrl1807\"\n\"cntrl1809\" -> \"cntrl1940\"\n\"cntrl1809\" -> \"cntrl1941\"\n\"cntrl1810\" -> \"cntrl1809\"\n\"cntrl1811\" -> \"cntrl1942\"\n\"cntrl1811\" -> \"cntrl1943\"\n\"cntrl1812\" -> \"cntrl1811\"\n\"cntrl1813\" -> \"cntrl1944\"\n\"cntrl1814\" -> \"cntrl1813\"\n\"cntrl1815\" -> \"cntrl1945\"\n\"cntrl1816\" -> \"cntrl1815\"\n\"cntrl1817\" -> \"cntrl1946\"\n\"cntrl1818\" -> \"cntrl1817\"\n\"cntrl1819\" -> \"cntrl1947\"\n\"cntrl1820\" -> \"cntrl1819\"\n\"cntrl1821\" -> \"cntrl1948\"\n\"cntrl1822\" -> \"cntrl1821\"\n\"cntrl1823\" -> \"cntrl1949\"\n\"cntrl1823\" -> \"cntrl1950\"\n\"cntrl1824\" -> \"cntrl1823\"\n\"cntrl1825\" -> \"cntrl1951\"\n\"cntrl1825\" -> \"cntrl1952\"\n\"cntrl1826\" -> \"cntrl1825\"\n\"cntrl1827\" -> \"cntrl1953\"\n\"cntrl1827\" -> \"cntrl1954\"\n\"cntrl1828\" -> \"cntrl1827\"\n\"cntrl1829\" -> \"cntrl1955\"\n\"cntrl1829\" -> \"cntrl1956\"\n\"cntrl1830\" -> \"cntrl1829\"\n\"cntrl1831\" -> \"cntrl1957\"\n\"cntrl1831\" -> \"cntrl1958\"\n\"cntrl1832\" -> \"cntrl1831\"\n\"cntrl1833\" -> \"cntrl1959\"\n\"cntrl1834\" -> \"cntrl1833\"\n\"cntrl1835\" -> \"cntrl1960\"\n\"cntrl1836\" -> \"cntrl1835\"\n\"cntrl1837\" -> \"cntrl1961\"\n\"cntrl1838\" -> \"cntrl1837\"\n\"cntrl1839\" -> \"cntrl1962\"\n\"cntrl1840\" -> \"cntrl1839\"\n\"cntrl1841\" -> \"cntrl1963\"\n\"cntrl1842\" -> \"cntrl1841\"\n\"cntrl1843\" -> \"cntrl1964\"\n\"cntrl1843\" -> \"cntrl1965\"\n\"cntrl1844\" -> \"cntrl1843\"\n\"cntrl1845\" -> \"cntrl1966\"\n\"cntrl1845\" -> \"cntrl1967\"\n\"cntrl1846\" -> \"cntrl1845\"\n\"cntrl1847\" -> \"cntrl1968\"\n\"cntrl1847\" -> \"cntrl1969\"\n\"cntrl1848\" -> \"cntrl1847\"\n\"cntrl1849\" -> \"cntrl1970\"\n\"cntrl1849\" -> \"cntrl1971\"\n\"cntrl1850\" -> \"cntrl1849\"\n\"cntrl1851\" -> \"cntrl1972\"\n\"cntrl1851\" -> \"cntrl1973\"\n\"cntrl1852\" -> \"cntrl1851\"\n\"cntrl1853\" -> \"cntrl1974\"\n\"cntrl1854\" -> \"cntrl1853\"\n\"cntrl1855\" -> \"cntrl1975\"\n\"cntrl1856\" -> \"cntrl1855\"\n\"cntrl1857\" -> \"cntrl1976\"\n\"cntrl1858\" -> \"cntrl1857\"\n\"cntrl1859\" -> \"cntrl1977\"\n\"cntrl1860\" -> \"cntrl1859\"\n\"cntrl1861\" -> \"cntrl1978\"\n\"cntrl1862\" -> \"cntrl1861\"\n\"cntrl1863\" -> \"cntrl1979\"\n\"cntrl1863\" -> \"cntrl1980\"\n\"cntrl1864\" -> \"cntrl1863\"\n\"cntrl1865\" -> \"cntrl1981\"\n\"cntrl1865\" -> \"cntrl1982\"\n\"cntrl1866\" -> \"cntrl1865\"\n\"cntrl1867\" -> \"cntrl1983\"\n\"cntrl1868\" -> \"cntrl1867\"\n\"cntrl1870\" -> \"cntrl1869\"\n\"cntrl1871\" -> \"cntrl1984\"\n\"cntrl1872\" -> \"cntrl1871\"\n\"cntrl1873\" -> \"cntrl1985\"\n\"cntrl1874\" -> \"cntrl1873\"\n\"cntrl1876\" -> \"cntrl1875\"\n\"cntrl1878\" -> \"cntrl1877\"\n\"cntrl1879\" -> \"cntrl1986\"\n\"cntrl1880\" -> \"cntrl1879\"\n\"cntrl1881\" -> \"cntrl1987\"\n\"cntrl1882\" -> \"cntrl1881\"\n\"cntrl1884\" -> \"cntrl1883\"\n\"cntrl1886\" -> \"cntrl1885\"\n\"cntrl1888\" -> \"cntrl1887\"\n\"cntrl1890\" -> \"cntrl1889\"\n\"cntrl1892\" -> \"cntrl1891\"\n\"cntrl1894\" -> \"cntrl1893\"\n\"cntrl1896\" -> \"cntrl1895\"\n\"cntrl1898\" -> \"cntrl1897\"\n\"cntrl1900\" -> \"cntrl1899\"\n\"cntrl1902\" -> \"cntrl1901\"\n\"cntrl1904\" -> \"cntrl1903\"\n\"cntrl1906\" -> \"cntrl1905\"\n\"cntrl1908\" -> \"cntrl1907\"\n\"cntrl1910\" -> \"cntrl1909\"\n\"cntrl1911\" -> \"cntrl1988\"\n\"cntrl1912\" -> \"cntrl1911\"\n\"cntrl1913\" -> \"cntrl1989\"\n\"cntrl1913\" -> \"cntrl1990\"\n\"cntrl1913\" -> \"cntrl1991\"\n\"cntrl1913\" -> \"cntrl1992\"\n\"cntrl1914\" -> \"cntrl1913\"\n\"cntrl1915\" -> \"cntrl1913\"\n\"cntrl1916\" -> \"cntrl1913\"\n\"cntrl1917\" -> \"cntrl1913\"\n\"cntrl1918\" -> \"cntrl1993\"\n\"cntrl1918\" -> \"cntrl1994\"\n\"cntrl1918\" -> \"cntrl1995\"\n\"cntrl1918\" -> \"cntrl1996\"\n\"cntrl1919\" -> \"cntrl1918\"\n\"cntrl1920\" -> \"cntrl1918\"\n\"cntrl1921\" -> \"cntrl1918\"\n\"cntrl1922\" -> \"cntrl1918\"\n\"cntrl1923\" -> \"cntrl1305\"\n\"cntrl1924\" -> \"cntrl188\"\n\"cntrl1925\" -> \"cntrl1322\"\n\"cntrl1926\" -> \"cntrl187\"\n\"cntrl1927\" -> \"cntrl229\"\n\"cntrl1928\" -> \"cntrl234\"\n\"cntrl1929\" -> \"cntrl239\"\n\"cntrl1930\" -> \"cntrl244\"\n\"cntrl1931\" -> \"cntrl249\"\n\"cntrl1932\" -> \"cntrl254\"\n\"cntrl1933\" -> \"cntrl259\"\n\"cntrl1934\" -> \"cntrl339\"\n\"cntrl1935\" -> \"cntrl422\"\n\"cntrl1936\" -> \"cntrl344\"\n\"cntrl1937\" -> \"cntrl420\"\n\"cntrl1938\" -> \"cntrl349\"\n\"cntrl1939\" -> \"cntrl430\"\n\"cntrl1940\" -> \"cntrl354\"\n\"cntrl1941\" -> \"cntrl440\"\n\"cntrl1942\" -> \"cntrl359\"\n\"cntrl1943\" -> \"cntrl450\"\n\"cntrl1944\" -> \"cntrl364\"\n\"cntrl1945\" -> \"cntrl369\"\n\"cntrl1946\" -> \"cntrl799\"\n\"cntrl1947\" -> \"cntrl330\"\n\"cntrl1948\" -> \"cntrl800\"\n\"cntrl1949\" -> \"cntrl429\"\n\"cntrl1950\" -> \"cntrl512\"\n\"cntrl1951\" -> \"cntrl434\"\n\"cntrl1952\" -> \"cntrl510\"\n\"cntrl1953\" -> \"cntrl439\"\n\"cntrl1954\" -> \"cntrl520\"\n\"cntrl1955\" -> \"cntrl444\"\n\"cntrl1956\" -> \"cntrl530\"\n\"cntrl1957\" -> \"cntrl449\"\n\"cntrl1958\" -> \"cntrl540\"\n\"cntrl1959\" -> \"cntrl454\"\n\"cntrl1960\" -> \"cntrl459\"\n\"cntrl1961\" -> \"cntrl800\"\n\"cntrl1962\" -> \"cntrl420\"\n\"cntrl1963\" -> \"cntrl801\"\n\"cntrl1964\" -> \"cntrl519\"\n\"cntrl1965\" -> \"cntrl52\"\n\"cntrl1966\" -> \"cntrl524\"\n\"cntrl1967\" -> \"cntrl47\"\n\"cntrl1968\" -> \"cntrl529\"\n\"cntrl1969\" -> \"cntrl67\"\n\"cntrl1970\" -> \"cntrl534\"\n\"cntrl1971\" -> \"cntrl85\"\n\"cntrl1972\" -> \"cntrl539\"\n\"cntrl1973\" -> \"cntrl103\"\n\"cntrl1974\" -> \"cntrl544\"\n\"cntrl1975\" -> \"cntrl549\"\n\"cntrl1976\" -> \"cntrl801\"\n\"cntrl1977\" -> \"cntrl510\"\n\"cntrl1978\" -> \"cntrl802\"\n\"cntrl1979\" -> \"cntrl978\"\n\"cntrl1980\" -> \"cntrl1093\"\n\"cntrl1981\" -> \"cntrl1157\"\n\"cntrl1982\" -> \"cntrl1755\"\n\"cntrl1983\" -> \"cntrl177\"\n\"cntrl1984\" -> \"cntrl717\"\n\"cntrl1985\" -> \"cntrl1025\"\n\"cntrl1986\" -> \"cntrl1046\"\n\"cntrl1987\" -> \"cntrl1115\"\n\"cntrl1988\" -> \"cntrl1187\"\n\"cntrl1989\" -> \"cntrl1244\"\n\"cntrl1990\" -> \"cntrl1369\"\n\"cntrl1991\" -> \"cntrl1447\"\n\"cntrl1992\" -> \"cntrl1525\"\n\"cntrl1993\" -> \"cntrl1296\"\n\"cntrl1994\" -> \"cntrl1408\"\n\"cntrl1995\" -> \"cntrl1486\"\n\"cntrl1996\" -> \"cntrl1564\"\n\"cntrl1997\" -> \"cntrl2009\"\n\"cntrl1998\" -> \"cntrl1997\"\n\"cntrl1999\" -> \"cntrl2010\"\n\"cntrl2000\" -> \"cntrl1999\"\n\"cntrl2004\" -> \"cntrl2003\"\n\"cntrl2007\" -> \"cntrl2011\"\n\"cntrl2008\" -> \"cntrl2007\"\n\"cntrl2009\" -> \"cntrl670\"\n\"cntrl2010\" -> \"cntrl670\"\n\"cntrl2011\" -> \"cntrl1179\"\n}\n}\n" + .command: + sync: false + operations: + - type: Tensor + tag: 0 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 0 + - 1 + - type: T_Load_Tiled + tag: 1 + tensorTag: -1 + - type: Tensor + tag: 2 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Load_Tiled + tag: 3 + tensorTag: -1 + - type: Tensor + tag: 4 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Load_Tiled + tag: 5 + tensorTag: -1 + - type: Scalar + tag: 6 + variableType: {dataType: Float, pointerType: Value} + pointer: {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - type: T_Load_Scalar + tag: 7 + scalarTag: -1 + - type: Scalar + tag: 8 + variableType: {dataType: Float, pointerType: Value} + pointer: {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - type: T_Load_Scalar + tag: 9 + scalarTag: -1 + - type: T_Mul + tag: 10 + a: 1 + b: 3 + - type: T_Execute + tag: 14 + xops: + - type: E_Mul + dest: 11 + a: 9 + b: 5 + - type: E_Mul + dest: 12 + a: 7 + b: 10 + - type: E_Add + dest: 13 + a: 11 + b: 12 + nextTag: 14 + inputs: [7, 10, 9, 5] + outputs: [13, 12, 11] + - type: Tensor + tag: 15 + variableType: {dataType: Half, pointerType: Value} + numDims: 2 + sizes: + - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + pointer: {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + extent: {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + strides: + - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + literalStrides: + - 1 + - type: T_Execute + tag: 17 + xops: + - type: E_Cvt + dest: 16 + a: 13 + nextTag: 17 + inputs: [13] + outputs: [16] + - type: T_Store_Tiled + tag: 18 + srcTag: 16 + dstTag: 15 + argOffsetMap: + 15 Stride 1: 192 + 15 Stride 0: 184 + 15 Size 1: 176 + 15 Size 0: 168 + 15 Limit -1: 160 + 8 Value -1: 148 + 4 Stride 0: 128 + 6 Value -1: 144 + 4 Limit -1: 104 + 0 Value -1: 0 + 0 Limit -1: 8 + 2 Value -1: 48 + 0 Size 0: 16 + 4 Size 1: 120 + 0 Size 1: 24 + 2 Size 1: 72 + 15 Value -1: 152 + 2 Stride 0: 80 + 4 Stride 1: 136 + 0 Stride 0: 32 + 0 Stride 1: 40 + 4 Size 0: 112 + 2 Limit -1: 56 + 2 Stride 1: 88 + 2 Size 0: 64 + 4 Value -1: 96 + commandArgs: + - {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} + - {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} + - {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} + nextTag: 19 + runtimeArgsOffset: 200 +... + +.end_amdgpu_metadata + diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s deleted file mode 100644 index 465d85556eb6..000000000000 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_gfx942.s +++ /dev/null @@ -1,20177 +0,0 @@ - // Tensor.Half.d2 0, (base=&0, lim=&8, sizes={&16 &24 }, strides={&32 &40 }) - // T_LOAD_TILED 1 Source 0 - // Tensor.Half.d2 2, (base=&48, lim=&56, sizes={&64 &72 }, strides={&80 &88 }) - // T_LOAD_TILED 3 Source 2 - // Tensor.Half.d2 4, (base=&96, lim=&104, sizes={&112 &120 }, strides={&128 &136 }) - // T_LOAD_TILED 5 Source 4 - // Scalar.Float.6 - // T_LOAD_SCALAR 7Source 6 - // Scalar.Float.8 - // T_LOAD_SCALAR 9Source 8 - // T_Mul 1 3 Value: Float - // T_EXECUTE 7 10 9 5 - // E_Mul 11, 9, 5 - // E_Mul 12, 7, 10 - // E_Add 13, 11, 12 - // Tensor.Half.d2 15, (base=&152, lim=&160, sizes={&168 &176 }, strides={&184 &192 }) - // T_EXECUTE 13 - // E_Cvt 16, 13 - // T_STORE_TILED 18 Source 16 Dest 15 - - // Tensor_0_pointer: PointerGlobal: Half(offset: 0, size: 8, read_write) - // Tensor_0_extent: Value: Int64(offset: 8, size: 8, read_only) - // Tensor_0_size_0: Value: Int64(offset: 16, size: 8, read_only) - // Tensor_0_size_1: Value: Int64(offset: 24, size: 8, read_only) - // Tensor_0_stride_0: Value: Int64(offset: 32, size: 8, read_only) - // Tensor_0_stride_1: Value: Int64(offset: 40, size: 8, read_only) - // Tensor_2_pointer: PointerGlobal: Half(offset: 48, size: 8, read_write) - // Tensor_2_extent: Value: Int64(offset: 56, size: 8, read_only) - // Tensor_2_size_0: Value: Int64(offset: 64, size: 8, read_only) - // Tensor_2_size_1: Value: Int64(offset: 72, size: 8, read_only) - // Tensor_2_stride_0: Value: Int64(offset: 80, size: 8, read_only) - // Tensor_2_stride_1: Value: Int64(offset: 88, size: 8, read_only) - // Tensor_4_pointer: PointerGlobal: Half(offset: 96, size: 8, read_write) - // Tensor_4_extent: Value: Int64(offset: 104, size: 8, read_only) - // Tensor_4_size_0: Value: Int64(offset: 112, size: 8, read_only) - // Tensor_4_size_1: Value: Int64(offset: 120, size: 8, read_only) - // Tensor_4_stride_0: Value: Int64(offset: 128, size: 8, read_only) - // Tensor_4_stride_1: Value: Int64(offset: 136, size: 8, read_only) - // user_Float_Value_6: Value: Float(offset: 144, size: 4, read_only) - // user_Float_Value_8: Value: Float(offset: 148, size: 4, read_only) - // Tensor_15_pointer: PointerGlobal: Half(offset: 152, size: 8, read_write) - // Tensor_15_extent: Value: Int64(offset: 160, size: 8, read_only) - // Tensor_15_size_0: Value: Int64(offset: 168, size: 8, read_only) - // Tensor_15_size_1: Value: Int64(offset: 176, size: 8, read_only) - // Tensor_15_stride_0: Value: Int64(offset: 184, size: 8, read_only) - // Tensor_15_stride_1: Value: Int64(offset: 192, size: 8, read_only) - -.amdgcn_target "amdgcn-amd-amdhsa--gfx942" -.set .amdgcn.next_free_vgpr, 0 -.set .amdgcn.next_free_sgpr, 0 -.text -.globl RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a -.p2align 8 -.type RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a,@function -// Allocated Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 -// Allocated Workgroup Index X: 1 SGPR (Value: UInt32): s2 -// Allocated Workgroup Index Y: 1 SGPR (Value: UInt32): s3 -// Allocated Packed Workitem Index: 1 VGPR (Value: Raw32): v0 -// Allocated Workitem Index X: 1 VGPR (Value: UInt32): v1 -// Allocated Workitem Index Y: 1 VGPR (Value: UInt32): v2 -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a: - - // Kernel Options: - // dsObserver: DSMEMObserver - // logLevel: Verbose - // alwaysWaitAfterLoad: false - // alwaysWaitAfterStore: false - // alwaysWaitBeforeBranch: false - // alwaysWaitZeroBeforeBarrier: false - // preloadKernelArguments: true - // maxACCVGPRs: 256 - // maxSGPRs: 102 - // maxVGPRs: 256 - // loadLocalWidth: 4 - // loadGlobalWidth: 8 - // storeLocalWidth: 4 - // storeGlobalWidth: 4 - // assertWaitCntState: true - // setNextFreeVGPRToMax: false - // deduplicateArguments: true - // lazyAddArguments: true - // minLaunchTimeExpressionComplexity: 20 - // maxConcurrentSubExpressions: 1 - // maxConcurrentControlOps: none - // enableFullDivision: false - // scaleSkipPermlane: None - // assertOpKind: NoOp - // removeSetCoordinate: false - - // Loading Kernel Arguments: - // KernelArg{Tensor_0_extent_0, Value: Int64, CommandArgument(Tensor_0_extent)I64(c 0), o:0, s:8} - // KernelArg{Tensor_0_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_0_pointer)PG(c 0), o:8, s:8} - // KernelArg{Tensor_2_extent_2, Value: Int64, CommandArgument(Tensor_2_extent)I64(c 0), o:16, s:8} - // KernelArg{Tensor_2_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_2_pointer)PG(c 0), o:24, s:8} - // KernelArg{Tensor_4_extent_4, Value: Int64, CommandArgument(Tensor_4_extent)I64(c 0), o:32, s:8} - // KernelArg{Tensor_4_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_4_pointer)PG(c 0), o:40, s:8} - // KernelArg{user_Float_Value_6, Value: Float, CommandArgument(user_Float_Value_6)S(c 0), o:48, s:4} - // KernelArg{user_Float_Value_8, Value: Float, CommandArgument(user_Float_Value_8)S(c 0), o:52, s:4} - // KernelArg{Tensor_0_stride_0_9, Value: Int64, CommandArgument(Tensor_0_stride_0)I64(c 0), o:56, s:8} - // KernelArg{Tensor_0_size_1_10, Value: Int64, CommandArgument(Tensor_0_size_1)I64(c 0), o:64, s:8} - // KernelArg{Tensor_2_stride_1_12, Value: Int64, CommandArgument(Tensor_2_stride_1)I64(c 0), o:72, s:8} - // KernelArg{Tensor_4_stride_1_13, Value: Int64, CommandArgument(Tensor_4_stride_1)I64(c 0), o:80, s:8} - // KernelArg{Tensor_15_stride_1_14, Value: Int64, CommandArgument(Tensor_15_stride_1)I64(c 0), o:88, s:8} - // KernelArg{Tensor_15_extent_15, Value: Int64, CommandArgument(Tensor_15_extent)I64(c 0), o:96, s:8} - // KernelArg{Tensor_15_pointer, PointerGlobal: Half, read_write, CommandArgument(Tensor_15_pointer)PG(c 0), o:104, s:8} - -s_load_dwordx2 s[4:5], s[0:1], 0 // Load scalar value -s_load_dwordx2 s[6:7], s[0:1], 8 // Load scalar value -s_load_dwordx2 s[8:9], s[0:1], 16 // Load scalar value -s_load_dwordx2 s[10:11], s[0:1], 24 // Load scalar value -s_load_dwordx2 s[12:13], s[0:1], 32 // Load scalar value -s_load_dwordx2 s[14:15], s[0:1], 40 // Load scalar value -s_load_dword s16, s[0:1], 48 // Load scalar value -s_load_dword s17, s[0:1], 52 // Load scalar value -s_load_dwordx2 s[18:19], s[0:1], 56 // Load scalar value -s_load_dwordx2 s[20:21], s[0:1], 64 // Load scalar value -s_load_dwordx2 s[22:23], s[0:1], 72 // Load scalar value -s_load_dwordx2 s[24:25], s[0:1], 80 // Load scalar value -s_load_dwordx2 s[26:27], s[0:1], 88 // Load scalar value -s_load_dwordx2 s[28:29], s[0:1], 96 // Load scalar value -s_load_dwordx2 s[30:31], s[0:1], 104 // Load scalar value - // Extract 10 bit X coordinate -v_bfe_u32 v1, v0, 0, 10 - // Generate {Workitem Index X: v1:U32} into Workitem Index X: VGPR Value: UInt32 x 1: v1 - // reg expression - // Extract 10 bit Y coordinate -v_bfe_u32 v2, v0, 10, 10 - // Generate {Workitem Index Y: v2:U32} into Workitem Index Y: VGPR Value: UInt32 x 1: v2 - // reg expression - // Freeing Packed Workitem Index: 1 VGPR (Value: Raw32): v0 - - // Freeing Kernel argument pointer: 2 SGPRs (PointerGlobal: Raw32): s0, s1 - - // Marking Workgroup Index X: SGPR Value: UInt32 x 1: s2 as read-only - // Marking Workgroup Index Y: SGPR Value: UInt32 x 1: s3 as read-only - // Marking Workitem Index X: VGPR Value: UInt32 x 1: v1 as read-only - // Marking Workitem Index Y: VGPR Value: UInt32 x 1: v2 as read-only - // CodeGeneratorVisitor::generate() begin - // IdentifyParallelDimensions - // OrderMemory - // UpdateParameters - // AddLDS - // LowerLinear - // LowerTile - // LowerTensorContraction - // Simplify - // AddLDSPadding - // ConstantPropagation - // FuseExpressions - // ConnectWorkgroups - // WorkgroupRemapXCC - // UnrollLoops - // FuseLoops - // RemoveDuplicates - // OrderEpilogueBlocks - // Simplify - // CleanLoops - // SwizzleScale - // AddPrefetch - // AddF6LDSPadding - // AddDirect2LDS - // Simplify - // AddPRNG - // UpdateWavefrontParameters - // AssignIndexExpressions - // LoadPacked - // AddConvert - // NopExtraScopes - // InlineInits - // InlineIncrements - // RemoveImplicitScheduling - // OrderMultiplyNodes - // Simplify - // ScheduleMultiplyAndLDS - // Simplify - // OrderExchangeNodes - // AliasDataFlowTags - // AddLDSBarriers - // AddDeallocateDataFlow - // CleanArguments - // AddDeallocateArguments - // MergeAdjacentDeallocates - // Simplify - // SetWorkitemCount - // generate({1}) - // Kernel(1) BEGIN - // (op 1) generate({}) - // (op 1) end: generate({}) - // (op 1) generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) - // (op 1) NOP(1239) BEGIN - // (op 1239) generate({}) - // (op 1239) end: generate({}) - // (op 1) NOP(1239) END - // (op 1) NOP(1291) BEGIN - // (op 1291) generate({}) - // (op 1291) end: generate({}) - // (op 1) NOP(1291) END - // (op 1) NOP(1364) BEGIN - // (op 1364) generate({}) - // (op 1364) end: generate({}) - // (op 1) NOP(1364) END - // (op 1) NOP(1403) BEGIN - // (op 1403) generate({}) - // (op 1403) end: generate({}) - // (op 1) NOP(1403) END - // (op 1) NOP(1442) BEGIN - // (op 1442) generate({}) - // (op 1442) end: generate({}) - // (op 1) NOP(1442) END - // (op 1) NOP(1481) BEGIN - // (op 1481) generate({}) - // (op 1481) end: generate({}) - // (op 1) NOP(1481) END - // (op 1) NOP(1520) BEGIN - // (op 1520) generate({}) - // (op 1520) end: generate({}) - // (op 1) NOP(1520) END - // (op 1) NOP(1559) BEGIN - // (op 1559) generate({}) - // (op 1559) end: generate({}) - // (op 1) NOP(1559) END - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) BEGIN - // (op 1243) Assign dim(530) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 530: v**UNALLOCATED** - // (op 1243) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag530: VGPR Value: UInt32 x 1: (unallocated) - // (op 1243) reg expression - // (op 1243) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) BEGIN - // (op 1295) Assign dim(546) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 546: v**UNALLOCATED** - // (op 1295) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag546: VGPR Value: UInt32 x 1: (unallocated) - // (op 1295) reg expression - // (op 1295) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) BEGIN - // (op 1368) Assign dim(568) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 568: v**UNALLOCATED** - // (op 1368) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag568: VGPR Value: UInt32 x 1: (unallocated) - // (op 1368) reg expression - // (op 1368) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) BEGIN - // (op 1407) Assign dim(580) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 580: v**UNALLOCATED** - // (op 1407) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag580: VGPR Value: UInt32 x 1: (unallocated) - // (op 1407) reg expression - // (op 1407) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) BEGIN - // (op 1446) Assign dim(592) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 592: v**UNALLOCATED** - // (op 1446) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag592: VGPR Value: UInt32 x 1: (unallocated) - // (op 1446) reg expression - // (op 1446) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) BEGIN - // (op 1485) Assign dim(604) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 604: v**UNALLOCATED** - // (op 1485) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag604: VGPR Value: UInt32 x 1: (unallocated) - // (op 1485) reg expression - // (op 1485) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) BEGIN - // (op 1524) Assign dim(616) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 616: v**UNALLOCATED** - // (op 1524) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag616: VGPR Value: UInt32 x 1: (unallocated) - // (op 1524) reg expression - // (op 1524) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) BEGIN - // (op 1563) Assign dim(628) = ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 - // tag 628: v**UNALLOCATED** - // (op 1563) Generate ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32 into DataFlowTag628: VGPR Value: UInt32 x 1: (unallocated) - // (op 1563) reg expression - // (op 1563) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 -v_lshrrev_b32 v0, 7, v1 // (op 1243) - // (op 1243) BEGIN: Flatten[1] - // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 -v_and_b32 v3, 31, v1 // (op 1243) - // (op 1243) END: Flatten[1] - // (op 1243) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v4 -v_lshl_add_u32 v4, v0, 5, v3 // (op 1243) - // (op 1243) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v3 - - // Freeing : 1 VGPR (Value: UInt32) (op 1243): v0 - - // (op 1243) BEGIN: Flatten[1] - // (op 1243) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 -v_and_b32 v0, 63, v1 // (op 1243) - // (op 1243) END: Flatten[1] - // (op 1243) LogicalShiftR({Flatten[1]: v0:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 -v_lshrrev_b32 v3, 5, v0 // (op 1243) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1243): v0 - - // (op 1243) BEGIN: TileTile - // (op 1243) {TileTile: ShiftL(v3:U32, 2:U32)U32} - // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1243) value (VGPR Value: UInt32 x 1: v3) - // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v0 -v_lshlrev_b32 v0, 2, v3 // (op 1243) - // (op 1243) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1243): v3 - - // (op 1243) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1243): v3 -v_lshl_add_u32 v3, v4, 6, v0 // (op 1243) - // (op 1243) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1243): v0 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v4 - - // (op 1243) ShiftL({Tile: v3:U32}, 1:U32)U32 - // (op 1243) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1243) value (Tile: VGPR Value: UInt32 x 1: v3) - // (op 1243) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 -v_lshlrev_b32 v0, 1, v3 // (op 1243) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1243): v3 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243) END -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 -v_lshrrev_b32 v3, 6, v1 // (op 1295) - // (op 1295) BEGIN: Tile - // (op 1295) {Tile: BitwiseAnd(v3:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 -v_and_b32 v4, 1, v3 // (op 1295) - // (op 1295) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1295): v3 - - // (op 1295) BEGIN: Flatten[1] - // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 -v_and_b32 v3, 31, v1 // (op 1295) - // (op 1295) END: Flatten[1] - // (op 1295) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v5 -v_lshl_add_u32 v5, v4, 5, v3 // (op 1295) - // (op 1295) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v3 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v4 - - // (op 1295) BEGIN: Flatten[1] - // (op 1295) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 -v_and_b32 v3, 63, v1 // (op 1295) - // (op 1295) END: Flatten[1] - // (op 1295) LogicalShiftR({Flatten[1]: v3:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 -v_lshrrev_b32 v4, 5, v3 // (op 1295) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1295): v3 - - // (op 1295) BEGIN: TileTile - // (op 1295) {TileTile: ShiftL(v4:U32, 2:U32)U32} - // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1295) value (VGPR Value: UInt32 x 1: v4) - // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v3 -v_lshlrev_b32 v3, 2, v4 // (op 1295) - // (op 1295) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1295): v4 - - // (op 1295) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1295): v4 -v_lshl_add_u32 v4, v5, 6, v3 // (op 1295) - // (op 1295) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1295): v3 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v5 - - // (op 1295) ShiftL({Tile: v4:U32}, 1:U32)U32 - // (op 1295) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1295) value (Tile: VGPR Value: UInt32 x 1: v4) - // (op 1295) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v3 -v_lshlrev_b32 v3, 1, v4 // (op 1295) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1295): v4 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295) END -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 -v_lshrrev_b32 v4, 7, v1 // (op 1368) - // (op 1368) BEGIN: Flatten[1] - // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 -v_and_b32 v5, 31, v1 // (op 1368) - // (op 1368) END: Flatten[1] - // (op 1368) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v6 -v_lshl_add_u32 v6, v4, 5, v5 // (op 1368) - // (op 1368) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v5 - - // Freeing : 1 VGPR (Value: UInt32) (op 1368): v4 - - // (op 1368) BEGIN: Flatten[1] - // (op 1368) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 -v_and_b32 v4, 63, v1 // (op 1368) - // (op 1368) END: Flatten[1] - // (op 1368) LogicalShiftR({Flatten[1]: v4:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 -v_lshrrev_b32 v5, 5, v4 // (op 1368) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1368): v4 - - // (op 1368) BEGIN: TileTile - // (op 1368) {TileTile: ShiftL(v5:U32, 2:U32)U32} - // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1368) value (VGPR Value: UInt32 x 1: v5) - // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v4 -v_lshlrev_b32 v4, 2, v5 // (op 1368) - // (op 1368) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1368): v5 - - // (op 1368) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1368): v5 -v_lshl_add_u32 v5, v6, 6, v4 // (op 1368) - // (op 1368) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1368): v4 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v6 - - // (op 1368) ShiftL({Tile: v5:U32}, 1:U32)U32 - // (op 1368) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1368) value (Tile: VGPR Value: UInt32 x 1: v5) - // (op 1368) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v4 -v_lshlrev_b32 v4, 1, v5 // (op 1368) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1368): v5 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368) END -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 -v_lshrrev_b32 v5, 6, v1 // (op 1407) - // (op 1407) BEGIN: Tile - // (op 1407) {Tile: BitwiseAnd(v5:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 -v_and_b32 v6, 1, v5 // (op 1407) - // (op 1407) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1407): v5 - - // (op 1407) BEGIN: Flatten[1] - // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 -v_and_b32 v5, 31, v1 // (op 1407) - // (op 1407) END: Flatten[1] - // (op 1407) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v7 -v_lshl_add_u32 v7, v6, 5, v5 // (op 1407) - // (op 1407) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v5 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v6 - - // (op 1407) BEGIN: Flatten[1] - // (op 1407) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 -v_and_b32 v5, 63, v1 // (op 1407) - // (op 1407) END: Flatten[1] - // (op 1407) LogicalShiftR({Flatten[1]: v5:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 -v_lshrrev_b32 v6, 5, v5 // (op 1407) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1407): v5 - - // (op 1407) BEGIN: TileTile - // (op 1407) {TileTile: ShiftL(v6:U32, 2:U32)U32} - // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1407) value (VGPR Value: UInt32 x 1: v6) - // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v5 -v_lshlrev_b32 v5, 2, v6 // (op 1407) - // (op 1407) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1407): v6 - - // (op 1407) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1407): v6 -v_lshl_add_u32 v6, v7, 6, v5 // (op 1407) - // (op 1407) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1407): v5 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v7 - - // (op 1407) ShiftL({Tile: v6:U32}, 1:U32)U32 - // (op 1407) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1407) value (Tile: VGPR Value: UInt32 x 1: v6) - // (op 1407) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v5 -v_lshlrev_b32 v5, 1, v6 // (op 1407) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1407): v6 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407) END -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 -v_lshrrev_b32 v6, 7, v1 // (op 1446) - // (op 1446) BEGIN: Flatten[1] - // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 -v_and_b32 v7, 31, v1 // (op 1446) - // (op 1446) END: Flatten[1] - // (op 1446) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v8 -v_lshl_add_u32 v8, v6, 5, v7 // (op 1446) - // (op 1446) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v7 - - // Freeing : 1 VGPR (Value: UInt32) (op 1446): v6 - - // (op 1446) BEGIN: Flatten[1] - // (op 1446) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 -v_and_b32 v6, 63, v1 // (op 1446) - // (op 1446) END: Flatten[1] - // (op 1446) LogicalShiftR({Flatten[1]: v6:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 -v_lshrrev_b32 v7, 5, v6 // (op 1446) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1446): v6 - - // (op 1446) BEGIN: TileTile - // (op 1446) {TileTile: ShiftL(v7:U32, 2:U32)U32} - // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1446) value (VGPR Value: UInt32 x 1: v7) - // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v6 -v_lshlrev_b32 v6, 2, v7 // (op 1446) - // (op 1446) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1446): v7 - - // (op 1446) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1446): v7 -v_lshl_add_u32 v7, v8, 6, v6 // (op 1446) - // (op 1446) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1446): v6 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v8 - - // (op 1446) ShiftL({Tile: v7:U32}, 1:U32)U32 - // (op 1446) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1446) value (Tile: VGPR Value: UInt32 x 1: v7) - // (op 1446) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v6 -v_lshlrev_b32 v6, 1, v7 // (op 1446) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1446): v7 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446) END -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 -v_lshrrev_b32 v7, 6, v1 // (op 1485) - // (op 1485) BEGIN: Tile - // (op 1485) {Tile: BitwiseAnd(v7:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 -v_and_b32 v8, 1, v7 // (op 1485) - // (op 1485) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1485): v7 - - // (op 1485) BEGIN: Flatten[1] - // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 -v_and_b32 v7, 31, v1 // (op 1485) - // (op 1485) END: Flatten[1] - // (op 1485) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v9 -v_lshl_add_u32 v9, v8, 5, v7 // (op 1485) - // (op 1485) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v7 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v8 - - // (op 1485) BEGIN: Flatten[1] - // (op 1485) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 -v_and_b32 v7, 63, v1 // (op 1485) - // (op 1485) END: Flatten[1] - // (op 1485) LogicalShiftR({Flatten[1]: v7:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 -v_lshrrev_b32 v8, 5, v7 // (op 1485) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1485): v7 - - // (op 1485) BEGIN: TileTile - // (op 1485) {TileTile: ShiftL(v8:U32, 2:U32)U32} - // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1485) value (VGPR Value: UInt32 x 1: v8) - // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v7 -v_lshlrev_b32 v7, 2, v8 // (op 1485) - // (op 1485) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1485): v8 - - // (op 1485) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1485): v8 -v_lshl_add_u32 v8, v9, 6, v7 // (op 1485) - // (op 1485) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1485): v7 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v9 - - // (op 1485) ShiftL({Tile: v8:U32}, 1:U32)U32 - // (op 1485) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1485) value (Tile: VGPR Value: UInt32 x 1: v8) - // (op 1485) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v7 -v_lshlrev_b32 v7, 1, v8 // (op 1485) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1485): v8 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485) END -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 -v_lshrrev_b32 v8, 7, v1 // (op 1524) - // (op 1524) BEGIN: Flatten[1] - // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 -v_and_b32 v9, 31, v1 // (op 1524) - // (op 1524) END: Flatten[1] - // (op 1524) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v10 -v_lshl_add_u32 v10, v8, 5, v9 // (op 1524) - // (op 1524) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v9 - - // Freeing : 1 VGPR (Value: UInt32) (op 1524): v8 - - // (op 1524) BEGIN: Flatten[1] - // (op 1524) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 -v_and_b32 v8, 63, v1 // (op 1524) - // (op 1524) END: Flatten[1] - // (op 1524) LogicalShiftR({Flatten[1]: v8:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 -v_lshrrev_b32 v9, 5, v8 // (op 1524) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1524): v8 - - // (op 1524) BEGIN: TileTile - // (op 1524) {TileTile: ShiftL(v9:U32, 2:U32)U32} - // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1524) value (VGPR Value: UInt32 x 1: v9) - // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v8 -v_lshlrev_b32 v8, 2, v9 // (op 1524) - // (op 1524) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1524): v9 - - // (op 1524) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1524): v9 -v_lshl_add_u32 v9, v10, 6, v8 // (op 1524) - // (op 1524) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1524): v8 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v10 - - // (op 1524) ShiftL({Tile: v9:U32}, 1:U32)U32 - // (op 1524) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1524) value (Tile: VGPR Value: UInt32 x 1: v9) - // (op 1524) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v8 -v_lshlrev_b32 v8, 1, v9 // (op 1524) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1524): v9 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524) END -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 -v_lshrrev_b32 v9, 6, v1 // (op 1563) - // (op 1563) BEGIN: Tile - // (op 1563) {Tile: BitwiseAnd(v9:U32, 1:U32)U32} - // (op 1) Deallocate{}(1913) BEGIN - // (op 1913) Deallocate 84 - // Deleting tag 84 - // (op 1) Deallocate{}(1913) END -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 -v_and_b32 v10, 1, v9 // (op 1563) - // (op 1563) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1563): v9 - - // (op 1563) BEGIN: Flatten[1] - // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 31:U32)U32} - // (op 1) Assign VGPR 16:U32(1244) BEGIN - // (op 1244) Assign dim(531) = 16:U32 - // (op 1244) Assign stride expression - // (op 1) Assign VGPR 16:U32(1244) END - // (op 1) Assign VGPR 16:U32(1369) BEGIN - // (op 1369) Assign dim(569) = 16:U32 - // (op 1369) Assign stride expression - // (op 1) Assign VGPR 16:U32(1369) END - // (op 1) Assign VGPR 16:U32(1447) BEGIN - // (op 1447) Assign dim(593) = 16:U32 - // (op 1447) Assign stride expression - // (op 1) Assign VGPR 16:U32(1447) END - // (op 1) Assign VGPR 16:U32(1525) BEGIN - // (op 1525) Assign dim(617) = 16:U32 - // (op 1525) Assign stride expression - // (op 1) Assign VGPR 16:U32(1525) END - // (op 1) NOP(1240) BEGIN - // (op 1240) generate({}) - // (op 1240) end: generate({}) - // (op 1) NOP(1240) END - // (op 1) NOP(1365) BEGIN - // (op 1365) generate({}) - // (op 1365) end: generate({}) - // (op 1) NOP(1365) END - // (op 1) NOP(1443) BEGIN - // (op 1443) generate({}) - // (op 1443) end: generate({}) - // (op 1) NOP(1443) END - // (op 1) NOP(1521) BEGIN - // (op 1521) generate({}) - // (op 1521) end: generate({}) - // (op 1) NOP(1521) END - // (op 1) Assign VGPR 2:U32(1248) BEGIN - // (op 1248) Assign dim(533) = 2:U32 - // (op 1248) Assign stride expression - // (op 1) Assign VGPR 2:U32(1248) END - // (op 1) Assign VGPR 2:U32(1373) BEGIN - // (op 1373) Assign dim(571) = 2:U32 - // (op 1373) Assign stride expression - // (op 1) Assign VGPR 2:U32(1373) END - // (op 1) Assign VGPR 2:U32(1451) BEGIN - // (op 1451) Assign dim(595) = 2:U32 - // (op 1451) Assign stride expression - // (op 1) Assign VGPR 2:U32(1451) END - // (op 1) Assign VGPR 2:U32(1529) BEGIN - // (op 1529) Assign dim(619) = 2:U32 - // (op 1529) Assign stride expression - // (op 1) Assign VGPR 2:U32(1529) END -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 -v_and_b32 v9, 31, v1 // (op 1563) - // (op 1563) END: Flatten[1] - // (op 1563) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v11 -v_lshl_add_u32 v11, v10, 5, v9 // (op 1563) - // (op 1563) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v9 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v10 - - // (op 1563) BEGIN: Flatten[1] - // (op 1563) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 -v_and_b32 v9, 63, v1 // (op 1563) - // (op 1563) END: Flatten[1] - // (op 1563) LogicalShiftR({Flatten[1]: v9:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 -v_lshrrev_b32 v10, 5, v9 // (op 1563) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1563): v9 - - // (op 1563) BEGIN: TileTile - // (op 1563) {TileTile: ShiftL(v10:U32, 2:U32)U32} - // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1563) value (VGPR Value: UInt32 x 1: v10) - // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v9 -v_lshlrev_b32 v9, 2, v10 // (op 1563) - // (op 1563) END: TileTile - // Freeing : 1 VGPR (Value: UInt32) (op 1563): v10 - - // (op 1563) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1563): v10 -v_lshl_add_u32 v10, v11, 6, v9 // (op 1563) - // (op 1563) END: Tile - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1563): v9 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v11 - - // (op 1563) ShiftL({Tile: v10:U32}, 1:U32)U32 - // (op 1563) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1563) value (Tile: VGPR Value: UInt32 x 1: v10) - // (op 1563) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v9 -v_lshlrev_b32 v9, 1, v10 // (op 1563) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1563): v10 - - // (op 1) Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563) END - // (op 1) Deallocate{}(1918) BEGIN - // (op 1918) Deallocate 144 - // Deleting tag 144 - // (op 1) Deallocate{}(1918) END - // (op 1) Assign VGPR 16:U32(1296) BEGIN - // (op 1296) Assign dim(547) = 16:U32 - // (op 1296) Assign stride expression - // (op 1) Assign VGPR 16:U32(1296) END - // (op 1) Assign VGPR 16:U32(1408) BEGIN - // (op 1408) Assign dim(581) = 16:U32 - // (op 1408) Assign stride expression - // (op 1) Assign VGPR 16:U32(1408) END - // (op 1) Assign VGPR 16:U32(1486) BEGIN - // (op 1486) Assign dim(605) = 16:U32 - // (op 1486) Assign stride expression - // (op 1) Assign VGPR 16:U32(1486) END - // (op 1) Assign VGPR 16:U32(1564) BEGIN - // (op 1564) Assign dim(629) = 16:U32 - // (op 1564) Assign stride expression - // (op 1) Assign VGPR 16:U32(1564) END - // (op 1) NOP(1292) BEGIN - // (op 1292) generate({}) - // (op 1292) end: generate({}) - // (op 1) NOP(1292) END - // (op 1) NOP(1404) BEGIN - // (op 1404) generate({}) - // (op 1404) end: generate({}) - // (op 1) NOP(1404) END - // (op 1) NOP(1482) BEGIN - // (op 1482) generate({}) - // (op 1482) end: generate({}) - // (op 1) NOP(1482) END - // (op 1) NOP(1560) BEGIN - // (op 1560) generate({}) - // (op 1560) end: generate({}) - // (op 1) NOP(1560) END - // (op 1) Assign VGPR 2:U32(1300) BEGIN - // (op 1300) Assign dim(549) = 2:U32 - // (op 1300) Assign stride expression - // (op 1) Assign VGPR 2:U32(1300) END - // (op 1) Assign VGPR 2:U32(1412) BEGIN - // (op 1412) Assign dim(583) = 2:U32 - // (op 1412) Assign stride expression - // (op 1) Assign VGPR 2:U32(1412) END - // (op 1) Assign VGPR 2:U32(1490) BEGIN - // (op 1490) Assign dim(607) = 2:U32 - // (op 1490) Assign stride expression - // (op 1) Assign VGPR 2:U32(1490) END - // (op 1) Assign VGPR 2:U32(1568) BEGIN - // (op 1568) Assign dim(631) = 2:U32 - // (op 1568) Assign stride expression - // (op 1) Assign VGPR 2:U32(1568) END - // (op 1) LoadVGPR Value: Float(2) BEGIN - // tag 24: v**UNALLOCATED** - // (op 2) GEN: LoadVGPR; scalar value - // (op 2) Get arg user_Float_Value_8 - // (op 1) LoadVGPR Value: Float(24) BEGIN - // tag 33: v**UNALLOCATED** - // (op 24) GEN: LoadVGPR; scalar value - // (op 24) Get arg user_Float_Value_6 -// Allocated : 1 VGPR (Value: Float) (op 2): v10 -s_waitcnt lgkmcnt(0) -v_mov_b32 v10, s17 // (op 2) Move value - // (op 1) LoadVGPR Value: Float(2) END -// Allocated : 1 VGPR (Value: Float) (op 24): v11 -v_mov_b32 v11, s16 // (op 24) Move value - // (op 1) LoadVGPR Value: Float(24) END - // (op 1) Deallocate{user_Float_Value_8}(1997) BEGIN - // (op 1997) Deallocate user_Float_Value_8 - // Freeing user_Float_Value_8: 1 SGPR (Value: Raw32): s17 - - // (op 1) Deallocate{user_Float_Value_8}(1997) END - // (op 1) Deallocate{user_Float_Value_6}(1999) BEGIN - // (op 1999) Deallocate user_Float_Value_6 - // Freeing user_Float_Value_6: 1 SGPR (Value: Raw32): s16 - - // (op 1) Deallocate{user_Float_Value_6}(1999) END - // (op 1) Scope(670) BEGIN - // (op 670) Lock Scope 670 - // Lock Branch - // (op 670) generate({675}) - // (op 670) NOP(675) BEGIN - // (op 675) generate({}) - // (op 675) end: generate({}) - // (op 670) NOP(675) END - // (op 670) Assign ACCVGPR 0.00000:S(44) BEGIN - // (op 44) Assign dim(35) = 0.00000:S - // tag 35: a**UNALLOCATED** - // (op 44) Generate 0.00000:S into DataFlowTag35: ACCVGPR Value: Float x 16: (unallocated) -// Allocated DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 -v_accvgpr_write a0, 0.00000 // (op 44) call() -v_accvgpr_write a1, 0.00000 // (op 44) call() -v_accvgpr_write a2, 0.00000 // (op 44) call() -v_accvgpr_write a3, 0.00000 // (op 44) call() -v_accvgpr_write a4, 0.00000 // (op 44) call() -v_accvgpr_write a5, 0.00000 // (op 44) call() -v_accvgpr_write a6, 0.00000 // (op 44) call() -v_accvgpr_write a7, 0.00000 // (op 44) call() -v_accvgpr_write a8, 0.00000 // (op 44) call() -v_accvgpr_write a9, 0.00000 // (op 44) call() -v_accvgpr_write a10, 0.00000 // (op 44) call() -v_accvgpr_write a11, 0.00000 // (op 44) call() -v_accvgpr_write a12, 0.00000 // (op 44) call() -v_accvgpr_write a13, 0.00000 // (op 44) call() -v_accvgpr_write a14, 0.00000 // (op 44) call() -v_accvgpr_write a15, 0.00000 // (op 44) call() - // (op 670) Assign ACCVGPR 0.00000:S(44) END - // (op 670) Scope(1074) BEGIN - // (op 1074) Lock Scope 1074 - // Lock Branch - // (op 1074) generate({1069}) - // (op 1074) NOP(1069) BEGIN - // (op 1069) generate({}) - // (op 1069) end: generate({}) - // (op 1074) NOP(1069) END - // (op 1074) Assign VGPR 128:U64(1079) BEGIN - // (op 1079) Assign dim(482) = 128:U64 - // (op 1079) Assign stride expression - // (op 1074) Assign VGPR 128:U64(1079) END - // (op 1074) NOP(1070) BEGIN - // (op 1070) generate({}) - // (op 1070) end: generate({}) - // (op 1074) NOP(1070) END - // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) BEGIN - // (op 1082) Assign dim(483) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 - // tag 483: v**UNALLOCATED** - // (op 1082) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag483: VGPR Value: UInt64 x 1: (unallocated) - // (op 1082) Get arg Tensor_0_stride_0_9 - // (op 1082) reg expression - // (op 1082) reg expression - // (op 1082) reg expression - // (op 1082) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 -v_lshrrev_b32 v12, 5, v1 // (op 1082) - // (op 1082) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1082): v13 -v_lshl_add_u32 v13, s2, 6, v12 // (op 1082) - // (op 1082) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1082): v12 - - // (op 1082) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 -v_and_b32 v12, -32, v1 // (op 1082) - // (op 1082) BEGIN: Flatten[1] - // (op 1082) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1082): v14 -v_sub_u32 v14, v1, v12 // (op 1082) - // (op 1082) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1082): v12 - - // (op 1082) BEGIN: TileTile - // (op 1082) {TileTile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} - // (op 1082) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1082) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) - // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1082): v12 -v_lshlrev_b32 v12, 1, v14 // (op 1082) - // (op 1082) END: TileTile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1082): v14 - -// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 -v_mov_b32 v15, 0 // (op 1082) convert -v_mov_b32 v14, v12 // (op 1082) convert - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1082): v12 - - // (op 1082) BEGIN: Split - // (op 1082) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1082) lhs (Tile: VGPR Value: UInt32 x 1: v13) - // (op 1082) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) -// Allocated : 2 VGPRs (Value: UInt64) (op 1082): v16, v17 -v_mul_lo_u32 v17, v13, s19 // (op 1082) most significant: low of low * high - // (op 1082) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1082): v12 -v_mul_hi_u32 v12, v13, s18 // (op 1082) most significant: high of low * low -v_mul_lo_u32 v16, v13, s18 // (op 1082) least significant: low of low * low -v_add_u32 v17, v17, v12 // (op 1082) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1082): v12 - - // (op 1082) Add: dest (VGPR Value: UInt64 x 1: v[16:17]) = - // (op 1082) lhs (VGPR Value: UInt64 x 1: v[16:17]) - // (op 1082) rhs (TileTile: VGPR Value: UInt64 x 1: v[14:15]) -// Allocated : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 -v_add_co_u32 v16, s[0:1], v16, v14 // (op 1082) least significant half -v_addc_co_u32 v17, s[0:1], v17, v15, s[0:1] // (op 1082) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1082): s0, s1 - - // (op 1082) END: Split - // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1082): v14, v15 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1082): v13 - - // (op 1082) ShiftL({Split: v[16:17]:U64}, 1:U32)U64 - // (op 1082) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1082) value (Split: VGPR Value: UInt64 x 1: v[16:17]) - // (op 1082) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v12, v13 -v_lshlrev_b64 v[12:13], 1, v[16:17] // (op 1082) - // Freeing Split: 2 VGPRs (Value: UInt64) (op 1082): v16, v17 - - // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082) END - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) BEGIN - // (op 1083) Assign dim(484) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1083) Assign stride expression - // (op 1074) Tag 1083non referenced extraArgs = {Tensor_0_stride_0_9} - - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083) END - // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) BEGIN - // (op 1084) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // tag 477: s**UNALLOCATED** - // (op 1084) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: (unallocated) - // (op 1084) Get arg Tensor_0_pointer - // (op 1084) Get arg Tensor_0_extent_0 - // (op 1084) reg expression - // (op 1084) reg expression - // (op 1084) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 - // (op 1084) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1084) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) - // (op 1084) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1084): s0, s1 -s_lshl_b64 s[0:1], s[4:5], 1 // (op 1084) - // (op 1084) reg expression -// Allocated DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 -s_mov_b32 s32, s6 // (op 1084) reg expression -s_mov_b32 s33, s7 // (op 1084) reg expression -s_mov_b32 s34, s0 // (op 1084) reg expression -s_mov_b32 s35, 131072 // (op 1084) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1084): s0, s1 - - // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084) END - // (op 1074) NOP(1071) BEGIN - // (op 1071) generate({}) - // (op 1071) end: generate({}) - // (op 1074) NOP(1071) END - // (op 1074) Assign VGPR 2:U64(1089) BEGIN - // (op 1089) Assign dim(486) = 2:U64 - // (op 1089) Assign stride expression - // (op 1074) Assign VGPR 2:U64(1089) END - // (op 1074) NOP(1092) BEGIN - // (op 1092) generate({}) - // (op 1092) end: generate({}) - // (op 1074) NOP(1092) END - // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) BEGIN - // (op 1101) Assign dim(487) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 - // tag 487: v**UNALLOCATED** - // (op 1101) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: (unallocated) - // (op 1101) Get arg Tensor_0_stride_0_9 - // (op 1101) reg expression - // (op 1101) reg expression - // (op 1101) reg expression - // (op 1101) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 -v_lshrrev_b32 v14, 5, v1 // (op 1101) - // (op 1101) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1101): v15 -v_lshl_add_u32 v15, s2, 6, v14 // (op 1101) - // (op 1101) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1101): v14 - - // (op 1101) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 -v_and_b32 v14, -32, v1 // (op 1101) - // (op 1101) BEGIN: Flatten[1] - // (op 1101) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v14:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1101): v16 -v_sub_u32 v16, v1, v14 // (op 1101) - // (op 1101) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1101): v14 - - // (op 1101) BEGIN: TileTile - // (op 1101) {TileTile: ShiftL({Flatten[1]: v16:U32}, 1:U32)U32} - // (op 1101) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1101) value (Flatten[1]: VGPR Value: UInt32 x 1: v16) - // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1101): v14 -v_lshlrev_b32 v14, 1, v16 // (op 1101) - // (op 1101) END: TileTile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1101): v16 - -// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 -v_mov_b32 v17, 0 // (op 1101) convert -v_mov_b32 v16, v14 // (op 1101) convert - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1101): v14 - - // (op 1101) BEGIN: Split - // (op 1101) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1101) lhs (Tile: VGPR Value: UInt32 x 1: v15) - // (op 1101) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) -// Allocated : 2 VGPRs (Value: UInt64) (op 1101): v18, v19 -v_mul_lo_u32 v19, v15, s19 // (op 1101) most significant: low of low * high - // (op 1101) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1101): v14 -v_mul_hi_u32 v14, v15, s18 // (op 1101) most significant: high of low * low -v_mul_lo_u32 v18, v15, s18 // (op 1101) least significant: low of low * low -v_add_u32 v19, v19, v14 // (op 1101) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1101): v14 - - // (op 1101) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = - // (op 1101) lhs (VGPR Value: UInt64 x 1: v[18:19]) - // (op 1101) rhs (TileTile: VGPR Value: UInt64 x 1: v[16:17]) -// Allocated : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 -v_add_co_u32 v18, s[0:1], v18, v16 // (op 1101) least significant half -v_addc_co_u32 v19, s[0:1], v19, v17, s[0:1] // (op 1101) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1101): s0, s1 - - // (op 1101) END: Split - // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1101): v16, v17 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1101): v15 - - // (op 1101) ShiftL({Split: v[18:19]:U64}, 1:U32)U64 - // (op 1101) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1101) value (Split: VGPR Value: UInt64 x 1: v[18:19]) - // (op 1101) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v14, v15 -v_lshlrev_b64 v[14:15], 1, v[18:19] // (op 1101) - // Freeing Split: 2 VGPRs (Value: UInt64) (op 1101): v18, v19 - - // (op 1074) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101) END - // (op 1074) Assign VGPR 128:U64(1102) BEGIN - // (op 1102) Assign dim(488) = 128:U64 - // (op 1102) Assign stride expression - // (op 1074) Assign VGPR 128:U64(1102) END - // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) BEGIN - // (op 1103) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // (op 1103) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // (op 1103) Get arg Tensor_0_pointer - // (op 1103) Get arg Tensor_0_extent_0 - // (op 1103) reg expression - // (op 1103) reg expression - // (op 1103) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 - // (op 1103) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1103) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) - // (op 1103) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1103): s0, s1 -s_lshl_b64 s[0:1], s[4:5], 1 // (op 1103) - // (op 1103) reg expression -s_mov_b32 s32, s6 // (op 1103) reg expression -s_mov_b32 s33, s7 // (op 1103) reg expression -s_mov_b32 s34, s0 // (op 1103) reg expression -s_mov_b32 s35, 131072 // (op 1103) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1103): s0, s1 - - // (op 1074) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103) END - // (op 1074) NOP(1094) BEGIN - // (op 1094) generate({}) - // (op 1094) end: generate({}) - // (op 1074) NOP(1094) END - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) BEGIN - // (op 1108) Assign dim(490) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1108) Assign stride expression - // (op 1074) Tag 1108non referenced extraArgs = {Tensor_0_stride_0_9} - - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108) END - // (op 1074) NOP(1095) BEGIN - // (op 1095) generate({}) - // (op 1095) end: generate({}) - // (op 1074) NOP(1095) END - // (op 1074) Assign VGPR 2:U64(1111) BEGIN - // (op 1111) Assign dim(492) = 2:U64 - // (op 1111) Assign stride expression - // (op 1074) Assign VGPR 2:U64(1111) END - // (op 1074) NOP(1136) BEGIN - // (op 1136) generate({}) - // (op 1136) end: generate({}) - // (op 1074) NOP(1136) END - // (op 1074) Assign VGPR 128:U64(1143) BEGIN - // (op 1143) Assign dim(501) = 128:U64 - // (op 1143) Assign stride expression - // (op 1074) Assign VGPR 128:U64(1143) END - // (op 1074) NOP(1137) BEGIN - // (op 1137) generate({}) - // (op 1137) end: generate({}) - // (op 1074) NOP(1137) END - // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) BEGIN - // (op 1146) Assign dim(502) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} - // tag 502: v**UNALLOCATED** - // (op 1146) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag502: VGPR Value: UInt64 x 1: (unallocated) - // (op 1146) Get arg Tensor_2_stride_1_12 - // (op 1146) reg expression - // (op 1146) reg expression - // (op 1146) reg expression - // (op 1146) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 -v_and_b32 v16, -32, v1 // (op 1146) - // (op 1146) BEGIN: Flatten[1] - // (op 1146) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 -v_sub_u32 v17, v1, v16 // (op 1146) - // (op 1146) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1146): v16 - - // (op 1146) BEGIN: TileTile - // (op 1146) {TileTile: ShiftL({Flatten[1]: v17:U32}, 1:U32)U32} - // (op 1146) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1146) value (Flatten[1]: VGPR Value: UInt32 x 1: v17) - // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 -v_lshlrev_b32 v16, 1, v17 // (op 1146) - // (op 1146) END: TileTile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1146): v17 - -// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1146): v18, v19 -v_mov_b32 v19, 0 // (op 1146) convert -v_mov_b32 v18, v16 // (op 1146) convert - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1146): v16 - - // (op 1146) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1146): v16 -v_lshrrev_b32 v16, 5, v1 // (op 1146) - // (op 1146) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1146): v17 -v_lshl_add_u32 v17, s3, 6, v16 // (op 1146) - // (op 1146) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1146): v16 - - // (op 1146) Multiply({Tile: v17:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 - // (op 1146) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = - // (op 1146) lhs (Tile: VGPR Value: UInt32 x 1: v17) - // (op 1146) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) -// Allocated : 2 VGPRs (Value: Int64) (op 1146): v20, v21 -v_mul_lo_u32 v21, v17, s23 // (op 1146) most significant: low of low * high - // (op 1146) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1146): v16 -v_mul_hi_u32 v16, v17, s22 // (op 1146) most significant: high of low * low -v_mul_lo_u32 v20, v17, s22 // (op 1146) least significant: low of low * low -v_add_u32 v21, v21, v16 // (op 1146) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1146): v16 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1146): v17 - - // (op 1146) BEGIN: Split - // (op 1146) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1146) lhs (TileTile: VGPR Value: UInt64 x 1: v[18:19]) - // (op 1146) rhs (VGPR Value: Int64 x 1: v[20:21]) -// Allocated DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 -// Allocated : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 -v_add_co_u32 v16, s[0:1], v18, v20 // (op 1146) least significant half -v_addc_co_u32 v17, s[0:1], v19, v21, s[0:1] // (op 1146) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1146): s0, s1 - - // (op 1146) ShiftL: dest (VGPR Value: UInt64 x 1: v[16:17]) = - // (op 1146) value (VGPR Value: UInt64 x 1: v[16:17]) - // (op 1146) shiftAmount (Literal Value: UInt32 x 0: 1) -v_lshlrev_b64 v[16:17], 1, v[16:17] // (op 1146) - // (op 1146) END: Split - // Freeing : 2 VGPRs (Value: Int64) (op 1146): v20, v21 - - // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1146): v18, v19 - - // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146) END - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) BEGIN - // (op 1147) Assign dim(503) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1147) Assign stride expression - // (op 1074) Tag 1147non referenced extraArgs = {Tensor_2_stride_1_12} - - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147) END - // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) BEGIN - // (op 1148) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // tag 496: s**UNALLOCATED** - // (op 1148) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: (unallocated) - // (op 1148) Get arg Tensor_2_pointer - // (op 1148) Get arg Tensor_2_extent_2 - // (op 1148) reg expression - // (op 1148) reg expression - // (op 1148) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 - // (op 1148) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1148) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) - // (op 1148) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1148): s0, s1 -s_lshl_b64 s[0:1], s[8:9], 1 // (op 1148) - // (op 1148) reg expression -// Allocated DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 -s_mov_b32 s36, s10 // (op 1148) reg expression -s_mov_b32 s37, s11 // (op 1148) reg expression -s_mov_b32 s38, s0 // (op 1148) reg expression -s_mov_b32 s39, 131072 // (op 1148) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1148): s0, s1 - - // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148) END - // (op 1074) NOP(1138) BEGIN - // (op 1138) generate({}) - // (op 1138) end: generate({}) - // (op 1074) NOP(1138) END - // (op 1074) Assign VGPR 2:U64(1153) BEGIN - // (op 1153) Assign dim(505) = 2:U64 - // (op 1153) Assign stride expression - // (op 1074) Assign VGPR 2:U64(1153) END - // (op 1074) NOP(1156) BEGIN - // (op 1156) generate({}) - // (op 1156) end: generate({}) - // (op 1074) NOP(1156) END - // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) BEGIN - // (op 1165) Assign dim(506) = {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} - // tag 506: v**UNALLOCATED** - // (op 1165) Generate {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag506: VGPR Value: UInt64 x 1: (unallocated) - // (op 1165) Get arg Tensor_2_stride_1_12 - // (op 1165) reg expression - // (op 1165) reg expression - // (op 1165) reg expression - // (op 1165) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 -v_and_b32 v18, -32, v1 // (op 1165) - // (op 1165) BEGIN: Flatten[1] - // (op 1165) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v18:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 -v_sub_u32 v19, v1, v18 // (op 1165) - // (op 1165) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1165): v18 - - // (op 1165) BEGIN: TileTile - // (op 1165) {TileTile: ShiftL({Flatten[1]: v19:U32}, 1:U32)U32} - // (op 1165) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1165) value (Flatten[1]: VGPR Value: UInt32 x 1: v19) - // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 -v_lshlrev_b32 v18, 1, v19 // (op 1165) - // (op 1165) END: TileTile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1165): v19 - -// Allocated TileTile: 2 VGPRs (Value: UInt64) (op 1165): v20, v21 -v_mov_b32 v21, 0 // (op 1165) convert -v_mov_b32 v20, v18 // (op 1165) convert - // Freeing TileTile: 1 VGPR (Value: UInt32) (op 1165): v18 - - // (op 1165) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1165): v18 -v_lshrrev_b32 v18, 5, v1 // (op 1165) - // (op 1165) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1165): v19 -v_lshl_add_u32 v19, s3, 6, v18 // (op 1165) - // (op 1165) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1165): v18 - - // (op 1165) Multiply({Tile: v19:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 - // (op 1165) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = - // (op 1165) lhs (Tile: VGPR Value: UInt32 x 1: v19) - // (op 1165) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) -// Allocated : 2 VGPRs (Value: Int64) (op 1165): v22, v23 -v_mul_lo_u32 v23, v19, s23 // (op 1165) most significant: low of low * high - // (op 1165) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1165): v18 -v_mul_hi_u32 v18, v19, s22 // (op 1165) most significant: high of low * low -v_mul_lo_u32 v22, v19, s22 // (op 1165) least significant: low of low * low -v_add_u32 v23, v23, v18 // (op 1165) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1165): v18 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1165): v19 - - // (op 1165) BEGIN: Split - // (op 1165) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1165) lhs (TileTile: VGPR Value: UInt64 x 1: v[20:21]) - // (op 1165) rhs (VGPR Value: Int64 x 1: v[22:23]) -// Allocated DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 -// Allocated : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 -v_add_co_u32 v18, s[0:1], v20, v22 // (op 1165) least significant half -v_addc_co_u32 v19, s[0:1], v21, v23, s[0:1] // (op 1165) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1165): s0, s1 - - // (op 1165) ShiftL: dest (VGPR Value: UInt64 x 1: v[18:19]) = - // (op 1165) value (VGPR Value: UInt64 x 1: v[18:19]) - // (op 1165) shiftAmount (Literal Value: UInt32 x 0: 1) -v_lshlrev_b64 v[18:19], 1, v[18:19] // (op 1165) - // (op 1165) END: Split - // Freeing : 2 VGPRs (Value: Int64) (op 1165): v22, v23 - - // Freeing TileTile: 2 VGPRs (Value: UInt64) (op 1165): v20, v21 - - // (op 1074) Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165) END - // (op 1074) Assign VGPR 128:U64(1166) BEGIN - // (op 1166) Assign dim(507) = 128:U64 - // (op 1166) Assign stride expression - // (op 1074) Assign VGPR 128:U64(1166) END - // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) BEGIN - // (op 1167) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // (op 1167) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // (op 1167) Get arg Tensor_2_pointer - // (op 1167) Get arg Tensor_2_extent_2 - // (op 1167) reg expression - // (op 1167) reg expression - // (op 1167) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 - // (op 1167) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1167) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) - // (op 1167) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1167): s0, s1 -s_lshl_b64 s[0:1], s[8:9], 1 // (op 1167) - // (op 1167) reg expression -s_mov_b32 s36, s10 // (op 1167) reg expression -s_mov_b32 s37, s11 // (op 1167) reg expression -s_mov_b32 s38, s0 // (op 1167) reg expression -s_mov_b32 s39, 131072 // (op 1167) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1167): s0, s1 - - // (op 1074) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167) END - // (op 1074) NOP(1158) BEGIN - // (op 1158) generate({}) - // (op 1158) end: generate({}) - // (op 1074) NOP(1158) END - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) BEGIN - // (op 1172) Assign dim(509) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1172) Assign stride expression - // (op 1074) Tag 1172non referenced extraArgs = {Tensor_2_stride_1_12} - - // (op 1074) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172) END - // (op 1074) NOP(1159) BEGIN - // (op 1159) generate({}) - // (op 1159) end: generate({}) - // (op 1074) NOP(1159) END - // (op 1074) Assign VGPR 2:U64(1175) BEGIN - // (op 1175) Assign dim(511) = 2:U64 - // (op 1175) Assign stride expression - // (op 1074) Assign VGPR 2:U64(1175) END - // (op 1074) NOP(690) BEGIN - // (op 690) generate({}) - // (op 690) end: generate({}) - // (op 1074) NOP(690) END - // (op 1074) SetCoordinate(696) BEGIN - // (op 696) generate({}) - // (op 696) end: generate({}) - // (op 696) generate({1279}) - // (op 696) Scope(1279) BEGIN - // (op 1279) Lock Scope 1279 - // Lock Branch - // (op 1279) generate({1276}) - // (op 1279) NOP(1276) BEGIN - // (op 1276) generate({}) - // (op 1276) end: generate({}) - // (op 1279) NOP(1276) END - // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) BEGIN - // (op 1283) Assign dim(542) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 542: s**UNALLOCATED** - // (op 1283) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag542: SGPR Value: UInt32 x 1: (unallocated) - // (op 1283) reg expression - // (op 1283) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 -v_and_b32 v20, -32, v1 // (op 1283) - // (op 1283) BEGIN: Tile[1] - // (op 1283) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 -v_sub_u32 v21, v1, v20 // (op 1283) - // (op 1283) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1283): v20 - - // (op 1283) BEGIN: Flatten - // (op 1283) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1283) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1283) - // (op 1283) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1283): v21 - - // (op 1283) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1283) - // (op 1283) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1283) - // (op 1283) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1283): v21 - - // (op 1283) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1283) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1283) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1283) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1283): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1283) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1283): v22 - -// Allocated DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1283) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1283): v20 - - // (op 1279) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283) END - // (op 1279) Assign VGPR 1024:U32(1284) BEGIN - // (op 1284) Assign dim(543) = 1024:U32 - // (op 1284) Assign stride expression - // (op 1279) Assign VGPR 1024:U32(1284) END - // (op 1279) NOP(1277) BEGIN - // (op 1277) generate({}) - // (op 1277) end: generate({}) - // (op 1279) NOP(1277) END - // (op 1279) Assign VGPR 2:U32(1288) BEGIN - // (op 1288) Assign dim(545) = 2:U32 - // (op 1288) Assign stride expression - // (op 1279) Assign VGPR 2:U32(1288) END - // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) BEGIN - // (op 1023) GEN: LoadTileDirect2LDS - // (op 1023) GEN: loadMacroTileDirect2LDS OP 1023 LDS 21 MacroTile 7 - // (op 1023) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1023) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) - // (op 1023) Get arg Tensor_2_stride_1_12 - // (op 1023) reg expression - // (op 1023) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1023) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1023) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 -s_lshl_b64 s[16:17], s[22:23], 3 // (op 1023) - // (op 1023) convert - // (op 1023) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1023) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1023) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1023) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1023) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1023): s16, s17 - - // (op 1023) Generate 2:U64 into nullptr - // (op 1023) Generate 1024:U32 into nullptr - // (op 1023) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 0 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 -v_mov_b64 v[22:23], v[16:17] // (op 1023) - // (op 1023) Generate Add(0:U32, {DataFlowTag542: s0:U32})U32 into nullptr - // (op 1023) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1023) Generate {DataFlowTag542: s0:U32} into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s0 // (op 1023) reg expression -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 268 (current 193) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 272 (current 197) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 276 (current 201) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 280 (current 205) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 -// VMEM: Expected complete at 344 (current 269) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 348 (current 273) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 352 (current 277) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1023) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1023) reg expression - // (op 1023) reg expression - // (op 1023) Add(v[22:23]:U64, v20:R)U64 - // (op 1023) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1023) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1023) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1023) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1023) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1023): s16, s17 - - // (op 1023) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1023) reg expression - // (op 1023) Add(m0:U32, 1024:U32)U32 - // (op 1023) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1023) - // (op 1023) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], 0 offen offset: 0 lds // (op 1023) Load value direct to lds -// VMEM: Expected complete at 356 (current 281) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1023): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1023): v22, v23 - - // (op 1279) LoadTileDirect2LDS Value: Halfx2(1023) END - // (op 1279) Deallocate{}(1895) BEGIN - // (op 1895) Deallocate 544 - // Deleting tag 544 - // (op 1895) Deallocate 543 - // Deleting tag 543 - // (op 1895) Deallocate 542 - // Freeing DataFlowTag542: 1 SGPR (Value: UInt32) (op 1283): s0 - - // Deleting tag 542 - // (op 1895) Deallocate 545 - // Deleting tag 545 - // (op 1279) Deallocate{}(1895) END - // (op 1279) end: generate({1276}) - // (op 1279) Unlock Scope 1279 - // Unlock None - // (op 696) Scope(1279) END - // (op 696) end: generate({1279}) - // (op 1074) SetCoordinate(696) END - // (op 1074) SetCoordinate(699) BEGIN - // (op 699) generate({}) - // (op 699) end: generate({}) - // (op 699) generate({1227}) - // (op 699) Scope(1227) BEGIN - // (op 1227) Lock Scope 1227 - // Lock Branch - // (op 1227) generate({1224}) - // (op 1227) NOP(1224) BEGIN - // (op 1224) generate({}) - // (op 1224) end: generate({}) - // (op 1227) NOP(1224) END - // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) BEGIN - // (op 1231) Assign dim(526) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 526: s**UNALLOCATED** - // (op 1231) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag526: SGPR Value: UInt32 x 1: (unallocated) - // (op 1231) reg expression - // (op 1231) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 -v_and_b32 v20, -32, v1 // (op 1231) - // (op 1231) BEGIN: Tile[1] - // (op 1231) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 -v_sub_u32 v21, v1, v20 // (op 1231) - // (op 1231) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1231): v20 - - // (op 1231) BEGIN: Flatten - // (op 1231) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1231) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1231) - // (op 1231) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1231): v21 - - // (op 1231) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1231) - // (op 1231) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1231) - // (op 1231) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1231): v21 - - // (op 1231) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1231) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1231) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1231) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1231): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1231) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1231): v22 - -// Allocated DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1231) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1231): v20 - - // (op 1227) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231) END - // (op 1227) Assign VGPR 1024:U32(1232) BEGIN - // (op 1232) Assign dim(527) = 1024:U32 - // (op 1232) Assign stride expression - // (op 1227) Assign VGPR 1024:U32(1232) END - // (op 1227) NOP(1225) BEGIN - // (op 1225) generate({}) - // (op 1225) end: generate({}) - // (op 1227) NOP(1225) END - // (op 1227) Assign VGPR 2:U32(1236) BEGIN - // (op 1236) Assign dim(529) = 2:U32 - // (op 1236) Assign stride expression - // (op 1227) Assign VGPR 2:U32(1236) END - // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) BEGIN - // (op 1028) GEN: LoadTileDirect2LDS - // (op 1028) GEN: loadMacroTileDirect2LDS OP 1028 LDS 13 MacroTile 6 - // (op 1028) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1028) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) - // (op 1028) Get arg Tensor_0_stride_0_9 - // (op 1028) reg expression - // (op 1028) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1028) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1028) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 -s_lshl_b64 s[16:17], s[18:19], 3 // (op 1028) - // (op 1028) convert - // (op 1028) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1028) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1028) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1028) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1028) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1028): s16, s17 - - // (op 1028) Generate 2:U64 into nullptr - // (op 1028) Generate 1024:U32 into nullptr - // (op 1028) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 8192 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 -v_mov_b64 v[22:23], v[12:13] // (op 1028) - // (op 1028) Generate Add(8192:U32, {DataFlowTag526: s0:U32})U32 into nullptr - // (op 1028) reg expression - // (op 1028) Add(8192:U32, {DataFlowTag526: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1028): s1 -s_add_u32 s1, 8192, s0 // (op 1028) - // (op 1028) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1028) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1028) reg expression -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected stall of 50. CBNW: 4, Inc: 4 -// VMEM: Expected complete at 420 (current 345) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 424 (current 349) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 428 (current 353) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 432 (current 357) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 -// VMEM: Expected complete at 496 (current 421) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 500 (current 425) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 504 (current 429) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 1028) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1028) reg expression - // (op 1028) reg expression - // (op 1028) Add(v[22:23]:U64, v20:R)U64 - // (op 1028) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1028) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1028) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 -v_add_co_u32 v22, s[16:17], v22, v20 // (op 1028) least significant half -v_addc_co_u32 v23, s[16:17], 0, v23, s[16:17] // (op 1028) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1028): s16, s17 - - // (op 1028) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1028) reg expression - // (op 1028) Add(m0:U32, 1024:U32)U32 - // (op 1028) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1028) - // (op 1028) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], 0 offen offset: 0 lds // (op 1028) Load value direct to lds -// VMEM: Expected complete at 508 (current 433) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1028): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1028): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1028): s1 - - // (op 1227) LoadTileDirect2LDS Value: Halfx2(1028) END - // (op 1227) Deallocate{}(1897) BEGIN - // (op 1897) Deallocate 529 - // Deleting tag 529 - // (op 1897) Deallocate 526 - // Freeing DataFlowTag526: 1 SGPR (Value: UInt32) (op 1231): s0 - - // Deleting tag 526 - // (op 1897) Deallocate 528 - // Deleting tag 528 - // (op 1897) Deallocate 527 - // Deleting tag 527 - // (op 1227) Deallocate{}(1897) END - // (op 1227) end: generate({1224}) - // (op 1227) Unlock Scope 1227 - // Unlock None - // (op 699) Scope(1227) END - // (op 699) end: generate({1227}) - // (op 1074) SetCoordinate(699) END - // (op 1074) SetCoordinate(702) BEGIN - // (op 702) generate({}) - // (op 702) end: generate({}) - // (op 702) generate({1391}) - // (op 702) Scope(1391) BEGIN - // (op 1391) Lock Scope 1391 - // Lock Branch - // (op 1391) generate({1388}) - // (op 1391) NOP(1388) BEGIN - // (op 1388) generate({}) - // (op 1388) end: generate({}) - // (op 1391) NOP(1388) END - // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) BEGIN - // (op 1395) Assign dim(576) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 576: s**UNALLOCATED** - // (op 1395) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag576: SGPR Value: UInt32 x 1: (unallocated) - // (op 1395) reg expression - // (op 1395) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 -v_and_b32 v20, -32, v1 // (op 1395) - // (op 1395) BEGIN: Tile[1] - // (op 1395) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 -v_sub_u32 v21, v1, v20 // (op 1395) - // (op 1395) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1395): v20 - - // (op 1395) BEGIN: Flatten - // (op 1395) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1395) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1395) - // (op 1395) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1395): v21 - - // (op 1395) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1395) - // (op 1395) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1395) - // (op 1395) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1395): v21 - - // (op 1395) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1395) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1395) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1395) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1395): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1395) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1395): v22 - -// Allocated DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1395) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1395): v20 - - // (op 1391) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395) END - // (op 1391) Assign VGPR 1024:U32(1396) BEGIN - // (op 1396) Assign dim(577) = 1024:U32 - // (op 1396) Assign stride expression - // (op 1391) Assign VGPR 1024:U32(1396) END - // (op 1391) NOP(1389) BEGIN - // (op 1389) generate({}) - // (op 1389) end: generate({}) - // (op 1391) NOP(1389) END - // (op 1391) Assign VGPR 2:U32(1400) BEGIN - // (op 1400) Assign dim(579) = 2:U32 - // (op 1400) Assign stride expression - // (op 1391) Assign VGPR 2:U32(1400) END - // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) BEGIN - // (op 1033) GEN: LoadTileDirect2LDS - // (op 1033) GEN: loadMacroTileDirect2LDS OP 1033 LDS 360 MacroTile 358 - // (op 1033) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1033) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) - // (op 1033) Get arg Tensor_2_stride_1_12 - // (op 1033) reg expression - // (op 1033) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1033) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1033) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 -s_lshl_b64 s[16:17], s[22:23], 3 // (op 1033) - // (op 1033) convert - // (op 1033) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1033) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1033) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1033) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1033) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1033): s16, s17 - - // (op 1033) Generate 2:U64 into nullptr - // (op 1033) Generate 1024:U32 into nullptr - // (op 1033) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 16384 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 -v_mov_b64 v[22:23], v[16:17] // (op 1033) - // (op 1033) Generate Add(16384:U32, {DataFlowTag576: s0:U32})U32 into nullptr - // (op 1033) reg expression - // (op 1033) Add(16384:U32, {DataFlowTag576: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1033): s1 -s_add_u32 s1, 16384, s0 // (op 1033) - // (op 1033) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1033) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1033) reg expression - // (op 1033) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 128 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s16 -s_mov_b32 s16, 128 // (op 1033) call() -// 128 is not a supported value! -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 12, Inc: 4 -// VMEM: Expected complete at 572 (current 497) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 576 (current 501) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 580 (current 505) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 584 (current 509) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 16, Inc: 4 -// VMEM: Expected complete at 648 (current 573) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 652 (current 577) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 656 (current 581) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 1033) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1033) reg expression - // (op 1033) reg expression - // (op 1033) Add(v[22:23]:U64, v20:R)U64 - // (op 1033) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1033) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1033) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1033) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1033) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1033): s40, s41 - - // (op 1033) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1033) reg expression - // (op 1033) Add(m0:U32, 1024:U32)U32 - // (op 1033) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1033) - // (op 1033) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1033) Load value direct to lds -// VMEM: Expected complete at 660 (current 585) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1033): s16 - - // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1033): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1033): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1033): s1 - - // (op 1391) LoadTileDirect2LDS Value: Halfx2(1033) END - // (op 1391) Deallocate{}(1899) BEGIN - // (op 1899) Deallocate 578 - // Deleting tag 578 - // (op 1899) Deallocate 579 - // Deleting tag 579 - // (op 1899) Deallocate 576 - // Freeing DataFlowTag576: 1 SGPR (Value: UInt32) (op 1395): s0 - - // Deleting tag 576 - // (op 1899) Deallocate 577 - // Deleting tag 577 - // (op 1391) Deallocate{}(1899) END - // (op 1391) end: generate({1388}) - // (op 1391) Unlock Scope 1391 - // Unlock None - // (op 702) Scope(1391) END - // (op 702) end: generate({1391}) - // (op 1074) SetCoordinate(702) END - // (op 1074) SetCoordinate(705) BEGIN - // (op 705) generate({}) - // (op 705) end: generate({}) - // (op 705) generate({1352}) - // (op 705) Scope(1352) BEGIN - // (op 1352) Lock Scope 1352 - // Lock Branch - // (op 1352) generate({1349}) - // (op 1352) NOP(1349) BEGIN - // (op 1349) generate({}) - // (op 1349) end: generate({}) - // (op 1352) NOP(1349) END - // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) BEGIN - // (op 1356) Assign dim(564) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 564: s**UNALLOCATED** - // (op 1356) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag564: SGPR Value: UInt32 x 1: (unallocated) - // (op 1356) reg expression - // (op 1356) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 -v_and_b32 v20, -32, v1 // (op 1356) - // (op 1356) BEGIN: Tile[1] - // (op 1356) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 -v_sub_u32 v21, v1, v20 // (op 1356) - // (op 1356) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1356): v20 - - // (op 1356) BEGIN: Flatten - // (op 1356) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1356) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1356) - // (op 1356) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1356): v21 - - // (op 1356) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1356) - // (op 1356) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1356) - // (op 1356) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1356): v21 - - // (op 1356) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1356) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1356) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1356) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1356): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1356) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1356): v22 - -// Allocated DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1356) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1356): v20 - - // (op 1352) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356) END - // (op 1352) Assign VGPR 1024:U32(1357) BEGIN - // (op 1357) Assign dim(565) = 1024:U32 - // (op 1357) Assign stride expression - // (op 1352) Assign VGPR 1024:U32(1357) END - // (op 1352) NOP(1350) BEGIN - // (op 1350) generate({}) - // (op 1350) end: generate({}) - // (op 1352) NOP(1350) END - // (op 1352) Assign VGPR 2:U32(1361) BEGIN - // (op 1361) Assign dim(567) = 2:U32 - // (op 1361) Assign stride expression - // (op 1352) Assign VGPR 2:U32(1361) END - // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) BEGIN - // (op 1035) GEN: LoadTileDirect2LDS - // (op 1035) GEN: loadMacroTileDirect2LDS OP 1035 LDS 356 MacroTile 354 - // (op 1035) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1035) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) - // (op 1035) Get arg Tensor_0_stride_0_9 - // (op 1035) reg expression - // (op 1035) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1035) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1035) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 -s_lshl_b64 s[16:17], s[18:19], 3 // (op 1035) - // (op 1035) convert - // (op 1035) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1035) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1035) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1035) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1035) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1035): s16, s17 - - // (op 1035) Generate 2:U64 into nullptr - // (op 1035) Generate 1024:U32 into nullptr - // (op 1035) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 24576 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 -v_mov_b64 v[22:23], v[12:13] // (op 1035) - // (op 1035) Generate Add(24576:U32, {DataFlowTag564: s0:U32})U32 into nullptr - // (op 1035) reg expression - // (op 1035) Add(24576:U32, {DataFlowTag564: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1035): s1 -s_add_u32 s1, 24576, s0 // (op 1035) - // (op 1035) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1035) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1035) reg expression - // (op 1035) Generate 128:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 128 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s16 -s_mov_b32 s16, 128 // (op 1035) call() -// 128 is not a supported value! -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 20, Inc: 4 -// VMEM: Expected complete at 724 (current 649) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 728 (current 653) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 732 (current 657) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 736 (current 661) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 24, Inc: 4 -// VMEM: Expected complete at 800 (current 725) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 804 (current 729) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 808 (current 733) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 1035) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1035) reg expression - // (op 1035) reg expression - // (op 1035) Add(v[22:23]:U64, v20:R)U64 - // (op 1035) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1035) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1035) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1035) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1035) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1035): s40, s41 - - // (op 1035) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1035) reg expression - // (op 1035) Add(m0:U32, 1024:U32)U32 - // (op 1035) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1035) - // (op 1035) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1035) Load value direct to lds -// VMEM: Expected complete at 812 (current 737) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1035): s16 - - // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1035): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1035): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1035): s1 - - // (op 1352) LoadTileDirect2LDS Value: Halfx2(1035) END - // (op 1352) Deallocate{}(1901) BEGIN - // (op 1901) Deallocate 565 - // Deleting tag 565 - // (op 1901) Deallocate 567 - // Deleting tag 567 - // (op 1901) Deallocate 564 - // Freeing DataFlowTag564: 1 SGPR (Value: UInt32) (op 1356): s0 - - // Deleting tag 564 - // (op 1901) Deallocate 566 - // Deleting tag 566 - // (op 1352) Deallocate{}(1901) END - // (op 1352) end: generate({1349}) - // (op 1352) Unlock Scope 1352 - // Unlock None - // (op 705) Scope(1352) END - // (op 705) end: generate({1352}) - // (op 1074) SetCoordinate(705) END - // (op 1074) SetCoordinate(708) BEGIN - // (op 708) generate({}) - // (op 708) end: generate({}) - // (op 708) generate({1469}) - // (op 708) Scope(1469) BEGIN - // (op 1469) Lock Scope 1469 - // Lock Branch - // (op 1469) generate({1466}) - // (op 1469) NOP(1466) BEGIN - // (op 1466) generate({}) - // (op 1466) end: generate({}) - // (op 1469) NOP(1466) END - // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) BEGIN - // (op 1473) Assign dim(600) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 600: s**UNALLOCATED** - // (op 1473) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag600: SGPR Value: UInt32 x 1: (unallocated) - // (op 1473) reg expression - // (op 1473) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 -v_and_b32 v20, -32, v1 // (op 1473) - // (op 1473) BEGIN: Tile[1] - // (op 1473) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 -v_sub_u32 v21, v1, v20 // (op 1473) - // (op 1473) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1473): v20 - - // (op 1473) BEGIN: Flatten - // (op 1473) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1473) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1473) - // (op 1473) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1473): v21 - - // (op 1473) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1473) - // (op 1473) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1473) - // (op 1473) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1473): v21 - - // (op 1473) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1473) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1473) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1473) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1473): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1473) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1473): v22 - -// Allocated DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1473) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1473): v20 - - // (op 1469) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473) END - // (op 1469) Assign VGPR 1024:U32(1474) BEGIN - // (op 1474) Assign dim(601) = 1024:U32 - // (op 1474) Assign stride expression - // (op 1469) Assign VGPR 1024:U32(1474) END - // (op 1469) NOP(1467) BEGIN - // (op 1467) generate({}) - // (op 1467) end: generate({}) - // (op 1469) NOP(1467) END - // (op 1469) Assign VGPR 2:U32(1478) BEGIN - // (op 1478) Assign dim(603) = 2:U32 - // (op 1478) Assign stride expression - // (op 1469) Assign VGPR 2:U32(1478) END - // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) BEGIN - // (op 1037) GEN: LoadTileDirect2LDS - // (op 1037) GEN: loadMacroTileDirect2LDS OP 1037 LDS 400 MacroTile 398 - // (op 1037) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1037) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) - // (op 1037) Get arg Tensor_2_stride_1_12 - // (op 1037) reg expression - // (op 1037) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1037) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1037) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 -s_lshl_b64 s[16:17], s[22:23], 3 // (op 1037) - // (op 1037) convert - // (op 1037) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1037) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1037) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1037) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1037) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1037): s16, s17 - - // (op 1037) Generate 2:U64 into nullptr - // (op 1037) Generate 1024:U32 into nullptr - // (op 1037) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 32768 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 -v_mov_b64 v[22:23], v[16:17] // (op 1037) - // (op 1037) Generate Add(32768:U32, {DataFlowTag600: s0:U32})U32 into nullptr - // (op 1037) reg expression - // (op 1037) Add(32768:U32, {DataFlowTag600: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1037): s1 -s_add_u32 s1, 32768, s0 // (op 1037) - // (op 1037) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1037) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1037) reg expression - // (op 1037) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 256 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s16 -s_mov_b32 s16, 256 // (op 1037) call() -// 256 is not a supported value! -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 28, Inc: 4 -// VMEM: Expected complete at 876 (current 801) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 880 (current 805) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 884 (current 809) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 888 (current 813) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 32, Inc: 4 -// VMEM: Expected complete at 952 (current 877) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 956 (current 881) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 960 (current 885) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1037) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1037) reg expression - // (op 1037) reg expression - // (op 1037) Add(v[22:23]:U64, v20:R)U64 - // (op 1037) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1037) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1037) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1037) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1037) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1037): s40, s41 - - // (op 1037) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1037) reg expression - // (op 1037) Add(m0:U32, 1024:U32)U32 - // (op 1037) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1037) - // (op 1037) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1037) Load value direct to lds -// VMEM: Expected complete at 964 (current 889) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1037): s16 - - // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1037): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1037): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1037): s1 - - // (op 1469) LoadTileDirect2LDS Value: Halfx2(1037) END - // (op 1469) Deallocate{}(1903) BEGIN - // (op 1903) Deallocate 600 - // Freeing DataFlowTag600: 1 SGPR (Value: UInt32) (op 1473): s0 - - // Deleting tag 600 - // (op 1903) Deallocate 603 - // Deleting tag 603 - // (op 1903) Deallocate 601 - // Deleting tag 601 - // (op 1903) Deallocate 602 - // Deleting tag 602 - // (op 1469) Deallocate{}(1903) END - // (op 1469) end: generate({1466}) - // (op 1469) Unlock Scope 1469 - // Unlock None - // (op 708) Scope(1469) END - // (op 708) end: generate({1469}) - // (op 1074) SetCoordinate(708) END - // (op 1074) SetCoordinate(711) BEGIN - // (op 711) generate({}) - // (op 711) end: generate({}) - // (op 711) generate({1430}) - // (op 711) Scope(1430) BEGIN - // (op 1430) Lock Scope 1430 - // Lock Branch - // (op 1430) generate({1427}) - // (op 1430) NOP(1427) BEGIN - // (op 1427) generate({}) - // (op 1427) end: generate({}) - // (op 1430) NOP(1427) END - // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) BEGIN - // (op 1434) Assign dim(588) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 588: s**UNALLOCATED** - // (op 1434) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag588: SGPR Value: UInt32 x 1: (unallocated) - // (op 1434) reg expression - // (op 1434) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 -v_and_b32 v20, -32, v1 // (op 1434) - // (op 1434) BEGIN: Tile[1] - // (op 1434) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 -v_sub_u32 v21, v1, v20 // (op 1434) - // (op 1434) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1434): v20 - - // (op 1434) BEGIN: Flatten - // (op 1434) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1434) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1434) - // (op 1434) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1434): v21 - - // (op 1434) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1434) - // (op 1434) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1434) - // (op 1434) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1434): v21 - - // (op 1434) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1434) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1434) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1434) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1434): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1434) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1434): v22 - -// Allocated DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1434) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1434): v20 - - // (op 1430) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434) END - // (op 1430) Assign VGPR 1024:U32(1435) BEGIN - // (op 1435) Assign dim(589) = 1024:U32 - // (op 1435) Assign stride expression - // (op 1430) Assign VGPR 1024:U32(1435) END - // (op 1430) NOP(1428) BEGIN - // (op 1428) generate({}) - // (op 1428) end: generate({}) - // (op 1430) NOP(1428) END - // (op 1430) Assign VGPR 2:U32(1439) BEGIN - // (op 1439) Assign dim(591) = 2:U32 - // (op 1439) Assign stride expression - // (op 1430) Assign VGPR 2:U32(1439) END - // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) BEGIN - // (op 1039) GEN: LoadTileDirect2LDS - // (op 1039) GEN: loadMacroTileDirect2LDS OP 1039 LDS 396 MacroTile 394 - // (op 1039) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1039) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) - // (op 1039) Get arg Tensor_0_stride_0_9 - // (op 1039) reg expression - // (op 1039) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1039) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1039) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 -s_lshl_b64 s[16:17], s[18:19], 3 // (op 1039) - // (op 1039) convert - // (op 1039) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1039) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1039) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1039) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1039) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1039): s16, s17 - - // (op 1039) Generate 2:U64 into nullptr - // (op 1039) Generate 1024:U32 into nullptr - // (op 1039) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 40960 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 -v_mov_b64 v[22:23], v[12:13] // (op 1039) - // (op 1039) Generate Add(40960:U32, {DataFlowTag588: s0:U32})U32 into nullptr - // (op 1039) reg expression - // (op 1039) Add(40960:U32, {DataFlowTag588: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1039): s1 -s_add_u32 s1, 40960, s0 // (op 1039) - // (op 1039) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1039) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1039) reg expression - // (op 1039) Generate 256:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 256 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s16 -s_mov_b32 s16, 256 // (op 1039) call() -// 256 is not a supported value! -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 36, Inc: 4 -// VMEM: Expected complete at 1028 (current 953) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1032 (current 957) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1036 (current 961) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1040 (current 965) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 40, Inc: 4 -// VMEM: Expected complete at 1104 (current 1029) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1108 (current 1033) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1112 (current 1037) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1039) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1039) reg expression - // (op 1039) reg expression - // (op 1039) Add(v[22:23]:U64, v20:R)U64 - // (op 1039) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1039) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1039) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1039) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1039) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1039): s40, s41 - - // (op 1039) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1039) reg expression - // (op 1039) Add(m0:U32, 1024:U32)U32 - // (op 1039) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1039) - // (op 1039) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[32:35], s16 offen offset: 0 lds // (op 1039) Load value direct to lds -// VMEM: Expected complete at 1116 (current 1041) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1039): s16 - - // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1039): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1039): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1039): s1 - - // (op 1430) LoadTileDirect2LDS Value: Halfx2(1039) END - // (op 1430) Deallocate{}(1905) BEGIN - // (op 1905) Deallocate 588 - // Freeing DataFlowTag588: 1 SGPR (Value: UInt32) (op 1434): s0 - - // Deleting tag 588 - // (op 1905) Deallocate 591 - // Deleting tag 591 - // (op 1905) Deallocate 589 - // Deleting tag 589 - // (op 1905) Deallocate 590 - // Deleting tag 590 - // (op 1430) Deallocate{}(1905) END - // (op 1430) end: generate({1427}) - // (op 1430) Unlock Scope 1430 - // Unlock None - // (op 711) Scope(1430) END - // (op 711) end: generate({1430}) - // (op 1074) SetCoordinate(711) END - // (op 1074) SetCoordinate(714) BEGIN - // (op 714) generate({}) - // (op 714) end: generate({}) - // (op 714) generate({1547}) - // (op 714) Scope(1547) BEGIN - // (op 1547) Lock Scope 1547 - // Lock Branch - // (op 1547) generate({1544}) - // (op 1547) NOP(1544) BEGIN - // (op 1544) generate({}) - // (op 1544) end: generate({}) - // (op 1547) NOP(1544) END - // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) BEGIN - // (op 1551) Assign dim(624) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 624: s**UNALLOCATED** - // (op 1551) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag624: SGPR Value: UInt32 x 1: (unallocated) - // (op 1551) reg expression - // (op 1551) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 -v_and_b32 v20, -32, v1 // (op 1551) - // (op 1551) BEGIN: Tile[1] - // (op 1551) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v20:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 -v_sub_u32 v21, v1, v20 // (op 1551) - // (op 1551) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1551): v20 - - // (op 1551) BEGIN: Flatten - // (op 1551) {Flatten: ShiftL({Tile[1]: v21:U32}, 1:U32)U32} - // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1551) value (Tile[1]: VGPR Value: UInt32 x 1: v21) - // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 -v_lshlrev_b32 v20, 1, v21 // (op 1551) - // (op 1551) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1551): v21 - - // (op 1551) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v21 -v_lshrrev_b32 v21, 5, v1 // (op 1551) - // (op 1551) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v22 -v_lshl_add_u32 v22, v21, 6, v20 // (op 1551) - // (op 1551) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v20 - - // Freeing : 1 VGPR (Value: UInt32) (op 1551): v21 - - // (op 1551) ShiftL({Flatten: v22:U32}, 1:U32)U32 - // (op 1551) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1551) value (Flatten: VGPR Value: UInt32 x 1: v22) - // (op 1551) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1551): v20 -v_lshlrev_b32 v20, 1, v22 // (op 1551) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1551): v22 - -// Allocated DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s0 -s_nop 0 -v_readfirstlane_b32 s0, v20 // (op 1551) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1551): v20 - - // (op 1547) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551) END - // (op 1547) Assign VGPR 1024:U32(1552) BEGIN - // (op 1552) Assign dim(625) = 1024:U32 - // (op 1552) Assign stride expression - // (op 1547) Assign VGPR 1024:U32(1552) END - // (op 1547) NOP(1545) BEGIN - // (op 1545) generate({}) - // (op 1545) end: generate({}) - // (op 1547) NOP(1545) END - // (op 1547) Assign VGPR 2:U32(1556) BEGIN - // (op 1556) Assign dim(627) = 2:U32 - // (op 1556) Assign stride expression - // (op 1547) Assign VGPR 2:U32(1556) END - // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) BEGIN - // (op 1041) GEN: LoadTileDirect2LDS - // (op 1041) GEN: loadMacroTileDirect2LDS OP 1041 LDS 440 MacroTile 438 - // (op 1041) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1041) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride503: VGPR Value: UInt64 x 1: (unallocated) - // (op 1041) Get arg Tensor_2_stride_1_12 - // (op 1041) reg expression - // (op 1041) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1041) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1041) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 -s_lshl_b64 s[16:17], s[22:23], 3 // (op 1041) - // (op 1041) convert - // (op 1041) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1041) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1041) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1041) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 -v_lshlrev_b64 v[20:21], 1, s[16:17] // (op 1041) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1041): s16, s17 - - // (op 1041) Generate 2:U64 into nullptr - // (op 1041) Generate 1024:U32 into nullptr - // (op 1041) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 49152 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride503: VGPR Value: UInt64 x 1: v[20:21] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 -v_mov_b64 v[22:23], v[16:17] // (op 1041) - // (op 1041) Generate Add(49152:U32, {DataFlowTag624: s0:U32})U32 into nullptr - // (op 1041) reg expression - // (op 1041) Add(49152:U32, {DataFlowTag624: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1041): s1 -s_add_u32 s1, 49152, s0 // (op 1041) - // (op 1041) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride503: v[20:21]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1041) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1041) reg expression - // (op 1041) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 384 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s16 -s_mov_b32 s16, 384 // (op 1041) call() -// 384 is not a supported value! -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 44, Inc: 4 -// VMEM: Expected complete at 1180 (current 1105) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1184 (current 1109) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1188 (current 1113) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1192 (current 1117) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 48, Inc: 4 -// VMEM: Expected complete at 1256 (current 1181) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1260 (current 1185) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1264 (current 1189) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1041) Generate Add(v[22:23]:U64, v20:R)U64 into VGPR Value: UInt64 x 1: v[22:23] - // (op 1041) reg expression - // (op 1041) reg expression - // (op 1041) Add(v[22:23]:U64, v20:R)U64 - // (op 1041) Add: dest (VGPR Value: UInt64 x 1: v[22:23]) = - // (op 1041) lhs (VGPR Value: UInt64 x 1: v[22:23]) - // (op 1041) rhs (VGPR Value: Raw32 x 1: v20) -// Allocated : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 -v_add_co_u32 v22, s[40:41], v22, v20 // (op 1041) least significant half -v_addc_co_u32 v23, s[40:41], 0, v23, s[40:41] // (op 1041) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1041): s40, s41 - - // (op 1041) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1041) reg expression - // (op 1041) Add(m0:U32, 1024:U32)U32 - // (op 1041) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1041) - // (op 1041) Expression temporary in special register - // Unlock None -buffer_load_dword v22, s[36:39], s16 offen offset: 0 lds // (op 1041) Load value direct to lds -// VMEM: Expected complete at 1268 (current 1193) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1041): s16 - - // Freeing Stride503: 2 VGPRs (Value: UInt64) (op 1041): v20, v21 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1041): v22, v23 - - // Freeing : 1 SGPR (Value: UInt32) (op 1041): s1 - - // (op 1547) LoadTileDirect2LDS Value: Halfx2(1041) END - // (op 1547) Deallocate{}(1907) BEGIN - // (op 1907) Deallocate 626 - // Deleting tag 626 - // (op 1907) Deallocate 624 - // Freeing DataFlowTag624: 1 SGPR (Value: UInt32) (op 1551): s0 - - // Deleting tag 624 - // (op 1907) Deallocate 627 - // Deleting tag 627 - // (op 1907) Deallocate 625 - // Deleting tag 625 - // (op 1547) Deallocate{}(1907) END - // (op 1547) end: generate({1544}) - // (op 1547) Unlock Scope 1547 - // Unlock None - // (op 714) Scope(1547) END - // (op 714) end: generate({1547}) - // (op 1074) SetCoordinate(714) END - // (op 1074) Deallocate{}(1871) BEGIN - // (op 1871) Deallocate 504 - // Deleting tag 504 - // (op 1871) Deallocate 503 - // Deleting tag 503 - // (op 1871) Deallocate 502 - // Freeing DataFlowTag502: 2 VGPRs (Value: UInt64) (op 1146): v16, v17 - - // Deleting tag 502 - // (op 1871) Deallocate 505 - // Deleting tag 505 - // (op 1871) Deallocate 501 - // Deleting tag 501 - // (op 1074) Deallocate{}(1871) END - // (op 1074) SetCoordinate(717) BEGIN - // (op 717) generate({}) - // (op 717) end: generate({}) - // (op 717) generate({1508}) - // (op 717) Scope(1508) BEGIN - // (op 1508) Lock Scope 1508 - // Lock Branch - // (op 1508) generate({1505}) - // (op 1508) NOP(1505) BEGIN - // (op 1505) generate({}) - // (op 1505) end: generate({}) - // (op 1508) NOP(1505) END - // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) BEGIN - // (op 1512) Assign dim(612) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 612: s**UNALLOCATED** - // (op 1512) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag612: SGPR Value: UInt32 x 1: (unallocated) - // (op 1512) reg expression - // (op 1512) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 -v_and_b32 v16, -32, v1 // (op 1512) - // (op 1512) BEGIN: Tile[1] - // (op 1512) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 -v_sub_u32 v17, v1, v16 // (op 1512) - // (op 1512) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1512): v16 - - // (op 1512) BEGIN: Flatten - // (op 1512) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} - // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1512) value (Tile[1]: VGPR Value: UInt32 x 1: v17) - // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 -v_lshlrev_b32 v16, 1, v17 // (op 1512) - // (op 1512) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1512): v17 - - // (op 1512) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v17 -v_lshrrev_b32 v17, 5, v1 // (op 1512) - // (op 1512) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v20 -v_lshl_add_u32 v20, v17, 6, v16 // (op 1512) - // (op 1512) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v16 - - // Freeing : 1 VGPR (Value: UInt32) (op 1512): v17 - - // (op 1512) ShiftL({Flatten: v20:U32}, 1:U32)U32 - // (op 1512) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1512) value (Flatten: VGPR Value: UInt32 x 1: v20) - // (op 1512) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1512): v16 -v_lshlrev_b32 v16, 1, v20 // (op 1512) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1512): v20 - -// Allocated DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s0 -s_nop 0 -v_readfirstlane_b32 s0, v16 // (op 1512) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1512): v16 - - // (op 1508) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512) END - // (op 1508) Assign VGPR 1024:U32(1513) BEGIN - // (op 1513) Assign dim(613) = 1024:U32 - // (op 1513) Assign stride expression - // (op 1508) Assign VGPR 1024:U32(1513) END - // (op 1508) NOP(1506) BEGIN - // (op 1506) generate({}) - // (op 1506) end: generate({}) - // (op 1508) NOP(1506) END - // (op 1508) Assign VGPR 2:U32(1517) BEGIN - // (op 1517) Assign dim(615) = 2:U32 - // (op 1517) Assign stride expression - // (op 1508) Assign VGPR 2:U32(1517) END - // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) BEGIN - // (op 1043) GEN: LoadTileDirect2LDS - // (op 1043) GEN: loadMacroTileDirect2LDS OP 1043 LDS 436 MacroTile 434 - // (op 1043) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1043) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride484: VGPR Value: UInt64 x 1: (unallocated) - // (op 1043) Get arg Tensor_0_stride_0_9 - // (op 1043) reg expression - // (op 1043) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1043) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1043) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 -s_lshl_b64 s[16:17], s[18:19], 3 // (op 1043) - // (op 1043) convert - // (op 1043) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 1043) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1043) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 1043) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 -v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 1043) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1043): s16, s17 - - // (op 1043) Generate 2:U64 into nullptr - // (op 1043) Generate 1024:U32 into nullptr - // (op 1043) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 57344 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride484: VGPR Value: UInt64 x 1: v[16:17] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 -v_mov_b64 v[20:21], v[12:13] // (op 1043) - // (op 1043) Generate Add(57344:U32, {DataFlowTag612: s0:U32})U32 into nullptr - // (op 1043) reg expression - // (op 1043) Add(57344:U32, {DataFlowTag612: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1043): s1 -s_add_u32 s1, 57344, s0 // (op 1043) - // (op 1043) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride484: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1043) Generate s1:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 1043) reg expression - // (op 1043) Generate 384:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 384 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s16 -s_mov_b32 s16, 384 // (op 1043) call() -// 384 is not a supported value! -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected stall of 49. CBNW: 52, Inc: 4 -// VMEM: Expected complete at 1332 (current 1257) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1336 (current 1261) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1340 (current 1265) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1344 (current 1269) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 56, Inc: 4 -// VMEM: Expected complete at 1408 (current 1333) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1412 (current 1337) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1416 (current 1341) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1043) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 1043) reg expression - // (op 1043) reg expression - // (op 1043) Add(v[20:21]:U64, v16:R)U64 - // (op 1043) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 1043) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 1043) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 -v_add_co_u32 v20, s[40:41], v20, v16 // (op 1043) least significant half -v_addc_co_u32 v21, s[40:41], 0, v21, s[40:41] // (op 1043) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1043): s40, s41 - - // (op 1043) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1043) reg expression - // (op 1043) Add(m0:U32, 1024:U32)U32 - // (op 1043) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1043) - // (op 1043) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], s16 offen offset: 0 lds // (op 1043) Load value direct to lds -// VMEM: Expected complete at 1420 (current 1345) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1043): s16 - - // Freeing Stride484: 2 VGPRs (Value: UInt64) (op 1043): v16, v17 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1043): v20, v21 - - // Freeing : 1 SGPR (Value: UInt32) (op 1043): s1 - - // (op 1508) LoadTileDirect2LDS Value: Halfx2(1043) END - // (op 1508) Deallocate{}(1909) BEGIN - // (op 1909) Deallocate 613 - // Deleting tag 613 - // (op 1909) Deallocate 614 - // Deleting tag 614 - // (op 1909) Deallocate 612 - // Freeing DataFlowTag612: 1 SGPR (Value: UInt32) (op 1512): s0 - - // Deleting tag 612 - // (op 1909) Deallocate 615 - // Deleting tag 615 - // (op 1508) Deallocate{}(1909) END - // (op 1508) end: generate({1505}) - // (op 1508) Unlock Scope 1508 - // Unlock None - // (op 717) Scope(1508) END - // (op 717) end: generate({1508}) - // (op 1074) SetCoordinate(717) END - // (op 1074) Deallocate{}(1873) BEGIN - // (op 1873) Deallocate 484 - // Deleting tag 484 - // (op 1873) Deallocate 483 - // Freeing DataFlowTag483: 2 VGPRs (Value: UInt64) (op 1082): v12, v13 - - // Deleting tag 483 - // (op 1873) Deallocate 482 - // Deleting tag 482 - // (op 1873) Deallocate 486 - // Deleting tag 486 - // (op 1873) Deallocate 485 - // Deleting tag 485 - // (op 1074) Deallocate{}(1873) END - // (op 1074) NOP(1025) BEGIN - // (op 1025) generate({}) - // (op 1025) end: generate({}) - // (op 1074) NOP(1025) END - // (op 1074) NOP(1030) BEGIN - // (op 1030) generate({}) - // (op 1030) end: generate({}) - // (op 1074) NOP(1030) END - // (op 1074) Barrier(693) BEGIN -s_waitcnt vmcnt(48) -s_barrier // (op 693) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 1074) Barrier(693) END - // (op 1074) SetCoordinate(757) BEGIN - // (op 757) generate({}) - // (op 757) end: generate({}) - // (op 757) generate({758}) - // (op 757) LoadLDSTile{Value: Halfx2}(758) BEGIN - // (op 758) GEN: loadMacroTileWAVELDS OP 758 LDS 21 WaveTile 145 - // (op 758) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 758) Generate 2:U32 into nullptr - // tag 19: v**UNALLOCATED** - // (op 758) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 758) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 758) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 758): v12, v13 -ds_read_b64 v[12:13], v3 // (op 758) Load local data -// DSMEM: Expected complete at 1368 (current 1348) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 757) LoadLDSTile{Value: Halfx2}(758) END - // (op 757) end: generate({758}) - // (op 1074) SetCoordinate(757) END - // (op 1074) SetCoordinate(760) BEGIN - // (op 760) generate({}) - // (op 760) end: generate({}) - // (op 760) generate({761}) - // (op 760) LoadLDSTile{Value: Halfx2}(761) BEGIN - // (op 761) GEN: loadMacroTileWAVELDS OP 761 LDS 21 WaveTile 145 - // (op 761) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 761) Generate 2:U32 into nullptr - // tag 255: v**UNALLOCATED** - // (op 761) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 761) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 761) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 761): v16, v17 -ds_read_b64 v[16:17], v3 offset:16 // (op 761) Load local data -// DSMEM: Expected complete at 1369 (current 1349) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 760) LoadLDSTile{Value: Halfx2}(761) END - // (op 760) end: generate({761}) - // (op 1074) SetCoordinate(760) END - // (op 1074) SetCoordinate(763) BEGIN - // (op 763) generate({}) - // (op 763) end: generate({}) - // (op 763) generate({764}) - // (op 763) LoadLDSTile{Value: Halfx2}(764) BEGIN - // (op 764) GEN: loadMacroTileWAVELDS OP 764 LDS 21 WaveTile 145 - // (op 764) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 764) Generate 2:U32 into nullptr - // tag 259: v**UNALLOCATED** - // (op 764) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 764) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 764) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 -ds_read_b64 v[20:21], v3 offset:32 // (op 764) Load local data -// DSMEM: Expected complete at 1370 (current 1350) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 763) LoadLDSTile{Value: Halfx2}(764) END - // (op 763) end: generate({764}) - // (op 1074) SetCoordinate(763) END - // (op 1074) SetCoordinate(766) BEGIN - // (op 766) generate({}) - // (op 766) end: generate({}) - // (op 766) generate({767}) - // (op 766) LoadLDSTile{Value: Halfx2}(767) BEGIN - // (op 767) GEN: loadMacroTileWAVELDS OP 767 LDS 21 WaveTile 145 - // (op 767) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 767) Generate 2:U32 into nullptr - // tag 263: v**UNALLOCATED** - // (op 767) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 767) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 48 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 767) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 -ds_read_b64 v[22:23], v3 offset:48 // (op 767) Load local data -// DSMEM: Expected complete at 1371 (current 1351) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 766) LoadLDSTile{Value: Halfx2}(767) END - // (op 766) end: generate({767}) - // (op 1074) SetCoordinate(766) END - // (op 1074) SetCoordinate(769) BEGIN - // (op 769) generate({}) - // (op 769) end: generate({}) - // (op 769) generate({770}) - // (op 769) LoadLDSTile{Value: Halfx2}(770) BEGIN - // (op 770) GEN: loadMacroTileWAVELDS OP 770 LDS 21 WaveTile 145 - // (op 770) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 770) Generate 2:U32 into nullptr - // tag 267: v**UNALLOCATED** - // (op 770) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 770) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 64 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 770) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 -ds_read_b64 v[24:25], v3 offset:64 // (op 770) Load local data -// DSMEM: Expected stall of 17. CBNW: 0, Inc: 4 -// DSMEM: Expected complete at 1389 (current 1369) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 769) LoadLDSTile{Value: Halfx2}(770) END - // (op 769) end: generate({770}) - // (op 1074) SetCoordinate(769) END - // (op 1074) SetCoordinate(772) BEGIN - // (op 772) generate({}) - // (op 772) end: generate({}) - // (op 772) generate({773}) - // (op 772) LoadLDSTile{Value: Halfx2}(773) BEGIN - // (op 773) GEN: loadMacroTileWAVELDS OP 773 LDS 21 WaveTile 145 - // (op 773) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 773) Generate 2:U32 into nullptr - // tag 271: v**UNALLOCATED** - // (op 773) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 773) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 80 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 773) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 -ds_read_b64 v[26:27], v3 offset:80 // (op 773) Load local data -// DSMEM: Expected complete at 1390 (current 1370) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 772) LoadLDSTile{Value: Halfx2}(773) END - // (op 772) end: generate({773}) - // (op 1074) SetCoordinate(772) END - // (op 1074) SetCoordinate(775) BEGIN - // (op 775) generate({}) - // (op 775) end: generate({}) - // (op 775) generate({776}) - // (op 775) LoadLDSTile{Value: Halfx2}(776) BEGIN - // (op 776) GEN: loadMacroTileWAVELDS OP 776 LDS 21 WaveTile 145 - // (op 776) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 776) Generate 2:U32 into nullptr - // tag 275: v**UNALLOCATED** - // (op 776) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 776) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 96 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 776) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 -ds_read_b64 v[28:29], v3 offset:96 // (op 776) Load local data -// DSMEM: Expected complete at 1391 (current 1371) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 775) LoadLDSTile{Value: Halfx2}(776) END - // (op 775) end: generate({776}) - // (op 1074) SetCoordinate(775) END - // (op 1074) SetCoordinate(778) BEGIN - // (op 778) generate({}) - // (op 778) end: generate({}) - // (op 778) generate({779}) - // (op 778) LoadLDSTile{Value: Halfx2}(779) BEGIN - // (op 779) GEN: loadMacroTileWAVELDS OP 779 LDS 21 WaveTile 145 - // (op 779) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 779) Generate 2:U32 into nullptr - // tag 279: v**UNALLOCATED** - // (op 779) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 779) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 112 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 779) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 -ds_read_b64 v[30:31], v3 offset:112 // (op 779) Load local data -// DSMEM: Expected complete at 1392 (current 1372) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 778) LoadLDSTile{Value: Halfx2}(779) END - // (op 778) end: generate({779}) - // (op 1074) SetCoordinate(778) END - // (op 1074) SetCoordinate(733) BEGIN - // (op 733) generate({}) - // (op 733) end: generate({}) - // (op 733) generate({734}) - // (op 733) LoadLDSTile{Value: Halfx2}(734) BEGIN - // (op 734) GEN: loadMacroTileWAVELDS OP 734 LDS 13 WaveTile 85 - // (op 734) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 734) Generate 2:U32 into nullptr - // tag 11: v**UNALLOCATED** - // (op 734) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 734) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 734) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 -ds_read_b64 v[32:33], v0 offset:8192 // (op 734) Load local data -// DSMEM: Expected stall of 17. CBNW: 4, Inc: 4 -// DSMEM: Expected complete at 1410 (current 1390) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 733) LoadLDSTile{Value: Halfx2}(734) END - // (op 733) end: generate({734}) - // (op 1074) SetCoordinate(733) END - // (op 1074) SetCoordinate(736) BEGIN - // (op 736) generate({}) - // (op 736) end: generate({}) - // (op 736) generate({737}) - // (op 736) LoadLDSTile{Value: Halfx2}(737) BEGIN - // (op 737) GEN: loadMacroTileWAVELDS OP 737 LDS 13 WaveTile 85 - // (op 737) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 737) Generate 2:U32 into nullptr - // tag 253: v**UNALLOCATED** - // (op 737) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 737) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8208 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 737) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 -ds_read_b64 v[34:35], v0 offset:8208 // (op 737) Load local data -// DSMEM: Expected complete at 1411 (current 1391) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 736) LoadLDSTile{Value: Halfx2}(737) END - // (op 736) end: generate({737}) - // (op 1074) SetCoordinate(736) END - // (op 1074) SetCoordinate(739) BEGIN - // (op 739) generate({}) - // (op 739) end: generate({}) - // (op 739) generate({740}) - // (op 739) LoadLDSTile{Value: Halfx2}(740) BEGIN - // (op 740) GEN: loadMacroTileWAVELDS OP 740 LDS 13 WaveTile 85 - // (op 740) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 740) Generate 2:U32 into nullptr - // tag 257: v**UNALLOCATED** - // (op 740) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 740) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8224 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 740) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 -ds_read_b64 v[36:37], v0 offset:8224 // (op 740) Load local data -// DSMEM: Expected complete at 1412 (current 1392) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 739) LoadLDSTile{Value: Halfx2}(740) END - // (op 739) end: generate({740}) - // (op 1074) SetCoordinate(739) END - // (op 1074) SetCoordinate(742) BEGIN - // (op 742) generate({}) - // (op 742) end: generate({}) - // (op 742) generate({743}) - // (op 742) LoadLDSTile{Value: Halfx2}(743) BEGIN - // (op 743) GEN: loadMacroTileWAVELDS OP 743 LDS 13 WaveTile 85 - // (op 743) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 743) Generate 2:U32 into nullptr - // tag 261: v**UNALLOCATED** - // (op 743) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 743) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8240 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 743) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 -ds_read_b64 v[38:39], v0 offset:8240 // (op 743) Load local data -// DSMEM: Expected complete at 1413 (current 1393) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 742) LoadLDSTile{Value: Halfx2}(743) END - // (op 742) end: generate({743}) - // (op 1074) SetCoordinate(742) END - // (op 1074) SetCoordinate(745) BEGIN - // (op 745) generate({}) - // (op 745) end: generate({}) - // (op 745) generate({746}) - // (op 745) LoadLDSTile{Value: Halfx2}(746) BEGIN - // (op 746) GEN: loadMacroTileWAVELDS OP 746 LDS 13 WaveTile 85 - // (op 746) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 746) Generate 2:U32 into nullptr - // tag 265: v**UNALLOCATED** - // (op 746) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 746) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8256 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 746) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 -ds_read_b64 v[40:41], v0 offset:8256 // (op 746) Load local data -// DSMEM: Expected stall of 17. CBNW: 8, Inc: 4 -// DSMEM: Expected complete at 1431 (current 1411) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 745) LoadLDSTile{Value: Halfx2}(746) END - // (op 745) end: generate({746}) - // (op 1074) SetCoordinate(745) END - // (op 1074) SetCoordinate(748) BEGIN - // (op 748) generate({}) - // (op 748) end: generate({}) - // (op 748) generate({749}) - // (op 748) LoadLDSTile{Value: Halfx2}(749) BEGIN - // (op 749) GEN: loadMacroTileWAVELDS OP 749 LDS 13 WaveTile 85 - // (op 749) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 749) Generate 2:U32 into nullptr - // tag 269: v**UNALLOCATED** - // (op 749) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 749) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8272 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 749) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 -ds_read_b64 v[42:43], v0 offset:8272 // (op 749) Load local data -// DSMEM: Expected complete at 1432 (current 1412) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 748) LoadLDSTile{Value: Halfx2}(749) END - // (op 748) end: generate({749}) - // (op 1074) SetCoordinate(748) END - // (op 1074) SetCoordinate(751) BEGIN - // (op 751) generate({}) - // (op 751) end: generate({}) - // (op 751) generate({752}) - // (op 751) LoadLDSTile{Value: Halfx2}(752) BEGIN - // (op 752) GEN: loadMacroTileWAVELDS OP 752 LDS 13 WaveTile 85 - // (op 752) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 752) Generate 2:U32 into nullptr - // tag 273: v**UNALLOCATED** - // (op 752) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 752) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8288 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 752) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 -ds_read_b64 v[44:45], v0 offset:8288 // (op 752) Load local data -// DSMEM: Expected complete at 1433 (current 1413) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 751) LoadLDSTile{Value: Halfx2}(752) END - // (op 751) end: generate({752}) - // (op 1074) SetCoordinate(751) END - // (op 1074) SetCoordinate(754) BEGIN - // (op 754) generate({}) - // (op 754) end: generate({}) - // (op 754) generate({755}) - // (op 754) LoadLDSTile{Value: Halfx2}(755) BEGIN - // (op 755) GEN: loadMacroTileWAVELDS OP 755 LDS 13 WaveTile 85 - // (op 755) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 755) Generate 2:U32 into nullptr - // tag 277: v**UNALLOCATED** - // (op 755) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 755) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8304 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 755) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 -ds_read_b64 v[46:47], v0 offset:8304 // (op 755) Load local data -// DSMEM: Expected complete at 1434 (current 1414) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 754) LoadLDSTile{Value: Halfx2}(755) END - // (op 754) end: generate({755}) - // (op 1074) SetCoordinate(754) END - // (op 1074) NOP(694) BEGIN - // (op 694) generate({}) - // (op 694) end: generate({}) - // (op 1074) NOP(694) END - // (op 1074) NOP(1199) BEGIN - // (op 1199) generate({}) - // (op 1199) end: generate({}) - // (op 1074) NOP(1199) END - // (op 1074) NOP(1196) BEGIN - // (op 1196) generate({}) - // (op 1196) end: generate({}) - // (op 1074) NOP(1196) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) BEGIN - // (op 1203) Assign dim(518) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 518: s**UNALLOCATED** - // (op 1203) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag518: SGPR Value: UInt32 x 1: (unallocated) - // (op 1203) reg expression - // (op 1203) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 -v_and_b32 v48, -32, v1 // (op 1203) - // (op 1203) BEGIN: Tile[1] - // (op 1203) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 -v_sub_u32 v49, v1, v48 // (op 1203) - // (op 1203) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1203): v48 - - // (op 1203) BEGIN: Flatten - // (op 1203) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1203) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1203) - // (op 1203) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1203): v49 - - // (op 1203) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1203) - // (op 1203) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1203) - // (op 1203) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1203): v49 - - // (op 1203) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1203) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1203) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1203) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1203): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1203) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1203): v50 - -// Allocated DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s0 -s_nop 0 -v_readfirstlane_b32 s0, v48 // (op 1203) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1203): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203) END - // (op 1074) Assign VGPR 1024:U32(1204) BEGIN - // (op 1204) Assign dim(519) = 1024:U32 - // (op 1204) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1204) END - // (op 1074) NOP(1197) BEGIN - // (op 1197) generate({}) - // (op 1197) end: generate({}) - // (op 1074) NOP(1197) END - // (op 1074) Assign VGPR 2:U32(1208) BEGIN - // (op 1208) Assign dim(521) = 2:U32 - // (op 1208) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1208) END - // (op 1074) NOP(1250) BEGIN - // (op 1250) generate({}) - // (op 1250) end: generate({}) - // (op 1074) NOP(1250) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) BEGIN - // (op 1255) Assign dim(534) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 534: s**UNALLOCATED** - // (op 1255) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag534: SGPR Value: UInt32 x 1: (unallocated) - // (op 1255) reg expression - // (op 1255) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 -v_and_b32 v48, -32, v1 // (op 1255) - // (op 1255) BEGIN: Tile[1] - // (op 1255) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 -v_sub_u32 v49, v1, v48 // (op 1255) - // (op 1255) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1255): v48 - - // (op 1255) BEGIN: Flatten - // (op 1255) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1255) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1255) - // (op 1255) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1255): v49 - - // (op 1255) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1255) - // (op 1255) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1255) - // (op 1255) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1255): v49 - - // (op 1255) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1255) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1255) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1255) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1255): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1255) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1255): v50 - -// Allocated DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s1 -s_nop 0 -v_readfirstlane_b32 s1, v48 // (op 1255) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1255): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255) END - // (op 1074) Assign VGPR 1024:U32(1256) BEGIN - // (op 1256) Assign dim(535) = 1024:U32 - // (op 1256) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1256) END - // (op 1074) NOP(1251) BEGIN - // (op 1251) generate({}) - // (op 1251) end: generate({}) - // (op 1074) NOP(1251) END - // (op 1074) Assign VGPR 2:U32(1260) BEGIN - // (op 1260) Assign dim(537) = 2:U32 - // (op 1260) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1260) END - // (op 1074) NOP(1336) BEGIN - // (op 1336) generate({}) - // (op 1336) end: generate({}) - // (op 1074) NOP(1336) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) BEGIN - // (op 1341) Assign dim(560) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 560: s**UNALLOCATED** - // (op 1341) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag560: SGPR Value: UInt32 x 1: (unallocated) - // (op 1341) reg expression - // (op 1341) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 -v_and_b32 v48, -32, v1 // (op 1341) - // (op 1341) BEGIN: Tile[1] - // (op 1341) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 -v_sub_u32 v49, v1, v48 // (op 1341) - // (op 1341) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1341): v48 - - // (op 1341) BEGIN: Flatten - // (op 1341) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1341) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1341) - // (op 1341) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1341): v49 - - // (op 1341) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1341) - // (op 1341) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1341) - // (op 1341) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1341): v49 - - // (op 1341) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1341) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1341) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1341) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1341): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1341) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1341): v50 - -// Allocated DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s16 -s_nop 0 -v_readfirstlane_b32 s16, v48 // (op 1341) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1341): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341) END - // (op 1074) Assign VGPR 1024:U32(1342) BEGIN - // (op 1342) Assign dim(561) = 1024:U32 - // (op 1342) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1342) END - // (op 1074) NOP(1337) BEGIN - // (op 1337) generate({}) - // (op 1337) end: generate({}) - // (op 1074) NOP(1337) END - // (op 1074) Assign VGPR 2:U32(1346) BEGIN - // (op 1346) Assign dim(563) = 2:U32 - // (op 1346) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1346) END - // (op 1074) NOP(1375) BEGIN - // (op 1375) generate({}) - // (op 1375) end: generate({}) - // (op 1074) NOP(1375) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) BEGIN - // (op 1380) Assign dim(572) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 572: s**UNALLOCATED** - // (op 1380) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag572: SGPR Value: UInt32 x 1: (unallocated) - // (op 1380) reg expression - // (op 1380) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 -v_and_b32 v48, -32, v1 // (op 1380) - // (op 1380) BEGIN: Tile[1] - // (op 1380) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 -v_sub_u32 v49, v1, v48 // (op 1380) - // (op 1380) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1380): v48 - - // (op 1380) BEGIN: Flatten - // (op 1380) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1380) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1380) - // (op 1380) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1380): v49 - - // (op 1380) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1380) - // (op 1380) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1380) - // (op 1380) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1380): v49 - - // (op 1380) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1380) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1380) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1380) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1380): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1380) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1380): v50 - -// Allocated DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s17 -s_nop 0 -v_readfirstlane_b32 s17, v48 // (op 1380) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1380): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380) END - // (op 1074) Assign VGPR 1024:U32(1381) BEGIN - // (op 1381) Assign dim(573) = 1024:U32 - // (op 1381) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1381) END - // (op 1074) NOP(1376) BEGIN - // (op 1376) generate({}) - // (op 1376) end: generate({}) - // (op 1074) NOP(1376) END - // (op 1074) Assign VGPR 2:U32(1385) BEGIN - // (op 1385) Assign dim(575) = 2:U32 - // (op 1385) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1385) END - // (op 1074) NOP(1414) BEGIN - // (op 1414) generate({}) - // (op 1414) end: generate({}) - // (op 1074) NOP(1414) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) BEGIN - // (op 1419) Assign dim(584) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 584: s**UNALLOCATED** - // (op 1419) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag584: SGPR Value: UInt32 x 1: (unallocated) - // (op 1419) reg expression - // (op 1419) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 -v_and_b32 v48, -32, v1 // (op 1419) - // (op 1419) BEGIN: Tile[1] - // (op 1419) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 -v_sub_u32 v49, v1, v48 // (op 1419) - // (op 1419) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1419): v48 - - // (op 1419) BEGIN: Flatten - // (op 1419) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1419) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1419) - // (op 1419) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1419): v49 - - // (op 1419) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1419) - // (op 1419) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1419) - // (op 1419) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1419): v49 - - // (op 1419) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1419) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1419) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1419) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1419): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1419) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1419): v50 - -// Allocated DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 -s_nop 0 -v_readfirstlane_b32 s40, v48 // (op 1419) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1419): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419) END - // (op 1074) Assign VGPR 1024:U32(1420) BEGIN - // (op 1420) Assign dim(585) = 1024:U32 - // (op 1420) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1420) END - // (op 1074) NOP(1415) BEGIN - // (op 1415) generate({}) - // (op 1415) end: generate({}) - // (op 1074) NOP(1415) END - // (op 1074) Assign VGPR 2:U32(1424) BEGIN - // (op 1424) Assign dim(587) = 2:U32 - // (op 1424) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1424) END - // (op 1074) NOP(1453) BEGIN - // (op 1453) generate({}) - // (op 1453) end: generate({}) - // (op 1074) NOP(1453) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) BEGIN - // (op 1458) Assign dim(596) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 596: s**UNALLOCATED** - // (op 1458) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag596: SGPR Value: UInt32 x 1: (unallocated) - // (op 1458) reg expression - // (op 1458) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 -v_and_b32 v48, -32, v1 // (op 1458) - // (op 1458) BEGIN: Tile[1] - // (op 1458) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 -v_sub_u32 v49, v1, v48 // (op 1458) - // (op 1458) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1458): v48 - - // (op 1458) BEGIN: Flatten - // (op 1458) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1458) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1458) - // (op 1458) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1458): v49 - - // (op 1458) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1458) - // (op 1458) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1458) - // (op 1458) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1458): v49 - - // (op 1458) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1458) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1458) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1458) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1458): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1458) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1458): v50 - -// Allocated DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 -s_nop 0 -v_readfirstlane_b32 s41, v48 // (op 1458) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1458): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458) END - // (op 1074) Assign VGPR 1024:U32(1459) BEGIN - // (op 1459) Assign dim(597) = 1024:U32 - // (op 1459) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1459) END - // (op 1074) NOP(1454) BEGIN - // (op 1454) generate({}) - // (op 1454) end: generate({}) - // (op 1074) NOP(1454) END - // (op 1074) Assign VGPR 2:U32(1463) BEGIN - // (op 1463) Assign dim(599) = 2:U32 - // (op 1463) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1463) END - // (op 1074) NOP(1492) BEGIN - // (op 1492) generate({}) - // (op 1492) end: generate({}) - // (op 1074) NOP(1492) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) BEGIN - // (op 1497) Assign dim(608) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 608: s**UNALLOCATED** - // (op 1497) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag608: SGPR Value: UInt32 x 1: (unallocated) - // (op 1497) reg expression - // (op 1497) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 -v_and_b32 v48, -32, v1 // (op 1497) - // (op 1497) BEGIN: Tile[1] - // (op 1497) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 -v_sub_u32 v49, v1, v48 // (op 1497) - // (op 1497) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1497): v48 - - // (op 1497) BEGIN: Flatten - // (op 1497) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1497) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1497) - // (op 1497) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1497): v49 - - // (op 1497) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1497) - // (op 1497) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1497) - // (op 1497) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1497): v49 - - // (op 1497) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1497) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1497) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1497) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1497): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1497) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1497): v50 - -// Allocated DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 -s_nop 0 -v_readfirstlane_b32 s42, v48 // (op 1497) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1497): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497) END - // (op 1074) Assign VGPR 1024:U32(1498) BEGIN - // (op 1498) Assign dim(609) = 1024:U32 - // (op 1498) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1498) END - // (op 1074) NOP(1493) BEGIN - // (op 1493) generate({}) - // (op 1493) end: generate({}) - // (op 1074) NOP(1493) END - // (op 1074) Assign VGPR 2:U32(1502) BEGIN - // (op 1502) Assign dim(611) = 2:U32 - // (op 1502) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1502) END - // (op 1074) NOP(1531) BEGIN - // (op 1531) generate({}) - // (op 1531) end: generate({}) - // (op 1074) NOP(1531) END - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) BEGIN - // (op 1536) Assign dim(620) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 620: s**UNALLOCATED** - // (op 1536) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag620: SGPR Value: UInt32 x 1: (unallocated) - // (op 1536) reg expression - // (op 1536) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 -v_and_b32 v48, -32, v1 // (op 1536) - // (op 1536) BEGIN: Tile[1] - // (op 1536) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v48:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 -v_sub_u32 v49, v1, v48 // (op 1536) - // (op 1536) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1536): v48 - - // (op 1536) BEGIN: Flatten - // (op 1536) {Flatten: ShiftL({Tile[1]: v49:U32}, 1:U32)U32} - // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1536) value (Tile[1]: VGPR Value: UInt32 x 1: v49) - // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 -v_lshlrev_b32 v48, 1, v49 // (op 1536) - // (op 1536) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1536): v49 - - // (op 1536) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v49 -v_lshrrev_b32 v49, 5, v1 // (op 1536) - // (op 1536) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v50 -v_lshl_add_u32 v50, v49, 6, v48 // (op 1536) - // (op 1536) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v48 - - // Freeing : 1 VGPR (Value: UInt32) (op 1536): v49 - - // (op 1536) ShiftL({Flatten: v50:U32}, 1:U32)U32 - // (op 1536) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1536) value (Flatten: VGPR Value: UInt32 x 1: v50) - // (op 1536) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1536): v48 -v_lshlrev_b32 v48, 1, v50 // (op 1536) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1536): v50 - -// Allocated DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 -s_nop 0 -v_readfirstlane_b32 s43, v48 // (op 1536) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1536): v48 - - // (op 1074) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536) END - // (op 1074) Assign VGPR 1024:U32(1537) BEGIN - // (op 1537) Assign dim(621) = 1024:U32 - // (op 1537) Assign stride expression - // (op 1074) Assign VGPR 1024:U32(1537) END - // (op 1074) NOP(1532) BEGIN - // (op 1532) generate({}) - // (op 1532) end: generate({}) - // (op 1074) NOP(1532) END - // (op 1074) Assign VGPR 2:U32(1541) BEGIN - // (op 1541) Assign dim(623) = 2:U32 - // (op 1541) Assign stride expression - // (op 1074) Assign VGPR 2:U32(1541) END - // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) BEGIN - // (op 39) Initialize For Loop - // (op 39) generate({40}) - // (op 39) Assign SGPR 0:U32(40) BEGIN - // (op 40) Assign dim(245) = 0:U32 - // tag 245: s**UNALLOCATED** - // (op 40) Generate 0:U32 into DataFlowTag245: SGPR Value: UInt32 x 1: (unallocated) -// Allocated DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 -s_mov_b32 s44, 0 // (op 40) call() - // (op 39) Tag 40non referenced extraArgs = {Tensor_0_size_1_10} - - // (op 39) Assign SGPR 0:U32(40) END - // (op 39) end: generate({40}) - // (op 39) Lock For Loop - // Lock Branch - // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc - // (op 39) Get arg Tensor_0_size_1_10 - // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL - // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 - // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 -s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) -// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 -s_mov_b32 s45, s46 // (op 39) convert - // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 - -// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 -s_and_b32 s46, s45, 4294967292 // (op 39) - // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 - -s_cmp_lt_u32 s44, s46 // (op 39) - // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 - -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 39) -s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39 // (op 39) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39 if false) -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39: - // (op 39) - // (op 39) generate({41, 57, 811, 1733}) - // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) BEGIN - // (op 41) Assign dim(245) = Add(DataFlowTag(245)U32, 4:U32)U32 - // (op 41) Generate Add(DataFlowTag(245)U32, 4:U32)U32 into DataFlowTag245: SGPR Value: UInt32 x 1: s44 - // (op 41) reg expression - // (op 41) Add({DataFlowTag245: s44:U32}, 4:U32)U32 - // (op 39) Multiply(57) BEGIN - // (op 57) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) Barrier(811) BEGIN - // (op 39) Barrier(1733) BEGIN -s_waitcnt vmcnt(32) -s_barrier // (op 811) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 39) Barrier(811) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 57) - // (op 39) Multiply(57) END -s_barrier // (op 1733) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 39) Barrier(1733) END - // (op 39) Multiply(66) BEGIN - // (op 66) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(332) BEGIN - // (op 332) generate({}) - // (op 332) end: generate({}) - // (op 332) generate({333}) - // (op 332) LoadLDSTile{Value: Halfx2}(333) BEGIN - // (op 333) GEN: loadMacroTileWAVELDS OP 333 LDS 360 WaveTile 145 - // (op 333) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 333) Generate 2:U32 into nullptr - // tag 364: v[12:13] alias 364 -> 19 - // (op 333) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 333) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 333) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) SetCoordinate(604) BEGIN - // (op 604) generate({}) - // (op 604) end: generate({}) - // (op 604) generate({976}) - // (op 604) LoadTileDirect2LDS Value: Halfx2(976) BEGIN - // (op 976) GEN: LoadTileDirect2LDS - // (op 976) GEN: loadMacroTileDirect2LDS OP 976 LDS 21 MacroTile 7 - // (op 976) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 976) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) - // (op 976) Get arg Tensor_2_stride_1_12 - // (op 976) reg expression - // (op 976) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 976) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 976) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 976) shiftAmount (Literal Value: UInt32 x 0: 3) -ds_read_b64 v[12:13], v5 offset:16384 // (op 333) Load local data -// DSMEM: Expected complete at 1511 (current 1491) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 332) LoadLDSTile{Value: Halfx2}(333) END - // (op 332) end: generate({333}) - // (op 39) SetCoordinate(332) END -s_add_u32 s44, s44, 4 // (op 41) - // (op 39) Tag 41non referenced extraArgs = {Tensor_0_size_1_10} - - // (op 39) Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41) END - // (op 39) SetCoordinate(337) BEGIN - // (op 337) generate({}) - // (op 337) end: generate({}) - // (op 337) generate({338}) - // (op 337) LoadLDSTile{Value: Halfx2}(338) BEGIN - // (op 338) GEN: loadMacroTileWAVELDS OP 338 LDS 360 WaveTile 145 - // (op 338) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 338) Generate 2:U32 into nullptr - // tag 368: v**UNALLOCATED** - // (op 338) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 338) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16400 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 338) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 -ds_read_b64 v[48:49], v5 offset:16400 // (op 338) Load local data -// DSMEM: Expected complete at 1513 (current 1493) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 337) LoadLDSTile{Value: Halfx2}(338) END - // (op 337) end: generate({338}) - // (op 39) SetCoordinate(337) END -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 -s_lshl_b64 s[46:47], s[22:23], 3 // (op 976) - // (op 976) convert - // (op 976) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 976) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 976) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 976) shiftAmount (Literal Value: UInt32 x 0: 1) - // (op 39) SetCoordinate(342) BEGIN - // (op 342) generate({}) - // (op 342) end: generate({}) - // (op 342) generate({343}) - // (op 342) LoadLDSTile{Value: Halfx2}(343) BEGIN - // (op 343) GEN: loadMacroTileWAVELDS OP 343 LDS 360 WaveTile 145 - // (op 343) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 343) Generate 2:U32 into nullptr - // tag 372: v**UNALLOCATED** - // (op 343) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 343) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16416 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 343) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 -v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 976) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 976): s46, s47 - - // (op 976) Generate 2:U64 into nullptr - // (op 976) Generate 1024:U32 into nullptr - // (op 976) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 0 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // tag 508: v**UNALLOCATED** -// Allocated Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 -v_mov_b64 v[52:53], v[18:19] // (op 976) -// Allocated : 2 VGPRs (Value: UInt64) (op 976): v54, v55 -v_mov_b64 v[54:55], v[52:53] // (op 976) - // (op 976) Generate Add(0:U32, {DataFlowTag534: s1:U32})U32 into nullptr - // (op 976) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 976) Generate {DataFlowTag534: s1:U32} into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 976) reg expression - // (op 976) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 512 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 -s_mov_b32 s45, 512 // (op 976) call() -// 512 is not a supported value! -s_waitcnt lgkmcnt(8) -v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[16:17], a[0:15] // (op 66) - // (op 39) Multiply(66) END -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1577 (current 1502) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) Multiply(75) BEGIN - // (op 75) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1581 (current 1506) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1585 (current 1510) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 75) - // (op 39) Multiply(75) END -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half - // (op 39) Multiply(84) BEGIN - // (op 84) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1591 (current 1516) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 -ds_read_b64 v[56:57], v5 offset:16416 // (op 343) Load local data -// DSMEM: Expected complete at 1540 (current 1520) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 342) LoadLDSTile{Value: Halfx2}(343) END - // (op 342) end: generate({343}) - // (op 39) SetCoordinate(342) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[22:23], a[0:15] // (op 84) - // (op 39) Multiply(84) END - // (op 39) SetCoordinate(347) BEGIN - // (op 347) generate({}) - // (op 347) end: generate({}) - // (op 347) generate({348}) - // (op 347) LoadLDSTile{Value: Halfx2}(348) BEGIN - // (op 348) GEN: loadMacroTileWAVELDS OP 348 LDS 360 WaveTile 145 - // (op 348) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 348) Generate 2:U32 into nullptr - // tag 376: v**UNALLOCATED** - // (op 348) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 348) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16432 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 348) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(93) BEGIN - // (op 93) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 -ds_read_b64 v[58:59], v5 offset:16432 // (op 348) Load local data -// DSMEM: Expected complete at 1543 (current 1523) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 347) LoadLDSTile{Value: Halfx2}(348) END - // (op 347) end: generate({348}) - // (op 39) SetCoordinate(347) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[24:25], a[0:15] // (op 93) - // (op 39) Multiply(93) END - // (op 39) SetCoordinate(352) BEGIN - // (op 352) generate({}) - // (op 352) end: generate({}) - // (op 352) generate({353}) - // (op 352) LoadLDSTile{Value: Halfx2}(353) BEGIN - // (op 353) GEN: loadMacroTileWAVELDS OP 353 LDS 360 WaveTile 145 - // (op 353) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 353) Generate 2:U32 into nullptr - // tag 380: v**UNALLOCATED** - // (op 353) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 353) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16448 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 353) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(102) BEGIN - // (op 102) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 -ds_read_b64 v[60:61], v5 offset:16448 // (op 353) Load local data -// DSMEM: Expected complete at 1553 (current 1533) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 352) LoadLDSTile{Value: Halfx2}(353) END - // (op 352) end: generate({353}) - // (op 39) SetCoordinate(352) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[26:27], a[0:15] // (op 102) - // (op 39) Multiply(102) END - // (op 39) SetCoordinate(357) BEGIN - // (op 357) generate({}) - // (op 357) end: generate({}) - // (op 357) generate({358}) - // (op 357) LoadLDSTile{Value: Halfx2}(358) BEGIN - // (op 358) GEN: loadMacroTileWAVELDS OP 358 LDS 360 WaveTile 145 - // (op 358) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 358) Generate 2:U32 into nullptr - // tag 384: v**UNALLOCATED** - // (op 358) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 358) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16464 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 358) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(111) BEGIN - // (op 111) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 -ds_read_b64 v[62:63], v5 offset:16464 // (op 358) Load local data -// DSMEM: Expected complete at 1563 (current 1543) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 357) LoadLDSTile{Value: Halfx2}(358) END - // (op 357) end: generate({358}) - // (op 39) SetCoordinate(357) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[28:29], a[0:15] // (op 111) - // (op 39) Multiply(111) END - // (op 39) SetCoordinate(362) BEGIN - // (op 362) generate({}) - // (op 362) end: generate({}) - // (op 362) generate({363}) - // (op 362) LoadLDSTile{Value: Halfx2}(363) BEGIN - // (op 363) GEN: loadMacroTileWAVELDS OP 363 LDS 360 WaveTile 145 - // (op 363) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 363) Generate 2:U32 into nullptr - // tag 388: v**UNALLOCATED** - // (op 363) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 363) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16480 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 363) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(120) BEGIN - // (op 120) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 -ds_read_b64 v[64:65], v5 offset:16480 // (op 363) Load local data -// DSMEM: Expected complete at 1573 (current 1553) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 362) LoadLDSTile{Value: Halfx2}(363) END - // (op 362) end: generate({363}) - // (op 39) SetCoordinate(362) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[30:31], a[0:15] // (op 120) - // (op 39) Multiply(120) END - // (op 39) SetCoordinate(367) BEGIN - // (op 367) generate({}) - // (op 367) end: generate({}) - // (op 367) generate({368}) - // (op 367) LoadLDSTile{Value: Halfx2}(368) BEGIN - // (op 368) GEN: loadMacroTileWAVELDS OP 368 LDS 360 WaveTile 145 - // (op 368) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 368) Generate 2:U32 into nullptr - // tag 392: v**UNALLOCATED** - // (op 368) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16384 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 368) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag580: VGPR Value: UInt32 x 1: v5 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16496 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 368) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 -ds_read_b64 v[66:67], v5 offset:16496 // (op 368) Load local data -// DSMEM: Expected complete at 1583 (current 1563) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 367) LoadLDSTile{Value: Halfx2}(368) END - // (op 367) end: generate({368}) - // (op 39) SetCoordinate(367) END -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected stall of 14. CBNW: 32, Inc: 4 -// VMEM: Expected complete at 1653 (current 1578) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) Deallocate{}(1819) BEGIN - // (op 1819) Deallocate 582 - // Deleting tag 582 - // (op 39) Deallocate{}(1819) END -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half - // (op 39) SetCoordinate(330) BEGIN - // (op 330) generate({}) - // (op 330) end: generate({}) - // (op 330) generate({331}) - // (op 330) LoadLDSTile{Value: Halfx2}(331) BEGIN - // (op 331) GEN: loadMacroTileWAVELDS OP 331 LDS 356 WaveTile 85 - // (op 331) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 331) Generate 2:U32 into nullptr - // tag 362: v[32:33] alias 362 -> 11 - // (op 331) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 331) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 331) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -ds_read_b64 v[32:33], v4 offset:24576 // (op 331) Load local data -// DSMEM: Expected complete at 1601 (current 1581) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 330) LoadLDSTile{Value: Halfx2}(331) END - // (op 330) end: generate({331}) - // (op 39) SetCoordinate(330) END -s_add_u32 m0, m0, 1024 // (op 976) - // (op 39) SetCoordinate(335) BEGIN - // (op 335) generate({}) - // (op 335) end: generate({}) - // (op 335) generate({336}) - // (op 335) LoadLDSTile{Value: Halfx2}(336) BEGIN - // (op 336) GEN: loadMacroTileWAVELDS OP 336 LDS 356 WaveTile 85 - // (op 336) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 336) Generate 2:U32 into nullptr - // tag 366: v[34:35] alias 366 -> 253 - // (op 336) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 336) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24592 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 336) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 976) Expression temporary in special register - // Unlock None -ds_read_b64 v[34:35], v4 offset:24592 // (op 336) Load local data -// DSMEM: Expected complete at 1603 (current 1583) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 335) LoadLDSTile{Value: Halfx2}(336) END - // (op 335) end: generate({336}) - // (op 39) SetCoordinate(335) END -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1659 (current 1584) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(340) BEGIN - // (op 340) generate({}) - // (op 340) end: generate({}) - // (op 340) generate({341}) - // (op 340) LoadLDSTile{Value: Halfx2}(341) BEGIN - // (op 341) GEN: loadMacroTileWAVELDS OP 341 LDS 356 WaveTile 85 - // (op 341) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 341) Generate 2:U32 into nullptr - // tag 370: v[36:37] alias 370 -> 257 - // (op 341) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 341) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24608 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 341) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[36:37], v4 offset:24608 // (op 341) Load local data -// DSMEM: Expected complete at 1605 (current 1585) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 340) LoadLDSTile{Value: Halfx2}(341) END - // (op 340) end: generate({341}) - // (op 39) SetCoordinate(340) END -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half - // (op 39) SetCoordinate(345) BEGIN - // (op 345) generate({}) - // (op 345) end: generate({}) - // (op 345) generate({346}) - // (op 345) LoadLDSTile{Value: Halfx2}(346) BEGIN - // (op 346) GEN: loadMacroTileWAVELDS OP 346 LDS 356 WaveTile 85 - // (op 346) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 346) Generate 2:U32 into nullptr - // tag 374: v**UNALLOCATED** - // (op 346) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 346) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24624 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 346) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1664 (current 1589) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 976) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 976) reg expression - // (op 976) reg expression - // (op 976) Add(v[54:55]:U64, v50:R)U64 - // (op 976) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 976) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 976) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 976): s46, s47 -v_add_co_u32 v54, s[46:47], v54, v50 // (op 976) least significant half -v_addc_co_u32 v55, s[46:47], 0, v55, s[46:47] // (op 976) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 976): s46, s47 - - // (op 976) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 976) reg expression - // (op 976) Add(m0:U32, 1024:U32)U32 - // (op 976) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 976) - // (op 976) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s45 offen offset: 0 lds // (op 976) Load value direct to lds -// VMEM: Expected complete at 1668 (current 1593) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 976): s45 - - // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 976): v50, v51 - - // Freeing : 2 VGPRs (Value: UInt64) (op 976): v54, v55 - - // (op 604) LoadTileDirect2LDS Value: Halfx2(976) END - // (op 604) Deallocate{}(1877) BEGIN - // (op 1877) Deallocate 536 - // Deleting tag 536 - // (op 604) Deallocate{}(1877) END - // (op 604) end: generate({976}) - // (op 39) SetCoordinate(604) END -// Allocated : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 -ds_read_b64 v[50:51], v4 offset:24624 // (op 346) Load local data -// DSMEM: Expected complete at 1614 (current 1594) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 345) LoadLDSTile{Value: Halfx2}(346) END - // (op 345) end: generate({346}) - // (op 39) SetCoordinate(345) END - // (op 39) Barrier(1723) BEGIN - // (op 39) SetCoordinate(350) BEGIN - // (op 350) generate({}) - // (op 350) end: generate({}) - // (op 350) generate({351}) - // (op 350) LoadLDSTile{Value: Halfx2}(351) BEGIN - // (op 351) GEN: loadMacroTileWAVELDS OP 351 LDS 356 WaveTile 85 - // (op 351) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 351) Generate 2:U32 into nullptr - // tag 378: v[38:39] alias 378 -> 261 - // (op 351) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 351) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24640 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 351) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -s_barrier // (op 1723) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 39) Barrier(1723) END -ds_read_b64 v[38:39], v4 offset:24640 // (op 351) Load local data -// DSMEM: Expected stall of 6. CBNW: 8, Inc: 4 -// DSMEM: Expected complete at 1622 (current 1602) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 350) LoadLDSTile{Value: Halfx2}(351) END - // (op 350) end: generate({351}) - // (op 39) SetCoordinate(350) END - // (op 39) SetCoordinate(599) BEGIN - // (op 599) generate({}) - // (op 599) end: generate({}) - // (op 599) generate({971}) - // (op 599) LoadTileDirect2LDS Value: Halfx2(971) BEGIN - // (op 971) GEN: LoadTileDirect2LDS - // (op 971) GEN: loadMacroTileDirect2LDS OP 971 LDS 13 MacroTile 6 - // (op 971) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 971) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) - // (op 971) Get arg Tensor_0_stride_0_9 - // (op 971) reg expression - // (op 971) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 971) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 971) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 971) shiftAmount (Literal Value: UInt32 x 0: 3) - // (op 39) SetCoordinate(355) BEGIN - // (op 355) generate({}) - // (op 355) end: generate({}) - // (op 355) generate({356}) - // (op 355) LoadLDSTile{Value: Halfx2}(356) BEGIN - // (op 356) GEN: loadMacroTileWAVELDS OP 356 LDS 356 WaveTile 85 - // (op 356) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 356) Generate 2:U32 into nullptr - // tag 382: v**UNALLOCATED** - // (op 356) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 356) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24656 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 356) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 -s_lshl_b64 s[46:47], s[18:19], 3 // (op 971) - // (op 971) convert - // (op 971) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 971) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 971) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 971) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 -v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 971) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 971): s46, s47 - - // (op 971) Generate 2:U64 into nullptr - // (op 971) Generate 1024:U32 into nullptr - // (op 971) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 8192 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[54:55] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // tag 489: v**UNALLOCATED** -// Allocated Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 -v_mov_b64 v[68:69], v[14:15] // (op 971) -// Allocated : 2 VGPRs (Value: UInt64) (op 971): v70, v71 -v_mov_b64 v[70:71], v[68:69] // (op 971) - // (op 971) Generate Add(8192:U32, {DataFlowTag518: s0:U32})U32 into nullptr - // (op 971) reg expression - // (op 971) Add(8192:U32, {DataFlowTag518: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 971): s45 -s_add_u32 s45, 8192, s0 // (op 971) - // (op 971) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 971) Generate s45:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s45 // (op 971) reg expression - // (op 971) Generate 512:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 512 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 -s_mov_b32 s46, 512 // (op 971) call() -// 512 is not a supported value! -// Allocated : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 -ds_read_b64 v[72:73], v4 offset:24656 // (op 356) Load local data -// DSMEM: Expected complete at 1630 (current 1610) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 355) LoadLDSTile{Value: Halfx2}(356) END - // (op 355) end: generate({356}) - // (op 39) SetCoordinate(355) END -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected stall of 43. CBNW: 36, Inc: 4 -// VMEM: Expected complete at 1729 (current 1654) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) - // (op 39) SetCoordinate(360) BEGIN - // (op 360) generate({}) - // (op 360) end: generate({}) - // (op 360) generate({361}) - // (op 360) LoadLDSTile{Value: Halfx2}(361) BEGIN - // (op 361) GEN: loadMacroTileWAVELDS OP 361 LDS 356 WaveTile 85 - // (op 361) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 361) Generate 2:U32 into nullptr - // tag 386: v[40:41] alias 386 -> 265 - // (op 361) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 361) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24672 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 361) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[40:41], v4 offset:24672 // (op 361) Load local data -// DSMEM: Expected complete at 1675 (current 1655) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 360) LoadLDSTile{Value: Halfx2}(361) END - // (op 360) end: generate({361}) - // (op 39) SetCoordinate(360) END -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half - // (op 39) SetCoordinate(365) BEGIN - // (op 365) generate({}) - // (op 365) end: generate({}) - // (op 365) generate({366}) - // (op 365) LoadLDSTile{Value: Halfx2}(366) BEGIN - // (op 366) GEN: loadMacroTileWAVELDS OP 366 LDS 356 WaveTile 85 - // (op 366) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 366) Generate 2:U32 into nullptr - // tag 390: v**UNALLOCATED** - // (op 366) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24576 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 366) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag568: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 24688 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 366) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 -ds_read_b64 v[74:75], v4 offset:24688 // (op 366) Load local data -// DSMEM: Expected complete at 1679 (current 1659) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 365) LoadLDSTile{Value: Halfx2}(366) END - // (op 365) end: generate({366}) - // (op 39) SetCoordinate(365) END -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected complete at 1735 (current 1660) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) - // (op 39) Deallocate{}(1817) BEGIN - // (op 1817) Deallocate 570 - // Deleting tag 570 - // (op 39) Deallocate{}(1817) END -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 -// VMEM: Expected complete at 1740 (current 1665) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected complete at 1744 (current 1669) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected stall of 57. CBNW: 40, Inc: 4 -// VMEM: Expected complete at 1805 (current 1730) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 41, Inc: 4 -// VMEM: Expected complete at 1811 (current 1736) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 -// VMEM: Expected complete at 1816 (current 1741) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 971) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 971) reg expression - // (op 971) reg expression - // (op 971) Add(v[70:71]:U64, v54:R)U64 - // (op 971) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 971) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 971) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 971): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 971) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 971) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 971): s48, s49 - - // (op 971) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 971) reg expression - // (op 971) Add(m0:U32, 1024:U32)U32 - // (op 971) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 971) - // (op 971) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[32:35], s46 offen offset: 0 lds // (op 971) Load value direct to lds -// VMEM: Expected complete at 1820 (current 1745) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 971): s46 - - // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 971): v54, v55 - - // Freeing : 2 VGPRs (Value: UInt64) (op 971): v70, v71 - - // Freeing : 1 SGPR (Value: UInt32) (op 971): s45 - - // (op 599) LoadTileDirect2LDS Value: Halfx2(971) END - // (op 599) Deallocate{}(1875) BEGIN - // (op 1875) Deallocate 520 - // Deleting tag 520 - // (op 599) Deallocate{}(1875) END - // (op 599) end: generate({971}) - // (op 39) SetCoordinate(599) END - // (op 39) NOP(1000) BEGIN - // (op 1000) generate({}) - // (op 1000) end: generate({}) - // (op 39) NOP(1000) END - // (op 39) NOP(995) BEGIN - // (op 995) generate({}) - // (op 995) end: generate({}) - // (op 39) NOP(995) END - // (op 39) NOP(799) BEGIN - // (op 799) generate({}) - // (op 799) end: generate({}) - // (op 39) NOP(799) END - // (op 39) Multiply(334) BEGIN - // (op 334) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) Barrier(853) BEGIN - // (op 39) Barrier(1746) BEGIN -s_waitcnt vmcnt(32) -s_barrier // (op 853) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 39) Barrier(853) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 334) - // (op 39) Multiply(334) END -s_barrier // (op 1746) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 39) Barrier(1746) END - // (op 39) Deallocate{}(1803) BEGIN - // (op 1803) Deallocate 364 - // Deleting tag 364alias (-> 19) - // (op 1803) Deallocate 362 - // Deleting tag 362alias (-> 11) - // (op 39) Deallocate{}(1803) END - // (op 39) SetCoordinate(615) BEGIN - // (op 615) generate({}) - // (op 615) end: generate({}) - // (op 615) generate({998}) - // (op 615) LoadTileDirect2LDS Value: Halfx2(998) BEGIN - // (op 998) GEN: LoadTileDirect2LDS - // (op 998) GEN: loadMacroTileDirect2LDS OP 998 LDS 360 MacroTile 358 - // (op 998) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 998) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) - // (op 998) Get arg Tensor_2_stride_1_12 - // (op 998) reg expression - // (op 998) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 998) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 998) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 998) shiftAmount (Literal Value: UInt32 x 0: 3) - // (op 39) Multiply(339) BEGIN - // (op 339) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(422) BEGIN - // (op 422) generate({}) - // (op 422) end: generate({}) - // (op 422) generate({423}) - // (op 422) LoadLDSTile{Value: Halfx2}(423) BEGIN - // (op 423) GEN: loadMacroTileWAVELDS OP 423 LDS 400 WaveTile 145 - // (op 423) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 423) Generate 2:U32 into nullptr - // tag 404: v[12:13] alias 404 -> 19 - // (op 423) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 423) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 423) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[12:13], v7 offset:32768 // (op 423) Load local data -// DSMEM: Expected complete at 1771 (current 1751) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 422) LoadLDSTile{Value: Halfx2}(423) END - // (op 422) end: generate({423}) - // (op 39) SetCoordinate(422) END -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 -s_lshl_b64 s[46:47], s[22:23], 3 // (op 998) - // (op 998) convert - // (op 998) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 998) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 998) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 998) shiftAmount (Literal Value: UInt32 x 0: 1) - // (op 39) SetCoordinate(427) BEGIN - // (op 427) generate({}) - // (op 427) end: generate({}) - // (op 427) generate({428}) - // (op 427) LoadLDSTile{Value: Halfx2}(428) BEGIN - // (op 428) GEN: loadMacroTileWAVELDS OP 428 LDS 400 WaveTile 145 - // (op 428) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 428) Generate 2:U32 into nullptr - // tag 408: v[16:17] alias 408 -> 255 - // (op 428) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[16:17] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 428) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[16:17] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32784 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 428) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[16:17], v7 offset:32784 // (op 428) Load local data -// DSMEM: Expected complete at 1773 (current 1753) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 427) LoadLDSTile{Value: Halfx2}(428) END - // (op 427) end: generate({428}) - // (op 39) SetCoordinate(427) END -// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 -v_lshlrev_b64 v[54:55], 1, s[46:47] // (op 998) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 998): s46, s47 - - // (op 998) Generate 2:U64 into nullptr - // (op 998) Generate 1024:U32 into nullptr - // (op 998) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 16384 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[54:55] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // (op 39) SetCoordinate(432) BEGIN - // (op 432) generate({}) - // (op 432) end: generate({}) - // (op 432) generate({433}) - // (op 432) LoadLDSTile{Value: Halfx2}(433) BEGIN - // (op 433) GEN: loadMacroTileWAVELDS OP 433 LDS 400 WaveTile 145 - // (op 433) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 433) Generate 2:U32 into nullptr - // tag 412: v[20:21] alias 412 -> 259 - // (op 433) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[20:21] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 433) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[20:21] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32800 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 433) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[20:21], v7 offset:32800 // (op 433) Load local data -// DSMEM: Expected complete at 1775 (current 1755) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 432) LoadLDSTile{Value: Halfx2}(433) END - // (op 432) end: generate({433}) - // (op 39) SetCoordinate(432) END -// Allocated : 2 VGPRs (Value: UInt64) (op 998): v70, v71 -v_mov_b64 v[70:71], v[52:53] // (op 998) - // (op 998) Generate Add(16384:U32, {DataFlowTag572: s17:U32})U32 into nullptr - // (op 998) reg expression - // (op 998) Add(16384:U32, {DataFlowTag572: s17:U32})U32 - // (op 39) SetCoordinate(437) BEGIN - // (op 437) generate({}) - // (op 437) end: generate({}) - // (op 437) generate({438}) - // (op 437) LoadLDSTile{Value: Halfx2}(438) BEGIN - // (op 438) GEN: loadMacroTileWAVELDS OP 438 LDS 400 WaveTile 145 - // (op 438) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 438) Generate 2:U32 into nullptr - // tag 416: v[22:23] alias 416 -> 263 - // (op 438) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[22:23] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 438) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[22:23] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32816 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 438) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[22:23], v7 offset:32816 // (op 438) Load local data -// DSMEM: Expected complete at 1777 (current 1757) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 437) LoadLDSTile{Value: Halfx2}(438) END - // (op 437) end: generate({438}) - // (op 39) SetCoordinate(437) END -s_waitcnt lgkmcnt(10) -v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[48:49], a[0:15] // (op 339) - // (op 39) Multiply(339) END - // (op 39) SetCoordinate(442) BEGIN - // (op 442) generate({}) - // (op 442) end: generate({}) - // (op 442) generate({443}) - // (op 442) LoadLDSTile{Value: Halfx2}(443) BEGIN - // (op 443) GEN: loadMacroTileWAVELDS OP 443 LDS 400 WaveTile 145 - // (op 443) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 443) Generate 2:U32 into nullptr - // tag 420: v[24:25] alias 420 -> 267 - // (op 443) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[24:25] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 443) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[24:25] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32832 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 443) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1805) BEGIN - // (op 1805) Deallocate 366 - // Deleting tag 366alias (-> 253) - // (op 1805) Deallocate 368 - // Freeing : 2 VGPRs (Value: Halfx2) (op 338): v48, v49 - - // Deleting tag 368 - // (op 39) Deallocate{}(1805) END -// Allocated : 1 SGPR (Value: UInt32) (op 998): s45 -s_add_u32 s45, 16384, s17 // (op 998) - // (op 998) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[54:55]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 998) Generate s45:U32 into M0 Value: UInt32 x 1: m0 - // (op 39) Multiply(344) BEGIN - // (op 344) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_mov_b32 m0, s45 // (op 998) reg expression - // (op 998) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 640 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 -s_mov_b32 s46, 640 // (op 998) call() -// 640 is not a supported value! -s_waitcnt lgkmcnt(9) -v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[56:57], a[0:15] // (op 344) - // (op 39) Multiply(344) END -ds_read_b64 v[24:25], v7 offset:32832 // (op 443) Load local data -// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 -// DSMEM: Expected complete at 1792 (current 1772) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 442) LoadLDSTile{Value: Halfx2}(443) END - // (op 442) end: generate({443}) - // (op 39) SetCoordinate(442) END - // (op 39) Deallocate{}(1807) BEGIN - // (op 1807) Deallocate 372 - // Freeing : 2 VGPRs (Value: Halfx2) (op 343): v56, v57 - - // Deleting tag 372 - // (op 1807) Deallocate 370 - // Deleting tag 370alias (-> 257) - // (op 39) Deallocate{}(1807) END - // (op 39) SetCoordinate(447) BEGIN - // (op 447) generate({}) - // (op 447) end: generate({}) - // (op 447) generate({448}) - // (op 447) LoadLDSTile{Value: Halfx2}(448) BEGIN - // (op 448) GEN: loadMacroTileWAVELDS OP 448 LDS 400 WaveTile 145 - // (op 448) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 448) Generate 2:U32 into nullptr - // tag 424: v[26:27] alias 424 -> 271 - // (op 448) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[26:27] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 448) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[26:27] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32848 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 448) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(349) BEGIN - // (op 349) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -ds_read_b64 v[26:27], v7 offset:32848 // (op 448) Load local data -// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 -// DSMEM: Expected complete at 1794 (current 1774) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 447) LoadLDSTile{Value: Halfx2}(448) END - // (op 447) end: generate({448}) - // (op 39) SetCoordinate(447) END -s_waitcnt lgkmcnt(10) -v_mfma_f32_32x32x8f16 a[0:15], v[50:51], v[58:59], a[0:15] // (op 349) - // (op 39) Multiply(349) END - // (op 39) SetCoordinate(452) BEGIN - // (op 452) generate({}) - // (op 452) end: generate({}) - // (op 452) generate({453}) - // (op 452) LoadLDSTile{Value: Halfx2}(453) BEGIN - // (op 453) GEN: loadMacroTileWAVELDS OP 453 LDS 400 WaveTile 145 - // (op 453) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 453) Generate 2:U32 into nullptr - // tag 428: v[28:29] alias 428 -> 275 - // (op 453) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[28:29] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 453) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[28:29] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32864 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 453) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1809) BEGIN - // (op 1809) Deallocate 376 - // Freeing : 2 VGPRs (Value: Halfx2) (op 348): v58, v59 - - // Deleting tag 376 - // (op 1809) Deallocate 374 - // Freeing : 2 VGPRs (Value: Halfx2) (op 346): v50, v51 - - // Deleting tag 374 - // (op 39) Deallocate{}(1809) END -ds_read_b64 v[28:29], v7 offset:32864 // (op 453) Load local data -// DSMEM: Expected complete at 1800 (current 1780) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 452) LoadLDSTile{Value: Halfx2}(453) END - // (op 452) end: generate({453}) - // (op 39) SetCoordinate(452) END - // (op 39) Multiply(354) BEGIN - // (op 354) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(457) BEGIN - // (op 457) generate({}) - // (op 457) end: generate({}) - // (op 457) generate({458}) - // (op 457) LoadLDSTile{Value: Halfx2}(458) BEGIN - // (op 458) GEN: loadMacroTileWAVELDS OP 458 LDS 400 WaveTile 145 - // (op 458) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 458) Generate 2:U32 into nullptr - // tag 432: v[30:31] alias 432 -> 279 - // (op 458) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[30:31] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32768 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 458) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[30:31] - // info.rowOffsetReg = DataFlowTag604: VGPR Value: UInt32 x 1: v7 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32880 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 458) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[30:31], v7 offset:32880 // (op 458) Load local data -// DSMEM: Expected complete at 1801 (current 1781) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 457) LoadLDSTile{Value: Halfx2}(458) END - // (op 457) end: generate({458}) - // (op 39) SetCoordinate(457) END -s_waitcnt lgkmcnt(11) -v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[60:61], a[0:15] // (op 354) - // (op 39) Multiply(354) END - // (op 39) Deallocate{}(1839) BEGIN - // (op 1839) Deallocate 606 - // Deleting tag 606 - // (op 39) Deallocate{}(1839) END - // (op 39) Deallocate{}(1811) BEGIN - // (op 1811) Deallocate 378 - // Deleting tag 378alias (-> 261) - // (op 1811) Deallocate 380 - // Freeing : 2 VGPRs (Value: Halfx2) (op 353): v60, v61 - - // Deleting tag 380 - // (op 39) Deallocate{}(1811) END - // (op 39) SetCoordinate(420) BEGIN - // (op 420) generate({}) - // (op 420) end: generate({}) - // (op 420) generate({421}) - // (op 420) LoadLDSTile{Value: Halfx2}(421) BEGIN - // (op 421) GEN: loadMacroTileWAVELDS OP 421 LDS 396 WaveTile 85 - // (op 421) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 421) Generate 2:U32 into nullptr - // tag 402: v[32:33] alias 402 -> 11 - // (op 421) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 421) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 421) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(359) BEGIN - // (op 359) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -ds_read_b64 v[32:33], v6 offset:40960 // (op 421) Load local data -// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 -// DSMEM: Expected complete at 1813 (current 1793) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 420) LoadLDSTile{Value: Halfx2}(421) END - // (op 420) end: generate({421}) - // (op 39) SetCoordinate(420) END -s_waitcnt lgkmcnt(11) -v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[62:63], a[0:15] // (op 359) - // (op 39) Multiply(359) END - // (op 39) SetCoordinate(425) BEGIN - // (op 425) generate({}) - // (op 425) end: generate({}) - // (op 425) generate({426}) - // (op 425) LoadLDSTile{Value: Halfx2}(426) BEGIN - // (op 426) GEN: loadMacroTileWAVELDS OP 426 LDS 396 WaveTile 85 - // (op 426) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 426) Generate 2:U32 into nullptr - // tag 406: v[34:35] alias 406 -> 253 - // (op 426) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 426) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40976 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 426) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1813) BEGIN - // (op 1813) Deallocate 382 - // Freeing : 2 VGPRs (Value: Halfx2) (op 356): v72, v73 - - // Deleting tag 382 - // (op 1813) Deallocate 384 - // Freeing : 2 VGPRs (Value: Halfx2) (op 358): v62, v63 - - // Deleting tag 384 - // (op 39) Deallocate{}(1813) END -ds_read_b64 v[34:35], v6 offset:40976 // (op 426) Load local data -// DSMEM: Expected complete at 1820 (current 1800) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 425) LoadLDSTile{Value: Halfx2}(426) END - // (op 425) end: generate({426}) - // (op 39) SetCoordinate(425) END - // (op 39) Multiply(364) BEGIN - // (op 364) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(430) BEGIN - // (op 430) generate({}) - // (op 430) end: generate({}) - // (op 430) generate({431}) - // (op 430) LoadLDSTile{Value: Halfx2}(431) BEGIN - // (op 431) GEN: loadMacroTileWAVELDS OP 431 LDS 396 WaveTile 85 - // (op 431) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 431) Generate 2:U32 into nullptr - // tag 410: v[36:37] alias 410 -> 257 - // (op 431) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 431) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40992 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 431) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[36:37], v6 offset:40992 // (op 431) Load local data -// DSMEM: Expected complete at 1821 (current 1801) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 430) LoadLDSTile{Value: Halfx2}(431) END - // (op 430) end: generate({431}) - // (op 39) SetCoordinate(430) END -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected stall of 4. CBNW: 28, Inc: 4 -// VMEM: Expected complete at 1881 (current 1806) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) - // (op 39) SetCoordinate(435) BEGIN - // (op 435) generate({}) - // (op 435) end: generate({}) - // (op 435) generate({436}) - // (op 435) LoadLDSTile{Value: Halfx2}(436) BEGIN - // (op 436) GEN: loadMacroTileWAVELDS OP 436 LDS 396 WaveTile 85 - // (op 436) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 436) Generate 2:U32 into nullptr - // tag 414: v[42:43] alias 414 -> 269 - // (op 436) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[42:43] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 436) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[42:43] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 41008 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 436) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[42:43], v6 offset:41008 // (op 436) Load local data -// DSMEM: Expected complete at 1827 (current 1807) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 435) LoadLDSTile{Value: Halfx2}(436) END - // (op 435) end: generate({436}) - // (op 39) SetCoordinate(435) END -s_waitcnt lgkmcnt(13) -v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[64:65], a[0:15] // (op 364) - // (op 39) Multiply(364) END - // (op 39) SetCoordinate(440) BEGIN - // (op 440) generate({}) - // (op 440) end: generate({}) - // (op 440) generate({441}) - // (op 440) LoadLDSTile{Value: Halfx2}(441) BEGIN - // (op 441) GEN: loadMacroTileWAVELDS OP 441 LDS 396 WaveTile 85 - // (op 441) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 441) Generate 2:U32 into nullptr - // tag 418: v[44:45] alias 418 -> 273 - // (op 441) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[44:45] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 441) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[44:45] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 41024 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 441) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1815) BEGIN - // (op 1815) Deallocate 386 - // Deleting tag 386alias (-> 265) - // (op 1815) Deallocate 388 - // Freeing : 2 VGPRs (Value: Halfx2) (op 363): v64, v65 - - // Deleting tag 388 - // (op 39) Deallocate{}(1815) END -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half - // (op 39) Multiply(369) BEGIN - // (op 369) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected complete at 1888 (current 1813) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) -ds_read_b64 v[44:45], v6 offset:41024 // (op 441) Load local data -// DSMEM: Expected complete at 1834 (current 1814) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 440) LoadLDSTile{Value: Halfx2}(441) END - // (op 440) end: generate({441}) - // (op 39) SetCoordinate(440) END -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half - // (op 39) SetCoordinate(445) BEGIN - // (op 445) generate({}) - // (op 445) end: generate({}) - // (op 445) generate({446}) - // (op 445) LoadLDSTile{Value: Halfx2}(446) BEGIN - // (op 446) GEN: loadMacroTileWAVELDS OP 446 LDS 396 WaveTile 85 - // (op 446) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 446) Generate 2:U32 into nullptr - // tag 422: v[46:47] alias 422 -> 277 - // (op 446) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[46:47] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 446) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[46:47] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 41040 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 446) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -s_waitcnt lgkmcnt(13) -v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[66:67], a[0:15] // (op 369) - // (op 39) Multiply(369) END -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected complete at 1895 (current 1820) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) - // (op 39) Deallocate{}(1821) BEGIN - // (op 1821) Deallocate 392 - // Freeing : 2 VGPRs (Value: Halfx2) (op 368): v66, v67 - - // Deleting tag 392 - // (op 1821) Deallocate 390 - // Freeing : 2 VGPRs (Value: Halfx2) (op 366): v74, v75 - - // Deleting tag 390 - // (op 39) Deallocate{}(1821) END -ds_read_b64 v[46:47], v6 offset:41040 // (op 446) Load local data -// DSMEM: Expected complete at 1841 (current 1821) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 445) LoadLDSTile{Value: Halfx2}(446) END - // (op 445) end: generate({446}) - // (op 39) SetCoordinate(445) END -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half - // (op 39) SetCoordinate(450) BEGIN - // (op 450) generate({}) - // (op 450) end: generate({}) - // (op 450) generate({451}) - // (op 450) LoadLDSTile{Value: Halfx2}(451) BEGIN - // (op 451) GEN: loadMacroTileWAVELDS OP 451 LDS 396 WaveTile 85 - // (op 451) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 451) Generate 2:U32 into nullptr - // tag 426: v[38:39] alias 426 -> 261 - // (op 451) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 451) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 41056 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 451) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -ds_read_b64 v[38:39], v6 offset:41056 // (op 451) Load local data -// DSMEM: Expected complete at 1844 (current 1824) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 450) LoadLDSTile{Value: Halfx2}(451) END - // (op 450) end: generate({451}) - // (op 39) SetCoordinate(450) END -s_add_u32 m0, m0, 1024 // (op 998) - // (op 39) SetCoordinate(455) BEGIN - // (op 455) generate({}) - // (op 455) end: generate({}) - // (op 455) generate({456}) - // (op 455) LoadLDSTile{Value: Halfx2}(456) BEGIN - // (op 456) GEN: loadMacroTileWAVELDS OP 456 LDS 396 WaveTile 85 - // (op 456) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 456) Generate 2:U32 into nullptr - // tag 430: v**UNALLOCATED** - // (op 456) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 40960 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 456) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag592: VGPR Value: UInt32 x 1: v6 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 41072 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 456) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 998) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected complete at 1901 (current 1826) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 456): v48, v49 -ds_read_b64 v[48:49], v6 offset:41072 // (op 456) Load local data -// DSMEM: Expected complete at 1850 (current 1830) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 455) LoadLDSTile{Value: Halfx2}(456) END - // (op 455) end: generate({456}) - // (op 39) SetCoordinate(455) END -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 -// VMEM: Expected complete at 1957 (current 1882) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) - // (op 39) Deallocate{}(1837) BEGIN - // (op 1837) Deallocate 594 - // Deleting tag 594 - // (op 39) Deallocate{}(1837) END -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 -// VMEM: Expected complete at 1964 (current 1889) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 -// VMEM: Expected complete at 1971 (current 1896) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // (op 998) Generate Add(v[70:71]:U64, v54:R)U64 into VGPR Value: UInt64 x 1: v[70:71] - // (op 998) reg expression - // (op 998) reg expression - // (op 998) Add(v[70:71]:U64, v54:R)U64 - // (op 998) Add: dest (VGPR Value: UInt64 x 1: v[70:71]) = - // (op 998) lhs (VGPR Value: UInt64 x 1: v[70:71]) - // (op 998) rhs (VGPR Value: Raw32 x 1: v54) -// Allocated : 2 SGPRs (Value: Bool64) (op 998): s48, s49 -v_add_co_u32 v70, s[48:49], v70, v54 // (op 998) least significant half -v_addc_co_u32 v71, s[48:49], 0, v71, s[48:49] // (op 998) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 998): s48, s49 - - // (op 998) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 998) reg expression - // (op 998) Add(m0:U32, 1024:U32)U32 - // (op 998) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 998) - // (op 998) Expression temporary in special register - // Unlock None -buffer_load_dword v70, s[36:39], s46 offen offset: 0 lds // (op 998) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 -// VMEM: Expected complete at 1977 (current 1902) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 16384, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 998): s46 - - // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 998): v54, v55 - - // Freeing : 2 VGPRs (Value: UInt64) (op 998): v70, v71 - - // Freeing : 1 SGPR (Value: UInt32) (op 998): s45 - - // (op 615) LoadTileDirect2LDS Value: Halfx2(998) END - // (op 615) Deallocate{}(1885) BEGIN - // (op 1885) Deallocate 574 - // Deleting tag 574 - // (op 615) Deallocate{}(1885) END - // (op 615) end: generate({998}) - // (op 39) SetCoordinate(615) END - // (op 39) Barrier(1743) BEGIN -s_barrier // (op 1743) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 39) Barrier(1743) END - // (op 39) SetCoordinate(610) BEGIN - // (op 610) generate({}) - // (op 610) end: generate({}) - // (op 610) generate({993}) - // (op 610) LoadTileDirect2LDS Value: Halfx2(993) BEGIN - // (op 993) GEN: LoadTileDirect2LDS - // (op 993) GEN: loadMacroTileDirect2LDS OP 993 LDS 356 MacroTile 354 - // (op 993) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 993) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) - // (op 993) Get arg Tensor_0_stride_0_9 - // (op 993) reg expression - // (op 993) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 993) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 993) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 993) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 -s_lshl_b64 s[46:47], s[18:19], 3 // (op 993) - // (op 993) convert - // (op 993) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 993) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 993) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 993) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 993): v50, v51 -v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 993) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 993): s46, s47 - - // (op 993) Generate 2:U64 into nullptr - // (op 993) Generate 1024:U32 into nullptr - // (op 993) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 24576 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[50:51] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 993): v54, v55 -v_mov_b64 v[54:55], v[68:69] // (op 993) - // (op 993) Generate Add(24576:U32, {DataFlowTag560: s16:U32})U32 into nullptr - // (op 993) reg expression - // (op 993) Add(24576:U32, {DataFlowTag560: s16:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 993): s45 -s_add_u32 s45, 24576, s16 // (op 993) - // (op 993) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 993) Generate s45:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s45 // (op 993) reg expression - // (op 993) Generate 640:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 640 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 -s_mov_b32 s46, 640 // (op 993) call() -// 640 is not a supported value! -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 48. CBNW: 36, Inc: 4 -// VMEM: Expected complete at 2033 (current 1958) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 -// VMEM: Expected complete at 2040 (current 1965) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 -// VMEM: Expected complete at 2047 (current 1972) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 -// VMEM: Expected complete at 2053 (current 1978) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 -// VMEM: Expected complete at 2109 (current 2034) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 -// VMEM: Expected complete at 2116 (current 2041) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 -// VMEM: Expected complete at 2123 (current 2048) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // (op 993) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 993) reg expression - // (op 993) reg expression - // (op 993) Add(v[54:55]:U64, v50:R)U64 - // (op 993) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 993) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 993) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 993): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 993) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 993) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 993): s48, s49 - - // (op 993) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 993) reg expression - // (op 993) Add(m0:U32, 1024:U32)U32 - // (op 993) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 993) - // (op 993) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 993) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 -// VMEM: Expected complete at 2129 (current 2054) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 24576, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 993): s46 - - // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 993): v50, v51 - - // Freeing : 2 VGPRs (Value: UInt64) (op 993): v54, v55 - - // Freeing : 1 SGPR (Value: UInt32) (op 993): s45 - - // (op 610) LoadTileDirect2LDS Value: Halfx2(993) END - // (op 610) Deallocate{}(1883) BEGIN - // (op 1883) Deallocate 562 - // Deleting tag 562 - // (op 610) Deallocate{}(1883) END - // (op 610) end: generate({993}) - // (op 39) SetCoordinate(610) END - // (op 39) NOP(1010) BEGIN - // (op 1010) generate({}) - // (op 1010) end: generate({}) - // (op 39) NOP(1010) END - // (op 39) NOP(1005) BEGIN - // (op 1005) generate({}) - // (op 1005) end: generate({}) - // (op 39) NOP(1005) END - // (op 39) NOP(800) BEGIN - // (op 800) generate({}) - // (op 800) end: generate({}) - // (op 39) NOP(800) END - // (op 39) Multiply(424) BEGIN - // (op 424) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) Barrier(895) BEGIN - // (op 39) Barrier(1752) BEGIN -s_waitcnt vmcnt(32) -s_barrier // (op 895) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 39) Barrier(895) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 424) - // (op 39) Multiply(424) END -s_barrier // (op 1752) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 39) Barrier(1752) END - // (op 39) Deallocate{}(1823) BEGIN - // (op 1823) Deallocate 402 - // Deleting tag 402alias (-> 11) - // (op 1823) Deallocate 404 - // Deleting tag 404alias (-> 19) - // (op 39) Deallocate{}(1823) END - // (op 39) SetCoordinate(629) BEGIN - // (op 629) generate({}) - // (op 629) end: generate({}) - // (op 629) generate({1008}) - // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) BEGIN - // (op 1008) GEN: LoadTileDirect2LDS - // (op 1008) GEN: loadMacroTileDirect2LDS OP 1008 LDS 400 MacroTile 398 - // (op 1008) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1008) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) - // (op 1008) Get arg Tensor_2_stride_1_12 - // (op 1008) reg expression - // (op 1008) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1008) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1008) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 3) - // (op 39) Multiply(429) BEGIN - // (op 429) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(512) BEGIN - // (op 512) generate({}) - // (op 512) end: generate({}) - // (op 512) generate({513}) - // (op 512) LoadLDSTile{Value: Halfx2}(513) BEGIN - // (op 513) GEN: loadMacroTileWAVELDS OP 513 LDS 440 WaveTile 145 - // (op 513) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 513) Generate 2:U32 into nullptr - // tag 444: v[12:13] alias 444 -> 19 - // (op 513) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 513) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 513) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[12:13], v9 offset:49152 // (op 513) Load local data -// DSMEM: Expected complete at 2080 (current 2060) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 512) LoadLDSTile{Value: Halfx2}(513) END - // (op 512) end: generate({513}) - // (op 39) SetCoordinate(512) END -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 -s_lshl_b64 s[46:47], s[22:23], 3 // (op 1008) - // (op 1008) convert - // (op 1008) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 1008) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1008) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 1008) shiftAmount (Literal Value: UInt32 x 0: 1) - // (op 39) SetCoordinate(517) BEGIN - // (op 517) generate({}) - // (op 517) end: generate({}) - // (op 517) generate({518}) - // (op 517) LoadLDSTile{Value: Halfx2}(518) BEGIN - // (op 518) GEN: loadMacroTileWAVELDS OP 518 LDS 440 WaveTile 145 - // (op 518) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 518) Generate 2:U32 into nullptr - // tag 448: v**UNALLOCATED** - // (op 518) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 518) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49168 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 518) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1008): v50, v51 -v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1008) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1008): s46, s47 - - // (op 1008) Generate 2:U64 into nullptr - // (op 1008) Generate 1024:U32 into nullptr - // (op 1008) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 32768 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1008): v54, v55 -v_mov_b64 v[54:55], v[52:53] // (op 1008) - // (op 1008) Generate Add(32768:U32, {DataFlowTag596: s41:U32})U32 into nullptr - // (op 1008) reg expression - // (op 1008) Add(32768:U32, {DataFlowTag596: s41:U32})U32 -// Allocated : 2 VGPRs (Value: Halfx2) (op 518): v56, v57 -ds_read_b64 v[56:57], v9 offset:49168 // (op 518) Load local data -// DSMEM: Expected complete at 2084 (current 2064) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 517) LoadLDSTile{Value: Halfx2}(518) END - // (op 517) end: generate({518}) - // (op 39) SetCoordinate(517) END -// Allocated : 1 SGPR (Value: UInt32) (op 1008): s45 -s_add_u32 s45, 32768, s41 // (op 1008) - // (op 1008) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1008) Generate s45:U32 into M0 Value: UInt32 x 1: m0 - // (op 39) SetCoordinate(522) BEGIN - // (op 522) generate({}) - // (op 522) end: generate({}) - // (op 522) generate({523}) - // (op 522) LoadLDSTile{Value: Halfx2}(523) BEGIN - // (op 523) GEN: loadMacroTileWAVELDS OP 523 LDS 440 WaveTile 145 - // (op 523) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 523) Generate 2:U32 into nullptr - // tag 452: v**UNALLOCATED** - // (op 523) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 523) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49184 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 523) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -s_mov_b32 m0, s45 // (op 1008) reg expression - // (op 1008) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 768 is not a supported value! -// Allocated : 2 VGPRs (Value: Halfx2) (op 523): v58, v59 -ds_read_b64 v[58:59], v9 offset:49184 // (op 523) Load local data -// DSMEM: Expected complete at 2087 (current 2067) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 522) LoadLDSTile{Value: Halfx2}(523) END - // (op 522) end: generate({523}) - // (op 39) SetCoordinate(522) END -s_waitcnt lgkmcnt(9) -v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[16:17], a[0:15] // (op 429) - // (op 39) Multiply(429) END - // (op 39) SetCoordinate(527) BEGIN - // (op 527) generate({}) - // (op 527) end: generate({}) - // (op 527) generate({528}) - // (op 527) LoadLDSTile{Value: Halfx2}(528) BEGIN - // (op 528) GEN: loadMacroTileWAVELDS OP 528 LDS 440 WaveTile 145 - // (op 528) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 528) Generate 2:U32 into nullptr - // tag 456: v**UNALLOCATED** - // (op 528) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 528) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49200 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 528) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1825) BEGIN - // (op 1825) Deallocate 406 - // Deleting tag 406alias (-> 253) - // (op 1825) Deallocate 408 - // Deleting tag 408alias (-> 255) - // (op 39) Deallocate{}(1825) END -// Allocated : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 -ds_read_b64 v[60:61], v9 offset:49200 // (op 528) Load local data -// DSMEM: Expected complete at 2090 (current 2070) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 527) LoadLDSTile{Value: Halfx2}(528) END - // (op 527) end: generate({528}) - // (op 39) SetCoordinate(527) END - // (op 39) Multiply(434) BEGIN - // (op 434) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(532) BEGIN - // (op 532) generate({}) - // (op 532) end: generate({}) - // (op 532) generate({533}) - // (op 532) LoadLDSTile{Value: Halfx2}(533) BEGIN - // (op 533) GEN: loadMacroTileWAVELDS OP 533 LDS 440 WaveTile 145 - // (op 533) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 533) Generate 2:U32 into nullptr - // tag 460: v**UNALLOCATED** - // (op 533) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 533) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49216 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 533) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 -s_mov_b32 s46, 768 // (op 1008) call() -// 768 is not a supported value! -s_waitcnt lgkmcnt(9) -v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[20:21], a[0:15] // (op 434) - // (op 39) Multiply(434) END -// Allocated : 2 VGPRs (Value: Halfx2) (op 533): v62, v63 -ds_read_b64 v[62:63], v9 offset:49216 // (op 533) Load local data -// DSMEM: Expected stall of 1. CBNW: 5, Inc: 4 -// DSMEM: Expected complete at 2101 (current 2081) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 532) LoadLDSTile{Value: Halfx2}(533) END - // (op 532) end: generate({533}) - // (op 39) SetCoordinate(532) END - // (op 39) Deallocate{}(1827) BEGIN - // (op 1827) Deallocate 410 - // Deleting tag 410alias (-> 257) - // (op 1827) Deallocate 412 - // Deleting tag 412alias (-> 259) - // (op 39) Deallocate{}(1827) END - // (op 39) SetCoordinate(537) BEGIN - // (op 537) generate({}) - // (op 537) end: generate({}) - // (op 537) generate({538}) - // (op 537) LoadLDSTile{Value: Halfx2}(538) BEGIN - // (op 538) GEN: loadMacroTileWAVELDS OP 538 LDS 440 WaveTile 145 - // (op 538) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 538) Generate 2:U32 into nullptr - // tag 464: v**UNALLOCATED** - // (op 538) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 538) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49232 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 538) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(439) BEGIN - // (op 439) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -// Allocated : 2 VGPRs (Value: Halfx2) (op 538): v64, v65 -ds_read_b64 v[64:65], v9 offset:49232 // (op 538) Load local data -// DSMEM: Expected stall of 3. CBNW: 6, Inc: 4 -// DSMEM: Expected complete at 2105 (current 2085) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 537) LoadLDSTile{Value: Halfx2}(538) END - // (op 537) end: generate({538}) - // (op 39) SetCoordinate(537) END -s_waitcnt lgkmcnt(10) -v_mfma_f32_32x32x8f16 a[0:15], v[42:43], v[22:23], a[0:15] // (op 439) - // (op 39) Multiply(439) END - // (op 39) SetCoordinate(542) BEGIN - // (op 542) generate({}) - // (op 542) end: generate({}) - // (op 542) generate({543}) - // (op 542) LoadLDSTile{Value: Halfx2}(543) BEGIN - // (op 543) GEN: loadMacroTileWAVELDS OP 543 LDS 440 WaveTile 145 - // (op 543) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 543) Generate 2:U32 into nullptr - // tag 468: v**UNALLOCATED** - // (op 543) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 543) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49248 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 543) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1829) BEGIN - // (op 1829) Deallocate 414 - // Deleting tag 414alias (-> 269) - // (op 1829) Deallocate 416 - // Deleting tag 416alias (-> 263) - // (op 39) Deallocate{}(1829) END -// Allocated : 2 VGPRs (Value: Halfx2) (op 543): v66, v67 -ds_read_b64 v[66:67], v9 offset:49248 // (op 543) Load local data -// DSMEM: Expected complete at 2110 (current 2090) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 542) LoadLDSTile{Value: Halfx2}(543) END - // (op 542) end: generate({543}) - // (op 39) SetCoordinate(542) END - // (op 39) Multiply(444) BEGIN - // (op 444) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(547) BEGIN - // (op 547) generate({}) - // (op 547) end: generate({}) - // (op 547) generate({548}) - // (op 547) LoadLDSTile{Value: Halfx2}(548) BEGIN - // (op 548) GEN: loadMacroTileWAVELDS OP 548 LDS 440 WaveTile 145 - // (op 548) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 548) Generate 2:U32 into nullptr - // tag 472: v**UNALLOCATED** - // (op 548) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49152 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 548) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag628: VGPR Value: UInt32 x 1: v9 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 49264 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 548) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 -ds_read_b64 v[70:71], v9 offset:49264 // (op 548) Load local data -// DSMEM: Expected complete at 2111 (current 2091) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 547) LoadLDSTile{Value: Halfx2}(548) END - // (op 547) end: generate({548}) - // (op 39) SetCoordinate(547) END -s_waitcnt lgkmcnt(11) -v_mfma_f32_32x32x8f16 a[0:15], v[44:45], v[24:25], a[0:15] // (op 444) - // (op 39) Multiply(444) END - // (op 39) Deallocate{}(1859) BEGIN - // (op 1859) Deallocate 630 - // Deleting tag 630 - // (op 39) Deallocate{}(1859) END - // (op 39) Deallocate{}(1831) BEGIN - // (op 1831) Deallocate 418 - // Deleting tag 418alias (-> 273) - // (op 1831) Deallocate 420 - // Deleting tag 420alias (-> 267) - // (op 39) Deallocate{}(1831) END - // (op 39) SetCoordinate(510) BEGIN - // (op 510) generate({}) - // (op 510) end: generate({}) - // (op 510) generate({511}) - // (op 510) LoadLDSTile{Value: Halfx2}(511) BEGIN - // (op 511) GEN: loadMacroTileWAVELDS OP 511 LDS 436 WaveTile 85 - // (op 511) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 511) Generate 2:U32 into nullptr - // tag 442: v[32:33] alias 442 -> 11 - // (op 511) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 511) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 511) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(449) BEGIN - // (op 449) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -ds_read_b64 v[32:33], v8 offset:57344 // (op 511) Load local data -// DSMEM: Expected stall of 2. CBNW: 7, Inc: 4 -// DSMEM: Expected complete at 2122 (current 2102) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 510) LoadLDSTile{Value: Halfx2}(511) END - // (op 510) end: generate({511}) - // (op 39) SetCoordinate(510) END -s_waitcnt lgkmcnt(11) -v_mfma_f32_32x32x8f16 a[0:15], v[46:47], v[26:27], a[0:15] // (op 449) - // (op 39) Multiply(449) END - // (op 39) SetCoordinate(515) BEGIN - // (op 515) generate({}) - // (op 515) end: generate({}) - // (op 515) generate({516}) - // (op 515) LoadLDSTile{Value: Halfx2}(516) BEGIN - // (op 516) GEN: loadMacroTileWAVELDS OP 516 LDS 436 WaveTile 85 - // (op 516) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 516) Generate 2:U32 into nullptr - // tag 446: v[34:35] alias 446 -> 253 - // (op 516) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 516) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57360 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 516) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1833) BEGIN - // (op 1833) Deallocate 422 - // Deleting tag 422alias (-> 277) - // (op 1833) Deallocate 424 - // Deleting tag 424alias (-> 271) - // (op 39) Deallocate{}(1833) END -ds_read_b64 v[34:35], v8 offset:57360 // (op 516) Load local data -// DSMEM: Expected complete at 2130 (current 2110) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 515) LoadLDSTile{Value: Halfx2}(516) END - // (op 515) end: generate({516}) - // (op 39) SetCoordinate(515) END - // (op 39) Multiply(454) BEGIN - // (op 454) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(520) BEGIN - // (op 520) generate({}) - // (op 520) end: generate({}) - // (op 520) generate({521}) - // (op 520) LoadLDSTile{Value: Halfx2}(521) BEGIN - // (op 521) GEN: loadMacroTileWAVELDS OP 521 LDS 436 WaveTile 85 - // (op 521) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 521) Generate 2:U32 into nullptr - // tag 450: v[36:37] alias 450 -> 257 - // (op 521) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 521) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57376 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 521) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[36:37], v8 offset:57376 // (op 521) Load local data -// DSMEM: Expected complete at 2131 (current 2111) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 520) LoadLDSTile{Value: Halfx2}(521) END - // (op 520) end: generate({521}) - // (op 39) SetCoordinate(520) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected complete at 2187 (current 2112) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(525) BEGIN - // (op 525) generate({}) - // (op 525) end: generate({}) - // (op 525) generate({526}) - // (op 525) LoadLDSTile{Value: Halfx2}(526) BEGIN - // (op 526) GEN: loadMacroTileWAVELDS OP 526 LDS 436 WaveTile 85 - // (op 526) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 526) Generate 2:U32 into nullptr - // tag 454: v[40:41] alias 454 -> 265 - // (op 526) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 526) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57392 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 526) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[40:41], v8 offset:57392 // (op 526) Load local data -// DSMEM: Expected complete at 2133 (current 2113) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 525) LoadLDSTile{Value: Halfx2}(526) END - // (op 525) end: generate({526}) - // (op 39) SetCoordinate(525) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half - // (op 39) SetCoordinate(530) BEGIN - // (op 530) generate({}) - // (op 530) end: generate({}) - // (op 530) generate({531}) - // (op 530) LoadLDSTile{Value: Halfx2}(531) BEGIN - // (op 531) GEN: loadMacroTileWAVELDS OP 531 LDS 436 WaveTile 85 - // (op 531) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 531) Generate 2:U32 into nullptr - // tag 458: v**UNALLOCATED** - // (op 531) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 531) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57408 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 531) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected complete at 2192 (current 2117) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) -s_waitcnt lgkmcnt(13) -v_mfma_f32_32x32x8f16 a[0:15], v[38:39], v[28:29], a[0:15] // (op 454) - // (op 39) Multiply(454) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half - // (op 39) Deallocate{}(1835) BEGIN - // (op 1835) Deallocate 426 - // Deleting tag 426alias (-> 261) - // (op 1835) Deallocate 428 - // Deleting tag 428alias (-> 275) - // (op 39) Deallocate{}(1835) END -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 39) Multiply(459) BEGIN - // (op 459) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 -ds_read_b64 v[72:73], v8 offset:57408 // (op 531) Load local data -// DSMEM: Expected complete at 2143 (current 2123) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 530) LoadLDSTile{Value: Halfx2}(531) END - // (op 530) end: generate({531}) - // (op 39) SetCoordinate(530) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected complete at 2199 (current 2124) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(535) BEGIN - // (op 535) generate({}) - // (op 535) end: generate({}) - // (op 535) generate({536}) - // (op 535) LoadLDSTile{Value: Halfx2}(536) BEGIN - // (op 536) GEN: loadMacroTileWAVELDS OP 536 LDS 436 WaveTile 85 - // (op 536) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 536) Generate 2:U32 into nullptr - // tag 462: v**UNALLOCATED** - // (op 536) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 536) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57424 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 536) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -s_waitcnt lgkmcnt(13) -v_mfma_f32_32x32x8f16 a[0:15], v[48:49], v[30:31], a[0:15] // (op 459) - // (op 39) Multiply(459) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected complete at 2205 (current 2130) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) Deallocate{}(1841) BEGIN - // (op 1841) Deallocate 430 - // Freeing : 2 VGPRs (Value: Halfx2) (op 456): v48, v49 - - // Deleting tag 430 - // (op 1841) Deallocate 432 - // Deleting tag 432alias (-> 279) - // (op 39) Deallocate{}(1841) END -// Allocated : 2 VGPRs (Value: Halfx2) (op 536): v48, v49 -ds_read_b64 v[48:49], v8 offset:57424 // (op 536) Load local data -// DSMEM: Expected complete at 2151 (current 2131) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 535) LoadLDSTile{Value: Halfx2}(536) END - // (op 535) end: generate({536}) - // (op 39) SetCoordinate(535) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half - // (op 39) SetCoordinate(540) BEGIN - // (op 540) generate({}) - // (op 540) end: generate({}) - // (op 540) generate({541}) - // (op 540) LoadLDSTile{Value: Halfx2}(541) BEGIN - // (op 541) GEN: loadMacroTileWAVELDS OP 541 LDS 436 WaveTile 85 - // (op 541) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 541) Generate 2:U32 into nullptr - // tag 466: v**UNALLOCATED** - // (op 541) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 541) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57440 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 541) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 -ds_read_b64 v[74:75], v8 offset:57440 // (op 541) Load local data -// DSMEM: Expected complete at 2155 (current 2135) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 540) LoadLDSTile{Value: Halfx2}(541) END - // (op 540) end: generate({541}) - // (op 39) SetCoordinate(540) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected stall of 52. CBNW: 32, Inc: 4 -// VMEM: Expected complete at 2263 (current 2188) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(545) BEGIN - // (op 545) generate({}) - // (op 545) end: generate({}) - // (op 545) generate({546}) - // (op 545) LoadLDSTile{Value: Halfx2}(546) BEGIN - // (op 546) GEN: loadMacroTileWAVELDS OP 546 LDS 436 WaveTile 85 - // (op 546) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 546) Generate 2:U32 into nullptr - // tag 470: v**UNALLOCATED** - // (op 546) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57344 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 546) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag616: VGPR Value: UInt32 x 1: v8 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 57456 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 546) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -// Allocated : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 -ds_read_b64 v[76:77], v8 offset:57456 // (op 546) Load local data -// DSMEM: Expected complete at 2212 (current 2192) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 545) LoadLDSTile{Value: Halfx2}(546) END - // (op 545) end: generate({546}) - // (op 39) SetCoordinate(545) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected complete at 2268 (current 2193) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) Deallocate{}(1857) BEGIN - // (op 1857) Deallocate 618 - // Deleting tag 618 - // (op 39) Deallocate{}(1857) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 34, Inc: 4 -// VMEM: Expected complete at 2275 (current 2200) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // (op 1008) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1008) reg expression - // (op 1008) reg expression - // (op 1008) Add(v[54:55]:U64, v50:R)U64 - // (op 1008) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1008) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1008) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1008) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1008) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1008): s48, s49 - - // (op 1008) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1008) reg expression - // (op 1008) Add(m0:U32, 1024:U32)U32 - // (op 1008) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1008) - // (op 1008) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1008) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 35, Inc: 4 -// VMEM: Expected complete at 2281 (current 2206) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 32768, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1008): s46 - - // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1008): v50, v51 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1008): v54, v55 - - // Freeing : 1 SGPR (Value: UInt32) (op 1008): s45 - - // (op 629) LoadTileDirect2LDS Value: Halfx2(1008) END - // (op 629) Deallocate{}(1889) BEGIN - // (op 1889) Deallocate 598 - // Deleting tag 598 - // (op 629) Deallocate{}(1889) END - // (op 629) end: generate({1008}) - // (op 39) SetCoordinate(629) END - // (op 39) Barrier(1749) BEGIN -s_barrier // (op 1749) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 39) Barrier(1749) END - // (op 39) SetCoordinate(624) BEGIN - // (op 624) generate({}) - // (op 624) end: generate({}) - // (op 624) generate({1003}) - // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) BEGIN - // (op 1003) GEN: LoadTileDirect2LDS - // (op 1003) GEN: loadMacroTileDirect2LDS OP 1003 LDS 396 MacroTile 394 - // (op 1003) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1003) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) - // (op 1003) Get arg Tensor_0_stride_0_9 - // (op 1003) reg expression - // (op 1003) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1003) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1003) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 -s_lshl_b64 s[46:47], s[18:19], 3 // (op 1003) - // (op 1003) convert - // (op 1003) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 1003) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1003) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 1003) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1003): v50, v51 -v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1003) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1003): s46, s47 - - // (op 1003) Generate 2:U64 into nullptr - // (op 1003) Generate 1024:U32 into nullptr - // (op 1003) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 40960 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[50:51] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1003): v54, v55 -v_mov_b64 v[54:55], v[68:69] // (op 1003) - // (op 1003) Generate Add(40960:U32, {DataFlowTag584: s40:U32})U32 into nullptr - // (op 1003) reg expression - // (op 1003) Add(40960:U32, {DataFlowTag584: s40:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1003): s45 -s_add_u32 s45, 40960, s40 // (op 1003) - // (op 1003) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1003) Generate s45:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s45 // (op 1003) reg expression - // (op 1003) Generate 768:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 768 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 -s_mov_b32 s46, 768 // (op 1003) call() -// 768 is not a supported value! -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 50. CBNW: 36, Inc: 4 -// VMEM: Expected complete at 2339 (current 2264) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 37, Inc: 4 -// VMEM: Expected complete at 2344 (current 2269) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 38, Inc: 4 -// VMEM: Expected complete at 2351 (current 2276) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 39, Inc: 4 -// VMEM: Expected complete at 2357 (current 2282) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 54. CBNW: 40, Inc: 4 -// VMEM: Expected complete at 2415 (current 2340) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 41, Inc: 4 -// VMEM: Expected complete at 2420 (current 2345) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 42, Inc: 4 -// VMEM: Expected complete at 2427 (current 2352) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // (op 1003) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1003) reg expression - // (op 1003) reg expression - // (op 1003) Add(v[54:55]:U64, v50:R)U64 - // (op 1003) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1003) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1003) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1003) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1003) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1003): s48, s49 - - // (op 1003) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1003) reg expression - // (op 1003) Add(m0:U32, 1024:U32)U32 - // (op 1003) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1003) - // (op 1003) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[32:35], s46 offen offset: 0 lds // (op 1003) Load value direct to lds -// VMEM: Expected stall of 2. CBNW: 43, Inc: 4 -// VMEM: Expected complete at 2433 (current 2358) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 40960, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1003): s46 - - // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1003): v50, v51 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1003): v54, v55 - - // Freeing : 1 SGPR (Value: UInt32) (op 1003): s45 - - // (op 624) LoadTileDirect2LDS Value: Halfx2(1003) END - // (op 624) Deallocate{}(1887) BEGIN - // (op 1887) Deallocate 586 - // Deleting tag 586 - // (op 624) Deallocate{}(1887) END - // (op 624) end: generate({1003}) - // (op 39) SetCoordinate(624) END - // (op 39) NOP(1020) BEGIN - // (op 1020) generate({}) - // (op 1020) end: generate({}) - // (op 39) NOP(1020) END - // (op 39) NOP(1015) BEGIN - // (op 1015) generate({}) - // (op 1015) end: generate({}) - // (op 39) NOP(1015) END - // (op 39) NOP(801) BEGIN - // (op 801) generate({}) - // (op 801) end: generate({}) - // (op 39) NOP(801) END - // (op 39) Multiply(514) BEGIN - // (op 514) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) Barrier(937) BEGIN - // (op 39) Barrier(1758) BEGIN -s_waitcnt vmcnt(32) -s_barrier // (op 937) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 39) Barrier(937) END -s_waitcnt lgkmcnt(7) -v_mfma_f32_32x32x8f16 a[0:15], v[32:33], v[12:13], a[0:15] // (op 514) - // (op 39) Multiply(514) END -s_barrier // (op 1758) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 39) Barrier(1758) END - // (op 39) Deallocate{}(1843) BEGIN - // (op 1843) Deallocate 442 - // Deleting tag 442alias (-> 11) - // (op 1843) Deallocate 444 - // Deleting tag 444alias (-> 19) - // (op 39) Deallocate{}(1843) END - // (op 39) SetCoordinate(643) BEGIN - // (op 643) generate({}) - // (op 643) end: generate({}) - // (op 643) generate({1018}) - // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) BEGIN - // (op 1018) GEN: LoadTileDirect2LDS - // (op 1018) GEN: loadMacroTileDirect2LDS OP 1018 LDS 440 MacroTile 438 - // (op 1018) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1018) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride509: VGPR Value: UInt64 x 1: (unallocated) - // (op 1018) Get arg Tensor_2_stride_1_12 - // (op 1018) reg expression - // (op 1018) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 1018) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1018) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 3) - // (op 39) SetCoordinate(52) BEGIN - // (op 52) generate({}) - // (op 52) end: generate({}) - // (op 52) generate({54}) - // (op 52) LoadLDSTile{Value: Halfx2}(54) BEGIN - // (op 54) GEN: loadMacroTileWAVELDS OP 54 LDS 21 WaveTile 145 - // (op 54) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 54) Generate 2:U32 into nullptr - // (op 54) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 54) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[12:13] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 54) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(519) BEGIN - // (op 519) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -ds_read_b64 v[12:13], v3 // (op 54) Load local data -// DSMEM: Expected complete at 2384 (current 2364) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 52) LoadLDSTile{Value: Halfx2}(54) END - // (op 52) end: generate({54}) - // (op 39) SetCoordinate(52) END -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 -s_lshl_b64 s[46:47], s[22:23], 3 // (op 1018) - // (op 1018) convert - // (op 1018) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 1018) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1018) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 1018) shiftAmount (Literal Value: UInt32 x 0: 1) - // (op 39) SetCoordinate(62) BEGIN - // (op 62) generate({}) - // (op 62) end: generate({}) - // (op 62) generate({64}) - // (op 62) LoadLDSTile{Value: Halfx2}(64) BEGIN - // (op 64) GEN: loadMacroTileWAVELDS OP 64 LDS 21 WaveTile 145 - // (op 64) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 64) Generate 2:U32 into nullptr - // (op 64) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[16:17] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 64) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[16:17] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 64) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[16:17], v3 offset:16 // (op 64) Load local data -// DSMEM: Expected complete at 2386 (current 2366) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 62) LoadLDSTile{Value: Halfx2}(64) END - // (op 62) end: generate({64}) - // (op 39) SetCoordinate(62) END -// Allocated Stride509: 2 VGPRs (Value: UInt64) (op 1018): v50, v51 -v_lshlrev_b64 v[50:51], 1, s[46:47] // (op 1018) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1018): s46, s47 - - // (op 1018) Generate 2:U64 into nullptr - // (op 1018) Generate 1024:U32 into nullptr - // (op 1018) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 49152 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride509: VGPR Value: UInt64 x 1: v[50:51] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // (op 39) SetCoordinate(71) BEGIN - // (op 71) generate({}) - // (op 71) end: generate({}) - // (op 71) generate({73}) - // (op 71) LoadLDSTile{Value: Halfx2}(73) BEGIN - // (op 73) GEN: loadMacroTileWAVELDS OP 73 LDS 21 WaveTile 145 - // (op 73) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 73) Generate 2:U32 into nullptr - // (op 73) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[20:21] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 73) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[20:21] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 73) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[20:21], v3 offset:32 // (op 73) Load local data -// DSMEM: Expected complete at 2388 (current 2368) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 71) LoadLDSTile{Value: Halfx2}(73) END - // (op 71) end: generate({73}) - // (op 39) SetCoordinate(71) END -// Allocated : 2 VGPRs (Value: UInt64) (op 1018): v54, v55 -v_mov_b64 v[54:55], v[52:53] // (op 1018) - // (op 1018) Generate Add(49152:U32, {DataFlowTag620: s43:U32})U32 into nullptr - // (op 1018) reg expression - // (op 1018) Add(49152:U32, {DataFlowTag620: s43:U32})U32 - // (op 39) SetCoordinate(80) BEGIN - // (op 80) generate({}) - // (op 80) end: generate({}) - // (op 80) generate({82}) - // (op 80) LoadLDSTile{Value: Halfx2}(82) BEGIN - // (op 82) GEN: loadMacroTileWAVELDS OP 82 LDS 21 WaveTile 145 - // (op 82) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 82) Generate 2:U32 into nullptr - // (op 82) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[22:23] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 82) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[22:23] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 48 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 82) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[22:23], v3 offset:48 // (op 82) Load local data -// DSMEM: Expected complete at 2390 (current 2370) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 80) LoadLDSTile{Value: Halfx2}(82) END - // (op 80) end: generate({82}) - // (op 39) SetCoordinate(80) END -s_waitcnt lgkmcnt(10) -v_mfma_f32_32x32x8f16 a[0:15], v[34:35], v[56:57], a[0:15] // (op 519) - // (op 39) Multiply(519) END - // (op 39) SetCoordinate(89) BEGIN - // (op 89) generate({}) - // (op 89) end: generate({}) - // (op 89) generate({91}) - // (op 89) LoadLDSTile{Value: Halfx2}(91) BEGIN - // (op 91) GEN: loadMacroTileWAVELDS OP 91 LDS 21 WaveTile 145 - // (op 91) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 91) Generate 2:U32 into nullptr - // (op 91) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[24:25] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 91) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[24:25] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 64 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 91) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1845) BEGIN - // (op 1845) Deallocate 446 - // Deleting tag 446alias (-> 253) - // (op 1845) Deallocate 448 - // Freeing : 2 VGPRs (Value: Halfx2) (op 518): v56, v57 - - // Deleting tag 448 - // (op 39) Deallocate{}(1845) END -// Allocated : 1 SGPR (Value: UInt32) (op 1018): s45 -s_add_u32 s45, 49152, s43 // (op 1018) - // (op 1018) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride509: v[50:51]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1018) Generate s45:U32 into M0 Value: UInt32 x 1: m0 - // (op 39) Multiply(524) BEGIN - // (op 524) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_mov_b32 m0, s45 // (op 1018) reg expression - // (op 1018) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 896 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 -s_mov_b32 s46, 896 // (op 1018) call() -// 896 is not a supported value! -s_waitcnt lgkmcnt(9) -v_mfma_f32_32x32x8f16 a[0:15], v[36:37], v[58:59], a[0:15] // (op 524) - // (op 39) Multiply(524) END -ds_read_b64 v[24:25], v3 offset:64 // (op 91) Load local data -// DSMEM: Expected stall of 2. CBNW: 5, Inc: 4 -// DSMEM: Expected complete at 2405 (current 2385) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 89) LoadLDSTile{Value: Halfx2}(91) END - // (op 89) end: generate({91}) - // (op 39) SetCoordinate(89) END - // (op 39) Deallocate{}(1847) BEGIN - // (op 1847) Deallocate 450 - // Deleting tag 450alias (-> 257) - // (op 1847) Deallocate 452 - // Freeing : 2 VGPRs (Value: Halfx2) (op 523): v58, v59 - - // Deleting tag 452 - // (op 39) Deallocate{}(1847) END - // (op 39) SetCoordinate(98) BEGIN - // (op 98) generate({}) - // (op 98) end: generate({}) - // (op 98) generate({100}) - // (op 98) LoadLDSTile{Value: Halfx2}(100) BEGIN - // (op 100) GEN: loadMacroTileWAVELDS OP 100 LDS 21 WaveTile 145 - // (op 100) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 100) Generate 2:U32 into nullptr - // (op 100) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[26:27] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 100) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[26:27] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 80 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 100) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Multiply(529) BEGIN - // (op 529) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -ds_read_b64 v[26:27], v3 offset:80 // (op 100) Load local data -// DSMEM: Expected stall of 1. CBNW: 6, Inc: 4 -// DSMEM: Expected complete at 2407 (current 2387) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 98) LoadLDSTile{Value: Halfx2}(100) END - // (op 98) end: generate({100}) - // (op 39) SetCoordinate(98) END -s_waitcnt lgkmcnt(10) -v_mfma_f32_32x32x8f16 a[0:15], v[40:41], v[60:61], a[0:15] // (op 529) - // (op 39) Multiply(529) END - // (op 39) SetCoordinate(107) BEGIN - // (op 107) generate({}) - // (op 107) end: generate({}) - // (op 107) generate({109}) - // (op 107) LoadLDSTile{Value: Halfx2}(109) BEGIN - // (op 109) GEN: loadMacroTileWAVELDS OP 109 LDS 21 WaveTile 145 - // (op 109) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 109) Generate 2:U32 into nullptr - // (op 109) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[28:29] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 109) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[28:29] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 96 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 109) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1849) BEGIN - // (op 1849) Deallocate 454 - // Deleting tag 454alias (-> 265) - // (op 1849) Deallocate 456 - // Freeing : 2 VGPRs (Value: Halfx2) (op 528): v60, v61 - - // Deleting tag 456 - // (op 39) Deallocate{}(1849) END -ds_read_b64 v[28:29], v3 offset:96 // (op 109) Load local data -// DSMEM: Expected complete at 2413 (current 2393) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 107) LoadLDSTile{Value: Halfx2}(109) END - // (op 107) end: generate({109}) - // (op 39) SetCoordinate(107) END - // (op 39) Multiply(534) BEGIN - // (op 534) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(116) BEGIN - // (op 116) generate({}) - // (op 116) end: generate({}) - // (op 116) generate({118}) - // (op 116) LoadLDSTile{Value: Halfx2}(118) BEGIN - // (op 118) GEN: loadMacroTileWAVELDS OP 118 LDS 21 WaveTile 145 - // (op 118) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 118) Generate 2:U32 into nullptr - // (op 118) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[30:31] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 118) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[30:31] - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 112 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 118) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[30:31], v3 offset:112 // (op 118) Load local data -// DSMEM: Expected complete at 2414 (current 2394) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 116) LoadLDSTile{Value: Halfx2}(118) END - // (op 116) end: generate({118}) - // (op 39) SetCoordinate(116) END -s_waitcnt lgkmcnt(11) -v_mfma_f32_32x32x8f16 a[0:15], v[72:73], v[62:63], a[0:15] // (op 534) - // (op 39) Multiply(534) END - // (op 39) SetCoordinate(47) BEGIN - // (op 47) generate({}) - // (op 47) end: generate({}) - // (op 47) generate({49}) - // (op 47) LoadLDSTile{Value: Halfx2}(49) BEGIN - // (op 49) GEN: loadMacroTileWAVELDS OP 49 LDS 13 WaveTile 85 - // (op 49) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 49) Generate 2:U32 into nullptr - // (op 49) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 49) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[32:33] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 49) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1851) BEGIN - // (op 1851) Deallocate 458 - // Freeing : 2 VGPRs (Value: Halfx2) (op 531): v72, v73 - - // Deleting tag 458 - // (op 1851) Deallocate 460 - // Freeing : 2 VGPRs (Value: Halfx2) (op 533): v62, v63 - - // Deleting tag 460 - // (op 39) Deallocate{}(1851) END -ds_read_b64 v[32:33], v0 offset:8192 // (op 49) Load local data -// DSMEM: Expected stall of 3. CBNW: 7, Inc: 4 -// DSMEM: Expected complete at 2426 (current 2406) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 47) LoadLDSTile{Value: Halfx2}(49) END - // (op 47) end: generate({49}) - // (op 39) SetCoordinate(47) END - // (op 39) Multiply(539) BEGIN - // (op 539) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(58) BEGIN - // (op 58) generate({}) - // (op 58) end: generate({}) - // (op 58) generate({60}) - // (op 58) LoadLDSTile{Value: Halfx2}(60) BEGIN - // (op 60) GEN: loadMacroTileWAVELDS OP 60 LDS 13 WaveTile 85 - // (op 60) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 60) Generate 2:U32 into nullptr - // (op 60) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 60) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[34:35] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8208 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 60) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[34:35], v0 offset:8208 // (op 60) Load local data -// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 -// DSMEM: Expected complete at 2428 (current 2408) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 58) LoadLDSTile{Value: Halfx2}(60) END - // (op 58) end: generate({60}) - // (op 39) SetCoordinate(58) END -s_waitcnt lgkmcnt(12) -v_mfma_f32_32x32x8f16 a[0:15], v[48:49], v[64:65], a[0:15] // (op 539) - // (op 39) Multiply(539) END - // (op 39) SetCoordinate(67) BEGIN - // (op 67) generate({}) - // (op 67) end: generate({}) - // (op 67) generate({69}) - // (op 67) LoadLDSTile{Value: Halfx2}(69) BEGIN - // (op 69) GEN: loadMacroTileWAVELDS OP 69 LDS 13 WaveTile 85 - // (op 69) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 69) Generate 2:U32 into nullptr - // (op 69) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 69) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[36:37] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8224 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 69) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - - // (op 39) Deallocate{}(1853) BEGIN - // (op 1853) Deallocate 462 - // Freeing : 2 VGPRs (Value: Halfx2) (op 536): v48, v49 - - // Deleting tag 462 - // (op 1853) Deallocate 464 - // Freeing : 2 VGPRs (Value: Halfx2) (op 538): v64, v65 - - // Deleting tag 464 - // (op 39) Deallocate{}(1853) END -ds_read_b64 v[36:37], v0 offset:8224 // (op 69) Load local data -// DSMEM: Expected stall of 1. CBNW: 8, Inc: 4 -// DSMEM: Expected complete at 2434 (current 2414) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 67) LoadLDSTile{Value: Halfx2}(69) END - // (op 67) end: generate({69}) - // (op 39) SetCoordinate(67) END - // (op 39) Multiply(544) BEGIN - // (op 544) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] - // (op 39) SetCoordinate(76) BEGIN - // (op 76) generate({}) - // (op 76) end: generate({}) - // (op 76) generate({78}) - // (op 76) LoadLDSTile{Value: Halfx2}(78) BEGIN - // (op 78) GEN: loadMacroTileWAVELDS OP 78 LDS 13 WaveTile 85 - // (op 78) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 78) Generate 2:U32 into nullptr - // (op 78) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 78) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[38:39] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8240 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 78) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[38:39], v0 offset:8240 // (op 78) Load local data -// DSMEM: Expected complete at 2435 (current 2415) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 76) LoadLDSTile{Value: Halfx2}(78) END - // (op 76) end: generate({78}) - // (op 39) SetCoordinate(76) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected complete at 2491 (current 2416) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(85) BEGIN - // (op 85) generate({}) - // (op 85) end: generate({}) - // (op 85) generate({87}) - // (op 85) LoadLDSTile{Value: Halfx2}(87) BEGIN - // (op 87) GEN: loadMacroTileWAVELDS OP 87 LDS 13 WaveTile 85 - // (op 87) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 87) Generate 2:U32 into nullptr - // (op 87) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 87) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[40:41] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8256 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 87) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -s_waitcnt lgkmcnt(13) -v_mfma_f32_32x32x8f16 a[0:15], v[74:75], v[66:67], a[0:15] // (op 544) - // (op 39) Multiply(544) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected complete at 2498 (current 2423) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) Deallocate{}(1855) BEGIN - // (op 1855) Deallocate 466 - // Freeing : 2 VGPRs (Value: Halfx2) (op 541): v74, v75 - - // Deleting tag 466 - // (op 1855) Deallocate 468 - // Freeing : 2 VGPRs (Value: Halfx2) (op 543): v66, v67 - - // Deleting tag 468 - // (op 39) Deallocate{}(1855) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half - // (op 39) Multiply(549) BEGIN - // (op 549) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -ds_read_b64 v[40:41], v0 offset:8256 // (op 87) Load local data -// DSMEM: Expected complete at 2447 (current 2427) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 85) LoadLDSTile{Value: Halfx2}(87) END - // (op 85) end: generate({87}) - // (op 39) SetCoordinate(85) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected complete at 2503 (current 2428) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(94) BEGIN - // (op 94) generate({}) - // (op 94) end: generate({}) - // (op 94) generate({96}) - // (op 94) LoadLDSTile{Value: Halfx2}(96) BEGIN - // (op 96) GEN: loadMacroTileWAVELDS OP 96 LDS 13 WaveTile 85 - // (op 96) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 96) Generate 2:U32 into nullptr - // (op 96) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[42:43] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 96) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[42:43] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8272 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 96) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[42:43], v0 offset:8272 // (op 96) Load local data -// DSMEM: Expected complete at 2449 (current 2429) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 94) LoadLDSTile{Value: Halfx2}(96) END - // (op 94) end: generate({96}) - // (op 39) SetCoordinate(94) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half - // (op 39) SetCoordinate(103) BEGIN - // (op 103) generate({}) - // (op 103) end: generate({}) - // (op 103) generate({105}) - // (op 103) LoadLDSTile{Value: Halfx2}(105) BEGIN - // (op 105) GEN: loadMacroTileWAVELDS OP 105 LDS 13 WaveTile 85 - // (op 105) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 105) Generate 2:U32 into nullptr - // (op 105) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[44:45] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 105) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[44:45] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8288 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 105) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -s_waitcnt lgkmcnt(14) -v_mfma_f32_32x32x8f16 a[0:15], v[76:77], v[70:71], a[0:15] // (op 549) - // (op 39) Multiply(549) END -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 39) Deallocate{}(1861) BEGIN - // (op 1861) Deallocate 470 - // Freeing : 2 VGPRs (Value: Halfx2) (op 546): v76, v77 - - // Deleting tag 470 - // (op 1861) Deallocate 472 - // Freeing : 2 VGPRs (Value: Halfx2) (op 548): v70, v71 - - // Deleting tag 472 - // (op 39) Deallocate{}(1861) END - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -ds_read_b64 v[44:45], v0 offset:8288 // (op 105) Load local data -// DSMEM: Expected complete at 2455 (current 2435) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 103) LoadLDSTile{Value: Halfx2}(105) END - // (op 103) end: generate({105}) - // (op 39) SetCoordinate(103) END -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected complete at 2511 (current 2436) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) - // (op 39) SetCoordinate(112) BEGIN - // (op 112) generate({}) - // (op 112) end: generate({}) - // (op 112) generate({114}) - // (op 112) LoadLDSTile{Value: Halfx2}(114) BEGIN - // (op 114) GEN: loadMacroTileWAVELDS OP 114 LDS 13 WaveTile 85 - // (op 114) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 114) Generate 2:U32 into nullptr - // (op 114) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[46:47] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 114) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: v[46:47] - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8304 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 114) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -ds_read_b64 v[46:47], v0 offset:8304 // (op 114) Load local data -// DSMEM: Expected complete at 2457 (current 2437) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 112) LoadLDSTile{Value: Halfx2}(114) END - // (op 112) end: generate({114}) - // (op 39) SetCoordinate(112) END -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected stall of 51. CBNW: 32, Inc: 4 -// VMEM: Expected complete at 2567 (current 2492) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 33, Inc: 4 -// VMEM: Expected complete at 2574 (current 2499) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 34, Inc: 4 -// VMEM: Expected complete at 2579 (current 2504) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // (op 1018) Generate Add(v[54:55]:U64, v50:R)U64 into VGPR Value: UInt64 x 1: v[54:55] - // (op 1018) reg expression - // (op 1018) reg expression - // (op 1018) Add(v[54:55]:U64, v50:R)U64 - // (op 1018) Add: dest (VGPR Value: UInt64 x 1: v[54:55]) = - // (op 1018) lhs (VGPR Value: UInt64 x 1: v[54:55]) - // (op 1018) rhs (VGPR Value: Raw32 x 1: v50) -// Allocated : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 -v_add_co_u32 v54, s[48:49], v54, v50 // (op 1018) least significant half -v_addc_co_u32 v55, s[48:49], 0, v55, s[48:49] // (op 1018) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1018): s48, s49 - - // (op 1018) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1018) reg expression - // (op 1018) Add(m0:U32, 1024:U32)U32 - // (op 1018) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1018) - // (op 1018) Expression temporary in special register - // Unlock None -buffer_load_dword v54, s[36:39], s46 offen offset: 0 lds // (op 1018) Load value direct to lds -// VMEM: Expected stall of 4. CBNW: 35, Inc: 4 -// VMEM: Expected complete at 2587 (current 2512) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 49152, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1018): s46 - - // Freeing Stride509: 2 VGPRs (Value: UInt64) (op 1018): v50, v51 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1018): v54, v55 - - // Freeing : 1 SGPR (Value: UInt32) (op 1018): s45 - - // (op 643) LoadTileDirect2LDS Value: Halfx2(1018) END - // (op 643) Deallocate{}(1893) BEGIN - // (op 1893) Deallocate 622 - // Deleting tag 622 - // (op 643) Deallocate{}(1893) END - // (op 643) end: generate({1018}) - // (op 39) SetCoordinate(643) END - // (op 39) Deallocate{}(1865) BEGIN - // (op 1865) Deallocate 508 - // Freeing Offset508: 2 VGPRs (Value: UInt64) (op 976): v52, v53 - - // Deleting tag 508 - // (op 1865) Deallocate 510 - // Deleting tag 510 - // (op 39) Deallocate{}(1865) END - // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) BEGIN - // (op 1157) Assign dim(506) = Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 - // (op 1157) Generate Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64 into DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19] - // (op 1157) reg expression - // (op 1157) Add({DataFlowTag506: v[18:19]:U64}, 512:U64)U64 - // (op 1157) Add: dest (VGPR Value: UInt64 x 1: v[18:19]) = - // (op 1157) lhs (DataFlowTag506: VGPR Value: UInt64 x 1: v[18:19]) - // (op 1157) rhs (Literal Value: UInt64 x 0: 512) - // (op 39) Barrier(1755) BEGIN -s_barrier // (op 1755) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 39) Barrier(1755) END -v_add_co_u32 v18, vcc, 512, v18 // (op 1157) least significant half - // Lock VCC -// Start of Int64 add, locking VCC - // (op 39) SetCoordinate(638) BEGIN - // (op 638) generate({}) - // (op 638) end: generate({}) - // (op 638) generate({1013}) - // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) BEGIN - // (op 1013) GEN: LoadTileDirect2LDS - // (op 1013) GEN: loadMacroTileDirect2LDS OP 1013 LDS 436 MacroTile 434 - // (op 1013) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 1013) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride490: VGPR Value: UInt64 x 1: (unallocated) - // (op 1013) Get arg Tensor_0_stride_0_9 - // (op 1013) reg expression - // (op 1013) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 1013) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1013) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 3) -v_addc_co_u32 v19, vcc, 0, v19, vcc // (op 1157) most significant half - // Unlock VCC -// End of Int64 add, Unlocking VCC. - // (op 39) Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157) END -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 -s_lshl_b64 s[46:47], s[18:19], 3 // (op 1013) - // (op 1013) convert - // (op 1013) ShiftL({ convertInPlace: s[46:47]:U64}, 1:U32)U64 - // (op 1013) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1013) value ( convertInPlace: SGPR Value: UInt64 x 1: s[46:47]) - // (op 1013) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride490: 2 VGPRs (Value: UInt64) (op 1013): v48, v49 -v_lshlrev_b64 v[48:49], 1, s[46:47] // (op 1013) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 1013): s46, s47 - - // (op 1013) Generate 2:U64 into nullptr - // (op 1013) Generate 1024:U32 into nullptr - // (op 1013) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 57344 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride490: VGPR Value: UInt64 x 1: v[48:49] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - -// Allocated : 2 VGPRs (Value: UInt64) (op 1013): v50, v51 -v_mov_b64 v[50:51], v[68:69] // (op 1013) - // (op 1013) Generate Add(57344:U32, {DataFlowTag608: s42:U32})U32 into nullptr - // (op 1013) reg expression - // (op 1013) Add(57344:U32, {DataFlowTag608: s42:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 1013): s45 -s_add_u32 s45, 57344, s42 // (op 1013) - // (op 1013) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride490: v[48:49]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 1013) Generate s45:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s45 // (op 1013) reg expression - // (op 1013) Generate 896:U32 into OffsetD2L: SGPR Value: UInt32 x 1: (unallocated) -// 896 is not a supported value! -// Allocated OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 -s_mov_b32 s46, 896 // (op 1013) call() -// 896 is not a supported value! -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 46. CBNW: 36, Inc: 4 -// VMEM: Expected complete at 2643 (current 2568) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 37, Inc: 4 -// VMEM: Expected complete at 2650 (current 2575) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 38, Inc: 4 -// VMEM: Expected complete at 2655 (current 2580) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 4. CBNW: 39, Inc: 4 -// VMEM: Expected complete at 2663 (current 2588) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 52. CBNW: 40, Inc: 4 -// VMEM: Expected complete at 2719 (current 2644) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 3. CBNW: 41, Inc: 4 -// VMEM: Expected complete at 2726 (current 2651) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 1. CBNW: 42, Inc: 4 -// VMEM: Expected complete at 2731 (current 2656) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // (op 1013) Generate Add(v[50:51]:U64, v48:R)U64 into VGPR Value: UInt64 x 1: v[50:51] - // (op 1013) reg expression - // (op 1013) reg expression - // (op 1013) Add(v[50:51]:U64, v48:R)U64 - // (op 1013) Add: dest (VGPR Value: UInt64 x 1: v[50:51]) = - // (op 1013) lhs (VGPR Value: UInt64 x 1: v[50:51]) - // (op 1013) rhs (VGPR Value: Raw32 x 1: v48) -// Allocated : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 -v_add_co_u32 v50, s[48:49], v50, v48 // (op 1013) least significant half -v_addc_co_u32 v51, s[48:49], 0, v51, s[48:49] // (op 1013) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1013): s48, s49 - - // (op 1013) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 1013) reg expression - // (op 1013) Add(m0:U32, 1024:U32)U32 - // (op 1013) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 1013) - // (op 1013) Expression temporary in special register - // Unlock None -buffer_load_dword v50, s[32:35], s46 offen offset: 0 lds // (op 1013) Load value direct to lds -// VMEM: Expected stall of 4. CBNW: 43, Inc: 4 -// VMEM: Expected complete at 2739 (current 2664) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 57344, Size: 8192) - // Freeing OffsetD2L: 1 SGPR (Value: UInt32) (op 1013): s46 - - // Freeing Stride490: 2 VGPRs (Value: UInt64) (op 1013): v48, v49 - - // Freeing : 2 VGPRs (Value: UInt64) (op 1013): v50, v51 - - // Freeing : 1 SGPR (Value: UInt32) (op 1013): s45 - - // (op 638) LoadTileDirect2LDS Value: Halfx2(1013) END - // (op 638) Deallocate{}(1891) BEGIN - // (op 1891) Deallocate 610 - // Deleting tag 610 - // (op 638) Deallocate{}(1891) END - // (op 638) end: generate({1013}) - // (op 39) SetCoordinate(638) END - // (op 39) Deallocate{}(1863) BEGIN - // (op 1863) Deallocate 491 - // Deleting tag 491 - // (op 1863) Deallocate 489 - // Freeing Offset489: 2 VGPRs (Value: UInt64) (op 971): v68, v69 - - // Deleting tag 489 - // (op 39) Deallocate{}(1863) END - // (op 39) NOP(978) BEGIN - // (op 978) generate({}) - // (op 978) end: generate({}) - // (op 39) NOP(978) END - // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) BEGIN - // (op 1093) Assign dim(487) = Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 - // (op 1093) Generate Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64 into DataFlowTag487: VGPR Value: UInt64 x 1: v[14:15] - // (op 1093) reg expression - // (op 1093) Add({DataFlowTag487: v[14:15]:U64}, 512:U64)U64 - // (op 1093) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = - // (op 1093) lhs (DataFlowTag487: VGPR Value: UInt64 x 1: v[14:15]) - // (op 1093) rhs (Literal Value: UInt64 x 0: 512) - // (op 39) NOP(973) BEGIN - // (op 973) generate({}) - // (op 973) end: generate({}) - // (op 39) NOP(973) END -v_add_co_u32 v14, vcc, 512, v14 // (op 1093) least significant half - // Lock VCC -// Start of Int64 add, locking VCC - // (op 39) NOP(802) BEGIN - // (op 802) generate({}) - // (op 802) end: generate({}) - // (op 39) NOP(802) END -v_addc_co_u32 v15, vcc, 0, v15, vcc // (op 1093) most significant half - // Unlock VCC -// End of Int64 add, Unlocking VCC. - // (op 39) Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093) END - // (op 39) end: generate({41, 57, 811, 1733}) - // (op 39) For Loop Increment - // (op 39) generate({}) - // (op 39) end: generate({}) - // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 if true) - // (op 39) Generate LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL into SCC Value: Bool x 1: scc - // (op 39) Get arg Tensor_0_size_1_10 - // (op 39) LessThan({DataFlowTag245: s44:U32}, BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32)BL - // (op 39) BitwiseAnd(Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32, 4294967292:U32)U32 - // (op 39) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated : 2 SGPRs (Value: Int64) (op 39): s46, s47 -s_ashr_i64 s[46:47], s[20:21], 6 // (op 39) -// Allocated : 1 SGPR (Value: UInt32) (op 39): s45 -s_mov_b32 s45, s46 // (op 39) convert - // Freeing : 2 SGPRs (Value: Int64) (op 39): s46, s47 - -// Allocated : 1 SGPR (Value: UInt32) (op 39): s46 -s_and_b32 s46, s45, 4294967292 // (op 39) - // Freeing : 1 SGPR (Value: UInt32) (op 39): s45 - -s_cmp_lt_u32 s44, s46 // (op 39) - // Freeing : 1 SGPR (Value: UInt32) (op 39): s46 - -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 39) -s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 // (op 39) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoop_39 if true) -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoop_39: - // (op 39) -s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch - // (op 39) - // (op 39) Unlock For Loop - // Unlock None - // (op 1074) ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39) END - // (op 1074) Deallocate{}(1765) BEGIN - // (op 1765) Deallocate 623 - // Deleting tag 623 - // (op 1765) Deallocate 621 - // Deleting tag 621 - // (op 1765) Deallocate 620 - // Freeing DataFlowTag620: 1 SGPR (Value: UInt32) (op 1536): s43 - - // Deleting tag 620 - // (op 1765) Deallocate 609 - // Deleting tag 609 - // (op 1765) Deallocate 6 - // Deleting tag 6 - // (op 1765) Deallocate 611 - // Deleting tag 611 - // (op 1765) Deallocate 354 - // Deleting tag 354 - // (op 1765) Deallocate 537 - // Deleting tag 537 - // (op 1765) Deallocate 265 - // Freeing : 2 VGPRs (Value: Halfx2) (op 746): v40, v41 - - // Deleting tag 265 - // (op 1765) Deallocate 535 - // Deleting tag 535 - // (op 1765) Deallocate 534 - // Freeing DataFlowTag534: 1 SGPR (Value: UInt32) (op 1255): s1 - - // Deleting tag 534 - // (op 1765) Deallocate 277 - // Freeing : 2 VGPRs (Value: Halfx2) (op 755): v46, v47 - - // Deleting tag 277 - // (op 1765) Deallocate 261 - // Freeing : 2 VGPRs (Value: Halfx2) (op 743): v38, v39 - - // Deleting tag 261 - // (op 1765) Deallocate 518 - // Freeing DataFlowTag518: 1 SGPR (Value: UInt32) (op 1203): s0 - - // Deleting tag 518 - // (op 1765) Deallocate 438 - // Deleting tag 438 - // (op 1765) Deallocate 358 - // Deleting tag 358 - // (op 1765) Deallocate 271 - // Freeing : 2 VGPRs (Value: Halfx2) (op 773): v26, v27 - - // Deleting tag 271 - // (op 1765) Deallocate 7 - // Deleting tag 7 - // (op 1765) Deallocate 521 - // Deleting tag 521 - // (op 1765) Deallocate 394 - // Deleting tag 394 - // (op 1765) Deallocate 572 - // Freeing DataFlowTag572: 1 SGPR (Value: UInt32) (op 1380): s17 - - // Deleting tag 572 - // (op 1765) Deallocate 360 - // Deleting tag 360 - // (op 1765) Deallocate 490 - // Deleting tag 490 - // (op 1765) Deallocate 587 - // Deleting tag 587 - // (op 1765) Deallocate 511 - // Deleting tag 511 - // (op 1765) Deallocate 257 - // Freeing : 2 VGPRs (Value: Halfx2) (op 740): v36, v37 - - // Deleting tag 257 - // (op 1765) Deallocate 279 - // Freeing : 2 VGPRs (Value: Halfx2) (op 779): v30, v31 - - // Deleting tag 279 - // (op 1765) Deallocate 263 - // Freeing : 2 VGPRs (Value: Halfx2) (op 767): v22, v23 - - // Deleting tag 263 - // (op 1765) Deallocate 253 - // Freeing : 2 VGPRs (Value: Halfx2) (op 737): v34, v35 - - // Deleting tag 253 - // (op 1765) Deallocate 507 - // Deleting tag 507 - // (op 1765) Deallocate 273 - // Freeing : 2 VGPRs (Value: Halfx2) (op 752): v44, v45 - - // Deleting tag 273 - // (op 1765) Deallocate 400 - // Deleting tag 400 - // (op 1765) Deallocate 267 - // Freeing : 2 VGPRs (Value: Halfx2) (op 770): v24, v25 - - // Deleting tag 267 - // (op 1765) Deallocate 259 - // Freeing : 2 VGPRs (Value: Halfx2) (op 764): v20, v21 - - // Deleting tag 259 - // (op 1765) Deallocate 255 - // Freeing : 2 VGPRs (Value: Halfx2) (op 761): v16, v17 - - // Deleting tag 255 - // (op 1765) Deallocate 519 - // Deleting tag 519 - // (op 1765) Deallocate 11 - // Freeing : 2 VGPRs (Value: Halfx2) (op 734): v32, v33 - - // Deleting tag 11 - // (op 1765) Deallocate 398 - // Deleting tag 398 - // (op 1765) Deallocate 436 - // Deleting tag 436 - // (op 1765) Deallocate 434 - // Deleting tag 434 - // (op 1765) Deallocate 269 - // Freeing : 2 VGPRs (Value: Halfx2) (op 749): v42, v43 - - // Deleting tag 269 - // (op 1765) Deallocate 396 - // Deleting tag 396 - // (op 1765) Deallocate 440 - // Deleting tag 440 - // (op 1765) Deallocate 487 - // Freeing DataFlowTag487: 2 VGPRs (Value: UInt64) (op 1101): v14, v15 - - // Deleting tag 487 - // (op 1765) Deallocate 488 - // Deleting tag 488 - // (op 1765) Deallocate 275 - // Freeing : 2 VGPRs (Value: Halfx2) (op 776): v28, v29 - - // Deleting tag 275 - // (op 1765) Deallocate 356 - // Deleting tag 356 - // (op 1765) Deallocate 509 - // Deleting tag 509 - // (op 1765) Deallocate 492 - // Deleting tag 492 - // (op 1765) Deallocate 19 - // Freeing : 2 VGPRs (Value: Halfx2) (op 758): v12, v13 - - // Deleting tag 19 - // (op 1765) Deallocate 560 - // Freeing DataFlowTag560: 1 SGPR (Value: UInt32) (op 1341): s16 - - // Deleting tag 560 - // (op 1765) Deallocate 245 - // Freeing DataFlowTag245: 1 SGPR (Value: UInt32) (op 40): s44 - - // Deleting tag 245 - // (op 1765) Deallocate 506 - // Freeing DataFlowTag506: 2 VGPRs (Value: UInt64) (op 1165): v18, v19 - - // Deleting tag 506 - // (op 1765) Deallocate 561 - // Deleting tag 561 - // (op 1765) Deallocate 563 - // Deleting tag 563 - // (op 1765) Deallocate 573 - // Deleting tag 573 - // (op 1765) Deallocate 575 - // Deleting tag 575 - // (op 1765) Deallocate 584 - // Freeing DataFlowTag584: 1 SGPR (Value: UInt32) (op 1419): s40 - - // Deleting tag 584 - // (op 1765) Deallocate 585 - // Deleting tag 585 - // (op 1765) Deallocate 596 - // Freeing DataFlowTag596: 1 SGPR (Value: UInt32) (op 1458): s41 - - // Deleting tag 596 - // (op 1765) Deallocate 597 - // Deleting tag 597 - // (op 1765) Deallocate 599 - // Deleting tag 599 - // (op 1765) Deallocate 608 - // Freeing DataFlowTag608: 1 SGPR (Value: UInt32) (op 1497): s42 - - // Deleting tag 608 - // (op 1074) Deallocate{}(1765) END - // (op 1074) Barrier(1767) BEGIN -s_barrier // (op 1767) - // (op 1074) Barrier(1767) END - // (op 1074) end: generate({1069}) - // (op 1074) Unlock Scope 1074 - // Unlock None - // (op 670) Scope(1074) END - // (op 670) SetCoordinate(313) BEGIN - // (op 313) generate({}) - // (op 313) end: generate({}) - // (op 313) generate({314}) - // (op 313) SetCoordinate(314) BEGIN - // (op 314) generate({}) - // (op 314) end: generate({}) - // (op 314) generate({1051}) - // (op 314) Scope(1051) BEGIN - // (op 1051) Lock Scope 1051 - // Lock Branch - // (op 1051) generate({1045}) - // (op 1051) NOP(1045) BEGIN - // (op 1045) generate({}) - // (op 1045) end: generate({}) - // (op 1051) NOP(1045) END - // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) BEGIN - // (op 1056) Assign dim(474) = ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 - // tag 474: v**UNALLOCATED** - // (op 1056) Generate ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: (unallocated) - // (op 1056) Get arg Tensor_0_stride_0_9 - // (op 1056) Get arg Tensor_0_size_1_10 - // (op 1056) reg expression - // (op 1056) reg expression - // (op 1056) reg expression - // (op 1056) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 - // (op 1056) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 -v_lshrrev_b32 v12, 5, v1 // (op 1056) -// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 -s_ashr_i64 s[0:1], s[20:21], 6 // (op 1056) - // (op 1056) BEGIN: Tile - // (op 1056) convert -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v13 -v_lshl_add_u32 v13, s2, 6, v12 // (op 1056) - // (op 1056) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1056): v12 - - // (op 1056) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 - // (op 1056) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 -v_and_b32 v12, -32, v1 // (op 1056) -// Allocated : 1 SGPR (Value: UInt32) (op 1056): s16 -s_lshr_b32 s16, s0, 2 // (op 1056) - // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1056): s0, s1 - - // (op 1056) BEGIN: Flatten[1] - // (op 1056) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v12:U32)U32} - // (op 1056) reg expression -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 -v_sub_u32 v14, v1, v12 // (op 1056) - // (op 1056) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1056): v12 - - // (op 1056) BEGIN: Tile - // (op 1056) {Tile: ShiftL({Flatten[1]: v14:U32}, 1:U32)U32} - // (op 1056) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1056) value (Flatten[1]: VGPR Value: UInt32 x 1: v14) - // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v12 -v_lshlrev_b32 v12, 1, v14 // (op 1056) - // (op 1056) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1056): v14 - - // (op 1056) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1056): v14 -v_lshl_add_u32 v14, s16, 8, v12 // (op 1056) - // (op 1056) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v12 - - // Freeing : 1 SGPR (Value: UInt32) (op 1056): s16 - -// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 -v_mov_b32 v17, 0 // (op 1056) convert -v_mov_b32 v16, v14 // (op 1056) convert - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v14 - - // (op 1056) BEGIN: Split - // (op 1056) Multiply: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1056) lhs (Tile: VGPR Value: UInt32 x 1: v13) - // (op 1056) rhs (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) -// Allocated : 2 VGPRs (Value: UInt64) (op 1056): v14, v15 -v_mul_lo_u32 v15, v13, s19 // (op 1056) most significant: low of low * high - // (op 1056) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1056): v12 -v_mul_hi_u32 v12, v13, s18 // (op 1056) most significant: high of low * low -v_mul_lo_u32 v14, v13, s18 // (op 1056) least significant: low of low * low -v_add_u32 v15, v15, v12 // (op 1056) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1056): v12 - - // (op 1056) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = - // (op 1056) lhs (VGPR Value: UInt64 x 1: v[14:15]) - // (op 1056) rhs (Tile: VGPR Value: UInt64 x 1: v[16:17]) -// Allocated : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 -v_add_co_u32 v14, s[0:1], v14, v16 // (op 1056) least significant half -v_addc_co_u32 v15, s[0:1], v15, v17, s[0:1] // (op 1056) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1056): s0, s1 - - // (op 1056) END: Split - // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1056): v16, v17 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1056): v13 - - // (op 1056) ShiftL({Split: v[14:15]:U64}, 1:U32)U64 - // (op 1056) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1056) value (Split: VGPR Value: UInt64 x 1: v[14:15]) - // (op 1056) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 -v_lshlrev_b64 v[12:13], 1, v[14:15] // (op 1056) - // Freeing Split: 2 VGPRs (Value: UInt64) (op 1056): v14, v15 - - // (op 1051) Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056) END - // (op 1051) Assign VGPR 128:U64(1057) BEGIN - // (op 1057) Assign dim(475) = 128:U64 - // (op 1057) Assign stride expression - // (op 1051) Assign VGPR 128:U64(1057) END - // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) BEGIN - // (op 1058) Assign dim(477) = Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // (op 1058) Generate Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // (op 1058) Get arg Tensor_0_pointer - // (op 1058) Get arg Tensor_0_extent_0 - // (op 1058) reg expression - // (op 1058) reg expression - // (op 1058) ShiftL({Tensor_0_extent_0: s[4:5]:I64}, 1:U32)I64 - // (op 1058) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1058) value (Tensor_0_extent_0: SGPR Value: Int64 x 1: s[4:5]) - // (op 1058) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1058): s0, s1 -s_lshl_b64 s[0:1], s[4:5], 1 // (op 1058) - // (op 1058) reg expression -s_mov_b32 s32, s6 // (op 1058) reg expression -s_mov_b32 s33, s7 // (op 1058) reg expression -s_mov_b32 s34, s0 // (op 1058) reg expression -s_mov_b32 s35, 131072 // (op 1058) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1058): s0, s1 - - // (op 1051) Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058) END - // (op 1051) NOP(1047) BEGIN - // (op 1047) generate({}) - // (op 1047) end: generate({}) - // (op 1051) NOP(1047) END - // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) BEGIN - // (op 1063) Assign dim(479) = ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1063) Assign stride expression - // (op 1051) Tag 1063non referenced extraArgs = {Tensor_0_stride_0_9} - - // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063) END - // (op 1051) NOP(1048) BEGIN - // (op 1048) generate({}) - // (op 1048) end: generate({}) - // (op 1051) NOP(1048) END - // (op 1051) Assign VGPR 2:U64(1066) BEGIN - // (op 1066) Assign dim(481) = 2:U64 - // (op 1066) Assign stride expression - // (op 1051) Assign VGPR 2:U64(1066) END - // (op 1051) NOP(1114) BEGIN - // (op 1114) generate({}) - // (op 1114) end: generate({}) - // (op 1051) NOP(1114) END - // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) BEGIN - // (op 1123) Assign dim(493) = {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} - // tag 493: v**UNALLOCATED** - // (op 1123) Generate {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64} into DataFlowTag493: VGPR Value: UInt64 x 1: (unallocated) - // (op 1123) Get arg Tensor_0_size_1_10 - // (op 1123) Get arg Tensor_2_stride_1_12 - // (op 1123) reg expression - // (op 1123) reg expression - // (op 1123) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 - // (op 1123) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 -v_and_b32 v14, -32, v1 // (op 1123) -// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 -s_ashr_i64 s[0:1], s[20:21], 6 // (op 1123) - // (op 1123) BEGIN: Flatten[1] - // (op 1123) {Flatten[1]: Subtract({Workitem Index X: v1:U32}, v14:U32)U32} - // (op 1123) convert -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 -v_sub_u32 v15, v1, v14 // (op 1123) - // (op 1123) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1123): v14 - - // (op 1123) LogicalShiftR({ convertForwardSubset: s0:U32}, 2:U32)U32 - // (op 1123) BEGIN: Tile - // (op 1123) {Tile: ShiftL({Flatten[1]: v15:U32}, 1:U32)U32} - // (op 1123) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1123) value (Flatten[1]: VGPR Value: UInt32 x 1: v15) - // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 -v_lshlrev_b32 v14, 1, v15 // (op 1123) - // (op 1123) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1123): v15 - -// Allocated : 1 SGPR (Value: UInt32) (op 1123): s16 -s_lshr_b32 s16, s0, 2 // (op 1123) - // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 1123): s0, s1 - - // (op 1123) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 - // (op 1123) reg expression -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v15 -v_lshrrev_b32 v15, 5, v1 // (op 1123) - // (op 1123) reg expression - // (op 1123) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v16 -v_lshl_add_u32 v16, s16, 8, v14 // (op 1123) - // (op 1123) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 - - // Freeing : 1 SGPR (Value: UInt32) (op 1123): s16 - -// Allocated Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 -v_mov_b32 v19, 0 // (op 1123) convert -v_mov_b32 v18, v16 // (op 1123) convert - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v16 - - // (op 1123) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1123): v14 -v_lshl_add_u32 v14, s3, 6, v15 // (op 1123) - // (op 1123) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1123): v15 - - // (op 1123) Multiply({Tile: v14:U32}, {Tensor_2_stride_1_12: s[22:23]:I64})I64 - // (op 1123) Multiply: dest (VGPR Value: Int64 x 1: (unallocated)) = - // (op 1123) lhs (Tile: VGPR Value: UInt32 x 1: v14) - // (op 1123) rhs (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) -// Allocated : 2 VGPRs (Value: Int64) (op 1123): v16, v17 -v_mul_lo_u32 v17, v14, s23 // (op 1123) most significant: low of low * high - // (op 1123) low of high * low omitted due to zero input. -// Allocated : 1 VGPR (Value: Int32) (op 1123): v15 -v_mul_hi_u32 v15, v14, s22 // (op 1123) most significant: high of low * low -v_mul_lo_u32 v16, v14, s22 // (op 1123) least significant: low of low * low -v_add_u32 v17, v17, v15 // (op 1123) most significant: sum - // Freeing : 1 VGPR (Value: Int32) (op 1123): v15 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1123): v14 - - // (op 1123) BEGIN: Split - // (op 1123) Add: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 1123) lhs (Tile: VGPR Value: UInt64 x 1: v[18:19]) - // (op 1123) rhs (VGPR Value: Int64 x 1: v[16:17]) -// Allocated DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 -// Allocated : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 -v_add_co_u32 v14, s[0:1], v18, v16 // (op 1123) least significant half -v_addc_co_u32 v15, s[0:1], v19, v17, s[0:1] // (op 1123) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 1123): s0, s1 - - // (op 1123) ShiftL: dest (VGPR Value: UInt64 x 1: v[14:15]) = - // (op 1123) value (VGPR Value: UInt64 x 1: v[14:15]) - // (op 1123) shiftAmount (Literal Value: UInt32 x 0: 1) -v_lshlrev_b64 v[14:15], 1, v[14:15] // (op 1123) - // (op 1123) END: Split - // Freeing : 2 VGPRs (Value: Int64) (op 1123): v16, v17 - - // Freeing Tile: 2 VGPRs (Value: UInt64) (op 1123): v18, v19 - - // (op 1051) Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123) END - // (op 1051) Assign VGPR 128:U64(1124) BEGIN - // (op 1124) Assign dim(494) = 128:U64 - // (op 1124) Assign stride expression - // (op 1051) Assign VGPR 128:U64(1124) END - // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) BEGIN - // (op 1125) Assign dim(496) = Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // (op 1125) Generate Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // (op 1125) Get arg Tensor_2_pointer - // (op 1125) Get arg Tensor_2_extent_2 - // (op 1125) reg expression - // (op 1125) reg expression - // (op 1125) ShiftL({Tensor_2_extent_2: s[8:9]:I64}, 1:U32)I64 - // (op 1125) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1125) value (Tensor_2_extent_2: SGPR Value: Int64 x 1: s[8:9]) - // (op 1125) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1125): s0, s1 -s_lshl_b64 s[0:1], s[8:9], 1 // (op 1125) - // (op 1125) reg expression -s_mov_b32 s36, s10 // (op 1125) reg expression -s_mov_b32 s37, s11 // (op 1125) reg expression -s_mov_b32 s38, s0 // (op 1125) reg expression -s_mov_b32 s39, 131072 // (op 1125) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1125): s0, s1 - - // (op 1051) Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125) END - // (op 1051) NOP(1116) BEGIN - // (op 1116) generate({}) - // (op 1116) end: generate({}) - // (op 1051) NOP(1116) END - // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) BEGIN - // (op 1130) Assign dim(498) = ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 - // (op 1130) Assign stride expression - // (op 1051) Tag 1130non referenced extraArgs = {Tensor_2_stride_1_12} - - // (op 1051) Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130) END - // (op 1051) NOP(1117) BEGIN - // (op 1117) generate({}) - // (op 1117) end: generate({}) - // (op 1051) NOP(1117) END - // (op 1051) Assign VGPR 2:U64(1133) BEGIN - // (op 1133) Assign dim(500) = 2:U64 - // (op 1133) Assign stride expression - // (op 1051) Assign VGPR 2:U64(1133) END - // (op 1051) NOP(1211) BEGIN - // (op 1211) generate({}) - // (op 1211) end: generate({}) - // (op 1051) NOP(1211) END - // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) BEGIN - // (op 1216) Assign dim(522) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 522: s**UNALLOCATED** - // (op 1216) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag522: SGPR Value: UInt32 x 1: (unallocated) - // (op 1216) reg expression - // (op 1216) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 -v_and_b32 v16, -32, v1 // (op 1216) - // (op 1216) BEGIN: Tile[1] - // (op 1216) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 -v_sub_u32 v17, v1, v16 // (op 1216) - // (op 1216) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1216): v16 - - // (op 1216) BEGIN: Flatten - // (op 1216) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} - // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1216) value (Tile[1]: VGPR Value: UInt32 x 1: v17) - // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 -v_lshlrev_b32 v16, 1, v17 // (op 1216) - // (op 1216) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1216): v17 - - // (op 1216) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v17 -v_lshrrev_b32 v17, 5, v1 // (op 1216) - // (op 1216) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v18 -v_lshl_add_u32 v18, v17, 6, v16 // (op 1216) - // (op 1216) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v16 - - // Freeing : 1 VGPR (Value: UInt32) (op 1216): v17 - - // (op 1216) ShiftL({Flatten: v18:U32}, 1:U32)U32 - // (op 1216) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1216) value (Flatten: VGPR Value: UInt32 x 1: v18) - // (op 1216) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1216): v16 -v_lshlrev_b32 v16, 1, v18 // (op 1216) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1216): v18 - -// Allocated DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s0 -s_nop 0 -v_readfirstlane_b32 s0, v16 // (op 1216) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1216): v16 - - // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216) END - // (op 1051) Assign VGPR 1024:U32(1217) BEGIN - // (op 1217) Assign dim(523) = 1024:U32 - // (op 1217) Assign stride expression - // (op 1051) Assign VGPR 1024:U32(1217) END - // (op 1051) NOP(1212) BEGIN - // (op 1212) generate({}) - // (op 1212) end: generate({}) - // (op 1051) NOP(1212) END - // (op 1051) Assign VGPR 2:U32(1221) BEGIN - // (op 1221) Assign dim(525) = 2:U32 - // (op 1221) Assign stride expression - // (op 1051) Assign VGPR 2:U32(1221) END - // (op 1051) NOP(1263) BEGIN - // (op 1263) generate({}) - // (op 1263) end: generate({}) - // (op 1051) NOP(1263) END - // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) BEGIN - // (op 1268) Assign dim(538) = ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 - // tag 538: s**UNALLOCATED** - // (op 1268) Generate ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32 into DataFlowTag538: SGPR Value: UInt32 x 1: (unallocated) - // (op 1268) reg expression - // (op 1268) BitwiseAnd({Workitem Index X: v1:U32}, -32:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 -v_and_b32 v16, -32, v1 // (op 1268) - // (op 1268) BEGIN: Tile[1] - // (op 1268) {Tile[1]: Subtract({Workitem Index X: v1:U32}, v16:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 -v_sub_u32 v17, v1, v16 // (op 1268) - // (op 1268) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1268): v16 - - // (op 1268) BEGIN: Flatten - // (op 1268) {Flatten: ShiftL({Tile[1]: v17:U32}, 1:U32)U32} - // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1268) value (Tile[1]: VGPR Value: UInt32 x 1: v17) - // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 -v_lshlrev_b32 v16, 1, v17 // (op 1268) - // (op 1268) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1268): v17 - - // (op 1268) LogicalShiftR({Workitem Index X: v1:U32}, 5:I)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v17 -v_lshrrev_b32 v17, 5, v1 // (op 1268) - // (op 1268) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v18 -v_lshl_add_u32 v18, v17, 6, v16 // (op 1268) - // (op 1268) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v16 - - // Freeing : 1 VGPR (Value: UInt32) (op 1268): v17 - - // (op 1268) ShiftL({Flatten: v18:U32}, 1:U32)U32 - // (op 1268) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1268) value (Flatten: VGPR Value: UInt32 x 1: v18) - // (op 1268) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 1 VGPR (Value: UInt32) (op 1268): v16 -v_lshlrev_b32 v16, 1, v18 // (op 1268) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1268): v18 - -// Allocated DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s1 -s_nop 0 -v_readfirstlane_b32 s1, v16 // (op 1268) Wait state hazard: VALU Write Readlane Hazard - // Freeing : 1 VGPR (Value: UInt32) (op 1268): v16 - - // (op 1051) Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268) END - // (op 1051) Assign VGPR 1024:U32(1269) BEGIN - // (op 1269) Assign dim(539) = 1024:U32 - // (op 1269) Assign stride expression - // (op 1051) Assign VGPR 1024:U32(1269) END - // (op 1051) NOP(1264) BEGIN - // (op 1264) generate({}) - // (op 1264) end: generate({}) - // (op 1051) NOP(1264) END - // (op 1051) Assign VGPR 2:U32(1273) BEGIN - // (op 1273) Assign dim(541) = 2:U32 - // (op 1273) Assign stride expression - // (op 1051) Assign VGPR 2:U32(1273) END - // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) BEGIN - // (op 217) Initialize For Loop - // (op 217) generate({218}) - // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) BEGIN - // (op 218) Assign dim(316) = BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 - // tag 316: s**UNALLOCATED** - // (op 218) Generate BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: (unallocated) - // (op 218) Get arg Tensor_0_size_1_10 - // (op 218) reg expression - // (op 218) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 -s_ashr_i64 s[16:17], s[20:21], 6 // (op 218) - // (op 218) convert - // (op 218) BitwiseAnd({ convertForwardSubset: s16:U32}, 4294967292:U32)U32 -// Allocated DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 -s_and_b32 s40, s16, 4294967292 // (op 218) - // Freeing convertForwardSubset: 2 SGPRs (Value: Int64) (op 218): s16, s17 - - // (op 217) Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218) END - // (op 217) end: generate({218}) - // (op 217) Lock For Loop - // Lock Branch - // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc - // (op 217) Get arg Tensor_0_size_1_10 - // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL - // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 -s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) -// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 -s_mov_b32 s41, s16 // (op 217) convert - // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 - -s_cmp_lt_u32 s40, s41 // (op 217) - // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 - -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 217) -s_cbranch_scc0 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217 // (op 217) Condition: Top (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217 if false) -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217: - // (op 217) - // (op 217) generate({219, 1726}) - // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) BEGIN - // (op 219) Assign dim(316) = Add(DataFlowTag(316)U32, 1:U32)U32 - // (op 219) Generate Add(DataFlowTag(316)U32, 1:U32)U32 into DataFlowTag316: SGPR Value: UInt32 x 1: s40 - // (op 219) reg expression - // (op 219) Add({DataFlowTag316: s40:U32}, 1:U32)U32 - // (op 217) Barrier(1726) BEGIN -s_barrier // (op 1726) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 217) Barrier(1726) END -s_add_u32 s40, s40, 1 // (op 219) - // (op 217) Tag 219non referenced extraArgs = {Tensor_0_size_1_10} - - // (op 217) Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219) END - // (op 217) SetCoordinate(318) BEGIN - // (op 318) generate({}) - // (op 318) end: generate({}) - // (op 318) generate({981}) - // (op 318) LoadTileDirect2LDS Value: Halfx2(981) BEGIN - // (op 981) GEN: LoadTileDirect2LDS - // (op 981) GEN: loadMacroTileDirect2LDS OP 981 LDS 13 MacroTile 318 - // (op 981) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 981) Generate ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64 into Stride479: VGPR Value: UInt64 x 1: (unallocated) - // (op 981) Get arg Tensor_0_stride_0_9 - // (op 981) reg expression - // (op 981) ShiftL({Tensor_0_stride_0_9: s[18:19]:I64}, 3:U32)I64 - // (op 981) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 981) value (Tensor_0_stride_0_9: SGPR Value: Int64 x 1: s[18:19]) - // (op 981) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 -s_lshl_b64 s[16:17], s[18:19], 3 // (op 981) - // (op 981) convert - // (op 981) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 981) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 981) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 981) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 -v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 981) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 981): s16, s17 - - // (op 981) Generate 2:U64 into nullptr - // (op 981) Generate 1024:U32 into nullptr - // (op 981) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 8192 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride479: VGPR Value: UInt64 x 1: v[16:17] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_0_stride_0)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag477: SGPR Buffer: None x 1: s[32:35] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // tag 478: v**UNALLOCATED** -// Allocated Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 -v_mov_b64 v[18:19], v[12:13] // (op 981) -// Allocated : 2 VGPRs (Value: UInt64) (op 981): v20, v21 -v_mov_b64 v[20:21], v[18:19] // (op 981) - // (op 981) Generate Add(8192:U32, {DataFlowTag522: s0:U32})U32 into nullptr - // (op 981) reg expression - // (op 981) Add(8192:U32, {DataFlowTag522: s0:U32})U32 -// Allocated : 1 SGPR (Value: UInt32) (op 981): s16 -s_add_u32 s16, 8192, s0 // (op 981) - // (op 981) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride479: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 981) Generate s16:U32 into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s16 // (op 981) reg expression -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2892 (current 2817) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2896 (current 2821) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2900 (current 2825) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2904 (current 2829) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 0, Inc: 4 -// VMEM: Expected complete at 2968 (current 2893) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2972 (current 2897) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2976 (current 2901) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 981) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 981) reg expression - // (op 981) reg expression - // (op 981) Add(v[20:21]:U64, v16:R)U64 - // (op 981) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 981) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 981) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 981): s42, s43 -v_add_co_u32 v20, s[42:43], v20, v16 // (op 981) least significant half -v_addc_co_u32 v21, s[42:43], 0, v21, s[42:43] // (op 981) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 981): s42, s43 - - // (op 981) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 981) reg expression - // (op 981) Add(m0:U32, 1024:U32)U32 - // (op 981) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 981) - // (op 981) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[32:35], 0 offen offset: 0 lds // (op 981) Load value direct to lds -// VMEM: Expected complete at 2980 (current 2905) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // Freeing Stride479: 2 VGPRs (Value: UInt64) (op 981): v16, v17 - - // Freeing : 2 VGPRs (Value: UInt64) (op 981): v20, v21 - - // Freeing : 1 SGPR (Value: UInt32) (op 981): s16 - - // (op 318) LoadTileDirect2LDS Value: Halfx2(981) END - // (op 318) Deallocate{}(1879) BEGIN - // (op 1879) Deallocate 318 - // Deleting tag 318 - // (op 1879) Deallocate 524 - // Deleting tag 524 - // (op 1879) Deallocate 478 - // Freeing Offset478: 2 VGPRs (Value: UInt64) (op 981): v18, v19 - - // Deleting tag 478 - // (op 1879) Deallocate 480 - // Deleting tag 480 - // (op 318) Deallocate{}(1879) END - // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) BEGIN - // (op 1046) Assign dim(474) = Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 - // (op 1046) Generate Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64 into DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13] - // (op 1046) reg expression - // (op 1046) Add({DataFlowTag474: v[12:13]:U64}, 128:U64)U64 - // (op 1046) Add: dest (VGPR Value: UInt64 x 1: v[12:13]) = - // (op 1046) lhs (DataFlowTag474: VGPR Value: UInt64 x 1: v[12:13]) - // (op 1046) rhs (Literal Value: UInt64 x 0: 128) -v_add_co_u32 v12, vcc, 128, v12 // (op 1046) least significant half - // Lock VCC -// Start of Int64 add, locking VCC -v_addc_co_u32 v13, vcc, 0, v13, vcc // (op 1046) most significant half - // Unlock VCC -// End of Int64 add, Unlocking VCC. - // (op 318) Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046) END - // (op 318) end: generate({981}) - // (op 217) SetCoordinate(318) END - // (op 217) NOP(983) BEGIN - // (op 983) generate({}) - // (op 983) end: generate({}) - // (op 217) NOP(983) END - // (op 217) Barrier(1736) BEGIN -s_barrier // (op 1736) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 217) Barrier(1736) END - // (op 217) SetCoordinate(323) BEGIN - // (op 323) generate({}) - // (op 323) end: generate({}) - // (op 323) generate({987}) - // (op 323) LoadTileDirect2LDS Value: Halfx2(987) BEGIN - // (op 987) GEN: LoadTileDirect2LDS - // (op 987) GEN: loadMacroTileDirect2LDS OP 987 LDS 21 MacroTile 320 - // (op 987) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 987) Generate ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64 into Stride498: VGPR Value: UInt64 x 1: (unallocated) - // (op 987) Get arg Tensor_2_stride_1_12 - // (op 987) reg expression - // (op 987) ShiftL({Tensor_2_stride_1_12: s[22:23]:I64}, 3:U32)I64 - // (op 987) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 987) value (Tensor_2_stride_1_12: SGPR Value: Int64 x 1: s[22:23]) - // (op 987) shiftAmount (Literal Value: UInt32 x 0: 3) -// Allocated convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 -s_lshl_b64 s[16:17], s[22:23], 3 // (op 987) - // (op 987) convert - // (op 987) ShiftL({ convertInPlace: s[16:17]:U64}, 1:U32)U64 - // (op 987) ShiftL: dest (VGPR Value: UInt64 x 1: (unallocated)) = - // (op 987) value ( convertInPlace: SGPR Value: UInt64 x 1: s[16:17]) - // (op 987) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 -v_lshlrev_b64 v[16:17], 1, s[16:17] // (op 987) - // Freeing convertInPlace: 2 SGPRs (Value: Int64) (op 987): s16, s17 - - // (op 987) Generate 2:U64 into nullptr - // (op 987) Generate 1024:U32 into nullptr - // (op 987) Dir = Load - // LSTInfo { - // info.kind = Buffer2LDS - // info.m = 8 - // info.n = 1 - // info.elementBits = 32 - // info.packedAmount = 1 - // info.ldsWriteStride = 1024 - // info.data = Literal Value: UInt32 x 0: 0 - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Stride498: VGPR Value: UInt64 x 1: v[16:17] - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(Convert(Multiply(64:U32, CommandArgument(Tensor_2_stride_1)I64)I64)U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag496: SGPR Buffer: None x 1: s[36:39] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 1 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 0 - // colStrideIsOne = 1 - - // tag 497: v**UNALLOCATED** -// Allocated Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 -v_mov_b64 v[18:19], v[14:15] // (op 987) -// Allocated : 2 VGPRs (Value: UInt64) (op 987): v20, v21 -v_mov_b64 v[20:21], v[18:19] // (op 987) - // (op 987) Generate Add(0:U32, {DataFlowTag538: s1:U32})U32 into nullptr - // (op 987) M 8 N 1 elementsPerMove 1 bytesPerMove 4 rowStride {Stride498: v[16:17]:U64} colStride 2:U64 vgprBlockSize 8 numVGPRBlocks 1 - // (op 987) Generate {DataFlowTag538: s1:U32} into M0 Value: UInt32 x 1: m0 -s_mov_b32 m0, s1 // (op 987) reg expression -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected stall of 55. CBNW: 4, Inc: 4 -// VMEM: Expected complete at 3044 (current 2969) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3048 (current 2973) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3052 (current 2977) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3056 (current 2981) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected stall of 60. CBNW: 8, Inc: 4 -// VMEM: Expected complete at 3120 (current 3045) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3124 (current 3049) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3128 (current 3053) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 987) Generate Add(v[20:21]:U64, v16:R)U64 into VGPR Value: UInt64 x 1: v[20:21] - // (op 987) reg expression - // (op 987) reg expression - // (op 987) Add(v[20:21]:U64, v16:R)U64 - // (op 987) Add: dest (VGPR Value: UInt64 x 1: v[20:21]) = - // (op 987) lhs (VGPR Value: UInt64 x 1: v[20:21]) - // (op 987) rhs (VGPR Value: Raw32 x 1: v16) -// Allocated : 2 SGPRs (Value: Bool64) (op 987): s16, s17 -v_add_co_u32 v20, s[16:17], v20, v16 // (op 987) least significant half -v_addc_co_u32 v21, s[16:17], 0, v21, s[16:17] // (op 987) most significant half - // Freeing : 2 SGPRs (Value: Bool64) (op 987): s16, s17 - - // (op 987) Generate Add(m0:U32, 1024:U32)U32 into M0 Value: UInt32 x 1: m0 - // (op 987) reg expression - // (op 987) Add(m0:U32, 1024:U32)U32 - // (op 987) Expression temporary in special register (M0) - // Lock M0 -s_add_u32 m0, m0, 1024 // (op 987) - // (op 987) Expression temporary in special register - // Unlock None -buffer_load_dword v20, s[36:39], 0 offen offset: 0 lds // (op 987) Load value direct to lds -// VMEM: Expected complete at 3132 (current 3057) -// Extra dsts: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // Freeing Stride498: 2 VGPRs (Value: UInt64) (op 987): v16, v17 - - // Freeing : 2 VGPRs (Value: UInt64) (op 987): v20, v21 - - // (op 323) LoadTileDirect2LDS Value: Halfx2(987) END - // (op 323) Deallocate{}(1881) BEGIN - // (op 1881) Deallocate 320 - // Deleting tag 320 - // (op 1881) Deallocate 497 - // Freeing Offset497: 2 VGPRs (Value: UInt64) (op 987): v18, v19 - - // Deleting tag 497 - // (op 1881) Deallocate 540 - // Deleting tag 540 - // (op 1881) Deallocate 499 - // Deleting tag 499 - // (op 323) Deallocate{}(1881) END - // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) BEGIN - // (op 1115) Assign dim(493) = Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 - // (op 1115) Generate Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64 into DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15] - // (op 1115) reg expression - // (op 1115) Add({DataFlowTag493: v[14:15]:U64}, 128:U64)U64 - // (op 1115) Add: dest (VGPR Value: UInt64 x 1: v[14:15]) = - // (op 1115) lhs (DataFlowTag493: VGPR Value: UInt64 x 1: v[14:15]) - // (op 1115) rhs (Literal Value: UInt64 x 0: 128) -v_add_co_u32 v14, vcc, 128, v14 // (op 1115) least significant half - // Lock VCC -// Start of Int64 add, locking VCC -v_addc_co_u32 v15, vcc, 0, v15, vcc // (op 1115) most significant half - // Unlock VCC -// End of Int64 add, Unlocking VCC. - // (op 323) Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115) END - // (op 323) end: generate({987}) - // (op 217) SetCoordinate(323) END - // (op 217) NOP(989) BEGIN - // (op 989) generate({}) - // (op 989) end: generate({}) - // (op 217) NOP(989) END - // (op 217) Barrier(1729) BEGIN -s_waitcnt vmcnt(8) -s_barrier // (op 1729) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 217) Barrier(1729) END - // (op 217) SetCoordinate(224) BEGIN - // (op 224) generate({}) - // (op 224) end: generate({}) - // (op 224) generate({225}) - // (op 224) LoadLDSTile{Value: Halfx2}(225) BEGIN - // (op 225) GEN: loadMacroTileWAVELDS OP 225 LDS 13 WaveTile 85 - // (op 225) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 225) Generate 2:U32 into nullptr - // tag 322: v**UNALLOCATED** - // (op 225) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 225) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 225) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 -ds_read_b64 v[16:17], v0 offset:8192 // (op 225) Load local data -// DSMEM: Expected complete at 3015 (current 2995) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 224) LoadLDSTile{Value: Halfx2}(225) END - // (op 224) end: generate({225}) - // (op 217) SetCoordinate(224) END - // (op 217) Barrier(1739) BEGIN -s_waitcnt vmcnt(0) -s_barrier // (op 1739) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 217) Barrier(1739) END - // (op 217) SetCoordinate(226) BEGIN - // (op 226) generate({}) - // (op 226) end: generate({}) - // (op 226) generate({227}) - // (op 226) LoadLDSTile{Value: Halfx2}(227) BEGIN - // (op 227) GEN: loadMacroTileWAVELDS OP 227 LDS 21 WaveTile 145 - // (op 227) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 227) Generate 2:U32 into nullptr - // tag 324: v**UNALLOCATED** - // (op 227) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 227) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 227) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 -ds_read_b64 v[18:19], v3 // (op 227) Load local data -// DSMEM: Expected complete at 3018 (current 2998) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 226) LoadLDSTile{Value: Halfx2}(227) END - // (op 226) end: generate({227}) - // (op 217) SetCoordinate(226) END - // (op 217) Multiply(228) BEGIN - // (op 228) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 228) - // (op 217) Multiply(228) END - // (op 217) Deallocate{}(1783) BEGIN - // (op 1783) Deallocate 322 - // Freeing : 2 VGPRs (Value: Halfx2) (op 225): v16, v17 - - // Deleting tag 322 - // (op 1783) Deallocate 324 - // Freeing : 2 VGPRs (Value: Halfx2) (op 227): v18, v19 - - // Deleting tag 324 - // (op 217) Deallocate{}(1783) END - // (op 217) SetCoordinate(229) BEGIN - // (op 229) generate({}) - // (op 229) end: generate({}) - // (op 229) generate({230}) - // (op 229) LoadLDSTile{Value: Halfx2}(230) BEGIN - // (op 230) GEN: loadMacroTileWAVELDS OP 230 LDS 13 WaveTile 85 - // (op 230) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 230) Generate 2:U32 into nullptr - // tag 326: v**UNALLOCATED** - // (op 230) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 230) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8208 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 230) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 -ds_read_b64 v[16:17], v0 offset:8208 // (op 230) Load local data -// DSMEM: Expected complete at 3041 (current 3021) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 229) LoadLDSTile{Value: Halfx2}(230) END - // (op 229) end: generate({230}) - // (op 217) SetCoordinate(229) END - // (op 217) SetCoordinate(231) BEGIN - // (op 231) generate({}) - // (op 231) end: generate({}) - // (op 231) generate({232}) - // (op 231) LoadLDSTile{Value: Halfx2}(232) BEGIN - // (op 232) GEN: loadMacroTileWAVELDS OP 232 LDS 21 WaveTile 145 - // (op 232) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 232) Generate 2:U32 into nullptr - // tag 328: v**UNALLOCATED** - // (op 232) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 232) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 16 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 232) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 -ds_read_b64 v[18:19], v3 offset:16 // (op 232) Load local data -// DSMEM: Expected complete at 3042 (current 3022) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 231) LoadLDSTile{Value: Halfx2}(232) END - // (op 231) end: generate({232}) - // (op 217) SetCoordinate(231) END - // (op 217) Multiply(233) BEGIN - // (op 233) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 233) - // (op 217) Multiply(233) END - // (op 217) Deallocate{}(1785) BEGIN - // (op 1785) Deallocate 328 - // Freeing : 2 VGPRs (Value: Halfx2) (op 232): v18, v19 - - // Deleting tag 328 - // (op 1785) Deallocate 326 - // Freeing : 2 VGPRs (Value: Halfx2) (op 230): v16, v17 - - // Deleting tag 326 - // (op 217) Deallocate{}(1785) END - // (op 217) SetCoordinate(234) BEGIN - // (op 234) generate({}) - // (op 234) end: generate({}) - // (op 234) generate({235}) - // (op 234) LoadLDSTile{Value: Halfx2}(235) BEGIN - // (op 235) GEN: loadMacroTileWAVELDS OP 235 LDS 13 WaveTile 85 - // (op 235) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 235) Generate 2:U32 into nullptr - // tag 330: v**UNALLOCATED** - // (op 235) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 235) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8224 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 235) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 -ds_read_b64 v[16:17], v0 offset:8224 // (op 235) Load local data -// DSMEM: Expected complete at 3071 (current 3051) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 234) LoadLDSTile{Value: Halfx2}(235) END - // (op 234) end: generate({235}) - // (op 217) SetCoordinate(234) END - // (op 217) SetCoordinate(236) BEGIN - // (op 236) generate({}) - // (op 236) end: generate({}) - // (op 236) generate({237}) - // (op 236) LoadLDSTile{Value: Halfx2}(237) BEGIN - // (op 237) GEN: loadMacroTileWAVELDS OP 237 LDS 21 WaveTile 145 - // (op 237) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 237) Generate 2:U32 into nullptr - // tag 332: v**UNALLOCATED** - // (op 237) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 237) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 32 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 237) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 -ds_read_b64 v[18:19], v3 offset:32 // (op 237) Load local data -// DSMEM: Expected complete at 3072 (current 3052) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 236) LoadLDSTile{Value: Halfx2}(237) END - // (op 236) end: generate({237}) - // (op 217) SetCoordinate(236) END - // (op 217) Multiply(238) BEGIN - // (op 238) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 238) - // (op 217) Multiply(238) END - // (op 217) Deallocate{}(1787) BEGIN - // (op 1787) Deallocate 332 - // Freeing : 2 VGPRs (Value: Halfx2) (op 237): v18, v19 - - // Deleting tag 332 - // (op 1787) Deallocate 330 - // Freeing : 2 VGPRs (Value: Halfx2) (op 235): v16, v17 - - // Deleting tag 330 - // (op 217) Deallocate{}(1787) END - // (op 217) SetCoordinate(239) BEGIN - // (op 239) generate({}) - // (op 239) end: generate({}) - // (op 239) generate({240}) - // (op 239) LoadLDSTile{Value: Halfx2}(240) BEGIN - // (op 240) GEN: loadMacroTileWAVELDS OP 240 LDS 13 WaveTile 85 - // (op 240) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 240) Generate 2:U32 into nullptr - // tag 334: v**UNALLOCATED** - // (op 240) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 240) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8240 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 240) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 -ds_read_b64 v[16:17], v0 offset:8240 // (op 240) Load local data -// DSMEM: Expected complete at 3101 (current 3081) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 239) LoadLDSTile{Value: Halfx2}(240) END - // (op 239) end: generate({240}) - // (op 217) SetCoordinate(239) END - // (op 217) SetCoordinate(241) BEGIN - // (op 241) generate({}) - // (op 241) end: generate({}) - // (op 241) generate({242}) - // (op 241) LoadLDSTile{Value: Halfx2}(242) BEGIN - // (op 242) GEN: loadMacroTileWAVELDS OP 242 LDS 21 WaveTile 145 - // (op 242) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 242) Generate 2:U32 into nullptr - // tag 336: v**UNALLOCATED** - // (op 242) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 242) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 48 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 242) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 -ds_read_b64 v[18:19], v3 offset:48 // (op 242) Load local data -// DSMEM: Expected complete at 3102 (current 3082) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 241) LoadLDSTile{Value: Halfx2}(242) END - // (op 241) end: generate({242}) - // (op 217) SetCoordinate(241) END - // (op 217) Multiply(243) BEGIN - // (op 243) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 243) - // (op 217) Multiply(243) END - // (op 217) Deallocate{}(1789) BEGIN - // (op 1789) Deallocate 334 - // Freeing : 2 VGPRs (Value: Halfx2) (op 240): v16, v17 - - // Deleting tag 334 - // (op 1789) Deallocate 336 - // Freeing : 2 VGPRs (Value: Halfx2) (op 242): v18, v19 - - // Deleting tag 336 - // (op 217) Deallocate{}(1789) END - // (op 217) SetCoordinate(244) BEGIN - // (op 244) generate({}) - // (op 244) end: generate({}) - // (op 244) generate({245}) - // (op 244) LoadLDSTile{Value: Halfx2}(245) BEGIN - // (op 245) GEN: loadMacroTileWAVELDS OP 245 LDS 13 WaveTile 85 - // (op 245) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 245) Generate 2:U32 into nullptr - // tag 338: v**UNALLOCATED** - // (op 245) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 245) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8256 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 245) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 -ds_read_b64 v[16:17], v0 offset:8256 // (op 245) Load local data -// DSMEM: Expected complete at 3131 (current 3111) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 244) LoadLDSTile{Value: Halfx2}(245) END - // (op 244) end: generate({245}) - // (op 217) SetCoordinate(244) END - // (op 217) SetCoordinate(246) BEGIN - // (op 246) generate({}) - // (op 246) end: generate({}) - // (op 246) generate({247}) - // (op 246) LoadLDSTile{Value: Halfx2}(247) BEGIN - // (op 247) GEN: loadMacroTileWAVELDS OP 247 LDS 21 WaveTile 145 - // (op 247) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 247) Generate 2:U32 into nullptr - // tag 340: v**UNALLOCATED** - // (op 247) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 247) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 64 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 247) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 -ds_read_b64 v[18:19], v3 offset:64 // (op 247) Load local data -// DSMEM: Expected complete at 3132 (current 3112) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 246) LoadLDSTile{Value: Halfx2}(247) END - // (op 246) end: generate({247}) - // (op 217) SetCoordinate(246) END - // (op 217) Multiply(248) BEGIN - // (op 248) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 248) - // (op 217) Multiply(248) END - // (op 217) Deallocate{}(1791) BEGIN - // (op 1791) Deallocate 340 - // Freeing : 2 VGPRs (Value: Halfx2) (op 247): v18, v19 - - // Deleting tag 340 - // (op 1791) Deallocate 338 - // Freeing : 2 VGPRs (Value: Halfx2) (op 245): v16, v17 - - // Deleting tag 338 - // (op 217) Deallocate{}(1791) END - // (op 217) SetCoordinate(249) BEGIN - // (op 249) generate({}) - // (op 249) end: generate({}) - // (op 249) generate({250}) - // (op 249) LoadLDSTile{Value: Halfx2}(250) BEGIN - // (op 250) GEN: loadMacroTileWAVELDS OP 250 LDS 13 WaveTile 85 - // (op 250) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 250) Generate 2:U32 into nullptr - // tag 342: v**UNALLOCATED** - // (op 250) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 250) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8272 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 250) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 -ds_read_b64 v[16:17], v0 offset:8272 // (op 250) Load local data -// DSMEM: Expected complete at 3161 (current 3141) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 249) LoadLDSTile{Value: Halfx2}(250) END - // (op 249) end: generate({250}) - // (op 217) SetCoordinate(249) END - // (op 217) SetCoordinate(251) BEGIN - // (op 251) generate({}) - // (op 251) end: generate({}) - // (op 251) generate({252}) - // (op 251) LoadLDSTile{Value: Halfx2}(252) BEGIN - // (op 252) GEN: loadMacroTileWAVELDS OP 252 LDS 21 WaveTile 145 - // (op 252) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 252) Generate 2:U32 into nullptr - // tag 344: v**UNALLOCATED** - // (op 252) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 252) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 80 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 252) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 -ds_read_b64 v[18:19], v3 offset:80 // (op 252) Load local data -// DSMEM: Expected complete at 3162 (current 3142) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 251) LoadLDSTile{Value: Halfx2}(252) END - // (op 251) end: generate({252}) - // (op 217) SetCoordinate(251) END - // (op 217) Multiply(253) BEGIN - // (op 253) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 253) - // (op 217) Multiply(253) END - // (op 217) Deallocate{}(1793) BEGIN - // (op 1793) Deallocate 342 - // Freeing : 2 VGPRs (Value: Halfx2) (op 250): v16, v17 - - // Deleting tag 342 - // (op 1793) Deallocate 344 - // Freeing : 2 VGPRs (Value: Halfx2) (op 252): v18, v19 - - // Deleting tag 344 - // (op 217) Deallocate{}(1793) END - // (op 217) SetCoordinate(254) BEGIN - // (op 254) generate({}) - // (op 254) end: generate({}) - // (op 254) generate({255}) - // (op 254) LoadLDSTile{Value: Halfx2}(255) BEGIN - // (op 255) GEN: loadMacroTileWAVELDS OP 255 LDS 13 WaveTile 85 - // (op 255) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 255) Generate 2:U32 into nullptr - // tag 346: v**UNALLOCATED** - // (op 255) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 255) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8288 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 255) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 -ds_read_b64 v[16:17], v0 offset:8288 // (op 255) Load local data -// DSMEM: Expected complete at 3191 (current 3171) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 254) LoadLDSTile{Value: Halfx2}(255) END - // (op 254) end: generate({255}) - // (op 217) SetCoordinate(254) END - // (op 217) SetCoordinate(256) BEGIN - // (op 256) generate({}) - // (op 256) end: generate({}) - // (op 256) generate({257}) - // (op 256) LoadLDSTile{Value: Halfx2}(257) BEGIN - // (op 257) GEN: loadMacroTileWAVELDS OP 257 LDS 21 WaveTile 145 - // (op 257) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 257) Generate 2:U32 into nullptr - // tag 348: v**UNALLOCATED** - // (op 257) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 257) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 96 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 257) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 -ds_read_b64 v[18:19], v3 offset:96 // (op 257) Load local data -// DSMEM: Expected complete at 3192 (current 3172) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 256) LoadLDSTile{Value: Halfx2}(257) END - // (op 256) end: generate({257}) - // (op 217) SetCoordinate(256) END - // (op 217) Multiply(258) BEGIN - // (op 258) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 258) - // (op 217) Multiply(258) END - // (op 217) Deallocate{}(1795) BEGIN - // (op 1795) Deallocate 348 - // Freeing : 2 VGPRs (Value: Halfx2) (op 257): v18, v19 - - // Deleting tag 348 - // (op 1795) Deallocate 346 - // Freeing : 2 VGPRs (Value: Halfx2) (op 255): v16, v17 - - // Deleting tag 346 - // (op 217) Deallocate{}(1795) END - // (op 217) SetCoordinate(259) BEGIN - // (op 259) generate({}) - // (op 259) end: generate({}) - // (op 259) generate({260}) - // (op 259) LoadLDSTile{Value: Halfx2}(260) BEGIN - // (op 260) GEN: loadMacroTileWAVELDS OP 260 LDS 13 WaveTile 85 - // (op 260) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 260) Generate 2:U32 into nullptr - // tag 350: v**UNALLOCATED** - // (op 260) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8192 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 260) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag530: VGPR Value: UInt32 x 1: v0 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 8304 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 260) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 -ds_read_b64 v[16:17], v0 offset:8304 // (op 260) Load local data -// DSMEM: Expected complete at 3221 (current 3201) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 8192, Size: 8192) - // (op 259) LoadLDSTile{Value: Halfx2}(260) END - // (op 259) end: generate({260}) - // (op 217) SetCoordinate(259) END - // (op 217) SetCoordinate(261) BEGIN - // (op 261) generate({}) - // (op 261) end: generate({}) - // (op 261) generate({262}) - // (op 261) LoadLDSTile{Value: Halfx2}(262) BEGIN - // (op 262) GEN: loadMacroTileWAVELDS OP 262 LDS 21 WaveTile 145 - // (op 262) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 262) Generate 2:U32 into nullptr - // tag 352: v**UNALLOCATED** - // (op 262) Dir = Load - // LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 262) LSTInfo { - // info.kind = Local - // info.m = 1 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 2: (unallocated) - // info.rowOffsetReg = DataFlowTag546: VGPR Value: UInt32 x 1: v3 - // info.rowStrideReg = Literal Value: UInt32 x 0: 0 - // info.rowStrideAttributes = { - // t.dataType = None - // t.unitStride = 0 - // t.elementBlockSize = 0 - // t.elementBlockStride = nullptr - // t.trLoadPairStride = nullptr - // } - // info.colStrideReg = Literal Value: UInt32 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // t.trLoadPairStride = Add(Multiply(8:U32, 2:U32)U32, 0:U32)U32 - // } - // info.offset = Literal Value: UInt32 x 0: 112 - // info.bufDesc = (nullptr) - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 262) info.m = 1 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 0 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 -ds_read_b64 v[18:19], v3 offset:112 // (op 262) Load local data -// DSMEM: Expected complete at 3222 (current 3202) -// Extra srcs: LDS Value: Halfx2 x 0: LDS:(Offset: 0, Size: 8192) - // (op 261) LoadLDSTile{Value: Halfx2}(262) END - // (op 261) end: generate({262}) - // (op 217) SetCoordinate(261) END - // (op 217) Multiply(263) BEGIN - // (op 263) Generate MatrixMultiply(WaveTile2xH, WaveTile2xH, {DataFlowTag35: a[0:15]:S})S into DataFlowTag35: ACCVGPR Value: Float x 16: a[0:15] -s_waitcnt lgkmcnt(0) -v_mfma_f32_32x32x8f16 a[0:15], v[16:17], v[18:19], a[0:15] // (op 263) - // (op 217) Multiply(263) END - // (op 217) Deallocate{}(1797) BEGIN - // (op 1797) Deallocate 352 - // Freeing : 2 VGPRs (Value: Halfx2) (op 262): v18, v19 - - // Deleting tag 352 - // (op 1797) Deallocate 350 - // Freeing : 2 VGPRs (Value: Halfx2) (op 260): v16, v17 - - // Deleting tag 350 - // (op 217) Deallocate{}(1797) END - // (op 217) end: generate({219, 1726}) - // (op 217) For Loop Increment - // (op 217) generate({}) - // (op 217) end: generate({}) - // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 if true) - // (op 217) Generate LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL into SCC Value: Bool x 1: scc - // (op 217) Get arg Tensor_0_size_1_10 - // (op 217) LessThan({DataFlowTag316: s40:U32}, Convert(ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64)U32)BL - // (op 217) ArithmeticShiftR({Tensor_0_size_1_10: s[20:21]:I64}, 6:U32)I64 -// Allocated : 2 SGPRs (Value: Int64) (op 217): s16, s17 -s_ashr_i64 s[16:17], s[20:21], 6 // (op 217) -// Allocated : 1 SGPR (Value: UInt32) (op 217): s41 -s_mov_b32 s41, s16 // (op 217) convert - // Freeing : 2 SGPRs (Value: Int64) (op 217): s16, s17 - -s_cmp_lt_u32 s40, s41 // (op 217) - // Freeing : 1 SGPR (Value: UInt32) (op 217): s41 - -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 217) -s_cbranch_scc1 RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 // (op 217) Condition: Bottom (jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopTop_KLoopTail_217 if true) -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ForLoopBottom_KLoopTail_217: - // (op 217) -s_waitcnt vmcnt(0) lgkmcnt(0) expcnt(0)// DEBUG: Wait after branch - // (op 217) - // (op 217) Unlock For Loop - // Unlock None - // (op 1051) ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217) END - // (op 1051) Deallocate{}(1781) BEGIN - // (op 1781) Deallocate 316 - // Freeing DataFlowTag316: 1 SGPR (Value: UInt32) (op 218): s40 - - // Deleting tag 316 - // (op 1781) Deallocate 538 - // Freeing DataFlowTag538: 1 SGPR (Value: UInt32) (op 1268): s1 - - // Deleting tag 538 - // (op 1781) Deallocate 541 - // Deleting tag 541 - // (op 1781) Deallocate 539 - // Deleting tag 539 - // (op 1781) Deallocate 523 - // Deleting tag 523 - // (op 1781) Deallocate 500 - // Deleting tag 500 - // (op 1781) Deallocate 498 - // Deleting tag 498 - // (op 1781) Deallocate 494 - // Deleting tag 494 - // (op 1781) Deallocate 493 - // Freeing DataFlowTag493: 2 VGPRs (Value: UInt64) (op 1123): v14, v15 - - // Deleting tag 493 - // (op 1781) Deallocate 481 - // Deleting tag 481 - // (op 1781) Deallocate 479 - // Deleting tag 479 - // (op 1781) Deallocate 475 - // Deleting tag 475 - // (op 1781) Deallocate 474 - // Freeing DataFlowTag474: 2 VGPRs (Value: UInt64) (op 1056): v12, v13 - - // Deleting tag 474 - // (op 1781) Deallocate 522 - // Freeing DataFlowTag522: 1 SGPR (Value: UInt32) (op 1216): s0 - - // Deleting tag 522 - // (op 1781) Deallocate 525 - // Deleting tag 525 - // (op 1051) Deallocate{}(1781) END - // (op 1051) end: generate({1045}) - // (op 1051) Unlock Scope 1051 - // Unlock None - // (op 314) Scope(1051) END - // (op 314) end: generate({1051}) - // (op 313) SetCoordinate(314) END - // (op 313) end: generate({314}) - // (op 670) SetCoordinate(313) END - // (op 670) Deallocate{}(1799) BEGIN - // (op 1799) Deallocate 58 - // Deleting tag 58 - // (op 1799) Deallocate 303 - // Deleting tag 303 - // (op 1799) Deallocate 118 - // Deleting tag 118 - // (op 1799) Deallocate 477 - // Freeing DataFlowTag477: 4 SGPRs (Buffer: None) (op 1084): s32, s33, s34, s35 - - // Deleting tag 477 - // (op 1799) Deallocate 496 - // Freeing DataFlowTag496: 4 SGPRs (Buffer: None) (op 1148): s36, s37, s38, s39 - - // Deleting tag 496 - // (op 1799) Deallocate 532 - // Deleting tag 532 - // (op 1799) Deallocate 133 - // Deleting tag 133 - // (op 1799) Deallocate 73 - // Deleting tag 73 - // (op 1799) Deallocate 301 - // Deleting tag 301 - // (op 1799) Deallocate 21 - // Deleting tag 21 - // (op 1799) Deallocate 548 - // Deleting tag 548 - // (op 1799) Deallocate 13 - // Deleting tag 13 - // (op 670) Deallocate{}(1799) END - // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) BEGIN - // (op 2003) Deallocate Tensor_2_pointer - // Freeing Tensor_2_pointer: 2 SGPRs (Value: Raw32): s10, s11 - - // (op 2003) Deallocate Tensor_0_pointer - // Freeing Tensor_0_pointer: 2 SGPRs (Value: Raw32): s6, s7 - - // (op 2003) Deallocate Tensor_0_extent_0 - // Freeing Tensor_0_extent_0: 2 SGPRs (Value: Raw32): s4, s5 - - // (op 2003) Deallocate Tensor_2_stride_1_12 - // Freeing Tensor_2_stride_1_12: 2 SGPRs (Value: Raw32): s22, s23 - - // (op 2003) Deallocate Tensor_0_stride_0_9 - // Freeing Tensor_0_stride_0_9: 2 SGPRs (Value: Raw32): s18, s19 - - // (op 2003) Deallocate Tensor_2_extent_2 - // Freeing Tensor_2_extent_2: 2 SGPRs (Value: Raw32): s8, s9 - - // (op 2003) Deallocate Tensor_0_size_1_10 - // Freeing Tensor_0_size_1_10: 2 SGPRs (Value: Raw32): s20, s21 - - // (op 670) Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003) END - // (op 670) Barrier(1801) BEGIN -s_barrier // (op 1801) - // (op 670) Barrier(1801) END - // (op 670) end: generate({675}) - // (op 670) Unlock Scope 670 - // Unlock None - // (op 1) Scope(670) END - // (op 1) Deallocate{}(1867) BEGIN - // (op 1867) Deallocate 631 - // Deleting tag 631 - // (op 1867) Deallocate 629 - // Deleting tag 629 - // (op 1867) Deallocate 619 - // Deleting tag 619 - // (op 1867) Deallocate 531 - // Deleting tag 531 - // (op 1867) Deallocate 568 - // Freeing DataFlowTag568: 1 VGPR (Value: UInt32) (op 1368): v4 - - // Deleting tag 568 - // (op 1867) Deallocate 604 - // Freeing DataFlowTag604: 1 VGPR (Value: UInt32) (op 1485): v7 - - // Deleting tag 604 - // (op 1867) Deallocate 546 - // Freeing DataFlowTag546: 1 VGPR (Value: UInt32) (op 1295): v3 - - // Deleting tag 546 - // (op 1867) Deallocate 605 - // Deleting tag 605 - // (op 1867) Deallocate 547 - // Deleting tag 547 - // (op 1867) Deallocate 530 - // Freeing DataFlowTag530: 1 VGPR (Value: UInt32) (op 1243): v0 - - // Deleting tag 530 - // (op 1867) Deallocate 533 - // Deleting tag 533 - // (op 1867) Deallocate 580 - // Freeing DataFlowTag580: 1 VGPR (Value: UInt32) (op 1407): v5 - - // Deleting tag 580 - // (op 1867) Deallocate 616 - // Freeing DataFlowTag616: 1 VGPR (Value: UInt32) (op 1524): v8 - - // Deleting tag 616 - // (op 1867) Deallocate 628 - // Freeing DataFlowTag628: 1 VGPR (Value: UInt32) (op 1563): v9 - - // Deleting tag 628 - // (op 1867) Deallocate 569 - // Deleting tag 569 - // (op 1867) Deallocate 617 - // Deleting tag 617 - // (op 1867) Deallocate 581 - // Deleting tag 581 - // (op 1867) Deallocate 593 - // Deleting tag 593 - // (op 1867) Deallocate 571 - // Deleting tag 571 - // (op 1867) Deallocate 549 - // Deleting tag 549 - // (op 1867) Deallocate 607 - // Deleting tag 607 - // (op 1867) Deallocate 583 - // Deleting tag 583 - // (op 1867) Deallocate 592 - // Freeing DataFlowTag592: 1 VGPR (Value: UInt32) (op 1446): v6 - - // Deleting tag 592 - // (op 1867) Deallocate 595 - // Deleting tag 595 - // (op 1) Deallocate{}(1867) END - // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) BEGIN - // (op 177) Lock for Conditional - // Lock Branch - // (op 177) Generate Equal(0.00000:S, DataFlowTag(24)S)BL into VCC Value: Bool64 x 1: vcc - // (op 177) reg expression - // (op 177) Equal(0.00000:S, v10:S)BL64 -v_cmp_eq_f32 vcc, 0.00000, v10 // (op 177) -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 177) -s_cbranch_vccz RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177 // (op 177) Condition: False, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177 - // (op 177) generate({678}) - // (op 177) Scope(678) BEGIN - // (op 678) Lock Scope 678 - // Lock Branch - // (op 678) generate({681}) - // (op 678) NOP(681) BEGIN - // (op 681) generate({}) - // (op 681) end: generate({}) - // (op 678) NOP(681) END - // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) BEGIN - // (op 29) Assign dim(39) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA - // (op 29) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr - // (op 29) reg expression - // (op 29) reg expression - // (op 29) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S -// Allocated : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 -s_nop 3 -v_accvgpr_read v12, a0 // (op 29) Wait state hazard: XDL Write Hazard -v_accvgpr_read v13, a1 // (op 29) -v_accvgpr_read v14, a2 // (op 29) -v_accvgpr_read v15, a3 // (op 29) -v_accvgpr_read v16, a4 // (op 29) -v_accvgpr_read v17, a5 // (op 29) -v_accvgpr_read v18, a6 // (op 29) -v_accvgpr_read v19, a7 // (op 29) -v_accvgpr_read v20, a8 // (op 29) -v_accvgpr_read v21, a9 // (op 29) -v_accvgpr_read v22, a10 // (op 29) -v_accvgpr_read v23, a11 // (op 29) -v_accvgpr_read v24, a12 // (op 29) -v_accvgpr_read v25, a13 // (op 29) -v_accvgpr_read v26, a14 // (op 29) -v_accvgpr_read v27, a15 // (op 29) -// Allocated : 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 -v_mul_f32 v28, v11, v12 // (op 29) -v_mul_f32 v29, v11, v13 // (op 29) -v_mul_f32 v30, v11, v14 // (op 29) -v_mul_f32 v31, v11, v15 // (op 29) -v_mul_f32 v32, v11, v16 // (op 29) -v_mul_f32 v33, v11, v17 // (op 29) -v_mul_f32 v34, v11, v18 // (op 29) -v_mul_f32 v35, v11, v19 // (op 29) -v_mul_f32 v36, v11, v20 // (op 29) -v_mul_f32 v37, v11, v21 // (op 29) -v_mul_f32 v38, v11, v22 // (op 29) -v_mul_f32 v39, v11, v23 // (op 29) -v_mul_f32 v40, v11, v24 // (op 29) -v_mul_f32 v41, v11, v25 // (op 29) -v_mul_f32 v42, v11, v26 // (op 29) -v_mul_f32 v43, v11, v27 // (op 29) - // Freeing : 16 VGPRs (Value: Float) (op 29): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 - - // (op 678) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29) END - // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) BEGIN - // (op 35) Assign dim(41) = Convert(DataFlowTag(39)NA)H - // (op 35) Generate Convert(DataFlowTag(39)NA)H into nullptr - // (op 35) reg expression -// Allocated DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 -v_cvt_f16_f32 v12, v28 // (op 35) -v_cvt_f16_f32 v13, v29 // (op 35) -v_cvt_f16_f32 v14, v30 // (op 35) -v_cvt_f16_f32 v15, v31 // (op 35) -v_cvt_f16_f32 v16, v32 // (op 35) -v_cvt_f16_f32 v17, v33 // (op 35) -v_cvt_f16_f32 v18, v34 // (op 35) -v_cvt_f16_f32 v19, v35 // (op 35) -v_cvt_f16_f32 v20, v36 // (op 35) -v_cvt_f16_f32 v21, v37 // (op 35) -v_cvt_f16_f32 v22, v38 // (op 35) -v_cvt_f16_f32 v23, v39 // (op 35) -v_cvt_f16_f32 v24, v40 // (op 35) -v_cvt_f16_f32 v25, v41 // (op 35) -v_cvt_f16_f32 v26, v42 // (op 35) -v_cvt_f16_f32 v27, v43 // (op 35) - // (op 678) Assign VGPR Convert(DataFlowTag(39)NA)H(35) END - // (op 678) Deallocate{}(1761) BEGIN - // (op 1761) Deallocate 39 - // Freeing DataFlowTag39: 16 VGPRs (Value: Float) (op 29): v28, v29, v30, v31, v32, v33, v34, v35, v36, v37, v38, v39, v40, v41, v42, v43 - - // Deleting tag 39 - // (op 678) Deallocate{}(1761) END - // (op 678) NOP(1305) BEGIN - // (op 1305) generate({}) - // (op 1305) end: generate({}) - // (op 678) NOP(1305) END - // (op 678) NOP(1302) BEGIN - // (op 1302) generate({}) - // (op 1302) end: generate({}) - // (op 678) NOP(1302) END - // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) BEGIN - // (op 1309) Assign dim(550) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} - // tag 550: v**UNALLOCATED** - // (op 1309) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag550: VGPR Value: UInt32 x 1: (unallocated) - // (op 1309) Get arg Tensor_15_stride_1_14 - // (op 1309) reg expression - // (op 1309) reg expression - // (op 1309) reg expression - // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1309) reg expression -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 -v_lshrrev_b32 v0, 7, v1 // (op 1309) - // (op 1309) convert - // (op 1309) BEGIN: Tile[1] - // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 -v_and_b32 v3, 63, v1 // (op 1309) - // (op 1309) END: Tile[1] - // (op 1309) LogicalShiftR({Tile[1]: v3:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_lshrrev_b32 v4, 5, v3 // (op 1309) - // (op 1309) BEGIN: Flatten - // (op 1309) {Flatten: ShiftL(v4:U32, 2:U32)U32} - // (op 1309) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1309) value (VGPR Value: UInt32 x 1: v4) - // (op 1309) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v5 -v_lshlrev_b32 v5, 2, v4 // (op 1309) - // (op 1309) END: Flatten - // Freeing : 1 VGPR (Value: UInt32) (op 1309): v4 - - // (op 1309) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_lshl_add_u32 v4, v0, 5, v5 // (op 1309) - // (op 1309) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v5 - - // Freeing : 1 VGPR (Value: UInt32) (op 1309): v0 - - // (op 1309) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v0 -v_lshl_add_u32 v0, s2, 6, v4 // (op 1309) - // (op 1309) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v4 - - // (op 1309) LogicalShiftR({Tile[1]: v3:U32}, 2:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_lshrrev_b32 v4, 2, v3 // (op 1309) - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v3 - - // (op 1309) BEGIN: Tile[1] - // (op 1309) {Tile[1]: BitwiseAnd(v4:U32, 7:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 -v_and_b32 v3, 7, v4 // (op 1309) - // (op 1309) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1309): v4 - - // (op 1309) BEGIN: Tile[1] - // (op 1309) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_and_b32 v4, 3, v1 // (op 1309) - // (op 1309) END: Tile[1] - // (op 1309) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v5 -v_lshl_add_u32 v5, v3, 2, v4 // (op 1309) - // (op 1309) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v4 - - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v3 - - // (op 1309) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 -v_lshrrev_b32 v3, 6, v1 // (op 1309) - // (op 1309) BEGIN: Tile[1] - // (op 1309) {Tile[1]: BitwiseAnd(v3:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_and_b32 v4, 1, v3 // (op 1309) - // (op 1309) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1309): v3 - - // (op 1309) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 -v_lshl_add_u32 v3, v4, 5, v5 // (op 1309) - // (op 1309) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v5 - - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1309): v4 - - // (op 1309) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v4 -v_lshl_add_u32 v4, s3, 6, v3 // (op 1309) - // (op 1309) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v3 - - // (op 1309) Multiply({Flatten: v4:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1309): v3 -v_mul_lo_u32 v3, v4, s26 // (op 1309) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v4 - - // (op 1309) BEGIN: Join -// Allocated DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v4 -v_add_lshl_u32 v4, v0, v3, 1 // (op 1309) - // (op 1309) END: Join - // Freeing : 1 VGPR (Value: UInt32) (op 1309): v3 - - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1309): v0 - - // (op 678) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309) END - // (op 678) Assign VGPR 16:U64(1310) BEGIN - // (op 1310) Assign dim(551) = 16:U64 - // (op 1310) Assign stride expression - // (op 678) Assign VGPR 16:U64(1310) END - // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) BEGIN - // (op 1311) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // tag 553: s**UNALLOCATED** - // (op 1311) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: (unallocated) - // (op 1311) Get arg Tensor_15_pointer - // (op 1311) Get arg Tensor_15_extent_15 - // (op 1311) reg expression - // (op 1311) reg expression - // (op 1311) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 - // (op 1311) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1311) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) - // (op 1311) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1311): s0, s1 -s_lshl_b64 s[0:1], s[28:29], 1 // (op 1311) - // (op 1311) reg expression -// Allocated DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s4, s5, s6, s7 -s_mov_b32 s4, s30 // (op 1311) reg expression -s_mov_b32 s5, s31 // (op 1311) reg expression -s_mov_b32 s6, s0 // (op 1311) reg expression -s_mov_b32 s7, 131072 // (op 1311) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1311): s0, s1 - - // (op 678) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311) END - // (op 678) NOP(1303) BEGIN - // (op 1303) generate({}) - // (op 1303) end: generate({}) - // (op 678) NOP(1303) END - // (op 678) Assign VGPR 2:U64(1316) BEGIN - // (op 1316) Assign dim(555) = 2:U64 - // (op 1316) Assign stride expression - // (op 678) Assign VGPR 2:U64(1316) END - // (op 678) StoreTiled Value: Halfx2(37) BEGIN - // (op 37) GEN: storeMacroTileWAVE OP 37 MacroTile 41 WaveTile 215 - // (op 37) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 37) Generate 16:U64 into nullptr - // (op 37) Generate 2:U64 into nullptr - // (op 37) Convert in LSTGen - // (op 37) Generate Convert({DataFlowTag39: v[12:27]:H})2xH into nullptr - // (op 37) reg expression -// Allocated DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 -v_pack_b32_f16 v28, v12, v13 // (op 37) -v_pack_b32_f16 v29, v14, v15 // (op 37) -v_pack_b32_f16 v30, v16, v17 // (op 37) -v_pack_b32_f16 v31, v18, v19 // (op 37) -v_pack_b32_f16 v32, v20, v21 // (op 37) -v_pack_b32_f16 v33, v22, v23 // (op 37) -v_pack_b32_f16 v34, v24, v25 // (op 37) -v_pack_b32_f16 v35, v26, v27 // (op 37) - // (op 37) Dir = Store - // LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 37) LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = DataFlowTag39: VGPR Value: Halfx2 x 8: v[28:35] - // info.rowOffsetReg = DataFlowTag550: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 37) info.m = 4 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 16 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -buffer_store_dwordx2 v[28:29], v4, s[4:7], 0 offen // (op 37) Store value -// VMEM: Expected complete at 3374 (current 3299) -buffer_store_dwordx2 v[30:31], v4, s[4:7], 0 offen offset:16 // (op 37) Store value -// VMEM: Expected complete at 3375 (current 3300) -buffer_store_dwordx2 v[32:33], v4, s[4:7], 0 offen offset:32 // (op 37) Store value -// VMEM: Expected complete at 3376 (current 3301) -buffer_store_dwordx2 v[34:35], v4, s[4:7], 0 offen offset:48 // (op 37) Store value -// VMEM: Expected complete at 3377 (current 3302) - // Freeing DataFlowTag39: 8 VGPRs (Value: Halfx2) (op 37): v28, v29, v30, v31, v32, v33, v34, v35 - - // (op 678) Tag 37non referenced extraArgs = {Tensor_15_stride_1_14} - - // (op 678) StoreTiled Value: Halfx2(37) END - // (op 678) Deallocate{}(1763) BEGIN - // (op 1763) Deallocate 551 - // Deleting tag 551 - // (op 1763) Deallocate 555 - // Deleting tag 555 - // (op 1763) Deallocate 554 - // Deleting tag 554 - // (op 1763) Deallocate 41 - // Freeing DataFlowTag39: 16 VGPRs (Value: Half) (op 35): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 - - // Deleting tag 41 - // (op 1763) Deallocate 550 - // Freeing DataFlowTag550: 1 VGPR (Value: UInt32) (op 1309): v4 - - // Deleting tag 550 - // (op 678) Deallocate{}(1763) END - // (op 678) end: generate({681}) - // (op 678) Unlock Scope 678 - // Unlock None - // (op 177) Scope(678) END - // (op 177) end: generate({678}) -s_waitcnt vmcnt(63) lgkmcnt(15) expcnt(7)// Keep queues within max waitcnt limit - // (op 177) -s_branch RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177 // (op 177) Condition: Done, jump to RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177 -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalFalse_0_beta_177: - // (op 177) - // (op 177) generate({684}) - // (op 177) Scope(684) BEGIN - // (op 684) Lock Scope 684 - // Lock Branch - // (op 684) generate({687}) - // (op 684) NOP(687) BEGIN - // (op 687) generate({}) - // (op 687) end: generate({}) - // (op 684) NOP(687) END - // (op 684) NOP(185) BEGIN - // (op 185) generate({}) - // (op 185) end: generate({}) - // (op 684) NOP(185) END - // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) BEGIN - // (op 186) Assign dim(295) = Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA - // (op 186) Generate Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA into nullptr - // (op 186) reg expression - // (op 186) reg expression - // (op 186) Multiply(v11:S, {DataFlowTag35: a[0:15]:S})S - // (op 684) Scope(1181) BEGIN - // (op 1181) Lock Scope 1181 - // Lock Branch - // (op 1181) generate({1178}) - // (op 1181) NOP(1178) BEGIN - // (op 1178) generate({}) - // (op 1178) end: generate({}) - // (op 1181) NOP(1178) END - // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) BEGIN - // (op 1186) Assign dim(512) = {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} - // tag 512: v**UNALLOCATED** - // (op 1186) Generate {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32} into DataFlowTag512: VGPR Value: UInt32 x 1: (unallocated) - // (op 1186) Get arg Tensor_4_stride_1_13 - // (op 1186) reg expression - // (op 1186) reg expression - // (op 1186) reg expression - // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1186) reg expression -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 -v_lshrrev_b32 v0, 7, v1 // (op 1186) - // (op 1186) convert - // (op 1186) BEGIN: Flatten[1] - // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 -v_and_b32 v3, 63, v1 // (op 1186) - // (op 1186) END: Flatten[1] - // (op 1186) LogicalShiftR({Flatten[1]: v3:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_lshrrev_b32 v4, 5, v3 // (op 1186) - // (op 1186) BEGIN: Tile - // (op 1186) {Tile: ShiftL(v4:U32, 2:U32)U32} - // (op 1186) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1186) value (VGPR Value: UInt32 x 1: v4) - // (op 1186) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v5 -v_lshlrev_b32 v5, 2, v4 // (op 1186) - // (op 1186) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1186): v4 - - // (op 1186) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_lshl_add_u32 v4, v0, 5, v5 // (op 1186) - // (op 1186) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v5 - - // Freeing : 1 VGPR (Value: UInt32) (op 1186): v0 - - // (op 1186) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v0 -v_lshl_add_u32 v0, s2, 6, v4 // (op 1186) - // (op 1186) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 - - // (op 1186) LogicalShiftR({Flatten[1]: v3:U32}, 2:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_lshrrev_b32 v4, 2, v3 // (op 1186) - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v3 - - // (op 1186) BEGIN: Flatten[1] - // (op 1186) {Flatten[1]: BitwiseAnd(v4:U32, 7:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 -v_and_b32 v3, 7, v4 // (op 1186) - // (op 1186) END: Flatten[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1186): v4 - - // (op 1186) BEGIN: Flatten[1] - // (op 1186) {Flatten[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_and_b32 v4, 3, v1 // (op 1186) - // (op 1186) END: Flatten[1] - // (op 1186) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v5 -v_lshl_add_u32 v5, v3, 2, v4 // (op 1186) - // (op 1186) END: Tile - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v4 - - // Freeing Flatten[1]: 1 VGPR (Value: UInt32) (op 1186): v3 - - // (op 1186) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 -v_lshrrev_b32 v3, 6, v1 // (op 1186) - // (op 1186) BEGIN: Tile - // (op 1186) {Tile: BitwiseAnd(v3:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_and_b32 v4, 1, v3 // (op 1186) - // (op 1186) END: Tile - // Freeing : 1 VGPR (Value: UInt32) (op 1186): v3 - - // (op 1186) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 -v_lshl_add_u32 v3, v4, 5, v5 // (op 1186) - // (op 1186) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v5 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 - - // (op 1186) BEGIN: Tile -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v4 -v_lshl_add_u32 v4, s3, 6, v3 // (op 1186) - // (op 1186) END: Tile - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v3 - - // (op 1186) Multiply({Tile: v4:U32}, { convertForwardSubsetTensor_4_stride_1_13: s24:U32})U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1186): v3 -v_mul_lo_u32 v3, v4, s24 // (op 1186) - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v4 - - // (op 1186) BEGIN: Split -// Allocated DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v4 -v_add_lshl_u32 v4, v0, v3, 1 // (op 1186) - // (op 1186) END: Split - // Freeing : 1 VGPR (Value: UInt32) (op 1186): v3 - - // Freeing Tile: 1 VGPR (Value: UInt32) (op 1186): v0 - - // (op 1181) Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186) END - // (op 1181) Deallocate{}(1911) BEGIN - // (op 1911) Deallocate 305 - // Deleting tag 305 - // (op 1911) Deallocate 174 - // Deleting tag 174 - // (op 1911) Deallocate 307 - // Deleting tag 307 - // (op 1181) Deallocate{}(1911) END - // (op 1181) Assign VGPR 16:U64(1187) BEGIN - // (op 1187) Assign dim(513) = 16:U64 - // (op 1187) Assign stride expression - // (op 1181) Assign VGPR 16:U64(1187) END - // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) BEGIN - // (op 1188) Assign dim(515) = Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // tag 515: s**UNALLOCATED** - // (op 1188) Generate Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag515: SGPR Buffer: None x 1: (unallocated) - // (op 1188) Get arg Tensor_4_pointer - // (op 1188) Get arg Tensor_4_extent_4 - // (op 1188) reg expression - // (op 1188) reg expression - // (op 1188) ShiftL({Tensor_4_extent_4: s[12:13]:I64}, 1:U32)I64 - // (op 1188) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1188) value (Tensor_4_extent_4: SGPR Value: Int64 x 1: s[12:13]) - // (op 1188) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1188): s0, s1 -s_lshl_b64 s[0:1], s[12:13], 1 // (op 1188) - // (op 1188) reg expression -// Allocated DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s8, s9, s10, s11 -s_mov_b32 s8, s14 // (op 1188) reg expression -s_mov_b32 s9, s15 // (op 1188) reg expression -s_mov_b32 s10, s0 // (op 1188) reg expression -s_mov_b32 s11, 131072 // (op 1188) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1188): s0, s1 - - // (op 1181) Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188) END - // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) BEGIN - // (op 2007) Deallocate Tensor_4_pointer - // Freeing Tensor_4_pointer: 2 SGPRs (Value: Raw32): s14, s15 - - // (op 2007) Deallocate Tensor_4_extent_4 - // Freeing Tensor_4_extent_4: 2 SGPRs (Value: Raw32): s12, s13 - - // (op 1181) Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007) END - // (op 1181) NOP(1179) BEGIN - // (op 1179) generate({}) - // (op 1179) end: generate({}) - // (op 1181) NOP(1179) END - // (op 1181) Assign VGPR 2:U64(1193) BEGIN - // (op 1193) Assign dim(517) = 2:U64 - // (op 1193) Assign stride expression - // (op 1181) Assign VGPR 2:U64(1193) END - // (op 1181) LoadTiled Value: Halfx2(190) BEGIN - // (op 190) GEN: loadMacroTileWAVECIACCUM OP 190 WaveTile 175 - // (op 190) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 190) Generate 16:U64 into nullptr - // (op 190) Generate 2:U64 into nullptr - // tag 291: v**UNALLOCATED** - // (op 190) Dir = Load - // LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 8: (unallocated) - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[8:11] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 190) LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = VGPR Value: Halfx2 x 8: (unallocated) - // info.rowOffsetReg = DataFlowTag512: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag515: SGPR Buffer: None x 1: s[8:11] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 190) info.m = 4 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 16 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -// Allocated : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 -buffer_load_dwordx2 v[12:13], v4, s[8:11], 0 offen // (op 190) Load value -// VMEM: Expected stall of 49. CBNW: 0, Inc: 4 -// VMEM: Expected complete at 3450 (current 3375) -buffer_load_dwordx2 v[14:15], v4, s[8:11], 0 offen offset:16 // (op 190) Load value -// VMEM: Expected complete at 3451 (current 3376) -buffer_load_dwordx2 v[16:17], v4, s[8:11], 0 offen offset:32 // (op 190) Load value -// VMEM: Expected complete at 3452 (current 3377) -buffer_load_dwordx2 v[18:19], v4, s[8:11], 0 offen offset:48 // (op 190) Load value -// VMEM: Expected complete at 3453 (current 3378) - // (op 1181) Tag 190non referenced extraArgs = {Tensor_4_stride_1_13} - - // (op 1181) LoadTiled Value: Halfx2(190) END - // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) BEGIN - // (op 1777) Deallocate 3 - // Deleting tag 3 - // (op 1777) Deallocate 513 - // Deleting tag 513 - // (op 1777) Deallocate 515 - // Freeing DataFlowTag515: 4 SGPRs (Buffer: None) (op 1188): s8, s9, s10, s11 - - // Deleting tag 515 - // (op 1777) Deallocate 512 - // Freeing DataFlowTag512: 1 VGPR (Value: UInt32) (op 1186): v4 - - // Deleting tag 512 - // (op 1777) Deallocate 516 - // Deleting tag 516 - // (op 1777) Deallocate 517 - // Deleting tag 517 - // (op 1777) Deallocate Tensor_4_stride_1_13 - // Freeing Tensor_4_stride_1_13: 2 SGPRs (Value: Raw32): s24, s25 - - // (op 1181) Deallocate{Tensor_4_stride_1_13}(1777) END - // (op 1181) end: generate({1178}) - // (op 1181) Unlock Scope 1181 - // Unlock None - // (op 684) Scope(1181) END -// Allocated : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 -v_accvgpr_read v20, a0 // (op 186) - // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) BEGIN - // (op 191) Assign dim(293) = Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA - // (op 191) Generate Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA into nullptr - // (op 191) reg expression - // (op 191) reg expression - // (op 191) Multiply(v10:S, v[12:19]:2xH)S -v_accvgpr_read v21, a1 // (op 186) -v_accvgpr_read v22, a2 // (op 186) -v_accvgpr_read v23, a3 // (op 186) -v_accvgpr_read v24, a4 // (op 186) -v_accvgpr_read v25, a5 // (op 186) -v_accvgpr_read v26, a6 // (op 186) -v_accvgpr_read v27, a7 // (op 186) -v_accvgpr_read v28, a8 // (op 186) -v_accvgpr_read v29, a9 // (op 186) -v_accvgpr_read v30, a10 // (op 186) -v_accvgpr_read v31, a11 // (op 186) -v_accvgpr_read v32, a12 // (op 186) -v_accvgpr_read v33, a13 // (op 186) -v_accvgpr_read v34, a14 // (op 186) -v_accvgpr_read v35, a15 // (op 186) -// Allocated : 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 -v_mul_f32 v36, v11, v20 // (op 186) -v_mul_f32 v37, v11, v21 // (op 186) -v_mul_f32 v38, v11, v22 // (op 186) -v_mul_f32 v39, v11, v23 // (op 186) -v_mul_f32 v40, v11, v24 // (op 186) -v_mul_f32 v41, v11, v25 // (op 186) -v_mul_f32 v42, v11, v26 // (op 186) -v_mul_f32 v43, v11, v27 // (op 186) -v_mul_f32 v44, v11, v28 // (op 186) -v_mul_f32 v45, v11, v29 // (op 186) -v_mul_f32 v46, v11, v30 // (op 186) -v_mul_f32 v47, v11, v31 // (op 186) -v_mul_f32 v48, v11, v32 // (op 186) -v_mul_f32 v49, v11, v33 // (op 186) -v_mul_f32 v50, v11, v34 // (op 186) -v_mul_f32 v51, v11, v35 // (op 186) - // Freeing : 16 VGPRs (Value: Float) (op 186): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 - - // (op 684) Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186) END -// Allocated : 2 VGPRs (Value: Float) (op 191): v8, v9 -s_waitcnt vmcnt(3) -v_cvt_f32_f16 v8, v12 // (op 191) -v_lshrrev_b32 v9, 16, v12 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -// Allocated : 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 -v_mul_f32 v20, v10, v8 // (op 191) -v_mul_f32 v21, v10, v9 // (op 191) -v_cvt_f32_f16 v8, v13 // (op 191) -v_lshrrev_b32 v9, 16, v13 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v22, v10, v8 // (op 191) -v_mul_f32 v23, v10, v9 // (op 191) -s_waitcnt vmcnt(2) -v_cvt_f32_f16 v8, v14 // (op 191) -v_lshrrev_b32 v9, 16, v14 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v24, v10, v8 // (op 191) -v_mul_f32 v25, v10, v9 // (op 191) -v_cvt_f32_f16 v8, v15 // (op 191) -v_lshrrev_b32 v9, 16, v15 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v26, v10, v8 // (op 191) -v_mul_f32 v27, v10, v9 // (op 191) -s_waitcnt vmcnt(1) -v_cvt_f32_f16 v8, v16 // (op 191) -v_lshrrev_b32 v9, 16, v16 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v28, v10, v8 // (op 191) -v_mul_f32 v29, v10, v9 // (op 191) -v_cvt_f32_f16 v8, v17 // (op 191) -v_lshrrev_b32 v9, 16, v17 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v30, v10, v8 // (op 191) -v_mul_f32 v31, v10, v9 // (op 191) -s_waitcnt vmcnt(0) -v_cvt_f32_f16 v8, v18 // (op 191) -v_lshrrev_b32 v9, 16, v18 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v32, v10, v8 // (op 191) -v_mul_f32 v33, v10, v9 // (op 191) -v_cvt_f32_f16 v8, v19 // (op 191) -v_lshrrev_b32 v9, 16, v19 // (op 191) -v_cvt_f32_f16 v9, v9 // (op 191) -v_mul_f32 v34, v10, v8 // (op 191) -v_mul_f32 v35, v10, v9 // (op 191) - // Freeing : 2 VGPRs (Value: Float) (op 191): v8, v9 - - // (op 684) Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191) END - // (op 684) Deallocate{}(1779) BEGIN - // (op 1779) Deallocate 291 - // Freeing : 8 VGPRs (Value: Halfx2) (op 190): v12, v13, v14, v15, v16, v17, v18, v19 - - // Deleting tag 291 - // (op 684) Deallocate{}(1779) END - // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) BEGIN - // (op 187) Assign dim(297) = Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA - // (op 187) Generate Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA into nullptr - // (op 187) reg expression - // (op 187) reg expression - // (op 187) Add({DataFlowTag293: v[20:35]:S}, {DataFlowTag295: v[36:51]:S})S -// Allocated : 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 -v_add_f32 v52, v20, v36 // (op 187) -v_add_f32 v53, v21, v37 // (op 187) -v_add_f32 v54, v22, v38 // (op 187) -v_add_f32 v55, v23, v39 // (op 187) -v_add_f32 v56, v24, v40 // (op 187) -v_add_f32 v57, v25, v41 // (op 187) -v_add_f32 v58, v26, v42 // (op 187) -v_add_f32 v59, v27, v43 // (op 187) -v_add_f32 v60, v28, v44 // (op 187) -v_add_f32 v61, v29, v45 // (op 187) -v_add_f32 v62, v30, v46 // (op 187) -v_add_f32 v63, v31, v47 // (op 187) -v_add_f32 v64, v32, v48 // (op 187) -v_add_f32 v65, v33, v49 // (op 187) -v_add_f32 v66, v34, v50 // (op 187) -v_add_f32 v67, v35, v51 // (op 187) - // (op 684) Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187) END - // (op 684) Deallocate{}(1771) BEGIN - // (op 1771) Deallocate 293 - // Freeing DataFlowTag293: 16 VGPRs (Value: Float) (op 191): v20, v21, v22, v23, v24, v25, v26, v27, v28, v29, v30, v31, v32, v33, v34, v35 - - // Deleting tag 293 - // (op 1771) Deallocate 295 - // Freeing DataFlowTag295: 16 VGPRs (Value: Float) (op 186): v36, v37, v38, v39, v40, v41, v42, v43, v44, v45, v46, v47, v48, v49, v50, v51 - - // Deleting tag 295 - // (op 684) Deallocate{}(1771) END - // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) BEGIN - // (op 188) Assign dim(299) = Convert(DataFlowTag(297)NA)H - // (op 188) Generate Convert(DataFlowTag(297)NA)H into nullptr - // (op 188) reg expression -// Allocated DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 -v_cvt_f16_f32 v12, v52 // (op 188) -v_cvt_f16_f32 v13, v53 // (op 188) -v_cvt_f16_f32 v14, v54 // (op 188) -v_cvt_f16_f32 v15, v55 // (op 188) -v_cvt_f16_f32 v16, v56 // (op 188) -v_cvt_f16_f32 v17, v57 // (op 188) -v_cvt_f16_f32 v18, v58 // (op 188) -v_cvt_f16_f32 v19, v59 // (op 188) -v_cvt_f16_f32 v20, v60 // (op 188) -v_cvt_f16_f32 v21, v61 // (op 188) -v_cvt_f16_f32 v22, v62 // (op 188) -v_cvt_f16_f32 v23, v63 // (op 188) -v_cvt_f16_f32 v24, v64 // (op 188) -v_cvt_f16_f32 v25, v65 // (op 188) -v_cvt_f16_f32 v26, v66 // (op 188) -v_cvt_f16_f32 v27, v67 // (op 188) - // (op 684) Assign VGPR Convert(DataFlowTag(297)NA)H(188) END - // (op 684) Deallocate{}(1773) BEGIN - // (op 1773) Deallocate 297 - // Freeing DataFlowTag297: 16 VGPRs (Value: Float) (op 187): v52, v53, v54, v55, v56, v57, v58, v59, v60, v61, v62, v63, v64, v65, v66, v67 - - // Deleting tag 297 - // (op 684) Deallocate{}(1773) END - // (op 684) NOP(1322) BEGIN - // (op 1322) generate({}) - // (op 1322) end: generate({}) - // (op 684) NOP(1322) END - // (op 684) NOP(1319) BEGIN - // (op 1319) generate({}) - // (op 1319) end: generate({}) - // (op 684) NOP(1319) END - // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) BEGIN - // (op 1326) Assign dim(556) = {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} - // tag 556: v**UNALLOCATED** - // (op 1326) Generate {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32} into DataFlowTag556: VGPR Value: UInt32 x 1: (unallocated) - // (op 1326) Get arg Tensor_15_stride_1_14 - // (op 1326) reg expression - // (op 1326) reg expression - // (op 1326) reg expression - // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 7:U32)U32 - // (op 1326) reg expression -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 -v_lshrrev_b32 v0, 7, v1 // (op 1326) - // (op 1326) convert - // (op 1326) BEGIN: Tile[1] - // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 63:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 -v_and_b32 v3, 63, v1 // (op 1326) - // (op 1326) END: Tile[1] - // (op 1326) LogicalShiftR({Tile[1]: v3:U32}, 5:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_lshrrev_b32 v4, 5, v3 // (op 1326) - // (op 1326) BEGIN: Flatten - // (op 1326) {Flatten: ShiftL(v4:U32, 2:U32)U32} - // (op 1326) ShiftL: dest (VGPR Value: UInt32 x 1: (unallocated)) = - // (op 1326) value (VGPR Value: UInt32 x 1: v4) - // (op 1326) shiftAmount (Literal Value: UInt32 x 0: 2) -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v5 -v_lshlrev_b32 v5, 2, v4 // (op 1326) - // (op 1326) END: Flatten - // Freeing : 1 VGPR (Value: UInt32) (op 1326): v4 - - // (op 1326) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_lshl_add_u32 v4, v0, 5, v5 // (op 1326) - // (op 1326) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v5 - - // Freeing : 1 VGPR (Value: UInt32) (op 1326): v0 - - // (op 1326) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v0 -v_lshl_add_u32 v0, s2, 6, v4 // (op 1326) - // (op 1326) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v4 - - // (op 1326) LogicalShiftR({Tile[1]: v3:U32}, 2:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_lshrrev_b32 v4, 2, v3 // (op 1326) - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v3 - - // (op 1326) BEGIN: Tile[1] - // (op 1326) {Tile[1]: BitwiseAnd(v4:U32, 7:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 -v_and_b32 v3, 7, v4 // (op 1326) - // (op 1326) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1326): v4 - - // (op 1326) BEGIN: Tile[1] - // (op 1326) {Tile[1]: BitwiseAnd({Workitem Index X: v1:U32}, 3:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_and_b32 v4, 3, v1 // (op 1326) - // (op 1326) END: Tile[1] - // (op 1326) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v5 -v_lshl_add_u32 v5, v3, 2, v4 // (op 1326) - // (op 1326) END: Flatten - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v4 - - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v3 - - // (op 1326) LogicalShiftR({Workitem Index X: v1:U32}, 6:U32)U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 -v_lshrrev_b32 v3, 6, v1 // (op 1326) - // (op 1326) BEGIN: Tile[1] - // (op 1326) {Tile[1]: BitwiseAnd(v3:U32, 1:U32)U32} -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_and_b32 v4, 1, v3 // (op 1326) - // (op 1326) END: Tile[1] - // Freeing : 1 VGPR (Value: UInt32) (op 1326): v3 - - // (op 1326) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 -v_lshl_add_u32 v3, v4, 5, v5 // (op 1326) - // (op 1326) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v5 - - // Freeing Tile[1]: 1 VGPR (Value: UInt32) (op 1326): v4 - - // (op 1326) BEGIN: Flatten -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v4 -v_lshl_add_u32 v4, s3, 6, v3 // (op 1326) - // (op 1326) END: Flatten - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v3 - - // (op 1326) Multiply({Flatten: v4:U32}, { convertForwardSubsetTensor_15_stride_1_14: s26:U32})U32 -// Allocated : 1 VGPR (Value: UInt32) (op 1326): v3 -v_mul_lo_u32 v3, v4, s26 // (op 1326) - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v4 - - // (op 1326) BEGIN: Join -// Allocated DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v4 -v_add_lshl_u32 v4, v0, v3, 1 // (op 1326) - // (op 1326) END: Join - // Freeing : 1 VGPR (Value: UInt32) (op 1326): v3 - - // Freeing Flatten: 1 VGPR (Value: UInt32) (op 1326): v0 - - // (op 684) Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326) END - // (op 684) Assign VGPR 16:U64(1327) BEGIN - // (op 1327) Assign dim(557) = 16:U64 - // (op 1327) Assign stride expression - // (op 684) Assign VGPR 16:U64(1327) END - // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) BEGIN - // (op 1328) Assign dim(553) = Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB - // (op 1328) Generate Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB into DataFlowTag553: SGPR Buffer: None x 1: s[4:7] - // (op 1328) Get arg Tensor_15_pointer - // (op 1328) Get arg Tensor_15_extent_15 - // (op 1328) reg expression - // (op 1328) reg expression - // (op 1328) ShiftL({Tensor_15_extent_15: s[28:29]:I64}, 1:U32)I64 - // (op 1328) ShiftL: dest (SGPR Value: Int64 x 1: (unallocated)) = - // (op 1328) value (Tensor_15_extent_15: SGPR Value: Int64 x 1: s[28:29]) - // (op 1328) shiftAmount (Literal Value: UInt32 x 0: 1) -// Allocated : 2 SGPRs (Value: Int64) (op 1328): s0, s1 -s_lshl_b64 s[0:1], s[28:29], 1 // (op 1328) - // (op 1328) reg expression -s_mov_b32 s4, s30 // (op 1328) reg expression -s_mov_b32 s5, s31 // (op 1328) reg expression -s_mov_b32 s6, s0 // (op 1328) reg expression -s_mov_b32 s7, 131072 // (op 1328) call() - // Freeing : 2 SGPRs (Value: Int64) (op 1328): s0, s1 - - // (op 684) Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328) END - // (op 684) NOP(1320) BEGIN - // (op 1320) generate({}) - // (op 1320) end: generate({}) - // (op 684) NOP(1320) END - // (op 684) Assign VGPR 2:U64(1333) BEGIN - // (op 1333) Assign dim(559) = 2:U64 - // (op 1333) Assign stride expression - // (op 684) Assign VGPR 2:U64(1333) END - // (op 684) StoreTiled Value: Halfx2(189) BEGIN - // (op 189) GEN: storeMacroTileWAVE OP 189 MacroTile 299 WaveTile 215 - // (op 189) varTypeInfo.elementBits = 32 - // varTypeInfo.packing = 2 - - // (op 189) Generate 16:U64 into nullptr - // (op 189) Generate 2:U64 into nullptr - // (op 189) Convert in LSTGen - // (op 189) Generate Convert({DataFlowTag297: v[12:27]:H})2xH into nullptr - // (op 189) reg expression -// Allocated DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 -v_pack_b32_f16 v28, v12, v13 // (op 189) -v_pack_b32_f16 v29, v14, v15 // (op 189) -v_pack_b32_f16 v30, v16, v17 // (op 189) -v_pack_b32_f16 v31, v18, v19 // (op 189) -v_pack_b32_f16 v32, v20, v21 // (op 189) -v_pack_b32_f16 v33, v22, v23 // (op 189) -v_pack_b32_f16 v34, v24, v25 // (op 189) -v_pack_b32_f16 v35, v26, v27 // (op 189) - // (op 189) Dir = Store - // LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] - // info.rowOffsetReg = (nullptr) - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } allStridesAreLiteral = 1 - // colStrideIsOne = 1 - - // (op 189) LSTInfo { - // info.kind = Buffer - // info.m = 4 - // info.n = 2 - // info.elementBits = 32 - // info.packedAmount = 2 - // info.ldsWriteStride = 0 - // info.data = DataFlowTag297: VGPR Value: Halfx2 x 8: v[28:35] - // info.rowOffsetReg = DataFlowTag556: VGPR Value: UInt32 x 1: v4 - // info.rowStrideReg = Literal Value: UInt64 x 0: 16 - // info.rowStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 0 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(64:U64, 2:U32)U64, 0:U32)U64 - // } - // info.colStrideReg = Literal Value: UInt64 x 0: 2 - // info.colStrideAttributes = { - // t.dataType = UInt64 - // t.unitStride = 1 - // t.elementBlockSize = 8 - // t.elementBlockStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // t.trLoadPairStride = Add(Multiply(8:U64, 2:U32)U64, 0:U32)U64 - // } - // info.offset = Literal Value: UInt32 x 0: 0 - // info.bufDesc = DataFlowTag553: SGPR Buffer: None x 1: s[4:7] - // info.bufOpts = { options.offen = 0 - // options.glc = 0 - // options.slc = 0 - // options.sc1 = 0 - // options.lds = 0 - // } - // info.isTransposedTile = 0 - // } - // (op 189) info.m = 4 - // info.n = 2 - // elementsPerMove = 2 - // bytesPerMove = 8 - // rowStride = 16 - // colStride = 2 - // info.colStrideAttributes.elementBlockSize = 8 - // numVGPRBlocks = 1 - // elementBlockStride = 0 - -buffer_store_dwordx2 v[28:29], v4, s[4:7], 0 offen // (op 189) Store value -// VMEM: Expected complete at 3631 (current 3556) -buffer_store_dwordx2 v[30:31], v4, s[4:7], 0 offen offset:16 // (op 189) Store value -// VMEM: Expected complete at 3632 (current 3557) -buffer_store_dwordx2 v[32:33], v4, s[4:7], 0 offen offset:32 // (op 189) Store value -// VMEM: Expected complete at 3633 (current 3558) -buffer_store_dwordx2 v[34:35], v4, s[4:7], 0 offen offset:48 // (op 189) Store value -// VMEM: Expected complete at 3634 (current 3559) - // Freeing DataFlowTag297: 8 VGPRs (Value: Halfx2) (op 189): v28, v29, v30, v31, v32, v33, v34, v35 - - // (op 684) Tag 189non referenced extraArgs = {Tensor_15_stride_1_14} - - // (op 684) StoreTiled Value: Halfx2(189) END - // (op 684) Deallocate{}(1775) BEGIN - // (op 1775) Deallocate 558 - // Deleting tag 558 - // (op 1775) Deallocate 557 - // Deleting tag 557 - // (op 1775) Deallocate 559 - // Deleting tag 559 - // (op 1775) Deallocate 556 - // Freeing DataFlowTag556: 1 VGPR (Value: UInt32) (op 1326): v4 - - // Deleting tag 556 - // (op 1775) Deallocate 299 - // Freeing DataFlowTag297: 16 VGPRs (Value: Half) (op 188): v12, v13, v14, v15, v16, v17, v18, v19, v20, v21, v22, v23, v24, v25, v26, v27 - - // Deleting tag 299 - // (op 684) Deallocate{}(1775) END - // (op 684) end: generate({687}) - // (op 684) Unlock Scope 684 - // Unlock None - // (op 177) Scope(684) END - // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) BEGIN - // (op 1869) Deallocate 311 - // Deleting tag 311 - // (op 1869) Deallocate 553 - // Freeing DataFlowTag553: 4 SGPRs (Buffer: None) (op 1311): s4, s5, s6, s7 - - // Deleting tag 553 - // (op 1869) Deallocate 309 - // Deleting tag 309 - // (op 1869) Deallocate 214 - // Deleting tag 214 - // (op 1869) Deallocate Tensor_15_stride_1_14 - // Freeing Tensor_15_stride_1_14: 2 SGPRs (Value: Raw32): s26, s27 - - // (op 1869) Deallocate Tensor_15_extent_15 - // Freeing Tensor_15_extent_15: 2 SGPRs (Value: Raw32): s28, s29 - - // (op 1869) Deallocate Tensor_15_pointer - // Freeing Tensor_15_pointer: 2 SGPRs (Value: Raw32): s30, s31 - - // (op 177) Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869) END - // (op 177) end: generate({684}) -RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_ConditionalBottom_0_beta_177: - // (op 177) - // (op 177) Unlock Conditional - // Unlock None - // (op 1) ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177) END - // (op 1) Deallocate{}(1769) BEGIN - // (op 1769) Deallocate 33 - // Freeing : 1 VGPR (Value: Float) (op 24): v11 - - // Deleting tag 33 - // (op 1769) Deallocate 24 - // Freeing : 1 VGPR (Value: Float) (op 2): v10 - - // Deleting tag 24 - // (op 1769) Deallocate 35 - // Freeing DataFlowTag35: 16 ACCVGPRs (Value: Float) (op 44): a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15 - - // Deleting tag 35 - // (op 1) Deallocate{}(1769) END - // (op 1) end: generate({1239, 1291, 1364, 1403, 1442, 1481, 1520, 1559}) - // Kernel(1) END - // end: generate({1}) - // CodeGeneratorVisitor::generate() end -s_endpgm // End of RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a -.LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_end: - -.size RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a, .LRRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a_end-RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a -.rodata -.p2align 6 -.amdhsa_kernel RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a - // Resource limits - .amdhsa_next_free_vgpr 96 - .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr - .amdhsa_group_segment_fixed_size 65536 // lds bytes - .amdhsa_accum_offset 80 - // Initial kernel state - .amdhsa_user_sgpr_kernarg_segment_ptr 1 -.amdhsa_system_sgpr_workgroup_id_x 1 -.amdhsa_system_sgpr_workgroup_id_y 1 -.amdhsa_system_sgpr_workgroup_id_z 0 -.amdhsa_system_sgpr_workgroup_info 0 -.amdhsa_system_vgpr_workitem_id 1 -.end_amdhsa_kernel - -.amdgpu_metadata ---- -amdhsa.version: [1, 2] -amdhsa.kernels: - - .name: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a - .symbol: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a.kd - .kernarg_segment_size: 112 - .group_segment_fixed_size: 65536 - .private_segment_fixed_size: 0 - .kernarg_segment_align: 8 - .sgpr_count: 50 - .vgpr_count: 78 - .agpr_count: 16 - .max_flat_workgroup_size: 256 - .workgroup_size: [256, 1, 1] - .kernel_dimensions: 2 - .wavefront_size: 64 - .workitem_count: [{type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_0_size_0_8, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 56, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 256}}, {type: Multiply, lhs: {type: Convert, arg: {type: ArithmeticShiftR, lhs: {type: Subtract, lhs: {type: Add, lhs: {type: Kernel Argument, name: Tensor_2_size_1_11, variableType: {dataType: Int64, pointerType: Value}, dataDirection: read_only, expression: {type: CommandArgument, size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only}, offset: 80, size: 8}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 64}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 6}}, dataType: Int32}, rhs: {type: LiteralValue.UInt32, dataType: UInt32, value: 1}}, {is-null: true}] - .dynamic_sharedmemory_bytes: {type: LiteralValue.UInt32, dataType: UInt32, value: 0} - .args: - - .name: Tensor_0_extent_0 - .size: 8 - .offset: 0 - .expression: {type: CommandArgument, size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_0_pointer - .size: 8 - .offset: 8 - .expression: {type: CommandArgument, size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - .variableType: {dataType: Half, pointerType: PointerGlobal} - .address_space: global - .actual_access: read_write - .value_kind: global_buffer - - .name: Tensor_2_extent_2 - .size: 8 - .offset: 16 - .expression: {type: CommandArgument, size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_2_pointer - .size: 8 - .offset: 24 - .expression: {type: CommandArgument, size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - .variableType: {dataType: Half, pointerType: PointerGlobal} - .address_space: global - .actual_access: read_write - .value_kind: global_buffer - - .name: Tensor_4_extent_4 - .size: 8 - .offset: 32 - .expression: {type: CommandArgument, size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_4_pointer - .size: 8 - .offset: 40 - .expression: {type: CommandArgument, size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - .variableType: {dataType: Half, pointerType: PointerGlobal} - .address_space: global - .actual_access: read_write - .value_kind: global_buffer - - .name: user_Float_Value_6 - .size: 4 - .offset: 48 - .expression: {type: CommandArgument, size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - .variableType: {dataType: Float, pointerType: Value} - .value_kind: by_value - - .name: user_Float_Value_8 - .size: 4 - .offset: 52 - .expression: {type: CommandArgument, size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - .variableType: {dataType: Float, pointerType: Value} - .value_kind: by_value - - .name: Tensor_0_stride_0_9 - .size: 8 - .offset: 56 - .expression: {type: CommandArgument, size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_0_size_1_10 - .size: 8 - .offset: 64 - .expression: {type: CommandArgument, size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_2_stride_1_12 - .size: 8 - .offset: 72 - .expression: {type: CommandArgument, size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_4_stride_1_13 - .size: 8 - .offset: 80 - .expression: {type: CommandArgument, size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_15_stride_1_14 - .size: 8 - .offset: 88 - .expression: {type: CommandArgument, size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_15_extent_15 - .size: 8 - .offset: 96 - .expression: {type: CommandArgument, size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - .variableType: {dataType: Int64, pointerType: Value} - .value_kind: by_value - - .name: Tensor_15_pointer - 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NA}(552)\"];\n\"coord553\"[label=\"Buffer(553)\",shape=box];\n\"coord554\"[label=\"Offset(554)\",shape=box];\n\"coord555\"[label=\"Stride(555)\",shape=box];\n\"coord556\"[label=\"Offset(556)\",shape=box];\n\"coord557\"[label=\"Stride(557)\",shape=box];\n\"coord558\"[label=\"Offset(558)\",shape=box];\n\"coord559\"[label=\"Stride(559)\",shape=box];\n\"coord560\"[label=\"Offset(560)\",shape=box];\n\"coord561\"[label=\"Stride(561)\",shape=box];\n\"coord562\"[label=\"Offset(562)\",shape=box];\n\"coord563\"[label=\"Stride(563)\",shape=box];\n\"coord564\"[label=\"Offset(564)\",shape=box];\n\"coord565\"[label=\"Stride(565)\",shape=box];\n\"coord566\"[label=\"Offset(566)\",shape=box];\n\"coord567\"[label=\"Stride(567)\",shape=box];\n\"coord568\"[label=\"Offset(568)\",shape=box];\n\"coord569\"[label=\"Stride(569)\",shape=box];\n\"coord570\"[label=\"Offset(570)\",shape=box];\n\"coord571\"[label=\"Stride(571)\",shape=box];\n\"coord572\"[label=\"Offset(572)\",shape=box];\n\"coord573\"[label=\"Stride(573)\",shape=box];\n\"coord574\"[label=\"Offset(574)\",shape=box];\n\"coord575\"[label=\"Stride(575)\",shape=box];\n\"coord576\"[label=\"Offset(576)\",shape=box];\n\"coord577\"[label=\"Stride(577)\",shape=box];\n\"coord578\"[label=\"Offset(578)\",shape=box];\n\"coord579\"[label=\"Stride(579)\",shape=box];\n\"coord580\"[label=\"Offset(580)\",shape=box];\n\"coord581\"[label=\"Stride(581)\",shape=box];\n\"coord582\"[label=\"Offset(582)\",shape=box];\n\"coord583\"[label=\"Stride(583)\",shape=box];\n\"coord584\"[label=\"Offset(584)\",shape=box];\n\"coord585\"[label=\"Stride(585)\",shape=box];\n\"coord586\"[label=\"Offset(586)\",shape=box];\n\"coord587\"[label=\"Stride(587)\",shape=box];\n\"coord588\"[label=\"Offset(588)\",shape=box];\n\"coord589\"[label=\"Stride(589)\",shape=box];\n\"coord590\"[label=\"Offset(590)\",shape=box];\n\"coord591\"[label=\"Stride(591)\",shape=box];\n\"coord592\"[label=\"Offset(592)\",shape=box];\n\"coord593\"[label=\"Stride(593)\",shape=box];\n\"coord594\"[label=\"Offset(594)\",shape=box];\n\"coord595\"[label=\"Stride(595)\",shape=box];\n\"coord596\"[label=\"Offset(596)\",shape=box];\n\"coord597\"[label=\"Stride(597)\",shape=box];\n\"coord598\"[label=\"Offset(598)\",shape=box];\n\"coord599\"[label=\"Stride(599)\",shape=box];\n\"coord600\"[label=\"Offset(600)\",shape=box];\n\"coord601\"[label=\"Stride(601)\",shape=box];\n\"coord602\"[label=\"Offset(602)\",shape=box];\n\"coord603\"[label=\"Stride(603)\",shape=box];\n\"coord604\"[label=\"Offset(604)\",shape=box];\n\"coord605\"[label=\"Stride(605)\",shape=box];\n\"coord606\"[label=\"Offset(606)\",shape=box];\n\"coord607\"[label=\"Stride(607)\",shape=box];\n\"coord608\"[label=\"Offset(608)\",shape=box];\n\"coord609\"[label=\"Stride(609)\",shape=box];\n\"coord610\"[label=\"Offset(610)\",shape=box];\n\"coord611\"[label=\"Stride(611)\",shape=box];\n\"coord612\"[label=\"Offset(612)\",shape=box];\n\"coord613\"[label=\"Stride(613)\",shape=box];\n\"coord614\"[label=\"Offset(614)\",shape=box];\n\"coord615\"[label=\"Stride(615)\",shape=box];\n\"coord616\"[label=\"Offset(616)\",shape=box];\n\"coord617\"[label=\"Stride(617)\",shape=box];\n\"coord618\"[label=\"Offset(618)\",shape=box];\n\"coord619\"[label=\"Stride(619)\",shape=box];\n\"coord620\"[label=\"Offset(620)\",shape=box];\n\"coord621\"[label=\"Stride(621)\",shape=box];\n\"coord622\"[label=\"Offset(622)\",shape=box];\n\"coord623\"[label=\"Stride(623)\",shape=box];\n\"coord624\"[label=\"Offset(624)\",shape=box];\n\"coord625\"[label=\"Stride(625)\",shape=box];\n\"coord626\"[label=\"Offset(626)\",shape=box];\n\"coord627\"[label=\"Stride(627)\",shape=box];\n\"coord628\"[label=\"Offset(628)\",shape=box];\n\"coord629\"[label=\"Stride(629)\",shape=box];\n\"coord630\"[label=\"Offset(630)\",shape=box];\n\"coord631\"[label=\"Stride(631)\",shape=box];\n\"coord632\"[label=\"Alias(632)\",shape=box];\n\"coord633\"[label=\"Alias(633)\",shape=box];\n\"coord634\"[label=\"Alias(634)\",shape=box];\n\"coord635\"[label=\"Alias(635)\",shape=box];\n\"coord636\"[label=\"Alias(636)\",shape=box];\n\"coord637\"[label=\"Alias(637)\",shape=box];\n\"coord638\"[label=\"Alias(638)\",shape=box];\n\"coord639\"[label=\"Alias(639)\",shape=box];\n\"coord640\"[label=\"Alias(640)\",shape=box];\n\"coord641\"[label=\"Alias(641)\",shape=box];\n\"coord642\"[label=\"Alias(642)\",shape=box];\n\"coord643\"[label=\"Alias(643)\",shape=box];\n\"coord644\"[label=\"Alias(644)\",shape=box];\n\"coord645\"[label=\"Alias(645)\",shape=box];\n\"coord646\"[label=\"Alias(646)\",shape=box];\n\"coord647\"[label=\"Alias(647)\",shape=box];\n\"coord648\"[label=\"Alias(648)\",shape=box];\n\"coord649\"[label=\"Alias(649)\",shape=box];\n\"coord650\"[label=\"Alias(650)\",shape=box];\n\"coord651\"[label=\"Alias(651)\",shape=box];\n\"coord652\"[label=\"Alias(652)\",shape=box];\n\"coord653\"[label=\"Alias(653)\",shape=box];\n\"coord654\"[label=\"Alias(654)\",shape=box];\n\"coord655\"[label=\"Alias(655)\",shape=box];\n\"coord656\"[label=\"Alias(656)\",shape=box];\n\"coord657\"[label=\"Alias(657)\",shape=box];\n\"coord1\" -> \"coord10\"\n\"coord1\" -> \"coord12\"\n\"coord1\" -> \"coord66\"\n\"coord1\" -> \"coord474\"\n\"coord1\" -> \"coord475\"\n\"coord1\" -> \"coord478\"\n\"coord1\" -> \"coord479\"\n\"coord1\" -> \"coord480\"\n\"coord1\" -> \"coord481\"\n\"coord1\" -> \"coord482\"\n\"coord1\" -> \"coord483\"\n\"coord1\" -> \"coord484\"\n\"coord1\" -> \"coord485\"\n\"coord1\" -> \"coord486\"\n\"coord1\" -> \"coord487\"\n\"coord1\" -> \"coord488\"\n\"coord1\" -> \"coord489\"\n\"coord1\" -> \"coord490\"\n\"coord1\" -> \"coord491\"\n\"coord1\" -> \"coord492\"\n\"coord2\" -> \"coord18\"\n\"coord2\" -> \"coord20\"\n\"coord2\" -> \"coord126\"\n\"coord2\" -> \"coord493\"\n\"coord2\" -> \"coord494\"\n\"coord2\" -> \"coord497\"\n\"coord2\" -> \"coord498\"\n\"coord2\" -> \"coord499\"\n\"coord2\" -> \"coord500\"\n\"coord2\" -> \"coord501\"\n\"coord2\" -> \"coord502\"\n\"coord2\" -> \"coord503\"\n\"coord2\" -> \"coord504\"\n\"coord2\" -> \"coord505\"\n\"coord2\" -> \"coord506\"\n\"coord2\" -> \"coord507\"\n\"coord2\" -> \"coord508\"\n\"coord2\" -> \"coord509\"\n\"coord2\" -> \"coord510\"\n\"coord2\" -> \"coord511\"\n\"coord3\" -> \"coord28\"\n\"coord3\" -> \"coord30\"\n\"coord3\" -> \"coord207\"\n\"coord3\" -> \"coord512\"\n\"coord3\" -> \"coord513\"\n\"coord3\" -> \"coord516\"\n\"coord3\" -> \"coord517\"\n\"coord4\" -> \"coord34\"\n\"coord5\" -> \"coord25\"\n\"coord6\" -> \"coord14\"\n\"coord6\" -> \"coord36\"\n\"coord7\" -> \"coord22\"\n\"coord7\" -> \"coord36\"\n\"coord8\" -> \"coord52\"\n\"coord9\" -> \"coord53\"\n\"coord10\" -> \"coord8\"\n\"coord10\" -> \"coord9\"\n\"coord12\" -> \"coord11\"\n\"coord13\" -> \"coord15\"\n\"coord13\" -> \"coord107\"\n\"coord13\" -> \"coord530\"\n\"coord13\" -> \"coord531\"\n\"coord13\" -> \"coord532\"\n\"coord13\" -> \"coord533\"\n\"coord14\" -> \"coord13\"\n\"coord15\" -> \"coord11\"\n\"coord16\" -> \"coord112\"\n\"coord17\" -> \"coord113\"\n\"coord18\" -> \"coord16\"\n\"coord18\" -> \"coord17\"\n\"coord20\" -> \"coord19\"\n\"coord21\" -> \"coord23\"\n\"coord21\" -> \"coord167\"\n\"coord21\" -> \"coord546\"\n\"coord21\" -> \"coord547\"\n\"coord21\" -> \"coord548\"\n\"coord21\" -> \"coord549\"\n\"coord22\" -> \"coord21\"\n\"coord23\" -> \"coord19\"\n\"coord24\" -> \"coord32\"\n\"coord25\" -> \"coord24\"\n\"coord26\" -> \"coord172\"\n\"coord27\" -> \"coord173\"\n\"coord28\" -> \"coord26\"\n\"coord28\" -> \"coord27\"\n\"coord29\" -> \"coord32\"\n\"coord30\" -> \"coord29\"\n\"coord31\" -> \"coord40\"\n\"coord32\" -> \"coord31\"\n\"coord33\" -> \"coord38\"\n\"coord34\" -> \"coord33\"\n\"coord35\" -> \"coord38\"\n\"coord36\" -> \"coord35\"\n\"coord37\" -> \"coord40\"\n\"coord38\" -> \"coord37\"\n\"coord39\" -> \"coord42\"\n\"coord40\" -> \"coord39\"\n\"coord41\" -> \"coord47\"\n\"coord41\" -> \"coord244\"\n\"coord42\" -> \"coord41\"\n\"coord43\" -> \"coord46\"\n\"coord44\" -> \"coord46\"\n\"coord46\" -> \"coord45\"\n\"coord47\" -> \"coord45\"\n\"coord48\" -> \"coord302\"\n\"coord49\" -> \"coord314\"\n\"coord50\" -> \"coord64\"\n\"coord51\" -> \"coord65\"\n\"coord52\" -> \"coord48\"\n\"coord52\" -> \"coord50\"\n\"coord53\" -> \"coord49\"\n\"coord53\" -> \"coord51\"\n\"coord54\" -> \"coord63\"\n\"coord55\" -> \"coord63\"\n\"coord56\" -> \"coord61\"\n\"coord57\" -> \"coord62\"\n\"coord61\" -> \"coord59\"\n\"coord62\" -> \"coord60\"\n\"coord63\" -> \"coord58\"\n\"coord64\" -> \"coord56\"\n\"coord64\" -> \"coord54\"\n\"coord65\" -> \"coord55\"\n\"coord65\" -> \"coord57\"\n\"coord66\" -> \"coord6\"\n\"coord67\" -> \"coord81\"\n\"coord68\" -> \"coord81\"\n\"coord69\" -> \"coord79\"\n\"coord70\" -> \"coord80\"\n\"coord71\" -> \"coord79\"\n\"coord72\" -> \"coord80\"\n\"coord73\" -> \"coord78\"\n\"coord74\" -> \"coord76\"\n\"coord74\" -> \"coord518\"\n\"coord74\" -> \"coord519\"\n\"coord74\" -> \"coord522\"\n\"coord74\" -> \"coord523\"\n\"coord74\" -> \"coord526\"\n\"coord74\" -> \"coord527\"\n\"coord74\" -> \"coord560\"\n\"coord74\" -> \"coord561\"\n\"coord74\" -> \"coord564\"\n\"coord74\" -> \"coord565\"\n\"coord74\" -> \"coord584\"\n\"coord74\" -> \"coord585\"\n\"coord74\" -> \"coord588\"\n\"coord74\" -> \"coord589\"\n\"coord74\" -> \"coord608\"\n\"coord74\" -> \"coord609\"\n\"coord74\" -> \"coord612\"\n\"coord74\" -> \"coord613\"\n\"coord75\" -> \"coord77\"\n\"coord75\" -> \"coord520\"\n\"coord75\" -> \"coord521\"\n\"coord75\" -> \"coord524\"\n\"coord75\" -> \"coord525\"\n\"coord75\" -> \"coord528\"\n\"coord75\" -> \"coord529\"\n\"coord75\" -> \"coord562\"\n\"coord75\" -> \"coord563\"\n\"coord75\" -> \"coord566\"\n\"coord75\" -> \"coord567\"\n\"coord75\" -> \"coord586\"\n\"coord75\" -> \"coord587\"\n\"coord75\" -> \"coord590\"\n\"coord75\" -> \"coord591\"\n\"coord75\" -> \"coord610\"\n\"coord75\" -> \"coord611\"\n\"coord75\" -> \"coord614\"\n\"coord75\" -> \"coord615\"\n\"coord76\" -> \"coord71\"\n\"coord77\" -> \"coord72\"\n\"coord78\" -> \"coord69\"\n\"coord78\" -> \"coord70\"\n\"coord79\" -> \"coord67\"\n\"coord80\" -> \"coord68\"\n\"coord81\" -> \"coord13\"\n\"coord82\" -> \"coord91\"\n\"coord83\" -> \"coord92\"\n\"coord85\" -> \"coord86\"\n\"coord86\" -> \"coord11\"\n\"coord87\" -> \"coord106\"\n\"coord88\" -> \"coord251\"\n\"coord89\" -> \"coord104\"\n\"coord90\" -> \"coord103\"\n\"coord91\" -> \"coord87\"\n\"coord91\" -> \"coord89\"\n\"coord92\" -> \"coord88\"\n\"coord92\" -> \"coord90\"\n\"coord93\" -> \"coord98\"\n\"coord94\" -> \"coord98\"\n\"coord95\" -> \"coord99\"\n\"coord96\" -> \"coord99\"\n\"coord98\" -> \"coord95\"\n\"coord99\" -> \"coord84\"\n\"coord101\" -> \"coord104\"\n\"coord102\" -> \"coord105\"\n\"coord103\" -> \"coord101\"\n\"coord103\" -> \"coord102\"\n\"coord104\" -> \"coord96\"\n\"coord105\" -> \"coord97\"\n\"coord106\" -> \"coord93\"\n\"coord107\" -> \"coord82\"\n\"coord107\" -> \"coord83\"\n\"coord108\" -> \"coord315\"\n\"coord109\" -> \"coord304\"\n\"coord110\" -> \"coord124\"\n\"coord111\" -> \"coord125\"\n\"coord112\" -> \"coord108\"\n\"coord112\" -> \"coord110\"\n\"coord113\" -> \"coord109\"\n\"coord113\" -> \"coord111\"\n\"coord114\" -> \"coord123\"\n\"coord115\" -> \"coord123\"\n\"coord116\" -> \"coord121\"\n\"coord117\" -> \"coord122\"\n\"coord121\" -> \"coord120\"\n\"coord122\" -> \"coord119\"\n\"coord123\" -> \"coord118\"\n\"coord124\" -> \"coord114\"\n\"coord124\" -> \"coord116\"\n\"coord125\" -> \"coord117\"\n\"coord125\" -> \"coord115\"\n\"coord126\" -> \"coord7\"\n\"coord127\" -> \"coord141\"\n\"coord128\" -> \"coord141\"\n\"coord129\" -> \"coord139\"\n\"coord130\" -> \"coord140\"\n\"coord131\" -> \"coord139\"\n\"coord132\" -> \"coord140\"\n\"coord133\" -> \"coord138\"\n\"coord134\" -> \"coord137\"\n\"coord134\" -> \"coord534\"\n\"coord134\" -> \"coord535\"\n\"coord134\" -> \"coord538\"\n\"coord134\" -> \"coord539\"\n\"coord134\" -> \"coord542\"\n\"coord134\" -> \"coord543\"\n\"coord134\" -> \"coord572\"\n\"coord134\" -> \"coord573\"\n\"coord134\" -> \"coord576\"\n\"coord134\" -> \"coord577\"\n\"coord134\" -> \"coord596\"\n\"coord134\" -> \"coord597\"\n\"coord134\" -> \"coord600\"\n\"coord134\" -> \"coord601\"\n\"coord134\" -> \"coord620\"\n\"coord134\" -> \"coord621\"\n\"coord134\" -> \"coord624\"\n\"coord134\" -> \"coord625\"\n\"coord135\" -> \"coord136\"\n\"coord135\" -> \"coord536\"\n\"coord135\" -> \"coord537\"\n\"coord135\" -> \"coord540\"\n\"coord135\" -> \"coord541\"\n\"coord135\" -> \"coord544\"\n\"coord135\" -> \"coord545\"\n\"coord135\" -> \"coord574\"\n\"coord135\" -> \"coord575\"\n\"coord135\" -> \"coord578\"\n\"coord135\" -> \"coord579\"\n\"coord135\" -> \"coord598\"\n\"coord135\" -> \"coord599\"\n\"coord135\" -> \"coord602\"\n\"coord135\" -> \"coord603\"\n\"coord135\" -> \"coord622\"\n\"coord135\" -> \"coord623\"\n\"coord135\" -> \"coord626\"\n\"coord135\" -> \"coord627\"\n\"coord136\" -> \"coord131\"\n\"coord137\" -> \"coord132\"\n\"coord138\" -> \"coord130\"\n\"coord138\" -> \"coord129\"\n\"coord139\" -> \"coord127\"\n\"coord140\" -> \"coord128\"\n\"coord141\" -> \"coord21\"\n\"coord142\" -> \"coord151\"\n\"coord143\" -> \"coord152\"\n\"coord145\" -> \"coord146\"\n\"coord146\" -> \"coord19\"\n\"coord147\" -> \"coord252\"\n\"coord148\" -> \"coord166\"\n\"coord149\" -> \"coord163\"\n\"coord150\" -> \"coord164\"\n\"coord151\" -> \"coord147\"\n\"coord151\" -> \"coord149\"\n\"coord152\" -> \"coord148\"\n\"coord152\" -> \"coord150\"\n\"coord153\" -> \"coord158\"\n\"coord154\" -> \"coord158\"\n\"coord155\" -> \"coord159\"\n\"coord156\" -> \"coord159\"\n\"coord158\" -> \"coord155\"\n\"coord159\" -> \"coord144\"\n\"coord161\" -> \"coord164\"\n\"coord162\" -> \"coord165\"\n\"coord163\" -> \"coord161\"\n\"coord163\" -> \"coord162\"\n\"coord164\" -> \"coord156\"\n\"coord165\" -> \"coord157\"\n\"coord166\" -> \"coord154\"\n\"coord167\" -> \"coord143\"\n\"coord167\" -> \"coord142\"\n\"coord168\" -> \"coord306\"\n\"coord169\" -> \"coord308\"\n\"coord170\" -> \"coord181\"\n\"coord171\" -> \"coord182\"\n\"coord172\" -> \"coord168\"\n\"coord172\" -> \"coord170\"\n\"coord173\" -> \"coord169\"\n\"coord173\" -> \"coord171\"\n\"coord175\" -> \"coord176\"\n\"coord176\" -> \"coord29\"\n\"coord177\" -> \"coord205\"\n\"coord178\" -> \"coord206\"\n\"coord179\" -> \"coord199\"\n\"coord180\" -> \"coord200\"\n\"coord181\" -> \"coord177\"\n\"coord181\" -> \"coord179\"\n\"coord182\" -> \"coord178\"\n\"coord182\" -> \"coord180\"\n\"coord183\" -> \"coord188\"\n\"coord184\" -> \"coord188\"\n\"coord185\" -> \"coord189\"\n\"coord186\" -> \"coord189\"\n\"coord188\" -> \"coord185\"\n\"coord189\" -> \"coord174\"\n\"coord192\" -> \"coord203\"\n\"coord193\" -> \"coord203\"\n\"coord194\" -> \"coord204\"\n\"coord195\" -> \"coord204\"\n\"coord196\" -> \"coord202\"\n\"coord197\" -> \"coord201\"\n\"coord198\" -> \"coord201\"\n\"coord199\" -> \"coord197\"\n\"coord199\" -> \"coord193\"\n\"coord200\" -> \"coord198\"\n\"coord200\" -> \"coord195\"\n\"coord201\" -> \"coord196\"\n\"coord202\" -> \"coord192\"\n\"coord202\" -> \"coord194\"\n\"coord203\" -> \"coord187\"\n\"coord204\" -> \"coord186\"\n\"coord205\" -> \"coord183\"\n\"coord206\" -> \"coord184\"\n\"coord207\" -> \"coord29\"\n\"coord208\" -> \"coord212\"\n\"coord209\" -> \"coord213\"\n\"coord210\" -> \"coord212\"\n\"coord211\" -> \"coord213\"\n\"coord212\" -> \"coord43\"\n\"coord213\" -> \"coord44\"\n\"coord214\" -> \"coord243\"\n\"coord216\" -> \"coord227\"\n\"coord217\" -> \"coord228\"\n\"coord218\" -> \"coord227\"\n\"coord219\" -> \"coord228\"\n\"coord220\" -> \"coord237\"\n\"coord220\" -> \"coord550\"\n\"coord220\" -> \"coord551\"\n\"coord220\" -> \"coord556\"\n\"coord220\" -> \"coord557\"\n\"coord221\" -> \"coord241\"\n\"coord221\" -> \"coord554\"\n\"coord221\" -> \"coord555\"\n\"coord221\" -> \"coord558\"\n\"coord221\" -> \"coord559\"\n\"coord222\" -> \"coord237\"\n\"coord223\" -> \"coord242\"\n\"coord224\" -> \"coord238\"\n\"coord225\" -> \"coord241\"\n\"coord226\" -> \"coord242\"\n\"coord227\" -> \"coord210\"\n\"coord228\" -> \"coord211\"\n\"coord229\" -> \"coord239\"\n\"coord230\" -> \"coord240\"\n\"coord231\" -> \"coord232\"\n\"coord232\" -> \"coord229\"\n\"coord232\" -> \"coord230\"\n\"coord233\" -> \"coord236\"\n\"coord234\" -> \"coord235\"\n\"coord235\" -> \"coord220\"\n\"coord235\" -> \"coord221\"\n\"coord236\" -> \"coord222\"\n\"coord236\" -> \"coord223\"\n\"coord237\" -> \"coord224\"\n\"coord238\" -> \"coord225\"\n\"coord238\" -> \"coord226\"\n\"coord239\" -> \"coord216\"\n\"coord240\" -> \"coord217\"\n\"coord241\" -> \"coord218\"\n\"coord242\" -> \"coord219\"\n\"coord243\" -> \"coord231\"\n\"coord243\" -> \"coord233\"\n\"coord244\" -> \"coord45\"\n\"coord245\" -> \"coord247\"\n\"coord247\" -> \"coord246\"\n\"coord251\" -> \"coord250\"\n\"coord252\" -> \"coord250\"\n\"coord253\" -> \"coord254\"\n\"coord254\" -> \"coord11\"\n\"coord255\" -> \"coord256\"\n\"coord256\" -> \"coord19\"\n\"coord257\" -> \"coord258\"\n\"coord258\" -> \"coord11\"\n\"coord259\" -> \"coord260\"\n\"coord260\" -> \"coord19\"\n\"coord261\" -> \"coord262\"\n\"coord262\" -> \"coord11\"\n\"coord263\" -> \"coord264\"\n\"coord264\" -> \"coord19\"\n\"coord265\" -> \"coord266\"\n\"coord266\" -> \"coord11\"\n\"coord267\" -> \"coord268\"\n\"coord268\" -> \"coord19\"\n\"coord269\" -> \"coord270\"\n\"coord270\" -> \"coord11\"\n\"coord271\" -> \"coord272\"\n\"coord272\" -> \"coord19\"\n\"coord273\" -> \"coord274\"\n\"coord274\" -> \"coord11\"\n\"coord275\" -> \"coord276\"\n\"coord276\" -> \"coord19\"\n\"coord277\" -> \"coord278\"\n\"coord278\" -> \"coord11\"\n\"coord279\" -> \"coord280\"\n\"coord280\" -> \"coord19\"\n\"coord291\" -> \"coord292\"\n\"coord292\" -> \"coord29\"\n\"coord293\" -> \"coord294\"\n\"coord294\" -> \"coord31\"\n\"coord295\" -> \"coord296\"\n\"coord296\" -> \"coord37\"\n\"coord297\" -> \"coord298\"\n\"coord298\" -> \"coord39\"\n\"coord299\" -> \"coord300\"\n\"coord300\" -> \"coord41\"\n\"coord302\" -> \"coord301\"\n\"coord304\" -> \"coord303\"\n\"coord306\" -> \"coord305\"\n\"coord308\" -> \"coord307\"\n\"coord309\" -> \"coord310\"\n\"coord310\" -> \"coord208\"\n\"coord311\" -> \"coord312\"\n\"coord312\" -> \"coord209\"\n\"coord314\" -> \"coord246\"\n\"coord314\" -> \"coord313\"\n\"coord315\" -> \"coord246\"\n\"coord315\" -> \"coord313\"\n\"coord316\" -> \"coord317\"\n\"coord317\" -> \"coord246\"\n\"coord318\" -> \"coord319\"\n\"coord319\" -> \"coord6\"\n\"coord320\" -> \"coord321\"\n\"coord321\" -> \"coord7\"\n\"coord322\" -> \"coord323\"\n\"coord323\" -> \"coord11\"\n\"coord324\" -> \"coord325\"\n\"coord325\" -> \"coord19\"\n\"coord326\" -> \"coord327\"\n\"coord327\" -> \"coord11\"\n\"coord328\" -> \"coord329\"\n\"coord329\" -> \"coord19\"\n\"coord330\" -> \"coord331\"\n\"coord331\" -> \"coord11\"\n\"coord332\" -> \"coord333\"\n\"coord333\" -> \"coord19\"\n\"coord334\" -> \"coord335\"\n\"coord335\" -> \"coord11\"\n\"coord336\" -> \"coord337\"\n\"coord337\" -> \"coord19\"\n\"coord338\" -> \"coord339\"\n\"coord339\" -> \"coord11\"\n\"coord340\" -> \"coord341\"\n\"coord341\" -> \"coord19\"\n\"coord342\" -> \"coord343\"\n\"coord343\" -> \"coord11\"\n\"coord344\" -> \"coord345\"\n\"coord345\" -> \"coord19\"\n\"coord346\" -> \"coord347\"\n\"coord347\" -> \"coord11\"\n\"coord348\" -> \"coord349\"\n\"coord349\" -> \"coord19\"\n\"coord350\" -> \"coord351\"\n\"coord351\" -> \"coord11\"\n\"coord352\" -> \"coord353\"\n\"coord353\" -> \"coord19\"\n\"coord354\" -> \"coord355\"\n\"coord355\" -> \"coord6\"\n\"coord356\" -> \"coord357\"\n\"coord356\" -> \"coord568\"\n\"coord356\" -> \"coord569\"\n\"coord356\" -> \"coord570\"\n\"coord356\" -> \"coord571\"\n\"coord357\" -> \"coord13\"\n\"coord358\" -> \"coord359\"\n\"coord359\" -> \"coord7\"\n\"coord360\" -> \"coord361\"\n\"coord360\" -> \"coord580\"\n\"coord360\" -> \"coord581\"\n\"coord360\" -> \"coord582\"\n\"coord360\" -> \"coord583\"\n\"coord361\" -> \"coord21\"\n\"coord362\" -> \"coord363\"\n\"coord362\" -> \"coord632\"\n\"coord363\" -> \"coord11\"\n\"coord364\" -> \"coord365\"\n\"coord364\" -> \"coord633\"\n\"coord365\" -> \"coord19\"\n\"coord366\" -> \"coord367\"\n\"coord366\" -> \"coord634\"\n\"coord367\" -> \"coord11\"\n\"coord368\" -> \"coord369\"\n\"coord369\" -> \"coord19\"\n\"coord370\" -> \"coord371\"\n\"coord370\" -> \"coord635\"\n\"coord371\" -> \"coord11\"\n\"coord372\" -> \"coord373\"\n\"coord373\" -> \"coord19\"\n\"coord374\" -> \"coord375\"\n\"coord375\" -> \"coord11\"\n\"coord376\" -> \"coord377\"\n\"coord377\" -> \"coord19\"\n\"coord378\" -> \"coord379\"\n\"coord378\" -> \"coord636\"\n\"coord379\" -> \"coord11\"\n\"coord380\" -> \"coord381\"\n\"coord381\" -> \"coord19\"\n\"coord382\" -> \"coord383\"\n\"coord383\" -> \"coord11\"\n\"coord384\" -> \"coord385\"\n\"coord385\" -> \"coord19\"\n\"coord386\" -> \"coord387\"\n\"coord386\" -> \"coord637\"\n\"coord387\" -> \"coord11\"\n\"coord388\" -> \"coord389\"\n\"coord389\" -> \"coord19\"\n\"coord390\" -> \"coord391\"\n\"coord391\" -> \"coord11\"\n\"coord392\" -> \"coord393\"\n\"coord393\" -> \"coord19\"\n\"coord394\" -> \"coord395\"\n\"coord395\" -> \"coord6\"\n\"coord396\" -> \"coord397\"\n\"coord396\" -> \"coord592\"\n\"coord396\" -> \"coord593\"\n\"coord396\" -> \"coord594\"\n\"coord396\" -> \"coord595\"\n\"coord397\" -> \"coord13\"\n\"coord398\" -> \"coord399\"\n\"coord399\" -> \"coord7\"\n\"coord400\" -> \"coord401\"\n\"coord400\" -> \"coord604\"\n\"coord400\" -> \"coord605\"\n\"coord400\" -> \"coord606\"\n\"coord400\" -> \"coord607\"\n\"coord401\" -> \"coord21\"\n\"coord402\" -> \"coord403\"\n\"coord402\" -> \"coord638\"\n\"coord403\" -> \"coord11\"\n\"coord404\" -> \"coord405\"\n\"coord404\" -> \"coord639\"\n\"coord405\" -> \"coord19\"\n\"coord406\" -> \"coord407\"\n\"coord406\" -> \"coord640\"\n\"coord407\" -> \"coord11\"\n\"coord408\" -> \"coord409\"\n\"coord408\" -> \"coord641\"\n\"coord409\" -> \"coord19\"\n\"coord410\" -> \"coord411\"\n\"coord410\" -> \"coord642\"\n\"coord411\" -> \"coord11\"\n\"coord412\" -> \"coord413\"\n\"coord412\" -> \"coord643\"\n\"coord413\" -> \"coord19\"\n\"coord414\" -> \"coord415\"\n\"coord414\" -> \"coord644\"\n\"coord415\" -> \"coord11\"\n\"coord416\" -> \"coord417\"\n\"coord416\" -> \"coord645\"\n\"coord417\" -> \"coord19\"\n\"coord418\" -> \"coord419\"\n\"coord418\" -> \"coord646\"\n\"coord419\" -> \"coord11\"\n\"coord420\" -> \"coord421\"\n\"coord420\" -> \"coord647\"\n\"coord421\" -> \"coord19\"\n\"coord422\" -> \"coord423\"\n\"coord422\" -> \"coord648\"\n\"coord423\" -> \"coord11\"\n\"coord424\" -> \"coord425\"\n\"coord424\" -> \"coord649\"\n\"coord425\" -> \"coord19\"\n\"coord426\" -> \"coord427\"\n\"coord426\" -> \"coord650\"\n\"coord427\" -> \"coord11\"\n\"coord428\" -> \"coord429\"\n\"coord428\" -> \"coord651\"\n\"coord429\" -> \"coord19\"\n\"coord430\" -> \"coord431\"\n\"coord431\" -> \"coord11\"\n\"coord432\" -> \"coord433\"\n\"coord432\" -> \"coord652\"\n\"coord433\" -> \"coord19\"\n\"coord434\" -> \"coord435\"\n\"coord435\" -> \"coord6\"\n\"coord436\" -> \"coord437\"\n\"coord436\" -> \"coord616\"\n\"coord436\" -> \"coord617\"\n\"coord436\" -> \"coord618\"\n\"coord436\" -> \"coord619\"\n\"coord437\" -> \"coord13\"\n\"coord438\" -> \"coord439\"\n\"coord439\" -> \"coord7\"\n\"coord440\" -> \"coord441\"\n\"coord440\" -> \"coord628\"\n\"coord440\" -> \"coord629\"\n\"coord440\" -> \"coord630\"\n\"coord440\" -> \"coord631\"\n\"coord441\" -> \"coord21\"\n\"coord442\" -> \"coord443\"\n\"coord442\" -> \"coord653\"\n\"coord443\" -> \"coord11\"\n\"coord444\" -> \"coord445\"\n\"coord444\" -> \"coord654\"\n\"coord445\" -> \"coord19\"\n\"coord446\" -> \"coord447\"\n\"coord446\" -> \"coord655\"\n\"coord447\" -> \"coord11\"\n\"coord448\" -> \"coord449\"\n\"coord449\" -> \"coord19\"\n\"coord450\" -> \"coord451\"\n\"coord450\" -> \"coord656\"\n\"coord451\" -> \"coord11\"\n\"coord452\" -> \"coord453\"\n\"coord453\" -> \"coord19\"\n\"coord454\" -> \"coord455\"\n\"coord454\" -> \"coord657\"\n\"coord455\" -> \"coord11\"\n\"coord456\" -> \"coord457\"\n\"coord457\" -> \"coord19\"\n\"coord458\" -> \"coord459\"\n\"coord459\" -> \"coord11\"\n\"coord460\" -> \"coord461\"\n\"coord461\" -> \"coord19\"\n\"coord462\" -> \"coord463\"\n\"coord463\" -> \"coord11\"\n\"coord464\" -> \"coord465\"\n\"coord465\" -> \"coord19\"\n\"coord466\" -> \"coord467\"\n\"coord467\" -> \"coord11\"\n\"coord468\" -> \"coord469\"\n\"coord469\" -> \"coord19\"\n\"coord470\" -> \"coord471\"\n\"coord471\" -> \"coord11\"\n\"coord472\" -> \"coord473\"\n\"coord473\" -> \"coord19\"\n\"coord474\" -> \"coord49\"\n\"coord475\" -> \"coord49\"\n\"coord476\" -> \"coord477\"\n\"coord477\" -> \"coord1\"\n\"coord478\" -> \"coord59\"\n\"coord479\" -> \"coord59\"\n\"coord480\" -> \"coord60\"\n\"coord481\" -> \"coord60\"\n\"coord482\" -> \"coord49\"\n\"coord483\" -> \"coord59\"\n\"coord484\" -> \"coord59\"\n\"coord485\" -> \"coord60\"\n\"coord486\" -> \"coord60\"\n\"coord487\" -> \"coord49\"\n\"coord488\" -> \"coord49\"\n\"coord489\" -> \"coord59\"\n\"coord490\" -> \"coord59\"\n\"coord491\" -> \"coord60\"\n\"coord492\" -> \"coord60\"\n\"coord493\" -> \"coord108\"\n\"coord494\" -> \"coord108\"\n\"coord495\" -> \"coord496\"\n\"coord496\" -> \"coord2\"\n\"coord497\" -> \"coord119\"\n\"coord498\" -> \"coord119\"\n\"coord499\" -> \"coord120\"\n\"coord500\" -> \"coord120\"\n\"coord501\" -> \"coord108\"\n\"coord502\" -> \"coord119\"\n\"coord503\" -> \"coord119\"\n\"coord504\" -> \"coord120\"\n\"coord505\" -> \"coord120\"\n\"coord506\" -> \"coord108\"\n\"coord507\" -> \"coord108\"\n\"coord508\" -> \"coord119\"\n\"coord509\" -> \"coord119\"\n\"coord510\" -> \"coord120\"\n\"coord511\" -> \"coord120\"\n\"coord512\" -> \"coord192\"\n\"coord513\" -> \"coord192\"\n\"coord514\" -> \"coord515\"\n\"coord515\" -> \"coord3\"\n\"coord516\" -> \"coord193\"\n\"coord517\" -> \"coord193\"\n\"coord518\" -> \"coord13\"\n\"coord519\" -> \"coord13\"\n\"coord520\" -> \"coord13\"\n\"coord521\" -> \"coord13\"\n\"coord522\" -> \"coord13\"\n\"coord523\" -> \"coord13\"\n\"coord524\" -> \"coord13\"\n\"coord525\" -> \"coord13\"\n\"coord526\" -> \"coord13\"\n\"coord527\" -> \"coord13\"\n\"coord528\" -> \"coord13\"\n\"coord529\" -> \"coord13\"\n\"coord530\" -> \"coord88\"\n\"coord531\" -> \"coord88\"\n\"coord532\" -> \"coord97\"\n\"coord533\" -> \"coord97\"\n\"coord534\" -> \"coord21\"\n\"coord535\" -> \"coord21\"\n\"coord536\" -> \"coord21\"\n\"coord537\" -> \"coord21\"\n\"coord538\" -> \"coord21\"\n\"coord539\" -> \"coord21\"\n\"coord540\" -> \"coord21\"\n\"coord541\" -> \"coord21\"\n\"coord542\" -> \"coord21\"\n\"coord543\" -> \"coord21\"\n\"coord544\" -> \"coord21\"\n\"coord545\" -> \"coord21\"\n\"coord546\" -> \"coord147\"\n\"coord547\" -> \"coord147\"\n\"coord548\" -> \"coord157\"\n\"coord549\" -> \"coord157\"\n\"coord550\" -> \"coord45\"\n\"coord551\" -> \"coord45\"\n\"coord552\" -> \"coord553\"\n\"coord553\" -> \"coord45\"\n\"coord554\" -> \"coord45\"\n\"coord555\" -> \"coord45\"\n\"coord556\" -> \"coord45\"\n\"coord557\" -> \"coord45\"\n\"coord558\" -> \"coord45\"\n\"coord559\" -> \"coord45\"\n\"coord560\" -> \"coord356\"\n\"coord561\" -> \"coord356\"\n\"coord562\" -> \"coord356\"\n\"coord563\" -> \"coord356\"\n\"coord564\" -> \"coord356\"\n\"coord565\" -> \"coord356\"\n\"coord566\" -> \"coord356\"\n\"coord567\" -> \"coord356\"\n\"coord568\" -> \"coord88\"\n\"coord569\" -> \"coord88\"\n\"coord570\" -> \"coord97\"\n\"coord571\" -> \"coord97\"\n\"coord572\" -> \"coord360\"\n\"coord573\" -> \"coord360\"\n\"coord574\" -> \"coord360\"\n\"coord575\" -> \"coord360\"\n\"coord576\" -> \"coord360\"\n\"coord577\" -> \"coord360\"\n\"coord578\" -> \"coord360\"\n\"coord579\" -> \"coord360\"\n\"coord580\" -> \"coord147\"\n\"coord581\" -> \"coord147\"\n\"coord582\" -> \"coord157\"\n\"coord583\" -> \"coord157\"\n\"coord584\" -> \"coord396\"\n\"coord585\" -> \"coord396\"\n\"coord586\" -> \"coord396\"\n\"coord587\" -> \"coord396\"\n\"coord588\" -> \"coord396\"\n\"coord589\" -> \"coord396\"\n\"coord590\" -> \"coord396\"\n\"coord591\" -> \"coord396\"\n\"coord592\" -> \"coord88\"\n\"coord593\" -> \"coord88\"\n\"coord594\" -> \"coord97\"\n\"coord595\" -> \"coord97\"\n\"coord596\" -> \"coord400\"\n\"coord597\" -> \"coord400\"\n\"coord598\" -> \"coord400\"\n\"coord599\" -> \"coord400\"\n\"coord600\" -> \"coord400\"\n\"coord601\" -> \"coord400\"\n\"coord602\" -> \"coord400\"\n\"coord603\" -> \"coord400\"\n\"coord604\" -> \"coord147\"\n\"coord605\" -> \"coord147\"\n\"coord606\" -> \"coord157\"\n\"coord607\" -> \"coord157\"\n\"coord608\" -> \"coord436\"\n\"coord609\" -> \"coord436\"\n\"coord610\" -> \"coord436\"\n\"coord611\" -> \"coord436\"\n\"coord612\" -> \"coord436\"\n\"coord613\" -> \"coord436\"\n\"coord614\" -> \"coord436\"\n\"coord615\" -> \"coord436\"\n\"coord616\" -> \"coord88\"\n\"coord617\" -> \"coord88\"\n\"coord618\" -> \"coord97\"\n\"coord619\" -> \"coord97\"\n\"coord620\" -> \"coord440\"\n\"coord621\" -> \"coord440\"\n\"coord622\" -> \"coord440\"\n\"coord623\" -> \"coord440\"\n\"coord624\" -> \"coord440\"\n\"coord625\" -> \"coord440\"\n\"coord626\" -> \"coord440\"\n\"coord627\" -> \"coord440\"\n\"coord628\" -> \"coord147\"\n\"coord629\" -> \"coord147\"\n\"coord630\" -> \"coord157\"\n\"coord631\" -> \"coord157\"\n\"coord632\" -> \"coord11\"\n\"coord633\" -> \"coord19\"\n\"coord634\" -> \"coord253\"\n\"coord635\" -> \"coord257\"\n\"coord636\" -> \"coord261\"\n\"coord637\" -> \"coord265\"\n\"coord638\" -> \"coord11\"\n\"coord639\" -> \"coord19\"\n\"coord640\" -> \"coord253\"\n\"coord641\" -> \"coord255\"\n\"coord642\" -> \"coord257\"\n\"coord643\" -> \"coord259\"\n\"coord644\" -> \"coord269\"\n\"coord645\" -> \"coord263\"\n\"coord646\" -> \"coord273\"\n\"coord647\" -> \"coord267\"\n\"coord648\" -> \"coord277\"\n\"coord649\" -> \"coord271\"\n\"coord650\" -> \"coord261\"\n\"coord651\" -> \"coord275\"\n\"coord652\" -> \"coord279\"\n\"coord653\" -> \"coord11\"\n\"coord654\" -> \"coord19\"\n\"coord655\" -> \"coord253\"\n\"coord656\" -> \"coord257\"\n\"coord657\" -> \"coord265\"\n{\nrank=same\n\"coord8\"->\"coord9\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord16\"->\"coord17\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord26\"->\"coord27\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord24\"->\"coord29\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord6\"->\"coord7\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord33\"->\"coord35\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord31\"->\"coord37\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord43\"->\"coord44\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord48\"->\"coord50\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord49\"->\"coord51\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord54\"->\"coord55\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord56\"->\"coord54\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord55\"->\"coord57\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord69\"->\"coord70\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord71\"->\"coord69\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord70\"->\"coord72\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord67\"->\"coord68\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord87\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord88\"->\"coord90\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord93\"->\"coord94\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord95\"->\"coord96\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord102\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord101\"->\"coord89\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord82\"->\"coord83\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord108\"->\"coord110\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord109\"->\"coord111\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord115\"->\"coord114\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord114\"->\"coord116\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord117\"->\"coord115\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord130\"->\"coord129\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord129\"->\"coord131\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord132\"->\"coord130\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord128\"->\"coord127\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord147\"->\"coord149\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord148\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord153\"->\"coord154\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord155\"->\"coord156\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord162\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord161\"->\"coord150\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord143\"->\"coord142\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord168\"->\"coord170\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord169\"->\"coord171\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord177\"->\"coord179\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord178\"->\"coord180\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord183\"->\"coord184\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord185\"->\"coord186\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord198\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord197\"->\"coord198\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord194\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord192\"->\"coord193\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord194\"->\"coord195\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord208\"->\"coord210\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord209\"->\"coord211\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord216\"->\"coord218\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord217\"->\"coord219\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord229\"->\"coord230\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord222\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord220\"->\"coord222\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord226\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord225\"->\"coord221\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord226\"->\"coord223\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord231\"->\"coord233\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\n{\nrank=same\n\"coord246\"->\"coord313\"[style=invis]\nrankdir=LR\n}\nsubgraph clusterCF {label = \"Control Graph\";\n\"cntrl1\"[label=\"Kernel(1)\"];\n\"cntrl2\"[label=\"LoadVGPR Value: Float(2)\"];\n\"cntrl24\"[label=\"LoadVGPR Value: Float(24)\"];\n\"cntrl29\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(29)\"];\n\"cntrl35\"[label=\"Assign VGPR Convert(DataFlowTag(39)NA)H(35)\"];\n\"cntrl37\"[label=\"StoreTiled Value: Halfx2(37)\"];\n\"cntrl39\"[label=\"ForLoopOp KLoop: LessThan(DataFlowTag(245)U32, BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32)BL(39)\"];\n\"cntrl40\"[label=\"Assign SGPR 0:U32(40)\"];\n\"cntrl41\"[label=\"Assign SGPR Add(DataFlowTag(245)U32, 4:U32)U32(41)\"];\n\"cntrl42\"[label=\"Initialize(42)\",shape=box];\n\"cntrl44\"[label=\"Assign ACCVGPR 0.00000:S(44)\"];\n\"cntrl47\"[label=\"SetCoordinate(47)\"];\n\"cntrl49\"[label=\"LoadLDSTile{Value: Halfx2}(49)\"];\n\"cntrl50\"[label=\"Body(50)\",shape=box];\n\"cntrl52\"[label=\"SetCoordinate(52)\"];\n\"cntrl54\"[label=\"LoadLDSTile{Value: Halfx2}(54)\"];\n\"cntrl55\"[label=\"Body(55)\",shape=box];\n\"cntrl57\"[label=\"Multiply(57)\"];\n\"cntrl58\"[label=\"SetCoordinate(58)\"];\n\"cntrl60\"[label=\"LoadLDSTile{Value: Halfx2}(60)\"];\n\"cntrl61\"[label=\"Body(61)\",shape=box];\n\"cntrl62\"[label=\"SetCoordinate(62)\"];\n\"cntrl64\"[label=\"LoadLDSTile{Value: Halfx2}(64)\"];\n\"cntrl65\"[label=\"Body(65)\",shape=box];\n\"cntrl66\"[label=\"Multiply(66)\"];\n\"cntrl67\"[label=\"SetCoordinate(67)\"];\n\"cntrl69\"[label=\"LoadLDSTile{Value: Halfx2}(69)\"];\n\"cntrl70\"[label=\"Body(70)\",shape=box];\n\"cntrl71\"[label=\"SetCoordinate(71)\"];\n\"cntrl73\"[label=\"LoadLDSTile{Value: Halfx2}(73)\"];\n\"cntrl74\"[label=\"Body(74)\",shape=box];\n\"cntrl75\"[label=\"Multiply(75)\"];\n\"cntrl76\"[label=\"SetCoordinate(76)\"];\n\"cntrl78\"[label=\"LoadLDSTile{Value: Halfx2}(78)\"];\n\"cntrl79\"[label=\"Body(79)\",shape=box];\n\"cntrl80\"[label=\"SetCoordinate(80)\"];\n\"cntrl82\"[label=\"LoadLDSTile{Value: Halfx2}(82)\"];\n\"cntrl83\"[label=\"Body(83)\",shape=box];\n\"cntrl84\"[label=\"Multiply(84)\"];\n\"cntrl85\"[label=\"SetCoordinate(85)\"];\n\"cntrl87\"[label=\"LoadLDSTile{Value: Halfx2}(87)\"];\n\"cntrl88\"[label=\"Body(88)\",shape=box];\n\"cntrl89\"[label=\"SetCoordinate(89)\"];\n\"cntrl91\"[label=\"LoadLDSTile{Value: Halfx2}(91)\"];\n\"cntrl92\"[label=\"Body(92)\",shape=box];\n\"cntrl93\"[label=\"Multiply(93)\"];\n\"cntrl94\"[label=\"SetCoordinate(94)\"];\n\"cntrl96\"[label=\"LoadLDSTile{Value: Halfx2}(96)\"];\n\"cntrl97\"[label=\"Body(97)\",shape=box];\n\"cntrl98\"[label=\"SetCoordinate(98)\"];\n\"cntrl100\"[label=\"LoadLDSTile{Value: Halfx2}(100)\"];\n\"cntrl101\"[label=\"Body(101)\",shape=box];\n\"cntrl102\"[label=\"Multiply(102)\"];\n\"cntrl103\"[label=\"SetCoordinate(103)\"];\n\"cntrl105\"[label=\"LoadLDSTile{Value: Halfx2}(105)\"];\n\"cntrl106\"[label=\"Body(106)\",shape=box];\n\"cntrl107\"[label=\"SetCoordinate(107)\"];\n\"cntrl109\"[label=\"LoadLDSTile{Value: Halfx2}(109)\"];\n\"cntrl110\"[label=\"Body(110)\",shape=box];\n\"cntrl111\"[label=\"Multiply(111)\"];\n\"cntrl112\"[label=\"SetCoordinate(112)\"];\n\"cntrl114\"[label=\"LoadLDSTile{Value: Halfx2}(114)\"];\n\"cntrl115\"[label=\"Body(115)\",shape=box];\n\"cntrl116\"[label=\"SetCoordinate(116)\"];\n\"cntrl118\"[label=\"LoadLDSTile{Value: Halfx2}(118)\"];\n\"cntrl119\"[label=\"Body(119)\",shape=box];\n\"cntrl120\"[label=\"Multiply(120)\"];\n\"cntrl177\"[label=\"ConditionalOp 0 == beta: Equal(0.00000:S, DataFlowTag(24)S)BL(177)\"];\n\"cntrl185\"[label=\"NOP(185)\"];\n\"cntrl186\"[label=\"Assign VGPR Multiply(DataFlowTag(33)NA, DataFlowTag(35)NA)NA(186)\"];\n\"cntrl187\"[label=\"Assign VGPR Add(DataFlowTag(293)NA, DataFlowTag(295)NA)NA(187)\"];\n\"cntrl188\"[label=\"Assign VGPR Convert(DataFlowTag(297)NA)H(188)\"];\n\"cntrl189\"[label=\"StoreTiled Value: Halfx2(189)\"];\n\"cntrl190\"[label=\"LoadTiled Value: Halfx2(190)\"];\n\"cntrl191\"[label=\"Assign VGPR Multiply(DataFlowTag(24)NA, DataFlowTag(291)NA)NA(191)\"];\n\"cntrl194\"[label=\"Sequence(194)\",shape=box];\n\"cntrl203\"[label=\"Sequence(203)\",shape=box];\n\"cntrl217\"[label=\"ForLoopOp KLoopTail: LessThan(DataFlowTag(316)U32, Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32)BL(217)\"];\n\"cntrl218\"[label=\"Assign SGPR BitwiseAnd(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 4294967292:U32)U32(218)\"];\n\"cntrl219\"[label=\"Assign SGPR Add(DataFlowTag(316)U32, 1:U32)U32(219)\"];\n\"cntrl220\"[label=\"Initialize(220)\",shape=box];\n\"cntrl224\"[label=\"SetCoordinate(224)\"];\n\"cntrl225\"[label=\"LoadLDSTile{Value: Halfx2}(225)\"];\n\"cntrl226\"[label=\"SetCoordinate(226)\"];\n\"cntrl227\"[label=\"LoadLDSTile{Value: Halfx2}(227)\"];\n\"cntrl228\"[label=\"Multiply(228)\"];\n\"cntrl229\"[label=\"SetCoordinate(229)\"];\n\"cntrl230\"[label=\"LoadLDSTile{Value: Halfx2}(230)\"];\n\"cntrl231\"[label=\"SetCoordinate(231)\"];\n\"cntrl232\"[label=\"LoadLDSTile{Value: Halfx2}(232)\"];\n\"cntrl233\"[label=\"Multiply(233)\"];\n\"cntrl234\"[label=\"SetCoordinate(234)\"];\n\"cntrl235\"[label=\"LoadLDSTile{Value: Halfx2}(235)\"];\n\"cntrl236\"[label=\"SetCoordinate(236)\"];\n\"cntrl237\"[label=\"LoadLDSTile{Value: Halfx2}(237)\"];\n\"cntrl238\"[label=\"Multiply(238)\"];\n\"cntrl239\"[label=\"SetCoordinate(239)\"];\n\"cntrl240\"[label=\"LoadLDSTile{Value: Halfx2}(240)\"];\n\"cntrl241\"[label=\"SetCoordinate(241)\"];\n\"cntrl242\"[label=\"LoadLDSTile{Value: Halfx2}(242)\"];\n\"cntrl243\"[label=\"Multiply(243)\"];\n\"cntrl244\"[label=\"SetCoordinate(244)\"];\n\"cntrl245\"[label=\"LoadLDSTile{Value: Halfx2}(245)\"];\n\"cntrl246\"[label=\"SetCoordinate(246)\"];\n\"cntrl247\"[label=\"LoadLDSTile{Value: Halfx2}(247)\"];\n\"cntrl248\"[label=\"Multiply(248)\"];\n\"cntrl249\"[label=\"SetCoordinate(249)\"];\n\"cntrl250\"[label=\"LoadLDSTile{Value: Halfx2}(250)\"];\n\"cntrl251\"[label=\"SetCoordinate(251)\"];\n\"cntrl252\"[label=\"LoadLDSTile{Value: Halfx2}(252)\"];\n\"cntrl253\"[label=\"Multiply(253)\"];\n\"cntrl254\"[label=\"SetCoordinate(254)\"];\n\"cntrl255\"[label=\"LoadLDSTile{Value: Halfx2}(255)\"];\n\"cntrl256\"[label=\"SetCoordinate(256)\"];\n\"cntrl257\"[label=\"LoadLDSTile{Value: Halfx2}(257)\"];\n\"cntrl258\"[label=\"Multiply(258)\"];\n\"cntrl259\"[label=\"SetCoordinate(259)\"];\n\"cntrl260\"[label=\"LoadLDSTile{Value: Halfx2}(260)\"];\n\"cntrl261\"[label=\"SetCoordinate(261)\"];\n\"cntrl262\"[label=\"LoadLDSTile{Value: Halfx2}(262)\"];\n\"cntrl263\"[label=\"Multiply(263)\"];\n\"cntrl273\"[label=\"Body(273)\",shape=box];\n\"cntrl275\"[label=\"Body(275)\",shape=box];\n\"cntrl276\"[label=\"Sequence(276)\",shape=box];\n\"cntrl278\"[label=\"Body(278)\",shape=box];\n\"cntrl279\"[label=\"Sequence(279)\",shape=box];\n\"cntrl280\"[label=\"Body(280)\",shape=box];\n\"cntrl281\"[label=\"Sequence(281)\",shape=box];\n\"cntrl283\"[label=\"Body(283)\",shape=box];\n\"cntrl284\"[label=\"Sequence(284)\",shape=box];\n\"cntrl285\"[label=\"Body(285)\",shape=box];\n\"cntrl286\"[label=\"Sequence(286)\",shape=box];\n\"cntrl288\"[label=\"Body(288)\",shape=box];\n\"cntrl289\"[label=\"Sequence(289)\",shape=box];\n\"cntrl290\"[label=\"Body(290)\",shape=box];\n\"cntrl291\"[label=\"Sequence(291)\",shape=box];\n\"cntrl293\"[label=\"Body(293)\",shape=box];\n\"cntrl294\"[label=\"Sequence(294)\",shape=box];\n\"cntrl295\"[label=\"Body(295)\",shape=box];\n\"cntrl296\"[label=\"Sequence(296)\",shape=box];\n\"cntrl298\"[label=\"Body(298)\",shape=box];\n\"cntrl299\"[label=\"Sequence(299)\",shape=box];\n\"cntrl300\"[label=\"Body(300)\",shape=box];\n\"cntrl301\"[label=\"Sequence(301)\",shape=box];\n\"cntrl303\"[label=\"Body(303)\",shape=box];\n\"cntrl304\"[label=\"Sequence(304)\",shape=box];\n\"cntrl305\"[label=\"Body(305)\",shape=box];\n\"cntrl306\"[label=\"Sequence(306)\",shape=box];\n\"cntrl308\"[label=\"Body(308)\",shape=box];\n\"cntrl309\"[label=\"Sequence(309)\",shape=box];\n\"cntrl310\"[label=\"Body(310)\",shape=box];\n\"cntrl311\"[label=\"Sequence(311)\",shape=box];\n\"cntrl313\"[label=\"SetCoordinate(313)\"];\n\"cntrl314\"[label=\"SetCoordinate(314)\"];\n\"cntrl315\"[label=\"Body(315)\",shape=box];\n\"cntrl318\"[label=\"SetCoordinate(318)\"];\n\"cntrl323\"[label=\"SetCoordinate(323)\"];\n\"cntrl330\"[label=\"SetCoordinate(330)\"];\n\"cntrl331\"[label=\"LoadLDSTile{Value: Halfx2}(331)\"];\n\"cntrl332\"[label=\"SetCoordinate(332)\"];\n\"cntrl333\"[label=\"LoadLDSTile{Value: Halfx2}(333)\"];\n\"cntrl334\"[label=\"Multiply(334)\"];\n\"cntrl335\"[label=\"SetCoordinate(335)\"];\n\"cntrl336\"[label=\"LoadLDSTile{Value: Halfx2}(336)\"];\n\"cntrl337\"[label=\"SetCoordinate(337)\"];\n\"cntrl338\"[label=\"LoadLDSTile{Value: Halfx2}(338)\"];\n\"cntrl339\"[label=\"Multiply(339)\"];\n\"cntrl340\"[label=\"SetCoordinate(340)\"];\n\"cntrl341\"[label=\"LoadLDSTile{Value: Halfx2}(341)\"];\n\"cntrl342\"[label=\"SetCoordinate(342)\"];\n\"cntrl343\"[label=\"LoadLDSTile{Value: Halfx2}(343)\"];\n\"cntrl344\"[label=\"Multiply(344)\"];\n\"cntrl345\"[label=\"SetCoordinate(345)\"];\n\"cntrl346\"[label=\"LoadLDSTile{Value: Halfx2}(346)\"];\n\"cntrl347\"[label=\"SetCoordinate(347)\"];\n\"cntrl348\"[label=\"LoadLDSTile{Value: Halfx2}(348)\"];\n\"cntrl349\"[label=\"Multiply(349)\"];\n\"cntrl350\"[label=\"SetCoordinate(350)\"];\n\"cntrl351\"[label=\"LoadLDSTile{Value: Halfx2}(351)\"];\n\"cntrl352\"[label=\"SetCoordinate(352)\"];\n\"cntrl353\"[label=\"LoadLDSTile{Value: Halfx2}(353)\"];\n\"cntrl354\"[label=\"Multiply(354)\"];\n\"cntrl355\"[label=\"SetCoordinate(355)\"];\n\"cntrl356\"[label=\"LoadLDSTile{Value: Halfx2}(356)\"];\n\"cntrl357\"[label=\"SetCoordinate(357)\"];\n\"cntrl358\"[label=\"LoadLDSTile{Value: Halfx2}(358)\"];\n\"cntrl359\"[label=\"Multiply(359)\"];\n\"cntrl360\"[label=\"SetCoordinate(360)\"];\n\"cntrl361\"[label=\"LoadLDSTile{Value: Halfx2}(361)\"];\n\"cntrl362\"[label=\"SetCoordinate(362)\"];\n\"cntrl363\"[label=\"LoadLDSTile{Value: Halfx2}(363)\"];\n\"cntrl364\"[label=\"Multiply(364)\"];\n\"cntrl365\"[label=\"SetCoordinate(365)\"];\n\"cntrl366\"[label=\"LoadLDSTile{Value: Halfx2}(366)\"];\n\"cntrl367\"[label=\"SetCoordinate(367)\"];\n\"cntrl368\"[label=\"LoadLDSTile{Value: Halfx2}(368)\"];\n\"cntrl369\"[label=\"Multiply(369)\"];\n\"cntrl379\"[label=\"Body(379)\",shape=box];\n\"cntrl381\"[label=\"Body(381)\",shape=box];\n\"cntrl384\"[label=\"Body(384)\",shape=box];\n\"cntrl386\"[label=\"Body(386)\",shape=box];\n\"cntrl389\"[label=\"Body(389)\",shape=box];\n\"cntrl391\"[label=\"Body(391)\",shape=box];\n\"cntrl394\"[label=\"Body(394)\",shape=box];\n\"cntrl396\"[label=\"Body(396)\",shape=box];\n\"cntrl399\"[label=\"Body(399)\",shape=box];\n\"cntrl401\"[label=\"Body(401)\",shape=box];\n\"cntrl404\"[label=\"Body(404)\",shape=box];\n\"cntrl406\"[label=\"Body(406)\",shape=box];\n\"cntrl409\"[label=\"Body(409)\",shape=box];\n\"cntrl411\"[label=\"Body(411)\",shape=box];\n\"cntrl414\"[label=\"Body(414)\",shape=box];\n\"cntrl416\"[label=\"Body(416)\",shape=box];\n\"cntrl420\"[label=\"SetCoordinate(420)\"];\n\"cntrl421\"[label=\"LoadLDSTile{Value: Halfx2}(421)\"];\n\"cntrl422\"[label=\"SetCoordinate(422)\"];\n\"cntrl423\"[label=\"LoadLDSTile{Value: Halfx2}(423)\"];\n\"cntrl424\"[label=\"Multiply(424)\"];\n\"cntrl425\"[label=\"SetCoordinate(425)\"];\n\"cntrl426\"[label=\"LoadLDSTile{Value: Halfx2}(426)\"];\n\"cntrl427\"[label=\"SetCoordinate(427)\"];\n\"cntrl428\"[label=\"LoadLDSTile{Value: Halfx2}(428)\"];\n\"cntrl429\"[label=\"Multiply(429)\"];\n\"cntrl430\"[label=\"SetCoordinate(430)\"];\n\"cntrl431\"[label=\"LoadLDSTile{Value: Halfx2}(431)\"];\n\"cntrl432\"[label=\"SetCoordinate(432)\"];\n\"cntrl433\"[label=\"LoadLDSTile{Value: Halfx2}(433)\"];\n\"cntrl434\"[label=\"Multiply(434)\"];\n\"cntrl435\"[label=\"SetCoordinate(435)\"];\n\"cntrl436\"[label=\"LoadLDSTile{Value: Halfx2}(436)\"];\n\"cntrl437\"[label=\"SetCoordinate(437)\"];\n\"cntrl438\"[label=\"LoadLDSTile{Value: Halfx2}(438)\"];\n\"cntrl439\"[label=\"Multiply(439)\"];\n\"cntrl440\"[label=\"SetCoordinate(440)\"];\n\"cntrl441\"[label=\"LoadLDSTile{Value: Halfx2}(441)\"];\n\"cntrl442\"[label=\"SetCoordinate(442)\"];\n\"cntrl443\"[label=\"LoadLDSTile{Value: Halfx2}(443)\"];\n\"cntrl444\"[label=\"Multiply(444)\"];\n\"cntrl445\"[label=\"SetCoordinate(445)\"];\n\"cntrl446\"[label=\"LoadLDSTile{Value: Halfx2}(446)\"];\n\"cntrl447\"[label=\"SetCoordinate(447)\"];\n\"cntrl448\"[label=\"LoadLDSTile{Value: Halfx2}(448)\"];\n\"cntrl449\"[label=\"Multiply(449)\"];\n\"cntrl450\"[label=\"SetCoordinate(450)\"];\n\"cntrl451\"[label=\"LoadLDSTile{Value: Halfx2}(451)\"];\n\"cntrl452\"[label=\"SetCoordinate(452)\"];\n\"cntrl453\"[label=\"LoadLDSTile{Value: Halfx2}(453)\"];\n\"cntrl454\"[label=\"Multiply(454)\"];\n\"cntrl455\"[label=\"SetCoordinate(455)\"];\n\"cntrl456\"[label=\"LoadLDSTile{Value: Halfx2}(456)\"];\n\"cntrl457\"[label=\"SetCoordinate(457)\"];\n\"cntrl458\"[label=\"LoadLDSTile{Value: Halfx2}(458)\"];\n\"cntrl459\"[label=\"Multiply(459)\"];\n\"cntrl469\"[label=\"Body(469)\",shape=box];\n\"cntrl471\"[label=\"Body(471)\",shape=box];\n\"cntrl474\"[label=\"Body(474)\",shape=box];\n\"cntrl476\"[label=\"Body(476)\",shape=box];\n\"cntrl479\"[label=\"Body(479)\",shape=box];\n\"cntrl481\"[label=\"Body(481)\",shape=box];\n\"cntrl484\"[label=\"Body(484)\",shape=box];\n\"cntrl486\"[label=\"Body(486)\",shape=box];\n\"cntrl489\"[label=\"Body(489)\",shape=box];\n\"cntrl491\"[label=\"Body(491)\",shape=box];\n\"cntrl494\"[label=\"Body(494)\",shape=box];\n\"cntrl496\"[label=\"Body(496)\",shape=box];\n\"cntrl499\"[label=\"Body(499)\",shape=box];\n\"cntrl501\"[label=\"Body(501)\",shape=box];\n\"cntrl504\"[label=\"Body(504)\",shape=box];\n\"cntrl506\"[label=\"Body(506)\",shape=box];\n\"cntrl510\"[label=\"SetCoordinate(510)\"];\n\"cntrl511\"[label=\"LoadLDSTile{Value: Halfx2}(511)\"];\n\"cntrl512\"[label=\"SetCoordinate(512)\"];\n\"cntrl513\"[label=\"LoadLDSTile{Value: Halfx2}(513)\"];\n\"cntrl514\"[label=\"Multiply(514)\"];\n\"cntrl515\"[label=\"SetCoordinate(515)\"];\n\"cntrl516\"[label=\"LoadLDSTile{Value: Halfx2}(516)\"];\n\"cntrl517\"[label=\"SetCoordinate(517)\"];\n\"cntrl518\"[label=\"LoadLDSTile{Value: Halfx2}(518)\"];\n\"cntrl519\"[label=\"Multiply(519)\"];\n\"cntrl520\"[label=\"SetCoordinate(520)\"];\n\"cntrl521\"[label=\"LoadLDSTile{Value: Halfx2}(521)\"];\n\"cntrl522\"[label=\"SetCoordinate(522)\"];\n\"cntrl523\"[label=\"LoadLDSTile{Value: Halfx2}(523)\"];\n\"cntrl524\"[label=\"Multiply(524)\"];\n\"cntrl525\"[label=\"SetCoordinate(525)\"];\n\"cntrl526\"[label=\"LoadLDSTile{Value: Halfx2}(526)\"];\n\"cntrl527\"[label=\"SetCoordinate(527)\"];\n\"cntrl528\"[label=\"LoadLDSTile{Value: Halfx2}(528)\"];\n\"cntrl529\"[label=\"Multiply(529)\"];\n\"cntrl530\"[label=\"SetCoordinate(530)\"];\n\"cntrl531\"[label=\"LoadLDSTile{Value: Halfx2}(531)\"];\n\"cntrl532\"[label=\"SetCoordinate(532)\"];\n\"cntrl533\"[label=\"LoadLDSTile{Value: Halfx2}(533)\"];\n\"cntrl534\"[label=\"Multiply(534)\"];\n\"cntrl535\"[label=\"SetCoordinate(535)\"];\n\"cntrl536\"[label=\"LoadLDSTile{Value: Halfx2}(536)\"];\n\"cntrl537\"[label=\"SetCoordinate(537)\"];\n\"cntrl538\"[label=\"LoadLDSTile{Value: Halfx2}(538)\"];\n\"cntrl539\"[label=\"Multiply(539)\"];\n\"cntrl540\"[label=\"SetCoordinate(540)\"];\n\"cntrl541\"[label=\"LoadLDSTile{Value: Halfx2}(541)\"];\n\"cntrl542\"[label=\"SetCoordinate(542)\"];\n\"cntrl543\"[label=\"LoadLDSTile{Value: Halfx2}(543)\"];\n\"cntrl544\"[label=\"Multiply(544)\"];\n\"cntrl545\"[label=\"SetCoordinate(545)\"];\n\"cntrl546\"[label=\"LoadLDSTile{Value: Halfx2}(546)\"];\n\"cntrl547\"[label=\"SetCoordinate(547)\"];\n\"cntrl548\"[label=\"LoadLDSTile{Value: Halfx2}(548)\"];\n\"cntrl549\"[label=\"Multiply(549)\"];\n\"cntrl559\"[label=\"Body(559)\",shape=box];\n\"cntrl561\"[label=\"Body(561)\",shape=box];\n\"cntrl564\"[label=\"Body(564)\",shape=box];\n\"cntrl566\"[label=\"Body(566)\",shape=box];\n\"cntrl569\"[label=\"Body(569)\",shape=box];\n\"cntrl571\"[label=\"Body(571)\",shape=box];\n\"cntrl574\"[label=\"Body(574)\",shape=box];\n\"cntrl576\"[label=\"Body(576)\",shape=box];\n\"cntrl579\"[label=\"Body(579)\",shape=box];\n\"cntrl581\"[label=\"Body(581)\",shape=box];\n\"cntrl584\"[label=\"Body(584)\",shape=box];\n\"cntrl586\"[label=\"Body(586)\",shape=box];\n\"cntrl589\"[label=\"Body(589)\",shape=box];\n\"cntrl591\"[label=\"Body(591)\",shape=box];\n\"cntrl594\"[label=\"Body(594)\",shape=box];\n\"cntrl596\"[label=\"Body(596)\",shape=box];\n\"cntrl599\"[label=\"SetCoordinate(599)\"];\n\"cntrl604\"[label=\"SetCoordinate(604)\"];\n\"cntrl610\"[label=\"SetCoordinate(610)\"];\n\"cntrl615\"[label=\"SetCoordinate(615)\"];\n\"cntrl624\"[label=\"SetCoordinate(624)\"];\n\"cntrl629\"[label=\"SetCoordinate(629)\"];\n\"cntrl638\"[label=\"SetCoordinate(638)\"];\n\"cntrl643\"[label=\"SetCoordinate(643)\"];\n\"cntrl668\"[label=\"Sequence(668)\",shape=box];\n\"cntrl670\"[label=\"Scope(670)\"];\n\"cntrl675\"[label=\"NOP(675)\"];\n\"cntrl676\"[label=\"Body(676)\",shape=box];\n\"cntrl677\"[label=\"Sequence(677)\",shape=box];\n\"cntrl678\"[label=\"Scope(678)\"];\n\"cntrl679\"[label=\"Body(679)\",shape=box];\n\"cntrl681\"[label=\"NOP(681)\"];\n\"cntrl682\"[label=\"Body(682)\",shape=box];\n\"cntrl683\"[label=\"Sequence(683)\",shape=box];\n\"cntrl684\"[label=\"Scope(684)\"];\n\"cntrl685\"[label=\"Else(685)\",shape=box];\n\"cntrl687\"[label=\"NOP(687)\"];\n\"cntrl688\"[label=\"Body(688)\",shape=box];\n\"cntrl689\"[label=\"Sequence(689)\",shape=box];\n\"cntrl690\"[label=\"NOP(690)\"];\n\"cntrl693\"[label=\"Barrier(693)\"];\n\"cntrl694\"[label=\"NOP(694)\"];\n\"cntrl696\"[label=\"SetCoordinate(696)\"];\n\"cntrl699\"[label=\"SetCoordinate(699)\"];\n\"cntrl702\"[label=\"SetCoordinate(702)\"];\n\"cntrl705\"[label=\"SetCoordinate(705)\"];\n\"cntrl708\"[label=\"SetCoordinate(708)\"];\n\"cntrl711\"[label=\"SetCoordinate(711)\"];\n\"cntrl714\"[label=\"SetCoordinate(714)\"];\n\"cntrl717\"[label=\"SetCoordinate(717)\"];\n\"cntrl722\"[label=\"Sequence(722)\",shape=box];\n\"cntrl723\"[label=\"Sequence(723)\",shape=box];\n\"cntrl724\"[label=\"Sequence(724)\",shape=box];\n\"cntrl725\"[label=\"Sequence(725)\",shape=box];\n\"cntrl726\"[label=\"Sequence(726)\",shape=box];\n\"cntrl727\"[label=\"Sequence(727)\",shape=box];\n\"cntrl728\"[label=\"Sequence(728)\",shape=box];\n\"cntrl733\"[label=\"SetCoordinate(733)\"];\n\"cntrl734\"[label=\"LoadLDSTile{Value: Halfx2}(734)\"];\n\"cntrl735\"[label=\"Body(735)\",shape=box];\n\"cntrl736\"[label=\"SetCoordinate(736)\"];\n\"cntrl737\"[label=\"LoadLDSTile{Value: Halfx2}(737)\"];\n\"cntrl738\"[label=\"Body(738)\",shape=box];\n\"cntrl739\"[label=\"SetCoordinate(739)\"];\n\"cntrl740\"[label=\"LoadLDSTile{Value: Halfx2}(740)\"];\n\"cntrl741\"[label=\"Body(741)\",shape=box];\n\"cntrl742\"[label=\"SetCoordinate(742)\"];\n\"cntrl743\"[label=\"LoadLDSTile{Value: Halfx2}(743)\"];\n\"cntrl744\"[label=\"Body(744)\",shape=box];\n\"cntrl745\"[label=\"SetCoordinate(745)\"];\n\"cntrl746\"[label=\"LoadLDSTile{Value: Halfx2}(746)\"];\n\"cntrl747\"[label=\"Body(747)\",shape=box];\n\"cntrl748\"[label=\"SetCoordinate(748)\"];\n\"cntrl749\"[label=\"LoadLDSTile{Value: Halfx2}(749)\"];\n\"cntrl750\"[label=\"Body(750)\",shape=box];\n\"cntrl751\"[label=\"SetCoordinate(751)\"];\n\"cntrl752\"[label=\"LoadLDSTile{Value: Halfx2}(752)\"];\n\"cntrl753\"[label=\"Body(753)\",shape=box];\n\"cntrl754\"[label=\"SetCoordinate(754)\"];\n\"cntrl755\"[label=\"LoadLDSTile{Value: Halfx2}(755)\"];\n\"cntrl756\"[label=\"Body(756)\",shape=box];\n\"cntrl757\"[label=\"SetCoordinate(757)\"];\n\"cntrl758\"[label=\"LoadLDSTile{Value: Halfx2}(758)\"];\n\"cntrl759\"[label=\"Body(759)\",shape=box];\n\"cntrl760\"[label=\"SetCoordinate(760)\"];\n\"cntrl761\"[label=\"LoadLDSTile{Value: Halfx2}(761)\"];\n\"cntrl762\"[label=\"Body(762)\",shape=box];\n\"cntrl763\"[label=\"SetCoordinate(763)\"];\n\"cntrl764\"[label=\"LoadLDSTile{Value: Halfx2}(764)\"];\n\"cntrl765\"[label=\"Body(765)\",shape=box];\n\"cntrl766\"[label=\"SetCoordinate(766)\"];\n\"cntrl767\"[label=\"LoadLDSTile{Value: Halfx2}(767)\"];\n\"cntrl768\"[label=\"Body(768)\",shape=box];\n\"cntrl769\"[label=\"SetCoordinate(769)\"];\n\"cntrl770\"[label=\"LoadLDSTile{Value: Halfx2}(770)\"];\n\"cntrl771\"[label=\"Body(771)\",shape=box];\n\"cntrl772\"[label=\"SetCoordinate(772)\"];\n\"cntrl773\"[label=\"LoadLDSTile{Value: Halfx2}(773)\"];\n\"cntrl774\"[label=\"Body(774)\",shape=box];\n\"cntrl775\"[label=\"SetCoordinate(775)\"];\n\"cntrl776\"[label=\"LoadLDSTile{Value: Halfx2}(776)\"];\n\"cntrl777\"[label=\"Body(777)\",shape=box];\n\"cntrl778\"[label=\"SetCoordinate(778)\"];\n\"cntrl779\"[label=\"LoadLDSTile{Value: Halfx2}(779)\"];\n\"cntrl780\"[label=\"Body(780)\",shape=box];\n\"cntrl781\"[label=\"Sequence(781)\",shape=box];\n\"cntrl782\"[label=\"Sequence(782)\",shape=box];\n\"cntrl783\"[label=\"Sequence(783)\",shape=box];\n\"cntrl784\"[label=\"Sequence(784)\",shape=box];\n\"cntrl785\"[label=\"Sequence(785)\",shape=box];\n\"cntrl786\"[label=\"Sequence(786)\",shape=box];\n\"cntrl787\"[label=\"Sequence(787)\",shape=box];\n\"cntrl788\"[label=\"Sequence(788)\",shape=box];\n\"cntrl789\"[label=\"Sequence(789)\",shape=box];\n\"cntrl790\"[label=\"Sequence(790)\",shape=box];\n\"cntrl791\"[label=\"Sequence(791)\",shape=box];\n\"cntrl792\"[label=\"Sequence(792)\",shape=box];\n\"cntrl793\"[label=\"Sequence(793)\",shape=box];\n\"cntrl794\"[label=\"Sequence(794)\",shape=box];\n\"cntrl795\"[label=\"Sequence(795)\",shape=box];\n\"cntrl796\"[label=\"Sequence(796)\",shape=box];\n\"cntrl797\"[label=\"Sequence(797)\",shape=box];\n\"cntrl799\"[label=\"NOP(799)\"];\n\"cntrl800\"[label=\"NOP(800)\"];\n\"cntrl801\"[label=\"NOP(801)\"];\n\"cntrl802\"[label=\"NOP(802)\"];\n\"cntrl810\"[label=\"Body(810)\",shape=box];\n\"cntrl811\"[label=\"Barrier(811)\"];\n\"cntrl816\"[label=\"Body(816)\",shape=box];\n\"cntrl820\"[label=\"Sequence(820)\",shape=box];\n\"cntrl821\"[label=\"Sequence(821)\",shape=box];\n\"cntrl822\"[label=\"Sequence(822)\",shape=box];\n\"cntrl823\"[label=\"Sequence(823)\",shape=box];\n\"cntrl824\"[label=\"Sequence(824)\",shape=box];\n\"cntrl825\"[label=\"Sequence(825)\",shape=box];\n\"cntrl826\"[label=\"Sequence(826)\",shape=box];\n\"cntrl827\"[label=\"Sequence(827)\",shape=box];\n\"cntrl829\"[label=\"Sequence(829)\",shape=box];\n\"cntrl830\"[label=\"Sequence(830)\",shape=box];\n\"cntrl831\"[label=\"Sequence(831)\",shape=box];\n\"cntrl832\"[label=\"Sequence(832)\",shape=box];\n\"cntrl833\"[label=\"Sequence(833)\",shape=box];\n\"cntrl834\"[label=\"Sequence(834)\",shape=box];\n\"cntrl835\"[label=\"Sequence(835)\",shape=box];\n\"cntrl844\"[label=\"Sequence(844)\",shape=box];\n\"cntrl845\"[label=\"Sequence(845)\",shape=box];\n\"cntrl853\"[label=\"Barrier(853)\"];\n\"cntrl858\"[label=\"Sequence(858)\",shape=box];\n\"cntrl862\"[label=\"Sequence(862)\",shape=box];\n\"cntrl863\"[label=\"Sequence(863)\",shape=box];\n\"cntrl864\"[label=\"Sequence(864)\",shape=box];\n\"cntrl865\"[label=\"Sequence(865)\",shape=box];\n\"cntrl866\"[label=\"Sequence(866)\",shape=box];\n\"cntrl867\"[label=\"Sequence(867)\",shape=box];\n\"cntrl868\"[label=\"Sequence(868)\",shape=box];\n\"cntrl869\"[label=\"Sequence(869)\",shape=box];\n\"cntrl871\"[label=\"Sequence(871)\",shape=box];\n\"cntrl872\"[label=\"Sequence(872)\",shape=box];\n\"cntrl873\"[label=\"Sequence(873)\",shape=box];\n\"cntrl874\"[label=\"Sequence(874)\",shape=box];\n\"cntrl875\"[label=\"Sequence(875)\",shape=box];\n\"cntrl876\"[label=\"Sequence(876)\",shape=box];\n\"cntrl877\"[label=\"Sequence(877)\",shape=box];\n\"cntrl887\"[label=\"Sequence(887)\",shape=box];\n\"cntrl895\"[label=\"Barrier(895)\"];\n\"cntrl900\"[label=\"Sequence(900)\",shape=box];\n\"cntrl904\"[label=\"Sequence(904)\",shape=box];\n\"cntrl905\"[label=\"Sequence(905)\",shape=box];\n\"cntrl906\"[label=\"Sequence(906)\",shape=box];\n\"cntrl907\"[label=\"Sequence(907)\",shape=box];\n\"cntrl908\"[label=\"Sequence(908)\",shape=box];\n\"cntrl909\"[label=\"Sequence(909)\",shape=box];\n\"cntrl910\"[label=\"Sequence(910)\",shape=box];\n\"cntrl911\"[label=\"Sequence(911)\",shape=box];\n\"cntrl913\"[label=\"Sequence(913)\",shape=box];\n\"cntrl914\"[label=\"Sequence(914)\",shape=box];\n\"cntrl915\"[label=\"Sequence(915)\",shape=box];\n\"cntrl916\"[label=\"Sequence(916)\",shape=box];\n\"cntrl917\"[label=\"Sequence(917)\",shape=box];\n\"cntrl918\"[label=\"Sequence(918)\",shape=box];\n\"cntrl919\"[label=\"Sequence(919)\",shape=box];\n\"cntrl929\"[label=\"Sequence(929)\",shape=box];\n\"cntrl937\"[label=\"Barrier(937)\"];\n\"cntrl942\"[label=\"Sequence(942)\",shape=box];\n\"cntrl946\"[label=\"Sequence(946)\",shape=box];\n\"cntrl947\"[label=\"Sequence(947)\",shape=box];\n\"cntrl948\"[label=\"Sequence(948)\",shape=box];\n\"cntrl949\"[label=\"Sequence(949)\",shape=box];\n\"cntrl950\"[label=\"Sequence(950)\",shape=box];\n\"cntrl951\"[label=\"Sequence(951)\",shape=box];\n\"cntrl952\"[label=\"Sequence(952)\",shape=box];\n\"cntrl953\"[label=\"Sequence(953)\",shape=box];\n\"cntrl954\"[label=\"Sequence(954)\",shape=box];\n\"cntrl955\"[label=\"Sequence(955)\",shape=box];\n\"cntrl956\"[label=\"Sequence(956)\",shape=box];\n\"cntrl957\"[label=\"Sequence(957)\",shape=box];\n\"cntrl958\"[label=\"Sequence(958)\",shape=box];\n\"cntrl959\"[label=\"Sequence(959)\",shape=box];\n\"cntrl960\"[label=\"Sequence(960)\",shape=box];\n\"cntrl961\"[label=\"Sequence(961)\",shape=box];\n\"cntrl962\"[label=\"Sequence(962)\",shape=box];\n\"cntrl971\"[label=\"LoadTileDirect2LDS Value: Halfx2(971)\"];\n\"cntrl972\"[label=\"Body(972)\",shape=box];\n\"cntrl973\"[label=\"NOP(973)\"];\n\"cntrl975\"[label=\"Sequence(975)\",shape=box];\n\"cntrl976\"[label=\"LoadTileDirect2LDS Value: Halfx2(976)\"];\n\"cntrl977\"[label=\"Body(977)\",shape=box];\n\"cntrl978\"[label=\"NOP(978)\"];\n\"cntrl980\"[label=\"Sequence(980)\",shape=box];\n\"cntrl981\"[label=\"LoadTileDirect2LDS Value: Halfx2(981)\"];\n\"cntrl982\"[label=\"Body(982)\",shape=box];\n\"cntrl983\"[label=\"NOP(983)\"];\n\"cntrl984\"[label=\"Sequence(984)\",shape=box];\n\"cntrl987\"[label=\"LoadTileDirect2LDS Value: Halfx2(987)\"];\n\"cntrl988\"[label=\"Body(988)\",shape=box];\n\"cntrl989\"[label=\"NOP(989)\"];\n\"cntrl990\"[label=\"Sequence(990)\",shape=box];\n\"cntrl991\"[label=\"Sequence(991)\",shape=box];\n\"cntrl993\"[label=\"LoadTileDirect2LDS Value: Halfx2(993)\"];\n\"cntrl994\"[label=\"Body(994)\",shape=box];\n\"cntrl995\"[label=\"NOP(995)\"];\n\"cntrl997\"[label=\"Sequence(997)\",shape=box];\n\"cntrl998\"[label=\"LoadTileDirect2LDS Value: Halfx2(998)\"];\n\"cntrl999\"[label=\"Body(999)\",shape=box];\n\"cntrl1000\"[label=\"NOP(1000)\"];\n\"cntrl1001\"[label=\"Sequence(1001)\",shape=box];\n\"cntrl1002\"[label=\"Sequence(1002)\",shape=box];\n\"cntrl1003\"[label=\"LoadTileDirect2LDS Value: Halfx2(1003)\"];\n\"cntrl1004\"[label=\"Body(1004)\",shape=box];\n\"cntrl1005\"[label=\"NOP(1005)\"];\n\"cntrl1007\"[label=\"Sequence(1007)\",shape=box];\n\"cntrl1008\"[label=\"LoadTileDirect2LDS Value: Halfx2(1008)\"];\n\"cntrl1009\"[label=\"Body(1009)\",shape=box];\n\"cntrl1010\"[label=\"NOP(1010)\"];\n\"cntrl1011\"[label=\"Sequence(1011)\",shape=box];\n\"cntrl1012\"[label=\"Sequence(1012)\",shape=box];\n\"cntrl1013\"[label=\"LoadTileDirect2LDS Value: Halfx2(1013)\"];\n\"cntrl1014\"[label=\"Body(1014)\",shape=box];\n\"cntrl1015\"[label=\"NOP(1015)\"];\n\"cntrl1017\"[label=\"Sequence(1017)\",shape=box];\n\"cntrl1018\"[label=\"LoadTileDirect2LDS Value: Halfx2(1018)\"];\n\"cntrl1019\"[label=\"Body(1019)\",shape=box];\n\"cntrl1020\"[label=\"NOP(1020)\"];\n\"cntrl1021\"[label=\"Sequence(1021)\",shape=box];\n\"cntrl1022\"[label=\"Sequence(1022)\",shape=box];\n\"cntrl1023\"[label=\"LoadTileDirect2LDS Value: Halfx2(1023)\"];\n\"cntrl1025\"[label=\"NOP(1025)\"];\n\"cntrl1028\"[label=\"LoadTileDirect2LDS Value: Halfx2(1028)\"];\n\"cntrl1030\"[label=\"NOP(1030)\"];\n\"cntrl1031\"[label=\"Sequence(1031)\",shape=box];\n\"cntrl1032\"[label=\"Sequence(1032)\",shape=box];\n\"cntrl1033\"[label=\"LoadTileDirect2LDS Value: Halfx2(1033)\"];\n\"cntrl1035\"[label=\"LoadTileDirect2LDS Value: Halfx2(1035)\"];\n\"cntrl1037\"[label=\"LoadTileDirect2LDS Value: Halfx2(1037)\"];\n\"cntrl1039\"[label=\"LoadTileDirect2LDS Value: Halfx2(1039)\"];\n\"cntrl1041\"[label=\"LoadTileDirect2LDS Value: Halfx2(1041)\"];\n\"cntrl1043\"[label=\"LoadTileDirect2LDS Value: Halfx2(1043)\"];\n\"cntrl1045\"[label=\"NOP(1045)\"];\n\"cntrl1046\"[label=\"Assign VGPR Add(DataFlowTag(474)U64, DataFlowTag(475)U64)U64(1046)\"];\n\"cntrl1047\"[label=\"NOP(1047)\"];\n\"cntrl1048\"[label=\"NOP(1048)\"];\n\"cntrl1051\"[label=\"Scope(1051)\"];\n\"cntrl1052\"[label=\"Body(1052)\",shape=box];\n\"cntrl1053\"[label=\"Body(1053)\",shape=box];\n\"cntrl1056\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64)U64}, 1:U32)U64(1056)\"];\n\"cntrl1057\"[label=\"Assign VGPR 128:U64(1057)\"];\n\"cntrl1058\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1058)\"];\n\"cntrl1059\"[label=\"Sequence(1059)\",shape=box];\n\"cntrl1060\"[label=\"Sequence(1060)\",shape=box];\n\"cntrl1061\"[label=\"Sequence(1061)\",shape=box];\n\"cntrl1062\"[label=\"Sequence(1062)\",shape=box];\n\"cntrl1063\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1063)\"];\n\"cntrl1064\"[label=\"Sequence(1064)\",shape=box];\n\"cntrl1065\"[label=\"Sequence(1065)\",shape=box];\n\"cntrl1066\"[label=\"Assign VGPR 2:U64(1066)\"];\n\"cntrl1067\"[label=\"Sequence(1067)\",shape=box];\n\"cntrl1068\"[label=\"Sequence(1068)\",shape=box];\n\"cntrl1069\"[label=\"NOP(1069)\"];\n\"cntrl1070\"[label=\"NOP(1070)\"];\n\"cntrl1071\"[label=\"NOP(1071)\"];\n\"cntrl1074\"[label=\"Scope(1074)\"];\n\"cntrl1075\"[label=\"Sequence(1075)\",shape=box];\n\"cntrl1076\"[label=\"Sequence(1076)\",shape=box];\n\"cntrl1077\"[label=\"Body(1077)\",shape=box];\n\"cntrl1079\"[label=\"Assign VGPR 128:U64(1079)\"];\n\"cntrl1080\"[label=\"Sequence(1080)\",shape=box];\n\"cntrl1081\"[label=\"Sequence(1081)\",shape=box];\n\"cntrl1082\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1082)\"];\n\"cntrl1083\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1083)\"];\n\"cntrl1084\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1084)\"];\n\"cntrl1085\"[label=\"Sequence(1085)\",shape=box];\n\"cntrl1086\"[label=\"Sequence(1086)\",shape=box];\n\"cntrl1087\"[label=\"Sequence(1087)\",shape=box];\n\"cntrl1088\"[label=\"Sequence(1088)\",shape=box];\n\"cntrl1089\"[label=\"Assign VGPR 2:U64(1089)\"];\n\"cntrl1090\"[label=\"Sequence(1090)\",shape=box];\n\"cntrl1091\"[label=\"Sequence(1091)\",shape=box];\n\"cntrl1092\"[label=\"NOP(1092)\"];\n\"cntrl1093\"[label=\"Assign VGPR Add(DataFlowTag(487)U64, ShiftL(DataFlowTag(488)U64, 2:U32)U64)U64(1093)\"];\n\"cntrl1094\"[label=\"NOP(1094)\"];\n\"cntrl1095\"[label=\"NOP(1095)\"];\n\"cntrl1098\"[label=\"Sequence(1098)\",shape=box];\n\"cntrl1101\"[label=\"Assign VGPR ShiftL({Split: MultiplyAdd({Tile: ShiftLAdd(DataFlowTag(301)U32, 6:U32, LogicalShiftR(DataFlowTag(58)U32, 5:I)U32)U32}, Tensor_0_stride_0_9:I64, Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(58)U32, BitwiseAnd(DataFlowTag(58)U32, -32:I)U32)U32}, 1:U32)U32})U64)U64}, 1:U32)U64(1101)\"];\n\"cntrl1102\"[label=\"Assign VGPR 128:U64(1102)\"];\n\"cntrl1103\"[label=\"Assign SGPR Concatenate(Tensor_0_pointer:PG, BitFieldExtract(ShiftL(Tensor_0_extent_0:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1103)\"];\n\"cntrl1104\"[label=\"Sequence(1104)\",shape=box];\n\"cntrl1105\"[label=\"Sequence(1105)\",shape=box];\n\"cntrl1106\"[label=\"Sequence(1106)\",shape=box];\n\"cntrl1107\"[label=\"Sequence(1107)\",shape=box];\n\"cntrl1108\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_0_stride_0_9:I64, 3:U32)I64)U64, 1:U32)U64(1108)\"];\n\"cntrl1109\"[label=\"Sequence(1109)\",shape=box];\n\"cntrl1110\"[label=\"Sequence(1110)\",shape=box];\n\"cntrl1111\"[label=\"Assign VGPR 2:U64(1111)\"];\n\"cntrl1112\"[label=\"Sequence(1112)\",shape=box];\n\"cntrl1113\"[label=\"Sequence(1113)\",shape=box];\n\"cntrl1114\"[label=\"NOP(1114)\"];\n\"cntrl1115\"[label=\"Assign VGPR Add(DataFlowTag(493)U64, DataFlowTag(494)U64)U64(1115)\"];\n\"cntrl1116\"[label=\"NOP(1116)\"];\n\"cntrl1117\"[label=\"NOP(1117)\"];\n\"cntrl1120\"[label=\"Sequence(1120)\",shape=box];\n\"cntrl1123\"[label=\"Assign VGPR {Split: AddShiftL(Convert({Tile: ShiftLAdd(LogicalShiftR(Convert(ArithmeticShiftR(Tensor_0_size_1_10:I64, 6:U32)I64)U32, 2:U32)U32, 8:U32, {Tile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1123)\"];\n\"cntrl1124\"[label=\"Assign VGPR 128:U64(1124)\"];\n\"cntrl1125\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1125)\"];\n\"cntrl1126\"[label=\"Sequence(1126)\",shape=box];\n\"cntrl1127\"[label=\"Sequence(1127)\",shape=box];\n\"cntrl1128\"[label=\"Sequence(1128)\",shape=box];\n\"cntrl1129\"[label=\"Sequence(1129)\",shape=box];\n\"cntrl1130\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1130)\"];\n\"cntrl1131\"[label=\"Sequence(1131)\",shape=box];\n\"cntrl1132\"[label=\"Sequence(1132)\",shape=box];\n\"cntrl1133\"[label=\"Assign VGPR 2:U64(1133)\"];\n\"cntrl1134\"[label=\"Sequence(1134)\",shape=box];\n\"cntrl1135\"[label=\"Sequence(1135)\",shape=box];\n\"cntrl1136\"[label=\"NOP(1136)\"];\n\"cntrl1137\"[label=\"NOP(1137)\"];\n\"cntrl1138\"[label=\"NOP(1138)\"];\n\"cntrl1141\"[label=\"Sequence(1141)\",shape=box];\n\"cntrl1143\"[label=\"Assign VGPR 128:U64(1143)\"];\n\"cntrl1144\"[label=\"Sequence(1144)\",shape=box];\n\"cntrl1145\"[label=\"Sequence(1145)\",shape=box];\n\"cntrl1146\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1146)\"];\n\"cntrl1147\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1147)\"];\n\"cntrl1148\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1148)\"];\n\"cntrl1149\"[label=\"Sequence(1149)\",shape=box];\n\"cntrl1150\"[label=\"Sequence(1150)\",shape=box];\n\"cntrl1151\"[label=\"Sequence(1151)\",shape=box];\n\"cntrl1152\"[label=\"Sequence(1152)\",shape=box];\n\"cntrl1153\"[label=\"Assign VGPR 2:U64(1153)\"];\n\"cntrl1154\"[label=\"Sequence(1154)\",shape=box];\n\"cntrl1155\"[label=\"Sequence(1155)\",shape=box];\n\"cntrl1156\"[label=\"NOP(1156)\"];\n\"cntrl1157\"[label=\"Assign VGPR Add(DataFlowTag(506)U64, ShiftL(DataFlowTag(507)U64, 2:U32)U64)U64(1157)\"];\n\"cntrl1158\"[label=\"NOP(1158)\"];\n\"cntrl1159\"[label=\"NOP(1159)\"];\n\"cntrl1162\"[label=\"Sequence(1162)\",shape=box];\n\"cntrl1165\"[label=\"Assign VGPR {Split: AddShiftL(Convert({TileTile: ShiftL({Flatten[1]: Subtract(DataFlowTag(118)U32, BitwiseAnd(DataFlowTag(118)U32, -32:I)U32)U32}, 1:U32)U32})U64, Multiply({Tile: ShiftLAdd(DataFlowTag(303)U32, 6:U32, LogicalShiftR(DataFlowTag(118)U32, 5:I)U32)U32}, Tensor_2_stride_1_12:I64)I64, 1:U32)U64}(1165)\"];\n\"cntrl1166\"[label=\"Assign VGPR 128:U64(1166)\"];\n\"cntrl1167\"[label=\"Assign SGPR Concatenate(Tensor_2_pointer:PG, BitFieldExtract(ShiftL(Tensor_2_extent_2:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1167)\"];\n\"cntrl1168\"[label=\"Sequence(1168)\",shape=box];\n\"cntrl1169\"[label=\"Sequence(1169)\",shape=box];\n\"cntrl1170\"[label=\"Sequence(1170)\",shape=box];\n\"cntrl1171\"[label=\"Sequence(1171)\",shape=box];\n\"cntrl1172\"[label=\"Assign VGPR ShiftL(Convert(ShiftL(Tensor_2_stride_1_12:I64, 3:U32)I64)U64, 1:U32)U64(1172)\"];\n\"cntrl1173\"[label=\"Sequence(1173)\",shape=box];\n\"cntrl1174\"[label=\"Sequence(1174)\",shape=box];\n\"cntrl1175\"[label=\"Assign VGPR 2:U64(1175)\"];\n\"cntrl1176\"[label=\"Sequence(1176)\",shape=box];\n\"cntrl1177\"[label=\"Sequence(1177)\",shape=box];\n\"cntrl1178\"[label=\"NOP(1178)\"];\n\"cntrl1179\"[label=\"NOP(1179)\"];\n\"cntrl1181\"[label=\"Scope(1181)\"];\n\"cntrl1182\"[label=\"Sequence(1182)\",shape=box];\n\"cntrl1183\"[label=\"Sequence(1183)\",shape=box];\n\"cntrl1184\"[label=\"Body(1184)\",shape=box];\n\"cntrl1186\"[label=\"Assign VGPR {Split: AddShiftL({Tile: ShiftLAdd(DataFlowTag(305)U32, 6:U32, {Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(174)U32, 7:U32)U32, 5:U32, {Tile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Tile: ShiftLAdd(DataFlowTag(307)U32, 6:U32, {Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(174)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Tile: ShiftLAdd({Flatten[1]: BitwiseAnd(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(174)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_4_stride_1_13:I64)U32)U32, 1:U32)U32}(1186)\"];\n\"cntrl1187\"[label=\"Assign VGPR 16:U64(1187)\"];\n\"cntrl1188\"[label=\"Assign SGPR Concatenate(Tensor_4_pointer:PG, BitFieldExtract(ShiftL(Tensor_4_extent_4:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1188)\"];\n\"cntrl1190\"[label=\"Sequence(1190)\",shape=box];\n\"cntrl1192\"[label=\"Sequence(1192)\",shape=box];\n\"cntrl1193\"[label=\"Assign VGPR 2:U64(1193)\"];\n\"cntrl1194\"[label=\"Sequence(1194)\",shape=box];\n\"cntrl1195\"[label=\"Sequence(1195)\",shape=box];\n\"cntrl1196\"[label=\"NOP(1196)\"];\n\"cntrl1197\"[label=\"NOP(1197)\"];\n\"cntrl1199\"[label=\"NOP(1199)\"];\n\"cntrl1200\"[label=\"Sequence(1200)\",shape=box];\n\"cntrl1201\"[label=\"Sequence(1201)\",shape=box];\n\"cntrl1203\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1203)\"];\n\"cntrl1204\"[label=\"Assign VGPR 1024:U32(1204)\"];\n\"cntrl1205\"[label=\"Sequence(1205)\",shape=box];\n\"cntrl1206\"[label=\"Sequence(1206)\",shape=box];\n\"cntrl1207\"[label=\"Sequence(1207)\",shape=box];\n\"cntrl1208\"[label=\"Assign VGPR 2:U32(1208)\"];\n\"cntrl1209\"[label=\"Sequence(1209)\",shape=box];\n\"cntrl1210\"[label=\"Sequence(1210)\",shape=box];\n\"cntrl1211\"[label=\"NOP(1211)\"];\n\"cntrl1212\"[label=\"NOP(1212)\"];\n\"cntrl1214\"[label=\"Sequence(1214)\",shape=box];\n\"cntrl1216\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1216)\"];\n\"cntrl1217\"[label=\"Assign VGPR 1024:U32(1217)\"];\n\"cntrl1218\"[label=\"Sequence(1218)\",shape=box];\n\"cntrl1219\"[label=\"Sequence(1219)\",shape=box];\n\"cntrl1220\"[label=\"Sequence(1220)\",shape=box];\n\"cntrl1221\"[label=\"Assign VGPR 2:U32(1221)\"];\n\"cntrl1222\"[label=\"Sequence(1222)\",shape=box];\n\"cntrl1223\"[label=\"Sequence(1223)\",shape=box];\n\"cntrl1224\"[label=\"NOP(1224)\"];\n\"cntrl1225\"[label=\"NOP(1225)\"];\n\"cntrl1227\"[label=\"Scope(1227)\"];\n\"cntrl1228\"[label=\"Body(1228)\",shape=box];\n\"cntrl1229\"[label=\"Body(1229)\",shape=box];\n\"cntrl1231\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1231)\"];\n\"cntrl1232\"[label=\"Assign VGPR 1024:U32(1232)\"];\n\"cntrl1233\"[label=\"Sequence(1233)\",shape=box];\n\"cntrl1234\"[label=\"Sequence(1234)\",shape=box];\n\"cntrl1235\"[label=\"Sequence(1235)\",shape=box];\n\"cntrl1236\"[label=\"Assign VGPR 2:U32(1236)\"];\n\"cntrl1237\"[label=\"Sequence(1237)\",shape=box];\n\"cntrl1238\"[label=\"Sequence(1238)\",shape=box];\n\"cntrl1239\"[label=\"NOP(1239)\"];\n\"cntrl1240\"[label=\"NOP(1240)\"];\n\"cntrl1242\"[label=\"Body(1242)\",shape=box];\n\"cntrl1243\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1243)\"];\n\"cntrl1244\"[label=\"Assign VGPR 16:U32(1244)\"];\n\"cntrl1245\"[label=\"Sequence(1245)\",shape=box];\n\"cntrl1247\"[label=\"Sequence(1247)\",shape=box];\n\"cntrl1248\"[label=\"Assign VGPR 2:U32(1248)\"];\n\"cntrl1249\"[label=\"Sequence(1249)\",shape=box];\n\"cntrl1250\"[label=\"NOP(1250)\"];\n\"cntrl1251\"[label=\"NOP(1251)\"];\n\"cntrl1253\"[label=\"Sequence(1253)\",shape=box];\n\"cntrl1255\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1255)\"];\n\"cntrl1256\"[label=\"Assign VGPR 1024:U32(1256)\"];\n\"cntrl1257\"[label=\"Sequence(1257)\",shape=box];\n\"cntrl1258\"[label=\"Sequence(1258)\",shape=box];\n\"cntrl1259\"[label=\"Sequence(1259)\",shape=box];\n\"cntrl1260\"[label=\"Assign VGPR 2:U32(1260)\"];\n\"cntrl1261\"[label=\"Sequence(1261)\",shape=box];\n\"cntrl1262\"[label=\"Sequence(1262)\",shape=box];\n\"cntrl1263\"[label=\"NOP(1263)\"];\n\"cntrl1264\"[label=\"NOP(1264)\"];\n\"cntrl1266\"[label=\"Sequence(1266)\",shape=box];\n\"cntrl1268\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1268)\"];\n\"cntrl1269\"[label=\"Assign VGPR 1024:U32(1269)\"];\n\"cntrl1270\"[label=\"Sequence(1270)\",shape=box];\n\"cntrl1271\"[label=\"Sequence(1271)\",shape=box];\n\"cntrl1272\"[label=\"Sequence(1272)\",shape=box];\n\"cntrl1273\"[label=\"Assign VGPR 2:U32(1273)\"];\n\"cntrl1274\"[label=\"Sequence(1274)\",shape=box];\n\"cntrl1275\"[label=\"Sequence(1275)\",shape=box];\n\"cntrl1276\"[label=\"NOP(1276)\"];\n\"cntrl1277\"[label=\"NOP(1277)\"];\n\"cntrl1279\"[label=\"Scope(1279)\"];\n\"cntrl1280\"[label=\"Body(1280)\",shape=box];\n\"cntrl1281\"[label=\"Body(1281)\",shape=box];\n\"cntrl1283\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1283)\"];\n\"cntrl1284\"[label=\"Assign VGPR 1024:U32(1284)\"];\n\"cntrl1285\"[label=\"Sequence(1285)\",shape=box];\n\"cntrl1286\"[label=\"Sequence(1286)\",shape=box];\n\"cntrl1287\"[label=\"Sequence(1287)\",shape=box];\n\"cntrl1288\"[label=\"Assign VGPR 2:U32(1288)\"];\n\"cntrl1289\"[label=\"Sequence(1289)\",shape=box];\n\"cntrl1290\"[label=\"Sequence(1290)\",shape=box];\n\"cntrl1291\"[label=\"NOP(1291)\"];\n\"cntrl1292\"[label=\"NOP(1292)\"];\n\"cntrl1294\"[label=\"Body(1294)\",shape=box];\n\"cntrl1295\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1295)\"];\n\"cntrl1296\"[label=\"Assign VGPR 16:U32(1296)\"];\n\"cntrl1297\"[label=\"Sequence(1297)\",shape=box];\n\"cntrl1299\"[label=\"Sequence(1299)\",shape=box];\n\"cntrl1300\"[label=\"Assign VGPR 2:U32(1300)\"];\n\"cntrl1301\"[label=\"Sequence(1301)\",shape=box];\n\"cntrl1302\"[label=\"NOP(1302)\"];\n\"cntrl1303\"[label=\"NOP(1303)\"];\n\"cntrl1305\"[label=\"NOP(1305)\"];\n\"cntrl1307\"[label=\"Sequence(1307)\",shape=box];\n\"cntrl1309\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1309)\"];\n\"cntrl1310\"[label=\"Assign VGPR 16:U64(1310)\"];\n\"cntrl1311\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1311)\"];\n\"cntrl1312\"[label=\"Sequence(1312)\",shape=box];\n\"cntrl1313\"[label=\"Sequence(1313)\",shape=box];\n\"cntrl1314\"[label=\"Sequence(1314)\",shape=box];\n\"cntrl1315\"[label=\"Sequence(1315)\",shape=box];\n\"cntrl1316\"[label=\"Assign VGPR 2:U64(1316)\"];\n\"cntrl1317\"[label=\"Sequence(1317)\",shape=box];\n\"cntrl1318\"[label=\"Sequence(1318)\",shape=box];\n\"cntrl1319\"[label=\"NOP(1319)\"];\n\"cntrl1320\"[label=\"NOP(1320)\"];\n\"cntrl1322\"[label=\"NOP(1322)\"];\n\"cntrl1324\"[label=\"Sequence(1324)\",shape=box];\n\"cntrl1326\"[label=\"Assign VGPR {Join: AddShiftL({Flatten: ShiftLAdd(DataFlowTag(309)U32, 6:U32, {Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(214)U32, 7:U32)U32, 5:U32, {Flatten: ShiftL(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32})U32}, Multiply({Flatten: ShiftLAdd(DataFlowTag(311)U32, 6:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR(DataFlowTag(214)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten: ShiftLAdd({Tile[1]: BitwiseAnd(LogicalShiftR({Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 63:U32)U32}, 2:U32)U32, 7:U32)U32}, 2:U32, {Tile[1]: BitwiseAnd(DataFlowTag(214)U32, 3:U32)U32})U32})U32})U32}, Convert(Tensor_15_stride_1_14:I64)U32)U32, 1:U32)U32}(1326)\"];\n\"cntrl1327\"[label=\"Assign VGPR 16:U64(1327)\"];\n\"cntrl1328\"[label=\"Assign SGPR Concatenate(Tensor_15_pointer:PG, BitFieldExtract(ShiftL(Tensor_15_extent_15:I64, 1:U32)I64, width:32, offset:0)R, 131072:R)PB(1328)\"];\n\"cntrl1329\"[label=\"Sequence(1329)\",shape=box];\n\"cntrl1330\"[label=\"Sequence(1330)\",shape=box];\n\"cntrl1331\"[label=\"Sequence(1331)\",shape=box];\n\"cntrl1332\"[label=\"Sequence(1332)\",shape=box];\n\"cntrl1333\"[label=\"Assign VGPR 2:U64(1333)\"];\n\"cntrl1334\"[label=\"Sequence(1334)\",shape=box];\n\"cntrl1335\"[label=\"Sequence(1335)\",shape=box];\n\"cntrl1336\"[label=\"NOP(1336)\"];\n\"cntrl1337\"[label=\"NOP(1337)\"];\n\"cntrl1339\"[label=\"Sequence(1339)\",shape=box];\n\"cntrl1341\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1341)\"];\n\"cntrl1342\"[label=\"Assign VGPR 1024:U32(1342)\"];\n\"cntrl1343\"[label=\"Sequence(1343)\",shape=box];\n\"cntrl1344\"[label=\"Sequence(1344)\",shape=box];\n\"cntrl1345\"[label=\"Sequence(1345)\",shape=box];\n\"cntrl1346\"[label=\"Assign VGPR 2:U32(1346)\"];\n\"cntrl1347\"[label=\"Sequence(1347)\",shape=box];\n\"cntrl1348\"[label=\"Sequence(1348)\",shape=box];\n\"cntrl1349\"[label=\"NOP(1349)\"];\n\"cntrl1350\"[label=\"NOP(1350)\"];\n\"cntrl1352\"[label=\"Scope(1352)\"];\n\"cntrl1353\"[label=\"Body(1353)\",shape=box];\n\"cntrl1354\"[label=\"Body(1354)\",shape=box];\n\"cntrl1356\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1356)\"];\n\"cntrl1357\"[label=\"Assign VGPR 1024:U32(1357)\"];\n\"cntrl1358\"[label=\"Sequence(1358)\",shape=box];\n\"cntrl1359\"[label=\"Sequence(1359)\",shape=box];\n\"cntrl1360\"[label=\"Sequence(1360)\",shape=box];\n\"cntrl1361\"[label=\"Assign VGPR 2:U32(1361)\"];\n\"cntrl1362\"[label=\"Sequence(1362)\",shape=box];\n\"cntrl1363\"[label=\"Sequence(1363)\",shape=box];\n\"cntrl1364\"[label=\"NOP(1364)\"];\n\"cntrl1365\"[label=\"NOP(1365)\"];\n\"cntrl1367\"[label=\"Body(1367)\",shape=box];\n\"cntrl1368\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1368)\"];\n\"cntrl1369\"[label=\"Assign VGPR 16:U32(1369)\"];\n\"cntrl1370\"[label=\"Sequence(1370)\",shape=box];\n\"cntrl1372\"[label=\"Sequence(1372)\",shape=box];\n\"cntrl1373\"[label=\"Assign VGPR 2:U32(1373)\"];\n\"cntrl1374\"[label=\"Sequence(1374)\",shape=box];\n\"cntrl1375\"[label=\"NOP(1375)\"];\n\"cntrl1376\"[label=\"NOP(1376)\"];\n\"cntrl1378\"[label=\"Sequence(1378)\",shape=box];\n\"cntrl1380\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1380)\"];\n\"cntrl1381\"[label=\"Assign VGPR 1024:U32(1381)\"];\n\"cntrl1382\"[label=\"Sequence(1382)\",shape=box];\n\"cntrl1383\"[label=\"Sequence(1383)\",shape=box];\n\"cntrl1384\"[label=\"Sequence(1384)\",shape=box];\n\"cntrl1385\"[label=\"Assign VGPR 2:U32(1385)\"];\n\"cntrl1386\"[label=\"Sequence(1386)\",shape=box];\n\"cntrl1387\"[label=\"Sequence(1387)\",shape=box];\n\"cntrl1388\"[label=\"NOP(1388)\"];\n\"cntrl1389\"[label=\"NOP(1389)\"];\n\"cntrl1391\"[label=\"Scope(1391)\"];\n\"cntrl1392\"[label=\"Body(1392)\",shape=box];\n\"cntrl1393\"[label=\"Body(1393)\",shape=box];\n\"cntrl1395\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1395)\"];\n\"cntrl1396\"[label=\"Assign VGPR 1024:U32(1396)\"];\n\"cntrl1397\"[label=\"Sequence(1397)\",shape=box];\n\"cntrl1398\"[label=\"Sequence(1398)\",shape=box];\n\"cntrl1399\"[label=\"Sequence(1399)\",shape=box];\n\"cntrl1400\"[label=\"Assign VGPR 2:U32(1400)\"];\n\"cntrl1401\"[label=\"Sequence(1401)\",shape=box];\n\"cntrl1402\"[label=\"Sequence(1402)\",shape=box];\n\"cntrl1403\"[label=\"NOP(1403)\"];\n\"cntrl1404\"[label=\"NOP(1404)\"];\n\"cntrl1406\"[label=\"Body(1406)\",shape=box];\n\"cntrl1407\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1407)\"];\n\"cntrl1408\"[label=\"Assign VGPR 16:U32(1408)\"];\n\"cntrl1409\"[label=\"Sequence(1409)\",shape=box];\n\"cntrl1411\"[label=\"Sequence(1411)\",shape=box];\n\"cntrl1412\"[label=\"Assign VGPR 2:U32(1412)\"];\n\"cntrl1413\"[label=\"Sequence(1413)\",shape=box];\n\"cntrl1414\"[label=\"NOP(1414)\"];\n\"cntrl1415\"[label=\"NOP(1415)\"];\n\"cntrl1417\"[label=\"Sequence(1417)\",shape=box];\n\"cntrl1419\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1419)\"];\n\"cntrl1420\"[label=\"Assign VGPR 1024:U32(1420)\"];\n\"cntrl1421\"[label=\"Sequence(1421)\",shape=box];\n\"cntrl1422\"[label=\"Sequence(1422)\",shape=box];\n\"cntrl1423\"[label=\"Sequence(1423)\",shape=box];\n\"cntrl1424\"[label=\"Assign VGPR 2:U32(1424)\"];\n\"cntrl1425\"[label=\"Sequence(1425)\",shape=box];\n\"cntrl1426\"[label=\"Sequence(1426)\",shape=box];\n\"cntrl1427\"[label=\"NOP(1427)\"];\n\"cntrl1428\"[label=\"NOP(1428)\"];\n\"cntrl1430\"[label=\"Scope(1430)\"];\n\"cntrl1431\"[label=\"Body(1431)\",shape=box];\n\"cntrl1432\"[label=\"Body(1432)\",shape=box];\n\"cntrl1434\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1434)\"];\n\"cntrl1435\"[label=\"Assign VGPR 1024:U32(1435)\"];\n\"cntrl1436\"[label=\"Sequence(1436)\",shape=box];\n\"cntrl1437\"[label=\"Sequence(1437)\",shape=box];\n\"cntrl1438\"[label=\"Sequence(1438)\",shape=box];\n\"cntrl1439\"[label=\"Assign VGPR 2:U32(1439)\"];\n\"cntrl1440\"[label=\"Sequence(1440)\",shape=box];\n\"cntrl1441\"[label=\"Sequence(1441)\",shape=box];\n\"cntrl1442\"[label=\"NOP(1442)\"];\n\"cntrl1443\"[label=\"NOP(1443)\"];\n\"cntrl1445\"[label=\"Body(1445)\",shape=box];\n\"cntrl1446\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1446)\"];\n\"cntrl1447\"[label=\"Assign VGPR 16:U32(1447)\"];\n\"cntrl1448\"[label=\"Sequence(1448)\",shape=box];\n\"cntrl1450\"[label=\"Sequence(1450)\",shape=box];\n\"cntrl1451\"[label=\"Assign VGPR 2:U32(1451)\"];\n\"cntrl1452\"[label=\"Sequence(1452)\",shape=box];\n\"cntrl1453\"[label=\"NOP(1453)\"];\n\"cntrl1454\"[label=\"NOP(1454)\"];\n\"cntrl1456\"[label=\"Sequence(1456)\",shape=box];\n\"cntrl1458\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1458)\"];\n\"cntrl1459\"[label=\"Assign VGPR 1024:U32(1459)\"];\n\"cntrl1460\"[label=\"Sequence(1460)\",shape=box];\n\"cntrl1461\"[label=\"Sequence(1461)\",shape=box];\n\"cntrl1462\"[label=\"Sequence(1462)\",shape=box];\n\"cntrl1463\"[label=\"Assign VGPR 2:U32(1463)\"];\n\"cntrl1464\"[label=\"Sequence(1464)\",shape=box];\n\"cntrl1465\"[label=\"Sequence(1465)\",shape=box];\n\"cntrl1466\"[label=\"NOP(1466)\"];\n\"cntrl1467\"[label=\"NOP(1467)\"];\n\"cntrl1469\"[label=\"Scope(1469)\"];\n\"cntrl1470\"[label=\"Body(1470)\",shape=box];\n\"cntrl1471\"[label=\"Body(1471)\",shape=box];\n\"cntrl1473\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1473)\"];\n\"cntrl1474\"[label=\"Assign VGPR 1024:U32(1474)\"];\n\"cntrl1475\"[label=\"Sequence(1475)\",shape=box];\n\"cntrl1476\"[label=\"Sequence(1476)\",shape=box];\n\"cntrl1477\"[label=\"Sequence(1477)\",shape=box];\n\"cntrl1478\"[label=\"Assign VGPR 2:U32(1478)\"];\n\"cntrl1479\"[label=\"Sequence(1479)\",shape=box];\n\"cntrl1480\"[label=\"Sequence(1480)\",shape=box];\n\"cntrl1481\"[label=\"NOP(1481)\"];\n\"cntrl1482\"[label=\"NOP(1482)\"];\n\"cntrl1484\"[label=\"Body(1484)\",shape=box];\n\"cntrl1485\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1485)\"];\n\"cntrl1486\"[label=\"Assign VGPR 16:U32(1486)\"];\n\"cntrl1487\"[label=\"Sequence(1487)\",shape=box];\n\"cntrl1489\"[label=\"Sequence(1489)\",shape=box];\n\"cntrl1490\"[label=\"Assign VGPR 2:U32(1490)\"];\n\"cntrl1491\"[label=\"Sequence(1491)\",shape=box];\n\"cntrl1492\"[label=\"NOP(1492)\"];\n\"cntrl1493\"[label=\"NOP(1493)\"];\n\"cntrl1495\"[label=\"Sequence(1495)\",shape=box];\n\"cntrl1497\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1497)\"];\n\"cntrl1498\"[label=\"Assign VGPR 1024:U32(1498)\"];\n\"cntrl1499\"[label=\"Sequence(1499)\",shape=box];\n\"cntrl1500\"[label=\"Sequence(1500)\",shape=box];\n\"cntrl1501\"[label=\"Sequence(1501)\",shape=box];\n\"cntrl1502\"[label=\"Assign VGPR 2:U32(1502)\"];\n\"cntrl1503\"[label=\"Sequence(1503)\",shape=box];\n\"cntrl1504\"[label=\"Sequence(1504)\",shape=box];\n\"cntrl1505\"[label=\"NOP(1505)\"];\n\"cntrl1506\"[label=\"NOP(1506)\"];\n\"cntrl1508\"[label=\"Scope(1508)\"];\n\"cntrl1509\"[label=\"Body(1509)\",shape=box];\n\"cntrl1510\"[label=\"Body(1510)\",shape=box];\n\"cntrl1512\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(73)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(73)U32, BitwiseAnd(DataFlowTag(73)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1512)\"];\n\"cntrl1513\"[label=\"Assign VGPR 1024:U32(1513)\"];\n\"cntrl1514\"[label=\"Sequence(1514)\",shape=box];\n\"cntrl1515\"[label=\"Sequence(1515)\",shape=box];\n\"cntrl1516\"[label=\"Sequence(1516)\",shape=box];\n\"cntrl1517\"[label=\"Assign VGPR 2:U32(1517)\"];\n\"cntrl1518\"[label=\"Sequence(1518)\",shape=box];\n\"cntrl1519\"[label=\"Sequence(1519)\",shape=box];\n\"cntrl1520\"[label=\"NOP(1520)\"];\n\"cntrl1521\"[label=\"NOP(1521)\"];\n\"cntrl1523\"[label=\"Body(1523)\",shape=box];\n\"cntrl1524\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd(LogicalShiftR(DataFlowTag(84)U32, 7:U32)U32, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(84)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1524)\"];\n\"cntrl1525\"[label=\"Assign VGPR 16:U32(1525)\"];\n\"cntrl1526\"[label=\"Sequence(1526)\",shape=box];\n\"cntrl1528\"[label=\"Sequence(1528)\",shape=box];\n\"cntrl1529\"[label=\"Assign VGPR 2:U32(1529)\"];\n\"cntrl1530\"[label=\"Sequence(1530)\",shape=box];\n\"cntrl1531\"[label=\"NOP(1531)\"];\n\"cntrl1532\"[label=\"NOP(1532)\"];\n\"cntrl1534\"[label=\"Sequence(1534)\",shape=box];\n\"cntrl1536\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1536)\"];\n\"cntrl1537\"[label=\"Assign VGPR 1024:U32(1537)\"];\n\"cntrl1538\"[label=\"Sequence(1538)\",shape=box];\n\"cntrl1539\"[label=\"Sequence(1539)\",shape=box];\n\"cntrl1540\"[label=\"Sequence(1540)\",shape=box];\n\"cntrl1541\"[label=\"Assign VGPR 2:U32(1541)\"];\n\"cntrl1542\"[label=\"Sequence(1542)\",shape=box];\n\"cntrl1543\"[label=\"Sequence(1543)\",shape=box];\n\"cntrl1544\"[label=\"NOP(1544)\"];\n\"cntrl1545\"[label=\"NOP(1545)\"];\n\"cntrl1547\"[label=\"Scope(1547)\"];\n\"cntrl1548\"[label=\"Body(1548)\",shape=box];\n\"cntrl1549\"[label=\"Body(1549)\",shape=box];\n\"cntrl1551\"[label=\"Assign SGPR ToScalar(ShiftL({Flatten: ShiftLAdd(LogicalShiftR(DataFlowTag(133)U32, 5:I)U32, 6:U32, {Flatten: ShiftL({Tile[1]: Subtract(DataFlowTag(133)U32, BitwiseAnd(DataFlowTag(133)U32, -32:I)U32)U32}, 1:U32)U32})U32}, 1:U32)U32)U32(1551)\"];\n\"cntrl1552\"[label=\"Assign VGPR 1024:U32(1552)\"];\n\"cntrl1553\"[label=\"Sequence(1553)\",shape=box];\n\"cntrl1554\"[label=\"Sequence(1554)\",shape=box];\n\"cntrl1555\"[label=\"Sequence(1555)\",shape=box];\n\"cntrl1556\"[label=\"Assign VGPR 2:U32(1556)\"];\n\"cntrl1557\"[label=\"Sequence(1557)\",shape=box];\n\"cntrl1558\"[label=\"Sequence(1558)\",shape=box];\n\"cntrl1559\"[label=\"NOP(1559)\"];\n\"cntrl1560\"[label=\"NOP(1560)\"];\n\"cntrl1562\"[label=\"Body(1562)\",shape=box];\n\"cntrl1563\"[label=\"Assign VGPR ShiftL({Tile: ShiftLAdd({Tile: ShiftLAdd({Tile: BitwiseAnd(LogicalShiftR(DataFlowTag(144)U32, 6:U32)U32, 1:U32)U32}, 5:U32, {Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 31:U32)U32})U32}, 6:U32, {TileTile: ShiftL(LogicalShiftR({Flatten[1]: BitwiseAnd(DataFlowTag(144)U32, 63:U32)U32}, 5:U32)U32, 2:U32)U32})U32}, 1:U32)U32(1563)\"];\n\"cntrl1564\"[label=\"Assign VGPR 16:U32(1564)\"];\n\"cntrl1565\"[label=\"Sequence(1565)\",shape=box];\n\"cntrl1567\"[label=\"Sequence(1567)\",shape=box];\n\"cntrl1568\"[label=\"Assign VGPR 2:U32(1568)\"];\n\"cntrl1569\"[label=\"Sequence(1569)\",shape=box];\n\"cntrl1570\"[label=\"Sequence(1570)\",shape=box];\n\"cntrl1571\"[label=\"Sequence(1571)\",shape=box];\n\"cntrl1572\"[label=\"Sequence(1572)\",shape=box];\n\"cntrl1573\"[label=\"Sequence(1573)\",shape=box];\n\"cntrl1574\"[label=\"Sequence(1574)\",shape=box];\n\"cntrl1575\"[label=\"Sequence(1575)\",shape=box];\n\"cntrl1576\"[label=\"Sequence(1576)\",shape=box];\n\"cntrl1577\"[label=\"Sequence(1577)\",shape=box];\n\"cntrl1578\"[label=\"Sequence(1578)\",shape=box];\n\"cntrl1579\"[label=\"Sequence(1579)\",shape=box];\n\"cntrl1580\"[label=\"Sequence(1580)\",shape=box];\n\"cntrl1581\"[label=\"Sequence(1581)\",shape=box];\n\"cntrl1582\"[label=\"Sequence(1582)\",shape=box];\n\"cntrl1583\"[label=\"Sequence(1583)\",shape=box];\n\"cntrl1584\"[label=\"Sequence(1584)\",shape=box];\n\"cntrl1585\"[label=\"Sequence(1585)\",shape=box];\n\"cntrl1586\"[label=\"Body(1586)\",shape=box];\n\"cntrl1595\"[label=\"Body(1595)\",shape=box];\n\"cntrl1629\"[label=\"Sequence(1629)\",shape=box];\n\"cntrl1630\"[label=\"Sequence(1630)\",shape=box];\n\"cntrl1631\"[label=\"Sequence(1631)\",shape=box];\n\"cntrl1632\"[label=\"Sequence(1632)\",shape=box];\n\"cntrl1633\"[label=\"Sequence(1633)\",shape=box];\n\"cntrl1634\"[label=\"Sequence(1634)\",shape=box];\n\"cntrl1635\"[label=\"Sequence(1635)\",shape=box];\n\"cntrl1660\"[label=\"Sequence(1660)\",shape=box];\n\"cntrl1668\"[label=\"Sequence(1668)\",shape=box];\n\"cntrl1670\"[label=\"Sequence(1670)\",shape=box];\n\"cntrl1672\"[label=\"Sequence(1672)\",shape=box];\n\"cntrl1674\"[label=\"Sequence(1674)\",shape=box];\n\"cntrl1723\"[label=\"Barrier(1723)\"];\n\"cntrl1724\"[label=\"Sequence(1724)\",shape=box];\n\"cntrl1725\"[label=\"Sequence(1725)\",shape=box];\n\"cntrl1726\"[label=\"Barrier(1726)\"];\n\"cntrl1727\"[label=\"Body(1727)\",shape=box];\n\"cntrl1728\"[label=\"Sequence(1728)\",shape=box];\n\"cntrl1729\"[label=\"Barrier(1729)\"];\n\"cntrl1730\"[label=\"Sequence(1730)\",shape=box];\n\"cntrl1731\"[label=\"Sequence(1731)\",shape=box];\n\"cntrl1732\"[label=\"Sequence(1732)\",shape=box];\n\"cntrl1733\"[label=\"Barrier(1733)\"];\n\"cntrl1734\"[label=\"Body(1734)\",shape=box];\n\"cntrl1735\"[label=\"Sequence(1735)\",shape=box];\n\"cntrl1736\"[label=\"Barrier(1736)\"];\n\"cntrl1737\"[label=\"Sequence(1737)\",shape=box];\n\"cntrl1738\"[label=\"Sequence(1738)\",shape=box];\n\"cntrl1739\"[label=\"Barrier(1739)\"];\n\"cntrl1740\"[label=\"Sequence(1740)\",shape=box];\n\"cntrl1741\"[label=\"Sequence(1741)\",shape=box];\n\"cntrl1742\"[label=\"Sequence(1742)\",shape=box];\n\"cntrl1743\"[label=\"Barrier(1743)\"];\n\"cntrl1744\"[label=\"Sequence(1744)\",shape=box];\n\"cntrl1745\"[label=\"Sequence(1745)\",shape=box];\n\"cntrl1746\"[label=\"Barrier(1746)\"];\n\"cntrl1747\"[label=\"Sequence(1747)\",shape=box];\n\"cntrl1748\"[label=\"Sequence(1748)\",shape=box];\n\"cntrl1749\"[label=\"Barrier(1749)\"];\n\"cntrl1750\"[label=\"Sequence(1750)\",shape=box];\n\"cntrl1751\"[label=\"Sequence(1751)\",shape=box];\n\"cntrl1752\"[label=\"Barrier(1752)\"];\n\"cntrl1753\"[label=\"Sequence(1753)\",shape=box];\n\"cntrl1754\"[label=\"Sequence(1754)\",shape=box];\n\"cntrl1755\"[label=\"Barrier(1755)\"];\n\"cntrl1757\"[label=\"Sequence(1757)\",shape=box];\n\"cntrl1758\"[label=\"Barrier(1758)\"];\n\"cntrl1759\"[label=\"Sequence(1759)\",shape=box];\n\"cntrl1760\"[label=\"Sequence(1760)\",shape=box];\n\"cntrl1761\"[label=\"Deallocate{}(1761)\"];\n\"cntrl1762\"[label=\"Sequence(1762)\",shape=box];\n\"cntrl1763\"[label=\"Deallocate{}(1763)\"];\n\"cntrl1764\"[label=\"Sequence(1764)\",shape=box];\n\"cntrl1765\"[label=\"Deallocate{}(1765)\"];\n\"cntrl1766\"[label=\"Sequence(1766)\",shape=box];\n\"cntrl1767\"[label=\"Barrier(1767)\"];\n\"cntrl1768\"[label=\"Sequence(1768)\",shape=box];\n\"cntrl1769\"[label=\"Deallocate{}(1769)\"];\n\"cntrl1770\"[label=\"Sequence(1770)\",shape=box];\n\"cntrl1771\"[label=\"Deallocate{}(1771)\"];\n\"cntrl1772\"[label=\"Sequence(1772)\",shape=box];\n\"cntrl1773\"[label=\"Deallocate{}(1773)\"];\n\"cntrl1774\"[label=\"Sequence(1774)\",shape=box];\n\"cntrl1775\"[label=\"Deallocate{}(1775)\"];\n\"cntrl1776\"[label=\"Sequence(1776)\",shape=box];\n\"cntrl1777\"[label=\"Deallocate{Tensor_4_stride_1_13}(1777)\"];\n\"cntrl1778\"[label=\"Sequence(1778)\",shape=box];\n\"cntrl1779\"[label=\"Deallocate{}(1779)\"];\n\"cntrl1780\"[label=\"Sequence(1780)\",shape=box];\n\"cntrl1781\"[label=\"Deallocate{}(1781)\"];\n\"cntrl1782\"[label=\"Sequence(1782)\",shape=box];\n\"cntrl1783\"[label=\"Deallocate{}(1783)\"];\n\"cntrl1784\"[label=\"Sequence(1784)\",shape=box];\n\"cntrl1785\"[label=\"Deallocate{}(1785)\"];\n\"cntrl1786\"[label=\"Sequence(1786)\",shape=box];\n\"cntrl1787\"[label=\"Deallocate{}(1787)\"];\n\"cntrl1788\"[label=\"Sequence(1788)\",shape=box];\n\"cntrl1789\"[label=\"Deallocate{}(1789)\"];\n\"cntrl1790\"[label=\"Sequence(1790)\",shape=box];\n\"cntrl1791\"[label=\"Deallocate{}(1791)\"];\n\"cntrl1792\"[label=\"Sequence(1792)\",shape=box];\n\"cntrl1793\"[label=\"Deallocate{}(1793)\"];\n\"cntrl1794\"[label=\"Sequence(1794)\",shape=box];\n\"cntrl1795\"[label=\"Deallocate{}(1795)\"];\n\"cntrl1796\"[label=\"Sequence(1796)\",shape=box];\n\"cntrl1797\"[label=\"Deallocate{}(1797)\"];\n\"cntrl1798\"[label=\"Sequence(1798)\",shape=box];\n\"cntrl1799\"[label=\"Deallocate{}(1799)\"];\n\"cntrl1800\"[label=\"Sequence(1800)\",shape=box];\n\"cntrl1801\"[label=\"Barrier(1801)\"];\n\"cntrl1802\"[label=\"Sequence(1802)\",shape=box];\n\"cntrl1803\"[label=\"Deallocate{}(1803)\"];\n\"cntrl1804\"[label=\"Sequence(1804)\",shape=box];\n\"cntrl1805\"[label=\"Deallocate{}(1805)\"];\n\"cntrl1806\"[label=\"Sequence(1806)\",shape=box];\n\"cntrl1807\"[label=\"Deallocate{}(1807)\"];\n\"cntrl1808\"[label=\"Sequence(1808)\",shape=box];\n\"cntrl1809\"[label=\"Deallocate{}(1809)\"];\n\"cntrl1810\"[label=\"Sequence(1810)\",shape=box];\n\"cntrl1811\"[label=\"Deallocate{}(1811)\"];\n\"cntrl1812\"[label=\"Sequence(1812)\",shape=box];\n\"cntrl1813\"[label=\"Deallocate{}(1813)\"];\n\"cntrl1814\"[label=\"Sequence(1814)\",shape=box];\n\"cntrl1815\"[label=\"Deallocate{}(1815)\"];\n\"cntrl1816\"[label=\"Sequence(1816)\",shape=box];\n\"cntrl1817\"[label=\"Deallocate{}(1817)\"];\n\"cntrl1818\"[label=\"Sequence(1818)\",shape=box];\n\"cntrl1819\"[label=\"Deallocate{}(1819)\"];\n\"cntrl1820\"[label=\"Sequence(1820)\",shape=box];\n\"cntrl1821\"[label=\"Deallocate{}(1821)\"];\n\"cntrl1822\"[label=\"Sequence(1822)\",shape=box];\n\"cntrl1823\"[label=\"Deallocate{}(1823)\"];\n\"cntrl1824\"[label=\"Sequence(1824)\",shape=box];\n\"cntrl1825\"[label=\"Deallocate{}(1825)\"];\n\"cntrl1826\"[label=\"Sequence(1826)\",shape=box];\n\"cntrl1827\"[label=\"Deallocate{}(1827)\"];\n\"cntrl1828\"[label=\"Sequence(1828)\",shape=box];\n\"cntrl1829\"[label=\"Deallocate{}(1829)\"];\n\"cntrl1830\"[label=\"Sequence(1830)\",shape=box];\n\"cntrl1831\"[label=\"Deallocate{}(1831)\"];\n\"cntrl1832\"[label=\"Sequence(1832)\",shape=box];\n\"cntrl1833\"[label=\"Deallocate{}(1833)\"];\n\"cntrl1834\"[label=\"Sequence(1834)\",shape=box];\n\"cntrl1835\"[label=\"Deallocate{}(1835)\"];\n\"cntrl1836\"[label=\"Sequence(1836)\",shape=box];\n\"cntrl1837\"[label=\"Deallocate{}(1837)\"];\n\"cntrl1838\"[label=\"Sequence(1838)\",shape=box];\n\"cntrl1839\"[label=\"Deallocate{}(1839)\"];\n\"cntrl1840\"[label=\"Sequence(1840)\",shape=box];\n\"cntrl1841\"[label=\"Deallocate{}(1841)\"];\n\"cntrl1842\"[label=\"Sequence(1842)\",shape=box];\n\"cntrl1843\"[label=\"Deallocate{}(1843)\"];\n\"cntrl1844\"[label=\"Sequence(1844)\",shape=box];\n\"cntrl1845\"[label=\"Deallocate{}(1845)\"];\n\"cntrl1846\"[label=\"Sequence(1846)\",shape=box];\n\"cntrl1847\"[label=\"Deallocate{}(1847)\"];\n\"cntrl1848\"[label=\"Sequence(1848)\",shape=box];\n\"cntrl1849\"[label=\"Deallocate{}(1849)\"];\n\"cntrl1850\"[label=\"Sequence(1850)\",shape=box];\n\"cntrl1851\"[label=\"Deallocate{}(1851)\"];\n\"cntrl1852\"[label=\"Sequence(1852)\",shape=box];\n\"cntrl1853\"[label=\"Deallocate{}(1853)\"];\n\"cntrl1854\"[label=\"Sequence(1854)\",shape=box];\n\"cntrl1855\"[label=\"Deallocate{}(1855)\"];\n\"cntrl1856\"[label=\"Sequence(1856)\",shape=box];\n\"cntrl1857\"[label=\"Deallocate{}(1857)\"];\n\"cntrl1858\"[label=\"Sequence(1858)\",shape=box];\n\"cntrl1859\"[label=\"Deallocate{}(1859)\"];\n\"cntrl1860\"[label=\"Sequence(1860)\",shape=box];\n\"cntrl1861\"[label=\"Deallocate{}(1861)\"];\n\"cntrl1862\"[label=\"Sequence(1862)\",shape=box];\n\"cntrl1863\"[label=\"Deallocate{}(1863)\"];\n\"cntrl1864\"[label=\"Sequence(1864)\",shape=box];\n\"cntrl1865\"[label=\"Deallocate{}(1865)\"];\n\"cntrl1866\"[label=\"Sequence(1866)\",shape=box];\n\"cntrl1867\"[label=\"Deallocate{}(1867)\"];\n\"cntrl1868\"[label=\"Sequence(1868)\",shape=box];\n\"cntrl1869\"[label=\"Deallocate{Tensor_15_stride_1_14, Tensor_15_extent_15, Tensor_15_pointer}(1869)\"];\n\"cntrl1870\"[label=\"Sequence(1870)\",shape=box];\n\"cntrl1871\"[label=\"Deallocate{}(1871)\"];\n\"cntrl1872\"[label=\"Sequence(1872)\",shape=box];\n\"cntrl1873\"[label=\"Deallocate{}(1873)\"];\n\"cntrl1874\"[label=\"Sequence(1874)\",shape=box];\n\"cntrl1875\"[label=\"Deallocate{}(1875)\"];\n\"cntrl1876\"[label=\"Sequence(1876)\",shape=box];\n\"cntrl1877\"[label=\"Deallocate{}(1877)\"];\n\"cntrl1878\"[label=\"Sequence(1878)\",shape=box];\n\"cntrl1879\"[label=\"Deallocate{}(1879)\"];\n\"cntrl1880\"[label=\"Sequence(1880)\",shape=box];\n\"cntrl1881\"[label=\"Deallocate{}(1881)\"];\n\"cntrl1882\"[label=\"Sequence(1882)\",shape=box];\n\"cntrl1883\"[label=\"Deallocate{}(1883)\"];\n\"cntrl1884\"[label=\"Sequence(1884)\",shape=box];\n\"cntrl1885\"[label=\"Deallocate{}(1885)\"];\n\"cntrl1886\"[label=\"Sequence(1886)\",shape=box];\n\"cntrl1887\"[label=\"Deallocate{}(1887)\"];\n\"cntrl1888\"[label=\"Sequence(1888)\",shape=box];\n\"cntrl1889\"[label=\"Deallocate{}(1889)\"];\n\"cntrl1890\"[label=\"Sequence(1890)\",shape=box];\n\"cntrl1891\"[label=\"Deallocate{}(1891)\"];\n\"cntrl1892\"[label=\"Sequence(1892)\",shape=box];\n\"cntrl1893\"[label=\"Deallocate{}(1893)\"];\n\"cntrl1894\"[label=\"Sequence(1894)\",shape=box];\n\"cntrl1895\"[label=\"Deallocate{}(1895)\"];\n\"cntrl1896\"[label=\"Sequence(1896)\",shape=box];\n\"cntrl1897\"[label=\"Deallocate{}(1897)\"];\n\"cntrl1898\"[label=\"Sequence(1898)\",shape=box];\n\"cntrl1899\"[label=\"Deallocate{}(1899)\"];\n\"cntrl1900\"[label=\"Sequence(1900)\",shape=box];\n\"cntrl1901\"[label=\"Deallocate{}(1901)\"];\n\"cntrl1902\"[label=\"Sequence(1902)\",shape=box];\n\"cntrl1903\"[label=\"Deallocate{}(1903)\"];\n\"cntrl1904\"[label=\"Sequence(1904)\",shape=box];\n\"cntrl1905\"[label=\"Deallocate{}(1905)\"];\n\"cntrl1906\"[label=\"Sequence(1906)\",shape=box];\n\"cntrl1907\"[label=\"Deallocate{}(1907)\"];\n\"cntrl1908\"[label=\"Sequence(1908)\",shape=box];\n\"cntrl1909\"[label=\"Deallocate{}(1909)\"];\n\"cntrl1910\"[label=\"Sequence(1910)\",shape=box];\n\"cntrl1911\"[label=\"Deallocate{}(1911)\"];\n\"cntrl1912\"[label=\"Sequence(1912)\",shape=box];\n\"cntrl1913\"[label=\"Deallocate{}(1913)\"];\n\"cntrl1914\"[label=\"Sequence(1914)\",shape=box];\n\"cntrl1915\"[label=\"Sequence(1915)\",shape=box];\n\"cntrl1916\"[label=\"Sequence(1916)\",shape=box];\n\"cntrl1917\"[label=\"Sequence(1917)\",shape=box];\n\"cntrl1918\"[label=\"Deallocate{}(1918)\"];\n\"cntrl1919\"[label=\"Sequence(1919)\",shape=box];\n\"cntrl1920\"[label=\"Sequence(1920)\",shape=box];\n\"cntrl1921\"[label=\"Sequence(1921)\",shape=box];\n\"cntrl1922\"[label=\"Sequence(1922)\",shape=box];\n\"cntrl1923\"[label=\"Sequence(1923)\",shape=box];\n\"cntrl1924\"[label=\"Sequence(1924)\",shape=box];\n\"cntrl1925\"[label=\"Sequence(1925)\",shape=box];\n\"cntrl1926\"[label=\"Sequence(1926)\",shape=box];\n\"cntrl1927\"[label=\"Sequence(1927)\",shape=box];\n\"cntrl1928\"[label=\"Sequence(1928)\",shape=box];\n\"cntrl1929\"[label=\"Sequence(1929)\",shape=box];\n\"cntrl1930\"[label=\"Sequence(1930)\",shape=box];\n\"cntrl1931\"[label=\"Sequence(1931)\",shape=box];\n\"cntrl1932\"[label=\"Sequence(1932)\",shape=box];\n\"cntrl1933\"[label=\"Sequence(1933)\",shape=box];\n\"cntrl1934\"[label=\"Sequence(1934)\",shape=box];\n\"cntrl1935\"[label=\"Sequence(1935)\",shape=box];\n\"cntrl1936\"[label=\"Sequence(1936)\",shape=box];\n\"cntrl1937\"[label=\"Sequence(1937)\",shape=box];\n\"cntrl1938\"[label=\"Sequence(1938)\",shape=box];\n\"cntrl1939\"[label=\"Sequence(1939)\",shape=box];\n\"cntrl1940\"[label=\"Sequence(1940)\",shape=box];\n\"cntrl1941\"[label=\"Sequence(1941)\",shape=box];\n\"cntrl1942\"[label=\"Sequence(1942)\",shape=box];\n\"cntrl1943\"[label=\"Sequence(1943)\",shape=box];\n\"cntrl1944\"[label=\"Sequence(1944)\",shape=box];\n\"cntrl1945\"[label=\"Sequence(1945)\",shape=box];\n\"cntrl1946\"[label=\"Sequence(1946)\",shape=box];\n\"cntrl1947\"[label=\"Sequence(1947)\",shape=box];\n\"cntrl1948\"[label=\"Sequence(1948)\",shape=box];\n\"cntrl1949\"[label=\"Sequence(1949)\",shape=box];\n\"cntrl1950\"[label=\"Sequence(1950)\",shape=box];\n\"cntrl1951\"[label=\"Sequence(1951)\",shape=box];\n\"cntrl1952\"[label=\"Sequence(1952)\",shape=box];\n\"cntrl1953\"[label=\"Sequence(1953)\",shape=box];\n\"cntrl1954\"[label=\"Sequence(1954)\",shape=box];\n\"cntrl1955\"[label=\"Sequence(1955)\",shape=box];\n\"cntrl1956\"[label=\"Sequence(1956)\",shape=box];\n\"cntrl1957\"[label=\"Sequence(1957)\",shape=box];\n\"cntrl1958\"[label=\"Sequence(1958)\",shape=box];\n\"cntrl1959\"[label=\"Sequence(1959)\",shape=box];\n\"cntrl1960\"[label=\"Sequence(1960)\",shape=box];\n\"cntrl1961\"[label=\"Sequence(1961)\",shape=box];\n\"cntrl1962\"[label=\"Sequence(1962)\",shape=box];\n\"cntrl1963\"[label=\"Sequence(1963)\",shape=box];\n\"cntrl1964\"[label=\"Sequence(1964)\",shape=box];\n\"cntrl1965\"[label=\"Sequence(1965)\",shape=box];\n\"cntrl1966\"[label=\"Sequence(1966)\",shape=box];\n\"cntrl1967\"[label=\"Sequence(1967)\",shape=box];\n\"cntrl1968\"[label=\"Sequence(1968)\",shape=box];\n\"cntrl1969\"[label=\"Sequence(1969)\",shape=box];\n\"cntrl1970\"[label=\"Sequence(1970)\",shape=box];\n\"cntrl1971\"[label=\"Sequence(1971)\",shape=box];\n\"cntrl1972\"[label=\"Sequence(1972)\",shape=box];\n\"cntrl1973\"[label=\"Sequence(1973)\",shape=box];\n\"cntrl1974\"[label=\"Sequence(1974)\",shape=box];\n\"cntrl1975\"[label=\"Sequence(1975)\",shape=box];\n\"cntrl1976\"[label=\"Sequence(1976)\",shape=box];\n\"cntrl1977\"[label=\"Sequence(1977)\",shape=box];\n\"cntrl1978\"[label=\"Sequence(1978)\",shape=box];\n\"cntrl1979\"[label=\"Sequence(1979)\",shape=box];\n\"cntrl1980\"[label=\"Sequence(1980)\",shape=box];\n\"cntrl1981\"[label=\"Sequence(1981)\",shape=box];\n\"cntrl1982\"[label=\"Sequence(1982)\",shape=box];\n\"cntrl1983\"[label=\"Sequence(1983)\",shape=box];\n\"cntrl1984\"[label=\"Sequence(1984)\",shape=box];\n\"cntrl1985\"[label=\"Sequence(1985)\",shape=box];\n\"cntrl1986\"[label=\"Sequence(1986)\",shape=box];\n\"cntrl1987\"[label=\"Sequence(1987)\",shape=box];\n\"cntrl1988\"[label=\"Sequence(1988)\",shape=box];\n\"cntrl1989\"[label=\"Sequence(1989)\",shape=box];\n\"cntrl1990\"[label=\"Sequence(1990)\",shape=box];\n\"cntrl1991\"[label=\"Sequence(1991)\",shape=box];\n\"cntrl1992\"[label=\"Sequence(1992)\",shape=box];\n\"cntrl1993\"[label=\"Sequence(1993)\",shape=box];\n\"cntrl1994\"[label=\"Sequence(1994)\",shape=box];\n\"cntrl1995\"[label=\"Sequence(1995)\",shape=box];\n\"cntrl1996\"[label=\"Sequence(1996)\",shape=box];\n\"cntrl1997\"[label=\"Deallocate{user_Float_Value_8}(1997)\"];\n\"cntrl1998\"[label=\"Sequence(1998)\",shape=box];\n\"cntrl1999\"[label=\"Deallocate{user_Float_Value_6}(1999)\"];\n\"cntrl2000\"[label=\"Sequence(2000)\",shape=box];\n\"cntrl2003\"[label=\"Deallocate{Tensor_2_pointer, Tensor_0_pointer, Tensor_0_extent_0, Tensor_2_stride_1_12, Tensor_0_stride_0_9, Tensor_2_extent_2, Tensor_0_size_1_10}(2003)\"];\n\"cntrl2004\"[label=\"Sequence(2004)\",shape=box];\n\"cntrl2007\"[label=\"Deallocate{Tensor_4_pointer, Tensor_4_extent_4}(2007)\"];\n\"cntrl2008\"[label=\"Sequence(2008)\",shape=box];\n\"cntrl2009\"[label=\"Sequence(2009)\",shape=box];\n\"cntrl2010\"[label=\"Sequence(2010)\",shape=box];\n\"cntrl2011\"[label=\"Sequence(2011)\",shape=box];\n\"cntrl1\" -> \"cntrl1242\"\n\"cntrl1\" -> \"cntrl1294\"\n\"cntrl1\" -> \"cntrl1367\"\n\"cntrl1\" -> \"cntrl1406\"\n\"cntrl1\" -> \"cntrl1445\"\n\"cntrl1\" -> \"cntrl1484\"\n\"cntrl1\" -> \"cntrl1523\"\n\"cntrl1\" -> \"cntrl1562\"\n\"cntrl2\" -> \"cntrl1998\"\n\"cntrl24\" -> \"cntrl2000\"\n\"cntrl29\" -> \"cntrl668\"\n\"cntrl35\" -> \"cntrl1762\"\n\"cntrl37\" -> \"cntrl1764\"\n\"cntrl39\" -> \"cntrl42\"\n\"cntrl39\" -> \"cntrl810\"\n\"cntrl39\" -> \"cntrl816\"\n\"cntrl39\" -> \"cntrl1586\"\n\"cntrl39\" -> \"cntrl1734\"\n\"cntrl39\" -> \"cntrl1766\"\n\"cntrl42\" -> \"cntrl40\"\n\"cntrl44\" -> \"cntrl1075\"\n\"cntrl47\" -> \"cntrl50\"\n\"cntrl47\" -> \"cntrl955\"\n\"cntrl50\" -> \"cntrl49\"\n\"cntrl52\" -> \"cntrl55\"\n\"cntrl52\" -> \"cntrl947\"\n\"cntrl55\" -> \"cntrl54\"\n\"cntrl57\" -> \"cntrl1629\"\n\"cntrl57\" -> \"cntrl1660\"\n\"cntrl58\" -> \"cntrl61\"\n\"cntrl58\" -> \"cntrl956\"\n\"cntrl61\" -> \"cntrl60\"\n\"cntrl62\" -> \"cntrl65\"\n\"cntrl62\" -> \"cntrl948\"\n\"cntrl65\" -> \"cntrl64\"\n\"cntrl66\" -> \"cntrl1630\"\n\"cntrl66\" -> \"cntrl1668\"\n\"cntrl67\" -> \"cntrl70\"\n\"cntrl67\" -> \"cntrl957\"\n\"cntrl70\" -> \"cntrl69\"\n\"cntrl71\" -> \"cntrl74\"\n\"cntrl71\" -> \"cntrl949\"\n\"cntrl74\" -> \"cntrl73\"\n\"cntrl75\" -> \"cntrl1631\"\n\"cntrl75\" -> \"cntrl1670\"\n\"cntrl76\" -> \"cntrl79\"\n\"cntrl76\" -> \"cntrl958\"\n\"cntrl79\" -> \"cntrl78\"\n\"cntrl80\" -> \"cntrl83\"\n\"cntrl80\" -> \"cntrl950\"\n\"cntrl83\" -> \"cntrl82\"\n\"cntrl84\" -> \"cntrl1632\"\n\"cntrl84\" -> \"cntrl1672\"\n\"cntrl85\" -> \"cntrl88\"\n\"cntrl85\" -> \"cntrl959\"\n\"cntrl88\" -> \"cntrl87\"\n\"cntrl89\" -> \"cntrl92\"\n\"cntrl89\" -> \"cntrl951\"\n\"cntrl92\" -> \"cntrl91\"\n\"cntrl93\" -> \"cntrl1633\"\n\"cntrl93\" -> \"cntrl1674\"\n\"cntrl94\" -> \"cntrl97\"\n\"cntrl94\" -> \"cntrl960\"\n\"cntrl97\" -> \"cntrl96\"\n\"cntrl98\" -> \"cntrl101\"\n\"cntrl98\" -> \"cntrl952\"\n\"cntrl101\" -> \"cntrl100\"\n\"cntrl102\" -> \"cntrl1634\"\n\"cntrl103\" -> \"cntrl106\"\n\"cntrl103\" -> \"cntrl961\"\n\"cntrl106\" -> \"cntrl105\"\n\"cntrl107\" -> \"cntrl110\"\n\"cntrl107\" -> \"cntrl953\"\n\"cntrl110\" -> \"cntrl109\"\n\"cntrl111\" -> \"cntrl1635\"\n\"cntrl112\" -> \"cntrl115\"\n\"cntrl112\" -> \"cntrl962\"\n\"cntrl115\" -> \"cntrl114\"\n\"cntrl116\" -> \"cntrl119\"\n\"cntrl116\" -> \"cntrl954\"\n\"cntrl119\" -> \"cntrl118\"\n\"cntrl120\" -> \"cntrl844\"\n\"cntrl177\" -> \"cntrl679\"\n\"cntrl177\" -> \"cntrl685\"\n\"cntrl177\" -> \"cntrl1770\"\n\"cntrl185\" -> \"cntrl203\"\n\"cntrl185\" -> \"cntrl1182\"\n\"cntrl186\" -> \"cntrl194\"\n\"cntrl187\" -> \"cntrl1772\"\n\"cntrl188\" -> \"cntrl1774\"\n\"cntrl189\" -> \"cntrl1776\"\n\"cntrl190\" -> \"cntrl1778\"\n\"cntrl191\" -> \"cntrl1780\"\n\"cntrl194\" -> \"cntrl187\"\n\"cntrl203\" -> \"cntrl186\"\n\"cntrl217\" -> \"cntrl220\"\n\"cntrl217\" -> \"cntrl1595\"\n\"cntrl217\" -> \"cntrl1727\"\n\"cntrl217\" -> \"cntrl1782\"\n\"cntrl220\" -> \"cntrl218\"\n\"cntrl224\" -> \"cntrl273\"\n\"cntrl224\" -> \"cntrl1740\"\n\"cntrl226\" -> \"cntrl275\"\n\"cntrl226\" -> \"cntrl276\"\n\"cntrl228\" -> \"cntrl1784\"\n\"cntrl229\" -> \"cntrl278\"\n\"cntrl229\" -> \"cntrl279\"\n\"cntrl231\" -> \"cntrl280\"\n\"cntrl231\" -> \"cntrl281\"\n\"cntrl233\" -> \"cntrl1786\"\n\"cntrl234\" -> \"cntrl283\"\n\"cntrl234\" -> \"cntrl284\"\n\"cntrl236\" -> \"cntrl285\"\n\"cntrl236\" -> \"cntrl286\"\n\"cntrl238\" -> \"cntrl1788\"\n\"cntrl239\" -> \"cntrl288\"\n\"cntrl239\" -> \"cntrl289\"\n\"cntrl241\" -> \"cntrl290\"\n\"cntrl241\" -> \"cntrl291\"\n\"cntrl243\" -> \"cntrl1790\"\n\"cntrl244\" -> \"cntrl293\"\n\"cntrl244\" -> \"cntrl294\"\n\"cntrl246\" -> \"cntrl295\"\n\"cntrl246\" -> \"cntrl296\"\n\"cntrl248\" -> \"cntrl1792\"\n\"cntrl249\" -> \"cntrl298\"\n\"cntrl249\" -> \"cntrl299\"\n\"cntrl251\" -> \"cntrl300\"\n\"cntrl251\" -> \"cntrl301\"\n\"cntrl253\" -> \"cntrl1794\"\n\"cntrl254\" -> \"cntrl303\"\n\"cntrl254\" -> \"cntrl304\"\n\"cntrl256\" -> \"cntrl305\"\n\"cntrl256\" -> \"cntrl306\"\n\"cntrl258\" -> \"cntrl1796\"\n\"cntrl259\" -> \"cntrl308\"\n\"cntrl259\" -> \"cntrl309\"\n\"cntrl261\" -> \"cntrl310\"\n\"cntrl261\" -> \"cntrl311\"\n\"cntrl263\" -> \"cntrl1798\"\n\"cntrl273\" -> \"cntrl225\"\n\"cntrl275\" -> \"cntrl227\"\n\"cntrl276\" -> \"cntrl228\"\n\"cntrl278\" -> \"cntrl230\"\n\"cntrl279\" -> \"cntrl231\"\n\"cntrl280\" -> \"cntrl232\"\n\"cntrl281\" -> \"cntrl233\"\n\"cntrl283\" -> \"cntrl235\"\n\"cntrl284\" -> \"cntrl236\"\n\"cntrl285\" -> \"cntrl237\"\n\"cntrl286\" -> \"cntrl238\"\n\"cntrl288\" -> \"cntrl240\"\n\"cntrl289\" -> \"cntrl241\"\n\"cntrl290\" -> \"cntrl242\"\n\"cntrl291\" -> \"cntrl243\"\n\"cntrl293\" -> \"cntrl245\"\n\"cntrl294\" -> \"cntrl246\"\n\"cntrl295\" -> \"cntrl247\"\n\"cntrl296\" -> \"cntrl248\"\n\"cntrl298\" -> \"cntrl250\"\n\"cntrl299\" -> \"cntrl251\"\n\"cntrl300\" -> \"cntrl252\"\n\"cntrl301\" -> \"cntrl253\"\n\"cntrl303\" -> \"cntrl255\"\n\"cntrl304\" -> \"cntrl256\"\n\"cntrl305\" -> \"cntrl257\"\n\"cntrl306\" -> \"cntrl258\"\n\"cntrl308\" -> \"cntrl260\"\n\"cntrl309\" -> \"cntrl261\"\n\"cntrl310\" -> \"cntrl262\"\n\"cntrl311\" -> \"cntrl263\"\n\"cntrl313\" -> \"cntrl315\"\n\"cntrl313\" -> \"cntrl1800\"\n\"cntrl313\" -> \"cntrl2004\"\n\"cntrl314\" -> \"cntrl1052\"\n\"cntrl315\" -> \"cntrl314\"\n\"cntrl318\" -> \"cntrl982\"\n\"cntrl318\" -> \"cntrl984\"\n\"cntrl318\" -> \"cntrl1737\"\n\"cntrl323\" -> \"cntrl988\"\n\"cntrl323\" -> \"cntrl990\"\n\"cntrl323\" -> \"cntrl1730\"\n\"cntrl330\" -> \"cntrl379\"\n\"cntrl330\" -> \"cntrl829\"\n\"cntrl332\" -> \"cntrl381\"\n\"cntrl332\" -> \"cntrl821\"\n\"cntrl334\" -> \"cntrl1804\"\n\"cntrl335\" -> \"cntrl384\"\n\"cntrl335\" -> \"cntrl830\"\n\"cntrl337\" -> \"cntrl386\"\n\"cntrl337\" -> \"cntrl822\"\n\"cntrl339\" -> \"cntrl1806\"\n\"cntrl340\" -> \"cntrl389\"\n\"cntrl340\" -> \"cntrl831\"\n\"cntrl342\" -> \"cntrl391\"\n\"cntrl342\" -> \"cntrl823\"\n\"cntrl344\" -> \"cntrl1808\"\n\"cntrl345\" -> \"cntrl394\"\n\"cntrl345\" -> \"cntrl832\"\n\"cntrl347\" -> \"cntrl396\"\n\"cntrl347\" -> \"cntrl824\"\n\"cntrl349\" -> \"cntrl1810\"\n\"cntrl350\" -> \"cntrl399\"\n\"cntrl350\" -> \"cntrl833\"\n\"cntrl352\" -> \"cntrl401\"\n\"cntrl352\" -> \"cntrl825\"\n\"cntrl354\" -> \"cntrl1812\"\n\"cntrl355\" -> \"cntrl404\"\n\"cntrl355\" -> \"cntrl834\"\n\"cntrl357\" -> \"cntrl406\"\n\"cntrl357\" -> \"cntrl826\"\n\"cntrl359\" -> \"cntrl1814\"\n\"cntrl360\" -> \"cntrl409\"\n\"cntrl360\" -> \"cntrl835\"\n\"cntrl362\" -> \"cntrl411\"\n\"cntrl362\" -> \"cntrl827\"\n\"cntrl364\" -> \"cntrl1816\"\n\"cntrl365\" -> \"cntrl414\"\n\"cntrl365\" -> \"cntrl1818\"\n\"cntrl367\" -> \"cntrl416\"\n\"cntrl367\" -> \"cntrl1820\"\n\"cntrl369\" -> \"cntrl1822\"\n\"cntrl379\" -> \"cntrl331\"\n\"cntrl381\" -> \"cntrl333\"\n\"cntrl384\" -> \"cntrl336\"\n\"cntrl386\" -> \"cntrl338\"\n\"cntrl389\" -> \"cntrl341\"\n\"cntrl391\" -> \"cntrl343\"\n\"cntrl394\" -> \"cntrl346\"\n\"cntrl396\" -> \"cntrl348\"\n\"cntrl399\" -> \"cntrl351\"\n\"cntrl401\" -> \"cntrl353\"\n\"cntrl404\" -> \"cntrl356\"\n\"cntrl406\" -> \"cntrl358\"\n\"cntrl409\" -> \"cntrl361\"\n\"cntrl411\" -> \"cntrl363\"\n\"cntrl414\" -> \"cntrl366\"\n\"cntrl416\" -> \"cntrl368\"\n\"cntrl420\" -> \"cntrl469\"\n\"cntrl420\" -> \"cntrl871\"\n\"cntrl422\" -> \"cntrl471\"\n\"cntrl422\" -> \"cntrl863\"\n\"cntrl424\" -> \"cntrl1824\"\n\"cntrl425\" -> \"cntrl474\"\n\"cntrl425\" -> \"cntrl872\"\n\"cntrl427\" -> \"cntrl476\"\n\"cntrl427\" -> \"cntrl864\"\n\"cntrl429\" -> \"cntrl1826\"\n\"cntrl430\" -> \"cntrl479\"\n\"cntrl430\" -> \"cntrl873\"\n\"cntrl432\" -> \"cntrl481\"\n\"cntrl432\" -> \"cntrl865\"\n\"cntrl434\" -> \"cntrl1828\"\n\"cntrl435\" -> \"cntrl484\"\n\"cntrl435\" -> \"cntrl874\"\n\"cntrl437\" -> \"cntrl486\"\n\"cntrl437\" -> \"cntrl866\"\n\"cntrl439\" -> \"cntrl1830\"\n\"cntrl440\" -> \"cntrl489\"\n\"cntrl440\" -> \"cntrl875\"\n\"cntrl442\" -> \"cntrl491\"\n\"cntrl442\" -> \"cntrl867\"\n\"cntrl444\" -> \"cntrl1832\"\n\"cntrl445\" -> \"cntrl494\"\n\"cntrl445\" -> \"cntrl876\"\n\"cntrl447\" -> \"cntrl496\"\n\"cntrl447\" -> \"cntrl868\"\n\"cntrl449\" -> \"cntrl1834\"\n\"cntrl450\" -> \"cntrl499\"\n\"cntrl450\" -> \"cntrl877\"\n\"cntrl452\" -> \"cntrl501\"\n\"cntrl452\" -> \"cntrl869\"\n\"cntrl454\" -> \"cntrl1836\"\n\"cntrl455\" -> \"cntrl504\"\n\"cntrl455\" -> \"cntrl1838\"\n\"cntrl457\" -> \"cntrl506\"\n\"cntrl457\" -> \"cntrl1840\"\n\"cntrl459\" -> \"cntrl1842\"\n\"cntrl469\" -> \"cntrl421\"\n\"cntrl471\" -> \"cntrl423\"\n\"cntrl474\" -> \"cntrl426\"\n\"cntrl476\" -> \"cntrl428\"\n\"cntrl479\" -> \"cntrl431\"\n\"cntrl481\" -> \"cntrl433\"\n\"cntrl484\" -> \"cntrl436\"\n\"cntrl486\" -> \"cntrl438\"\n\"cntrl489\" -> \"cntrl441\"\n\"cntrl491\" -> \"cntrl443\"\n\"cntrl494\" -> \"cntrl446\"\n\"cntrl496\" -> \"cntrl448\"\n\"cntrl499\" -> \"cntrl451\"\n\"cntrl501\" -> \"cntrl453\"\n\"cntrl504\" -> \"cntrl456\"\n\"cntrl506\" -> \"cntrl458\"\n\"cntrl510\" -> \"cntrl559\"\n\"cntrl510\" -> \"cntrl913\"\n\"cntrl512\" -> \"cntrl561\"\n\"cntrl512\" -> \"cntrl905\"\n\"cntrl514\" -> \"cntrl1844\"\n\"cntrl515\" -> \"cntrl564\"\n\"cntrl515\" -> \"cntrl914\"\n\"cntrl517\" -> \"cntrl566\"\n\"cntrl517\" -> \"cntrl906\"\n\"cntrl519\" -> \"cntrl1846\"\n\"cntrl520\" -> \"cntrl569\"\n\"cntrl520\" -> \"cntrl915\"\n\"cntrl522\" -> \"cntrl571\"\n\"cntrl522\" -> \"cntrl907\"\n\"cntrl524\" -> \"cntrl1848\"\n\"cntrl525\" -> \"cntrl574\"\n\"cntrl525\" -> \"cntrl916\"\n\"cntrl527\" -> \"cntrl576\"\n\"cntrl527\" -> \"cntrl908\"\n\"cntrl529\" -> \"cntrl1850\"\n\"cntrl530\" -> \"cntrl579\"\n\"cntrl530\" -> \"cntrl917\"\n\"cntrl532\" -> \"cntrl581\"\n\"cntrl532\" -> \"cntrl909\"\n\"cntrl534\" -> \"cntrl1852\"\n\"cntrl535\" -> \"cntrl584\"\n\"cntrl535\" -> \"cntrl918\"\n\"cntrl537\" -> \"cntrl586\"\n\"cntrl537\" -> \"cntrl910\"\n\"cntrl539\" -> \"cntrl1854\"\n\"cntrl540\" -> \"cntrl589\"\n\"cntrl540\" -> \"cntrl919\"\n\"cntrl542\" -> \"cntrl591\"\n\"cntrl542\" -> \"cntrl911\"\n\"cntrl544\" -> \"cntrl1856\"\n\"cntrl545\" -> \"cntrl594\"\n\"cntrl545\" -> \"cntrl1858\"\n\"cntrl547\" -> \"cntrl596\"\n\"cntrl547\" -> \"cntrl1860\"\n\"cntrl549\" -> \"cntrl1862\"\n\"cntrl559\" -> \"cntrl511\"\n\"cntrl561\" -> \"cntrl513\"\n\"cntrl564\" -> \"cntrl516\"\n\"cntrl566\" -> \"cntrl518\"\n\"cntrl569\" -> \"cntrl521\"\n\"cntrl571\" -> \"cntrl523\"\n\"cntrl574\" -> \"cntrl526\"\n\"cntrl576\" -> \"cntrl528\"\n\"cntrl579\" -> \"cntrl531\"\n\"cntrl581\" -> \"cntrl533\"\n\"cntrl584\" -> \"cntrl536\"\n\"cntrl586\" -> \"cntrl538\"\n\"cntrl589\" -> \"cntrl541\"\n\"cntrl591\" -> \"cntrl543\"\n\"cntrl594\" -> \"cntrl546\"\n\"cntrl596\" -> \"cntrl548\"\n\"cntrl599\" -> \"cntrl972\"\n\"cntrl599\" -> \"cntrl1001\"\n\"cntrl604\" -> \"cntrl977\"\n\"cntrl604\" -> \"cntrl1724\"\n\"cntrl610\" -> \"cntrl994\"\n\"cntrl610\" -> \"cntrl1011\"\n\"cntrl615\" -> \"cntrl999\"\n\"cntrl615\" -> \"cntrl1744\"\n\"cntrl624\" -> \"cntrl1004\"\n\"cntrl624\" -> \"cntrl1021\"\n\"cntrl629\" -> \"cntrl1009\"\n\"cntrl629\" -> \"cntrl1750\"\n\"cntrl638\" -> \"cntrl1014\"\n\"cntrl638\" -> \"cntrl1864\"\n\"cntrl643\" -> \"cntrl1019\"\n\"cntrl643\" -> \"cntrl1866\"\n\"cntrl668\" -> \"cntrl35\"\n\"cntrl670\" -> \"cntrl676\"\n\"cntrl670\" -> \"cntrl1868\"\n\"cntrl675\" -> \"cntrl677\"\n\"cntrl676\" -> \"cntrl675\"\n\"cntrl677\" -> \"cntrl44\"\n\"cntrl678\" -> \"cntrl682\"\n\"cntrl679\" -> \"cntrl678\"\n\"cntrl681\" -> \"cntrl683\"\n\"cntrl682\" -> \"cntrl681\"\n\"cntrl683\" -> \"cntrl29\"\n\"cntrl684\" -> \"cntrl688\"\n\"cntrl684\" -> \"cntrl1870\"\n\"cntrl685\" -> \"cntrl684\"\n\"cntrl687\" -> \"cntrl689\"\n\"cntrl688\" -> \"cntrl687\"\n\"cntrl689\" -> \"cntrl185\"\n\"cntrl690\" -> \"cntrl722\"\n\"cntrl693\" -> \"cntrl781\"\n\"cntrl694\" -> \"cntrl1200\"\n\"cntrl696\" -> \"cntrl723\"\n\"cntrl696\" -> \"cntrl1280\"\n\"cntrl699\" -> \"cntrl724\"\n\"cntrl699\" -> \"cntrl1228\"\n\"cntrl702\" -> \"cntrl725\"\n\"cntrl702\" -> \"cntrl1392\"\n\"cntrl705\" -> \"cntrl726\"\n\"cntrl705\" -> \"cntrl1353\"\n\"cntrl708\" -> \"cntrl727\"\n\"cntrl708\" -> \"cntrl1470\"\n\"cntrl711\" -> \"cntrl728\"\n\"cntrl711\" -> \"cntrl1431\"\n\"cntrl714\" -> \"cntrl1548\"\n\"cntrl714\" -> \"cntrl1872\"\n\"cntrl717\" -> \"cntrl1509\"\n\"cntrl717\" -> \"cntrl1874\"\n\"cntrl722\" -> \"cntrl696\"\n\"cntrl723\" -> \"cntrl699\"\n\"cntrl724\" -> \"cntrl702\"\n\"cntrl725\" -> \"cntrl705\"\n\"cntrl726\" -> \"cntrl708\"\n\"cntrl727\" -> \"cntrl711\"\n\"cntrl728\" -> \"cntrl714\"\n\"cntrl733\" -> \"cntrl735\"\n\"cntrl733\" -> \"cntrl790\"\n\"cntrl735\" -> \"cntrl734\"\n\"cntrl736\" -> \"cntrl738\"\n\"cntrl736\" -> \"cntrl791\"\n\"cntrl738\" -> \"cntrl737\"\n\"cntrl739\" -> \"cntrl741\"\n\"cntrl739\" -> \"cntrl792\"\n\"cntrl741\" -> \"cntrl740\"\n\"cntrl742\" -> \"cntrl744\"\n\"cntrl742\" -> \"cntrl793\"\n\"cntrl744\" -> \"cntrl743\"\n\"cntrl745\" -> \"cntrl747\"\n\"cntrl745\" -> \"cntrl794\"\n\"cntrl747\" -> \"cntrl746\"\n\"cntrl748\" -> \"cntrl750\"\n\"cntrl748\" -> \"cntrl795\"\n\"cntrl750\" -> \"cntrl749\"\n\"cntrl751\" -> \"cntrl753\"\n\"cntrl751\" -> \"cntrl796\"\n\"cntrl753\" -> \"cntrl752\"\n\"cntrl754\" -> \"cntrl756\"\n\"cntrl754\" -> \"cntrl797\"\n\"cntrl756\" -> \"cntrl755\"\n\"cntrl757\" -> \"cntrl759\"\n\"cntrl757\" -> \"cntrl782\"\n\"cntrl759\" -> \"cntrl758\"\n\"cntrl760\" -> \"cntrl762\"\n\"cntrl760\" -> \"cntrl783\"\n\"cntrl762\" -> \"cntrl761\"\n\"cntrl763\" -> \"cntrl765\"\n\"cntrl763\" -> \"cntrl784\"\n\"cntrl765\" -> \"cntrl764\"\n\"cntrl766\" -> \"cntrl768\"\n\"cntrl766\" -> \"cntrl785\"\n\"cntrl768\" -> \"cntrl767\"\n\"cntrl769\" -> \"cntrl771\"\n\"cntrl769\" -> \"cntrl786\"\n\"cntrl771\" -> \"cntrl770\"\n\"cntrl772\" -> \"cntrl774\"\n\"cntrl772\" -> \"cntrl787\"\n\"cntrl774\" -> \"cntrl773\"\n\"cntrl775\" -> \"cntrl777\"\n\"cntrl775\" -> \"cntrl788\"\n\"cntrl777\" -> \"cntrl776\"\n\"cntrl778\" -> \"cntrl780\"\n\"cntrl778\" -> \"cntrl789\"\n\"cntrl780\" -> \"cntrl779\"\n\"cntrl781\" -> \"cntrl757\"\n\"cntrl782\" -> \"cntrl760\"\n\"cntrl783\" -> \"cntrl763\"\n\"cntrl784\" -> \"cntrl766\"\n\"cntrl785\" -> \"cntrl769\"\n\"cntrl786\" -> \"cntrl772\"\n\"cntrl787\" -> \"cntrl775\"\n\"cntrl788\" -> \"cntrl778\"\n\"cntrl789\" -> \"cntrl733\"\n\"cntrl790\" -> \"cntrl736\"\n\"cntrl791\" -> \"cntrl739\"\n\"cntrl792\" -> \"cntrl742\"\n\"cntrl793\" -> \"cntrl745\"\n\"cntrl794\" -> \"cntrl748\"\n\"cntrl795\" -> \"cntrl751\"\n\"cntrl796\" -> \"cntrl754\"\n\"cntrl797\" -> \"cntrl694\"\n\"cntrl799\" -> \"cntrl845\"\n\"cntrl799\" -> \"cntrl858\"\n\"cntrl799\" -> \"cntrl1747\"\n\"cntrl800\" -> \"cntrl887\"\n\"cntrl800\" -> \"cntrl900\"\n\"cntrl800\" -> \"cntrl1753\"\n\"cntrl801\" -> \"cntrl929\"\n\"cntrl801\" -> \"cntrl942\"\n\"cntrl801\" -> \"cntrl1759\"\n\"cntrl810\" -> \"cntrl57\"\n\"cntrl811\" -> \"cntrl820\"\n\"cntrl816\" -> \"cntrl811\"\n\"cntrl820\" -> \"cntrl332\"\n\"cntrl821\" -> \"cntrl337\"\n\"cntrl822\" -> \"cntrl342\"\n\"cntrl823\" -> \"cntrl347\"\n\"cntrl824\" -> \"cntrl352\"\n\"cntrl825\" -> \"cntrl357\"\n\"cntrl826\" -> \"cntrl362\"\n\"cntrl827\" -> \"cntrl367\"\n\"cntrl829\" -> \"cntrl335\"\n\"cntrl830\" -> \"cntrl340\"\n\"cntrl831\" -> \"cntrl345\"\n\"cntrl832\" -> \"cntrl350\"\n\"cntrl833\" -> \"cntrl355\"\n\"cntrl834\" -> \"cntrl360\"\n\"cntrl835\" -> \"cntrl365\"\n\"cntrl844\" -> \"cntrl799\"\n\"cntrl845\" -> \"cntrl334\"\n\"cntrl853\" -> \"cntrl862\"\n\"cntrl858\" -> \"cntrl853\"\n\"cntrl862\" -> \"cntrl422\"\n\"cntrl863\" -> \"cntrl427\"\n\"cntrl864\" -> \"cntrl432\"\n\"cntrl865\" -> \"cntrl437\"\n\"cntrl866\" -> \"cntrl442\"\n\"cntrl867\" -> \"cntrl447\"\n\"cntrl868\" -> \"cntrl452\"\n\"cntrl869\" -> \"cntrl457\"\n\"cntrl871\" -> \"cntrl425\"\n\"cntrl872\" -> \"cntrl430\"\n\"cntrl873\" -> \"cntrl435\"\n\"cntrl874\" -> \"cntrl440\"\n\"cntrl875\" -> \"cntrl445\"\n\"cntrl876\" -> \"cntrl450\"\n\"cntrl877\" -> \"cntrl455\"\n\"cntrl887\" -> \"cntrl424\"\n\"cntrl895\" -> \"cntrl904\"\n\"cntrl900\" -> \"cntrl895\"\n\"cntrl904\" -> \"cntrl512\"\n\"cntrl905\" -> \"cntrl517\"\n\"cntrl906\" -> \"cntrl522\"\n\"cntrl907\" -> \"cntrl527\"\n\"cntrl908\" -> \"cntrl532\"\n\"cntrl909\" -> \"cntrl537\"\n\"cntrl910\" -> \"cntrl542\"\n\"cntrl911\" -> \"cntrl547\"\n\"cntrl913\" -> \"cntrl515\"\n\"cntrl914\" -> \"cntrl520\"\n\"cntrl915\" -> \"cntrl525\"\n\"cntrl916\" -> \"cntrl530\"\n\"cntrl917\" -> \"cntrl535\"\n\"cntrl918\" -> \"cntrl540\"\n\"cntrl919\" -> \"cntrl545\"\n\"cntrl929\" -> \"cntrl514\"\n\"cntrl937\" -> \"cntrl946\"\n\"cntrl942\" -> \"cntrl937\"\n\"cntrl946\" -> \"cntrl52\"\n\"cntrl947\" -> \"cntrl62\"\n\"cntrl948\" -> \"cntrl71\"\n\"cntrl949\" -> \"cntrl80\"\n\"cntrl950\" -> \"cntrl89\"\n\"cntrl951\" -> \"cntrl98\"\n\"cntrl952\" -> \"cntrl107\"\n\"cntrl953\" -> \"cntrl116\"\n\"cntrl954\" -> \"cntrl47\"\n\"cntrl955\" -> \"cntrl58\"\n\"cntrl956\" -> \"cntrl67\"\n\"cntrl957\" -> \"cntrl76\"\n\"cntrl958\" -> \"cntrl85\"\n\"cntrl959\" -> \"cntrl94\"\n\"cntrl960\" -> \"cntrl103\"\n\"cntrl961\" -> \"cntrl112\"\n\"cntrl962\" -> \"cntrl802\"\n\"cntrl971\" -> \"cntrl1876\"\n\"cntrl972\" -> \"cntrl971\"\n\"cntrl973\" -> \"cntrl975\"\n\"cntrl975\" -> \"cntrl802\"\n\"cntrl976\" -> \"cntrl1878\"\n\"cntrl977\" -> \"cntrl976\"\n\"cntrl978\" -> \"cntrl980\"\n\"cntrl980\" -> \"cntrl973\"\n\"cntrl981\" -> \"cntrl1880\"\n\"cntrl982\" -> \"cntrl981\"\n\"cntrl983\" -> \"cntrl991\"\n\"cntrl983\" -> \"cntrl1731\"\n\"cntrl984\" -> \"cntrl983\"\n\"cntrl987\" -> \"cntrl1882\"\n\"cntrl988\" -> \"cntrl987\"\n\"cntrl989\" -> \"cntrl1741\"\n\"cntrl990\" -> \"cntrl989\"\n\"cntrl991\" -> \"cntrl989\"\n\"cntrl993\" -> \"cntrl1884\"\n\"cntrl994\" -> \"cntrl993\"\n\"cntrl995\" -> \"cntrl997\"\n\"cntrl997\" -> \"cntrl799\"\n\"cntrl998\" -> \"cntrl1886\"\n\"cntrl999\" -> \"cntrl998\"\n\"cntrl1000\" -> \"cntrl1002\"\n\"cntrl1001\" -> \"cntrl1000\"\n\"cntrl1002\" -> \"cntrl995\"\n\"cntrl1003\" -> \"cntrl1888\"\n\"cntrl1004\" -> \"cntrl1003\"\n\"cntrl1005\" -> \"cntrl1007\"\n\"cntrl1007\" -> \"cntrl800\"\n\"cntrl1008\" -> \"cntrl1890\"\n\"cntrl1009\" -> \"cntrl1008\"\n\"cntrl1010\" -> \"cntrl1012\"\n\"cntrl1011\" -> \"cntrl1010\"\n\"cntrl1012\" -> \"cntrl1005\"\n\"cntrl1013\" -> \"cntrl1892\"\n\"cntrl1014\" -> \"cntrl1013\"\n\"cntrl1015\" -> \"cntrl1017\"\n\"cntrl1017\" -> \"cntrl801\"\n\"cntrl1018\" -> \"cntrl1894\"\n\"cntrl1019\" -> \"cntrl1018\"\n\"cntrl1020\" -> \"cntrl1022\"\n\"cntrl1021\" -> \"cntrl1020\"\n\"cntrl1022\" -> \"cntrl1015\"\n\"cntrl1023\" -> \"cntrl1896\"\n\"cntrl1025\" -> \"cntrl1031\"\n\"cntrl1028\" -> \"cntrl1898\"\n\"cntrl1030\" -> \"cntrl1032\"\n\"cntrl1031\" -> \"cntrl1030\"\n\"cntrl1032\" -> \"cntrl693\"\n\"cntrl1033\" -> \"cntrl1900\"\n\"cntrl1035\" -> \"cntrl1902\"\n\"cntrl1037\" -> \"cntrl1904\"\n\"cntrl1039\" -> \"cntrl1906\"\n\"cntrl1041\" -> \"cntrl1908\"\n\"cntrl1043\" -> \"cntrl1910\"\n\"cntrl1045\" -> \"cntrl1062\"\n\"cntrl1047\" -> \"cntrl1065\"\n\"cntrl1048\" -> \"cntrl1068\"\n\"cntrl1048\" -> \"cntrl1120\"\n\"cntrl1051\" -> \"cntrl1053\"\n\"cntrl1052\" -> \"cntrl1051\"\n\"cntrl1053\" -> \"cntrl1045\"\n\"cntrl1056\" -> \"cntrl1061\"\n\"cntrl1057\" -> \"cntrl1060\"\n\"cntrl1058\" -> \"cntrl1059\"\n\"cntrl1059\" -> \"cntrl1047\"\n\"cntrl1060\" -> \"cntrl1058\"\n\"cntrl1061\" -> \"cntrl1057\"\n\"cntrl1062\" -> \"cntrl1056\"\n\"cntrl1063\" -> \"cntrl1064\"\n\"cntrl1064\" -> \"cntrl1048\"\n\"cntrl1065\" -> \"cntrl1063\"\n\"cntrl1066\" -> \"cntrl1067\"\n\"cntrl1067\" -> \"cntrl217\"\n\"cntrl1068\" -> \"cntrl1066\"\n\"cntrl1069\" -> \"cntrl1081\"\n\"cntrl1070\" -> \"cntrl1088\"\n\"cntrl1071\" -> \"cntrl1091\"\n\"cntrl1071\" -> \"cntrl1098\"\n\"cntrl1074\" -> \"cntrl1076\"\n\"cntrl1074\" -> \"cntrl1077\"\n\"cntrl1075\" -> \"cntrl1074\"\n\"cntrl1076\" -> \"cntrl313\"\n\"cntrl1077\" -> \"cntrl1069\"\n\"cntrl1079\" -> \"cntrl1080\"\n\"cntrl1080\" -> \"cntrl1070\"\n\"cntrl1081\" -> \"cntrl1079\"\n\"cntrl1082\" -> \"cntrl1087\"\n\"cntrl1083\" -> \"cntrl1086\"\n\"cntrl1084\" -> \"cntrl1085\"\n\"cntrl1085\" -> \"cntrl1071\"\n\"cntrl1086\" -> \"cntrl1084\"\n\"cntrl1087\" -> \"cntrl1083\"\n\"cntrl1088\" -> \"cntrl1082\"\n\"cntrl1089\" -> \"cntrl1090\"\n\"cntrl1090\" -> \"cntrl690\"\n\"cntrl1091\" -> \"cntrl1089\"\n\"cntrl1092\" -> \"cntrl1107\"\n\"cntrl1094\" -> \"cntrl1110\"\n\"cntrl1095\" -> \"cntrl1113\"\n\"cntrl1095\" -> \"cntrl1141\"\n\"cntrl1098\" -> \"cntrl1092\"\n\"cntrl1101\" -> \"cntrl1106\"\n\"cntrl1102\" -> \"cntrl1105\"\n\"cntrl1103\" -> \"cntrl1104\"\n\"cntrl1104\" -> \"cntrl1094\"\n\"cntrl1105\" -> \"cntrl1103\"\n\"cntrl1106\" -> \"cntrl1102\"\n\"cntrl1107\" -> \"cntrl1101\"\n\"cntrl1108\" -> \"cntrl1109\"\n\"cntrl1109\" -> \"cntrl1095\"\n\"cntrl1110\" -> \"cntrl1108\"\n\"cntrl1111\" -> \"cntrl1112\"\n\"cntrl1112\" -> \"cntrl690\"\n\"cntrl1113\" -> \"cntrl1111\"\n\"cntrl1114\" -> \"cntrl1129\"\n\"cntrl1116\" -> \"cntrl1132\"\n\"cntrl1117\" -> \"cntrl1135\"\n\"cntrl1117\" -> \"cntrl1214\"\n\"cntrl1120\" -> \"cntrl1114\"\n\"cntrl1123\" -> \"cntrl1128\"\n\"cntrl1124\" -> \"cntrl1127\"\n\"cntrl1125\" -> \"cntrl1126\"\n\"cntrl1126\" -> \"cntrl1116\"\n\"cntrl1127\" -> \"cntrl1125\"\n\"cntrl1128\" -> \"cntrl1124\"\n\"cntrl1129\" -> \"cntrl1123\"\n\"cntrl1130\" -> \"cntrl1131\"\n\"cntrl1131\" -> \"cntrl1117\"\n\"cntrl1132\" -> \"cntrl1130\"\n\"cntrl1133\" -> \"cntrl1134\"\n\"cntrl1134\" -> \"cntrl217\"\n\"cntrl1135\" -> \"cntrl1133\"\n\"cntrl1136\" -> \"cntrl1145\"\n\"cntrl1137\" -> \"cntrl1152\"\n\"cntrl1138\" -> \"cntrl1155\"\n\"cntrl1138\" -> \"cntrl1162\"\n\"cntrl1141\" -> \"cntrl1136\"\n\"cntrl1143\" -> \"cntrl1144\"\n\"cntrl1144\" -> \"cntrl1137\"\n\"cntrl1145\" -> \"cntrl1143\"\n\"cntrl1146\" -> \"cntrl1151\"\n\"cntrl1147\" -> \"cntrl1150\"\n\"cntrl1148\" -> \"cntrl1149\"\n\"cntrl1149\" -> \"cntrl1138\"\n\"cntrl1150\" -> \"cntrl1148\"\n\"cntrl1151\" -> \"cntrl1147\"\n\"cntrl1152\" -> \"cntrl1146\"\n\"cntrl1153\" -> \"cntrl1154\"\n\"cntrl1154\" -> \"cntrl690\"\n\"cntrl1155\" -> \"cntrl1153\"\n\"cntrl1156\" -> \"cntrl1171\"\n\"cntrl1158\" -> \"cntrl1174\"\n\"cntrl1159\" -> \"cntrl1177\"\n\"cntrl1162\" -> \"cntrl1156\"\n\"cntrl1165\" -> \"cntrl1170\"\n\"cntrl1166\" -> \"cntrl1169\"\n\"cntrl1167\" -> \"cntrl1168\"\n\"cntrl1168\" -> \"cntrl1158\"\n\"cntrl1169\" -> \"cntrl1167\"\n\"cntrl1170\" -> \"cntrl1166\"\n\"cntrl1171\" -> \"cntrl1165\"\n\"cntrl1172\" -> \"cntrl1173\"\n\"cntrl1173\" -> \"cntrl1159\"\n\"cntrl1174\" -> \"cntrl1172\"\n\"cntrl1175\" -> \"cntrl1176\"\n\"cntrl1176\" -> \"cntrl690\"\n\"cntrl1177\" -> \"cntrl1175\"\n\"cntrl1178\" -> \"cntrl1192\"\n\"cntrl1179\" -> \"cntrl1195\"\n\"cntrl1181\" -> \"cntrl1183\"\n\"cntrl1181\" -> \"cntrl1184\"\n\"cntrl1182\" -> \"cntrl1181\"\n\"cntrl1183\" -> \"cntrl191\"\n\"cntrl1184\" -> \"cntrl1178\"\n\"cntrl1186\" -> \"cntrl1912\"\n\"cntrl1187\" -> \"cntrl1190\"\n\"cntrl1188\" -> \"cntrl2008\"\n\"cntrl1190\" -> \"cntrl1188\"\n\"cntrl1192\" -> \"cntrl1186\"\n\"cntrl1193\" -> \"cntrl1194\"\n\"cntrl1194\" -> \"cntrl190\"\n\"cntrl1195\" -> \"cntrl1193\"\n\"cntrl1196\" -> \"cntrl1207\"\n\"cntrl1197\" -> \"cntrl1210\"\n\"cntrl1197\" -> \"cntrl1253\"\n\"cntrl1199\" -> \"cntrl1201\"\n\"cntrl1200\" -> \"cntrl1199\"\n\"cntrl1201\" -> \"cntrl1196\"\n\"cntrl1203\" -> \"cntrl1206\"\n\"cntrl1204\" -> \"cntrl1205\"\n\"cntrl1205\" -> \"cntrl1197\"\n\"cntrl1206\" -> \"cntrl1204\"\n\"cntrl1207\" -> \"cntrl1203\"\n\"cntrl1208\" -> \"cntrl1209\"\n\"cntrl1209\" -> \"cntrl39\"\n\"cntrl1210\" -> \"cntrl1208\"\n\"cntrl1211\" -> \"cntrl1220\"\n\"cntrl1212\" -> \"cntrl1223\"\n\"cntrl1212\" -> \"cntrl1266\"\n\"cntrl1214\" -> \"cntrl1211\"\n\"cntrl1216\" -> \"cntrl1219\"\n\"cntrl1217\" -> \"cntrl1218\"\n\"cntrl1218\" -> \"cntrl1212\"\n\"cntrl1219\" -> \"cntrl1217\"\n\"cntrl1220\" -> \"cntrl1216\"\n\"cntrl1221\" -> \"cntrl1222\"\n\"cntrl1222\" -> \"cntrl217\"\n\"cntrl1223\" -> \"cntrl1221\"\n\"cntrl1224\" -> \"cntrl1235\"\n\"cntrl1225\" -> \"cntrl1238\"\n\"cntrl1227\" -> \"cntrl1229\"\n\"cntrl1228\" -> \"cntrl1227\"\n\"cntrl1229\" -> \"cntrl1224\"\n\"cntrl1231\" -> \"cntrl1234\"\n\"cntrl1232\" -> \"cntrl1233\"\n\"cntrl1233\" -> \"cntrl1225\"\n\"cntrl1234\" -> \"cntrl1232\"\n\"cntrl1235\" -> \"cntrl1231\"\n\"cntrl1236\" -> \"cntrl1237\"\n\"cntrl1237\" -> \"cntrl1028\"\n\"cntrl1238\" -> \"cntrl1236\"\n\"cntrl1239\" -> \"cntrl1247\"\n\"cntrl1240\" -> \"cntrl1249\"\n\"cntrl1242\" -> \"cntrl1239\"\n\"cntrl1243\" -> \"cntrl1914\"\n\"cntrl1244\" -> \"cntrl1245\"\n\"cntrl1245\" -> \"cntrl1240\"\n\"cntrl1247\" -> \"cntrl1243\"\n\"cntrl1248\" -> \"cntrl1584\"\n\"cntrl1248\" -> \"cntrl1585\"\n\"cntrl1249\" -> \"cntrl1248\"\n\"cntrl1250\" -> \"cntrl1259\"\n\"cntrl1251\" -> \"cntrl1262\"\n\"cntrl1251\" -> \"cntrl1339\"\n\"cntrl1253\" -> \"cntrl1250\"\n\"cntrl1255\" -> \"cntrl1258\"\n\"cntrl1256\" -> \"cntrl1257\"\n\"cntrl1257\" -> \"cntrl1251\"\n\"cntrl1258\" -> \"cntrl1256\"\n\"cntrl1259\" -> \"cntrl1255\"\n\"cntrl1260\" -> \"cntrl1261\"\n\"cntrl1261\" -> \"cntrl39\"\n\"cntrl1262\" -> \"cntrl1260\"\n\"cntrl1263\" -> \"cntrl1272\"\n\"cntrl1264\" -> \"cntrl1275\"\n\"cntrl1266\" -> \"cntrl1263\"\n\"cntrl1268\" -> \"cntrl1271\"\n\"cntrl1269\" -> \"cntrl1270\"\n\"cntrl1270\" -> \"cntrl1264\"\n\"cntrl1271\" -> \"cntrl1269\"\n\"cntrl1272\" -> \"cntrl1268\"\n\"cntrl1273\" -> \"cntrl1274\"\n\"cntrl1274\" -> \"cntrl217\"\n\"cntrl1275\" -> \"cntrl1273\"\n\"cntrl1276\" -> \"cntrl1287\"\n\"cntrl1277\" -> \"cntrl1290\"\n\"cntrl1279\" -> \"cntrl1281\"\n\"cntrl1280\" -> \"cntrl1279\"\n\"cntrl1281\" -> \"cntrl1276\"\n\"cntrl1283\" -> \"cntrl1286\"\n\"cntrl1284\" -> \"cntrl1285\"\n\"cntrl1285\" -> \"cntrl1277\"\n\"cntrl1286\" -> \"cntrl1284\"\n\"cntrl1287\" -> \"cntrl1283\"\n\"cntrl1288\" -> \"cntrl1289\"\n\"cntrl1289\" -> \"cntrl1023\"\n\"cntrl1290\" -> \"cntrl1288\"\n\"cntrl1291\" -> \"cntrl1299\"\n\"cntrl1292\" -> \"cntrl1301\"\n\"cntrl1294\" -> \"cntrl1291\"\n\"cntrl1295\" -> \"cntrl1919\"\n\"cntrl1296\" -> \"cntrl1297\"\n\"cntrl1297\" -> \"cntrl1292\"\n\"cntrl1299\" -> \"cntrl1295\"\n\"cntrl1300\" -> \"cntrl1582\"\n\"cntrl1300\" -> \"cntrl1583\"\n\"cntrl1301\" -> \"cntrl1300\"\n\"cntrl1302\" -> \"cntrl1315\"\n\"cntrl1303\" -> \"cntrl1318\"\n\"cntrl1305\" -> \"cntrl1307\"\n\"cntrl1307\" -> \"cntrl1302\"\n\"cntrl1309\" -> \"cntrl1314\"\n\"cntrl1310\" -> \"cntrl1313\"\n\"cntrl1311\" -> \"cntrl1312\"\n\"cntrl1312\" -> \"cntrl1303\"\n\"cntrl1313\" -> \"cntrl1311\"\n\"cntrl1314\" -> \"cntrl1310\"\n\"cntrl1315\" -> \"cntrl1309\"\n\"cntrl1316\" -> \"cntrl1317\"\n\"cntrl1317\" -> \"cntrl37\"\n\"cntrl1318\" -> \"cntrl1316\"\n\"cntrl1319\" -> \"cntrl1332\"\n\"cntrl1320\" -> \"cntrl1335\"\n\"cntrl1322\" -> \"cntrl1324\"\n\"cntrl1324\" -> \"cntrl1319\"\n\"cntrl1326\" -> \"cntrl1331\"\n\"cntrl1327\" -> \"cntrl1330\"\n\"cntrl1328\" -> \"cntrl1329\"\n\"cntrl1329\" -> \"cntrl1320\"\n\"cntrl1330\" -> \"cntrl1328\"\n\"cntrl1331\" -> \"cntrl1327\"\n\"cntrl1332\" -> \"cntrl1326\"\n\"cntrl1333\" -> \"cntrl1334\"\n\"cntrl1334\" -> \"cntrl189\"\n\"cntrl1335\" -> \"cntrl1333\"\n\"cntrl1336\" -> \"cntrl1345\"\n\"cntrl1337\" -> \"cntrl1348\"\n\"cntrl1337\" -> \"cntrl1378\"\n\"cntrl1339\" -> \"cntrl1336\"\n\"cntrl1341\" -> \"cntrl1344\"\n\"cntrl1342\" -> \"cntrl1343\"\n\"cntrl1343\" -> \"cntrl1337\"\n\"cntrl1344\" -> \"cntrl1342\"\n\"cntrl1345\" -> \"cntrl1341\"\n\"cntrl1346\" -> \"cntrl1347\"\n\"cntrl1347\" -> \"cntrl39\"\n\"cntrl1348\" -> \"cntrl1346\"\n\"cntrl1349\" -> \"cntrl1360\"\n\"cntrl1350\" -> \"cntrl1363\"\n\"cntrl1352\" -> \"cntrl1354\"\n\"cntrl1353\" -> \"cntrl1352\"\n\"cntrl1354\" -> \"cntrl1349\"\n\"cntrl1356\" -> \"cntrl1359\"\n\"cntrl1357\" -> \"cntrl1358\"\n\"cntrl1358\" -> \"cntrl1350\"\n\"cntrl1359\" -> \"cntrl1357\"\n\"cntrl1360\" -> \"cntrl1356\"\n\"cntrl1361\" -> \"cntrl1362\"\n\"cntrl1362\" -> \"cntrl1035\"\n\"cntrl1363\" -> \"cntrl1361\"\n\"cntrl1364\" -> \"cntrl1372\"\n\"cntrl1365\" -> \"cntrl1374\"\n\"cntrl1367\" -> \"cntrl1364\"\n\"cntrl1368\" -> \"cntrl1915\"\n\"cntrl1369\" -> \"cntrl1370\"\n\"cntrl1370\" -> \"cntrl1365\"\n\"cntrl1372\" -> \"cntrl1368\"\n\"cntrl1373\" -> \"cntrl1580\"\n\"cntrl1373\" -> \"cntrl1581\"\n\"cntrl1374\" -> \"cntrl1373\"\n\"cntrl1375\" -> \"cntrl1384\"\n\"cntrl1376\" -> \"cntrl1387\"\n\"cntrl1376\" -> \"cntrl1417\"\n\"cntrl1378\" -> \"cntrl1375\"\n\"cntrl1380\" -> \"cntrl1383\"\n\"cntrl1381\" -> \"cntrl1382\"\n\"cntrl1382\" -> \"cntrl1376\"\n\"cntrl1383\" -> \"cntrl1381\"\n\"cntrl1384\" -> \"cntrl1380\"\n\"cntrl1385\" -> \"cntrl1386\"\n\"cntrl1386\" -> \"cntrl39\"\n\"cntrl1387\" -> \"cntrl1385\"\n\"cntrl1388\" -> \"cntrl1399\"\n\"cntrl1389\" -> \"cntrl1402\"\n\"cntrl1391\" -> \"cntrl1393\"\n\"cntrl1392\" -> \"cntrl1391\"\n\"cntrl1393\" -> \"cntrl1388\"\n\"cntrl1395\" -> \"cntrl1398\"\n\"cntrl1396\" -> \"cntrl1397\"\n\"cntrl1397\" -> \"cntrl1389\"\n\"cntrl1398\" -> \"cntrl1396\"\n\"cntrl1399\" -> \"cntrl1395\"\n\"cntrl1400\" -> \"cntrl1401\"\n\"cntrl1401\" -> \"cntrl1033\"\n\"cntrl1402\" -> \"cntrl1400\"\n\"cntrl1403\" -> \"cntrl1411\"\n\"cntrl1404\" -> \"cntrl1413\"\n\"cntrl1406\" -> \"cntrl1403\"\n\"cntrl1407\" -> \"cntrl1920\"\n\"cntrl1408\" -> \"cntrl1409\"\n\"cntrl1409\" -> \"cntrl1404\"\n\"cntrl1411\" -> \"cntrl1407\"\n\"cntrl1412\" -> \"cntrl1578\"\n\"cntrl1412\" -> \"cntrl1579\"\n\"cntrl1413\" -> \"cntrl1412\"\n\"cntrl1414\" -> \"cntrl1423\"\n\"cntrl1415\" -> \"cntrl1426\"\n\"cntrl1415\" -> \"cntrl1456\"\n\"cntrl1417\" -> \"cntrl1414\"\n\"cntrl1419\" -> \"cntrl1422\"\n\"cntrl1420\" -> \"cntrl1421\"\n\"cntrl1421\" -> \"cntrl1415\"\n\"cntrl1422\" -> \"cntrl1420\"\n\"cntrl1423\" -> \"cntrl1419\"\n\"cntrl1424\" -> \"cntrl1425\"\n\"cntrl1425\" -> \"cntrl39\"\n\"cntrl1426\" -> \"cntrl1424\"\n\"cntrl1427\" -> \"cntrl1438\"\n\"cntrl1428\" -> \"cntrl1441\"\n\"cntrl1430\" -> \"cntrl1432\"\n\"cntrl1431\" -> \"cntrl1430\"\n\"cntrl1432\" -> \"cntrl1427\"\n\"cntrl1434\" -> \"cntrl1437\"\n\"cntrl1435\" -> \"cntrl1436\"\n\"cntrl1436\" -> \"cntrl1428\"\n\"cntrl1437\" -> \"cntrl1435\"\n\"cntrl1438\" -> \"cntrl1434\"\n\"cntrl1439\" -> \"cntrl1440\"\n\"cntrl1440\" -> \"cntrl1039\"\n\"cntrl1441\" -> \"cntrl1439\"\n\"cntrl1442\" -> \"cntrl1450\"\n\"cntrl1443\" -> \"cntrl1452\"\n\"cntrl1445\" -> \"cntrl1442\"\n\"cntrl1446\" -> \"cntrl1916\"\n\"cntrl1447\" -> \"cntrl1448\"\n\"cntrl1448\" -> \"cntrl1443\"\n\"cntrl1450\" -> \"cntrl1446\"\n\"cntrl1451\" -> \"cntrl1576\"\n\"cntrl1451\" -> \"cntrl1577\"\n\"cntrl1452\" -> \"cntrl1451\"\n\"cntrl1453\" -> \"cntrl1462\"\n\"cntrl1454\" -> \"cntrl1465\"\n\"cntrl1454\" -> \"cntrl1495\"\n\"cntrl1456\" -> \"cntrl1453\"\n\"cntrl1458\" -> \"cntrl1461\"\n\"cntrl1459\" -> \"cntrl1460\"\n\"cntrl1460\" -> \"cntrl1454\"\n\"cntrl1461\" -> \"cntrl1459\"\n\"cntrl1462\" -> \"cntrl1458\"\n\"cntrl1463\" -> \"cntrl1464\"\n\"cntrl1464\" -> \"cntrl39\"\n\"cntrl1465\" -> \"cntrl1463\"\n\"cntrl1466\" -> \"cntrl1477\"\n\"cntrl1467\" -> \"cntrl1480\"\n\"cntrl1469\" -> \"cntrl1471\"\n\"cntrl1470\" -> \"cntrl1469\"\n\"cntrl1471\" -> \"cntrl1466\"\n\"cntrl1473\" -> \"cntrl1476\"\n\"cntrl1474\" -> \"cntrl1475\"\n\"cntrl1475\" -> \"cntrl1467\"\n\"cntrl1476\" -> \"cntrl1474\"\n\"cntrl1477\" -> \"cntrl1473\"\n\"cntrl1478\" -> \"cntrl1479\"\n\"cntrl1479\" -> \"cntrl1037\"\n\"cntrl1480\" -> \"cntrl1478\"\n\"cntrl1481\" -> \"cntrl1489\"\n\"cntrl1482\" -> \"cntrl1491\"\n\"cntrl1484\" -> \"cntrl1481\"\n\"cntrl1485\" -> \"cntrl1921\"\n\"cntrl1486\" -> \"cntrl1487\"\n\"cntrl1487\" -> \"cntrl1482\"\n\"cntrl1489\" -> \"cntrl1485\"\n\"cntrl1490\" -> \"cntrl1574\"\n\"cntrl1490\" -> \"cntrl1575\"\n\"cntrl1491\" -> \"cntrl1490\"\n\"cntrl1492\" -> \"cntrl1501\"\n\"cntrl1493\" -> \"cntrl1504\"\n\"cntrl1493\" -> \"cntrl1534\"\n\"cntrl1495\" -> \"cntrl1492\"\n\"cntrl1497\" -> \"cntrl1500\"\n\"cntrl1498\" -> \"cntrl1499\"\n\"cntrl1499\" -> \"cntrl1493\"\n\"cntrl1500\" -> \"cntrl1498\"\n\"cntrl1501\" -> \"cntrl1497\"\n\"cntrl1502\" -> \"cntrl1503\"\n\"cntrl1503\" -> \"cntrl39\"\n\"cntrl1504\" -> \"cntrl1502\"\n\"cntrl1505\" -> \"cntrl1516\"\n\"cntrl1506\" -> \"cntrl1519\"\n\"cntrl1508\" -> \"cntrl1510\"\n\"cntrl1509\" -> \"cntrl1508\"\n\"cntrl1510\" -> \"cntrl1505\"\n\"cntrl1512\" -> \"cntrl1515\"\n\"cntrl1513\" -> \"cntrl1514\"\n\"cntrl1514\" -> \"cntrl1506\"\n\"cntrl1515\" -> \"cntrl1513\"\n\"cntrl1516\" -> \"cntrl1512\"\n\"cntrl1517\" -> \"cntrl1518\"\n\"cntrl1518\" -> \"cntrl1043\"\n\"cntrl1519\" -> \"cntrl1517\"\n\"cntrl1520\" -> \"cntrl1528\"\n\"cntrl1521\" -> \"cntrl1530\"\n\"cntrl1523\" -> \"cntrl1520\"\n\"cntrl1524\" -> \"cntrl1917\"\n\"cntrl1525\" -> \"cntrl1526\"\n\"cntrl1526\" -> \"cntrl1521\"\n\"cntrl1528\" -> \"cntrl1524\"\n\"cntrl1529\" -> \"cntrl1572\"\n\"cntrl1529\" -> \"cntrl1573\"\n\"cntrl1530\" -> \"cntrl1529\"\n\"cntrl1531\" -> \"cntrl1540\"\n\"cntrl1532\" -> \"cntrl1543\"\n\"cntrl1534\" -> \"cntrl1531\"\n\"cntrl1536\" -> \"cntrl1539\"\n\"cntrl1537\" -> \"cntrl1538\"\n\"cntrl1538\" -> \"cntrl1532\"\n\"cntrl1539\" -> \"cntrl1537\"\n\"cntrl1540\" -> \"cntrl1536\"\n\"cntrl1541\" -> \"cntrl1542\"\n\"cntrl1542\" -> \"cntrl39\"\n\"cntrl1543\" -> \"cntrl1541\"\n\"cntrl1544\" -> \"cntrl1555\"\n\"cntrl1545\" -> \"cntrl1558\"\n\"cntrl1547\" -> \"cntrl1549\"\n\"cntrl1548\" -> \"cntrl1547\"\n\"cntrl1549\" -> \"cntrl1544\"\n\"cntrl1551\" -> \"cntrl1554\"\n\"cntrl1552\" -> \"cntrl1553\"\n\"cntrl1553\" -> \"cntrl1545\"\n\"cntrl1554\" -> \"cntrl1552\"\n\"cntrl1555\" -> \"cntrl1551\"\n\"cntrl1556\" -> \"cntrl1557\"\n\"cntrl1557\" -> \"cntrl1041\"\n\"cntrl1558\" -> \"cntrl1556\"\n\"cntrl1559\" -> \"cntrl1567\"\n\"cntrl1560\" -> \"cntrl1569\"\n\"cntrl1562\" -> \"cntrl1559\"\n\"cntrl1563\" -> \"cntrl1922\"\n\"cntrl1564\" -> \"cntrl1565\"\n\"cntrl1565\" -> \"cntrl1560\"\n\"cntrl1567\" -> \"cntrl1563\"\n\"cntrl1568\" -> \"cntrl1570\"\n\"cntrl1568\" -> \"cntrl1571\"\n\"cntrl1569\" -> \"cntrl1568\"\n\"cntrl1570\" -> \"cntrl24\"\n\"cntrl1571\" -> \"cntrl2\"\n\"cntrl1572\" -> \"cntrl24\"\n\"cntrl1573\" -> \"cntrl2\"\n\"cntrl1574\" -> \"cntrl24\"\n\"cntrl1575\" -> \"cntrl2\"\n\"cntrl1576\" -> \"cntrl24\"\n\"cntrl1577\" -> \"cntrl2\"\n\"cntrl1578\" -> \"cntrl24\"\n\"cntrl1579\" -> \"cntrl2\"\n\"cntrl1580\" -> \"cntrl24\"\n\"cntrl1581\" -> \"cntrl2\"\n\"cntrl1582\" -> \"cntrl24\"\n\"cntrl1583\" -> \"cntrl2\"\n\"cntrl1584\" -> \"cntrl24\"\n\"cntrl1585\" -> \"cntrl2\"\n\"cntrl1586\" -> \"cntrl41\"\n\"cntrl1595\" -> \"cntrl219\"\n\"cntrl1629\" -> \"cntrl66\"\n\"cntrl1630\" -> \"cntrl75\"\n\"cntrl1631\" -> \"cntrl84\"\n\"cntrl1632\" -> \"cntrl93\"\n\"cntrl1633\" -> \"cntrl102\"\n\"cntrl1634\" -> \"cntrl111\"\n\"cntrl1635\" -> \"cntrl120\"\n\"cntrl1660\" -> \"cntrl332\"\n\"cntrl1668\" -> \"cntrl330\"\n\"cntrl1670\" -> \"cntrl340\"\n\"cntrl1672\" -> \"cntrl350\"\n\"cntrl1674\" -> \"cntrl360\"\n\"cntrl1723\" -> \"cntrl1725\"\n\"cntrl1724\" -> \"cntrl1723\"\n\"cntrl1725\" -> \"cntrl599\"\n\"cntrl1726\" -> \"cntrl1728\"\n\"cntrl1727\" -> \"cntrl1726\"\n\"cntrl1728\" -> \"cntrl318\"\n\"cntrl1729\" -> \"cntrl1732\"\n\"cntrl1730\" -> \"cntrl1729\"\n\"cntrl1731\" -> \"cntrl1729\"\n\"cntrl1732\" -> \"cntrl224\"\n\"cntrl1733\" -> \"cntrl1735\"\n\"cntrl1734\" -> \"cntrl1733\"\n\"cntrl1735\" -> \"cntrl604\"\n\"cntrl1736\" -> \"cntrl1738\"\n\"cntrl1737\" -> \"cntrl1736\"\n\"cntrl1738\" -> \"cntrl323\"\n\"cntrl1739\" -> \"cntrl1742\"\n\"cntrl1740\" -> \"cntrl1739\"\n\"cntrl1741\" -> \"cntrl1739\"\n\"cntrl1742\" -> \"cntrl226\"\n\"cntrl1743\" -> \"cntrl1745\"\n\"cntrl1744\" -> \"cntrl1743\"\n\"cntrl1745\" -> \"cntrl610\"\n\"cntrl1746\" -> \"cntrl1748\"\n\"cntrl1747\" -> \"cntrl1746\"\n\"cntrl1748\" -> \"cntrl615\"\n\"cntrl1749\" -> \"cntrl1751\"\n\"cntrl1750\" -> \"cntrl1749\"\n\"cntrl1751\" -> \"cntrl624\"\n\"cntrl1752\" -> \"cntrl1754\"\n\"cntrl1753\" -> \"cntrl1752\"\n\"cntrl1754\" -> \"cntrl629\"\n\"cntrl1755\" -> \"cntrl1757\"\n\"cntrl1757\" -> \"cntrl638\"\n\"cntrl1758\" -> \"cntrl1760\"\n\"cntrl1759\" -> \"cntrl1758\"\n\"cntrl1760\" -> \"cntrl643\"\n\"cntrl1761\" -> \"cntrl1923\"\n\"cntrl1762\" -> \"cntrl1761\"\n\"cntrl1764\" -> \"cntrl1763\"\n\"cntrl1765\" -> \"cntrl1768\"\n\"cntrl1766\" -> \"cntrl1765\"\n\"cntrl1768\" -> \"cntrl1767\"\n\"cntrl1770\" -> \"cntrl1769\"\n\"cntrl1771\" -> \"cntrl1924\"\n\"cntrl1772\" -> \"cntrl1771\"\n\"cntrl1773\" -> \"cntrl1925\"\n\"cntrl1774\" -> \"cntrl1773\"\n\"cntrl1776\" -> \"cntrl1775\"\n\"cntrl1778\" -> \"cntrl1777\"\n\"cntrl1779\" -> \"cntrl1926\"\n\"cntrl1780\" -> \"cntrl1779\"\n\"cntrl1782\" -> \"cntrl1781\"\n\"cntrl1783\" -> \"cntrl1927\"\n\"cntrl1784\" -> \"cntrl1783\"\n\"cntrl1785\" -> \"cntrl1928\"\n\"cntrl1786\" -> \"cntrl1785\"\n\"cntrl1787\" -> \"cntrl1929\"\n\"cntrl1788\" -> \"cntrl1787\"\n\"cntrl1789\" -> \"cntrl1930\"\n\"cntrl1790\" -> \"cntrl1789\"\n\"cntrl1791\" -> \"cntrl1931\"\n\"cntrl1792\" -> \"cntrl1791\"\n\"cntrl1793\" -> \"cntrl1932\"\n\"cntrl1794\" -> \"cntrl1793\"\n\"cntrl1795\" -> \"cntrl1933\"\n\"cntrl1796\" -> \"cntrl1795\"\n\"cntrl1798\" -> \"cntrl1797\"\n\"cntrl1799\" -> \"cntrl1802\"\n\"cntrl1800\" -> \"cntrl1799\"\n\"cntrl1802\" -> \"cntrl1801\"\n\"cntrl1803\" -> \"cntrl1934\"\n\"cntrl1803\" -> \"cntrl1935\"\n\"cntrl1804\" -> \"cntrl1803\"\n\"cntrl1805\" -> \"cntrl1936\"\n\"cntrl1805\" -> \"cntrl1937\"\n\"cntrl1806\" -> \"cntrl1805\"\n\"cntrl1807\" -> \"cntrl1938\"\n\"cntrl1807\" -> \"cntrl1939\"\n\"cntrl1808\" -> \"cntrl1807\"\n\"cntrl1809\" -> \"cntrl1940\"\n\"cntrl1809\" -> \"cntrl1941\"\n\"cntrl1810\" -> \"cntrl1809\"\n\"cntrl1811\" -> \"cntrl1942\"\n\"cntrl1811\" -> \"cntrl1943\"\n\"cntrl1812\" -> \"cntrl1811\"\n\"cntrl1813\" -> \"cntrl1944\"\n\"cntrl1814\" -> \"cntrl1813\"\n\"cntrl1815\" -> \"cntrl1945\"\n\"cntrl1816\" -> \"cntrl1815\"\n\"cntrl1817\" -> \"cntrl1946\"\n\"cntrl1818\" -> \"cntrl1817\"\n\"cntrl1819\" -> \"cntrl1947\"\n\"cntrl1820\" -> \"cntrl1819\"\n\"cntrl1821\" -> \"cntrl1948\"\n\"cntrl1822\" -> \"cntrl1821\"\n\"cntrl1823\" -> \"cntrl1949\"\n\"cntrl1823\" -> \"cntrl1950\"\n\"cntrl1824\" -> \"cntrl1823\"\n\"cntrl1825\" -> \"cntrl1951\"\n\"cntrl1825\" -> \"cntrl1952\"\n\"cntrl1826\" -> \"cntrl1825\"\n\"cntrl1827\" -> \"cntrl1953\"\n\"cntrl1827\" -> \"cntrl1954\"\n\"cntrl1828\" -> \"cntrl1827\"\n\"cntrl1829\" -> \"cntrl1955\"\n\"cntrl1829\" -> \"cntrl1956\"\n\"cntrl1830\" -> \"cntrl1829\"\n\"cntrl1831\" -> \"cntrl1957\"\n\"cntrl1831\" -> \"cntrl1958\"\n\"cntrl1832\" -> \"cntrl1831\"\n\"cntrl1833\" -> \"cntrl1959\"\n\"cntrl1834\" -> \"cntrl1833\"\n\"cntrl1835\" -> \"cntrl1960\"\n\"cntrl1836\" -> \"cntrl1835\"\n\"cntrl1837\" -> \"cntrl1961\"\n\"cntrl1838\" -> \"cntrl1837\"\n\"cntrl1839\" -> \"cntrl1962\"\n\"cntrl1840\" -> \"cntrl1839\"\n\"cntrl1841\" -> \"cntrl1963\"\n\"cntrl1842\" -> \"cntrl1841\"\n\"cntrl1843\" -> \"cntrl1964\"\n\"cntrl1843\" -> \"cntrl1965\"\n\"cntrl1844\" -> \"cntrl1843\"\n\"cntrl1845\" -> \"cntrl1966\"\n\"cntrl1845\" -> \"cntrl1967\"\n\"cntrl1846\" -> \"cntrl1845\"\n\"cntrl1847\" -> \"cntrl1968\"\n\"cntrl1847\" -> \"cntrl1969\"\n\"cntrl1848\" -> \"cntrl1847\"\n\"cntrl1849\" -> \"cntrl1970\"\n\"cntrl1849\" -> \"cntrl1971\"\n\"cntrl1850\" -> \"cntrl1849\"\n\"cntrl1851\" -> \"cntrl1972\"\n\"cntrl1851\" -> \"cntrl1973\"\n\"cntrl1852\" -> \"cntrl1851\"\n\"cntrl1853\" -> \"cntrl1974\"\n\"cntrl1854\" -> \"cntrl1853\"\n\"cntrl1855\" -> \"cntrl1975\"\n\"cntrl1856\" -> \"cntrl1855\"\n\"cntrl1857\" -> \"cntrl1976\"\n\"cntrl1858\" -> \"cntrl1857\"\n\"cntrl1859\" -> \"cntrl1977\"\n\"cntrl1860\" -> \"cntrl1859\"\n\"cntrl1861\" -> \"cntrl1978\"\n\"cntrl1862\" -> \"cntrl1861\"\n\"cntrl1863\" -> \"cntrl1979\"\n\"cntrl1863\" -> \"cntrl1980\"\n\"cntrl1864\" -> \"cntrl1863\"\n\"cntrl1865\" -> \"cntrl1981\"\n\"cntrl1865\" -> \"cntrl1982\"\n\"cntrl1866\" -> \"cntrl1865\"\n\"cntrl1867\" -> \"cntrl1983\"\n\"cntrl1868\" -> \"cntrl1867\"\n\"cntrl1870\" -> \"cntrl1869\"\n\"cntrl1871\" -> \"cntrl1984\"\n\"cntrl1872\" -> \"cntrl1871\"\n\"cntrl1873\" -> \"cntrl1985\"\n\"cntrl1874\" -> \"cntrl1873\"\n\"cntrl1876\" -> \"cntrl1875\"\n\"cntrl1878\" -> \"cntrl1877\"\n\"cntrl1879\" -> \"cntrl1986\"\n\"cntrl1880\" -> \"cntrl1879\"\n\"cntrl1881\" -> \"cntrl1987\"\n\"cntrl1882\" -> \"cntrl1881\"\n\"cntrl1884\" -> \"cntrl1883\"\n\"cntrl1886\" -> \"cntrl1885\"\n\"cntrl1888\" -> \"cntrl1887\"\n\"cntrl1890\" -> \"cntrl1889\"\n\"cntrl1892\" -> \"cntrl1891\"\n\"cntrl1894\" -> \"cntrl1893\"\n\"cntrl1896\" -> \"cntrl1895\"\n\"cntrl1898\" -> \"cntrl1897\"\n\"cntrl1900\" -> \"cntrl1899\"\n\"cntrl1902\" -> \"cntrl1901\"\n\"cntrl1904\" -> \"cntrl1903\"\n\"cntrl1906\" -> \"cntrl1905\"\n\"cntrl1908\" -> \"cntrl1907\"\n\"cntrl1910\" -> \"cntrl1909\"\n\"cntrl1911\" -> \"cntrl1988\"\n\"cntrl1912\" -> \"cntrl1911\"\n\"cntrl1913\" -> \"cntrl1989\"\n\"cntrl1913\" -> \"cntrl1990\"\n\"cntrl1913\" -> \"cntrl1991\"\n\"cntrl1913\" -> \"cntrl1992\"\n\"cntrl1914\" -> \"cntrl1913\"\n\"cntrl1915\" -> \"cntrl1913\"\n\"cntrl1916\" -> \"cntrl1913\"\n\"cntrl1917\" -> \"cntrl1913\"\n\"cntrl1918\" -> \"cntrl1993\"\n\"cntrl1918\" -> \"cntrl1994\"\n\"cntrl1918\" -> \"cntrl1995\"\n\"cntrl1918\" -> \"cntrl1996\"\n\"cntrl1919\" -> \"cntrl1918\"\n\"cntrl1920\" -> \"cntrl1918\"\n\"cntrl1921\" -> \"cntrl1918\"\n\"cntrl1922\" -> \"cntrl1918\"\n\"cntrl1923\" -> \"cntrl1305\"\n\"cntrl1924\" -> \"cntrl188\"\n\"cntrl1925\" -> \"cntrl1322\"\n\"cntrl1926\" -> \"cntrl187\"\n\"cntrl1927\" -> \"cntrl229\"\n\"cntrl1928\" -> \"cntrl234\"\n\"cntrl1929\" -> \"cntrl239\"\n\"cntrl1930\" -> \"cntrl244\"\n\"cntrl1931\" -> \"cntrl249\"\n\"cntrl1932\" -> \"cntrl254\"\n\"cntrl1933\" -> \"cntrl259\"\n\"cntrl1934\" -> \"cntrl339\"\n\"cntrl1935\" -> \"cntrl422\"\n\"cntrl1936\" -> \"cntrl344\"\n\"cntrl1937\" -> \"cntrl420\"\n\"cntrl1938\" -> \"cntrl349\"\n\"cntrl1939\" -> \"cntrl430\"\n\"cntrl1940\" -> \"cntrl354\"\n\"cntrl1941\" -> \"cntrl440\"\n\"cntrl1942\" -> \"cntrl359\"\n\"cntrl1943\" -> \"cntrl450\"\n\"cntrl1944\" -> \"cntrl364\"\n\"cntrl1945\" -> \"cntrl369\"\n\"cntrl1946\" -> \"cntrl799\"\n\"cntrl1947\" -> \"cntrl330\"\n\"cntrl1948\" -> \"cntrl800\"\n\"cntrl1949\" -> \"cntrl429\"\n\"cntrl1950\" -> \"cntrl512\"\n\"cntrl1951\" -> \"cntrl434\"\n\"cntrl1952\" -> \"cntrl510\"\n\"cntrl1953\" -> \"cntrl439\"\n\"cntrl1954\" -> \"cntrl520\"\n\"cntrl1955\" -> \"cntrl444\"\n\"cntrl1956\" -> \"cntrl530\"\n\"cntrl1957\" -> \"cntrl449\"\n\"cntrl1958\" -> \"cntrl540\"\n\"cntrl1959\" -> \"cntrl454\"\n\"cntrl1960\" -> \"cntrl459\"\n\"cntrl1961\" -> \"cntrl800\"\n\"cntrl1962\" -> \"cntrl420\"\n\"cntrl1963\" -> \"cntrl801\"\n\"cntrl1964\" -> \"cntrl519\"\n\"cntrl1965\" -> \"cntrl52\"\n\"cntrl1966\" -> \"cntrl524\"\n\"cntrl1967\" -> \"cntrl47\"\n\"cntrl1968\" -> \"cntrl529\"\n\"cntrl1969\" -> \"cntrl67\"\n\"cntrl1970\" -> \"cntrl534\"\n\"cntrl1971\" -> \"cntrl85\"\n\"cntrl1972\" -> \"cntrl539\"\n\"cntrl1973\" -> \"cntrl103\"\n\"cntrl1974\" -> \"cntrl544\"\n\"cntrl1975\" -> \"cntrl549\"\n\"cntrl1976\" -> \"cntrl801\"\n\"cntrl1977\" -> \"cntrl510\"\n\"cntrl1978\" -> \"cntrl802\"\n\"cntrl1979\" -> \"cntrl978\"\n\"cntrl1980\" -> \"cntrl1093\"\n\"cntrl1981\" -> \"cntrl1157\"\n\"cntrl1982\" -> \"cntrl1755\"\n\"cntrl1983\" -> \"cntrl177\"\n\"cntrl1984\" -> \"cntrl717\"\n\"cntrl1985\" -> \"cntrl1025\"\n\"cntrl1986\" -> \"cntrl1046\"\n\"cntrl1987\" -> \"cntrl1115\"\n\"cntrl1988\" -> \"cntrl1187\"\n\"cntrl1989\" -> \"cntrl1244\"\n\"cntrl1990\" -> \"cntrl1369\"\n\"cntrl1991\" -> \"cntrl1447\"\n\"cntrl1992\" -> \"cntrl1525\"\n\"cntrl1993\" -> \"cntrl1296\"\n\"cntrl1994\" -> \"cntrl1408\"\n\"cntrl1995\" -> \"cntrl1486\"\n\"cntrl1996\" -> \"cntrl1564\"\n\"cntrl1997\" -> \"cntrl2009\"\n\"cntrl1998\" -> \"cntrl1997\"\n\"cntrl1999\" -> \"cntrl2010\"\n\"cntrl2000\" -> \"cntrl1999\"\n\"cntrl2004\" -> \"cntrl2003\"\n\"cntrl2007\" -> \"cntrl2011\"\n\"cntrl2008\" -> \"cntrl2007\"\n\"cntrl2009\" -> \"cntrl670\"\n\"cntrl2010\" -> \"cntrl670\"\n\"cntrl2011\" -> \"cntrl1179\"\n}\n}\n" - .command: - sync: false - operations: - - type: Tensor - tag: 0 - variableType: {dataType: Half, pointerType: Value} - numDims: 2 - sizes: - - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - pointer: {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - extent: {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - strides: - - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - literalStrides: - - 0 - - 1 - - type: T_Load_Tiled - tag: 1 - tensorTag: -1 - - type: Tensor - tag: 2 - variableType: {dataType: Half, pointerType: Value} - numDims: 2 - sizes: - - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - pointer: {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - extent: {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - strides: - - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - literalStrides: - - 1 - - type: T_Load_Tiled - tag: 3 - tensorTag: -1 - - type: Tensor - tag: 4 - variableType: {dataType: Half, pointerType: Value} - numDims: 2 - sizes: - - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - pointer: {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - extent: {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - strides: - - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - literalStrides: - - 1 - - type: T_Load_Tiled - tag: 5 - tensorTag: -1 - - type: Scalar - tag: 6 - variableType: {dataType: Float, pointerType: Value} - pointer: {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - - type: T_Load_Scalar - tag: 7 - scalarTag: -1 - - type: Scalar - tag: 8 - variableType: {dataType: Float, pointerType: Value} - pointer: {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - - type: T_Load_Scalar - tag: 9 - scalarTag: -1 - - type: T_Mul - tag: 10 - a: 1 - b: 3 - - type: T_Execute - tag: 14 - xops: - - type: E_Mul - dest: 11 - a: 9 - b: 5 - - type: E_Mul - dest: 12 - a: 7 - b: 10 - - type: E_Add - dest: 13 - a: 11 - b: 12 - nextTag: 14 - inputs: [7, 10, 9, 5] - outputs: [13, 12, 11] - - type: Tensor - tag: 15 - variableType: {dataType: Half, pointerType: Value} - numDims: 2 - sizes: - - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - pointer: {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - extent: {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - strides: - - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - literalStrides: - - 1 - - type: T_Execute - tag: 17 - xops: - - type: E_Cvt - dest: 16 - a: 13 - nextTag: 17 - inputs: [13] - outputs: [16] - - type: T_Store_Tiled - tag: 18 - srcTag: 16 - dstTag: 15 - argOffsetMap: - 15 Stride 1: 192 - 15 Stride 0: 184 - 15 Size 1: 176 - 15 Size 0: 168 - 15 Limit -1: 160 - 8 Value -1: 148 - 4 Stride 0: 128 - 6 Value -1: 144 - 4 Limit -1: 104 - 0 Value -1: 0 - 0 Limit -1: 8 - 2 Value -1: 48 - 0 Size 0: 16 - 4 Size 1: 120 - 0 Size 1: 24 - 2 Size 1: 72 - 15 Value -1: 152 - 2 Stride 0: 80 - 4 Stride 1: 136 - 0 Stride 0: 32 - 0 Stride 1: 40 - 4 Size 0: 112 - 2 Limit -1: 56 - 2 Stride 1: 88 - 2 Size 0: 64 - 4 Value -1: 96 - commandArgs: - - {size: 8, offset: 0, name: Tensor_0_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - - {size: 8, offset: 8, name: Tensor_0_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 16, name: Tensor_0_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 24, name: Tensor_0_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 32, name: Tensor_0_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 40, name: Tensor_0_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 48, name: Tensor_2_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - - {size: 8, offset: 56, name: Tensor_2_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 64, name: Tensor_2_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 72, name: Tensor_2_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 80, name: Tensor_2_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 88, name: Tensor_2_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 96, name: Tensor_4_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - - {size: 8, offset: 104, name: Tensor_4_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 112, name: Tensor_4_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 120, name: Tensor_4_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 128, name: Tensor_4_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 136, name: Tensor_4_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 4, offset: 144, name: user_Float_Value_6, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - - {size: 4, offset: 148, name: user_Float_Value_8, variableType: {dataType: Float, pointerType: Value}, direction: read_only} - - {size: 8, offset: 152, name: Tensor_15_pointer, variableType: {dataType: Half, pointerType: PointerGlobal}, direction: read_write} - - {size: 8, offset: 160, name: Tensor_15_extent, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 168, name: Tensor_15_size_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 176, name: Tensor_15_size_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 184, name: Tensor_15_stride_0, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - - {size: 8, offset: 192, name: Tensor_15_stride_1, variableType: {dataType: Int64, pointerType: Value}, direction: read_only} - nextTag: 19 - runtimeArgsOffset: 200 -... - -.end_amdgpu_metadata - diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index e43fd18fd415..f33a0e7d5467 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -42,8 +42,8 @@ BenchmarkProblems: - KernelLanguage: ["Assembly"] ForkParameters: - CustomKernel: - - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SDVGPRToGlobalMemoryWithBuffer_LSABufferToVGPR_LSBBufferToVGPR_SwizzleScale00_SwizzleTileSize_8fd6cc113dd5231a" - args: [AddressA, ExtentA, SizeA0, SizeA1, StrideA0, StrideA1, AddressB, ExtentB, SizeB0, SizeB1, StrideB0, StrideB1, AddressC, ExtentC, SizeC0, SizeC1, StrideC0, StrideC1, AddressD, ExtentD, SizeD0, SizeD1, StrideD0, StrideD1] + - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e" + args: [ExtentA, AddressA, ExtentB, AddressB, ExtentC, AddressC, Alpha, Beta, StrideA1, SizeA0, StrideB1, StrideC1, StrideD1, ExtentD, AddressD] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index e94893af0ece..4d6d82487ba9 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1722,13 +1722,15 @@ namespace TensileLite rv.kernelName = kernelName; calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); - rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + rv.numWorkGroups.x = 256; rv.numWorkGroups.y = 1; rv.numWorkGroups.z = 1; - rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; - rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; - rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; + rv.numWorkItems.x = 8192; + rv.numWorkItems.y = 64; + rv.numWorkItems.z = 1; + + std::cout << "Workgroups: " << rv.numWorkGroups.x << "\nWorkItems: " << rv.numWorkItems.x << " " << rv.numWorkItems.y << " " << rv.numWorkItems.z << std::endl; // Temporarily set internal args manually // uint32_t gemmCount = 1; @@ -1746,84 +1748,111 @@ namespace TensileLite for(auto arg : sizeMapping.customKernel.args) { + std::cout << "RR_ARG: " << toString(arg) << std::endl; switch(arg) { case KernelArgumentType::SizeA0: + std::cout << "SizeA0" << problem.a().sizes()[0] << std::endl; rv.args.template append("SizeA0", problem.a().sizes()[0]); break; case KernelArgumentType::SizeA1: + std::cout << "SizeA1" << problem.a().sizes()[1] << std::endl; rv.args.template append("SizeA1", problem.a().sizes()[1]); break; case KernelArgumentType::SizeB0: + std::cout << "SizeB0" << problem.b().sizes()[0] << std::endl; rv.args.template append("SizeB0", problem.b().sizes()[0]); break; case KernelArgumentType::SizeB1: + std::cout << "SizeB1" << problem.b().sizes()[1] << std::endl; rv.args.template append("SizeB1", problem.b().sizes()[1]); break; case KernelArgumentType::SizeC0: + std::cout << "SizeC0" << problem.c().sizes()[0] << std::endl; rv.args.template append("SizeC0", problem.c().sizes()[0]); break; case KernelArgumentType::SizeC1: + std::cout << "SizeC1" << problem.c().sizes()[1] << std::endl; rv.args.template append("SizeC1", problem.c().sizes()[1]); break; case KernelArgumentType::SizeD0: + std::cout << "SizeD0" << problem.d().sizes()[0] << std::endl; rv.args.template append("SizeD0", problem.d().sizes()[0]); break; case KernelArgumentType::SizeD1: + std::cout << "SizeD1" << problem.d().sizes()[1] << std::endl; rv.args.template append("SizeD1", problem.d().sizes()[1]); break; case KernelArgumentType::AddressA: + if(nullptr == inputs.a) std::cout << "AddressA: NULL" << std::endl; rv.args.template append("AddressA", inputs.a); break; case KernelArgumentType::AddressB: + if(nullptr == inputs.b) std::cout << "AddressB: NULL" << std::endl; rv.args.template append("AddressB", inputs.b); break; case KernelArgumentType::AddressC: + if(nullptr == inputs.c) std::cout << "AddressC: NULL" << std::endl; rv.args.template append("AddressC", inputs.c); break; case KernelArgumentType::AddressD: + if(nullptr == inputs.d) std::cout << "AddressD: NULL" << std::endl; rv.args.template append("AddressD", inputs.d); break; case KernelArgumentType::StrideA0: + std::cout << "StrideA0" << problem.a().sizes()[0] << std::endl; rv.args.template append("StrideA0", problem.a().strides()[0]); break; case KernelArgumentType::StrideA1: + std::cout << "StrideA1" << problem.a().sizes()[0] << std::endl; rv.args.template append("StrideA1", problem.a().strides()[1]); break; case KernelArgumentType::StrideB0: + std::cout << "StrideB0" << problem.a().sizes()[0] << std::endl; rv.args.template append("StrideB0", problem.b().strides()[0]); break; case KernelArgumentType::StrideB1: + std::cout << "StrideB1" << problem.a().sizes()[0] << std::endl; rv.args.template append("StrideB1", problem.b().strides()[1]); break; case KernelArgumentType::StrideC0: + std::cout << "StrideC0" << problem.c().strides()[0] << std::endl; rv.args.template append("StrideC0", problem.c().strides()[0]); break; case KernelArgumentType::StrideC1: + std::cout << "StrideC1" << problem.c().strides()[1] << std::endl; rv.args.template append("StrideC1", problem.c().strides()[1]); break; case KernelArgumentType::StrideD0: + std::cout << "StrideD0" << problem.d().strides()[0] << std::endl; rv.args.template append("StrideD0", problem.d().strides()[0]); break; case KernelArgumentType::StrideD1: + std::cout << "StrideD1" << problem.d().strides()[1] << std::endl; rv.args.template append("StrideD1", problem.d().strides()[1]); break; case KernelArgumentType::Alpha: + // std::cout << "Alpha" << inputs.alpha << std::endl; rv.args.append("Alpha", inputs.alpha, problem.alphaType()); break; case KernelArgumentType::Beta: + // std::cout << "Beta" << inputs.beta << std::endl; rv.args.append("Beta", inputs.beta, problem.betaType()); break; case KernelArgumentType::ExtentA: + std::cout << "ExtentA" << problem.a().totalLogicalElements() << std::endl; rv.args.template append("ExtentA", problem.a().totalLogicalElements()); break; case KernelArgumentType::ExtentB: + std::cout << "ExtentB" << problem.b().totalLogicalElements() << std::endl; rv.args.template append("ExtentB", problem.b().totalLogicalElements()); break; case KernelArgumentType::ExtentC: + std::cout << "ExtentC" << problem.c().totalLogicalElements() << std::endl; rv.args.template append("ExtentC", problem.c().totalLogicalElements()); break; case KernelArgumentType::ExtentD: + std::cout << "ExtentD" << problem.d().totalLogicalElements() << std::endl; rv.args.template append("ExtentD", problem.d().totalLogicalElements()); break; case KernelArgumentType::DebugPattern: @@ -1833,6 +1862,8 @@ namespace TensileLite throw std::runtime_error(concatenate("Invalid kernel argument type for rocroller kernel: ", arg)); } } + std::cout << "A\n" << problem.a().ToString() << "\nB\n" << problem.b().ToString() << "\nC\n" << problem.c().ToString() << "\nD\n" << problem.d().ToString() << std::endl; + std::cout << "KERNELARGS:\n" << rv.args << std::endl; return rv; } @@ -3214,7 +3245,7 @@ namespace TensileLite "StreamK kernel with splitting factor < 2\n"); } } - + std::cout << "KERNELNAME:\n" << sizeMapping.customKernel.name << std::endl; if(sizeMapping.customKernel.name.empty()) { // Regular generated kernel From feb36e90ee6ecea8a5eb2a979736f1639f550010 Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Mon, 2 Mar 2026 15:24:00 -0500 Subject: [PATCH 10/58] Add data types to custom kernel arguments --- .../Tensile/Tests/custom/custom_ck.yaml | 20 +- .../include/Tensile/ContractionSolution.hpp | 37 +- .../tensilelite/include/Tensile/DataTypes.hpp | 30 ++ .../include/Tensile/DataTypes_BFloat16.hpp | 5 + .../include/Tensile/KernelArguments.hpp | 94 +++++ .../include/Tensile/Serialization/Base.hpp | 23 +- .../Tensile/Serialization/Containers.hpp | 4 +- .../Serialization/ContractionSolution.hpp | 12 + .../tensilelite/src/ContractionSolution.cpp | 346 +++++++----------- .../hipblaslt/tensilelite/src/DataTypes.cpp | 103 ++++++ 10 files changed, 436 insertions(+), 238 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 3247a92ac1df..44f4cf120dc0 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -44,7 +44,25 @@ BenchmarkProblems: ForkParameters: - CustomKernel: - name: "c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942" - args: [AddressB, AddressA, AddressD, AddressD, SizeFree1, SizeFree0, SizeSum, StrideB0, StrideA0, StrideD0, StrideD0, SizeFree2, DebugPattern, DebugPattern, DebugPattern, DebugPattern, DebugPattern, DebugPattern] + args: [ { type: address, semantic: AddressB }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressD }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeSum }, + { type: uint32, semantic: StrideB0 }, + { type: uint32, semantic: StrideA0 }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: SizeFree2 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern } ] + # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 7e1d96e72a07..5a7383386fa2 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -50,7 +50,9 @@ namespace TensileLite { - enum KernelArgumentType + + + enum CustomArgSemantic { SizeFree0, // 0 SizeFree1, // 1 @@ -71,24 +73,23 @@ namespace TensileLite Alpha, // 16 Beta, // 17 DebugPattern, // 18 - ExtentA, // 19 - ExtentB, // 20 - ExtentC, // 21 - ExtentD, // 22 - SizeA0, // 23 - SizeA1, // 24 - SizeB0, // 25 - SizeB1, // 26 - SizeC0, // 27 - SizeC1, // 28 - SizeD0, // 29 - SizeD1, // 30 - Count, // 31 + CustomArgSemantic_Count, // 19 }; - std::string toString(KernelArgumentType arg); - std::ostream& operator<<(std::ostream& stream, const KernelArgumentType& t); - std::istream& operator>>(std::istream& stream, KernelArgumentType& t); + std::string toString(CustomArgSemantic arg); + CustomArgSemantic fromStringCustomArgSemantic(std::string& str); + std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t); + std::istream& operator>>(std::istream& stream, CustomArgSemantic& t); + + struct CustomArgDefinition + { + CustomArgType type; + CustomArgSemantic semantic; + }; + + std::string toString(CustomArgDefinition arg); + std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t); + std::istream& operator>>(std::istream& stream, CustomArgDefinition& t); template struct DeviceUserArguments @@ -154,7 +155,7 @@ namespace TensileLite struct CustomKernel { std::string name; - std::vector args; + std::vector args; }; struct SizeMapping diff --git a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp index 30b4e89af4a1..d3c15b0d911b 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp @@ -376,6 +376,36 @@ namespace TensileLite std::string ToString(ConstantVariant d); bool CompareValue(const ConstantVariant& d, double value); + enum CustomArgType + { + int8, + uint8, + int16, + uint16, + int32, + uint32, + int64, + uint64, + float4, + float6, + float8, + bfloat8, + float16, + bfloat16, + float32, + tfloat32, + float64, + // Complex types? + boolean, + address, + CustomArgType_Count, + }; + + std::string toString(CustomArgType arg); + CustomArgType fromStringCustomArgType(std::string& str); + std::ostream& operator<<(std::ostream& stream, const CustomArgType& t); + std::istream& operator>>(std::istream& stream, CustomArgType& t); + /** * @} */ diff --git a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes_BFloat16.hpp b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes_BFloat16.hpp index e703abbafb54..959c14a4dd49 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes_BFloat16.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes_BFloat16.hpp @@ -92,6 +92,11 @@ namespace TensileLite return static_cast(float(*this)); } + explicit operator uint8_t() const + { + return static_cast(float(*this)); + } + uint16_t data; private: diff --git a/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp b/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp index 69f509b72809..2c74facfb487 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp @@ -152,6 +152,9 @@ namespace TensileLite template void appendUnbound(std::string const& name); + template + void appendCustomType(std::string const& name, T value, CustomArgType type); + template void bind(std::string const& name, T value); @@ -304,6 +307,97 @@ namespace TensileLite append(name, static_cast(0), false); } + template + inline void KernelArguments::appendCustomType(std::string const& name, T value, CustomArgType type) + { + switch(type) + { + case CustomArgType::int8: + return append(name, static_cast(value)); + case CustomArgType::uint8: + return append(name, static_cast(value)); + case CustomArgType::int16: + return append(name, static_cast(value)); + case CustomArgType::uint16: + return append(name, static_cast(value)); + case CustomArgType::int32: + return append(name, static_cast(value)); + case CustomArgType::uint32: + return append(name, static_cast(value)); + case CustomArgType::int64: + return append(name, static_cast(value)); + case CustomArgType::uint64: + return append(name, static_cast(value)); + // case CustomArgType::float4: + // return append(name, static_cast(value)); + // case CustomArgType::float6: + // return append(name, static_cast(value)); + case CustomArgType::float8: + return append(name, static_cast(value)); + case CustomArgType::bfloat8: + return append(name, static_cast(value)); + case CustomArgType::float16: + return append(name, static_cast(value)); + case CustomArgType::bfloat16: + return append(name, static_cast(value)); + case CustomArgType::float32: + return append(name, static_cast(value)); + case CustomArgType::tfloat32: + return append(name, static_cast(value)); + case CustomArgType::float64: + return append(name, static_cast(value)); + case CustomArgType::boolean: + return append(name, static_cast(value)); + // case CustomArgType::address: + // return append(name, static_cast(value)); + case CustomArgType::float4: + case CustomArgType::float6: + case CustomArgType::address: + case CustomArgType::CustomArgType_Count: + throw std::runtime_error("Unsupported CustomArgType append type."); + } + } + + template <> + inline void KernelArguments::appendCustomType>(std::string const& name, std::complex value, CustomArgType type) + { + // Use real part if user requests cast from complex + appendCustomType(name, value.real(), type); + } + + template <> + inline void KernelArguments::appendCustomType>(std::string const& name, std::complex value, CustomArgType type) + { + // Use real part if user requests cast from complex + appendCustomType(name, value.real(), type); + } + + template <> + inline void KernelArguments::appendCustomType(std::string const& name, Int8x4 value, CustomArgType type) + { + // Use first value for conversion for now + appendCustomType(name, value.a, type); + } + + template <> + inline void KernelArguments::appendCustomType(std::string const& name, BFloat16 value, CustomArgType type) + { + // Convert to float first to facilitate other conversions + appendCustomType(name, static_cast(value), type); + } + + template <> + inline void KernelArguments::appendCustomType(std::string const& name, ConstantVariant value, CustomArgType type) + { + // Read variant with type used to set it, and call template function to convert to target type + auto visitor = [this, &name, &type](auto&& arg) { + appendCustomType(name, arg, type); + }; + std::visit(visitor, value); + } + + + template inline void KernelArguments::bind(std::string const& name, T value) { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index d4c9f85b7c02..903cf02c9c86 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -368,15 +368,30 @@ namespace TensileLite }; template - struct EnumTraits + struct EnumTraits { using iot = IOTraits; - static void enumeration(IO& io, KernelArgumentType& value) + static void enumeration(IO& io, CustomArgType& value) { - for(int i = 0; i < static_cast(KernelArgumentType::Count); i++) + for(int i = 0; i < static_cast(CustomArgType::CustomArgType_Count); i++) { - auto const& info = static_cast(i); + auto const& info = static_cast(i); + iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); + } + } + }; + + template + struct EnumTraits + { + using iot = IOTraits; + + static void enumeration(IO& io, CustomArgSemantic& value) + { + for(int i = 0; i < static_cast(CustomArgSemantic::CustomArgSemantic_Count); i++) + { + auto const& info = static_cast(i); iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); } } diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp index 96b866873273..b125a6c81436 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp @@ -202,8 +202,8 @@ namespace TensileLite TENSILE_SERIALIZE_VECTOR(true, TensileLite::MLPClassification::ResBlock); template - struct SequenceTraits, IO> - : public DefaultSequenceTraits, IO, false> + struct SequenceTraits, IO> + : public DefaultSequenceTraits, IO, false> { }; diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 4d69f096946f..4f92b6400c62 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -86,6 +86,18 @@ namespace TensileLite const static bool flow = false; }; + template + struct MappingTraits + { + using iot = IOTraits; + static void mapping(IO& io, CustomArgDefinition& s) + { + iot::mapRequired(io, "type", s.type); + iot::mapRequired(io, "semantic", s.semantic); + } + const static bool flow = true; + }; + template struct MappingTraits { diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 4d6d82487ba9..59feb56db2a4 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -53,218 +53,132 @@ namespace TensileLite { - - std::string toString(KernelArgumentType arg) + std::string toString(CustomArgSemantic arg) { switch(arg) { - case KernelArgumentType::SizeFree0: + case CustomArgSemantic::SizeFree0: return "SizeFree0"; - case KernelArgumentType::SizeFree1: + case CustomArgSemantic::SizeFree1: return "SizeFree1"; - case KernelArgumentType::SizeFree2: + case CustomArgSemantic::SizeFree2: return "SizeFree2"; - case KernelArgumentType::SizeSum: + case CustomArgSemantic::SizeSum: return "SizeSum"; - case KernelArgumentType::AddressA: + case CustomArgSemantic::AddressA: return "AddressA"; - case KernelArgumentType::AddressB: + case CustomArgSemantic::AddressB: return "AddressB"; - case KernelArgumentType::AddressC: + case CustomArgSemantic::AddressC: return "AddressC"; - case KernelArgumentType::AddressD: + case CustomArgSemantic::AddressD: return "AddressD"; - case KernelArgumentType::StrideA0: + case CustomArgSemantic::StrideA0: return "StrideA0"; - case KernelArgumentType::StrideA1: + case CustomArgSemantic::StrideA1: return "StrideA1"; - case KernelArgumentType::StrideB0: + case CustomArgSemantic::StrideB0: return "StrideB0"; - case KernelArgumentType::StrideB1: + case CustomArgSemantic::StrideB1: return "StrideB1"; - case KernelArgumentType::StrideC0: + case CustomArgSemantic::StrideC0: return "StrideC0"; - case KernelArgumentType::StrideC1: + case CustomArgSemantic::StrideC1: return "StrideC1"; - case KernelArgumentType::StrideD0: + case CustomArgSemantic::StrideD0: return "StrideD0"; - case KernelArgumentType::StrideD1: + case CustomArgSemantic::StrideD1: return "StrideD1"; - case KernelArgumentType::Alpha: + case CustomArgSemantic::Alpha: return "Alpha"; - case KernelArgumentType::Beta: + case CustomArgSemantic::Beta: return "Beta"; - case KernelArgumentType::DebugPattern: + case CustomArgSemantic::DebugPattern: return "DebugPattern"; - case KernelArgumentType::ExtentA: - return "ExtentA"; - case KernelArgumentType::ExtentB: - return "ExtentB"; - case KernelArgumentType::ExtentC: - return "ExtentC"; - case KernelArgumentType::ExtentD: - return "ExtentD"; - case KernelArgumentType::SizeA0: - return "SizeA0"; - case KernelArgumentType::SizeA1: - return "SizeA1"; - case KernelArgumentType::SizeB0: - return "SizeB0"; - case KernelArgumentType::SizeB1: - return "SizeB1"; - case KernelArgumentType::SizeC0: - return "SizeC0"; - case KernelArgumentType::SizeC1: - return "SizeC1"; - case KernelArgumentType::SizeD0: - return "SizeD0"; - case KernelArgumentType::SizeD1: - return "SizeD1"; - case KernelArgumentType::Count: + case CustomArgSemantic::CustomArgSemantic_Count: break; } throw std::runtime_error( - concatenate("Invalid KernelArgumentType value: ", static_cast(arg))); + concatenate("Invalid CustomArgSemantic value: ", static_cast(arg))); } - std::ostream& operator<<(std::ostream& stream, const KernelArgumentType& t) + CustomArgSemantic fromStringCustomArgSemantic(std::string& str) + { + + if(str == toString(CustomArgSemantic::SizeFree0)) + return CustomArgSemantic::SizeFree0; + else if(str == toString(CustomArgSemantic::SizeFree1)) + return CustomArgSemantic::SizeFree1; + else if(str == toString(CustomArgSemantic::SizeFree2)) + return CustomArgSemantic::SizeFree2; + else if(str == toString(CustomArgSemantic::SizeSum)) + return CustomArgSemantic::SizeSum; + else if(str == toString(CustomArgSemantic::AddressA)) + return CustomArgSemantic::AddressA; + else if(str == toString(CustomArgSemantic::AddressB)) + return CustomArgSemantic::AddressB; + else if(str == toString(CustomArgSemantic::AddressC)) + return CustomArgSemantic::AddressC; + else if(str == toString(CustomArgSemantic::AddressD)) + return CustomArgSemantic::AddressD; + else if(str == toString(CustomArgSemantic::StrideA0)) + return CustomArgSemantic::StrideA0; + else if(str == toString(CustomArgSemantic::StrideA1)) + return CustomArgSemantic::StrideA1; + else if(str == toString(CustomArgSemantic::StrideB0)) + return CustomArgSemantic::StrideB0; + else if(str == toString(CustomArgSemantic::StrideB1)) + return CustomArgSemantic::StrideB1; + else if(str == toString(CustomArgSemantic::StrideC0)) + return CustomArgSemantic::StrideC0; + else if(str == toString(CustomArgSemantic::StrideC1)) + return CustomArgSemantic::StrideC1; + else if(str == toString(CustomArgSemantic::StrideD0)) + return CustomArgSemantic::StrideD0; + else if(str == toString(CustomArgSemantic::StrideD1)) + return CustomArgSemantic::StrideD1; + else if(str == toString(CustomArgSemantic::Alpha)) + return CustomArgSemantic::Alpha; + else if(str == toString(CustomArgSemantic::Beta)) + return CustomArgSemantic::Beta; + else if(str == toString(CustomArgSemantic::DebugPattern)) + return CustomArgSemantic::DebugPattern; + else + throw std::runtime_error(concatenate("Invalid argument type: ", str)); + return CustomArgSemantic::CustomArgSemantic_Count; + } + + std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t) { return stream << toString(t); } - std::istream& operator>>(std::istream& stream, KernelArgumentType& t) + std::istream& operator>>(std::istream& stream, CustomArgSemantic& t) { std::string strValue; stream >> strValue; - if(strValue == toString(KernelArgumentType::SizeFree0)) - { - t = KernelArgumentType::SizeFree0; - } - else if(strValue == toString(KernelArgumentType::SizeFree1)) - { - t = KernelArgumentType::SizeFree1; - } - else if(strValue == toString(KernelArgumentType::SizeFree2)) - { - t = KernelArgumentType::SizeFree2; - } - else if(strValue == toString(KernelArgumentType::SizeSum)) - { - t = KernelArgumentType::SizeSum; - } - else if(strValue == toString(KernelArgumentType::AddressA)) - { - t = KernelArgumentType::AddressA; - } - else if(strValue == toString(KernelArgumentType::AddressB)) - { - t = KernelArgumentType::AddressB; - } - else if(strValue == toString(KernelArgumentType::AddressC)) - { - t = KernelArgumentType::AddressC; - } - else if(strValue == toString(KernelArgumentType::AddressD)) - { - t = KernelArgumentType::AddressD; - } - else if(strValue == toString(KernelArgumentType::StrideA0)) - { - t = KernelArgumentType::StrideA0; - } - else if(strValue == toString(KernelArgumentType::StrideA1)) - { - t = KernelArgumentType::StrideA1; - } - else if(strValue == toString(KernelArgumentType::StrideB0)) - { - t = KernelArgumentType::StrideB0; - } - else if(strValue == toString(KernelArgumentType::StrideB1)) - { - t = KernelArgumentType::StrideB1; - } - else if(strValue == toString(KernelArgumentType::StrideC0)) - { - t = KernelArgumentType::StrideC0; - } - else if(strValue == toString(KernelArgumentType::StrideC1)) - { - t = KernelArgumentType::StrideC1; - } - else if(strValue == toString(KernelArgumentType::StrideD0)) - { - t = KernelArgumentType::StrideD0; - } - else if(strValue == toString(KernelArgumentType::StrideD1)) - { - t = KernelArgumentType::StrideD1; - } - else if(strValue == toString(KernelArgumentType::Alpha)) - { - t = KernelArgumentType::Alpha; - } - else if(strValue == toString(KernelArgumentType::Beta)) - { - t = KernelArgumentType::Beta; - } - else if(strValue == toString(KernelArgumentType::DebugPattern)) - { - t = KernelArgumentType::DebugPattern; - } - else if(strValue == toString(KernelArgumentType::ExtentA)) - { - t = KernelArgumentType::ExtentA; - } - else if(strValue == toString(KernelArgumentType::ExtentB)) - { - t = KernelArgumentType::ExtentB; - } - else if(strValue == toString(KernelArgumentType::ExtentC)) - { - t = KernelArgumentType::ExtentC; - } - else if(strValue == toString(KernelArgumentType::ExtentD)) - { - t = KernelArgumentType::ExtentD; - } - else if(strValue == toString(KernelArgumentType::SizeA0)) - { - t = KernelArgumentType::SizeA0; - } - else if(strValue == toString(KernelArgumentType::SizeA1)) - { - t = KernelArgumentType::SizeA1; - } - else if(strValue == toString(KernelArgumentType::SizeB0)) - { - t = KernelArgumentType::SizeB0; - } - else if(strValue == toString(KernelArgumentType::SizeB1)) - { - t = KernelArgumentType::SizeB1; - } - else if(strValue == toString(KernelArgumentType::SizeC0)) - { - t = KernelArgumentType::SizeC0; - } - else if(strValue == toString(KernelArgumentType::SizeC1)) - { - t = KernelArgumentType::SizeC1; - } - else if(strValue == toString(KernelArgumentType::SizeD0)) - { - t = KernelArgumentType::SizeD0; - } - else if(strValue == toString(KernelArgumentType::SizeD1)) - { - t = KernelArgumentType::SizeD1; - } - else - { - throw std::runtime_error(concatenate("Invalid argument type: ", strValue)); - } + t = fromStringCustomArgSemantic(strValue); + return stream; + } + + std::string toString(CustomArgDefinition arg) + { + return toString(arg.type) + " " + toString(arg.semantic); + } + + std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t) + { + return stream << toString(t); + } + + std::istream& operator>>(std::istream& stream, CustomArgDefinition& t) + { + std::string strType; + std::string strSemantic; + stream >> strType >> strSemantic; + t.type = fromStringCustomArgType(strType); + t.semantic = fromStringCustomArgSemantic(strSemantic); return stream; } @@ -1604,7 +1518,7 @@ namespace TensileLite numWorkGroups.x = CeilDivide(numWorkGroups.x, sizeMapping.macroTile.x); numWorkGroups.y = CeilDivide(numWorkGroups.y, sizeMapping.macroTile.y); } - + template KernelInvocation ContractionSolution::generateCustomCall(ContractionSolution::Problem const& problem, ContractionInputs const& inputs, @@ -1640,65 +1554,71 @@ namespace TensileLite uint32_t debugPattern = 0xDB000001; + if(T_Debug) + std::cout << "Custom call arguments:" << std::endl; + for(auto arg : sizeMapping.customKernel.args) { - switch(arg) + if(T_Debug) + std::cout << "Type: " << toString(arg.type) << " Semantic: " << toString(arg.semantic) << std::endl; + + switch(arg.semantic) { - case KernelArgumentType::SizeFree0: - rv.args.template append("SizeFree0", problem.problemSizes()[0]); + case CustomArgSemantic::SizeFree0: + rv.args.appendCustomType("SizeFree0", problem.problemSizes()[0], arg.type); break; - case KernelArgumentType::SizeFree1: - rv.args.template append("SizeFree1", problem.problemSizes()[1]); + case CustomArgSemantic::SizeFree1: + rv.args.appendCustomType("SizeFree1", problem.problemSizes()[1], arg.type); break; - case KernelArgumentType::SizeFree2: - rv.args.template append("SizeFree2", problem.problemSizes()[2]); + case CustomArgSemantic::SizeFree2: + rv.args.appendCustomType("SizeFree2", problem.problemSizes()[2], arg.type); break; - case KernelArgumentType::SizeSum: - rv.args.template append("SizeSum", problem.problemSizes()[3]); + case CustomArgSemantic::SizeSum: + rv.args.appendCustomType("SizeSum", problem.problemSizes()[3], arg.type); break; - case KernelArgumentType::AddressA: + case CustomArgSemantic::AddressA: rv.args.template append("AddressA", inputs.a); break; - case KernelArgumentType::AddressB: + case CustomArgSemantic::AddressB: rv.args.template append("AddressB", inputs.b); break; - case KernelArgumentType::AddressC: + case CustomArgSemantic::AddressC: rv.args.template append("AddressC", inputs.c); break; - case KernelArgumentType::AddressD: + case CustomArgSemantic::AddressD: rv.args.template append("AddressD", inputs.d); break; - case KernelArgumentType::StrideA0: - rv.args.template append("StrideA0", problem.a().strides()[1]); + case CustomArgSemantic::StrideA0: + rv.args.appendCustomType("StrideA0", problem.a().strides()[1], arg.type); break; - case KernelArgumentType::StrideA1: - rv.args.template append("StrideA1", problem.a().strides()[2]); + case CustomArgSemantic::StrideA1: + rv.args.appendCustomType("StrideA1", problem.a().strides()[2], arg.type); break; - case KernelArgumentType::StrideB0: - rv.args.template append("StrideB0", problem.b().strides()[1]); + case CustomArgSemantic::StrideB0: + rv.args.appendCustomType("StrideB0", problem.b().strides()[1], arg.type); break; - case KernelArgumentType::StrideB1: - rv.args.template append("StrideB1", problem.b().strides()[2]); + case CustomArgSemantic::StrideB1: + rv.args.appendCustomType("StrideB1", problem.b().strides()[2], arg.type); break; - case KernelArgumentType::StrideC0: - rv.args.template append("StrideC0", problem.c().strides()[1]); + case CustomArgSemantic::StrideC0: + rv.args.appendCustomType("StrideC0", problem.c().strides()[1], arg.type); break; - case KernelArgumentType::StrideC1: - rv.args.template append("StrideC1", problem.c().strides()[2]); + case CustomArgSemantic::StrideC1: + rv.args.appendCustomType("StrideC1", problem.c().strides()[2], arg.type); break; - case KernelArgumentType::StrideD0: - rv.args.template append("StrideD0", problem.d().strides()[1]); + case CustomArgSemantic::StrideD0: + rv.args.appendCustomType("StrideD0", problem.d().strides()[1], arg.type); break; - case KernelArgumentType::StrideD1: - rv.args.template append("StrideD1", problem.d().strides()[2]); + case CustomArgSemantic::StrideD1: + rv.args.appendCustomType("StrideD1", problem.d().strides()[2], arg.type); break; - case KernelArgumentType::Alpha: - rv.args.append("Alpha", inputs.alpha, problem.alphaType()); + case CustomArgSemantic::Alpha: + rv.args.appendCustomType("Alpha", inputs.alpha, arg.type); break; - case KernelArgumentType::Beta: - rv.args.append("Beta", inputs.beta, problem.betaType()); + case CustomArgSemantic::Beta: + rv.args.appendCustomType("Beta", inputs.beta, arg.type); break; - case KernelArgumentType::DebugPattern: + case CustomArgSemantic::DebugPattern: rv.args.template append("DebugPattern", debugPattern); ++debugPattern; break; @@ -2159,7 +2079,7 @@ namespace TensileLite rv.numWorkItems.x / rv.workGroupSize.x / rv.workGroupSize.y / rv.workGroupSize.z); kernelArgs(0, - (uint32_t)KERNELARGTYPE::NORMAL, + (uint32_t)KERNELARGTYPE::NORMAL, rv.args, 0, &hardware, diff --git a/projects/hipblaslt/tensilelite/src/DataTypes.cpp b/projects/hipblaslt/tensilelite/src/DataTypes.cpp index e05229f9850a..2e7217bcbce0 100644 --- a/projects/hipblaslt/tensilelite/src/DataTypes.cpp +++ b/projects/hipblaslt/tensilelite/src/DataTypes.cpp @@ -337,4 +337,107 @@ namespace TensileLite throw std::runtime_error("Unsupported variant cast type."); } } + + std::string toString(CustomArgType arg) + { + switch(arg) + { + case CustomArgType::int8: + return "int8"; + case CustomArgType::uint8: + return "uint8"; + case CustomArgType::int16: + return "int16"; + case CustomArgType::uint16: + return "uint16"; + case CustomArgType::int32: + return "int32"; + case CustomArgType::uint32: + return "uint32"; + case CustomArgType::int64: + return "int64"; + case CustomArgType::uint64: + return "uint64"; + case CustomArgType::float4: + return "float4"; + case CustomArgType::float6: + return "float6"; + case CustomArgType::float8: + return "float8"; + case CustomArgType::bfloat8: + return "bfloat8"; + case CustomArgType::float16: + return "float16"; + case CustomArgType::bfloat16: + return "bfloat16"; + case CustomArgType::float32: + return "float32"; + case CustomArgType::tfloat32: + return "tfloat32"; + case CustomArgType::float64: + return "float64"; + case CustomArgType::boolean: + return "boolean"; + case CustomArgType::address: + return "address"; + case CustomArgType::CustomArgType_Count: + break; + } + + throw std::runtime_error(concatenate("Invalid CustomArgType value: ", static_cast(arg))); + } + + CustomArgType fromStringCustomArgType(std::string& str) + { + if(str == toString(CustomArgType::int8)) + return CustomArgType::int8; + else if(str == toString(CustomArgType::uint8)) + return CustomArgType::uint8; + else if(str == toString(CustomArgType::int32)) + return CustomArgType::int32; + else if(str == toString(CustomArgType::uint32)) + return CustomArgType::uint32; + else if(str == toString(CustomArgType::int64)) + return CustomArgType::int64; + else if(str == toString(CustomArgType::uint64)) + return CustomArgType::uint64; + else if(str == toString(CustomArgType::float4)) + return CustomArgType::float4; + else if(str == toString(CustomArgType::float6)) + return CustomArgType::float6; + else if(str == toString(CustomArgType::float8)) + return CustomArgType::float8; + else if(str == toString(CustomArgType::bfloat8)) + return CustomArgType::bfloat8; + else if(str == toString(CustomArgType::float16)) + return CustomArgType::float16; + else if(str == toString(CustomArgType::bfloat16)) + return CustomArgType::bfloat16; + else if(str == toString(CustomArgType::float32)) + return CustomArgType::float32; + else if(str == toString(CustomArgType::tfloat32)) + return CustomArgType::tfloat32; + else if(str == toString(CustomArgType::float64)) + return CustomArgType::float64; + else if(str == toString(CustomArgType::boolean)) + return CustomArgType::boolean; + else if(str == toString(CustomArgType::address)) + return CustomArgType::address; + else + throw std::runtime_error(concatenate("Invalid argument type: ", str)); + return CustomArgType::CustomArgType_Count; + } + + std::ostream& operator<<(std::ostream& stream, const CustomArgType& t) + { + return stream << toString(t); + } + + std::istream& operator>>(std::istream& stream, CustomArgType& t) + { + std::string strValue; + stream >> strValue; + t = fromStringCustomArgType(strValue); + return stream; + } } // namespace TensileLite From 696a9749d2807e653fd311bf9d143690c476f2cd Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Mon, 2 Mar 2026 21:43:53 +0000 Subject: [PATCH 11/58] Remove custom RR logic and use datatypes --- .../Tensile/Tests/custom/custom_rr.yaml | 16 +- .../include/Tensile/ContractionSolution.hpp | 6 - .../tensilelite/src/ContractionSolution.cpp | 166 ------------------ 3 files changed, 15 insertions(+), 173 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index f33a0e7d5467..c0dd32a9f9e3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -43,7 +43,21 @@ BenchmarkProblems: ForkParameters: - CustomKernel: - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e" - args: [ExtentA, AddressA, ExtentB, AddressB, ExtentC, AddressC, Alpha, Beta, StrideA1, SizeA0, StrideB1, StrideC1, StrideD1, ExtentD, AddressD] + args: [ { type: int64, semantic: StrideA1 }, + { type: address, semantic: AddressA }, + { type: int64, semantic: StrideB1 }, + { type: address, semantic: AddressB }, + { type: int64, semantic: StrideC1 }, + { type: address, semantic: AddressC }, + { type: float32, semantic: Alpha }, + { type: float32, semantic: Beta }, + { type: int64, semantic: StrideA0 }, + { type: int64, semantic: SizeA0 }, + { type: int64, semantic: StrideB0 }, + { type: int64, semantic: StrideC0 }, + { type: int64, semantic: StrideD0 }, + { type: int64, semantic: StrideD1 }, + { type: address, semantic: AddressD } ] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 5a7383386fa2..be9ba5cd4c10 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -503,12 +503,6 @@ namespace TensileLite Hardware const& hardware, StreamKSettings const& sk) const; - template - KernelInvocation generateRocRollerCall(ContractionSolution::Problem const& problem, - ContractionInputs const& inputs, - Hardware const& hardware, - StreamKSettings const& sk) const; - template KernelInvocation generateSingleCall(Problem const& problem, ContractionInputs const& inputs, diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 59feb56db2a4..1836d277579a 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1629,164 +1629,6 @@ namespace TensileLite return rv; } - template - KernelInvocation ContractionSolution::generateRocRollerCall(ContractionSolution::Problem const& problem, - ContractionInputs const& inputs, - Hardware const& hardware, - StreamKSettings const& sk) const - { - KernelInvocation rv; - rv.isSingleCall = true; - rv.args = KernelArguments(T_Debug); - rv.args.reserve(1024, 128); - rv.kernelName = kernelName; - - calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); - rv.numWorkGroups.x = 256; - rv.numWorkGroups.y = 1; - rv.numWorkGroups.z = 1; - - rv.numWorkItems.x = 8192; - rv.numWorkItems.y = 64; - rv.numWorkItems.z = 1; - - std::cout << "Workgroups: " << rv.numWorkGroups.x << "\nWorkItems: " << rv.numWorkItems.x << " " << rv.numWorkItems.y << " " << rv.numWorkItems.z << std::endl; - - // Temporarily set internal args manually - // uint32_t gemmCount = 1; - // gemmCount = gemmCount & 0x3FFFFFFF; - // rv.args.template append("gemm_count", gemmCount); - // uint32_t internalArg0 = 1048577; - // rv.args.template append("internalArgs", internalArg0); - // int32_t internalArg1 = 436731905; - // rv.args.template append("internalArgs1", internalArg1); - - // uint32_t numWorkGroups = getNumWorkGroups(rv); - // rv.args.template append("numWorkGroups", numWorkGroups); - - // uint32_t debugPattern = 0xDB000001; - - for(auto arg : sizeMapping.customKernel.args) - { - std::cout << "RR_ARG: " << toString(arg) << std::endl; - switch(arg) - { - case KernelArgumentType::SizeA0: - std::cout << "SizeA0" << problem.a().sizes()[0] << std::endl; - rv.args.template append("SizeA0", problem.a().sizes()[0]); - break; - case KernelArgumentType::SizeA1: - std::cout << "SizeA1" << problem.a().sizes()[1] << std::endl; - rv.args.template append("SizeA1", problem.a().sizes()[1]); - break; - case KernelArgumentType::SizeB0: - std::cout << "SizeB0" << problem.b().sizes()[0] << std::endl; - rv.args.template append("SizeB0", problem.b().sizes()[0]); - break; - case KernelArgumentType::SizeB1: - std::cout << "SizeB1" << problem.b().sizes()[1] << std::endl; - rv.args.template append("SizeB1", problem.b().sizes()[1]); - break; - case KernelArgumentType::SizeC0: - std::cout << "SizeC0" << problem.c().sizes()[0] << std::endl; - rv.args.template append("SizeC0", problem.c().sizes()[0]); - break; - case KernelArgumentType::SizeC1: - std::cout << "SizeC1" << problem.c().sizes()[1] << std::endl; - rv.args.template append("SizeC1", problem.c().sizes()[1]); - break; - case KernelArgumentType::SizeD0: - std::cout << "SizeD0" << problem.d().sizes()[0] << std::endl; - rv.args.template append("SizeD0", problem.d().sizes()[0]); - break; - case KernelArgumentType::SizeD1: - std::cout << "SizeD1" << problem.d().sizes()[1] << std::endl; - rv.args.template append("SizeD1", problem.d().sizes()[1]); - break; - case KernelArgumentType::AddressA: - if(nullptr == inputs.a) std::cout << "AddressA: NULL" << std::endl; - rv.args.template append("AddressA", inputs.a); - break; - case KernelArgumentType::AddressB: - if(nullptr == inputs.b) std::cout << "AddressB: NULL" << std::endl; - rv.args.template append("AddressB", inputs.b); - break; - case KernelArgumentType::AddressC: - if(nullptr == inputs.c) std::cout << "AddressC: NULL" << std::endl; - rv.args.template append("AddressC", inputs.c); - break; - case KernelArgumentType::AddressD: - if(nullptr == inputs.d) std::cout << "AddressD: NULL" << std::endl; - rv.args.template append("AddressD", inputs.d); - break; - case KernelArgumentType::StrideA0: - std::cout << "StrideA0" << problem.a().sizes()[0] << std::endl; - rv.args.template append("StrideA0", problem.a().strides()[0]); - break; - case KernelArgumentType::StrideA1: - std::cout << "StrideA1" << problem.a().sizes()[0] << std::endl; - rv.args.template append("StrideA1", problem.a().strides()[1]); - break; - case KernelArgumentType::StrideB0: - std::cout << "StrideB0" << problem.a().sizes()[0] << std::endl; - rv.args.template append("StrideB0", problem.b().strides()[0]); - break; - case KernelArgumentType::StrideB1: - std::cout << "StrideB1" << problem.a().sizes()[0] << std::endl; - rv.args.template append("StrideB1", problem.b().strides()[1]); - break; - case KernelArgumentType::StrideC0: - std::cout << "StrideC0" << problem.c().strides()[0] << std::endl; - rv.args.template append("StrideC0", problem.c().strides()[0]); - break; - case KernelArgumentType::StrideC1: - std::cout << "StrideC1" << problem.c().strides()[1] << std::endl; - rv.args.template append("StrideC1", problem.c().strides()[1]); - break; - case KernelArgumentType::StrideD0: - std::cout << "StrideD0" << problem.d().strides()[0] << std::endl; - rv.args.template append("StrideD0", problem.d().strides()[0]); - break; - case KernelArgumentType::StrideD1: - std::cout << "StrideD1" << problem.d().strides()[1] << std::endl; - rv.args.template append("StrideD1", problem.d().strides()[1]); - break; - case KernelArgumentType::Alpha: - // std::cout << "Alpha" << inputs.alpha << std::endl; - rv.args.append("Alpha", inputs.alpha, problem.alphaType()); - break; - case KernelArgumentType::Beta: - // std::cout << "Beta" << inputs.beta << std::endl; - rv.args.append("Beta", inputs.beta, problem.betaType()); - break; - case KernelArgumentType::ExtentA: - std::cout << "ExtentA" << problem.a().totalLogicalElements() << std::endl; - rv.args.template append("ExtentA", problem.a().totalLogicalElements()); - break; - case KernelArgumentType::ExtentB: - std::cout << "ExtentB" << problem.b().totalLogicalElements() << std::endl; - rv.args.template append("ExtentB", problem.b().totalLogicalElements()); - break; - case KernelArgumentType::ExtentC: - std::cout << "ExtentC" << problem.c().totalLogicalElements() << std::endl; - rv.args.template append("ExtentC", problem.c().totalLogicalElements()); - break; - case KernelArgumentType::ExtentD: - std::cout << "ExtentD" << problem.d().totalLogicalElements() << std::endl; - rv.args.template append("ExtentD", problem.d().totalLogicalElements()); - break; - case KernelArgumentType::DebugPattern: - // N/A - break; - default: - throw std::runtime_error(concatenate("Invalid kernel argument type for rocroller kernel: ", arg)); - } - } - std::cout << "A\n" << problem.a().ToString() << "\nB\n" << problem.b().ToString() << "\nC\n" << problem.c().ToString() << "\nD\n" << problem.d().ToString() << std::endl; - std::cout << "KERNELARGS:\n" << rv.args << std::endl; - return rv; - } - template KernelInvocation ContractionSolution::generateSingleCall(ContractionSolution::Problem const& problem, @@ -3174,14 +3016,6 @@ namespace TensileLite else rv.push_back(generateSingleCall(problem, inputs, hardware, sk)); } - else if(sizeMapping.customKernel.name.find("RRGEMM_") != std::string::npos) - { - // RocRoller kernel - if(debug) - rv.push_back(generateRocRollerCall(problem, inputs, hardware, sk)); - else - rv.push_back(generateRocRollerCall(problem, inputs, hardware, sk)); - } else { // Custom kernel From 670c33f39c9d4478de8caba51353ed244d18e23b Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Mon, 2 Mar 2026 21:45:50 +0000 Subject: [PATCH 12/58] Rm debug message --- projects/hipblaslt/tensilelite/src/ContractionSolution.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 1836d277579a..13f627496768 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -3007,7 +3007,7 @@ namespace TensileLite "StreamK kernel with splitting factor < 2\n"); } } - std::cout << "KERNELNAME:\n" << sizeMapping.customKernel.name << std::endl; + if(sizeMapping.customKernel.name.empty()) { // Regular generated kernel From c4e65f2215bea7e80beeed6d5517c53cb7d91b51 Mon Sep 17 00:00:00 2001 From: Andrew Whittle Date: Wed, 4 Mar 2026 18:14:01 +0000 Subject: [PATCH 13/58] Tweaks for RR custom kernel --- .../tensilelite/Tensile/Tests/custom/custom_rr.yaml | 4 ++-- projects/hipblaslt/tensilelite/src/ContractionSolution.cpp | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index c0dd32a9f9e3..017c3258e25d 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -52,14 +52,14 @@ BenchmarkProblems: { type: float32, semantic: Alpha }, { type: float32, semantic: Beta }, { type: int64, semantic: StrideA0 }, - { type: int64, semantic: SizeA0 }, + { type: int64, semantic: SizeSum }, { type: int64, semantic: StrideB0 }, { type: int64, semantic: StrideC0 }, { type: int64, semantic: StrideD0 }, { type: int64, semantic: StrideD1 }, { type: address, semantic: AddressD } ] - MatrixInstruction: - - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 + - [16,16,16, 1, 1, 2,2, 2,2] # 256 x 128 - PreloadKernArgs: [False] # - PrefetchGlobalRead: [2] # - PrefetchLocalRead: [1] diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 13f627496768..5a7b9f47c54c 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1532,9 +1532,9 @@ namespace TensileLite rv.kernelName = kernelName; calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); - rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); - rv.numWorkGroups.y = 1; - rv.numWorkGroups.z = 1; + // rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + // rv.numWorkGroups.y = 1; + // rv.numWorkGroups.z = 1; rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; From ee38e6c96d1e7e8296b8e2ec28b302aa732897ca Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Fri, 6 Mar 2026 11:25:45 -0500 Subject: [PATCH 14/58] Define launch grid parameters --- .../tensilelite/Tensile/Contractions.py | 4 +- .../Tensile/Tests/custom/custom_ck.yaml | 3 + .../include/Tensile/ContractionSolution.hpp | 38 +++- .../include/Tensile/Serialization/Base.hpp | 14 ++ .../Tensile/Serialization/Containers.hpp | 6 + .../Serialization/ContractionSolution.hpp | 3 + .../tensilelite/src/ContractionSolution.cpp | 168 +++++++++++++++++- 7 files changed, 222 insertions(+), 14 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index db860d242683..7ebf083851d0 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -582,11 +582,11 @@ def FromOriginalState(cls, d, problemType, morePreds=[]): return cls.And(predicates) class CustomKernel: - StateKeys = ['name', 'args'] + StateKeys = ['name', 'args', 'macrotile', 'threads', 'grid'] @classmethod def FromOriginalState(cls, d): - return cls(name=d['name'], args=d['args']) + return cls(name=d['name'], args=d['args'], macrotile=d['macrotile'], threads=d['threads'], grid=d['grid']) def __init__(self, **kwargs): for (key, value) in list(kwargs.items()): diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 44f4cf120dc0..0d47def6c172 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -63,6 +63,9 @@ BenchmarkProblems: { type: uint32, semantic: DebugPattern }, { type: uint32, semantic: DebugPattern } ] # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesXYBatch, One, One] - MatrixInstruction: - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - PreloadKernArgs: [False] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index be9ba5cd4c10..2c30e8d58d10 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -50,8 +50,6 @@ namespace TensileLite { - - enum CustomArgSemantic { SizeFree0, // 0 @@ -91,6 +89,34 @@ namespace TensileLite std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t); std::istream& operator>>(std::istream& stream, CustomArgDefinition& t); + enum CustomGridSize + { + One, + TilesX, + TilesY, + Batch, + TilesXY, + TilesXYBatch, + StreamKWithBatch, + StreamKNoBatch, + // TODO SplitK + CustomGridSize_Count, + }; + + std::string toString(CustomGridSize mode); + CustomGridSize fromStringCustomGridSize(std::string& str); + std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t); + std::istream& operator>>(std::istream& stream, CustomGridSize& t); + + struct CustomKernel + { + std::string name; + std::vector args; + dim3 macrotile; + dim3 threads; + vector3 grid; + }; + template struct DeviceUserArguments { @@ -152,12 +178,6 @@ namespace TensileLite size_t depthUorMT1; }; - struct CustomKernel - { - std::string name; - std::vector args; - }; - struct SizeMapping { size_t waveNum; @@ -376,6 +396,8 @@ namespace TensileLite size_t requiredSynchronizerSize(Problem const& problem, Hardware const& hardware) const; + void calculateTiles(dim3& tiles, + ContractionSolution::Problem const& problem) const; void calculateGrid(dim3& workGroupSize, dim3& numWorkGroups, ContractionSolution::Problem const& problem) const; diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index 903cf02c9c86..5a6d44775797 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -397,6 +397,20 @@ namespace TensileLite } }; + template + struct EnumTraits + { + using iot = IOTraits; + static void enumeration(IO& io, CustomGridSize& value) + { + for(int i = 0; i < static_cast(CustomGridSize::CustomGridSize_Count); i++) + { + auto const& info = static_cast(i); + iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); + } + } + }; + template struct EnumTraits { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp index b125a6c81436..7c7a55c19485 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Containers.hpp @@ -207,6 +207,12 @@ namespace TensileLite { }; + template + struct SequenceTraits, IO> + : public DefaultSequenceTraits, IO, false> + { + }; + template struct SequenceTraits>, IO> : public DefaultSequenceTraits>, IO, false> diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 4f92b6400c62..028babf55900 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -81,6 +81,9 @@ namespace TensileLite { iot::mapOptional(io, "name", s.name); iot::mapOptional(io, "args", s.args); + iot::mapOptional(io, "macrotile", s.macrotile); + iot::mapOptional(io, "threads", s.threads); + iot::mapOptional(io, "grid", s.grid); } const static bool flow = false; diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 5a7b9f47c54c..1aa12b34194d 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -182,6 +182,69 @@ namespace TensileLite return stream; } + std::string toString(CustomGridSize size) + { + switch(size) + { + case CustomGridSize::One: + return "One"; + case CustomGridSize::TilesX: + return "TilesX"; + case CustomGridSize::TilesY: + return "TilesY"; + case CustomGridSize::Batch: + return "Batch"; + case CustomGridSize::TilesXY: + return "TilesXY"; + case CustomGridSize::TilesXYBatch: + return "TilesXYBatch"; + case CustomGridSize::StreamKWithBatch: + return "StreamKWithBatch"; + case CustomGridSize::StreamKNoBatch: + return "StreamKNoBatch"; + case CustomGridSize::CustomGridSize_Count: + break; + } + + throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", static_cast(size))); + } + + CustomGridSize fromStringCustomGridSize(std::string& str) + { + if(str == toString(CustomGridSize::One)) + return CustomGridSize::One; + else if(str == toString(CustomGridSize::TilesX)) + return CustomGridSize::TilesX; + else if(str == toString(CustomGridSize::TilesY)) + return CustomGridSize::TilesY; + else if(str == toString(CustomGridSize::Batch)) + return CustomGridSize::Batch; + else if(str == toString(CustomGridSize::TilesXY)) + return CustomGridSize::TilesXY; + else if(str == toString(CustomGridSize::TilesXYBatch)) + return CustomGridSize::TilesXYBatch; + else if(str == toString(CustomGridSize::StreamKWithBatch)) + return CustomGridSize::StreamKWithBatch; + else if(str == toString(CustomGridSize::StreamKNoBatch)) + return CustomGridSize::StreamKNoBatch; + else + throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", str)); + return CustomGridSize::CustomGridSize_Count; + } + + std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t) + { + return stream << toString(t); + } + + std::istream& operator>>(std::istream& stream, CustomGridSize& t) + { + std::string strValue; + stream >> strValue; + t = fromStringCustomGridSize(strValue); + return stream; + } + enum class KERNELARGTYPE { NORMAL = 0, @@ -1480,6 +1543,39 @@ namespace TensileLite } } + void ContractionSolution::calculateTiles(dim3& tiles, + ContractionSolution::Problem const& problem) const + { + tiles.x = 1; + tiles.y = 1; + + for(size_t i = 0; i < problem.freeIndicesA().size(); i++) + { + tiles.x *= problem.freeSizeA(i); + } + for(size_t i = 0; i < problem.freeIndicesB().size(); i++) + { + tiles.y *= problem.freeSizeB(i); + } + + tiles.z = 1; + for(size_t i = 0; i < problem.batchIndices().size(); i++) + { + // if(sizeMapping.packBatchDims & 0x1) + // numWorkGroups.x *= problem.batchSize(i); + // if(sizeMapping.packBatchDims & 0x2) + // numWorkGroups.y *= problem.batchSize(i); + if(!sizeMapping.packBatchDims) + tiles.z *= problem.batchSize(i); + } + + if(problem.transposeC01()) + std::swap(tiles.x, tiles.y); + + tiles.x = CeilDivide(tiles.x, sizeMapping.customKernel.macrotile.x); + tiles.y = CeilDivide(tiles.y, sizeMapping.customKernel.macrotile.y); + } + void ContractionSolution::calculateGrid(dim3& workGroupSize, dim3& numWorkGroups, ContractionSolution::Problem const& problem) const @@ -1531,10 +1627,74 @@ namespace TensileLite rv.args.reserve(1024, 128); rv.kernelName = kernelName; - calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); - // rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); - // rv.numWorkGroups.y = 1; - // rv.numWorkGroups.z = 1; + AMDGPU const* pAMDGPU = dynamic_cast(&hardware); + assert(pAMDGPU); + + int wavefrontSize = pAMDGPU->wavefrontSize; + // rv.workGroupSize.x = sizeMapping.customKernel.waves.x * wavefrontSize; + // rv.workGroupSize.y = sizeMapping.customKernel.waves.y * wavefrontSize; + // rv.workGroupSize.z = sizeMapping.customKernel.waves.z * wavefrontSize; + rv.workGroupSize.x = sizeMapping.customKernel.threads.x; + rv.workGroupSize.y = sizeMapping.customKernel.threads.y; + rv.workGroupSize.z = sizeMapping.customKernel.threads.z; + + if(T_Debug) + { + std::cout << "Wavefront size: " << wavefrontSize << std::endl; + std::cout << "Threads: " << sizeMapping.customKernel.threads.x << ", " << sizeMapping.customKernel.threads.y << ", " << sizeMapping.customKernel.threads.z << std::endl; + std::cout << "Work group size: " << rv.workGroupSize.x << ", " << rv.workGroupSize.y << ", " << rv.workGroupSize.z << std::endl; + std::cout << "Macrotile: " << sizeMapping.customKernel.macrotile.x << ", " << sizeMapping.customKernel.macrotile.y << ", " << sizeMapping.customKernel.macrotile.z << std::endl; + } + + dim3 tiles; + calculateTiles(tiles, problem); + + if(T_Debug) + { + std::cout << "Tiles: " << tiles.x << ", " << tiles.y << ", " << tiles.z << std::endl; + } + + auto assignGridSize = [tiles](size_t& dim, CustomGridSize size) { + switch(size) + { + case CustomGridSize::One: + dim = 1; + break; + case CustomGridSize::TilesX: + dim = tiles.x; + break; + case CustomGridSize::TilesY: + dim = tiles.y; + break; + case CustomGridSize::Batch: + dim = tiles.z; + break; + case CustomGridSize::TilesXY: + dim = tiles.x * tiles.y; + break; + case CustomGridSize::TilesXYBatch: + dim = tiles.x * tiles.y * tiles.z; + break; + // case CustomGridSize::StreamKWithBatch: + // dim = TODO + // break; + // case CustomGridSize::StreamKNoBatch: + // dim = TODO + // break; + default: + throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", static_cast(size))); + break; + } + }; + + assignGridSize(rv.numWorkGroups.x, sizeMapping.customKernel.grid.x); + assignGridSize(rv.numWorkGroups.y, sizeMapping.customKernel.grid.y); + assignGridSize(rv.numWorkGroups.z, sizeMapping.customKernel.grid.z); + + if(T_Debug) + { + std::cout << "Num work groups: " << rv.numWorkGroups.x << ", " << rv.numWorkGroups.y << ", " << rv.numWorkGroups.z << std::endl; + } rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; From 8175333a047aa4d1c00572d443df053dc13ee047 Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Mon, 9 Mar 2026 16:48:00 -0400 Subject: [PATCH 15/58] Init CustomKernel to fix some build errors --- .../tensilelite/Tensile/Common/GlobalParameters.py | 2 +- projects/hipblaslt/tensilelite/Tensile/Contractions.py | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py index 6228ffb3ce47..e193750f65ae 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py @@ -425,7 +425,7 @@ {"NonTemporalMetadata": [0]}, {"NonTemporal": [-1]}, {"PreloadKernArgs": [True]}, - {"CustomKernel": [{"name": "", "args": []}]}, + {"CustomKernel": [{"name": "", "args": [], "macrotile": [0,0,0], "threads": [0,0,0], "grid": [0,0,0]}]}, {"NoReject": [False]}, {"StoreRemapVectorWidth": [0]}, {"SourceSwap": [False]}, diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index 7ebf083851d0..70957d98cb3d 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -589,6 +589,11 @@ def FromOriginalState(cls, d): return cls(name=d['name'], args=d['args'], macrotile=d['macrotile'], threads=d['threads'], grid=d['grid']) def __init__(self, **kwargs): + self.name = "" + self.args = [] + self.macrotile = [0,0,0] + self.threads = [0,0,0] + self.grid = [0,0,0] for (key, value) in list(kwargs.items()): setattr(self, key, value) @@ -684,7 +689,7 @@ def convertSFCWGMListToHex(value): if 'CustomKernel' in d: customKernel = CustomKernel.FromOriginalState(d['CustomKernel']) else: - customKernel = CustomKernel(name="", args=[]) + customKernel = CustomKernel(name="", args=[], macrotile=[0,0,0], threads=[0,0,0], grid=[0,0,0]) return cls(waveNum = d['NumThreads'] // d['WavefrontSize'], workGroup = d['WorkGroup'], From 2c6d801e8885b799fd90abc120bb114fe66f7dec Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Tue, 10 Mar 2026 12:14:24 -0700 Subject: [PATCH 16/58] [hipblaslt] Demo calling AITER bf16 kernel (#5267) Tensile log: https://gist.github.com/jinchen62/e800f160eab87ba3458ee41f15b43da0 --- .../_ZN5aiter24bf16gemm_bf16_tn_256x256E.s | 2571 +++++++++++++++++ .../Tests/custom/custom_aiter_bf16.yaml | 175 ++ .../include/Tensile/ContractionSolution.hpp | 10 +- .../tensilelite/src/ContractionSolution.cpp | 52 + 4 files changed, 2806 insertions(+), 2 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s new file mode 100644 index 000000000000..6d7d1ef5ec2b --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s @@ -0,0 +1,2571 @@ +// Auto-generated from bf16gemm_bf16_tn_256x256.co +// This file can be reassembled with: +// clang -x assembler -target amdgcn-amd-amdhsa -mcpu=gfx950 -c file.s -o file.o +// ld.lld -shared -o file.co file.o + +// Note: Target is specified via -mcpu= command line flag + +.set .amdgcn.next_free_vgpr, 0 +.set .amdgcn.next_free_sgpr, 0 + +// ===== Kernel Code ===== +.text +.globl _ZN5aiter24bf16gemm_bf16_tn_256x256E +.p2align 8 +.type _ZN5aiter24bf16gemm_bf16_tn_256x256E,@function + +_ZN5aiter24bf16gemm_bf16_tn_256x256E: + + s_mov_b32 s46, s2 + s_mov_b32 s47, s3 + s_mov_b32 s51, s4 + s_and_b32 s1, s1, 0xffff + s_load_dwordx2 s[4:5], s[0:1], 0x0 + s_load_dwordx2 s[8:9], s[0:1], 0x10 + s_load_dwordx2 s[12:13], s[0:1], 0x20 + s_load_dwordx2 s[16:17], s[0:1], 0x30 + s_load_dword s38, s[0:1], 0x40 + s_load_dword s39, s[0:1], 0x50 + s_load_dword s40, s[0:1], 0x80 + s_load_dword s41, s[0:1], 0xa0 + s_load_dword s42, s[0:1], 0xc0 + s_load_dword s43, s[0:1], 0xe0 + s_load_dword s44, s[0:1], 0xf0 + s_load_dword s45, s[0:1], 0x100 + s_load_dword s58, s[0:1], 0x110 + s_load_dword s59, s[0:1], 0x120 + v_lshrrev_b32_e32 v1, 10, v0 + v_lshrrev_b32_e32 v2, 10, v1 + v_and_b32_e32 v2, 0x3ff, v2 + v_and_b32_e32 v1, 0x3ff, v1 + v_and_b32_e32 v0, 0x3ff, v0 + v_lshrrev_b32_e32 v3, 6, v0 + v_and_b32_e32 v0, 63, v0 + v_readfirstlane_b32 s48, v3 + s_waitcnt lgkmcnt(0) + s_add_u32 s51, s44, 0xff + s_lshr_b32 s51, s51, 8 + s_mul_i32 s54, s51, s47 + s_add_i32 s54, s54, s46 + s_lshr_b32 s55, s51, 5 + s_lshl_b32 s55, s55, 5 + s_sub_i32 s56, s51, s55 + s_add_u32 s53, s43, 0xff + s_lshr_b32 s53, s53, 8 + s_mul_i32 s57, s55, s53 + s_cmp_lt_i32 s54, s57 + s_cbranch_scc0 label_0060 + s_lshr_b32 s51, s54, 5 + v_cvt_f32_u32_e32 v4, s53 + s_sub_i32 s52, 0, s53 + v_rcp_iflag_f32_e32 v4, v4 + s_nop 0 + v_mul_f32_e32 v4, 0x4f7ffffe, v4 + v_cvt_u32_f32_e32 v4, v4 + v_mul_lo_u32 v5, s52, v4 + v_mul_hi_u32 v5, v4, v5 + v_add_u32_e32 v4, v4, v5 + v_mul_hi_u32 v4, s51, v4 + v_mul_lo_u32 v5, v4, s53 + v_sub_u32_e32 v7, s51, v5 + v_add_u32_e32 v6, 1, v4 + v_cmp_le_u32_e32 vcc, s53, v7 + v_subrev_u32_e32 v5, s53, v7 + s_nop 0 + v_cndmask_b32_e32 v4, v4, v6, vcc + v_cndmask_b32_e32 v7, v7, v5, vcc + v_add_u32_e32 v5, 1, v4 + v_cmp_le_u32_e32 vcc, s53, v7 + s_nop 1 + v_cndmask_b32_e32 v7, v4, v5, vcc + s_nop 3 + v_readfirstlane_b32 s52, v7 + s_nop 3 + s_mul_i32 s47, s53, s52 + s_sub_i32 s47, s51, s47 + s_and_b32 s51, s54, 31 + s_lshl_b32 s46, s52, 5 + s_add_i32 s46, s46, s51 + s_branch label_0082 + +label_0060: + s_sub_i32 s51, s54, s57 + v_cvt_f32_u32_e32 v4, s56 + s_sub_i32 s47, 0, s56 + v_rcp_iflag_f32_e32 v4, v4 + s_nop 0 + v_mul_f32_e32 v4, 0x4f7ffffe, v4 + v_cvt_u32_f32_e32 v4, v4 + v_mul_lo_u32 v5, s47, v4 + v_mul_hi_u32 v5, v4, v5 + v_add_u32_e32 v4, v4, v5 + v_mul_hi_u32 v4, s51, v4 + v_mul_lo_u32 v5, v4, s56 + v_sub_u32_e32 v7, s51, v5 + v_add_u32_e32 v6, 1, v4 + v_cmp_le_u32_e32 vcc, s56, v7 + v_subrev_u32_e32 v5, s56, v7 + s_nop 0 + v_cndmask_b32_e32 v4, v4, v6, vcc + v_cndmask_b32_e32 v7, v7, v5, vcc + v_add_u32_e32 v5, 1, v4 + v_cmp_le_u32_e32 vcc, s56, v7 + s_nop 1 + v_cndmask_b32_e32 v7, v4, v5, vcc + s_nop 3 + v_readfirstlane_b32 s47, v7 + s_nop 3 + s_mul_i32 s52, s56, s47 + s_sub_i32 s46, s51, s52 + s_add_i32 s46, s55, s46 + +label_0082: + s_mov_b32 s6, -16 + s_mov_b32 s10, -16 + s_mov_b32 s18, -16 + s_mov_b32 s14, -16 + s_mov_b32 s7, 0x20000 + s_mov_b32 s11, 0x20000 + s_mov_b32 s19, 0x20000 + s_mov_b32 s15, 0x20000 + s_and_b32 s5, s5, 0xffff + s_and_b32 s9, s9, 0xffff + s_and_b32 s17, s17, 0xffff + s_and_b32 s13, s13, 0xffff + s_or_b32 s5, s5, 0x40000 + s_or_b32 s9, s9, 0x40000 + s_or_b32 s17, s17, 0x40000 + s_or_b32 s13, s13, 0x40000 + s_mul_i32 s51, s41, s43 + s_mov_b32 s14, s51 + s_mul_i32 s51, s42, s44 + s_mov_b32 s18, s51 + v_lshrrev_b32_e32 v4, 3, v0 + v_lshrrev_b32_e32 v5, 2, v4 + v_lshlrev_b32_e32 v5, 4, v5 + v_and_b32_e32 v4, 3, v4 + v_lshrrev_b32_e32 v6, 1, v4 + v_lshlrev_b32_e32 v6, 2, v6 + v_add_u32_e32 v5, v5, v6 + v_and_b32_e32 v4, 1, v4 + v_add_u32_e32 v5, v5, v4 + v_mul_lo_u32 v200, s41, v5 + v_mul_lo_u32 v210, s42, v5 + v_and_b32_e32 v4, 7, v0 + v_lshlrev_b32_e32 v4, 4, v4 + v_add_u32_e32 v200, v200, v4 + v_add_u32_e32 v210, v210, v4 + s_lshr_b32 s51, s48, 1 + s_mul_i32 s51, s51, 8 + s_and_b32 s52, s48, 1 + s_mul_i32 s52, s52, 2 + s_add_u32 s51, s51, s52 + s_mul_i32 s52, s47, 0x100 + s_add_u32 s52, s51, s52 + s_mul_i32 s52, s41, s52 + v_add_u32_e32 v200, s52, v200 + s_mul_i32 s52, s46, 0x100 + s_add_u32 s52, s51, s52 + s_mul_i32 s52, s42, s52 + v_add_u32_e32 v210, s52, v210 + s_mul_i32 s51, s41, 32 + v_add_u32_e32 v201, s51, v200 + v_add_u32_e32 v202, s51, v201 + v_add_u32_e32 v203, s51, v202 + v_add_u32_e32 v204, s51, v203 + v_add_u32_e32 v205, s51, v204 + v_add_u32_e32 v206, s51, v205 + v_add_u32_e32 v207, s51, v206 + s_mul_i32 s51, s42, 32 + v_add_u32_e32 v211, s51, v210 + v_add_u32_e32 v212, s51, v211 + v_add_u32_e32 v213, s51, v212 + v_add_u32_e32 v214, s51, v213 + v_add_u32_e32 v215, s51, v214 + v_add_u32_e32 v216, s51, v215 + v_add_u32_e32 v217, s51, v216 + s_mul_i32 s60, 0x420, s48 + s_add_u32 s60, 0, s60 + s_add_u32 s61, 0x10800, s60 + v_and_b32_e32 v4, 15, v0 + v_lshrrev_b32_e32 v5, 3, v4 + v_mul_i32_i24_e32 v5, 2, v5 + v_and_b32_e32 v4, 3, v0 + v_lshrrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, v5, v6 + v_mul_i32_i24_e32 v208, 0x420, v4 + v_mul_i32_i24_e32 v218, 0x420, v4 + v_and_b32_e32 v4, 7, v0 + v_lshrrev_b32_e32 v5, 2, v4 + v_mul_i32_i24_e32 v5, 0x100, v5 + v_add_u32_e32 v208, v5, v208 + v_add_u32_e32 v218, v5, v218 + v_and_b32_e32 v4, 1, v0 + v_mul_i32_i24_e32 v6, 0x80, v4 + v_add_u32_e32 v208, v6, v208 + v_add_u32_e32 v218, v6, v218 + v_lshrrev_b32_e32 v4, 4, v0 + v_mul_i32_i24_e32 v4, 16, v4 + v_add_u32_e32 v208, v4, v208 + v_add_u32_e32 v218, v4, v218 + s_mov_b32 s51, 0 + v_add_u32_e64 v208, v208, s51 + s_mov_b32 s51, 0x10800 + v_add_u32_e64 v218, v218, s51 + s_mul_i32 s51, 0x2100, s48 + v_add_u32_e64 v218, v218, s51 + v_add_u32_e32 v209, 0x8400, v208 + v_add_u32_e32 v219, 0x8400, v218 + s_mov_b32 s62, 0x80 + s_mov_b32 s63, 0x80 + s_add_u32 m0, 0, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + s_add_u32 m0, 0x1080, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + s_add_u32 m0, 0x2100, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + s_add_u32 m0, 0x3180, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_add_u32 m0, 0x4200, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + s_add_u32 m0, 0x5280, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + s_add_u32 m0, 0x6300, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + s_add_u32 m0, 0x7380, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + s_add_u32 m0, 0, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + s_add_u32 m0, 0x1080, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + s_add_u32 m0, 0x2100, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + s_add_u32 m0, 0x3180, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + s_add_u32 m0, 0x4200, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + s_add_u32 m0, 0x5280, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + s_add_u32 m0, 0x6300, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + s_add_u32 m0, 0x7380, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + s_add_u32 m0, 0x8400, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + s_add_u32 m0, 0x9480, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + s_add_u32 m0, 0xa500, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + s_add_u32 m0, 0xb580, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + s_add_u32 m0, 0xc600, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + s_add_u32 m0, 0xd680, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + s_add_u32 m0, 0xe700, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + s_add_u32 m0, 0xf780, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + s_add_u32 m0, 0x8400, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + s_add_u32 m0, 0x9480, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + s_add_u32 m0, 0xa500, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + s_add_u32 m0, 0xb580, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + s_add_u32 m0, 0xc600, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + s_add_u32 m0, 0xd680, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + s_add_u32 m0, 0xe700, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + s_add_u32 m0, 0xf780, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + s_waitcnt vmcnt(20) + s_barrier + ds_read_b128 v[136:139], v218 + ds_read_b128 v[152:155], v218 offset:64 + ds_read_b128 v[140:143], v218 offset:512 + ds_read_b128 v[156:159], v218 offset:576 + ds_read_b128 v[144:147], v218 offset:4224 + ds_read_b128 v[160:163], v218 offset:4288 + ds_read_b128 v[148:151], v218 offset:4736 + ds_read_b128 v[164:167], v218 offset:4800 + ds_read_b128 v[8:11], v208 + ds_read_b128 v[40:43], v208 offset:64 + ds_read_b128 v[12:15], v208 offset:512 + ds_read_b128 v[44:47], v208 offset:576 + ds_read_b128 v[16:19], v208 offset:4224 + ds_read_b128 v[48:51], v208 offset:4288 + ds_read_b128 v[20:23], v208 offset:4736 + ds_read_b128 v[52:55], v208 offset:4800 + ds_read_b128 v[24:27], v208 offset:8448 + ds_read_b128 v[56:59], v208 offset:8512 + ds_read_b128 v[28:31], v208 offset:8960 + ds_read_b128 v[60:63], v208 offset:9024 + ds_read_b128 v[32:35], v208 offset:12672 + ds_read_b128 v[64:67], v208 offset:12736 + ds_read_b128 v[36:39], v208 offset:13184 + ds_read_b128 v[68:71], v208 offset:13248 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_nop 0 + s_mul_i32 s51, s47, 0x100 + s_mul_hi_u32 s52, s51, s40 + s_add_u32 s5, s5, s52 + s_mul_i32 s52, s51, s40 + s_add_u32 s4, s4, s52 + s_addc_u32 s5, 0, s5 + s_sub_i32 s51, s43, s51 + s_mul_i32 s51, s51, s40 + s_mov_b32 s6, s51 + v_and_b32_e64 v220, v0, 15 + v_mul_lo_u32 v220, v220, s40 + v_lshrrev_b32_e32 v4, 5, v0 + v_mul_i32_i24_e32 v4, 16, v4 + v_add_u32_e32 v220, v4, v220 + v_lshrrev_b32_e32 v4, 4, v0 + v_and_b32_e32 v4, 1, v4 + v_mul_i32_i24_e32 v4, 32, v4 + v_add_u32_e32 v220, v4, v220 + s_mul_i32 s51, s46, 0x100 + s_mul_i32 s52, s48, 64 + s_add_i32 s51, s51, s52 + s_lshl_b32 s51, s51, 1 + v_add_u32_e32 v220, s51, v220 + s_mul_i32 s52, s40, 16 + v_add_u32_e64 v221, v220, s52 + v_add_u32_e64 v222, v221, s52 + v_add_u32_e64 v223, v222, s52 + v_add_u32_e64 v224, v223, s52 + v_add_u32_e64 v225, v224, s52 + v_add_u32_e64 v226, v225, s52 + v_add_u32_e64 v227, v226, s52 + v_add_u32_e64 v228, v227, s52 + v_add_u32_e64 v229, v228, s52 + v_add_u32_e64 v230, v229, s52 + v_add_u32_e64 v231, v230, s52 + v_add_u32_e64 v232, v231, s52 + v_add_u32_e64 v233, v232, s52 + v_add_u32_e64 v234, v233, s52 + v_add_u32_e64 v235, v234, s52 + s_mov_b32 s49, 0 + s_mov_b32 s50, s45 + s_cmp_lt_u32 0x80, s50 + s_cselect_b32 s62, s62, 0 + s_cmp_lt_u32 64, s50 + s_cselect_b32 s63, s63, 0 + s_cmp_lt_i32 s48, 2 + s_cbranch_scc0 label_075D + +label_040D: + s_waitcnt vmcnt(8) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[0:3], v[136:139], v[8:11], a[0:3] + s_add_u32 m0, 0, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[4:7], v[136:139], v[12:15], a[4:7] + ds_read_b128 v[72:75], v208 offset:16896 + v_mfma_f32_16x16x32_bf16 a[8:11], v[136:139], v[16:19], a[8:11] + v_mfma_f32_16x16x32_bf16 a[12:15], v[136:139], v[20:23], a[12:15] + ds_read_b128 v[104:107], v208 offset:16960 + v_mfma_f32_16x16x32_bf16 a[16:19], v[136:139], v[24:27], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[136:139], v[28:31], a[20:23] + ds_read_b128 v[76:79], v208 offset:17408 + v_mfma_f32_16x16x32_bf16 a[24:27], v[136:139], v[32:35], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[136:139], v[36:39], a[28:31] + ds_read_b128 v[108:111], v208 offset:17472 + v_mfma_f32_16x16x32_bf16 a[32:35], v[140:143], v[8:11], a[32:35] + s_add_u32 m0, 0x1080, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[36:39], v[140:143], v[12:15], a[36:39] + ds_read_b128 v[80:83], v208 offset:21120 + v_mfma_f32_16x16x32_bf16 a[40:43], v[140:143], v[16:19], a[40:43] + v_mfma_f32_16x16x32_bf16 a[44:47], v[140:143], v[20:23], a[44:47] + ds_read_b128 v[112:115], v208 offset:21184 + v_mfma_f32_16x16x32_bf16 a[48:51], v[140:143], v[24:27], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[140:143], v[28:31], a[52:55] + ds_read_b128 v[84:87], v208 offset:21632 + v_mfma_f32_16x16x32_bf16 a[56:59], v[140:143], v[32:35], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[140:143], v[36:39], a[60:63] + ds_read_b128 v[116:119], v208 offset:21696 + v_mfma_f32_16x16x32_bf16 a[64:67], v[144:147], v[8:11], a[64:67] + s_add_u32 m0, 0x2100, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[68:71], v[144:147], v[12:15], a[68:71] + ds_read_b128 v[88:91], v208 offset:25344 + v_mfma_f32_16x16x32_bf16 a[72:75], v[144:147], v[16:19], a[72:75] + v_mfma_f32_16x16x32_bf16 a[76:79], v[144:147], v[20:23], a[76:79] + ds_read_b128 v[120:123], v208 offset:25408 + v_mfma_f32_16x16x32_bf16 a[80:83], v[144:147], v[24:27], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[144:147], v[28:31], a[84:87] + ds_read_b128 v[92:95], v208 offset:25856 + v_mfma_f32_16x16x32_bf16 a[88:91], v[144:147], v[32:35], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[144:147], v[36:39], a[92:95] + ds_read_b128 v[124:127], v208 offset:25920 + v_mfma_f32_16x16x32_bf16 a[96:99], v[148:151], v[8:11], a[96:99] + s_add_u32 m0, 0x3180, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[100:103], v[148:151], v[12:15], a[100:103] + ds_read_b128 v[96:99], v208 offset:29568 + v_mfma_f32_16x16x32_bf16 a[104:107], v[148:151], v[16:19], a[104:107] + v_mfma_f32_16x16x32_bf16 a[108:111], v[148:151], v[20:23], a[108:111] + ds_read_b128 v[128:131], v208 offset:29632 + v_mfma_f32_16x16x32_bf16 a[112:115], v[148:151], v[24:27], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[148:151], v[28:31], a[116:119] + ds_read_b128 v[100:103], v208 offset:30080 + v_mfma_f32_16x16x32_bf16 a[120:123], v[148:151], v[32:35], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[148:151], v[36:39], a[124:127] + ds_read_b128 v[132:135], v208 offset:30144 + v_mfma_f32_16x16x32_bf16 a[0:3], v[152:155], v[40:43], a[0:3] + s_add_u32 m0, 0x4200, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[4:7], v[152:155], v[44:47], a[4:7] + ds_read_b128 v[168:171], v219 + v_mfma_f32_16x16x32_bf16 a[8:11], v[152:155], v[48:51], a[8:11] + v_mfma_f32_16x16x32_bf16 a[12:15], v[152:155], v[52:55], a[12:15] + ds_read_b128 v[184:187], v219 offset:64 + v_mfma_f32_16x16x32_bf16 a[16:19], v[152:155], v[56:59], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[152:155], v[60:63], a[20:23] + ds_read_b128 v[172:175], v219 offset:512 + v_mfma_f32_16x16x32_bf16 a[24:27], v[152:155], v[64:67], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[152:155], v[68:71], a[28:31] + ds_read_b128 v[188:191], v219 offset:576 + v_mfma_f32_16x16x32_bf16 a[32:35], v[156:159], v[40:43], a[32:35] + s_add_u32 m0, 0x5280, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[36:39], v[156:159], v[44:47], a[36:39] + ds_read_b128 v[176:179], v219 offset:4224 + v_mfma_f32_16x16x32_bf16 a[40:43], v[156:159], v[48:51], a[40:43] + v_mfma_f32_16x16x32_bf16 a[44:47], v[156:159], v[52:55], a[44:47] + ds_read_b128 v[192:195], v219 offset:4288 + v_mfma_f32_16x16x32_bf16 a[48:51], v[156:159], v[56:59], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[156:159], v[60:63], a[52:55] + ds_read_b128 v[180:183], v219 offset:4736 + v_mfma_f32_16x16x32_bf16 a[56:59], v[156:159], v[64:67], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[156:159], v[68:71], a[60:63] + ds_read_b128 v[196:199], v219 offset:4800 + v_mfma_f32_16x16x32_bf16 a[64:67], v[160:163], v[40:43], a[64:67] + s_add_u32 m0, 0x6300, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[68:71], v[160:163], v[44:47], a[68:71] + v_mfma_f32_16x16x32_bf16 a[72:75], v[160:163], v[48:51], a[72:75] + v_mfma_f32_16x16x32_bf16 a[76:79], v[160:163], v[52:55], a[76:79] + v_mfma_f32_16x16x32_bf16 a[80:83], v[160:163], v[56:59], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[160:163], v[60:63], a[84:87] + v_mfma_f32_16x16x32_bf16 a[88:91], v[160:163], v[64:67], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[160:163], v[68:71], a[92:95] + v_mfma_f32_16x16x32_bf16 a[96:99], v[164:167], v[40:43], a[96:99] + s_add_u32 m0, 0x7380, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[100:103], v[164:167], v[44:47], a[100:103] + v_mfma_f32_16x16x32_bf16 a[104:107], v[164:167], v[48:51], a[104:107] + s_add_u32 s52, 0x80, s49 + s_cmp_lt_u32 s52, s50 + s_cselect_b32 s63, s63, 0 + v_mfma_f32_16x16x32_bf16 a[108:111], v[164:167], v[52:55], a[108:111] + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_mfma_f32_16x16x32_bf16 a[112:115], v[164:167], v[56:59], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[164:167], v[60:63], a[116:119] + v_mfma_f32_16x16x32_bf16 a[120:123], v[164:167], v[64:67], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[164:167], v[68:71], a[124:127] + s_waitcnt vmcnt(12) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[128:131], v[136:139], v[72:75], a[128:131] + s_add_u32 m0, 0, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[132:135], v[136:139], v[76:79], a[132:135] + ds_read_b128 v[8:11], v209 + v_mfma_f32_16x16x32_bf16 a[136:139], v[136:139], v[80:83], a[136:139] + v_mfma_f32_16x16x32_bf16 a[140:143], v[136:139], v[84:87], a[140:143] + ds_read_b128 v[40:43], v209 offset:64 + v_mfma_f32_16x16x32_bf16 a[144:147], v[136:139], v[88:91], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[136:139], v[92:95], a[148:151] + ds_read_b128 v[12:15], v209 offset:512 + v_mfma_f32_16x16x32_bf16 a[152:155], v[136:139], v[96:99], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[136:139], v[100:103], a[156:159] + ds_read_b128 v[44:47], v209 offset:576 + v_mfma_f32_16x16x32_bf16 a[160:163], v[140:143], v[72:75], a[160:163] + s_add_u32 m0, 0x1080, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[164:167], v[140:143], v[76:79], a[164:167] + ds_read_b128 v[16:19], v209 offset:4224 + v_mfma_f32_16x16x32_bf16 a[168:171], v[140:143], v[80:83], a[168:171] + v_mfma_f32_16x16x32_bf16 a[172:175], v[140:143], v[84:87], a[172:175] + ds_read_b128 v[48:51], v209 offset:4288 + v_mfma_f32_16x16x32_bf16 a[176:179], v[140:143], v[88:91], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[140:143], v[92:95], a[180:183] + ds_read_b128 v[20:23], v209 offset:4736 + v_mfma_f32_16x16x32_bf16 a[184:187], v[140:143], v[96:99], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[140:143], v[100:103], a[188:191] + ds_read_b128 v[52:55], v209 offset:4800 + v_mfma_f32_16x16x32_bf16 a[192:195], v[144:147], v[72:75], a[192:195] + s_add_u32 m0, 0x2100, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[196:199], v[144:147], v[76:79], a[196:199] + ds_read_b128 v[24:27], v209 offset:8448 + v_mfma_f32_16x16x32_bf16 a[200:203], v[144:147], v[80:83], a[200:203] + v_mfma_f32_16x16x32_bf16 a[204:207], v[144:147], v[84:87], a[204:207] + ds_read_b128 v[56:59], v209 offset:8512 + v_mfma_f32_16x16x32_bf16 a[208:211], v[144:147], v[88:91], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[144:147], v[92:95], a[212:215] + ds_read_b128 v[28:31], v209 offset:8960 + v_mfma_f32_16x16x32_bf16 a[216:219], v[144:147], v[96:99], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[144:147], v[100:103], a[220:223] + ds_read_b128 v[60:63], v209 offset:9024 + v_mfma_f32_16x16x32_bf16 a[224:227], v[148:151], v[72:75], a[224:227] + s_add_u32 m0, 0x3180, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[228:231], v[148:151], v[76:79], a[228:231] + ds_read_b128 v[32:35], v209 offset:12672 + v_mfma_f32_16x16x32_bf16 a[232:235], v[148:151], v[80:83], a[232:235] + v_mfma_f32_16x16x32_bf16 a[236:239], v[148:151], v[84:87], a[236:239] + ds_read_b128 v[64:67], v209 offset:12736 + v_mfma_f32_16x16x32_bf16 a[240:243], v[148:151], v[88:91], a[240:243] + v_mfma_f32_16x16x32_bf16 a[244:247], v[148:151], v[92:95], a[244:247] + ds_read_b128 v[36:39], v209 offset:13184 + v_mfma_f32_16x16x32_bf16 a[248:251], v[148:151], v[96:99], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[148:151], v[100:103], a[252:255] + ds_read_b128 v[68:71], v209 offset:13248 + v_mfma_f32_16x16x32_bf16 a[128:131], v[152:155], v[104:107], a[128:131] + s_add_u32 m0, 0x4200, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[132:135], v[152:155], v[108:111], a[132:135] + v_mfma_f32_16x16x32_bf16 a[136:139], v[152:155], v[112:115], a[136:139] + v_mfma_f32_16x16x32_bf16 a[140:143], v[152:155], v[116:119], a[140:143] + v_mfma_f32_16x16x32_bf16 a[144:147], v[152:155], v[120:123], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[152:155], v[124:127], a[148:151] + v_mfma_f32_16x16x32_bf16 a[152:155], v[152:155], v[128:131], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[152:155], v[132:135], a[156:159] + v_mfma_f32_16x16x32_bf16 a[160:163], v[156:159], v[104:107], a[160:163] + s_add_u32 m0, 0x5280, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[164:167], v[156:159], v[108:111], a[164:167] + v_mfma_f32_16x16x32_bf16 a[168:171], v[156:159], v[112:115], a[168:171] + v_mfma_f32_16x16x32_bf16 a[172:175], v[156:159], v[116:119], a[172:175] + v_mfma_f32_16x16x32_bf16 a[176:179], v[156:159], v[120:123], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[156:159], v[124:127], a[180:183] + v_mfma_f32_16x16x32_bf16 a[184:187], v[156:159], v[128:131], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[156:159], v[132:135], a[188:191] + v_mfma_f32_16x16x32_bf16 a[192:195], v[160:163], v[104:107], a[192:195] + s_add_u32 m0, 0x6300, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[196:199], v[160:163], v[108:111], a[196:199] + v_mfma_f32_16x16x32_bf16 a[200:203], v[160:163], v[112:115], a[200:203] + v_mfma_f32_16x16x32_bf16 a[204:207], v[160:163], v[116:119], a[204:207] + v_mfma_f32_16x16x32_bf16 a[208:211], v[160:163], v[120:123], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[160:163], v[124:127], a[212:215] + v_mfma_f32_16x16x32_bf16 a[216:219], v[160:163], v[128:131], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[160:163], v[132:135], a[220:223] + v_mfma_f32_16x16x32_bf16 a[224:227], v[164:167], v[104:107], a[224:227] + s_add_u32 m0, 0x7380, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[228:231], v[164:167], v[108:111], a[228:231] + s_add_u32 s51, 0xc0, s49 + s_cmp_lt_u32 s51, s50 + s_cselect_b32 s62, s62, 0 + v_mfma_f32_16x16x32_bf16 a[232:235], v[164:167], v[112:115], a[232:235] + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + v_mfma_f32_16x16x32_bf16 a[236:239], v[164:167], v[116:119], a[236:239] + v_mfma_f32_16x16x32_bf16 a[240:243], v[164:167], v[120:123], a[240:243] + s_addk_i32 s49, 0x40 + s_cmp_lt_i32 s49, s50 + v_mfma_f32_16x16x32_bf16 a[244:247], v[164:167], v[124:127], a[244:247] + v_mfma_f32_16x16x32_bf16 a[248:251], v[164:167], v[128:131], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[164:167], v[132:135], a[252:255] + s_cbranch_scc0 label_0AA6 + s_waitcnt vmcnt(8) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[0:3], v[168:171], v[8:11], a[0:3] + s_add_u32 m0, 0x8400, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[4:7], v[168:171], v[12:15], a[4:7] + ds_read_b128 v[72:75], v209 offset:16896 + v_mfma_f32_16x16x32_bf16 a[8:11], v[168:171], v[16:19], a[8:11] + v_mfma_f32_16x16x32_bf16 a[12:15], v[168:171], v[20:23], a[12:15] + ds_read_b128 v[104:107], v209 offset:16960 + v_mfma_f32_16x16x32_bf16 a[16:19], v[168:171], v[24:27], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[168:171], v[28:31], a[20:23] + ds_read_b128 v[76:79], v209 offset:17408 + v_mfma_f32_16x16x32_bf16 a[24:27], v[168:171], v[32:35], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[168:171], v[36:39], a[28:31] + ds_read_b128 v[108:111], v209 offset:17472 + v_mfma_f32_16x16x32_bf16 a[32:35], v[172:175], v[8:11], a[32:35] + s_add_u32 m0, 0x9480, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[36:39], v[172:175], v[12:15], a[36:39] + ds_read_b128 v[80:83], v209 offset:21120 + v_mfma_f32_16x16x32_bf16 a[40:43], v[172:175], v[16:19], a[40:43] + v_mfma_f32_16x16x32_bf16 a[44:47], v[172:175], v[20:23], a[44:47] + ds_read_b128 v[112:115], v209 offset:21184 + v_mfma_f32_16x16x32_bf16 a[48:51], v[172:175], v[24:27], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[172:175], v[28:31], a[52:55] + ds_read_b128 v[84:87], v209 offset:21632 + v_mfma_f32_16x16x32_bf16 a[56:59], v[172:175], v[32:35], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[172:175], v[36:39], a[60:63] + ds_read_b128 v[116:119], v209 offset:21696 + v_mfma_f32_16x16x32_bf16 a[64:67], v[176:179], v[8:11], a[64:67] + s_add_u32 m0, 0xa500, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[68:71], v[176:179], v[12:15], a[68:71] + ds_read_b128 v[88:91], v209 offset:25344 + v_mfma_f32_16x16x32_bf16 a[72:75], v[176:179], v[16:19], a[72:75] + v_mfma_f32_16x16x32_bf16 a[76:79], v[176:179], v[20:23], a[76:79] + ds_read_b128 v[120:123], v209 offset:25408 + v_mfma_f32_16x16x32_bf16 a[80:83], v[176:179], v[24:27], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[176:179], v[28:31], a[84:87] + ds_read_b128 v[92:95], v209 offset:25856 + v_mfma_f32_16x16x32_bf16 a[88:91], v[176:179], v[32:35], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[176:179], v[36:39], a[92:95] + ds_read_b128 v[124:127], v209 offset:25920 + v_mfma_f32_16x16x32_bf16 a[96:99], v[180:183], v[8:11], a[96:99] + s_add_u32 m0, 0xb580, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[100:103], v[180:183], v[12:15], a[100:103] + ds_read_b128 v[96:99], v209 offset:29568 + v_mfma_f32_16x16x32_bf16 a[104:107], v[180:183], v[16:19], a[104:107] + v_mfma_f32_16x16x32_bf16 a[108:111], v[180:183], v[20:23], a[108:111] + ds_read_b128 v[128:131], v209 offset:29632 + v_mfma_f32_16x16x32_bf16 a[112:115], v[180:183], v[24:27], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[180:183], v[28:31], a[116:119] + ds_read_b128 v[100:103], v209 offset:30080 + v_mfma_f32_16x16x32_bf16 a[120:123], v[180:183], v[32:35], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[180:183], v[36:39], a[124:127] + ds_read_b128 v[132:135], v209 offset:30144 + v_mfma_f32_16x16x32_bf16 a[0:3], v[184:187], v[40:43], a[0:3] + s_add_u32 m0, 0xc600, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[4:7], v[184:187], v[44:47], a[4:7] + ds_read_b128 v[136:139], v218 + v_mfma_f32_16x16x32_bf16 a[8:11], v[184:187], v[48:51], a[8:11] + v_mfma_f32_16x16x32_bf16 a[12:15], v[184:187], v[52:55], a[12:15] + ds_read_b128 v[152:155], v218 offset:64 + v_mfma_f32_16x16x32_bf16 a[16:19], v[184:187], v[56:59], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[184:187], v[60:63], a[20:23] + ds_read_b128 v[140:143], v218 offset:512 + v_mfma_f32_16x16x32_bf16 a[24:27], v[184:187], v[64:67], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[184:187], v[68:71], a[28:31] + ds_read_b128 v[156:159], v218 offset:576 + v_mfma_f32_16x16x32_bf16 a[32:35], v[188:191], v[40:43], a[32:35] + s_add_u32 m0, 0xd680, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[36:39], v[188:191], v[44:47], a[36:39] + ds_read_b128 v[144:147], v218 offset:4224 + v_mfma_f32_16x16x32_bf16 a[40:43], v[188:191], v[48:51], a[40:43] + v_mfma_f32_16x16x32_bf16 a[44:47], v[188:191], v[52:55], a[44:47] + ds_read_b128 v[160:163], v218 offset:4288 + v_mfma_f32_16x16x32_bf16 a[48:51], v[188:191], v[56:59], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[188:191], v[60:63], a[52:55] + ds_read_b128 v[148:151], v218 offset:4736 + v_mfma_f32_16x16x32_bf16 a[56:59], v[188:191], v[64:67], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[188:191], v[68:71], a[60:63] + ds_read_b128 v[164:167], v218 offset:4800 + v_mfma_f32_16x16x32_bf16 a[64:67], v[192:195], v[40:43], a[64:67] + s_add_u32 m0, 0xe700, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[68:71], v[192:195], v[44:47], a[68:71] + v_mfma_f32_16x16x32_bf16 a[72:75], v[192:195], v[48:51], a[72:75] + v_mfma_f32_16x16x32_bf16 a[76:79], v[192:195], v[52:55], a[76:79] + v_mfma_f32_16x16x32_bf16 a[80:83], v[192:195], v[56:59], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[192:195], v[60:63], a[84:87] + v_mfma_f32_16x16x32_bf16 a[88:91], v[192:195], v[64:67], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[192:195], v[68:71], a[92:95] + v_mfma_f32_16x16x32_bf16 a[96:99], v[196:199], v[40:43], a[96:99] + s_add_u32 m0, 0xf780, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[100:103], v[196:199], v[44:47], a[100:103] + v_mfma_f32_16x16x32_bf16 a[104:107], v[196:199], v[48:51], a[104:107] + s_add_u32 s52, 0x80, s49 + s_cmp_lt_u32 s52, s50 + s_cselect_b32 s63, s63, 0 + v_mfma_f32_16x16x32_bf16 a[108:111], v[196:199], v[52:55], a[108:111] + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_mfma_f32_16x16x32_bf16 a[112:115], v[196:199], v[56:59], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[196:199], v[60:63], a[116:119] + v_mfma_f32_16x16x32_bf16 a[120:123], v[196:199], v[64:67], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[196:199], v[68:71], a[124:127] + s_waitcnt vmcnt(12) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[128:131], v[168:171], v[72:75], a[128:131] + s_add_u32 m0, 0x8400, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[132:135], v[168:171], v[76:79], a[132:135] + ds_read_b128 v[8:11], v208 + v_mfma_f32_16x16x32_bf16 a[136:139], v[168:171], v[80:83], a[136:139] + v_mfma_f32_16x16x32_bf16 a[140:143], v[168:171], v[84:87], a[140:143] + ds_read_b128 v[40:43], v208 offset:64 + v_mfma_f32_16x16x32_bf16 a[144:147], v[168:171], v[88:91], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[168:171], v[92:95], a[148:151] + ds_read_b128 v[12:15], v208 offset:512 + v_mfma_f32_16x16x32_bf16 a[152:155], v[168:171], v[96:99], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[168:171], v[100:103], a[156:159] + ds_read_b128 v[44:47], v208 offset:576 + v_mfma_f32_16x16x32_bf16 a[160:163], v[172:175], v[72:75], a[160:163] + s_add_u32 m0, 0x9480, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[164:167], v[172:175], v[76:79], a[164:167] + ds_read_b128 v[16:19], v208 offset:4224 + v_mfma_f32_16x16x32_bf16 a[168:171], v[172:175], v[80:83], a[168:171] + v_mfma_f32_16x16x32_bf16 a[172:175], v[172:175], v[84:87], a[172:175] + ds_read_b128 v[48:51], v208 offset:4288 + v_mfma_f32_16x16x32_bf16 a[176:179], v[172:175], v[88:91], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[172:175], v[92:95], a[180:183] + ds_read_b128 v[20:23], v208 offset:4736 + v_mfma_f32_16x16x32_bf16 a[184:187], v[172:175], v[96:99], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[172:175], v[100:103], a[188:191] + ds_read_b128 v[52:55], v208 offset:4800 + v_mfma_f32_16x16x32_bf16 a[192:195], v[176:179], v[72:75], a[192:195] + s_add_u32 m0, 0xa500, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[196:199], v[176:179], v[76:79], a[196:199] + ds_read_b128 v[24:27], v208 offset:8448 + v_mfma_f32_16x16x32_bf16 a[200:203], v[176:179], v[80:83], a[200:203] + v_mfma_f32_16x16x32_bf16 a[204:207], v[176:179], v[84:87], a[204:207] + ds_read_b128 v[56:59], v208 offset:8512 + v_mfma_f32_16x16x32_bf16 a[208:211], v[176:179], v[88:91], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[176:179], v[92:95], a[212:215] + ds_read_b128 v[28:31], v208 offset:8960 + v_mfma_f32_16x16x32_bf16 a[216:219], v[176:179], v[96:99], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[176:179], v[100:103], a[220:223] + ds_read_b128 v[60:63], v208 offset:9024 + v_mfma_f32_16x16x32_bf16 a[224:227], v[180:183], v[72:75], a[224:227] + s_add_u32 m0, 0xb580, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[228:231], v[180:183], v[76:79], a[228:231] + ds_read_b128 v[32:35], v208 offset:12672 + v_mfma_f32_16x16x32_bf16 a[232:235], v[180:183], v[80:83], a[232:235] + v_mfma_f32_16x16x32_bf16 a[236:239], v[180:183], v[84:87], a[236:239] + ds_read_b128 v[64:67], v208 offset:12736 + v_mfma_f32_16x16x32_bf16 a[240:243], v[180:183], v[88:91], a[240:243] + v_mfma_f32_16x16x32_bf16 a[244:247], v[180:183], v[92:95], a[244:247] + ds_read_b128 v[36:39], v208 offset:13184 + v_mfma_f32_16x16x32_bf16 a[248:251], v[180:183], v[96:99], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[180:183], v[100:103], a[252:255] + ds_read_b128 v[68:71], v208 offset:13248 + v_mfma_f32_16x16x32_bf16 a[128:131], v[184:187], v[104:107], a[128:131] + s_add_u32 m0, 0xc600, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[132:135], v[184:187], v[108:111], a[132:135] + v_mfma_f32_16x16x32_bf16 a[136:139], v[184:187], v[112:115], a[136:139] + v_mfma_f32_16x16x32_bf16 a[140:143], v[184:187], v[116:119], a[140:143] + v_mfma_f32_16x16x32_bf16 a[144:147], v[184:187], v[120:123], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[184:187], v[124:127], a[148:151] + v_mfma_f32_16x16x32_bf16 a[152:155], v[184:187], v[128:131], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[184:187], v[132:135], a[156:159] + v_mfma_f32_16x16x32_bf16 a[160:163], v[188:191], v[104:107], a[160:163] + s_add_u32 m0, 0xd680, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[164:167], v[188:191], v[108:111], a[164:167] + v_mfma_f32_16x16x32_bf16 a[168:171], v[188:191], v[112:115], a[168:171] + v_mfma_f32_16x16x32_bf16 a[172:175], v[188:191], v[116:119], a[172:175] + v_mfma_f32_16x16x32_bf16 a[176:179], v[188:191], v[120:123], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[188:191], v[124:127], a[180:183] + v_mfma_f32_16x16x32_bf16 a[184:187], v[188:191], v[128:131], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[188:191], v[132:135], a[188:191] + v_mfma_f32_16x16x32_bf16 a[192:195], v[192:195], v[104:107], a[192:195] + s_add_u32 m0, 0xe700, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[196:199], v[192:195], v[108:111], a[196:199] + v_mfma_f32_16x16x32_bf16 a[200:203], v[192:195], v[112:115], a[200:203] + v_mfma_f32_16x16x32_bf16 a[204:207], v[192:195], v[116:119], a[204:207] + v_mfma_f32_16x16x32_bf16 a[208:211], v[192:195], v[120:123], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[192:195], v[124:127], a[212:215] + v_mfma_f32_16x16x32_bf16 a[216:219], v[192:195], v[128:131], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[192:195], v[132:135], a[220:223] + v_mfma_f32_16x16x32_bf16 a[224:227], v[196:199], v[104:107], a[224:227] + s_add_u32 m0, 0xf780, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[228:231], v[196:199], v[108:111], a[228:231] + s_add_u32 s51, 0xc0, s49 + s_cmp_lt_u32 s51, s50 + s_cselect_b32 s62, s62, 0 + v_mfma_f32_16x16x32_bf16 a[232:235], v[196:199], v[112:115], a[232:235] + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + v_mfma_f32_16x16x32_bf16 a[236:239], v[196:199], v[116:119], a[236:239] + v_mfma_f32_16x16x32_bf16 a[240:243], v[196:199], v[120:123], a[240:243] + s_addk_i32 s49, 0x40 + s_cmp_lt_i32 s49, s50 + v_mfma_f32_16x16x32_bf16 a[244:247], v[196:199], v[124:127], a[244:247] + v_mfma_f32_16x16x32_bf16 a[248:251], v[196:199], v[128:131], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[196:199], v[132:135], a[252:255] + s_cbranch_scc0 label_0AA6 + s_branch label_040D + +label_075D: + s_waitcnt vmcnt(8) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[0:3], v[136:139], v[8:11], a[0:3] + v_mfma_f32_16x16x32_bf16 a[4:7], v[136:139], v[12:15], a[4:7] + ds_read_b128 v[72:75], v208 offset:16896 + v_mfma_f32_16x16x32_bf16 a[8:11], v[136:139], v[16:19], a[8:11] + s_add_u32 m0, 0, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[12:15], v[136:139], v[20:23], a[12:15] + ds_read_b128 v[104:107], v208 offset:16960 + v_mfma_f32_16x16x32_bf16 a[16:19], v[136:139], v[24:27], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[136:139], v[28:31], a[20:23] + ds_read_b128 v[76:79], v208 offset:17408 + v_mfma_f32_16x16x32_bf16 a[24:27], v[136:139], v[32:35], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[136:139], v[36:39], a[28:31] + ds_read_b128 v[108:111], v208 offset:17472 + v_mfma_f32_16x16x32_bf16 a[32:35], v[140:143], v[8:11], a[32:35] + v_mfma_f32_16x16x32_bf16 a[36:39], v[140:143], v[12:15], a[36:39] + ds_read_b128 v[80:83], v208 offset:21120 + v_mfma_f32_16x16x32_bf16 a[40:43], v[140:143], v[16:19], a[40:43] + s_add_u32 m0, 0x1080, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[44:47], v[140:143], v[20:23], a[44:47] + ds_read_b128 v[112:115], v208 offset:21184 + v_mfma_f32_16x16x32_bf16 a[48:51], v[140:143], v[24:27], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[140:143], v[28:31], a[52:55] + ds_read_b128 v[84:87], v208 offset:21632 + v_mfma_f32_16x16x32_bf16 a[56:59], v[140:143], v[32:35], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[140:143], v[36:39], a[60:63] + ds_read_b128 v[116:119], v208 offset:21696 + v_mfma_f32_16x16x32_bf16 a[64:67], v[144:147], v[8:11], a[64:67] + v_mfma_f32_16x16x32_bf16 a[68:71], v[144:147], v[12:15], a[68:71] + ds_read_b128 v[88:91], v208 offset:25344 + v_mfma_f32_16x16x32_bf16 a[72:75], v[144:147], v[16:19], a[72:75] + s_add_u32 m0, 0x2100, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[76:79], v[144:147], v[20:23], a[76:79] + ds_read_b128 v[120:123], v208 offset:25408 + v_mfma_f32_16x16x32_bf16 a[80:83], v[144:147], v[24:27], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[144:147], v[28:31], a[84:87] + ds_read_b128 v[92:95], v208 offset:25856 + v_mfma_f32_16x16x32_bf16 a[88:91], v[144:147], v[32:35], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[144:147], v[36:39], a[92:95] + ds_read_b128 v[124:127], v208 offset:25920 + v_mfma_f32_16x16x32_bf16 a[96:99], v[148:151], v[8:11], a[96:99] + v_mfma_f32_16x16x32_bf16 a[100:103], v[148:151], v[12:15], a[100:103] + ds_read_b128 v[96:99], v208 offset:29568 + v_mfma_f32_16x16x32_bf16 a[104:107], v[148:151], v[16:19], a[104:107] + s_add_u32 m0, 0x3180, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[108:111], v[148:151], v[20:23], a[108:111] + ds_read_b128 v[128:131], v208 offset:29632 + v_mfma_f32_16x16x32_bf16 a[112:115], v[148:151], v[24:27], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[148:151], v[28:31], a[116:119] + ds_read_b128 v[100:103], v208 offset:30080 + v_mfma_f32_16x16x32_bf16 a[120:123], v[148:151], v[32:35], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[148:151], v[36:39], a[124:127] + ds_read_b128 v[132:135], v208 offset:30144 + v_mfma_f32_16x16x32_bf16 a[0:3], v[152:155], v[40:43], a[0:3] + v_mfma_f32_16x16x32_bf16 a[4:7], v[152:155], v[44:47], a[4:7] + ds_read_b128 v[168:171], v219 + v_mfma_f32_16x16x32_bf16 a[8:11], v[152:155], v[48:51], a[8:11] + s_add_u32 m0, 0x4200, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[12:15], v[152:155], v[52:55], a[12:15] + ds_read_b128 v[184:187], v219 offset:64 + v_mfma_f32_16x16x32_bf16 a[16:19], v[152:155], v[56:59], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[152:155], v[60:63], a[20:23] + ds_read_b128 v[172:175], v219 offset:512 + v_mfma_f32_16x16x32_bf16 a[24:27], v[152:155], v[64:67], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[152:155], v[68:71], a[28:31] + ds_read_b128 v[188:191], v219 offset:576 + v_mfma_f32_16x16x32_bf16 a[32:35], v[156:159], v[40:43], a[32:35] + v_mfma_f32_16x16x32_bf16 a[36:39], v[156:159], v[44:47], a[36:39] + ds_read_b128 v[176:179], v219 offset:4224 + v_mfma_f32_16x16x32_bf16 a[40:43], v[156:159], v[48:51], a[40:43] + s_add_u32 m0, 0x5280, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[44:47], v[156:159], v[52:55], a[44:47] + ds_read_b128 v[192:195], v219 offset:4288 + v_mfma_f32_16x16x32_bf16 a[48:51], v[156:159], v[56:59], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[156:159], v[60:63], a[52:55] + ds_read_b128 v[180:183], v219 offset:4736 + v_mfma_f32_16x16x32_bf16 a[56:59], v[156:159], v[64:67], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[156:159], v[68:71], a[60:63] + ds_read_b128 v[196:199], v219 offset:4800 + v_mfma_f32_16x16x32_bf16 a[64:67], v[160:163], v[40:43], a[64:67] + v_mfma_f32_16x16x32_bf16 a[68:71], v[160:163], v[44:47], a[68:71] + v_mfma_f32_16x16x32_bf16 a[72:75], v[160:163], v[48:51], a[72:75] + s_add_u32 m0, 0x6300, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[76:79], v[160:163], v[52:55], a[76:79] + v_mfma_f32_16x16x32_bf16 a[80:83], v[160:163], v[56:59], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[160:163], v[60:63], a[84:87] + v_mfma_f32_16x16x32_bf16 a[88:91], v[160:163], v[64:67], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[160:163], v[68:71], a[92:95] + v_mfma_f32_16x16x32_bf16 a[96:99], v[164:167], v[40:43], a[96:99] + v_mfma_f32_16x16x32_bf16 a[100:103], v[164:167], v[44:47], a[100:103] + v_mfma_f32_16x16x32_bf16 a[104:107], v[164:167], v[48:51], a[104:107] + s_add_u32 m0, 0x7380, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[108:111], v[164:167], v[52:55], a[108:111] + s_add_u32 s52, 0x80, s49 + s_cmp_lt_u32 s52, s50 + s_cselect_b32 s63, s63, 0 + v_mfma_f32_16x16x32_bf16 a[112:115], v[164:167], v[56:59], a[112:115] + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_mfma_f32_16x16x32_bf16 a[116:119], v[164:167], v[60:63], a[116:119] + v_mfma_f32_16x16x32_bf16 a[120:123], v[164:167], v[64:67], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[164:167], v[68:71], a[124:127] + s_waitcnt vmcnt(12) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[128:131], v[136:139], v[72:75], a[128:131] + v_mfma_f32_16x16x32_bf16 a[132:135], v[136:139], v[76:79], a[132:135] + ds_read_b128 v[8:11], v209 + v_mfma_f32_16x16x32_bf16 a[136:139], v[136:139], v[80:83], a[136:139] + s_add_u32 m0, 0, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[140:143], v[136:139], v[84:87], a[140:143] + ds_read_b128 v[40:43], v209 offset:64 + v_mfma_f32_16x16x32_bf16 a[144:147], v[136:139], v[88:91], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[136:139], v[92:95], a[148:151] + ds_read_b128 v[12:15], v209 offset:512 + v_mfma_f32_16x16x32_bf16 a[152:155], v[136:139], v[96:99], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[136:139], v[100:103], a[156:159] + ds_read_b128 v[44:47], v209 offset:576 + v_mfma_f32_16x16x32_bf16 a[160:163], v[140:143], v[72:75], a[160:163] + v_mfma_f32_16x16x32_bf16 a[164:167], v[140:143], v[76:79], a[164:167] + ds_read_b128 v[16:19], v209 offset:4224 + v_mfma_f32_16x16x32_bf16 a[168:171], v[140:143], v[80:83], a[168:171] + s_add_u32 m0, 0x1080, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[172:175], v[140:143], v[84:87], a[172:175] + ds_read_b128 v[48:51], v209 offset:4288 + v_mfma_f32_16x16x32_bf16 a[176:179], v[140:143], v[88:91], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[140:143], v[92:95], a[180:183] + ds_read_b128 v[20:23], v209 offset:4736 + v_mfma_f32_16x16x32_bf16 a[184:187], v[140:143], v[96:99], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[140:143], v[100:103], a[188:191] + ds_read_b128 v[52:55], v209 offset:4800 + v_mfma_f32_16x16x32_bf16 a[192:195], v[144:147], v[72:75], a[192:195] + v_mfma_f32_16x16x32_bf16 a[196:199], v[144:147], v[76:79], a[196:199] + ds_read_b128 v[24:27], v209 offset:8448 + v_mfma_f32_16x16x32_bf16 a[200:203], v[144:147], v[80:83], a[200:203] + s_add_u32 m0, 0x2100, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[204:207], v[144:147], v[84:87], a[204:207] + ds_read_b128 v[56:59], v209 offset:8512 + v_mfma_f32_16x16x32_bf16 a[208:211], v[144:147], v[88:91], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[144:147], v[92:95], a[212:215] + ds_read_b128 v[28:31], v209 offset:8960 + v_mfma_f32_16x16x32_bf16 a[216:219], v[144:147], v[96:99], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[144:147], v[100:103], a[220:223] + ds_read_b128 v[60:63], v209 offset:9024 + v_mfma_f32_16x16x32_bf16 a[224:227], v[148:151], v[72:75], a[224:227] + v_mfma_f32_16x16x32_bf16 a[228:231], v[148:151], v[76:79], a[228:231] + ds_read_b128 v[32:35], v209 offset:12672 + v_mfma_f32_16x16x32_bf16 a[232:235], v[148:151], v[80:83], a[232:235] + s_add_u32 m0, 0x3180, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[236:239], v[148:151], v[84:87], a[236:239] + ds_read_b128 v[64:67], v209 offset:12736 + v_mfma_f32_16x16x32_bf16 a[240:243], v[148:151], v[88:91], a[240:243] + v_mfma_f32_16x16x32_bf16 a[244:247], v[148:151], v[92:95], a[244:247] + ds_read_b128 v[36:39], v209 offset:13184 + v_mfma_f32_16x16x32_bf16 a[248:251], v[148:151], v[96:99], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[148:151], v[100:103], a[252:255] + ds_read_b128 v[68:71], v209 offset:13248 + v_mfma_f32_16x16x32_bf16 a[128:131], v[152:155], v[104:107], a[128:131] + v_mfma_f32_16x16x32_bf16 a[132:135], v[152:155], v[108:111], a[132:135] + v_mfma_f32_16x16x32_bf16 a[136:139], v[152:155], v[112:115], a[136:139] + s_add_u32 m0, 0x4200, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[140:143], v[152:155], v[116:119], a[140:143] + v_mfma_f32_16x16x32_bf16 a[144:147], v[152:155], v[120:123], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[152:155], v[124:127], a[148:151] + v_mfma_f32_16x16x32_bf16 a[152:155], v[152:155], v[128:131], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[152:155], v[132:135], a[156:159] + v_mfma_f32_16x16x32_bf16 a[160:163], v[156:159], v[104:107], a[160:163] + v_mfma_f32_16x16x32_bf16 a[164:167], v[156:159], v[108:111], a[164:167] + v_mfma_f32_16x16x32_bf16 a[168:171], v[156:159], v[112:115], a[168:171] + s_add_u32 m0, 0x5280, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[172:175], v[156:159], v[116:119], a[172:175] + v_mfma_f32_16x16x32_bf16 a[176:179], v[156:159], v[120:123], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[156:159], v[124:127], a[180:183] + v_mfma_f32_16x16x32_bf16 a[184:187], v[156:159], v[128:131], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[156:159], v[132:135], a[188:191] + v_mfma_f32_16x16x32_bf16 a[192:195], v[160:163], v[104:107], a[192:195] + v_mfma_f32_16x16x32_bf16 a[196:199], v[160:163], v[108:111], a[196:199] + v_mfma_f32_16x16x32_bf16 a[200:203], v[160:163], v[112:115], a[200:203] + s_add_u32 m0, 0x6300, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[204:207], v[160:163], v[116:119], a[204:207] + v_mfma_f32_16x16x32_bf16 a[208:211], v[160:163], v[120:123], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[160:163], v[124:127], a[212:215] + v_mfma_f32_16x16x32_bf16 a[216:219], v[160:163], v[128:131], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[160:163], v[132:135], a[220:223] + v_mfma_f32_16x16x32_bf16 a[224:227], v[164:167], v[104:107], a[224:227] + v_mfma_f32_16x16x32_bf16 a[228:231], v[164:167], v[108:111], a[228:231] + v_mfma_f32_16x16x32_bf16 a[232:235], v[164:167], v[112:115], a[232:235] + s_add_u32 m0, 0x7380, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[236:239], v[164:167], v[116:119], a[236:239] + s_add_u32 s51, 0xc0, s49 + s_cmp_lt_u32 s51, s50 + s_cselect_b32 s62, s62, 0 + v_mfma_f32_16x16x32_bf16 a[240:243], v[164:167], v[120:123], a[240:243] + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + v_mfma_f32_16x16x32_bf16 a[244:247], v[164:167], v[124:127], a[244:247] + s_addk_i32 s49, 0x40 + s_cmp_lt_i32 s49, s50 + v_mfma_f32_16x16x32_bf16 a[248:251], v[164:167], v[128:131], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[164:167], v[132:135], a[252:255] + s_cbranch_scc0 label_0AA6 + s_waitcnt vmcnt(8) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[0:3], v[168:171], v[8:11], a[0:3] + v_mfma_f32_16x16x32_bf16 a[4:7], v[168:171], v[12:15], a[4:7] + ds_read_b128 v[72:75], v209 offset:16896 + v_mfma_f32_16x16x32_bf16 a[8:11], v[168:171], v[16:19], a[8:11] + s_add_u32 m0, 0x8400, s61 + buffer_load_dwordx4 v210, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[12:15], v[168:171], v[20:23], a[12:15] + ds_read_b128 v[104:107], v209 offset:16960 + v_mfma_f32_16x16x32_bf16 a[16:19], v[168:171], v[24:27], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[168:171], v[28:31], a[20:23] + ds_read_b128 v[76:79], v209 offset:17408 + v_mfma_f32_16x16x32_bf16 a[24:27], v[168:171], v[32:35], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[168:171], v[36:39], a[28:31] + ds_read_b128 v[108:111], v209 offset:17472 + v_mfma_f32_16x16x32_bf16 a[32:35], v[172:175], v[8:11], a[32:35] + v_mfma_f32_16x16x32_bf16 a[36:39], v[172:175], v[12:15], a[36:39] + ds_read_b128 v[80:83], v209 offset:21120 + v_mfma_f32_16x16x32_bf16 a[40:43], v[172:175], v[16:19], a[40:43] + s_add_u32 m0, 0x9480, s61 + buffer_load_dwordx4 v211, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[44:47], v[172:175], v[20:23], a[44:47] + ds_read_b128 v[112:115], v209 offset:21184 + v_mfma_f32_16x16x32_bf16 a[48:51], v[172:175], v[24:27], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[172:175], v[28:31], a[52:55] + ds_read_b128 v[84:87], v209 offset:21632 + v_mfma_f32_16x16x32_bf16 a[56:59], v[172:175], v[32:35], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[172:175], v[36:39], a[60:63] + ds_read_b128 v[116:119], v209 offset:21696 + v_mfma_f32_16x16x32_bf16 a[64:67], v[176:179], v[8:11], a[64:67] + v_mfma_f32_16x16x32_bf16 a[68:71], v[176:179], v[12:15], a[68:71] + ds_read_b128 v[88:91], v209 offset:25344 + v_mfma_f32_16x16x32_bf16 a[72:75], v[176:179], v[16:19], a[72:75] + s_add_u32 m0, 0xa500, s61 + buffer_load_dwordx4 v212, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[76:79], v[176:179], v[20:23], a[76:79] + ds_read_b128 v[120:123], v209 offset:25408 + v_mfma_f32_16x16x32_bf16 a[80:83], v[176:179], v[24:27], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[176:179], v[28:31], a[84:87] + ds_read_b128 v[92:95], v209 offset:25856 + v_mfma_f32_16x16x32_bf16 a[88:91], v[176:179], v[32:35], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[176:179], v[36:39], a[92:95] + ds_read_b128 v[124:127], v209 offset:25920 + v_mfma_f32_16x16x32_bf16 a[96:99], v[180:183], v[8:11], a[96:99] + v_mfma_f32_16x16x32_bf16 a[100:103], v[180:183], v[12:15], a[100:103] + ds_read_b128 v[96:99], v209 offset:29568 + v_mfma_f32_16x16x32_bf16 a[104:107], v[180:183], v[16:19], a[104:107] + s_add_u32 m0, 0xb580, s61 + buffer_load_dwordx4 v213, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[108:111], v[180:183], v[20:23], a[108:111] + ds_read_b128 v[128:131], v209 offset:29632 + v_mfma_f32_16x16x32_bf16 a[112:115], v[180:183], v[24:27], a[112:115] + v_mfma_f32_16x16x32_bf16 a[116:119], v[180:183], v[28:31], a[116:119] + ds_read_b128 v[100:103], v209 offset:30080 + v_mfma_f32_16x16x32_bf16 a[120:123], v[180:183], v[32:35], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[180:183], v[36:39], a[124:127] + ds_read_b128 v[132:135], v209 offset:30144 + v_mfma_f32_16x16x32_bf16 a[0:3], v[184:187], v[40:43], a[0:3] + v_mfma_f32_16x16x32_bf16 a[4:7], v[184:187], v[44:47], a[4:7] + ds_read_b128 v[136:139], v218 + v_mfma_f32_16x16x32_bf16 a[8:11], v[184:187], v[48:51], a[8:11] + s_add_u32 m0, 0xc600, s61 + buffer_load_dwordx4 v214, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[12:15], v[184:187], v[52:55], a[12:15] + ds_read_b128 v[152:155], v218 offset:64 + v_mfma_f32_16x16x32_bf16 a[16:19], v[184:187], v[56:59], a[16:19] + v_mfma_f32_16x16x32_bf16 a[20:23], v[184:187], v[60:63], a[20:23] + ds_read_b128 v[140:143], v218 offset:512 + v_mfma_f32_16x16x32_bf16 a[24:27], v[184:187], v[64:67], a[24:27] + v_mfma_f32_16x16x32_bf16 a[28:31], v[184:187], v[68:71], a[28:31] + ds_read_b128 v[156:159], v218 offset:576 + v_mfma_f32_16x16x32_bf16 a[32:35], v[188:191], v[40:43], a[32:35] + v_mfma_f32_16x16x32_bf16 a[36:39], v[188:191], v[44:47], a[36:39] + ds_read_b128 v[144:147], v218 offset:4224 + v_mfma_f32_16x16x32_bf16 a[40:43], v[188:191], v[48:51], a[40:43] + s_add_u32 m0, 0xd680, s61 + buffer_load_dwordx4 v215, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[44:47], v[188:191], v[52:55], a[44:47] + ds_read_b128 v[160:163], v218 offset:4288 + v_mfma_f32_16x16x32_bf16 a[48:51], v[188:191], v[56:59], a[48:51] + v_mfma_f32_16x16x32_bf16 a[52:55], v[188:191], v[60:63], a[52:55] + ds_read_b128 v[148:151], v218 offset:4736 + v_mfma_f32_16x16x32_bf16 a[56:59], v[188:191], v[64:67], a[56:59] + v_mfma_f32_16x16x32_bf16 a[60:63], v[188:191], v[68:71], a[60:63] + ds_read_b128 v[164:167], v218 offset:4800 + v_mfma_f32_16x16x32_bf16 a[64:67], v[192:195], v[40:43], a[64:67] + v_mfma_f32_16x16x32_bf16 a[68:71], v[192:195], v[44:47], a[68:71] + v_mfma_f32_16x16x32_bf16 a[72:75], v[192:195], v[48:51], a[72:75] + s_add_u32 m0, 0xe700, s61 + buffer_load_dwordx4 v216, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[76:79], v[192:195], v[52:55], a[76:79] + v_mfma_f32_16x16x32_bf16 a[80:83], v[192:195], v[56:59], a[80:83] + v_mfma_f32_16x16x32_bf16 a[84:87], v[192:195], v[60:63], a[84:87] + v_mfma_f32_16x16x32_bf16 a[88:91], v[192:195], v[64:67], a[88:91] + v_mfma_f32_16x16x32_bf16 a[92:95], v[192:195], v[68:71], a[92:95] + v_mfma_f32_16x16x32_bf16 a[96:99], v[196:199], v[40:43], a[96:99] + v_mfma_f32_16x16x32_bf16 a[100:103], v[196:199], v[44:47], a[100:103] + v_mfma_f32_16x16x32_bf16 a[104:107], v[196:199], v[48:51], a[104:107] + s_add_u32 m0, 0xf780, s61 + buffer_load_dwordx4 v217, s[16:19], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[108:111], v[196:199], v[52:55], a[108:111] + s_add_u32 s52, 0x80, s49 + s_cmp_lt_u32 s52, s50 + s_cselect_b32 s63, s63, 0 + v_mfma_f32_16x16x32_bf16 a[112:115], v[196:199], v[56:59], a[112:115] + s_add_u32 s16, s63, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s63 + v_mfma_f32_16x16x32_bf16 a[116:119], v[196:199], v[60:63], a[116:119] + v_mfma_f32_16x16x32_bf16 a[120:123], v[196:199], v[64:67], a[120:123] + v_mfma_f32_16x16x32_bf16 a[124:127], v[196:199], v[68:71], a[124:127] + s_waitcnt vmcnt(12) lgkmcnt(0) + s_barrier + v_mfma_f32_16x16x32_bf16 a[128:131], v[168:171], v[72:75], a[128:131] + v_mfma_f32_16x16x32_bf16 a[132:135], v[168:171], v[76:79], a[132:135] + ds_read_b128 v[8:11], v208 + v_mfma_f32_16x16x32_bf16 a[136:139], v[168:171], v[80:83], a[136:139] + s_add_u32 m0, 0x8400, s60 + buffer_load_dwordx4 v200, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[140:143], v[168:171], v[84:87], a[140:143] + ds_read_b128 v[40:43], v208 offset:64 + v_mfma_f32_16x16x32_bf16 a[144:147], v[168:171], v[88:91], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[168:171], v[92:95], a[148:151] + ds_read_b128 v[12:15], v208 offset:512 + v_mfma_f32_16x16x32_bf16 a[152:155], v[168:171], v[96:99], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[168:171], v[100:103], a[156:159] + ds_read_b128 v[44:47], v208 offset:576 + v_mfma_f32_16x16x32_bf16 a[160:163], v[172:175], v[72:75], a[160:163] + v_mfma_f32_16x16x32_bf16 a[164:167], v[172:175], v[76:79], a[164:167] + ds_read_b128 v[16:19], v208 offset:4224 + v_mfma_f32_16x16x32_bf16 a[168:171], v[172:175], v[80:83], a[168:171] + s_add_u32 m0, 0x9480, s60 + buffer_load_dwordx4 v201, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[172:175], v[172:175], v[84:87], a[172:175] + ds_read_b128 v[48:51], v208 offset:4288 + v_mfma_f32_16x16x32_bf16 a[176:179], v[172:175], v[88:91], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[172:175], v[92:95], a[180:183] + ds_read_b128 v[20:23], v208 offset:4736 + v_mfma_f32_16x16x32_bf16 a[184:187], v[172:175], v[96:99], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[172:175], v[100:103], a[188:191] + ds_read_b128 v[52:55], v208 offset:4800 + v_mfma_f32_16x16x32_bf16 a[192:195], v[176:179], v[72:75], a[192:195] + v_mfma_f32_16x16x32_bf16 a[196:199], v[176:179], v[76:79], a[196:199] + ds_read_b128 v[24:27], v208 offset:8448 + v_mfma_f32_16x16x32_bf16 a[200:203], v[176:179], v[80:83], a[200:203] + s_add_u32 m0, 0xa500, s60 + buffer_load_dwordx4 v202, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[204:207], v[176:179], v[84:87], a[204:207] + ds_read_b128 v[56:59], v208 offset:8512 + v_mfma_f32_16x16x32_bf16 a[208:211], v[176:179], v[88:91], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[176:179], v[92:95], a[212:215] + ds_read_b128 v[28:31], v208 offset:8960 + v_mfma_f32_16x16x32_bf16 a[216:219], v[176:179], v[96:99], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[176:179], v[100:103], a[220:223] + ds_read_b128 v[60:63], v208 offset:9024 + v_mfma_f32_16x16x32_bf16 a[224:227], v[180:183], v[72:75], a[224:227] + v_mfma_f32_16x16x32_bf16 a[228:231], v[180:183], v[76:79], a[228:231] + ds_read_b128 v[32:35], v208 offset:12672 + v_mfma_f32_16x16x32_bf16 a[232:235], v[180:183], v[80:83], a[232:235] + s_add_u32 m0, 0xb580, s60 + buffer_load_dwordx4 v203, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[236:239], v[180:183], v[84:87], a[236:239] + ds_read_b128 v[64:67], v208 offset:12736 + v_mfma_f32_16x16x32_bf16 a[240:243], v[180:183], v[88:91], a[240:243] + v_mfma_f32_16x16x32_bf16 a[244:247], v[180:183], v[92:95], a[244:247] + ds_read_b128 v[36:39], v208 offset:13184 + v_mfma_f32_16x16x32_bf16 a[248:251], v[180:183], v[96:99], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[180:183], v[100:103], a[252:255] + ds_read_b128 v[68:71], v208 offset:13248 + v_mfma_f32_16x16x32_bf16 a[128:131], v[184:187], v[104:107], a[128:131] + v_mfma_f32_16x16x32_bf16 a[132:135], v[184:187], v[108:111], a[132:135] + v_mfma_f32_16x16x32_bf16 a[136:139], v[184:187], v[112:115], a[136:139] + s_add_u32 m0, 0xc600, s60 + buffer_load_dwordx4 v204, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[140:143], v[184:187], v[116:119], a[140:143] + v_mfma_f32_16x16x32_bf16 a[144:147], v[184:187], v[120:123], a[144:147] + v_mfma_f32_16x16x32_bf16 a[148:151], v[184:187], v[124:127], a[148:151] + v_mfma_f32_16x16x32_bf16 a[152:155], v[184:187], v[128:131], a[152:155] + v_mfma_f32_16x16x32_bf16 a[156:159], v[184:187], v[132:135], a[156:159] + v_mfma_f32_16x16x32_bf16 a[160:163], v[188:191], v[104:107], a[160:163] + v_mfma_f32_16x16x32_bf16 a[164:167], v[188:191], v[108:111], a[164:167] + v_mfma_f32_16x16x32_bf16 a[168:171], v[188:191], v[112:115], a[168:171] + s_add_u32 m0, 0xd680, s60 + buffer_load_dwordx4 v205, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[172:175], v[188:191], v[116:119], a[172:175] + v_mfma_f32_16x16x32_bf16 a[176:179], v[188:191], v[120:123], a[176:179] + v_mfma_f32_16x16x32_bf16 a[180:183], v[188:191], v[124:127], a[180:183] + v_mfma_f32_16x16x32_bf16 a[184:187], v[188:191], v[128:131], a[184:187] + v_mfma_f32_16x16x32_bf16 a[188:191], v[188:191], v[132:135], a[188:191] + v_mfma_f32_16x16x32_bf16 a[192:195], v[192:195], v[104:107], a[192:195] + v_mfma_f32_16x16x32_bf16 a[196:199], v[192:195], v[108:111], a[196:199] + v_mfma_f32_16x16x32_bf16 a[200:203], v[192:195], v[112:115], a[200:203] + s_add_u32 m0, 0xe700, s60 + buffer_load_dwordx4 v206, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[204:207], v[192:195], v[116:119], a[204:207] + v_mfma_f32_16x16x32_bf16 a[208:211], v[192:195], v[120:123], a[208:211] + v_mfma_f32_16x16x32_bf16 a[212:215], v[192:195], v[124:127], a[212:215] + v_mfma_f32_16x16x32_bf16 a[216:219], v[192:195], v[128:131], a[216:219] + v_mfma_f32_16x16x32_bf16 a[220:223], v[192:195], v[132:135], a[220:223] + v_mfma_f32_16x16x32_bf16 a[224:227], v[196:199], v[104:107], a[224:227] + v_mfma_f32_16x16x32_bf16 a[228:231], v[196:199], v[108:111], a[228:231] + v_mfma_f32_16x16x32_bf16 a[232:235], v[196:199], v[112:115], a[232:235] + s_add_u32 m0, 0xf780, s60 + buffer_load_dwordx4 v207, s[12:15], 0 offen lds + v_mfma_f32_16x16x32_bf16 a[236:239], v[196:199], v[116:119], a[236:239] + s_add_u32 s51, 0xc0, s49 + s_cmp_lt_u32 s51, s50 + s_cselect_b32 s62, s62, 0 + v_mfma_f32_16x16x32_bf16 a[240:243], v[196:199], v[120:123], a[240:243] + s_add_u32 s12, s62, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s62 + v_mfma_f32_16x16x32_bf16 a[244:247], v[196:199], v[124:127], a[244:247] + s_addk_i32 s49, 0x40 + s_cmp_lt_i32 s49, s50 + v_mfma_f32_16x16x32_bf16 a[248:251], v[196:199], v[128:131], a[248:251] + v_mfma_f32_16x16x32_bf16 a[252:255], v[196:199], v[132:135], a[252:255] + s_cbranch_scc0 label_0AA6 + s_branch label_075D + +label_0AA6: + s_mov_b32 s49, 0 + s_mul_i32 s50, 16, s47 + s_lshr_b32 s52, s43, 4 + s_sub_u32 s50, s52, s50 + s_waitcnt vmcnt(0) lgkmcnt(0) + s_barrier + v_accvgpr_read_b32 v8, a0 + v_accvgpr_read_b32 v9, a1 + v_accvgpr_read_b32 v10, a2 + v_accvgpr_read_b32 v11, a3 + v_accvgpr_read_b32 v12, a32 + v_accvgpr_read_b32 v13, a33 + v_accvgpr_read_b32 v14, a34 + v_accvgpr_read_b32 v15, a35 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v220, s[4:7], 0 offen + v_add_i32 v220, v220, 64 + v_accvgpr_read_b32 v8, a64 + v_accvgpr_read_b32 v9, a65 + v_accvgpr_read_b32 v10, a66 + v_accvgpr_read_b32 v11, a67 + v_accvgpr_read_b32 v12, a96 + v_accvgpr_read_b32 v13, a97 + v_accvgpr_read_b32 v14, a98 + v_accvgpr_read_b32 v15, a99 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v220, s[4:7], 0 offen + v_add_i32 v220, v220, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a4 + v_accvgpr_read_b32 v9, a5 + v_accvgpr_read_b32 v10, a6 + v_accvgpr_read_b32 v11, a7 + v_accvgpr_read_b32 v12, a36 + v_accvgpr_read_b32 v13, a37 + v_accvgpr_read_b32 v14, a38 + v_accvgpr_read_b32 v15, a39 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v221, s[4:7], 0 offen + v_add_i32 v221, v221, 64 + v_accvgpr_read_b32 v8, a68 + v_accvgpr_read_b32 v9, a69 + v_accvgpr_read_b32 v10, a70 + v_accvgpr_read_b32 v11, a71 + v_accvgpr_read_b32 v12, a100 + v_accvgpr_read_b32 v13, a101 + v_accvgpr_read_b32 v14, a102 + v_accvgpr_read_b32 v15, a103 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v221, s[4:7], 0 offen + v_add_i32 v221, v221, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a8 + v_accvgpr_read_b32 v9, a9 + v_accvgpr_read_b32 v10, a10 + v_accvgpr_read_b32 v11, a11 + v_accvgpr_read_b32 v12, a40 + v_accvgpr_read_b32 v13, a41 + v_accvgpr_read_b32 v14, a42 + v_accvgpr_read_b32 v15, a43 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v222, s[4:7], 0 offen + v_add_i32 v222, v222, 64 + v_accvgpr_read_b32 v8, a72 + v_accvgpr_read_b32 v9, a73 + v_accvgpr_read_b32 v10, a74 + v_accvgpr_read_b32 v11, a75 + v_accvgpr_read_b32 v12, a104 + v_accvgpr_read_b32 v13, a105 + v_accvgpr_read_b32 v14, a106 + v_accvgpr_read_b32 v15, a107 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v222, s[4:7], 0 offen + v_add_i32 v222, v222, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a12 + v_accvgpr_read_b32 v9, a13 + v_accvgpr_read_b32 v10, a14 + v_accvgpr_read_b32 v11, a15 + v_accvgpr_read_b32 v12, a44 + v_accvgpr_read_b32 v13, a45 + v_accvgpr_read_b32 v14, a46 + v_accvgpr_read_b32 v15, a47 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v223, s[4:7], 0 offen + v_add_i32 v223, v223, 64 + v_accvgpr_read_b32 v8, a76 + v_accvgpr_read_b32 v9, a77 + v_accvgpr_read_b32 v10, a78 + v_accvgpr_read_b32 v11, a79 + v_accvgpr_read_b32 v12, a108 + v_accvgpr_read_b32 v13, a109 + v_accvgpr_read_b32 v14, a110 + v_accvgpr_read_b32 v15, a111 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v223, s[4:7], 0 offen + v_add_i32 v223, v223, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a16 + v_accvgpr_read_b32 v9, a17 + v_accvgpr_read_b32 v10, a18 + v_accvgpr_read_b32 v11, a19 + v_accvgpr_read_b32 v12, a48 + v_accvgpr_read_b32 v13, a49 + v_accvgpr_read_b32 v14, a50 + v_accvgpr_read_b32 v15, a51 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v224, s[4:7], 0 offen + v_add_i32 v224, v224, 64 + v_accvgpr_read_b32 v8, a80 + v_accvgpr_read_b32 v9, a81 + v_accvgpr_read_b32 v10, a82 + v_accvgpr_read_b32 v11, a83 + v_accvgpr_read_b32 v12, a112 + v_accvgpr_read_b32 v13, a113 + v_accvgpr_read_b32 v14, a114 + v_accvgpr_read_b32 v15, a115 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v224, s[4:7], 0 offen + v_add_i32 v224, v224, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a20 + v_accvgpr_read_b32 v9, a21 + v_accvgpr_read_b32 v10, a22 + v_accvgpr_read_b32 v11, a23 + v_accvgpr_read_b32 v12, a52 + v_accvgpr_read_b32 v13, a53 + v_accvgpr_read_b32 v14, a54 + v_accvgpr_read_b32 v15, a55 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v225, s[4:7], 0 offen + v_add_i32 v225, v225, 64 + v_accvgpr_read_b32 v8, a84 + v_accvgpr_read_b32 v9, a85 + v_accvgpr_read_b32 v10, a86 + v_accvgpr_read_b32 v11, a87 + v_accvgpr_read_b32 v12, a116 + v_accvgpr_read_b32 v13, a117 + v_accvgpr_read_b32 v14, a118 + v_accvgpr_read_b32 v15, a119 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v225, s[4:7], 0 offen + v_add_i32 v225, v225, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a24 + v_accvgpr_read_b32 v9, a25 + v_accvgpr_read_b32 v10, a26 + v_accvgpr_read_b32 v11, a27 + v_accvgpr_read_b32 v12, a56 + v_accvgpr_read_b32 v13, a57 + v_accvgpr_read_b32 v14, a58 + v_accvgpr_read_b32 v15, a59 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v226, s[4:7], 0 offen + v_add_i32 v226, v226, 64 + v_accvgpr_read_b32 v8, a88 + v_accvgpr_read_b32 v9, a89 + v_accvgpr_read_b32 v10, a90 + v_accvgpr_read_b32 v11, a91 + v_accvgpr_read_b32 v12, a120 + v_accvgpr_read_b32 v13, a121 + v_accvgpr_read_b32 v14, a122 + v_accvgpr_read_b32 v15, a123 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v226, s[4:7], 0 offen + v_add_i32 v226, v226, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a28 + v_accvgpr_read_b32 v9, a29 + v_accvgpr_read_b32 v10, a30 + v_accvgpr_read_b32 v11, a31 + v_accvgpr_read_b32 v12, a60 + v_accvgpr_read_b32 v13, a61 + v_accvgpr_read_b32 v14, a62 + v_accvgpr_read_b32 v15, a63 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v227, s[4:7], 0 offen + v_add_i32 v227, v227, 64 + v_accvgpr_read_b32 v8, a92 + v_accvgpr_read_b32 v9, a93 + v_accvgpr_read_b32 v10, a94 + v_accvgpr_read_b32 v11, a95 + v_accvgpr_read_b32 v12, a124 + v_accvgpr_read_b32 v13, a125 + v_accvgpr_read_b32 v14, a126 + v_accvgpr_read_b32 v15, a127 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v227, s[4:7], 0 offen + v_add_i32 v227, v227, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a128 + v_accvgpr_read_b32 v9, a129 + v_accvgpr_read_b32 v10, a130 + v_accvgpr_read_b32 v11, a131 + v_accvgpr_read_b32 v12, a160 + v_accvgpr_read_b32 v13, a161 + v_accvgpr_read_b32 v14, a162 + v_accvgpr_read_b32 v15, a163 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v228, s[4:7], 0 offen + v_add_i32 v228, v228, 64 + v_accvgpr_read_b32 v8, a192 + v_accvgpr_read_b32 v9, a193 + v_accvgpr_read_b32 v10, a194 + v_accvgpr_read_b32 v11, a195 + v_accvgpr_read_b32 v12, a224 + v_accvgpr_read_b32 v13, a225 + v_accvgpr_read_b32 v14, a226 + v_accvgpr_read_b32 v15, a227 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v228, s[4:7], 0 offen + v_add_i32 v228, v228, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a132 + v_accvgpr_read_b32 v9, a133 + v_accvgpr_read_b32 v10, a134 + v_accvgpr_read_b32 v11, a135 + v_accvgpr_read_b32 v12, a164 + v_accvgpr_read_b32 v13, a165 + v_accvgpr_read_b32 v14, a166 + v_accvgpr_read_b32 v15, a167 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v229, s[4:7], 0 offen + v_add_i32 v229, v229, 64 + v_accvgpr_read_b32 v8, a196 + v_accvgpr_read_b32 v9, a197 + v_accvgpr_read_b32 v10, a198 + v_accvgpr_read_b32 v11, a199 + v_accvgpr_read_b32 v12, a228 + v_accvgpr_read_b32 v13, a229 + v_accvgpr_read_b32 v14, a230 + v_accvgpr_read_b32 v15, a231 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v229, s[4:7], 0 offen + v_add_i32 v229, v229, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a136 + v_accvgpr_read_b32 v9, a137 + v_accvgpr_read_b32 v10, a138 + v_accvgpr_read_b32 v11, a139 + v_accvgpr_read_b32 v12, a168 + v_accvgpr_read_b32 v13, a169 + v_accvgpr_read_b32 v14, a170 + v_accvgpr_read_b32 v15, a171 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v230, s[4:7], 0 offen + v_add_i32 v230, v230, 64 + v_accvgpr_read_b32 v8, a200 + v_accvgpr_read_b32 v9, a201 + v_accvgpr_read_b32 v10, a202 + v_accvgpr_read_b32 v11, a203 + v_accvgpr_read_b32 v12, a232 + v_accvgpr_read_b32 v13, a233 + v_accvgpr_read_b32 v14, a234 + v_accvgpr_read_b32 v15, a235 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v230, s[4:7], 0 offen + v_add_i32 v230, v230, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a140 + v_accvgpr_read_b32 v9, a141 + v_accvgpr_read_b32 v10, a142 + v_accvgpr_read_b32 v11, a143 + v_accvgpr_read_b32 v12, a172 + v_accvgpr_read_b32 v13, a173 + v_accvgpr_read_b32 v14, a174 + v_accvgpr_read_b32 v15, a175 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v231, s[4:7], 0 offen + v_add_i32 v231, v231, 64 + v_accvgpr_read_b32 v8, a204 + v_accvgpr_read_b32 v9, a205 + v_accvgpr_read_b32 v10, a206 + v_accvgpr_read_b32 v11, a207 + v_accvgpr_read_b32 v12, a236 + v_accvgpr_read_b32 v13, a237 + v_accvgpr_read_b32 v14, a238 + v_accvgpr_read_b32 v15, a239 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v231, s[4:7], 0 offen + v_add_i32 v231, v231, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a144 + v_accvgpr_read_b32 v9, a145 + v_accvgpr_read_b32 v10, a146 + v_accvgpr_read_b32 v11, a147 + v_accvgpr_read_b32 v12, a176 + v_accvgpr_read_b32 v13, a177 + v_accvgpr_read_b32 v14, a178 + v_accvgpr_read_b32 v15, a179 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v232, s[4:7], 0 offen + v_add_i32 v232, v232, 64 + v_accvgpr_read_b32 v8, a208 + v_accvgpr_read_b32 v9, a209 + v_accvgpr_read_b32 v10, a210 + v_accvgpr_read_b32 v11, a211 + v_accvgpr_read_b32 v12, a240 + v_accvgpr_read_b32 v13, a241 + v_accvgpr_read_b32 v14, a242 + v_accvgpr_read_b32 v15, a243 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v232, s[4:7], 0 offen + v_add_i32 v232, v232, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a148 + v_accvgpr_read_b32 v9, a149 + v_accvgpr_read_b32 v10, a150 + v_accvgpr_read_b32 v11, a151 + v_accvgpr_read_b32 v12, a180 + v_accvgpr_read_b32 v13, a181 + v_accvgpr_read_b32 v14, a182 + v_accvgpr_read_b32 v15, a183 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v233, s[4:7], 0 offen + v_add_i32 v233, v233, 64 + v_accvgpr_read_b32 v8, a212 + v_accvgpr_read_b32 v9, a213 + v_accvgpr_read_b32 v10, a214 + v_accvgpr_read_b32 v11, a215 + v_accvgpr_read_b32 v12, a244 + v_accvgpr_read_b32 v13, a245 + v_accvgpr_read_b32 v14, a246 + v_accvgpr_read_b32 v15, a247 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v233, s[4:7], 0 offen + v_add_i32 v233, v233, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a152 + v_accvgpr_read_b32 v9, a153 + v_accvgpr_read_b32 v10, a154 + v_accvgpr_read_b32 v11, a155 + v_accvgpr_read_b32 v12, a184 + v_accvgpr_read_b32 v13, a185 + v_accvgpr_read_b32 v14, a186 + v_accvgpr_read_b32 v15, a187 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v234, s[4:7], 0 offen + v_add_i32 v234, v234, 64 + v_accvgpr_read_b32 v8, a216 + v_accvgpr_read_b32 v9, a217 + v_accvgpr_read_b32 v10, a218 + v_accvgpr_read_b32 v11, a219 + v_accvgpr_read_b32 v12, a248 + v_accvgpr_read_b32 v13, a249 + v_accvgpr_read_b32 v14, a250 + v_accvgpr_read_b32 v15, a251 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v234, s[4:7], 0 offen + v_add_i32 v234, v234, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + v_accvgpr_read_b32 v8, a156 + v_accvgpr_read_b32 v9, a157 + v_accvgpr_read_b32 v10, a158 + v_accvgpr_read_b32 v11, a159 + v_accvgpr_read_b32 v12, a188 + v_accvgpr_read_b32 v13, a189 + v_accvgpr_read_b32 v14, a190 + v_accvgpr_read_b32 v15, a191 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v235, s[4:7], 0 offen + v_add_i32 v235, v235, 64 + v_accvgpr_read_b32 v8, a220 + v_accvgpr_read_b32 v9, a221 + v_accvgpr_read_b32 v10, a222 + v_accvgpr_read_b32 v11, a223 + v_accvgpr_read_b32 v12, a252 + v_accvgpr_read_b32 v13, a253 + v_accvgpr_read_b32 v14, a254 + v_accvgpr_read_b32 v15, a255 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v235, s[4:7], 0 offen + v_add_i32 v235, v235, 64 + s_addk_i32 s49, 0x1 + s_cmp_lt_i32 s49, s50 + s_cbranch_scc0 label_0EFC + +label_0EFC: + s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) + s_endpgm + +// ===== Kernel Descriptor (generates .rodata) ===== +.rodata +.p2align 6 +.amdhsa_kernel _ZN5aiter24bf16gemm_bf16_tn_256x256E + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr + .amdhsa_group_segment_fixed_size 163840 + .amdhsa_accum_offset 256 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 1 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_vgpr_workitem_id 0 +.end_amdhsa_kernel + +// ===== AMDGPU Metadata ===== +.amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .actual_access: read_write + .address_space: global + .name: D + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 8 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: C + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 24 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: A + .offset: 32 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 40 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: B + .offset: 48 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 56 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .name: alpha + .offset: 64 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 68 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 72 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 76 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: beta + .offset: 80 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 84 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 88 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 92 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideD0 + .offset: 96 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 100 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 104 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 108 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideD1 + .offset: 112 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 116 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 120 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 124 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideC0 + .offset: 128 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 132 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 136 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 140 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideC1 + .offset: 144 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 148 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 152 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 156 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideA0 + .offset: 160 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 164 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 168 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 172 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideA1 + .offset: 176 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 180 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 184 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 188 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideB0 + .offset: 192 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 196 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 200 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 204 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideB1 + .offset: 208 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 212 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 216 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 220 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Mdim + .offset: 224 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 228 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 232 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 236 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Ndim + .offset: 240 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 244 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 248 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 252 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Kdim + .offset: 256 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 260 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 264 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 268 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: splitk + .offset: 272 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 276 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 280 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 284 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: is_out_b16 + .offset: 288 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 292 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 296 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 300 + .size: 4 + .value_kind: by_value + .value_type: i32 + .group_segment_fixed_size: 163840 + .kernarg_segment_align: 4 + .kernarg_segment_size: 304 + .max_flat_workgroup_size: 256 + .name: _ZN5aiter24bf16gemm_bf16_tn_256x256E + .private_segment_fixed_size: 0 + .reqd_workgroup_size: + - 256 + - 1 + - 1 + .sgpr_count: 112 + .symbol: _ZN5aiter24bf16gemm_bf16_tn_256x256E.kd + .vgpr_count: 512 + .wavefront_size: 64 +amdhsa.version: + - 1 + - 0 +... +.end_amdgpu_metadata + diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml new file mode 100644 index 000000000000..66d9e575261e --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -0,0 +1,175 @@ +TestParameters: + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + DeviceLDS: 163840 + MaxLDS: 163840 + # PrintTensorA: 1 + # PrintTensorB: 1 + # PrintTensorD: 2 + # PrintTensorRef: 2 + # NumWarmups: 20 # eqvlnt to cold-iter for hipblaslt + # EnqueuesPerSync: 1000 + # DataInitTypeA: 12 # TrigSin (problem dependant) + # DataInitTypeB: 13 # TrigCos (problem dependant) + # KeepBuildTmp: True + # ClientLogLevel: 3 # Debug level - includes rejection reasons + # KernelTime: True + # BoundsCheck: 2 + # RotatingBufferSize: 512 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: b + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + + - # BenchmarkProblemSizeGroup - Standard - All problem + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "_ZN5aiter24bf16gemm_bf16_tn_256x256E" + args: [ { type: address, semantic: AddressD }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: address, semantic: AddressC }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: address, semantic: AddressB }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: address, semantic: AddressA }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: float32, semantic: Alpha }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: float32, semantic: Beta }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideD0Bytes }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideD1 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideC0Bytes }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideC1 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideB0Bytes }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideB1 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideA0Bytes }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: StrideA1 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: SizeSum }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: SplitK }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: OutputBF16 }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern }, + { type: uint32, semantic: DebugPattern } ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + - MatrixInstruction: + - [16,16,32,1, 1, 8,8, 2,2] # 256 x 256 + - PreloadKernArgs: [False] + - DepthU: [64] + - VectorWidthA: [-1] + - VectorWidthB: [-1] + - GlobalReadVectorWidthA: [-1] + - GlobalReadVectorWidthB: [-1] + - LocalReadVectorWidth: [-1] + - TransposeLDS: [-1] + - LdsBlockSizePerPadA: [-1] + - LdsBlockSizePerPadB: [-1] + - LdsPadA: [-1] + - LdsPadB: [-1] + - StaggerU: [16] + - StaggerUStride: [-1] + - WorkGroupMapping: [1] + - StaggerUMapping: [0] + - 1LDSBuffer: [-1] + - WorkGroupMappingXCC: [8] + - WorkGroupMappingXCCGroup: [-1] + - GlobalSplitU: [1] + - GlobalSplitUAlgorithm: ["MultipleBuffer"] + - GlobalReadPerMfma: [1] + - LocalWritePerMfma: [-1] + - StoreRemapVectorWidth: [0] + - StoreVectorWidth: [-1] + - SourceSwap: [1] + - NumElementsPerBatchStore: [16] + - ClusterLocalRead: [1] + - NonTemporalA: [0] + - NonTemporalB: [0] + - DirectToVgprA: [1] + - DirectToVgprB: [0] + + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + - Exact: [4096, 4096, 1, 8192] + +LibraryLogic: + ScheduleName: "gfx950" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx950" + LibraryType: "GridBased" diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 2c30e8d58d10..80cd63bbb642 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -70,8 +70,14 @@ namespace TensileLite StrideD1, // 15 Alpha, // 16 Beta, // 17 - DebugPattern, // 18 - CustomArgSemantic_Count, // 19 + SplitK, // 18 + OutputBF16, // 19 + StrideA0Bytes, // 20 + StrideB0Bytes, // 21 + StrideC0Bytes, // 22 + StrideD0Bytes, // 23 + DebugPattern, // 24 + CustomArgSemantic_Count, // 25 }; std::string toString(CustomArgSemantic arg); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 1aa12b34194d..00c5f147661a 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -93,6 +93,18 @@ namespace TensileLite return "Alpha"; case CustomArgSemantic::Beta: return "Beta"; + case CustomArgSemantic::SplitK: + return "SplitK"; + case CustomArgSemantic::OutputBF16: + return "OutputBF16"; + case CustomArgSemantic::StrideA0Bytes: + return "StrideA0Bytes"; + case CustomArgSemantic::StrideB0Bytes: + return "StrideB0Bytes"; + case CustomArgSemantic::StrideC0Bytes: + return "StrideC0Bytes"; + case CustomArgSemantic::StrideD0Bytes: + return "StrideD0Bytes"; case CustomArgSemantic::DebugPattern: return "DebugPattern"; case CustomArgSemantic::CustomArgSemantic_Count: @@ -142,6 +154,18 @@ namespace TensileLite return CustomArgSemantic::Alpha; else if(str == toString(CustomArgSemantic::Beta)) return CustomArgSemantic::Beta; + else if(str == toString(CustomArgSemantic::SplitK)) + return CustomArgSemantic::SplitK; + else if(str == toString(CustomArgSemantic::OutputBF16)) + return CustomArgSemantic::OutputBF16; + else if(str == toString(CustomArgSemantic::StrideA0Bytes)) + return CustomArgSemantic::StrideA0Bytes; + else if(str == toString(CustomArgSemantic::StrideB0Bytes)) + return CustomArgSemantic::StrideB0Bytes; + else if(str == toString(CustomArgSemantic::StrideC0Bytes)) + return CustomArgSemantic::StrideC0Bytes; + else if(str == toString(CustomArgSemantic::StrideD0Bytes)) + return CustomArgSemantic::StrideD0Bytes; else if(str == toString(CustomArgSemantic::DebugPattern)) return CustomArgSemantic::DebugPattern; else @@ -1778,6 +1802,34 @@ namespace TensileLite case CustomArgSemantic::Beta: rv.args.appendCustomType("Beta", inputs.beta, arg.type); break; + case CustomArgSemantic::SplitK: + { + uint32_t splitK = (sizeMapping.globalSplitU > 0) ? sizeMapping.globalSplitU : 0; + rv.args.appendCustomType("SplitK", splitK, arg.type); + break; + } + case CustomArgSemantic::OutputBF16: + { + uint32_t isBF16 = (problem.d().dataType() == rocisa::DataType::BFloat16) ? 1 : 0; + rv.args.appendCustomType("OutputBF16", isBF16, arg.type); + break; + } + case CustomArgSemantic::StrideA0Bytes: + rv.args.appendCustomType("StrideA0Bytes", + problem.a().strides()[1] * problem.a().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideB0Bytes: + rv.args.appendCustomType("StrideB0Bytes", + problem.b().strides()[1] * problem.b().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideC0Bytes: + rv.args.appendCustomType("StrideC0Bytes", + problem.c().strides()[1] * problem.c().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideD0Bytes: + rv.args.appendCustomType("StrideD0Bytes", + problem.d().strides()[1] * problem.d().elementBytes(), arg.type); + break; case CustomArgSemantic::DebugPattern: rv.args.template append("DebugPattern", debugPattern); ++debugPattern; From 55604b74823ea8e4e56a992b237b6069ad481fba Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 11 Mar 2026 09:52:02 -0700 Subject: [PATCH 17/58] [hipblaslt] Allow subdirectories in CustomKernels folder (#5331) Update build scripts to allow subdirectories in CustomKernels folder to help organize files. --- .../tensilelite/Tensile/CustomKernels.py | 15 +++++++++++++-- .../_ZN5aiter24bf16gemm_bf16_tn_256x256E.s | 0 ...c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s | 0 ...leTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s | 0 .../tensilelite/Tensile/KernelWriterAssembly.py | 4 ++-- 5 files changed, 15 insertions(+), 4 deletions(-) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => aiter}/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => ck}/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => rocroller}/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s (100%) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 8e02cde22a35..f87131b0203c 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -33,10 +33,21 @@ def isCustomKernelConfig(config): return "CustomKernel" in config and config["CustomKernel"]["name"] def getCustomKernelFilepath(name, directory=CUSTOM_KERNEL_PATH): - return os.path.join(directory, (name + ".s")) + flat = os.path.join(directory, (name + ".s")) + if os.path.isfile(flat): + return flat + for root, _, files in os.walk(directory): + if (name + ".s") in files: + return os.path.join(root, (name + ".s")) + return flat def getAllCustomKernelNames(directory=CUSTOM_KERNEL_PATH): - return [fname[:-2] for fname in os.listdir(directory) if fname.endswith(".s")] + names = [] + for root, _, files in os.walk(directory): + for fname in files: + if fname.endswith(".s"): + names.append(fname[:-2]) + return names def getCustomKernelContents(name, directory=CUSTOM_KERNEL_PATH): try: diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py index c9b0368369d8..acb1229a7c85 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py @@ -74,7 +74,7 @@ from .SolutionStructs import isPackedIndex from .AsmStoreState import StoreState, VectorDataTypes from .Activation import ActivationType -from .CustomKernels import isCustomKernelConfig +from .CustomKernels import isCustomKernelConfig, getCustomKernelFilepath from .Common import roundUp, log2, ceilDivide, choose_multiplier from Tensile.Common import print2, printExit, printWarning, INDEX_CHARS, DebugConfig, DataDirection from Tensile.Common.DataType import DataType @@ -135,7 +135,7 @@ def __init__( def _getCustomKernelSource(self, kernel, CustomKernelDirectory): kernelName = getKernelFileBase(self.debugConfig.splitGSU, kernel) - with open(os.path.join(CustomKernelDirectory, (kernelName + ".s"))) as f: + with open(getCustomKernelFilepath(kernelName, CustomKernelDirectory)) as f: rocmVersion = self.assembler.rocm_version if not (rocmVersion.major >= 6 and rocmVersion.patch >= 32650): code = [] From 2b50d0294c20264a5f30d4987c29ce45dc260aeb Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Wed, 11 Mar 2026 10:52:45 -0600 Subject: [PATCH 18/58] CustomKernels don't need tuning arguments (#5320) Update the way CustomKernel info gets stored in a solution to improve default build, and avoid having to come up with equivalent tuning arguments to describe external kernels. --- .../Tensile/Common/GlobalParameters.py | 2 +- .../tensilelite/Tensile/Contractions.py | 40 +++++------- .../Tensile/SolutionStructs/Solution.py | 65 ++++++++++++++++--- .../Tensile/Tests/custom/custom_ck.yaml | 38 ----------- .../include/Tensile/ContractionSolution.hpp | 3 +- .../Serialization/ContractionSolution.hpp | 3 +- .../tensilelite/src/ContractionSolution.cpp | 32 ++++----- 7 files changed, 93 insertions(+), 90 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py index e193750f65ae..2f4329b4d6bc 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py @@ -425,7 +425,7 @@ {"NonTemporalMetadata": [0]}, {"NonTemporal": [-1]}, {"PreloadKernArgs": [True]}, - {"CustomKernel": [{"name": "", "args": [], "macrotile": [0,0,0], "threads": [0,0,0], "grid": [0,0,0]}]}, + # {"CustomKernel": [{"name": "", "args": [], "macrotile": [0,0,0], "threads": [0,0,0], "grid": [0,0,0]}]}, {"NoReject": [False]}, {"StoreRemapVectorWidth": [0]}, {"SourceSwap": [False]}, diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index 70957d98cb3d..313d8e412cd6 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -589,11 +589,6 @@ def FromOriginalState(cls, d): return cls(name=d['name'], args=d['args'], macrotile=d['macrotile'], threads=d['threads'], grid=d['grid']) def __init__(self, **kwargs): - self.name = "" - self.args = [] - self.macrotile = [0,0,0] - self.threads = [0,0,0] - self.grid = [0,0,0] for (key, value) in list(kwargs.items()): setattr(self, key, value) @@ -623,7 +618,6 @@ class SizeMapping: 'workspaceSizePerElemC', 'workspaceSizePerElemBias', 'activationFused', - 'customKernel', 'workGroupMappingXCC', 'workGroupMappingXCCGroup', 'globalSplitUCoalesced', @@ -686,11 +680,6 @@ def convertSFCWGMListToHex(value): dtlA = bool(d['DirectToLdsA']) dtlB = bool(d['DirectToLdsB']) - if 'CustomKernel' in d: - customKernel = CustomKernel.FromOriginalState(d['CustomKernel']) - else: - customKernel = CustomKernel(name="", args=[], macrotile=[0,0,0], threads=[0,0,0], grid=[0,0,0]) - return cls(waveNum = d['NumThreads'] // d['WavefrontSize'], workGroup = d['WorkGroup'], macroTile = cls.ReadOriginalMacroTile(d), @@ -716,7 +705,6 @@ def convertSFCWGMListToHex(value): workspaceSizePerElemC = d['_WorkspaceSizePerElemC'], workspaceSizePerElemBias = d['_WorkspaceSizePerElemBias'], activationFused = d['ActivationFused'], - customKernel = customKernel, workGroupMappingXCC = d['WorkGroupMappingXCC'], workGroupMappingXCCGroup = d['WorkGroupMappingXCCGroup'], globalSplitUCoalesced = d['GlobalSplitUCoalesced'], @@ -782,17 +770,18 @@ def __init__(self, **kwargs): class Solution: StateKeys = ['name', 'kernelName', - 'problemType', - 'hardwarePredicate', - 'problemPredicate', - 'taskPredicate', - 'sizeMapping', - 'internalArgsSupport', - 'debugKernel', - 'libraryLogicIndex', - 'index', - 'ideals', - 'linearModel'] + 'problemType', + 'hardwarePredicate', + 'problemPredicate', + 'taskPredicate', + 'sizeMapping', + 'customKernel', + 'internalArgsSupport', + 'debugKernel', + 'libraryLogicIndex', + 'index', + 'ideals', + 'linearModel'] HiddenKeys = ['originalSolution'] @classmethod @@ -851,6 +840,10 @@ def FromOriginalState( rv.libraryLogicIndex = int(info.get("SolutionIndex", -1)) rv.sizeMapping = SizeMapping.FromOriginalState(d) + if 'CustomKernel' in d: + rv.customKernel = CustomKernel.FromOriginalState(d['CustomKernel']) + else: + rv.customKernel = {} rv.internalArgsSupport = InternalArgsSupport.FromOriginalState(d) @@ -896,6 +889,7 @@ def __init__(self, **kwargs): self.problemPredicate = ProblemPredicate('TruePred') self.taskPredicate = TaskPredicate('TruePred') self.sizeMapping = None + self.customKernel = None self.debugKernel = False self.libraryLogicIndex = {} self.index = None diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 42081c964e45..e59b727df1b1 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -359,14 +359,17 @@ def __init__( self["AssignedProblemIndependentDerivedParameters"] = False if "AssignedDerivedParameters" not in self._state: self["AssignedDerivedParameters"] = False - Solution.assignDerivedParameters( - self._state, - splitGSU, - printSolutionRejectionReason, - printIndexAssignmentInfo, - isaInfoMap, - assembler.rocm_version - ) + if "CustomKernel" not in self._state: + Solution.assignDerivedParameters( + self._state, + splitGSU, + printSolutionRejectionReason, + printIndexAssignmentInfo, + isaInfoMap, + assembler.rocm_version + ) + else: + Solution.assignCustomKernelParameters(self._state) self._name = config["CustomKernel"]["name"] if "CustomKernel" in config and config["CustomKernel"]["name"] else None # these keys are copied from ProblemType to internal that may be overridden @@ -1079,6 +1082,52 @@ def getDivisorName(state, tC): divisorName = "LVP{}".format(tC) return divisorName + @staticmethod + def assignCustomKernelParameters(state): + # Store values in state so they can be saved in SizeMapping + # Not all SizeMapping values will be needed (or applicable) for custom kernels + + state["MacroTile0"] = state["CustomKernel"]["macrotile"][0] + state["MacroTile1"] = state["CustomKernel"]["macrotile"][1] + state["DepthU"] = state["CustomKernel"]["macrotile"][2] + + # TODO Temp values to allow serializing SizeMapping + state["_GlobalAccumulation"] = None + state["CUOccupancy"] = -1 + state["MathClocksUnrolledLoop"] = 0 + state["PackedC0IndicesX"] = [] + state["ThreadTile0"] = 0 + state["ThreadTile1"] = 0 + state["NumThreads"] = state["CustomKernel"]["threads"][0] * state["CustomKernel"]["threads"][1] * state["CustomKernel"]["threads"][2] + + # TODO LSU + # numElementsPerWorkGroup = state["MacroTile0"]*state["MacroTile1"]*state["NumWaveSplitK"] + numElementsPerWorkGroup = state["MacroTile0"] * state["MacroTile1"] + state["NumElementsPerThread"] = numElementsPerWorkGroup // state["NumThreads"] + + # TODO Check what DTL affects in SizeMapping + state["DirectToLdsA"] = state["DirectToLds"] == 1 or state["DirectToLds"] == 2 + state["DirectToLdsB"] = state["DirectToLds"] == 1 or state["DirectToLds"] == 3 + + # TODO Override workspace info for custom kernel + computeBytes = state["ProblemType"]["ComputeDataType"].numBytes() + state["_WorkspaceSizePerElemC"] = computeBytes + state["_WorkspaceSizePerElemBias"] = 0 + if state["ProblemType"]["UseBias"] and state["ProblemType"]["Gradient"]: + state["_WorkspaceSizePerElemBias"] = computeBytes + # state["WorkspaceCheck"] = [state["_WorkspaceSizePerElemC"], state["_WorkspaceSizePerElemBias"], state["GlobalSplitU"] if (state["GlobalSplitUAlgorithm"] == 'MultipleBuffer' or state["_GlobalAccumulation"] == 'MultipleBufferSingleKernel') else 1] + + # state["MIWaveGroup"] = [state["SubGroup0"] // state["WavefrontSize"], state["SubGroup1"]] + state["MIWaveGroup"] = [0, 0] + + # state["LocalSplitU"] = state["WorkGroup"][2] + state["LocalSplitU"] = 1 + + state["GlobalReadVectorWidthA"] = 1 + state["GlobalReadVectorWidthB"] = 1 + state["StoreVectorWidth"] = 1 + + ######################################## # assign all derived parameters @staticmethod diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 0d47def6c172..7316fb8d455c 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -66,44 +66,6 @@ BenchmarkProblems: macrotile: [256, 256, 64] threads: [256, 1, 1] grid: [TilesXYBatch, One, One] - - MatrixInstruction: - - [16,16,16, 1, 1, 8,8, 2,2] # 256 x 128 - - PreloadKernArgs: [False] - # - PrefetchGlobalRead: [2] - # - PrefetchLocalRead: [1] - - DepthU: [64] - - VectorWidthA: [-1] - - VectorWidthB: [-1] - - GlobalReadVectorWidthA: [-1] - - GlobalReadVectorWidthB: [-1] - - LocalReadVectorWidth: [-1] - - TransposeLDS: [-1] - - LdsBlockSizePerPadA: [-1] - - LdsBlockSizePerPadB: [-1] - - LdsPadA: [-1] - - LdsPadB: [-1] - - StaggerU: [16] - - StaggerUStride: [-1] - - WorkGroupMapping: [1] - - StaggerUMapping: [0] - - 1LDSBuffer: [-1] - - WorkGroupMappingXCC: [8] - - WorkGroupMappingXCCGroup: [-1] - - GlobalSplitU: [1] - - GlobalSplitUAlgorithm: ["MultipleBuffer"] - - GlobalReadPerMfma: [1] - - LocalWritePerMfma: [-1] - - StoreRemapVectorWidth: [0] - - StoreVectorWidth: [-1] - - SourceSwap: [1] - - NumElementsPerBatchStore: [16] - - ClusterLocalRead: [1] - - NonTemporalA: [0] - - NonTemporalB: [0] - - DirectToVgprA: [1] - - DirectToVgprB: [0] - # - WorkGroup: [[32,4,4]] - BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 80cd63bbb642..033b97628b07 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -222,8 +222,6 @@ namespace TensileLite bool activationFused = true; - CustomKernel customKernel; - int workGroupMappingXCC = 0; int workGroupMappingXCCGroup = 0; bool globalSplitUCoalesced = false; @@ -683,6 +681,7 @@ namespace TensileLite = std::make_shared>(); SizeMapping sizeMapping; + CustomKernel customKernel; InternalArgsSupport internalArgsSupport; diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 028babf55900..6d349a446799 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -66,6 +66,7 @@ namespace TensileLite iot::mapOptional(io, "linearModel", s.linearModel); iot::mapRequired(io, "sizeMapping", s.sizeMapping); + iot::mapOptional(io, "customKernel", s.customKernel); iot::mapRequired(io, "internalArgsSupport", s.internalArgsSupport); iot::mapRequired(io, "problemType", s.problemType); } @@ -141,8 +142,6 @@ namespace TensileLite iot::mapOptional(io, "activationFused", s.activationFused); - iot::mapOptional(io, "customKernel", s.customKernel); - iot::mapRequired(io, "workGroupMappingXCC", s.workGroupMappingXCC); iot::mapRequired(io, "workGroupMappingXCCGroup", s.workGroupMappingXCCGroup); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 00c5f147661a..7a55065f0ebf 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1596,8 +1596,8 @@ namespace TensileLite if(problem.transposeC01()) std::swap(tiles.x, tiles.y); - tiles.x = CeilDivide(tiles.x, sizeMapping.customKernel.macrotile.x); - tiles.y = CeilDivide(tiles.y, sizeMapping.customKernel.macrotile.y); + tiles.x = CeilDivide(tiles.x, customKernel.macrotile.x); + tiles.y = CeilDivide(tiles.y, customKernel.macrotile.y); } void ContractionSolution::calculateGrid(dim3& workGroupSize, @@ -1655,19 +1655,19 @@ namespace TensileLite assert(pAMDGPU); int wavefrontSize = pAMDGPU->wavefrontSize; - // rv.workGroupSize.x = sizeMapping.customKernel.waves.x * wavefrontSize; - // rv.workGroupSize.y = sizeMapping.customKernel.waves.y * wavefrontSize; - // rv.workGroupSize.z = sizeMapping.customKernel.waves.z * wavefrontSize; - rv.workGroupSize.x = sizeMapping.customKernel.threads.x; - rv.workGroupSize.y = sizeMapping.customKernel.threads.y; - rv.workGroupSize.z = sizeMapping.customKernel.threads.z; + // rv.workGroupSize.x = customKernel.waves.x * wavefrontSize; + // rv.workGroupSize.y = customKernel.waves.y * wavefrontSize; + // rv.workGroupSize.z = customKernel.waves.z * wavefrontSize; + rv.workGroupSize.x = customKernel.threads.x; + rv.workGroupSize.y = customKernel.threads.y; + rv.workGroupSize.z = customKernel.threads.z; if(T_Debug) { std::cout << "Wavefront size: " << wavefrontSize << std::endl; - std::cout << "Threads: " << sizeMapping.customKernel.threads.x << ", " << sizeMapping.customKernel.threads.y << ", " << sizeMapping.customKernel.threads.z << std::endl; + std::cout << "Threads: " << customKernel.threads.x << ", " << customKernel.threads.y << ", " << customKernel.threads.z << std::endl; std::cout << "Work group size: " << rv.workGroupSize.x << ", " << rv.workGroupSize.y << ", " << rv.workGroupSize.z << std::endl; - std::cout << "Macrotile: " << sizeMapping.customKernel.macrotile.x << ", " << sizeMapping.customKernel.macrotile.y << ", " << sizeMapping.customKernel.macrotile.z << std::endl; + std::cout << "Macrotile: " << customKernel.macrotile.x << ", " << customKernel.macrotile.y << ", " << customKernel.macrotile.z << std::endl; } dim3 tiles; @@ -1711,9 +1711,9 @@ namespace TensileLite } }; - assignGridSize(rv.numWorkGroups.x, sizeMapping.customKernel.grid.x); - assignGridSize(rv.numWorkGroups.y, sizeMapping.customKernel.grid.y); - assignGridSize(rv.numWorkGroups.z, sizeMapping.customKernel.grid.z); + assignGridSize(rv.numWorkGroups.x, customKernel.grid.x); + assignGridSize(rv.numWorkGroups.y, customKernel.grid.y); + assignGridSize(rv.numWorkGroups.z, customKernel.grid.z); if(T_Debug) { @@ -1741,7 +1741,7 @@ namespace TensileLite if(T_Debug) std::cout << "Custom call arguments:" << std::endl; - for(auto arg : sizeMapping.customKernel.args) + for(auto arg : customKernel.args) { if(T_Debug) std::cout << "Type: " << toString(arg.type) << " Semantic: " << toString(arg.semantic) << std::endl; @@ -3220,7 +3220,7 @@ namespace TensileLite } } - if(sizeMapping.customKernel.name.empty()) + if(customKernel.name.empty()) { // Regular generated kernel if(debug) @@ -3757,7 +3757,7 @@ namespace TensileLite AMDGPU const* pAMDGPU = dynamic_cast(&hardware); assert(pAMDGPU != nullptr && pAMDGPU->computeUnitCount != 0); - if(!sizeMapping.customKernel.name.empty()) + if(!customKernel.name.empty()) { // Custom kernel currently only supports single-kernel reduction reductionStrat = origami::reduction_t::tree; From 072126ed0f4e88ef0ba5de509a02a88cff1305de Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 18 Mar 2026 13:39:13 -0700 Subject: [PATCH 19/58] [hipblaslt] Add custom argument semantic for padding (#5322) - Add padding argument semantic e.g. { type: uint32, semantic: Padding} - Add padding param to the arg e.g. { type: address, semantic: AddressD, padding: 8 } AIGECORE-1985 --- .../Tests/custom/custom_aiter_bf16.yaml | 92 ++++--------------- .../Tensile/Tests/custom/custom_ck.yaml | 12 +-- .../include/Tensile/ContractionSolution.hpp | 6 +- .../include/Tensile/KernelArguments.hpp | 7 ++ .../Serialization/ContractionSolution.hpp | 1 + .../tensilelite/src/ContractionSolution.cpp | 15 ++- 6 files changed, 51 insertions(+), 82 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index 66d9e575261e..1c8a238cea84 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -53,78 +53,25 @@ BenchmarkProblems: ForkParameters: - CustomKernel: - name: "_ZN5aiter24bf16gemm_bf16_tn_256x256E" - args: [ { type: address, semantic: AddressD }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: address, semantic: AddressC }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: address, semantic: AddressB }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: address, semantic: AddressA }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: float32, semantic: Alpha }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: float32, semantic: Beta }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideD0Bytes }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideD1 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideC0Bytes }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideC1 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideB0Bytes }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideB1 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideA0Bytes }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: StrideA1 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: SizeFree1 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: SizeFree0 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: SizeSum }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: SplitK }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: OutputBF16 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern } ] + args: [ { type: address, semantic: AddressD, padding: 8 }, + { type: address, semantic: AddressC, padding: 8 }, + { type: address, semantic: AddressB, padding: 8 }, + { type: address, semantic: AddressA, padding: 8 }, + { type: float32, semantic: Alpha, padding: 12 }, + { type: float32, semantic: Beta, padding: 12 }, + { type: uint32, semantic: StrideD0Bytes, padding: 12 }, + { type: uint32, semantic: StrideD1, padding: 12 }, + { type: uint32, semantic: StrideC0Bytes, padding: 12 }, + { type: uint32, semantic: StrideC1, padding: 12 }, + { type: uint32, semantic: StrideB0Bytes, padding: 12 }, + { type: uint32, semantic: StrideB1, padding: 12 }, + { type: uint32, semantic: StrideA0Bytes, padding: 12 }, + { type: uint32, semantic: StrideA1, padding: 12 }, + { type: uint32, semantic: SizeFree1, padding: 12 }, + { type: uint32, semantic: SizeFree0, padding: 12 }, + { type: uint32, semantic: SizeSum, padding: 12 }, + { type: uint32, semantic: SplitK, padding: 12 }, + { type: uint32, semantic: OutputBF16, padding: 12 } ] macrotile: [256, 256, 64] threads: [256, 1, 1] grid: [TilesX, TilesY, One] @@ -162,7 +109,6 @@ BenchmarkProblems: - NonTemporalB: [0] - DirectToVgprA: [1] - DirectToVgprB: [0] - BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 7316fb8d455c..506ca656db5b 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -56,12 +56,12 @@ BenchmarkProblems: { type: uint32, semantic: StrideD0 }, { type: uint32, semantic: StrideD0 }, { type: uint32, semantic: SizeFree2 }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern }, - { type: uint32, semantic: DebugPattern } ] + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding } ] # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] macrotile: [256, 256, 64] threads: [256, 1, 1] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 033b97628b07..6ca3b1841d44 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -76,8 +76,9 @@ namespace TensileLite StrideB0Bytes, // 21 StrideC0Bytes, // 22 StrideD0Bytes, // 23 - DebugPattern, // 24 - CustomArgSemantic_Count, // 25 + Padding, // 24 + DebugPattern, // 25 + CustomArgSemantic_Count, // 26 }; std::string toString(CustomArgSemantic arg); @@ -89,6 +90,7 @@ namespace TensileLite { CustomArgType type; CustomArgSemantic semantic; + size_t padding = 0; }; std::string toString(CustomArgDefinition arg); diff --git a/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp b/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp index 2c74facfb487..5ad8602ba74b 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/KernelArguments.hpp @@ -149,6 +149,8 @@ namespace TensileLite template void appendAligned(std::string const& name, T value); + void appendPadding(size_t bytes); + template void appendUnbound(std::string const& name); @@ -460,6 +462,11 @@ namespace TensileLite append(name, value, true); } + inline void KernelArguments::appendPadding(size_t bytes) + { + m_data.insert(m_data.end(), bytes, 0); + } + template inline void KernelArguments::append(std::string const& name, T value, bool bound) { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 6d349a446799..4b3936a67c2d 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -98,6 +98,7 @@ namespace TensileLite { iot::mapRequired(io, "type", s.type); iot::mapRequired(io, "semantic", s.semantic); + iot::mapOptional(io, "padding", s.padding); } const static bool flow = true; }; diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 7a55065f0ebf..063236d79ee3 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -105,6 +105,8 @@ namespace TensileLite return "StrideC0Bytes"; case CustomArgSemantic::StrideD0Bytes: return "StrideD0Bytes"; + case CustomArgSemantic::Padding: + return "Padding"; case CustomArgSemantic::DebugPattern: return "DebugPattern"; case CustomArgSemantic::CustomArgSemantic_Count: @@ -166,6 +168,8 @@ namespace TensileLite return CustomArgSemantic::StrideC0Bytes; else if(str == toString(CustomArgSemantic::StrideD0Bytes)) return CustomArgSemantic::StrideD0Bytes; + else if(str == toString(CustomArgSemantic::Padding)) + return CustomArgSemantic::Padding; else if(str == toString(CustomArgSemantic::DebugPattern)) return CustomArgSemantic::DebugPattern; else @@ -188,7 +192,10 @@ namespace TensileLite std::string toString(CustomArgDefinition arg) { - return toString(arg.type) + " " + toString(arg.semantic); + auto s = toString(arg.type) + " " + toString(arg.semantic); + if(arg.padding > 0) + s += " padding:" + std::to_string(arg.padding); + return s; } std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t) @@ -1830,6 +1837,9 @@ namespace TensileLite rv.args.appendCustomType("StrideD0Bytes", problem.d().strides()[1] * problem.d().elementBytes(), arg.type); break; + case CustomArgSemantic::Padding: + rv.args.template append("Padding", 0); + break; case CustomArgSemantic::DebugPattern: rv.args.template append("DebugPattern", debugPattern); ++debugPattern; @@ -1837,6 +1847,9 @@ namespace TensileLite default: throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); } + + if(arg.padding > 0) + rv.args.appendPadding(arg.padding); } return rv; } From aeff1c45ef783956825992192a15ee5942dcc4d4 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 25 Mar 2026 12:54:31 -0500 Subject: [PATCH 20/58] Move tensile generated custom kernels --- ...BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s | 0 ...BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s | 0 ..._BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s | 0 ...k_Bljk_F8NH_HHS_BH_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s | 0 ...k_Bljk_F8NH_HHS_BH_MT128x16x128_MI16x16x1_16_Equality_gfx942.s | 0 ...lk_Bljk_F8NH_HHS_BH_MT128x16x64_MI16x16x1_30_Freesize_gfx942.s | 0 ...lk_Bljk_F8NH_HHS_BH_MT64x16x128_MI16x16x1_15_Equality_gfx942.s | 0 ...S_BH_Bias_AS_SAV_MT64x16x64_MI16x16x1_Freesize_2stage_gfx942.s | 0 ...AS_SAV_MT64x16x64_MI16x16x1_Freesize_2stage_iprefetch_gfx942.s | 0 ...AV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s | 0 ...8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_shortname2.s | 0 ...Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_shortname0_gfx942.s | 0 ...Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_shortname1_gfx942.s | 0 ...jk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname0_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname10_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname11_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname12_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname13_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname14_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname15_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname16_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname17_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname18_gfx942.s | 0 ...k_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname19_gfx942.s | 0 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...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname13_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname14_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname15_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname16_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname17_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname18_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname19_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname1_gfx942.s | 0 ...k_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname20_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname2_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname3_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname4_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname5_gfx942.s | 0 ...jk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname6_gfx942.s | 0 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...s_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s | 0 ...V_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s | 0 ...s_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s | 0 ...V_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s | 0 ...lik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s | 0 ...k_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s | 0 ..._Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s | 0 ...ljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s | 0 ..._Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s | 0 ...ljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s | 0 ...ljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s | 0 ...ljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s | 0 ..._Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s | 0 ..._Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s | 0 ...stom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s | 0 ...om_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s | 0 ...om_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s | 0 ...Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s | 0 ...ABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s | 0 ..._UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s | 0 ...ABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s | 0 ..._UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s | 0 ...ljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s | 0 ..._UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s | 0 ...AV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s | 0 119 files changed, 0 insertions(+), 0 deletions(-) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_MT128x16x128_MI16x16x1_16_Equality_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_MT128x16x64_MI16x16x1_30_Freesize_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_MT64x16x128_MI16x16x1_15_Equality_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_HSS_BH_Bias_AS_SAV_MT64x16x64_MI16x16x1_Freesize_2stage_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/CustomGSUs_Cijk_Ailk_Bljk_HSS_BH_Bias_AS_SAV_MT64x16x64_MI16x16x1_Freesize_2stage_iprefetch_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bjlk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_shortname2.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_shortname0_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_shortname1_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname0_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname10_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname11_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname12_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname13_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname14_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname15_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname16_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname17_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname18_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname19_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname1_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname20_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname2_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname3_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname4_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname5_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname6_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname7_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname8_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname9_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname0_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname10_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname11_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname12_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname13_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname14_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname15_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname16_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname17_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname18_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname19_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname1_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname20_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname2_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname3_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname4_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname5_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname6_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname7_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname8_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_F8NH_HSS_BH_Bias_GG_AS_SAB_SAV_UserArgs_shortname9_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname0_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname10_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname11_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname12_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname13_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname14_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname15_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname16_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname17_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname18_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname1_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname2_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname3_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname4_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname5_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname6_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname7_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname8_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HHS_BH_Bias_GG_AS_SAV_UserArgs_shortname9_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname0_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname10_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname11_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname12_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname13_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname14_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname15_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname16_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname17_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname18_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname1_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname2_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname3_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname4_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname5_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname6_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname7_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname8_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_HSS_BH_Bias_GG_AS_SAV_UserArgs_shortname9_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Ailk_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_HHS_BH_UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s (100%) rename projects/hipblaslt/tensilelite/Tensile/CustomKernels/{ => tensile}/Custom_Cijk_Alik_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s (100%) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_10_Freesize_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_44_Freesize_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/CustomGSUs_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x64_MI16x16x1_29_Freesize_gfx942.s diff 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diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Ailk_Bjlk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Ailk_Bjlk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Ailk_Bjlk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Ailk_Bjlk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_shortname2.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Ailk_Bljk_F8NH_HHS_BH_Bias_AS_SAB_SAV_MT128x16x128_MI16x16x1_shortname2.s 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--git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x224x64_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_Bias_AS_SAV_UserArgs_MT256x256x64_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT128x16x128_MI16x16x1_SN_GSUM_K1_MIWT2_1_01_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_2_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT16x16x128_MI16x16x1_SN_GSUM_K1_MIWT1_1_3_gfx942.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_BBS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname1_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8B8BS_BH_SAB_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_NTD_UserArgs_shortname1_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8BS_BH_SAB_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x224x128_MI16x16x1_SN_K1_MIWT4_14_WSGRB2_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_F8NBS_BH_BiasSB_AS_SABV_SAV_UserArgs_MT256x256x128_MI16x16x1_SN_K1_MIWT4_16_WSGRB2_DTVA.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_HHS_BH_MT256x256x64_MI16x16x1_UserArgs_shortname0_gfx950.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_HHS_BH_UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_HHS_BH_UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_HHS_BH_UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_HHS_BH_UserArgs_MT128x16x128_MI16x16x1_SN_K1_MIWT2_1_triple_buffer.s diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s similarity index 100% rename from projects/hipblaslt/tensilelite/Tensile/CustomKernels/Custom_Cijk_Alik_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s rename to projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/Custom_Cijk_Alik_Bljk_S_MX_B_BIAS_HA_S_SAV_NTD_SK3_UserArgs_MT256x256x32_MI16x16x1_shortname0_gfx950.s From a276415e2fd18fe4a410ee2c1df162235fdb4cae Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 1 Apr 2026 12:44:27 -0700 Subject: [PATCH 21/58] [hipblaslt] Demo calling wave bf16 kernel (#5756) Wave kernel is compiled from https://github.com/iree-org/wave Tensile log: https://gist.github.com/jinchen62/589e0b44525ccdf0662959169c349d6c --- .../wave/wave_bf16_gemm_256x256x64.s | 1993 +++++++++++++++++ .../Tests/custom/custom_wave_bf16.yaml | 98 + 2 files changed, 2091 insertions(+) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s new file mode 100644 index 000000000000..1fb2f5326555 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s @@ -0,0 +1,1993 @@ +; To reproduce the .rocmasm from .optimized.ll, run: +; llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -mattr='-fma-mix-insts' -O3 <.optimized.ll> -o + + .amdgcn_target "amdgcn-amd-amdhsa--gfx950" + .amdhsa_code_object_version 5 + .text + .globl wave_bf16_gemm_256x256x64 + .p2align 8 + .type wave_bf16_gemm_256x256x64,@function +wave_bf16_gemm_256x256x64: + s_load_dwordx2 s[2:3], s[0:1], 0x0 + s_load_dwordx8 s[4:11], s[0:1], 0x8 + s_load_dwordx2 s[12:13], s[0:1], 0x28 + s_waitcnt lgkmcnt(0) + s_branch .LBB0_0 + .p2align 8 +.LBB0_0: + s_mov_b32 s0, s15 + s_mov_b32 s15, 0 + s_mov_b32 s1, s15 + v_and_b32_e32 v90, 0x3ff, v0 + v_bfe_u32 v0, v0, 10, 10 + s_lshl_b64 s[36:37], s[14:15], 8 + s_lshl_b64 s[38:39], s[0:1], 8 + v_lshlrev_b32_e32 v1, 6, v0 + s_cmp_eq_u64 s[12:13], 0 + v_and_or_b32 v71, v90, 15, v1 + v_bfe_u32 v70, v90, 4, 2 + v_mov_b32_e32 v2, 0 + s_cbranch_scc1 .LBB0_68 + s_add_u32 s40, s12, -7 + s_addc_u32 s41, s13, -1 + s_add_u32 s42, s12, -6 + s_addc_u32 s43, s13, -1 + s_add_u32 s44, s12, -5 + s_addc_u32 s45, s13, -1 + s_add_u32 s46, s12, -4 + v_lshrrev_b32_e32 v3, 3, v90 + s_addc_u32 s47, s13, -1 + v_lshl_or_b32 v0, v0, 5, v3 + s_add_u32 s48, s12, -3 + v_or_b32_e32 v4, s36, v0 + v_mov_b32_e32 v5, s37 + s_addc_u32 s49, s13, -1 + v_cmp_gt_u64_e32 vcc, s[8:9], v[4:5] + v_lshlrev_b32_e32 v5, 3, v90 + v_lshlrev_b32_e32 v3, 6, v3 + s_add_u32 s50, s12, -2 + v_sub_u32_e32 v74, v5, v3 + v_or_b32_e32 v4, 0x80, v4 + v_mov_b32_e32 v5, s37 + s_addc_u32 s51, s13, -1 + v_cmp_gt_u64_e64 s[0:1], s[8:9], v[4:5] + v_or_b32_e32 v4, s38, v0 + v_mov_b32_e32 v5, s39 + s_add_u32 s52, s12, -1 + v_cmp_gt_u64_e64 s[30:31], s[10:11], v[4:5] + v_or_b32_e32 v4, 0x80, v4 + s_addc_u32 s53, s13, -1 + v_cmp_gt_u64_e64 s[34:35], s[10:11], v[4:5] + v_mul_u32_u24_e32 v5, 0x44, v0 + s_add_u32 s16, 0, s12 + v_or_b32_e32 v3, 48, v90 + v_and_b32_e32 v4, 0xcf, v90 + v_add_lshl_u32 v91, v5, v74, 1 + v_lshlrev_b32_e32 v5, 4, v70 + s_movk_i32 s14, 0x88 + s_addc_u32 s17, s13, 0 + v_mad_u32_u24 v92, v71, s14, v5 + v_mad_u32_u24 v93, v4, s14, v5 + v_mad_u32_u24 v94, v3, s14, v5 + s_add_u32 s14, s16, -1 + v_mov_b32_e32 v1, v2 + s_addc_u32 s15, s17, -1 + s_lshr_b64 s[14:15], s[14:15], 6 + v_lshl_add_u64 v[4:5], s[38:39], 0, v[0:1] + s_mov_b64 s[56:57], 0x80 + s_add_u32 s54, s14, 1 + v_lshl_add_u64 v[6:7], v[4:5], 0, s[56:57] + s_addc_u32 s55, s15, 0 + v_mul_lo_u32 v3, v7, s16 + v_mul_lo_u32 v8, v6, s17 + v_mad_u64_u32 v[6:7], s[14:15], v6, s16, 0 + v_lshlrev_b32_e32 v76, 4, v90 + v_add3_u32 v7, v7, v8, v3 + v_lshlrev_b64 v[6:7], 1, v[6:7] + v_and_b32_e32 v3, 0xf80, v76 + v_sub_co_u32_e64 v6, s[14:15], v6, v3 + v_lshl_add_u64 v[0:1], s[36:37], 0, v[0:1] + s_nop 0 + v_subbrev_co_u32_e64 v7, s[14:15], 0, v7, s[14:15] + v_lshl_add_u64 v[78:79], s[4:5], 0, v[6:7] + v_mul_lo_u32 v6, s17, v4 + v_mul_lo_u32 v7, s16, v5 + v_mad_u64_u32 v[4:5], s[14:15], s16, v4, 0 + v_add3_u32 v5, v5, v7, v6 + v_lshlrev_b64 v[4:5], 1, v[4:5] + v_sub_co_u32_e64 v4, s[14:15], v4, v3 + v_ashrrev_i32_e32 v75, 31, v74 + s_nop 0 + v_subbrev_co_u32_e64 v5, s[14:15], 0, v5, s[14:15] + v_lshl_add_u64 v[80:81], s[4:5], 0, v[4:5] + v_lshl_add_u64 v[4:5], v[0:1], 0, s[56:57] + v_mul_lo_u32 v6, v5, s16 + v_mul_lo_u32 v7, v4, s17 + v_mad_u64_u32 v[4:5], s[4:5], v4, s16, 0 + v_add3_u32 v5, v5, v7, v6 + v_lshlrev_b64 v[4:5], 1, v[4:5] + v_sub_co_u32_e64 v4, s[4:5], v4, v3 + v_mov_b32_e32 v77, v2 + s_nop 0 + v_subbrev_co_u32_e64 v5, s[4:5], 0, v5, s[4:5] + v_lshl_add_u64 v[82:83], s[2:3], 0, v[4:5] + v_mul_lo_u32 v4, s17, v0 + v_mul_lo_u32 v5, s16, v1 + v_mad_u64_u32 v[0:1], s[4:5], s16, v0, 0 + v_add3_u32 v1, v1, v5, v4 + v_lshlrev_b64 v[0:1], 1, v[0:1] + v_sub_co_u32_e64 v0, s[4:5], v0, v3 + v_mov_b32_e32 v66, 0 + s_nop 0 + v_subbrev_co_u32_e64 v1, s[4:5], 0, v1, s[4:5] + v_lshl_add_u64 v[84:85], s[2:3], 0, v[0:1] + s_mov_b32 s4, 0x5040100 + s_mov_b32 s5, 0xffff + v_mov_b32_e32 v67, v2 + v_mov_b32_e32 v68, v2 + v_mov_b32_e32 v69, v2 + v_mov_b32_e32 v62, 0 + v_mov_b32_e32 v63, v2 + v_mov_b32_e32 v64, v2 + v_mov_b32_e32 v65, v2 + v_mov_b32_e32 v58, 0 + v_mov_b32_e32 v59, v2 + v_mov_b32_e32 v60, v2 + v_mov_b32_e32 v61, v2 + v_mov_b32_e32 v54, 0 + v_mov_b32_e32 v55, v2 + v_mov_b32_e32 v56, v2 + v_mov_b32_e32 v57, v2 + v_mov_b32_e32 v50, 0 + v_mov_b32_e32 v51, v2 + v_mov_b32_e32 v52, v2 + v_mov_b32_e32 v53, v2 + v_mov_b32_e32 v46, 0 + v_mov_b32_e32 v47, v2 + v_mov_b32_e32 v48, v2 + v_mov_b32_e32 v49, v2 + v_mov_b32_e32 v42, 0 + v_mov_b32_e32 v43, v2 + v_mov_b32_e32 v44, v2 + v_mov_b32_e32 v45, v2 + v_mov_b32_e32 v38, 0 + v_mov_b32_e32 v39, v2 + v_mov_b32_e32 v40, v2 + v_mov_b32_e32 v41, v2 + v_mov_b32_e32 v34, 0 + v_mov_b32_e32 v35, v2 + v_mov_b32_e32 v36, v2 + v_mov_b32_e32 v37, v2 + v_mov_b32_e32 v30, 0 + v_mov_b32_e32 v31, v2 + v_mov_b32_e32 v32, v2 + v_mov_b32_e32 v33, v2 + v_mov_b32_e32 v26, 0 + v_mov_b32_e32 v27, v2 + v_mov_b32_e32 v28, v2 + v_mov_b32_e32 v29, v2 + v_mov_b32_e32 v22, 0 + v_mov_b32_e32 v23, v2 + v_mov_b32_e32 v24, v2 + v_mov_b32_e32 v25, v2 + v_mov_b32_e32 v18, 0 + v_mov_b32_e32 v19, v2 + v_mov_b32_e32 v20, v2 + v_mov_b32_e32 v21, v2 + v_mov_b32_e32 v10, 0 + v_mov_b32_e32 v11, v2 + v_mov_b32_e32 v12, v2 + v_mov_b32_e32 v13, v2 + v_mov_b32_e32 v14, 0 + v_mov_b32_e32 v15, v2 + v_mov_b32_e32 v16, v2 + v_mov_b32_e32 v17, v2 + v_mov_b32_e32 v6, 0 + v_mov_b32_e32 v7, v2 + v_mov_b32_e32 v8, v2 + v_mov_b32_e32 v9, v2 + v_mov_b32_e32 v95, 0x5040100 + scratch_store_dword off, v71, off + s_branch .LBB0_3 +.LBB0_2: + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v0, 0x4400, v91 + ds_write2_b64 v0, v[70:71], v[72:73] offset1:1 + v_add_u32_e32 v0, 0x8800, v93 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read2_b64 v[104:107], v0 offset1:1 + v_add_u32_e32 v0, 0x8840, v93 + ds_read2_b64 v[108:111], v0 offset1:1 + ds_read2_b64 v[112:115], v92 offset1:1 + ds_read2_b64 v[116:119], v92 offset0:8 offset1:9 + v_add_u32_e32 v0, 0x880, v92 + ds_read2_b64 v[120:123], v0 offset1:1 + v_add_u32_e32 v0, 0x8c0, v92 + ds_read2_b64 v[124:127], v0 offset1:1 + v_add_u32_e32 v0, 0x1100, v92 + ds_read2_b64 v[86:89], v0 offset1:1 + v_add_u32_e32 v0, 0x1140, v92 + ds_read2_b64 v[100:103], v0 offset1:1 + v_add_u32_e32 v0, 0x1980, v92 + ds_read2_b64 v[70:73], v0 offset1:1 + v_add_u32_e32 v0, 0x19c0, v92 + ds_read2_b64 v[96:99], v0 offset1:1 + v_add_u32_e32 v0, 0x9080, v93 + s_waitcnt lgkmcnt(7) + v_mfma_f32_16x16x32_bf16 v[66:69], v[104:107], v[112:115], v[66:69] + s_add_u32 s54, s54, -1 + s_addc_u32 s55, s55, -1 + v_lshl_add_u64 v[78:79], v[78:79], 0, s[56:57] + s_waitcnt lgkmcnt(5) + v_mfma_f32_16x16x32_bf16 v[62:65], v[104:107], v[120:123], v[62:65] + v_lshl_add_u64 v[80:81], v[80:81], 0, s[56:57] + v_lshl_add_u64 v[82:83], v[82:83], 0, s[56:57] + v_lshl_add_u64 v[84:85], v[84:85], 0, s[56:57] + s_waitcnt lgkmcnt(3) + v_mfma_f32_16x16x32_bf16 v[58:61], v[104:107], v[86:89], v[58:61] + v_lshl_add_u64 v[74:75], v[74:75], 0, 64 + s_cmp_lg_u64 s[54:55], 0 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[54:57], v[104:107], v[70:73], v[54:57] + ds_read2_b64 v[104:107], v0 offset1:1 + v_add_u32_e32 v0, 0x90c0, v93 + v_mfma_f32_16x16x32_bf16 v[66:69], v[108:111], v[116:119], v[66:69] + v_mfma_f32_16x16x32_bf16 v[62:65], v[108:111], v[124:127], v[62:65] + v_mfma_f32_16x16x32_bf16 v[58:61], v[108:111], v[100:103], v[58:61] + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[54:57], v[108:111], v[96:99], v[54:57] + ds_read2_b64 v[108:111], v0 offset1:1 + v_add_u32_e32 v0, 0x9900, v93 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[50:53], v[104:107], v[112:115], v[50:53] + v_mfma_f32_16x16x32_bf16 v[46:49], v[104:107], v[120:123], v[46:49] + v_mfma_f32_16x16x32_bf16 v[42:45], v[104:107], v[86:89], v[42:45] + v_mfma_f32_16x16x32_bf16 v[38:41], v[104:107], v[70:73], v[38:41] + ds_read2_b64 v[104:107], v0 offset1:1 + v_add_u32_e32 v0, 0x9940, v93 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[50:53], v[108:111], v[116:119], v[50:53] + v_mfma_f32_16x16x32_bf16 v[46:49], v[108:111], v[124:127], v[46:49] + v_mfma_f32_16x16x32_bf16 v[42:45], v[108:111], v[100:103], v[42:45] + v_mfma_f32_16x16x32_bf16 v[38:41], v[108:111], v[96:99], v[38:41] + ds_read2_b64 v[108:111], v0 offset1:1 + v_add_u32_e32 v0, 0x8800, v94 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[34:37], v[104:107], v[112:115], v[34:37] + v_mfma_f32_16x16x32_bf16 v[30:33], v[104:107], v[120:123], v[30:33] + v_mfma_f32_16x16x32_bf16 v[26:29], v[104:107], v[86:89], v[26:29] + v_mfma_f32_16x16x32_bf16 v[22:25], v[104:107], v[70:73], v[22:25] + ds_read2_b64 v[104:107], v0 offset1:1 + v_add_u32_e32 v0, 0x8840, v94 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[34:37], v[108:111], v[116:119], v[34:37] + v_mfma_f32_16x16x32_bf16 v[30:33], v[108:111], v[124:127], v[30:33] + v_mfma_f32_16x16x32_bf16 v[26:29], v[108:111], v[100:103], v[26:29] + v_mfma_f32_16x16x32_bf16 v[22:25], v[108:111], v[96:99], v[22:25] + ds_read2_b64 v[108:111], v0 offset1:1 + s_waitcnt lgkmcnt(1) + v_mfma_f32_16x16x32_bf16 v[18:21], v[104:107], v[112:115], v[18:21] + v_mfma_f32_16x16x32_bf16 v[10:13], v[104:107], v[120:123], v[10:13] + v_mfma_f32_16x16x32_bf16 v[14:17], v[104:107], v[86:89], v[14:17] + v_mfma_f32_16x16x32_bf16 v[4:7], v[104:107], v[70:73], v[6:9] + s_waitcnt lgkmcnt(0) + v_mfma_f32_16x16x32_bf16 v[18:21], v[108:111], v[116:119], v[18:21] + v_mfma_f32_16x16x32_bf16 v[10:13], v[108:111], v[124:127], v[10:13] + v_mfma_f32_16x16x32_bf16 v[14:17], v[108:111], v[100:103], v[14:17] + v_mfma_f32_16x16x32_bf16 v[6:9], v[108:111], v[96:99], v[4:7] + s_cbranch_scc0 .LBB0_67 +.LBB0_3: + s_nop 1 + v_mov_b32_e32 v4, v2 + v_mov_b32_e32 v5, v2 + v_cmp_gt_i64_e64 s[28:29], s[12:13], v[74:75] + v_mov_b32_e32 v3, v2 + v_mov_b64_e32 v[72:73], v[4:5] + v_cmp_gt_i64_e64 s[14:15], s[40:41], v[74:75] + v_cmp_gt_i64_e64 s[16:17], s[42:43], v[74:75] + v_cmp_gt_i64_e64 s[18:19], s[44:45], v[74:75] + v_cmp_gt_i64_e64 s[20:21], s[46:47], v[74:75] + v_cmp_gt_i64_e64 s[26:27], s[52:53], v[74:75] + v_cmp_gt_i64_e64 s[24:25], s[50:51], v[74:75] + v_cmp_gt_i64_e64 s[22:23], s[48:49], v[74:75] + s_and_b64 s[58:59], vcc, s[28:29] + v_lshl_add_u64 v[86:87], v[84:85], 0, v[76:77] + v_mov_b64_e32 v[70:71], v[2:3] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_38 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_39 +.LBB0_5: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_40 +.LBB0_6: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_41 +.LBB0_7: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_42 +.LBB0_8: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_43 +.LBB0_9: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_44 +.LBB0_10: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_12 +.LBB0_11: + global_load_ushort v0, v[86:87], off offset:14 + s_waitcnt vmcnt(0) + v_perm_b32 v73, v0, v73, s4 +.LBB0_12: + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v0, 0x8800, v91 + v_mov_b32_e32 v4, v2 + v_mov_b32_e32 v5, v2 + s_barrier + ds_write2_b64 v0, v[70:71], v[72:73] offset1:1 + v_mov_b32_e32 v3, v2 + v_mov_b64_e32 v[72:73], v[4:5] + s_and_b64 s[58:59], s[0:1], s[28:29] + v_lshl_add_u64 v[86:87], v[82:83], 0, v[76:77] + v_mov_b64_e32 v[70:71], v[2:3] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_45 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_46 +.LBB0_14: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_47 +.LBB0_15: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_48 +.LBB0_16: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_49 +.LBB0_17: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_50 +.LBB0_18: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_51 +.LBB0_19: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_21 +.LBB0_20: + global_load_ushort v0, v[86:87], off offset:14 + s_waitcnt vmcnt(0) + v_perm_b32 v73, v0, v73, s4 +.LBB0_21: + s_or_b64 exec, exec, s[2:3] + v_add_u32_e32 v0, 0xcc00, v91 + v_mov_b32_e32 v4, v2 + v_mov_b32_e32 v5, v2 + ds_write2_b64 v0, v[70:71], v[72:73] offset1:1 + v_mov_b32_e32 v3, v2 + v_mov_b64_e32 v[72:73], v[4:5] + s_and_b64 s[58:59], s[30:31], s[28:29] + v_lshl_add_u64 v[86:87], v[80:81], 0, v[76:77] + v_mov_b64_e32 v[70:71], v[2:3] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_52 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_53 +.LBB0_23: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_54 +.LBB0_24: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_55 +.LBB0_25: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_56 +.LBB0_26: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_57 +.LBB0_27: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_58 +.LBB0_28: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_30 +.LBB0_29: + global_load_ushort v0, v[86:87], off offset:14 + s_waitcnt vmcnt(0) + v_perm_b32 v73, v0, v73, s4 +.LBB0_30: + s_or_b64 exec, exec, s[2:3] + v_mov_b32_e32 v4, v2 + v_mov_b32_e32 v5, v2 + ds_write2_b64 v91, v[70:71], v[72:73] offset1:1 + v_mov_b32_e32 v3, v2 + v_mov_b64_e32 v[72:73], v[4:5] + s_and_b64 s[28:29], s[34:35], s[28:29] + v_lshl_add_u64 v[86:87], v[78:79], 0, v[76:77] + v_mov_b64_e32 v[70:71], v[2:3] + s_and_saveexec_b64 s[2:3], s[28:29] + s_cbranch_execnz .LBB0_59 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[26:27], s[34:35], s[26:27] + s_and_saveexec_b64 s[2:3], s[26:27] + s_cbranch_execnz .LBB0_60 +.LBB0_32: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[24:25], s[34:35], s[24:25] + s_and_saveexec_b64 s[2:3], s[24:25] + s_cbranch_execnz .LBB0_61 +.LBB0_33: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[22:23], s[34:35], s[22:23] + s_and_saveexec_b64 s[2:3], s[22:23] + s_cbranch_execnz .LBB0_62 +.LBB0_34: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[20:21], s[34:35], s[20:21] + s_and_saveexec_b64 s[2:3], s[20:21] + s_cbranch_execnz .LBB0_63 +.LBB0_35: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[18:19], s[34:35], s[18:19] + s_and_saveexec_b64 s[2:3], s[18:19] + s_cbranch_execnz .LBB0_64 +.LBB0_36: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[16:17], s[34:35], s[16:17] + s_and_saveexec_b64 s[2:3], s[16:17] + s_cbranch_execnz .LBB0_65 +.LBB0_37: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[14:15], s[34:35], s[14:15] + s_and_saveexec_b64 s[2:3], s[14:15] + s_cbranch_execz .LBB0_2 + s_branch .LBB0_66 +.LBB0_38: + global_load_ushort v0, v[86:87], off + v_mov_b32_e32 v3, v2 + v_mov_b32_e32 v1, v2 + s_waitcnt vmcnt(0) + v_perm_b32 v0, 0, v0, v95 + v_mov_b64_e32 v[72:73], v[2:3] + v_mov_b64_e32 v[70:71], v[0:1] + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_5 +.LBB0_39: + global_load_ushort v0, v[86:87], off offset:2 + s_waitcnt vmcnt(0) + v_perm_b32 v70, v0, v70, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_6 +.LBB0_40: + global_load_ushort v0, v[86:87], off offset:4 + s_waitcnt vmcnt(0) + v_bfi_b32 v71, s5, v0, v71 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_7 +.LBB0_41: + global_load_ushort v0, v[86:87], off offset:6 + s_waitcnt vmcnt(0) + v_perm_b32 v71, v0, v71, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_8 +.LBB0_42: + global_load_ushort v0, v[86:87], off offset:8 + s_waitcnt vmcnt(0) + v_bfi_b32 v72, s5, v0, v72 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_9 +.LBB0_43: + global_load_ushort v0, v[86:87], off offset:10 + s_waitcnt vmcnt(0) + v_perm_b32 v72, v0, v72, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_10 +.LBB0_44: + global_load_ushort v0, v[86:87], off offset:12 + s_waitcnt vmcnt(0) + v_bfi_b32 v73, s5, v0, v73 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], vcc, s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_11 + s_branch .LBB0_12 +.LBB0_45: + global_load_ushort v0, v[86:87], off + v_mov_b32_e32 v3, v2 + v_mov_b32_e32 v1, v2 + s_waitcnt vmcnt(0) + v_perm_b32 v0, 0, v0, v95 + v_mov_b64_e32 v[72:73], v[2:3] + v_mov_b64_e32 v[70:71], v[0:1] + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_14 +.LBB0_46: + global_load_ushort v0, v[86:87], off offset:2 + s_waitcnt vmcnt(0) + v_perm_b32 v70, v0, v70, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_15 +.LBB0_47: + global_load_ushort v0, v[86:87], off offset:4 + s_waitcnt vmcnt(0) + v_bfi_b32 v71, s5, v0, v71 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_16 +.LBB0_48: + global_load_ushort v0, v[86:87], off offset:6 + s_waitcnt vmcnt(0) + v_perm_b32 v71, v0, v71, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_17 +.LBB0_49: + global_load_ushort v0, v[86:87], off offset:8 + s_waitcnt vmcnt(0) + v_bfi_b32 v72, s5, v0, v72 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_18 +.LBB0_50: + global_load_ushort v0, v[86:87], off offset:10 + s_waitcnt vmcnt(0) + v_perm_b32 v72, v0, v72, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_19 +.LBB0_51: + global_load_ushort v0, v[86:87], off offset:12 + s_waitcnt vmcnt(0) + v_bfi_b32 v73, s5, v0, v73 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[0:1], s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_20 + s_branch .LBB0_21 +.LBB0_52: + global_load_ushort v0, v[86:87], off + v_mov_b32_e32 v3, v2 + v_mov_b32_e32 v1, v2 + s_waitcnt vmcnt(0) + v_perm_b32 v0, 0, v0, v95 + v_mov_b64_e32 v[72:73], v[2:3] + v_mov_b64_e32 v[70:71], v[0:1] + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[26:27] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_23 +.LBB0_53: + global_load_ushort v0, v[86:87], off offset:2 + s_waitcnt vmcnt(0) + v_perm_b32 v70, v0, v70, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[24:25] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_24 +.LBB0_54: + global_load_ushort v0, v[86:87], off offset:4 + s_waitcnt vmcnt(0) + v_bfi_b32 v71, s5, v0, v71 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[22:23] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_25 +.LBB0_55: + global_load_ushort v0, v[86:87], off offset:6 + s_waitcnt vmcnt(0) + v_perm_b32 v71, v0, v71, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[20:21] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_26 +.LBB0_56: + global_load_ushort v0, v[86:87], off offset:8 + s_waitcnt vmcnt(0) + v_bfi_b32 v72, s5, v0, v72 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[18:19] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_27 +.LBB0_57: + global_load_ushort v0, v[86:87], off offset:10 + s_waitcnt vmcnt(0) + v_perm_b32 v72, v0, v72, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[16:17] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execz .LBB0_28 +.LBB0_58: + global_load_ushort v0, v[86:87], off offset:12 + s_waitcnt vmcnt(0) + v_bfi_b32 v73, s5, v0, v73 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[58:59], s[30:31], s[14:15] + s_and_saveexec_b64 s[2:3], s[58:59] + s_cbranch_execnz .LBB0_29 + s_branch .LBB0_30 +.LBB0_59: + global_load_ushort v0, v[86:87], off + v_mov_b32_e32 v3, v2 + v_mov_b32_e32 v1, v2 + s_waitcnt vmcnt(0) + v_perm_b32 v0, 0, v0, v95 + v_mov_b64_e32 v[72:73], v[2:3] + v_mov_b64_e32 v[70:71], v[0:1] + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[26:27], s[34:35], s[26:27] + s_and_saveexec_b64 s[2:3], s[26:27] + s_cbranch_execz .LBB0_32 +.LBB0_60: + global_load_ushort v0, v[86:87], off offset:2 + s_waitcnt vmcnt(0) + v_perm_b32 v70, v0, v70, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[24:25], s[34:35], s[24:25] + s_and_saveexec_b64 s[2:3], s[24:25] + s_cbranch_execz .LBB0_33 +.LBB0_61: + global_load_ushort v0, v[86:87], off offset:4 + s_waitcnt vmcnt(0) + v_bfi_b32 v71, s5, v0, v71 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[22:23], s[34:35], s[22:23] + s_and_saveexec_b64 s[2:3], s[22:23] + s_cbranch_execz .LBB0_34 +.LBB0_62: + global_load_ushort v0, v[86:87], off offset:6 + s_waitcnt vmcnt(0) + v_perm_b32 v71, v0, v71, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[20:21], s[34:35], s[20:21] + s_and_saveexec_b64 s[2:3], s[20:21] + s_cbranch_execz .LBB0_35 +.LBB0_63: + global_load_ushort v0, v[86:87], off offset:8 + s_waitcnt vmcnt(0) + v_bfi_b32 v72, s5, v0, v72 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[18:19], s[34:35], s[18:19] + s_and_saveexec_b64 s[2:3], s[18:19] + s_cbranch_execz .LBB0_36 +.LBB0_64: + global_load_ushort v0, v[86:87], off offset:10 + s_waitcnt vmcnt(0) + v_perm_b32 v72, v0, v72, s4 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[16:17], s[34:35], s[16:17] + s_and_saveexec_b64 s[2:3], s[16:17] + s_cbranch_execz .LBB0_37 +.LBB0_65: + global_load_ushort v0, v[86:87], off offset:12 + s_waitcnt vmcnt(0) + v_bfi_b32 v73, s5, v0, v73 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[14:15], s[34:35], s[14:15] + s_and_saveexec_b64 s[2:3], s[14:15] + s_cbranch_execz .LBB0_2 +.LBB0_66: + global_load_ushort v0, v[86:87], off offset:14 + s_waitcnt vmcnt(0) + v_perm_b32 v73, v0, v73, s4 + s_branch .LBB0_2 +.LBB0_67: + scratch_load_dword v71, off, off + v_bfe_u32 v70, v90, 4, 2 + s_branch .LBB0_69 +.LBB0_68: + v_mov_b32_e32 v69, 0 + v_mov_b32_e32 v68, v69 + v_mov_b32_e32 v67, v69 + v_mov_b32_e32 v66, v69 + v_mov_b32_e32 v65, v69 + v_mov_b32_e32 v64, v69 + v_mov_b32_e32 v63, v69 + v_mov_b32_e32 v62, v69 + v_mov_b32_e32 v61, v69 + v_mov_b32_e32 v60, v69 + v_mov_b32_e32 v59, v69 + v_mov_b32_e32 v58, v69 + v_mov_b32_e32 v57, v69 + v_mov_b32_e32 v56, v69 + v_mov_b32_e32 v55, v69 + v_mov_b32_e32 v54, v69 + v_mov_b32_e32 v53, v69 + v_mov_b32_e32 v52, v69 + v_mov_b32_e32 v51, v69 + v_mov_b32_e32 v50, v69 + v_mov_b32_e32 v49, v69 + v_mov_b32_e32 v48, v69 + v_mov_b32_e32 v47, v69 + v_mov_b32_e32 v46, v69 + v_mov_b32_e32 v45, v69 + v_mov_b32_e32 v44, v69 + v_mov_b32_e32 v43, v69 + v_mov_b32_e32 v42, v69 + v_mov_b32_e32 v41, v69 + v_mov_b32_e32 v40, v69 + v_mov_b32_e32 v39, v69 + v_mov_b32_e32 v38, v69 + v_mov_b32_e32 v37, v69 + v_mov_b32_e32 v36, v69 + v_mov_b32_e32 v35, v69 + v_mov_b32_e32 v34, v69 + v_mov_b32_e32 v33, v69 + v_mov_b32_e32 v32, v69 + v_mov_b32_e32 v31, v69 + v_mov_b32_e32 v30, v69 + v_mov_b32_e32 v29, v69 + v_mov_b32_e32 v28, v69 + v_mov_b32_e32 v27, v69 + v_mov_b32_e32 v26, v69 + v_mov_b32_e32 v25, v69 + v_mov_b32_e32 v24, v69 + v_mov_b32_e32 v23, v69 + v_mov_b32_e32 v22, v69 + v_mov_b32_e32 v21, v69 + v_mov_b32_e32 v20, v69 + v_mov_b32_e32 v19, v69 + v_mov_b32_e32 v18, v69 + v_mov_b32_e32 v13, v69 + v_mov_b32_e32 v12, v69 + v_mov_b32_e32 v11, v69 + v_mov_b32_e32 v10, v69 + v_mov_b32_e32 v17, v69 + v_mov_b32_e32 v16, v69 + v_mov_b32_e32 v15, v69 + v_mov_b32_e32 v14, v69 + v_mov_b32_e32 v9, v69 + v_mov_b32_e32 v8, v69 + v_mov_b32_e32 v7, v69 + v_mov_b32_e32 v6, v69 +.LBB0_69: + v_and_b32_e32 v2, 0xc0, v90 + v_lshlrev_b32_e32 v3, 2, v70 + s_waitcnt vmcnt(0) + v_or_b32_e32 v0, s38, v71 + v_mov_b32_e32 v1, s39 + v_or3_b32 v2, v3, v2, s36 + v_mov_b32_e32 v3, s37 + v_cmp_gt_u64_e32 vcc, s[10:11], v[0:1] + v_cmp_gt_u64_e64 s[12:13], s[8:9], v[2:3] + s_and_b64 s[2:3], s[12:13], vcc + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_71 + v_mul_lo_u32 v70, s11, v2 + v_mul_lo_u32 v71, s10, v3 + v_mad_u64_u32 v[4:5], s[2:3], s10, v2, 0 + v_add3_u32 v5, v5, v71, v70 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v66, off +.LBB0_71: + s_or_b64 exec, exec, s[0:1] + v_or_b32_e32 v4, 1, v2 + v_mov_b32_e32 v5, v3 + v_cmp_gt_u64_e64 s[14:15], s[8:9], v[4:5] + s_and_b64 s[2:3], s[14:15], vcc + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_73 + v_mul_lo_u32 v66, s11, v4 + v_mul_lo_u32 v72, s10, v5 + v_mad_u64_u32 v[70:71], s[2:3], s10, v4, 0 + v_add3_u32 v71, v71, v72, v66 + v_lshl_add_u64 v[70:71], v[70:71], 2, s[6:7] + v_lshl_add_u64 v[70:71], v[0:1], 2, v[70:71] + global_store_dword v[70:71], v67, off +.LBB0_73: + s_or_b64 exec, exec, s[0:1] + v_or_b32_e32 v66, 2, v2 + v_mov_b32_e32 v67, v3 + v_cmp_gt_u64_e64 s[16:17], s[8:9], v[66:67] + s_and_b64 s[2:3], s[16:17], vcc + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_75 + v_mul_lo_u32 v72, s11, v66 + v_mul_lo_u32 v73, s10, v67 + v_mad_u64_u32 v[70:71], s[2:3], s10, v66, 0 + v_add3_u32 v71, v71, v73, v72 + v_lshl_add_u64 v[70:71], v[70:71], 2, s[6:7] + v_lshl_add_u64 v[70:71], v[0:1], 2, v[70:71] + global_store_dword v[70:71], v68, off +.LBB0_75: + s_or_b64 exec, exec, s[0:1] + v_or_b32_e32 v70, 3, v2 + v_mov_b32_e32 v71, v3 + v_cmp_gt_u64_e64 s[18:19], s[8:9], v[70:71] + s_and_b64 s[2:3], s[18:19], vcc + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_77 + v_mul_lo_u32 v68, s11, v70 + v_mul_lo_u32 v74, s10, v71 + v_mad_u64_u32 v[72:73], s[2:3], s10, v70, 0 + v_add3_u32 v73, v73, v74, v68 + v_lshl_add_u64 v[72:73], v[72:73], 2, s[6:7] + v_lshl_add_u64 v[72:73], v[0:1], 2, v[72:73] + global_store_dword v[72:73], v69, off +.LBB0_77: + s_or_b64 exec, exec, s[0:1] + v_or_b32_e32 v68, 16, v0 + v_mov_b32_e32 v69, v1 + v_cmp_gt_u64_e64 s[0:1], s[10:11], v[68:69] + s_and_b64 s[4:5], s[12:13], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execnz .LBB0_152 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[14:15], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execnz .LBB0_153 +.LBB0_79: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[16:17], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execnz .LBB0_154 +.LBB0_80: + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[18:19], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execz .LBB0_82 +.LBB0_81: + v_mul_lo_u32 v64, s11, v70 + v_mul_lo_u32 v68, s10, v71 + v_mad_u64_u32 v[62:63], s[4:5], s10, v70, 0 + v_add3_u32 v63, v63, v68, v64 + v_lshl_add_u64 v[62:63], v[62:63], 2, s[6:7] + v_lshl_add_u64 v[62:63], v[0:1], 2, v[62:63] + global_store_dword v[62:63], v65, off offset:64 +.LBB0_82: + s_or_b64 exec, exec, s[2:3] + v_or_b32_e32 v62, 32, v0 + v_mov_b32_e32 v63, v1 + v_cmp_gt_u64_e64 s[2:3], s[10:11], v[62:63] + s_and_b64 s[20:21], s[12:13], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execnz .LBB0_155 + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[14:15], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execnz .LBB0_156 +.LBB0_84: + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[16:17], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execnz .LBB0_157 +.LBB0_85: + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[18:19], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execz .LBB0_87 +.LBB0_86: + v_mul_lo_u32 v60, s11, v70 + v_mul_lo_u32 v62, s10, v71 + v_mad_u64_u32 v[58:59], s[20:21], s10, v70, 0 + v_add3_u32 v59, v59, v62, v60 + v_lshl_add_u64 v[58:59], v[58:59], 2, s[6:7] + v_lshl_add_u64 v[58:59], v[0:1], 2, v[58:59] + global_store_dword v[58:59], v61, off offset:128 +.LBB0_87: + s_or_b64 exec, exec, s[4:5] + v_or_b32_e32 v58, 48, v0 + v_mov_b32_e32 v59, v1 + v_cmp_gt_u64_e64 s[4:5], s[10:11], v[58:59] + s_and_b64 s[20:21], s[12:13], s[4:5] + s_and_saveexec_b64 s[12:13], s[20:21] + s_cbranch_execnz .LBB0_158 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_159 +.LBB0_89: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_160 +.LBB0_90: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_92 +.LBB0_91: + v_mul_lo_u32 v54, s11, v70 + v_mul_lo_u32 v55, s10, v71 + v_mad_u64_u32 v[4:5], s[14:15], s10, v70, 0 + v_add3_u32 v5, v5, v55, v54 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v57, off offset:192 +.LBB0_92: + s_or_b64 exec, exec, s[12:13] + v_or_b32_e32 v4, 16, v2 + v_mov_b32_e32 v5, v3 + v_cmp_gt_u64_e64 s[12:13], s[8:9], v[4:5] + s_and_b64 s[16:17], s[12:13], vcc + s_and_saveexec_b64 s[14:15], s[16:17] + s_cbranch_execz .LBB0_94 + v_mul_lo_u32 v56, s11, v4 + v_mul_lo_u32 v57, s10, v5 + v_mad_u64_u32 v[54:55], s[16:17], s10, v4, 0 + v_add3_u32 v55, v55, v57, v56 + v_lshl_add_u64 v[54:55], v[54:55], 2, s[6:7] + v_lshl_add_u64 v[54:55], v[0:1], 2, v[54:55] + global_store_dword v[54:55], v50, off +.LBB0_94: + s_or_b64 exec, exec, s[14:15] + v_or_b32_e32 v54, 17, v2 + v_mov_b32_e32 v55, v3 + v_cmp_gt_u64_e64 s[14:15], s[8:9], v[54:55] + s_and_b64 s[18:19], s[14:15], vcc + s_and_saveexec_b64 s[16:17], s[18:19] + s_cbranch_execz .LBB0_96 + v_mul_lo_u32 v50, s11, v54 + v_mul_lo_u32 v58, s10, v55 + v_mad_u64_u32 v[56:57], s[18:19], s10, v54, 0 + v_add3_u32 v57, v57, v58, v50 + v_lshl_add_u64 v[56:57], v[56:57], 2, s[6:7] + v_lshl_add_u64 v[56:57], v[0:1], 2, v[56:57] + global_store_dword v[56:57], v51, off +.LBB0_96: + s_or_b64 exec, exec, s[16:17] + v_or_b32_e32 v50, 18, v2 + v_mov_b32_e32 v51, v3 + v_cmp_gt_u64_e64 s[16:17], s[8:9], v[50:51] + s_and_b64 s[20:21], s[16:17], vcc + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_98 + v_mul_lo_u32 v58, s11, v50 + v_mul_lo_u32 v59, s10, v51 + v_mad_u64_u32 v[56:57], s[20:21], s10, v50, 0 + v_add3_u32 v57, v57, v59, v58 + v_lshl_add_u64 v[56:57], v[56:57], 2, s[6:7] + v_lshl_add_u64 v[56:57], v[0:1], 2, v[56:57] + global_store_dword v[56:57], v52, off +.LBB0_98: + s_or_b64 exec, exec, s[18:19] + v_or_b32_e32 v56, 19, v2 + v_mov_b32_e32 v57, v3 + v_cmp_gt_u64_e64 s[18:19], s[8:9], v[56:57] + s_and_b64 s[22:23], s[18:19], vcc + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_161 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_162 +.LBB0_100: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_163 +.LBB0_101: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_164 +.LBB0_102: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_165 +.LBB0_103: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_166 +.LBB0_104: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_167 +.LBB0_105: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_168 +.LBB0_106: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_169 +.LBB0_107: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[20:21], s[12:13], s[4:5] + s_and_saveexec_b64 s[12:13], s[20:21] + s_cbranch_execnz .LBB0_170 +.LBB0_108: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_171 +.LBB0_109: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_172 +.LBB0_110: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_112 +.LBB0_111: + v_mul_lo_u32 v38, s11, v56 + v_mul_lo_u32 v39, s10, v57 + v_mad_u64_u32 v[4:5], s[14:15], s10, v56, 0 + v_add3_u32 v5, v5, v39, v38 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v41, off offset:192 +.LBB0_112: + s_or_b64 exec, exec, s[12:13] + v_or_b32_e32 v4, 32, v2 + v_mov_b32_e32 v5, v3 + v_cmp_gt_u64_e64 s[12:13], s[8:9], v[4:5] + s_and_b64 s[16:17], s[12:13], vcc + s_and_saveexec_b64 s[14:15], s[16:17] + s_cbranch_execz .LBB0_114 + v_mul_lo_u32 v40, s11, v4 + v_mul_lo_u32 v41, s10, v5 + v_mad_u64_u32 v[38:39], s[16:17], s10, v4, 0 + v_add3_u32 v39, v39, v41, v40 + v_lshl_add_u64 v[38:39], v[38:39], 2, s[6:7] + v_lshl_add_u64 v[38:39], v[0:1], 2, v[38:39] + global_store_dword v[38:39], v34, off +.LBB0_114: + s_or_b64 exec, exec, s[14:15] + v_or_b32_e32 v38, 33, v2 + v_mov_b32_e32 v39, v3 + v_cmp_gt_u64_e64 s[14:15], s[8:9], v[38:39] + s_and_b64 s[18:19], s[14:15], vcc + s_and_saveexec_b64 s[16:17], s[18:19] + s_cbranch_execz .LBB0_116 + v_mul_lo_u32 v34, s11, v38 + v_mul_lo_u32 v42, s10, v39 + v_mad_u64_u32 v[40:41], s[18:19], s10, v38, 0 + v_add3_u32 v41, v41, v42, v34 + v_lshl_add_u64 v[40:41], v[40:41], 2, s[6:7] + v_lshl_add_u64 v[40:41], v[0:1], 2, v[40:41] + global_store_dword v[40:41], v35, off +.LBB0_116: + s_or_b64 exec, exec, s[16:17] + v_or_b32_e32 v34, 34, v2 + v_mov_b32_e32 v35, v3 + v_cmp_gt_u64_e64 s[16:17], s[8:9], v[34:35] + s_and_b64 s[20:21], s[16:17], vcc + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_118 + v_mul_lo_u32 v42, s11, v34 + v_mul_lo_u32 v43, s10, v35 + v_mad_u64_u32 v[40:41], s[20:21], s10, v34, 0 + v_add3_u32 v41, v41, v43, v42 + v_lshl_add_u64 v[40:41], v[40:41], 2, s[6:7] + v_lshl_add_u64 v[40:41], v[0:1], 2, v[40:41] + global_store_dword v[40:41], v36, off +.LBB0_118: + s_or_b64 exec, exec, s[18:19] + v_or_b32_e32 v40, 35, v2 + v_mov_b32_e32 v41, v3 + v_cmp_gt_u64_e64 s[18:19], s[8:9], v[40:41] + s_and_b64 s[22:23], s[18:19], vcc + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_173 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_174 +.LBB0_120: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_175 +.LBB0_121: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_176 +.LBB0_122: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_177 +.LBB0_123: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_178 +.LBB0_124: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_179 +.LBB0_125: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_180 +.LBB0_126: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execnz .LBB0_181 +.LBB0_127: + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[20:21], s[12:13], s[4:5] + s_and_saveexec_b64 s[12:13], s[20:21] + s_cbranch_execnz .LBB0_182 +.LBB0_128: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_183 +.LBB0_129: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_184 +.LBB0_130: + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_132 +.LBB0_131: + v_mul_lo_u32 v22, s11, v40 + v_mul_lo_u32 v23, s10, v41 + v_mad_u64_u32 v[4:5], s[14:15], s10, v40, 0 + v_add3_u32 v5, v5, v23, v22 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v25, off offset:192 +.LBB0_132: + s_or_b64 exec, exec, s[12:13] + v_or_b32_e32 v4, 48, v2 + v_mov_b32_e32 v5, v3 + v_cmp_gt_u64_e64 s[12:13], s[8:9], v[4:5] + s_and_b64 s[16:17], s[12:13], vcc + s_and_saveexec_b64 s[14:15], s[16:17] + s_cbranch_execz .LBB0_134 + v_mul_lo_u32 v24, s11, v4 + v_mul_lo_u32 v25, s10, v5 + v_mad_u64_u32 v[22:23], s[16:17], s10, v4, 0 + v_add3_u32 v23, v23, v25, v24 + v_lshl_add_u64 v[22:23], v[22:23], 2, s[6:7] + v_lshl_add_u64 v[22:23], v[0:1], 2, v[22:23] + global_store_dword v[22:23], v18, off +.LBB0_134: + s_or_b64 exec, exec, s[14:15] + v_or_b32_e32 v22, 49, v2 + v_mov_b32_e32 v23, v3 + v_cmp_gt_u64_e64 s[14:15], s[8:9], v[22:23] + s_and_b64 s[18:19], s[14:15], vcc + s_and_saveexec_b64 s[16:17], s[18:19] + s_cbranch_execz .LBB0_136 + v_mul_lo_u32 v18, s11, v22 + v_mul_lo_u32 v26, s10, v23 + v_mad_u64_u32 v[24:25], s[18:19], s10, v22, 0 + v_add3_u32 v25, v25, v26, v18 + v_lshl_add_u64 v[24:25], v[24:25], 2, s[6:7] + v_lshl_add_u64 v[24:25], v[0:1], 2, v[24:25] + global_store_dword v[24:25], v19, off +.LBB0_136: + s_or_b64 exec, exec, s[16:17] + v_or_b32_e32 v18, 50, v2 + v_mov_b32_e32 v19, v3 + v_cmp_gt_u64_e64 s[16:17], s[8:9], v[18:19] + s_and_b64 s[20:21], s[16:17], vcc + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_138 + v_mul_lo_u32 v26, s11, v18 + v_mul_lo_u32 v27, s10, v19 + v_mad_u64_u32 v[24:25], s[20:21], s10, v18, 0 + v_add3_u32 v25, v25, v27, v26 + v_lshl_add_u64 v[24:25], v[24:25], 2, s[6:7] + v_lshl_add_u64 v[24:25], v[0:1], 2, v[24:25] + global_store_dword v[24:25], v20, off +.LBB0_138: + s_or_b64 exec, exec, s[18:19] + v_or_b32_e32 v2, 51, v2 + v_cmp_gt_u64_e64 s[8:9], s[8:9], v[2:3] + s_and_b64 s[20:21], s[8:9], vcc + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execnz .LBB0_185 + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[12:13], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execnz .LBB0_186 +.LBB0_140: + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[14:15], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execnz .LBB0_187 +.LBB0_141: + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[16:17], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execnz .LBB0_188 +.LBB0_142: + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[18:19], s[8:9], s[0:1] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execnz .LBB0_189 +.LBB0_143: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[12:13], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execnz .LBB0_190 +.LBB0_144: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[14:15], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execnz .LBB0_191 +.LBB0_145: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[16:17], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execnz .LBB0_192 +.LBB0_146: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[8:9], s[2:3] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_193 +.LBB0_147: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[12:13], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_194 +.LBB0_148: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[14:15], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_195 +.LBB0_149: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[16:17], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_196 +.LBB0_150: + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[0:1], s[8:9], s[4:5] + s_and_saveexec_b64 s[2:3], s[0:1] + s_cbranch_execnz .LBB0_197 +.LBB0_151: + s_endpgm +.LBB0_152: + v_mul_lo_u32 v72, s11, v2 + v_mul_lo_u32 v73, s10, v3 + v_mad_u64_u32 v[68:69], s[4:5], s10, v2, 0 + v_add3_u32 v69, v69, v73, v72 + v_lshl_add_u64 v[68:69], v[68:69], 2, s[6:7] + v_lshl_add_u64 v[68:69], v[0:1], 2, v[68:69] + global_store_dword v[68:69], v62, off offset:64 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[14:15], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execz .LBB0_79 +.LBB0_153: + v_mul_lo_u32 v62, s11, v4 + v_mul_lo_u32 v72, s10, v5 + v_mad_u64_u32 v[68:69], s[4:5], s10, v4, 0 + v_add3_u32 v69, v69, v72, v62 + v_lshl_add_u64 v[68:69], v[68:69], 2, s[6:7] + v_lshl_add_u64 v[68:69], v[0:1], 2, v[68:69] + global_store_dword v[68:69], v63, off offset:64 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[16:17], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execz .LBB0_80 +.LBB0_154: + v_mul_lo_u32 v68, s11, v66 + v_mul_lo_u32 v69, s10, v67 + v_mad_u64_u32 v[62:63], s[4:5], s10, v66, 0 + v_add3_u32 v63, v63, v69, v68 + v_lshl_add_u64 v[62:63], v[62:63], 2, s[6:7] + v_lshl_add_u64 v[62:63], v[0:1], 2, v[62:63] + global_store_dword v[62:63], v64, off offset:64 + s_or_b64 exec, exec, s[2:3] + s_and_b64 s[4:5], s[18:19], s[0:1] + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execnz .LBB0_81 + s_branch .LBB0_82 +.LBB0_155: + v_mul_lo_u32 v64, s11, v2 + v_mul_lo_u32 v65, s10, v3 + v_mad_u64_u32 v[62:63], s[20:21], s10, v2, 0 + v_add3_u32 v63, v63, v65, v64 + v_lshl_add_u64 v[62:63], v[62:63], 2, s[6:7] + v_lshl_add_u64 v[62:63], v[0:1], 2, v[62:63] + global_store_dword v[62:63], v58, off offset:128 + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[14:15], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execz .LBB0_84 +.LBB0_156: + v_mul_lo_u32 v58, s11, v4 + v_mul_lo_u32 v64, s10, v5 + v_mad_u64_u32 v[62:63], s[20:21], s10, v4, 0 + v_add3_u32 v63, v63, v64, v58 + v_lshl_add_u64 v[62:63], v[62:63], 2, s[6:7] + v_lshl_add_u64 v[62:63], v[0:1], 2, v[62:63] + global_store_dword v[62:63], v59, off offset:128 + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[16:17], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execz .LBB0_85 +.LBB0_157: + v_mul_lo_u32 v62, s11, v66 + v_mul_lo_u32 v63, s10, v67 + v_mad_u64_u32 v[58:59], s[20:21], s10, v66, 0 + v_add3_u32 v59, v59, v63, v62 + v_lshl_add_u64 v[58:59], v[58:59], 2, s[6:7] + v_lshl_add_u64 v[58:59], v[0:1], 2, v[58:59] + global_store_dword v[58:59], v60, off offset:128 + s_or_b64 exec, exec, s[4:5] + s_and_b64 s[20:21], s[18:19], s[2:3] + s_and_saveexec_b64 s[4:5], s[20:21] + s_cbranch_execnz .LBB0_86 + s_branch .LBB0_87 +.LBB0_158: + v_mul_lo_u32 v60, s11, v2 + v_mul_lo_u32 v61, s10, v3 + v_mad_u64_u32 v[58:59], s[20:21], s10, v2, 0 + v_add3_u32 v59, v59, v61, v60 + v_lshl_add_u64 v[58:59], v[58:59], 2, s[6:7] + v_lshl_add_u64 v[58:59], v[0:1], 2, v[58:59] + global_store_dword v[58:59], v54, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_89 +.LBB0_159: + v_mul_lo_u32 v54, s11, v4 + v_mul_lo_u32 v58, s10, v5 + v_mad_u64_u32 v[4:5], s[14:15], s10, v4, 0 + v_add3_u32 v5, v5, v58, v54 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v55, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_90 +.LBB0_160: + v_mul_lo_u32 v54, s11, v66 + v_mul_lo_u32 v55, s10, v67 + v_mad_u64_u32 v[4:5], s[14:15], s10, v66, 0 + v_add3_u32 v5, v5, v55, v54 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v56, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_91 + s_branch .LBB0_92 +.LBB0_161: + v_mul_lo_u32 v52, s11, v56 + v_mul_lo_u32 v60, s10, v57 + v_mad_u64_u32 v[58:59], s[22:23], s10, v56, 0 + v_add3_u32 v59, v59, v60, v52 + v_lshl_add_u64 v[58:59], v[58:59], 2, s[6:7] + v_lshl_add_u64 v[58:59], v[0:1], 2, v[58:59] + global_store_dword v[58:59], v53, off + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_100 +.LBB0_162: + v_mul_lo_u32 v58, s11, v4 + v_mul_lo_u32 v59, s10, v5 + v_mad_u64_u32 v[52:53], s[22:23], s10, v4, 0 + v_add3_u32 v53, v53, v59, v58 + v_lshl_add_u64 v[52:53], v[52:53], 2, s[6:7] + v_lshl_add_u64 v[52:53], v[0:1], 2, v[52:53] + global_store_dword v[52:53], v46, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_101 +.LBB0_163: + v_mul_lo_u32 v46, s11, v54 + v_mul_lo_u32 v58, s10, v55 + v_mad_u64_u32 v[52:53], s[22:23], s10, v54, 0 + v_add3_u32 v53, v53, v58, v46 + v_lshl_add_u64 v[52:53], v[52:53], 2, s[6:7] + v_lshl_add_u64 v[52:53], v[0:1], 2, v[52:53] + global_store_dword v[52:53], v47, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_102 +.LBB0_164: + v_mul_lo_u32 v52, s11, v50 + v_mul_lo_u32 v53, s10, v51 + v_mad_u64_u32 v[46:47], s[22:23], s10, v50, 0 + v_add3_u32 v47, v47, v53, v52 + v_lshl_add_u64 v[46:47], v[46:47], 2, s[6:7] + v_lshl_add_u64 v[46:47], v[0:1], 2, v[46:47] + global_store_dword v[46:47], v48, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_103 +.LBB0_165: + v_mul_lo_u32 v48, s11, v56 + v_mul_lo_u32 v52, s10, v57 + v_mad_u64_u32 v[46:47], s[22:23], s10, v56, 0 + v_add3_u32 v47, v47, v52, v48 + v_lshl_add_u64 v[46:47], v[46:47], 2, s[6:7] + v_lshl_add_u64 v[46:47], v[0:1], 2, v[46:47] + global_store_dword v[46:47], v49, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_104 +.LBB0_166: + v_mul_lo_u32 v48, s11, v4 + v_mul_lo_u32 v49, s10, v5 + v_mad_u64_u32 v[46:47], s[22:23], s10, v4, 0 + v_add3_u32 v47, v47, v49, v48 + v_lshl_add_u64 v[46:47], v[46:47], 2, s[6:7] + v_lshl_add_u64 v[46:47], v[0:1], 2, v[46:47] + global_store_dword v[46:47], v42, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_105 +.LBB0_167: + v_mul_lo_u32 v42, s11, v54 + v_mul_lo_u32 v48, s10, v55 + v_mad_u64_u32 v[46:47], s[22:23], s10, v54, 0 + v_add3_u32 v47, v47, v48, v42 + v_lshl_add_u64 v[46:47], v[46:47], 2, s[6:7] + v_lshl_add_u64 v[46:47], v[0:1], 2, v[46:47] + global_store_dword v[46:47], v43, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_106 +.LBB0_168: + v_mul_lo_u32 v46, s11, v50 + v_mul_lo_u32 v47, s10, v51 + v_mad_u64_u32 v[42:43], s[22:23], s10, v50, 0 + v_add3_u32 v43, v43, v47, v46 + v_lshl_add_u64 v[42:43], v[42:43], 2, s[6:7] + v_lshl_add_u64 v[42:43], v[0:1], 2, v[42:43] + global_store_dword v[42:43], v44, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_107 +.LBB0_169: + v_mul_lo_u32 v44, s11, v56 + v_mul_lo_u32 v46, s10, v57 + v_mad_u64_u32 v[42:43], s[22:23], s10, v56, 0 + v_add3_u32 v43, v43, v46, v44 + v_lshl_add_u64 v[42:43], v[42:43], 2, s[6:7] + v_lshl_add_u64 v[42:43], v[0:1], 2, v[42:43] + global_store_dword v[42:43], v45, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[20:21], s[12:13], s[4:5] + s_and_saveexec_b64 s[12:13], s[20:21] + s_cbranch_execz .LBB0_108 +.LBB0_170: + v_mul_lo_u32 v42, s11, v4 + v_mul_lo_u32 v43, s10, v5 + v_mad_u64_u32 v[4:5], s[20:21], s10, v4, 0 + v_add3_u32 v5, v5, v43, v42 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v38, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_109 +.LBB0_171: + v_mul_lo_u32 v38, s11, v54 + v_mul_lo_u32 v42, s10, v55 + v_mad_u64_u32 v[4:5], s[14:15], s10, v54, 0 + v_add3_u32 v5, v5, v42, v38 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v39, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_110 +.LBB0_172: + v_mul_lo_u32 v38, s11, v50 + v_mul_lo_u32 v39, s10, v51 + v_mad_u64_u32 v[4:5], s[14:15], s10, v50, 0 + v_add3_u32 v5, v5, v39, v38 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v40, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_111 + s_branch .LBB0_112 +.LBB0_173: + v_mul_lo_u32 v36, s11, v40 + v_mul_lo_u32 v44, s10, v41 + v_mad_u64_u32 v[42:43], s[22:23], s10, v40, 0 + v_add3_u32 v43, v43, v44, v36 + v_lshl_add_u64 v[42:43], v[42:43], 2, s[6:7] + v_lshl_add_u64 v[42:43], v[0:1], 2, v[42:43] + global_store_dword v[42:43], v37, off + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_120 +.LBB0_174: + v_mul_lo_u32 v42, s11, v4 + v_mul_lo_u32 v43, s10, v5 + v_mad_u64_u32 v[36:37], s[22:23], s10, v4, 0 + v_add3_u32 v37, v37, v43, v42 + v_lshl_add_u64 v[36:37], v[36:37], 2, s[6:7] + v_lshl_add_u64 v[36:37], v[0:1], 2, v[36:37] + global_store_dword v[36:37], v30, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_121 +.LBB0_175: + v_mul_lo_u32 v30, s11, v38 + v_mul_lo_u32 v42, s10, v39 + v_mad_u64_u32 v[36:37], s[22:23], s10, v38, 0 + v_add3_u32 v37, v37, v42, v30 + v_lshl_add_u64 v[36:37], v[36:37], 2, s[6:7] + v_lshl_add_u64 v[36:37], v[0:1], 2, v[36:37] + global_store_dword v[36:37], v31, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_122 +.LBB0_176: + v_mul_lo_u32 v36, s11, v34 + v_mul_lo_u32 v37, s10, v35 + v_mad_u64_u32 v[30:31], s[22:23], s10, v34, 0 + v_add3_u32 v31, v31, v37, v36 + v_lshl_add_u64 v[30:31], v[30:31], 2, s[6:7] + v_lshl_add_u64 v[30:31], v[0:1], 2, v[30:31] + global_store_dword v[30:31], v32, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[0:1] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_123 +.LBB0_177: + v_mul_lo_u32 v32, s11, v40 + v_mul_lo_u32 v36, s10, v41 + v_mad_u64_u32 v[30:31], s[22:23], s10, v40, 0 + v_add3_u32 v31, v31, v36, v32 + v_lshl_add_u64 v[30:31], v[30:31], 2, s[6:7] + v_lshl_add_u64 v[30:31], v[0:1], 2, v[30:31] + global_store_dword v[30:31], v33, off offset:64 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[12:13], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_124 +.LBB0_178: + v_mul_lo_u32 v32, s11, v4 + v_mul_lo_u32 v33, s10, v5 + v_mad_u64_u32 v[30:31], s[22:23], s10, v4, 0 + v_add3_u32 v31, v31, v33, v32 + v_lshl_add_u64 v[30:31], v[30:31], 2, s[6:7] + v_lshl_add_u64 v[30:31], v[0:1], 2, v[30:31] + global_store_dword v[30:31], v26, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[14:15], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_125 +.LBB0_179: + v_mul_lo_u32 v26, s11, v38 + v_mul_lo_u32 v32, s10, v39 + v_mad_u64_u32 v[30:31], s[22:23], s10, v38, 0 + v_add3_u32 v31, v31, v32, v26 + v_lshl_add_u64 v[30:31], v[30:31], 2, s[6:7] + v_lshl_add_u64 v[30:31], v[0:1], 2, v[30:31] + global_store_dword v[30:31], v27, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[16:17], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_126 +.LBB0_180: + v_mul_lo_u32 v30, s11, v34 + v_mul_lo_u32 v31, s10, v35 + v_mad_u64_u32 v[26:27], s[22:23], s10, v34, 0 + v_add3_u32 v27, v27, v31, v30 + v_lshl_add_u64 v[26:27], v[26:27], 2, s[6:7] + v_lshl_add_u64 v[26:27], v[0:1], 2, v[26:27] + global_store_dword v[26:27], v28, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[22:23], s[18:19], s[2:3] + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_127 +.LBB0_181: + v_mul_lo_u32 v28, s11, v40 + v_mul_lo_u32 v30, s10, v41 + v_mad_u64_u32 v[26:27], s[22:23], s10, v40, 0 + v_add3_u32 v27, v27, v30, v28 + v_lshl_add_u64 v[26:27], v[26:27], 2, s[6:7] + v_lshl_add_u64 v[26:27], v[0:1], 2, v[26:27] + global_store_dword v[26:27], v29, off offset:128 + s_or_b64 exec, exec, s[20:21] + s_and_b64 s[20:21], s[12:13], s[4:5] + s_and_saveexec_b64 s[12:13], s[20:21] + s_cbranch_execz .LBB0_128 +.LBB0_182: + v_mul_lo_u32 v26, s11, v4 + v_mul_lo_u32 v27, s10, v5 + v_mad_u64_u32 v[4:5], s[20:21], s10, v4, 0 + v_add3_u32 v5, v5, v27, v26 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v22, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[14:15], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_129 +.LBB0_183: + v_mul_lo_u32 v22, s11, v38 + v_mul_lo_u32 v26, s10, v39 + v_mad_u64_u32 v[4:5], s[14:15], s10, v38, 0 + v_add3_u32 v5, v5, v26, v22 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v23, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[16:17], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execz .LBB0_130 +.LBB0_184: + v_mul_lo_u32 v22, s11, v34 + v_mul_lo_u32 v23, s10, v35 + v_mad_u64_u32 v[4:5], s[14:15], s10, v34, 0 + v_add3_u32 v5, v5, v23, v22 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v24, off offset:192 + s_or_b64 exec, exec, s[12:13] + s_and_b64 s[14:15], s[18:19], s[4:5] + s_and_saveexec_b64 s[12:13], s[14:15] + s_cbranch_execnz .LBB0_131 + s_branch .LBB0_132 +.LBB0_185: + v_mul_lo_u32 v20, s11, v2 + v_mul_lo_u32 v26, s10, v3 + v_mad_u64_u32 v[24:25], s[20:21], s10, v2, 0 + v_add3_u32 v25, v25, v26, v20 + v_lshl_add_u64 v[24:25], v[24:25], 2, s[6:7] + v_lshl_add_u64 v[24:25], v[0:1], 2, v[24:25] + global_store_dword v[24:25], v21, off + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[12:13], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_140 +.LBB0_186: + v_mul_lo_u32 v24, s11, v4 + v_mul_lo_u32 v25, s10, v5 + v_mad_u64_u32 v[20:21], s[20:21], s10, v4, 0 + v_add3_u32 v21, v21, v25, v24 + v_lshl_add_u64 v[20:21], v[20:21], 2, s[6:7] + v_lshl_add_u64 v[20:21], v[0:1], 2, v[20:21] + global_store_dword v[20:21], v10, off offset:64 + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[14:15], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_141 +.LBB0_187: + v_mul_lo_u32 v10, s11, v22 + v_mul_lo_u32 v24, s10, v23 + v_mad_u64_u32 v[20:21], s[20:21], s10, v22, 0 + v_add3_u32 v21, v21, v24, v10 + v_lshl_add_u64 v[20:21], v[20:21], 2, s[6:7] + v_lshl_add_u64 v[20:21], v[0:1], 2, v[20:21] + global_store_dword v[20:21], v11, off offset:64 + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[20:21], s[16:17], s[0:1] + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_142 +.LBB0_188: + v_mul_lo_u32 v20, s11, v18 + v_mul_lo_u32 v21, s10, v19 + v_mad_u64_u32 v[10:11], s[20:21], s10, v18, 0 + v_add3_u32 v11, v11, v21, v20 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v12, off offset:64 + s_or_b64 exec, exec, s[18:19] + s_and_b64 s[18:19], s[8:9], s[0:1] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execz .LBB0_143 +.LBB0_189: + v_mul_lo_u32 v12, s11, v2 + v_mul_lo_u32 v20, s10, v3 + v_mad_u64_u32 v[10:11], s[18:19], s10, v2, 0 + v_add3_u32 v11, v11, v20, v12 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v13, off offset:64 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[12:13], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execz .LBB0_144 +.LBB0_190: + v_mul_lo_u32 v12, s11, v4 + v_mul_lo_u32 v13, s10, v5 + v_mad_u64_u32 v[10:11], s[18:19], s10, v4, 0 + v_add3_u32 v11, v11, v13, v12 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v14, off offset:128 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[14:15], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execz .LBB0_145 +.LBB0_191: + v_mul_lo_u32 v12, s11, v22 + v_mul_lo_u32 v13, s10, v23 + v_mad_u64_u32 v[10:11], s[18:19], s10, v22, 0 + v_add3_u32 v11, v11, v13, v12 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v15, off offset:128 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[18:19], s[16:17], s[2:3] + s_and_saveexec_b64 s[0:1], s[18:19] + s_cbranch_execz .LBB0_146 +.LBB0_192: + v_mul_lo_u32 v12, s11, v18 + v_mul_lo_u32 v13, s10, v19 + v_mad_u64_u32 v[10:11], s[18:19], s10, v18, 0 + v_add3_u32 v11, v11, v13, v12 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v16, off offset:128 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[8:9], s[2:3] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_147 +.LBB0_193: + v_mul_lo_u32 v12, s11, v2 + v_mul_lo_u32 v13, s10, v3 + v_mad_u64_u32 v[10:11], s[2:3], s10, v2, 0 + v_add3_u32 v11, v11, v13, v12 + v_lshl_add_u64 v[10:11], v[10:11], 2, s[6:7] + v_lshl_add_u64 v[10:11], v[0:1], 2, v[10:11] + global_store_dword v[10:11], v17, off offset:128 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[12:13], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_148 +.LBB0_194: + v_mul_lo_u32 v10, s11, v4 + v_mul_lo_u32 v11, s10, v5 + v_mad_u64_u32 v[4:5], s[2:3], s10, v4, 0 + v_add3_u32 v5, v5, v11, v10 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v6, off offset:192 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[14:15], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_149 +.LBB0_195: + v_mul_lo_u32 v6, s11, v22 + v_mul_lo_u32 v10, s10, v23 + v_mad_u64_u32 v[4:5], s[2:3], s10, v22, 0 + v_add3_u32 v5, v5, v10, v6 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v7, off offset:192 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[2:3], s[16:17], s[4:5] + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_150 +.LBB0_196: + v_mul_lo_u32 v6, s11, v18 + v_mul_lo_u32 v7, s10, v19 + v_mad_u64_u32 v[4:5], s[2:3], s10, v18, 0 + v_add3_u32 v5, v5, v7, v6 + v_lshl_add_u64 v[4:5], v[4:5], 2, s[6:7] + v_lshl_add_u64 v[4:5], v[0:1], 2, v[4:5] + global_store_dword v[4:5], v8, off offset:192 + s_or_b64 exec, exec, s[0:1] + s_and_b64 s[0:1], s[8:9], s[4:5] + s_and_saveexec_b64 s[2:3], s[0:1] + s_cbranch_execz .LBB0_151 +.LBB0_197: + v_mul_lo_u32 v4, s11, v2 + v_mul_lo_u32 v5, s10, v3 + v_mad_u64_u32 v[2:3], s[0:1], s10, v2, 0 + v_add3_u32 v3, v3, v5, v4 + v_lshl_add_u64 v[2:3], v[2:3], 2, s[6:7] + v_lshl_add_u64 v[0:1], v[0:1], 2, v[2:3] + global_store_dword v[0:1], v9, off offset:192 + s_endpgm + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel wave_bf16_gemm_256x256x64 + .amdhsa_group_segment_fixed_size 69632 + .amdhsa_private_segment_fixed_size 8 + .amdhsa_kernarg_size 48 + .amdhsa_user_sgpr_count 14 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 12 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 1 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 1 + .amdhsa_next_free_vgpr 128 + .amdhsa_next_free_sgpr 60 + .amdhsa_accum_offset 128 + .amdhsa_reserve_vcc 1 + .amdhsa_reserve_xnack_mask 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text +.Lfunc_end0: + .size wave_bf16_gemm_256x256x64, .Lfunc_end0-wave_bf16_gemm_256x256x64 + + .set wave_bf16_gemm_256x256x64.num_vgpr, 128 + .set wave_bf16_gemm_256x256x64.num_agpr, 0 + .set wave_bf16_gemm_256x256x64.numbered_sgpr, 60 + .set wave_bf16_gemm_256x256x64.num_named_barrier, 0 + .set wave_bf16_gemm_256x256x64.private_seg_size, 8 + .set wave_bf16_gemm_256x256x64.uses_vcc, 1 + .set wave_bf16_gemm_256x256x64.uses_flat_scratch, 0 + .set wave_bf16_gemm_256x256x64.has_dyn_sized_stack, 0 + .set wave_bf16_gemm_256x256x64.has_recursion, 0 + .set wave_bf16_gemm_256x256x64.has_indirect_call, 0 + .p2alignl 6, 3212836864 + .fill 256, 4, 3212836864 + .section .AMDGPU.gpr_maximums,"",@progbits + .set amdgpu.max_num_vgpr, 0 + .set amdgpu.max_num_agpr, 0 + .set amdgpu.max_num_sgpr, 0 + .set amdgpu.max_num_named_barrier, 0 + .text + .section ".note.GNU-stack","",@progbits + .amdgpu_metadata +--- +amdhsa.kernels: + - .agpr_count: 0 + .args: + - .actual_access: read_only + .address_space: generic + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .actual_access: read_only + .address_space: generic + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .actual_access: write_only + .address_space: generic + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .offset: 24 + .size: 4 + .value_kind: by_value + - .offset: 28 + .size: 4 + .value_kind: by_value + - .offset: 32 + .size: 4 + .value_kind: by_value + - .offset: 36 + .size: 4 + .value_kind: by_value + - .offset: 40 + .size: 4 + .value_kind: by_value + - .offset: 44 + .size: 4 + .value_kind: by_value + .group_segment_fixed_size: 69632 + .kernarg_segment_align: 8 + .kernarg_segment_size: 48 + .max_flat_workgroup_size: 1024 + .name: wave_bf16_gemm_256x256x64 + .private_segment_fixed_size: 8 + .reqd_workgroup_size: + - 256 + - 4 + - 1 + .sgpr_count: 66 + .sgpr_spill_count: 0 + .symbol: wave_bf16_gemm_256x256x64.kd + .uniform_work_group_size: 1 + .uses_dynamic_stack: false + .vgpr_count: 128 + .vgpr_spill_count: 1 + .wavefront_size: 64 +amdhsa.target: amdgcn-amd-amdhsa--gfx950 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml new file mode 100644 index 000000000000..6ce94f319071 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml @@ -0,0 +1,98 @@ +TestParameters: + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + DeviceLDS: 163840 + MaxLDS: 163840 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: b + DestDataType: s + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + + - # BenchmarkProblemSizeGroup + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "wave_bf16_gemm_256x256x64" + args: [ { type: address, semantic: AddressB }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressD }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: SizeSum }, + { type: uint32, semantic: Padding } ] + macrotile: [256, 256, 64] + threads: [256, 4, 1] + grid: [TilesY, TilesX, One] + - MatrixInstruction: + - [16, 16, 32, 1, 1, 4, 4, 4, 4] + - PreloadKernArgs: [False] + - DepthU: [64] + - VectorWidthA: [-1] + - VectorWidthB: [-1] + - GlobalReadVectorWidthA: [-1] + - GlobalReadVectorWidthB: [-1] + - LocalReadVectorWidth: [-1] + - TransposeLDS: [-1] + - LdsBlockSizePerPadA: [-1] + - LdsBlockSizePerPadB: [-1] + - LdsPadA: [-1] + - LdsPadB: [-1] + - StaggerU: [16] + - StaggerUStride: [-1] + - WorkGroupMapping: [1] + - StaggerUMapping: [0] + - 1LDSBuffer: [-1] + - WorkGroupMappingXCC: [8] + - WorkGroupMappingXCCGroup: [-1] + - GlobalSplitU: [1] + - GlobalSplitUAlgorithm: ["MultipleBuffer"] + - GlobalReadPerMfma: [1] + - LocalWritePerMfma: [-1] + - StoreRemapVectorWidth: [0] + - StoreVectorWidth: [-1] + - SourceSwap: [1] + - NumElementsPerBatchStore: [16] + - ClusterLocalRead: [1] + - NonTemporalA: [0] + - NonTemporalB: [0] + - DirectToVgprA: [1] + - DirectToVgprB: [0] + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + - Exact: [4096, 4096, 1, 4096] + +LibraryLogic: + ScheduleName: "gfx950" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx950" + LibraryType: "GridBased" From 9ae272890e2bd4b444a98e8f602787f6e878bbab Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Tue, 7 Apr 2026 12:35:32 -0700 Subject: [PATCH 22/58] [hipblaslt][G-F-A] fix MFMA_BF16_1K KeyError of install build (#6217) Fix `KeyError: 'MFMA_BF16_1K'` when building install.sh --- projects/hipblaslt/tensilelite/Tensile/CustomKernels.py | 4 +++- projects/hipblaslt/tensilelite/Tensile/KernelWriter.py | 2 +- .../hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py | 4 ++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index f87131b0203c..56be72dba9c8 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -30,7 +30,9 @@ import os def isCustomKernelConfig(config): - return "CustomKernel" in config and config["CustomKernel"]["name"] + if "CustomKernel" in config and config["CustomKernel"]["name"]: + return True + return bool(config.get("CustomKernelName", "")) def getCustomKernelFilepath(name, directory=CUSTOM_KERNEL_PATH): flat = os.path.join(directory, (name + ".s")) diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py index cdc092a2c051..4e8b4ba85d81 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py @@ -4743,7 +4743,7 @@ def readWriteVectors(mat, vw, kernel): elif not ( self.states.asmCaps["HasMFMA"] or self.states.asmCaps["HasWMMA"]): raise RuntimeError("MatrixInstruction not supported for {0}".format(self.states.version)) - if kernel["MFMA_BF16_1K"] and not self.states.asmCaps["HasMFMA_bf16_1k"]: + if kernel.get("MFMA_BF16_1K") and not self.states.asmCaps["HasMFMA_bf16_1k"]: raise RuntimeError("BF16_1k MatrixInstruction not supported for {0}".format(self.states.version)) if kernel["ProblemType"]["Sparse"] and not self.states.asmCaps["HasSMFMA"]: diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py index 98dd136b06ac..be31df7cceba 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py @@ -97,6 +97,8 @@ def _getName(state, requiredParameters: frozenset, splitGSU: bool, ignoreInterna if "CustomKernel" in state and state["CustomKernel"]["name"]: return state["CustomKernel"]["name"] + if state.get("CustomKernelName", ""): + return state["CustomKernelName"] gsuBackup = state["GlobalSplitU"] ggBackup = state["ProblemType"]["GroupedGemm"] @@ -171,6 +173,8 @@ def shortenFileBase(splitGSU, kernel): def getKernelFileBase(splitGSU: bool, kernel): if "CustomKernel" in kernel and kernel["CustomKernel"]["name"]: fileBase = kernel["CustomKernel"]["name"] + elif kernel.get("CustomKernelName", ""): + fileBase = kernel["CustomKernelName"] else: fileBase = shortenFileBase(splitGSU, kernel) return fileBase From 9105a661be7189443698d31ecf5c681f4791094e Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Tue, 7 Apr 2026 19:06:12 -0700 Subject: [PATCH 23/58] [hipblaslt][G-F-A] fix rr demo yaml (#6238) --- .../hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index 017c3258e25d..0f1c584e8a91 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -58,6 +58,9 @@ BenchmarkProblems: { type: int64, semantic: StrideD0 }, { type: int64, semantic: StrideD1 }, { type: address, semantic: AddressD } ] + macrotile: [64, 64, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, Batch] - MatrixInstruction: - [16,16,16, 1, 1, 2,2, 2,2] # 256 x 128 - PreloadKernArgs: [False] From b36aa100a78846a8d8933318ec5e5bc6a24bac17 Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 8 Apr 2026 22:57:35 -0700 Subject: [PATCH 24/58] [hipblaslt] fix gemm_ck_gfx942 test (#6301) --- projects/hipblaslt/tensilelite/Tensile/CustomKernels.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 56be72dba9c8..1c6c432f4452 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -114,6 +114,9 @@ def getCustomKernelConfig( checkParametersAreValid((k, [v]), validParameters) kernelConfig["KernelLanguage"] = "Assembly" - kernelConfig["CustomKernel"]["name"] = kernelName + if "CustomKernel" in kernelConfig: + kernelConfig["CustomKernel"]["name"] = kernelName + else: + kernelConfig["CustomKernelName"] = kernelName return kernelConfig From 6d5e1bd0f0a847dd9746c5a21f93e010eb95bbb5 Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Wed, 22 Apr 2026 16:06:20 +0000 Subject: [PATCH 25/58] Make it easier to add new semantics --- .../include/Tensile/ContractionSolution.hpp | 61 ++++---- .../include/Tensile/Serialization/Base.hpp | 2 +- .../tensilelite/src/ContractionSolution.cpp | 136 +++--------------- 3 files changed, 52 insertions(+), 147 deletions(-) diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 422826f47466..657c849dd49d 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -50,35 +50,40 @@ namespace TensileLite { - enum CustomArgSemantic + #define CustomArgSemantic_MACRO \ + X_MACRO(SizeFree0) \ + X_MACRO(SizeFree1) \ + X_MACRO(SizeFree2) \ + X_MACRO(SizeSum) \ + X_MACRO(AddressA) \ + X_MACRO(AddressB) \ + X_MACRO(AddressC) \ + X_MACRO(AddressD) \ + X_MACRO(StrideA0) \ + X_MACRO(StrideA1) \ + X_MACRO(StrideB0) \ + X_MACRO(StrideB1) \ + X_MACRO(StrideC0) \ + X_MACRO(StrideC1) \ + X_MACRO(StrideD0) \ + X_MACRO(StrideD1) \ + X_MACRO(Alpha) \ + X_MACRO(Beta) \ + X_MACRO(SplitK) \ + X_MACRO(OutputBF16) \ + X_MACRO(StrideA0Bytes) \ + X_MACRO(StrideB0Bytes) \ + X_MACRO(StrideC0Bytes) \ + X_MACRO(StrideD0Bytes) \ + X_MACRO(Padding) \ + X_MACRO(DebugPattern) + + enum class CustomArgSemantic { - SizeFree0, // 0 - SizeFree1, // 1 - SizeFree2, // 2 - SizeSum, // 3 - AddressA, // 4 - AddressB, // 5 - AddressC, // 6 - AddressD, // 7 - StrideA0, // 8 - StrideA1, // 9 - StrideB0, // 10 - StrideB1, // 11 - StrideC0, // 12 - StrideC1, // 13 - StrideD0, // 14 - StrideD1, // 15 - Alpha, // 16 - Beta, // 17 - SplitK, // 18 - OutputBF16, // 19 - StrideA0Bytes, // 20 - StrideB0Bytes, // 21 - StrideC0Bytes, // 22 - StrideD0Bytes, // 23 - Padding, // 24 - DebugPattern, // 25 - CustomArgSemantic_Count, // 26 + #define X_MACRO(name) name, + CustomArgSemantic_MACRO + #undef X_MACRO + COUNT, }; std::string toString(CustomArgSemantic arg); diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index 5a6d44775797..d60222736e1a 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -389,7 +389,7 @@ namespace TensileLite static void enumeration(IO& io, CustomArgSemantic& value) { - for(int i = 0; i < static_cast(CustomArgSemantic::CustomArgSemantic_Count); i++) + for(int i = 0; i < static_cast(CustomArgSemantic::COUNT); i++) { auto const& info = static_cast(i); iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index ca7b134dda2e..f9a07672e7dc 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -55,126 +55,26 @@ namespace TensileLite { std::string toString(CustomArgSemantic arg) { - switch(arg) - { - case CustomArgSemantic::SizeFree0: - return "SizeFree0"; - case CustomArgSemantic::SizeFree1: - return "SizeFree1"; - case CustomArgSemantic::SizeFree2: - return "SizeFree2"; - case CustomArgSemantic::SizeSum: - return "SizeSum"; - case CustomArgSemantic::AddressA: - return "AddressA"; - case CustomArgSemantic::AddressB: - return "AddressB"; - case CustomArgSemantic::AddressC: - return "AddressC"; - case CustomArgSemantic::AddressD: - return "AddressD"; - case CustomArgSemantic::StrideA0: - return "StrideA0"; - case CustomArgSemantic::StrideA1: - return "StrideA1"; - case CustomArgSemantic::StrideB0: - return "StrideB0"; - case CustomArgSemantic::StrideB1: - return "StrideB1"; - case CustomArgSemantic::StrideC0: - return "StrideC0"; - case CustomArgSemantic::StrideC1: - return "StrideC1"; - case CustomArgSemantic::StrideD0: - return "StrideD0"; - case CustomArgSemantic::StrideD1: - return "StrideD1"; - case CustomArgSemantic::Alpha: - return "Alpha"; - case CustomArgSemantic::Beta: - return "Beta"; - case CustomArgSemantic::SplitK: - return "SplitK"; - case CustomArgSemantic::OutputBF16: - return "OutputBF16"; - case CustomArgSemantic::StrideA0Bytes: - return "StrideA0Bytes"; - case CustomArgSemantic::StrideB0Bytes: - return "StrideB0Bytes"; - case CustomArgSemantic::StrideC0Bytes: - return "StrideC0Bytes"; - case CustomArgSemantic::StrideD0Bytes: - return "StrideD0Bytes"; - case CustomArgSemantic::Padding: - return "Padding"; - case CustomArgSemantic::DebugPattern: - return "DebugPattern"; - case CustomArgSemantic::CustomArgSemantic_Count: - break; - } - - throw std::runtime_error( - concatenate("Invalid CustomArgSemantic value: ", static_cast(arg))); + static const std::array(CustomArgSemantic::COUNT)> CustomArgSemanticStrings = { + #define X_MACRO(name) TENSILELITE_TO_STR(name), + CustomArgSemantic_MACRO + #undef X_MACRO + }; + return CustomArgSemanticStrings[static_cast(arg)]; } - + CustomArgSemantic fromStringCustomArgSemantic(std::string& str) { + static const std::map CustomArgSemanticMap = { + #define X_MACRO(name) {TENSILELITE_TO_STR(name), CustomArgSemantic::name}, + CustomArgSemantic_MACRO + #undef X_MACRO + }; - if(str == toString(CustomArgSemantic::SizeFree0)) - return CustomArgSemantic::SizeFree0; - else if(str == toString(CustomArgSemantic::SizeFree1)) - return CustomArgSemantic::SizeFree1; - else if(str == toString(CustomArgSemantic::SizeFree2)) - return CustomArgSemantic::SizeFree2; - else if(str == toString(CustomArgSemantic::SizeSum)) - return CustomArgSemantic::SizeSum; - else if(str == toString(CustomArgSemantic::AddressA)) - return CustomArgSemantic::AddressA; - else if(str == toString(CustomArgSemantic::AddressB)) - return CustomArgSemantic::AddressB; - else if(str == toString(CustomArgSemantic::AddressC)) - return CustomArgSemantic::AddressC; - else if(str == toString(CustomArgSemantic::AddressD)) - return CustomArgSemantic::AddressD; - else if(str == toString(CustomArgSemantic::StrideA0)) - return CustomArgSemantic::StrideA0; - else if(str == toString(CustomArgSemantic::StrideA1)) - return CustomArgSemantic::StrideA1; - else if(str == toString(CustomArgSemantic::StrideB0)) - return CustomArgSemantic::StrideB0; - else if(str == toString(CustomArgSemantic::StrideB1)) - return CustomArgSemantic::StrideB1; - else if(str == toString(CustomArgSemantic::StrideC0)) - return CustomArgSemantic::StrideC0; - else if(str == toString(CustomArgSemantic::StrideC1)) - return CustomArgSemantic::StrideC1; - else if(str == toString(CustomArgSemantic::StrideD0)) - return CustomArgSemantic::StrideD0; - else if(str == toString(CustomArgSemantic::StrideD1)) - return CustomArgSemantic::StrideD1; - else if(str == toString(CustomArgSemantic::Alpha)) - return CustomArgSemantic::Alpha; - else if(str == toString(CustomArgSemantic::Beta)) - return CustomArgSemantic::Beta; - else if(str == toString(CustomArgSemantic::SplitK)) - return CustomArgSemantic::SplitK; - else if(str == toString(CustomArgSemantic::OutputBF16)) - return CustomArgSemantic::OutputBF16; - else if(str == toString(CustomArgSemantic::StrideA0Bytes)) - return CustomArgSemantic::StrideA0Bytes; - else if(str == toString(CustomArgSemantic::StrideB0Bytes)) - return CustomArgSemantic::StrideB0Bytes; - else if(str == toString(CustomArgSemantic::StrideC0Bytes)) - return CustomArgSemantic::StrideC0Bytes; - else if(str == toString(CustomArgSemantic::StrideD0Bytes)) - return CustomArgSemantic::StrideD0Bytes; - else if(str == toString(CustomArgSemantic::Padding)) - return CustomArgSemantic::Padding; - else if(str == toString(CustomArgSemantic::DebugPattern)) - return CustomArgSemantic::DebugPattern; - else - throw std::runtime_error(concatenate("Invalid argument type: ", str)); - return CustomArgSemantic::CustomArgSemantic_Count; + auto it = CustomArgSemanticMap.find(str); + if (it == CustomArgSemanticMap.end()) + throw std::runtime_error(concatenate("Invalid CustomArgSemantic value: ", str)); + return it->second; } std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t) @@ -1001,7 +901,7 @@ namespace TensileLite // then no Stream-K tiles are needed, all data-parallel uint32_t skTiles = sk.grid; // If not evenly divisible, determine number of Stream-K tiles - if(tiles % sk.grid != 0) + if(tiles % sk.grid != 0) { // Number of data-parallel tiles on each workgroup would be: // dpTilesPerWG = bigEnough ? (tiles - skTiles) / skGrid : 0; @@ -2160,7 +2060,7 @@ namespace TensileLite rv.numWorkItems.x / rv.workGroupSize.x / rv.workGroupSize.y / rv.workGroupSize.z); kernelArgs(0, - (uint32_t)KERNELARGTYPE::NORMAL, + (uint32_t)KERNELARGTYPE::NORMAL, rv.args, 0, &hardware, From b56bd25cfbfc4011fd2f214fb9dad77cc88bc699 Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 29 Apr 2026 09:51:47 -0700 Subject: [PATCH 26/58] [hipblaslt][G-F-A] Demo calling aiter mxfp4 kernel (#6516) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Integrate AITER's FP4 GEMM custom kernel into TensileLite by adding MX scale argument semantics (`AddressScaleA/B`, `StrideScaleA0/A1/B0/B1`) to the custom kernel framework and creating test configuration - Enable the existing `SwizzleTensorA` mechanism for the FP4 kernel's pre-shuffled B data requirement. The kernel expects `BpreShuffle` layout, and due to `SourceSwap: 1`, Tensile's A tensor feeds the kernel's direct-to-VGPR path — so `SwizzleTensorA: True` applies the 5D swizzle (pad, reshape, permute) on the host side to match the kernel's expected data layout - Implement macrotile padding in the Python benchmark layer so custom kernels (which lack edge-tile bounds checking) can handle arbitrary problem sizes by rounding M/N up to macrotile boundaries with adjusted strides - Add slice-back validation so the client only checks the original M x N sub-region of the padded output, and report original (unpadded) problem sizes in the CSV so post-processing in `LibraryLogic.py` matches the YAML Tensile log: https://gist.github.com/jinchen62/f5ce775bc85d5e4866c2f30773448ff8 --- projects/hipblaslt/tensilelite/CMakeLists.txt | 10 + .../tensilelite/Tensile/BenchmarkProblems.py | 18 +- .../tensilelite/Tensile/ClientWriter.py | 36 +- .../Tensile/Common/ValidParameters.py | 1 + ...emm_bf16_per1x32Fp4_BpreShuffle_256x256E.s | 3894 +++++++++++++++++ .../Tensile/SolutionStructs/Problem.py | 2 + .../Tests/custom/custom_aiter_bf16.yaml | 14 +- .../Tensile/Tests/custom/custom_aiter_f4.yaml | 118 + .../tensilelite/client/CMakeLists.txt | 12 +- .../client/include/DataInitialization.hpp | 4 +- .../client/include/ProgressListener.hpp | 3 + .../client/include/ReferenceValidator.hpp | 3 + .../tensilelite/client/include/TypedId.hpp | 3 + .../hipblaslt/tensilelite/client/main.cpp | 6 + .../tensilelite/client/src/CMakeLists.txt | 11 + .../client/src/DataInitialization.cpp | 84 +- .../client/src/ProgressListener.cpp | 28 +- .../tensilelite/client/src/Reference.cpp | 7 + .../client/src/ReferenceValidator.cpp | 64 +- .../include/Tensile/ContractionSolution.hpp | 16 +- .../tensilelite/src/ContractionSolution.cpp | 71 +- .../hipblaslt/tensilelite/src/DataTypes.cpp | 4 +- 22 files changed, 4330 insertions(+), 79 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml diff --git a/projects/hipblaslt/tensilelite/CMakeLists.txt b/projects/hipblaslt/tensilelite/CMakeLists.txt index 8d631455a3dd..7d708995eeac 100644 --- a/projects/hipblaslt/tensilelite/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/CMakeLists.txt @@ -44,12 +44,22 @@ if(TENSILELITE_ENABLE_HOST) "${CMAKE_CURRENT_BINARY_DIR}/include" ) + if(NOT TARGET roc::mxDataGenerator) + if(HIPBLASLT_ENABLE_THEROCK) + find_package(mxDataGenerator REQUIRED) + else() + add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/../../../shared/mxdatagenerator" + "${CMAKE_CURRENT_BINARY_DIR}/mxdatagenerator") + endif() + endif() + target_link_libraries(tensilelite-host PUBLIC $ roc::origami PRIVATE hip::device + roc::mxDataGenerator ) add_subdirectory(src) diff --git a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py index b0570fa6b3f7..670c680bdc35 100644 --- a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py +++ b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py @@ -305,6 +305,18 @@ def writeBenchmarkFiles( for f in codeObjectFiles] with timing_context("python_benchpost_client_config"): + # If the custom kernel declares padProblemSizeToTile, extract + # the macrotile dims and per-axis flags so problemSizeParams() + # can pad M/N to tile boundaries. + macroTile = None + for sol in solutions: + if "CustomKernel" in sol and sol["CustomKernel"]: + ck = sol["CustomKernel"] + padFlags = ck.get("padProblemSizeToTile", None) + if padFlags: + macroTile = (sol["MacroTile0"], sol["MacroTile1"], padFlags) + break + if "TileAwareSelection" in problemType and problemType["TileAwareSelection"]: maxMacroTile0 = 0 maxMacroTile1 = 0 @@ -330,12 +342,14 @@ def writeBenchmarkFiles( writeClientConfig(True, solutions, idealProblemSizes, biasTypeArgs, \ factorDimArgs, activationArgs, icacheFlushArgs, stepName, stepBaseDir, \ newLibrary, codeObjectFiles, True, deviceId, gfxName, \ - libraryFile=newLibraryFileFull, probSolMap=probSolMap) + libraryFile=newLibraryFileFull, probSolMap=probSolMap, + macroTile=macroTile) else: writeClientConfig(True, solutions, problemSizes, biasTypeArgs, \ factorDimArgs, activationArgs, icacheFlushArgs, stepName, stepBaseDir, \ newLibrary, codeObjectFiles, False, deviceId, gfxName, \ - libraryFile=newLibraryFileFull, probSolMap=probSolMap) + libraryFile=newLibraryFileFull, probSolMap=probSolMap, + macroTile=macroTile) if len(solutions) == 0: printExit("write solutions and kernels results 0 valid soultion.") diff --git a/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py b/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py index 52b36529edc8..50e212813544 100644 --- a/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py @@ -394,7 +394,10 @@ def checkConstStride(constStrideMap, keyIdx): return finalVal -def problemSizeParams(problemType, problem, factorDim): +def _ceilTo(val, multiple): + return ((val + multiple - 1) // multiple) * multiple + +def problemSizeParams(problemType, problem, factorDim, macroTile=None): numIndices = len(problemType.indices) rv = [] @@ -461,8 +464,28 @@ def problemSizeParams(problemType, problem, factorDim): "Invalid number of problem type indices: {0} - Indices: {1}, problemSize: {2}".format(len(problem.sizes), numIndices, ', '.join(map(str, problem.sizes)))) - problemSizeArg = ('problem-size', ','.join(map(str, problem.sizes[:numIndices]))) + sizes = list(problem.sizes[:numIndices]) + originalSizes = None + # When a custom kernel declares padProblemSizeToTile: [padM, padN], + # pad the requested dimensions to macrotile boundaries. Save the + # original sizes so the client can report/validate the unpadded region. + if macroTile is not None: + mt0, mt1, padFlags = macroTile + padM = _ceilTo(sizes[0], mt0) if padFlags[0] else sizes[0] + padN = _ceilTo(sizes[1], mt1) if padFlags[1] else sizes[1] + if padM != sizes[0] or padN != sizes[1]: + originalSizes = list(sizes) + sizes[0] = padM + sizes[1] = padN + if cstrides and cstrides[1] != -1: + cstrides[1] = max(cstrides[1], padM) + if dstrides and dstrides[1] != -1: + dstrides[1] = max(dstrides[1], padM) + + problemSizeArg = ('problem-size', ','.join(map(str, sizes))) rv.insert(0, problemSizeArg) + if originalSizes is not None: + rv.append(('original-problem-size', ','.join(map(str, originalSizes)))) rv.append(('a-strides', ",".join(map(str, astrides)))) rv.append(('b-strides', ",".join(map(str, bstrides)))) @@ -551,7 +574,7 @@ def pruneModeName(mode): if mode == 5: return 'Prune0X0X' if mode == 6: return 'Prune00XX' -def writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, problemType, sourceDir, codeObjectFiles, resultsFileName, parametersFilePath, deviceId: int, gfxName: str, libraryFile=None, probSolMap={}): +def writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, problemType, sourceDir, codeObjectFiles, resultsFileName, parametersFilePath, deviceId: int, gfxName: str, libraryFile=None, probSolMap={}, macroTile=None): assert os.path.exists(sourceDir), f"sourceDir={sourceDir} does not exist" @@ -622,7 +645,7 @@ def param(key, value): probIdx = 0 for problem in problemSizes.problems: - for key,value in problemSizeParams(problemType, problem, factorDimArgs.factorDims): + for key,value in problemSizeParams(problemType, problem, factorDimArgs.factorDims, macroTile): param(key,value) if probIdx in probSolMap: solutionIdx = probSolMap[probIdx] @@ -729,7 +752,8 @@ def writeClientConfig( gfxName: str, configBase = "ClientParameters", libraryFile = None, - probSolMap = {} + probSolMap = {}, + macroTile = None ): sourceDir = os.path.join(stepBaseDir, "source") @@ -749,7 +773,7 @@ def writeClientConfig( resultsFileName = os.path.join(stepBaseDir, "../Data", stepName+".csv") newSolution = next(iter(newLibrary.solutions.values())) - writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, newSolution.problemType, sourceDir, codeObjectFiles, resultsFileName, filename, deviceId, gfxName, libraryFile, probSolMap) + writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, newSolution.problemType, sourceDir, codeObjectFiles, resultsFileName, filename, deviceId, gfxName, libraryFile, probSolMap, macroTile) return filename diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py index eb0729476dc3..b4689976db8a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py @@ -119,6 +119,7 @@ def makeValidMFMA(): validMFMA["B8"] = validMFMA["F8"] validMFMA["F8B8"] = validMFMA["F8"] validMFMA["B8F8"] = validMFMA["F8"] + validMFMA["F4"] = [[32, 32, 64, 1], [16, 16, 128, 1]] validMFMA["F8N"] = [[32, 32, 16, 1], [16, 16, 32, 1]] validMFMA["B8N"] = validMFMA["F8N"] validMFMA["F8B8N"] = validMFMA["F8N"] diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s new file mode 100644 index 000000000000..8ba6f9e65413 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s @@ -0,0 +1,3894 @@ +// Auto-generated from f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256.co +// This file can be reassembled with: +// clang -x assembler -target amdgcn-amd-amdhsa -mcpu=gfx950 -c file.s -o file.o +// ld.lld -shared -o file.co file.o + +// Note: Target is specified via -mcpu= command line flag + +.set .amdgcn.next_free_vgpr, 0 +.set .amdgcn.next_free_sgpr, 0 + +// ===== Kernel Code ===== +.text +.globl _ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E +.p2align 8 +.type _ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E,@function + +_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E: + + s_and_b32 s1, s1, 0xffff + s_mov_b32 s56, s4 + s_load_dwordx2 s[4:5], s[0:1], 0x0 + s_load_dwordx2 s[8:9], s[0:1], 0x10 + s_load_dwordx2 s[12:13], s[0:1], 0x20 + s_load_dwordx2 s[16:17], s[0:1], 0x30 + s_load_dword s38, s[0:1], 0x40 + s_load_dword s39, s[0:1], 0x50 + s_load_dword s40, s[0:1], 0x80 + s_load_dword s41, s[0:1], 0xa0 + s_load_dword s42, s[0:1], 0xc0 + s_load_dword s43, s[0:1], 0xe0 + s_load_dword s44, s[0:1], 0xf0 + s_load_dword s45, s[0:1], 0x100 + s_load_dwordx2 s[20:21], s[0:1], 0x110 + s_load_dwordx2 s[24:25], s[0:1], 0x120 + s_load_dword s36, s[0:1], 0x130 + s_load_dword s37, s[0:1], 0x150 + s_load_dword s57, s[0:1], 0x170 + v_lshrrev_b32_e32 v1, 10, v0 + v_lshrrev_b32_e32 v2, 10, v1 + v_and_b32_e32 v2, 0x3ff, v2 + v_and_b32_e32 v1, 0x3ff, v1 + v_and_b32_e32 v0, 0x3ff, v0 + v_lshrrev_b32_e32 v3, 6, v0 + v_and_b32_e32 v0, 63, v0 + s_mov_b32 s46, s2 + s_mov_b32 s47, s3 + v_readfirstlane_b32 s49, v3 + s_waitcnt lgkmcnt(0) + s_add_u32 s55, s44, 0xff + s_lshr_b32 s54, s55, 8 + s_mul_i32 s48, s54, s47 + s_add_i32 s48, s48, s46 + s_add_u32 s55, s43, 0xff + s_lshr_b32 s52, s55, 8 + s_lshl_b32 s52, s52, 5 + s_mov_b32 s46, 0 + +label_003D: + s_cmp_lt_i32 s48, s52 + s_cbranch_scc1 label_0042 + s_sub_i32 s48, s48, s52 + s_add_i32 s46, s46, 32 + s_branch label_003D + +label_0042: + s_sub_i32 s54, s54, s46 + s_cmp_lt_i32 s54, 32 + s_cbranch_scc1 label_0048 + s_lshr_b32 s47, s48, 5 + s_and_b32 s52, s48, 31 + s_branch label_0068 + +label_0048: + v_cvt_f32_u32_e32 v4, s54 + s_sub_i32 s47, 0, s54 + v_rcp_iflag_f32_e32 v4, v4 + s_nop 0 + v_mul_f32_e32 v4, 0x4f7ffffe, v4 + v_cvt_u32_f32_e32 v4, v4 + v_mul_lo_u32 v5, s47, v4 + v_mul_hi_u32 v5, v4, v5 + v_add_u32_e32 v4, v4, v5 + v_mul_hi_u32 v4, s48, v4 + v_mul_lo_u32 v5, v4, s54 + v_sub_u32_e32 v7, s48, v5 + v_add_u32_e32 v6, 1, v4 + v_cmp_le_u32_e32 vcc, s54, v7 + v_subrev_u32_e32 v5, s54, v7 + s_nop 0 + v_cndmask_b32_e32 v4, v4, v6, vcc + v_cndmask_b32_e32 v7, v7, v5, vcc + v_add_u32_e32 v5, 1, v4 + v_cmp_le_u32_e32 vcc, s54, v7 + s_nop 1 + v_cndmask_b32_e32 v7, v4, v5, vcc + s_nop 3 + v_readfirstlane_b32 s47, v7 + s_nop 3 + s_mul_i32 s52, s54, s47 + s_sub_i32 s52, s48, s52 + +label_0068: + s_add_i32 s46, s52, s46 + s_mov_b32 s6, -16 + s_mov_b32 s10, -16 + s_mov_b32 s18, -16 + s_mov_b32 s14, -16 + s_mov_b32 s7, 0x20000 + s_mov_b32 s11, 0x20000 + s_mov_b32 s19, 0x20000 + s_mov_b32 s15, 0x20000 + s_and_b32 s5, s5, 0xffff + s_and_b32 s9, s9, 0xffff + s_and_b32 s17, s17, 0xffff + s_and_b32 s13, s13, 0xffff + s_or_b32 s5, s5, 0x40000 + s_or_b32 s9, s9, 0x40000 + s_or_b32 s17, s17, 0x40000 + s_or_b32 s13, s13, 0x40000 + s_cmp_gt_u32 s57, 0 + s_cbranch_scc0 label_0090 + s_lshr_b32 s58, s45, s57 + s_add_u32 s58, s58, 0xff + s_lshr_b32 s58, s58, 8 + s_lshl_b32 s58, s58, 8 + s_mul_i32 s53, s58, s56 + s_sub_i32 s52, s45, s53 + s_cmp_lt_i32 s52, s58 + s_cselect_b32 s45, s52, s58 + +label_0090: + s_lshr_b32 s41, s41, 1 + s_mul_i32 s52, s41, s43 + s_mov_b32 s14, s52 + s_cmp_gt_u32 s57, 0 + s_cbranch_scc0 label_009A + s_mul_i32 s53, s58, s56 + s_lshr_b32 s52, s53, 1 + s_add_u32 s12, s12, s52 + s_addc_u32 s13, s13, 0 + s_sub_u32 s14, s14, s52 + +label_009A: + s_lshr_b32 s42, s42, 1 + s_mul_i32 s52, s42, s44 + s_mov_b32 s18, s52 + s_add_u32 s52, s43, 31 + s_lshr_b32 s52, s52, 5 + s_lshl_b32 s52, s52, 5 + s_mul_i32 s53, s52, s36 + s_mov_b32 s22, s53 + s_mul_i32 s53, s44, s37 + s_mov_b32 s26, s53 + s_mov_b32 s23, 0x20000 + s_mov_b32 s27, 0x20000 + s_and_b32 s21, s21, 0xffff + s_and_b32 s25, s25, 0xffff + s_or_b32 s21, s21, 0x40000 + s_or_b32 s25, s25, 0x40000 + v_lshrrev_b32_e32 v4, 3, v0 + v_lshrrev_b32_e32 v5, 2, v4 + v_lshlrev_b32_e32 v5, 4, v5 + v_and_b32_e32 v4, 3, v4 + v_lshrrev_b32_e32 v6, 1, v4 + v_lshlrev_b32_e32 v6, 2, v6 + v_add_u32_e32 v5, v5, v6 + v_and_b32_e32 v4, 1, v4 + v_add_u32_e32 v5, v5, v4 + v_mul_lo_u32 v212, s41, v5 + v_and_b32_e32 v4, 7, v0 + v_lshlrev_b32_e32 v4, 4, v4 + v_add_u32_e32 v212, v212, v4 + s_lshr_b32 s52, s49, 1 + s_mul_i32 s52, s52, 8 + s_and_b32 s53, s49, 1 + s_mul_i32 s53, s53, 2 + s_add_u32 s52, s52, s53 + s_mul_i32 s53, s47, 0x100 + s_add_u32 s52, s52, s53 + s_mul_i32 s52, s41, s52 + v_add_u32_e32 v212, s52, v212 + s_mul_i32 s52, s41, 32 + v_add_u32_e32 v213, s52, v212 + v_add_u32_e32 v214, s52, v213 + v_add_u32_e32 v215, s52, v214 + v_add_u32_e32 v216, s52, v215 + v_add_u32_e32 v217, s52, v216 + v_add_u32_e32 v218, s52, v217 + v_add_u32_e32 v219, s52, v218 + s_mul_i32 s59, 0x420, s49 + s_add_u32 s59, 0x1000, s59 + v_and_b32_e32 v4, 15, v0 + v_lshrrev_b32_e32 v5, 3, v4 + v_mul_i32_i24_e32 v5, 2, v5 + v_and_b32_e32 v4, 3, v0 + v_lshrrev_b32_e32 v6, 1, v4 + v_add_u32_e32 v4, v5, v6 + v_mul_i32_i24_e32 v220, 0x420, v4 + v_and_b32_e32 v4, 7, v0 + v_lshrrev_b32_e32 v5, 2, v4 + v_mul_i32_i24_e32 v5, 0x100, v5 + v_add_u32_e32 v220, v5, v220 + v_and_b32_e32 v4, 1, v0 + v_mul_i32_i24_e32 v6, 0x80, v4 + v_add_u32_e32 v220, v6, v220 + v_lshrrev_b32_e32 v4, 4, v0 + v_mul_i32_i24_e32 v4, 16, v4 + v_add_u32_e32 v220, v4, v220 + s_mov_b32 s52, 0x1000 + v_add_u32_e64 v220, v220, s52 + v_add_u32_e32 v221, 0x8400, v220 + s_cmp_gt_u32 s57, 0 + s_cbranch_scc0 label_00F4 + s_mul_i32 s53, s58, s56 + s_add_u32 s20, s20, s53 + s_addc_u32 s21, s21, 0 + s_sub_u32 s22, s22, s53 + +label_00F4: + v_lshlrev_b32_e32 v222, 2, v0 + s_mul_i32 s52, s47, 0x100 + s_mul_i32 s53, s49, 32 + s_add_i32 s52, s53, s52 + s_mul_i32 s53, s52, s36 + v_add_u32_e32 v222, s53, v222 + s_mul_i32 s53, 0x80, s36 + v_add_u32_e32 v223, s53, v222 + s_mul_i32 s60, s49, 0x100 + s_add_i32 s60, s60, 0 + v_lshlrev_b32_e32 v224, 2, v0 + v_add_u32_e32 v224, 0, v224 + s_cmp_gt_u32 s57, 0 + s_cbranch_scc0 label_010B + s_mul_i32 s53, s58, s56 + s_lshr_b32 s52, s53, 1 + s_mul_i32 s52, s52, 16 + s_add_u32 s16, s16, s52 + s_addc_u32 s17, s17, 0 + s_sub_u32 s18, s18, s52 + +label_010B: + v_lshlrev_b32_e32 v225, 4, v0 + s_mul_i32 s52, s46, 0x100 + s_mul_i32 s53, s49, 64 + s_add_u32 s52, s52, s53 + s_mul_i32 s52, s52, s42 + v_add_u32_e32 v225, s52, v225 + s_mul_i32 s52, 16, s42 + v_add_u32_e32 v226, s52, v225 + v_add_u32_e32 v227, s52, v226 + v_add_u32_e32 v228, s52, v227 + v_add_u32_e32 v229, 0x400, v225 + v_add_u32_e32 v230, 0x400, v226 + v_add_u32_e32 v231, 0x400, v227 + v_add_u32_e32 v232, 0x400, v228 + s_cmp_gt_u32 s57, 0 + s_cbranch_scc0 label_0124 + s_mul_i32 s53, s58, s56 + s_add_u32 s24, s24, s53 + s_addc_u32 s25, s25, 0 + s_sub_u32 s26, s26, s53 + +label_0124: + v_lshlrev_b32_e32 v233, 2, v0 + s_mul_i32 s52, s46, 0x100 + s_mul_i32 s53, s49, 64 + s_add_i32 s52, s53, s52 + s_mul_i32 s53, s52, s37 + v_add_u32_e32 v233, s53, v233 + s_mul_i32 s52, 32, s37 + v_add_u32_e32 v234, s52, v233 + s_mov_b32 s61, 0x80 + s_mov_b32 s62, 0x800 + s_mov_b32 s63, 0x100 + s_mov_b32 s64, 0x100 + s_add_u32 m0, 0, s59 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_accvgpr_write_b32 a0, 0 + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + v_accvgpr_write_b32 a7, 0 + s_add_u32 m0, 0x1080, s59 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_accvgpr_write_b32 a8, 0 + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + v_accvgpr_write_b32 a15, 0 + s_add_u32 m0, 0x2100, s59 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_accvgpr_write_b32 a16, 0 + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + v_accvgpr_write_b32 a23, 0 + s_add_u32 m0, 0x3180, s59 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_accvgpr_write_b32 a24, 0 + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + v_accvgpr_write_b32 a31, 0 + s_add_u32 m0, 0, s60 + buffer_load_dword v222, s[20:23], 0 offen lds + v_accvgpr_write_b32 a32, 0 + v_accvgpr_write_b32 a33, 0 + v_accvgpr_write_b32 a34, 0 + v_accvgpr_write_b32 a35, 0 + v_accvgpr_write_b32 a36, 0 + v_accvgpr_write_b32 a37, 0 + v_accvgpr_write_b32 a38, 0 + v_accvgpr_write_b32 a39, 0 + s_add_u32 m0, 0x4200, s59 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_accvgpr_write_b32 a40, 0 + v_accvgpr_write_b32 a41, 0 + v_accvgpr_write_b32 a42, 0 + v_accvgpr_write_b32 a43, 0 + v_accvgpr_write_b32 a44, 0 + v_accvgpr_write_b32 a45, 0 + v_accvgpr_write_b32 a46, 0 + v_accvgpr_write_b32 a47, 0 + s_add_u32 m0, 0x5280, s59 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_accvgpr_write_b32 a48, 0 + v_accvgpr_write_b32 a49, 0 + v_accvgpr_write_b32 a50, 0 + v_accvgpr_write_b32 a51, 0 + v_accvgpr_write_b32 a52, 0 + v_accvgpr_write_b32 a53, 0 + v_accvgpr_write_b32 a54, 0 + v_accvgpr_write_b32 a55, 0 + s_add_u32 m0, 0x6300, s59 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_accvgpr_write_b32 a56, 0 + v_accvgpr_write_b32 a57, 0 + v_accvgpr_write_b32 a58, 0 + v_accvgpr_write_b32 a59, 0 + v_accvgpr_write_b32 a60, 0 + v_accvgpr_write_b32 a61, 0 + v_accvgpr_write_b32 a62, 0 + v_accvgpr_write_b32 a63, 0 + s_add_u32 m0, 0x7380, s59 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_accvgpr_write_b32 a64, 0 + v_accvgpr_write_b32 a65, 0 + v_accvgpr_write_b32 a66, 0 + v_accvgpr_write_b32 a67, 0 + v_accvgpr_write_b32 a68, 0 + v_accvgpr_write_b32 a69, 0 + v_accvgpr_write_b32 a70, 0 + v_accvgpr_write_b32 a71, 0 + s_add_u32 m0, 0x400, s60 + buffer_load_dword v223, s[20:23], 0 offen lds + v_accvgpr_write_b32 a72, 0 + v_accvgpr_write_b32 a73, 0 + v_accvgpr_write_b32 a74, 0 + v_accvgpr_write_b32 a75, 0 + v_accvgpr_write_b32 a76, 0 + v_accvgpr_write_b32 a77, 0 + v_accvgpr_write_b32 a78, 0 + v_accvgpr_write_b32 a79, 0 + s_add_u32 s12, s61, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s61 + s_add_u32 s20, s63, s20 + s_addc_u32 s21, 0, s21 + s_sub_u32 s22, s22, s63 + v_accvgpr_write_b32 a80, 0 + v_accvgpr_write_b32 a81, 0 + v_accvgpr_write_b32 a82, 0 + v_accvgpr_write_b32 a83, 0 + v_accvgpr_write_b32 a84, 0 + v_accvgpr_write_b32 a85, 0 + v_accvgpr_write_b32 a86, 0 + v_accvgpr_write_b32 a87, 0 + buffer_load_dwordx4 v[136:139], v225, s[16:19], 0 offen + v_accvgpr_write_b32 a88, 0 + v_accvgpr_write_b32 a89, 0 + v_accvgpr_write_b32 a90, 0 + v_accvgpr_write_b32 a91, 0 + v_accvgpr_write_b32 a92, 0 + v_accvgpr_write_b32 a93, 0 + v_accvgpr_write_b32 a94, 0 + v_accvgpr_write_b32 a95, 0 + buffer_load_dwordx4 v[140:143], v226, s[16:19], 0 offen + v_accvgpr_write_b32 a96, 0 + v_accvgpr_write_b32 a97, 0 + v_accvgpr_write_b32 a98, 0 + v_accvgpr_write_b32 a99, 0 + v_accvgpr_write_b32 a100, 0 + v_accvgpr_write_b32 a101, 0 + v_accvgpr_write_b32 a102, 0 + v_accvgpr_write_b32 a103, 0 + buffer_load_dwordx4 v[144:147], v227, s[16:19], 0 offen + v_accvgpr_write_b32 a104, 0 + v_accvgpr_write_b32 a105, 0 + v_accvgpr_write_b32 a106, 0 + v_accvgpr_write_b32 a107, 0 + v_accvgpr_write_b32 a108, 0 + v_accvgpr_write_b32 a109, 0 + v_accvgpr_write_b32 a110, 0 + v_accvgpr_write_b32 a111, 0 + buffer_load_dwordx4 v[148:151], v228, s[16:19], 0 offen + v_accvgpr_write_b32 a112, 0 + v_accvgpr_write_b32 a113, 0 + v_accvgpr_write_b32 a114, 0 + v_accvgpr_write_b32 a115, 0 + v_accvgpr_write_b32 a116, 0 + v_accvgpr_write_b32 a117, 0 + v_accvgpr_write_b32 a118, 0 + v_accvgpr_write_b32 a119, 0 + buffer_load_dwordx4 v[152:155], v229, s[16:19], 0 offen + v_accvgpr_write_b32 a120, 0 + v_accvgpr_write_b32 a121, 0 + v_accvgpr_write_b32 a122, 0 + v_accvgpr_write_b32 a123, 0 + v_accvgpr_write_b32 a124, 0 + v_accvgpr_write_b32 a125, 0 + v_accvgpr_write_b32 a126, 0 + v_accvgpr_write_b32 a127, 0 + buffer_load_dwordx4 v[156:159], v230, s[16:19], 0 offen + v_accvgpr_write_b32 a128, 0 + v_accvgpr_write_b32 a129, 0 + v_accvgpr_write_b32 a130, 0 + v_accvgpr_write_b32 a131, 0 + v_accvgpr_write_b32 a132, 0 + v_accvgpr_write_b32 a133, 0 + v_accvgpr_write_b32 a134, 0 + v_accvgpr_write_b32 a135, 0 + buffer_load_dwordx4 v[160:163], v231, s[16:19], 0 offen + v_accvgpr_write_b32 a136, 0 + v_accvgpr_write_b32 a137, 0 + v_accvgpr_write_b32 a138, 0 + v_accvgpr_write_b32 a139, 0 + v_accvgpr_write_b32 a140, 0 + v_accvgpr_write_b32 a141, 0 + v_accvgpr_write_b32 a142, 0 + v_accvgpr_write_b32 a143, 0 + buffer_load_dwordx4 v[164:167], v232, s[16:19], 0 offen + v_accvgpr_write_b32 a144, 0 + v_accvgpr_write_b32 a145, 0 + v_accvgpr_write_b32 a146, 0 + v_accvgpr_write_b32 a147, 0 + v_accvgpr_write_b32 a148, 0 + v_accvgpr_write_b32 a149, 0 + v_accvgpr_write_b32 a150, 0 + v_accvgpr_write_b32 a151, 0 + s_add_u32 s16, s62, s16 + s_addc_u32 s17, 0, s17 + s_sub_u32 s18, s18, s62 + buffer_load_dword v208, v233, s[24:27], 0 offen + v_accvgpr_write_b32 a152, 0 + v_accvgpr_write_b32 a153, 0 + v_accvgpr_write_b32 a154, 0 + v_accvgpr_write_b32 a155, 0 + v_accvgpr_write_b32 a156, 0 + v_accvgpr_write_b32 a157, 0 + v_accvgpr_write_b32 a158, 0 + v_accvgpr_write_b32 a159, 0 + buffer_load_dword v209, v234, s[24:27], 0 offen + v_accvgpr_write_b32 a160, 0 + v_accvgpr_write_b32 a161, 0 + v_accvgpr_write_b32 a162, 0 + v_accvgpr_write_b32 a163, 0 + v_accvgpr_write_b32 a164, 0 + v_accvgpr_write_b32 a165, 0 + v_accvgpr_write_b32 a166, 0 + v_accvgpr_write_b32 a167, 0 + s_add_u32 s24, s64, s24 + s_addc_u32 s25, 0, s25 + s_sub_u32 s26, s26, s64 + s_add_u32 m0, 0x8400, s59 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_accvgpr_write_b32 a168, 0 + v_accvgpr_write_b32 a169, 0 + v_accvgpr_write_b32 a170, 0 + v_accvgpr_write_b32 a171, 0 + v_accvgpr_write_b32 a172, 0 + v_accvgpr_write_b32 a173, 0 + v_accvgpr_write_b32 a174, 0 + v_accvgpr_write_b32 a175, 0 + s_add_u32 m0, 0x9480, s59 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_accvgpr_write_b32 a176, 0 + v_accvgpr_write_b32 a177, 0 + v_accvgpr_write_b32 a178, 0 + v_accvgpr_write_b32 a179, 0 + v_accvgpr_write_b32 a180, 0 + v_accvgpr_write_b32 a181, 0 + v_accvgpr_write_b32 a182, 0 + v_accvgpr_write_b32 a183, 0 + s_add_u32 m0, 0xa500, s59 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_accvgpr_write_b32 a184, 0 + v_accvgpr_write_b32 a185, 0 + v_accvgpr_write_b32 a186, 0 + v_accvgpr_write_b32 a187, 0 + v_accvgpr_write_b32 a188, 0 + v_accvgpr_write_b32 a189, 0 + v_accvgpr_write_b32 a190, 0 + v_accvgpr_write_b32 a191, 0 + s_add_u32 m0, 0xb580, s59 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_accvgpr_write_b32 a192, 0 + v_accvgpr_write_b32 a193, 0 + v_accvgpr_write_b32 a194, 0 + v_accvgpr_write_b32 a195, 0 + v_accvgpr_write_b32 a196, 0 + v_accvgpr_write_b32 a197, 0 + v_accvgpr_write_b32 a198, 0 + v_accvgpr_write_b32 a199, 0 + s_add_u32 m0, 0x800, s60 + buffer_load_dword v222, s[20:23], 0 offen lds + v_accvgpr_write_b32 a200, 0 + v_accvgpr_write_b32 a201, 0 + v_accvgpr_write_b32 a202, 0 + v_accvgpr_write_b32 a203, 0 + v_accvgpr_write_b32 a204, 0 + v_accvgpr_write_b32 a205, 0 + v_accvgpr_write_b32 a206, 0 + v_accvgpr_write_b32 a207, 0 + s_add_u32 m0, 0xc600, s59 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_accvgpr_write_b32 a208, 0 + v_accvgpr_write_b32 a209, 0 + v_accvgpr_write_b32 a210, 0 + v_accvgpr_write_b32 a211, 0 + v_accvgpr_write_b32 a212, 0 + v_accvgpr_write_b32 a213, 0 + v_accvgpr_write_b32 a214, 0 + v_accvgpr_write_b32 a215, 0 + s_add_u32 m0, 0xd680, s59 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_accvgpr_write_b32 a216, 0 + v_accvgpr_write_b32 a217, 0 + v_accvgpr_write_b32 a218, 0 + v_accvgpr_write_b32 a219, 0 + v_accvgpr_write_b32 a220, 0 + v_accvgpr_write_b32 a221, 0 + v_accvgpr_write_b32 a222, 0 + v_accvgpr_write_b32 a223, 0 + s_add_u32 m0, 0xe700, s59 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_accvgpr_write_b32 a224, 0 + v_accvgpr_write_b32 a225, 0 + v_accvgpr_write_b32 a226, 0 + v_accvgpr_write_b32 a227, 0 + v_accvgpr_write_b32 a228, 0 + v_accvgpr_write_b32 a229, 0 + v_accvgpr_write_b32 a230, 0 + v_accvgpr_write_b32 a231, 0 + s_add_u32 m0, 0xf780, s59 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_accvgpr_write_b32 a232, 0 + v_accvgpr_write_b32 a233, 0 + v_accvgpr_write_b32 a234, 0 + v_accvgpr_write_b32 a235, 0 + v_accvgpr_write_b32 a236, 0 + v_accvgpr_write_b32 a237, 0 + v_accvgpr_write_b32 a238, 0 + v_accvgpr_write_b32 a239, 0 + s_add_u32 m0, 0xc00, s60 + buffer_load_dword v223, s[20:23], 0 offen lds + v_accvgpr_write_b32 a240, 0 + v_accvgpr_write_b32 a241, 0 + v_accvgpr_write_b32 a242, 0 + v_accvgpr_write_b32 a243, 0 + v_accvgpr_write_b32 a244, 0 + v_accvgpr_write_b32 a245, 0 + v_accvgpr_write_b32 a246, 0 + v_accvgpr_write_b32 a247, 0 + s_add_u32 s12, s61, s12 + s_addc_u32 s13, 0, s13 + s_sub_u32 s14, s14, s61 + s_add_u32 s20, s63, s20 + s_addc_u32 s21, 0, s21 + s_sub_u32 s22, s22, s63 + v_accvgpr_write_b32 a248, 0 + v_accvgpr_write_b32 a249, 0 + v_accvgpr_write_b32 a250, 0 + v_accvgpr_write_b32 a251, 0 + v_accvgpr_write_b32 a252, 0 + v_accvgpr_write_b32 a253, 0 + v_accvgpr_write_b32 a254, 0 + v_accvgpr_write_b32 a255, 0 + s_waitcnt vmcnt(25) + s_barrier + ds_read_b128 v[8:11], v220 + ds_read_b128 v[40:43], v220 offset:64 + ds_read_b128 v[12:15], v220 offset:512 + ds_read_b128 v[44:47], v220 offset:576 + ds_read_b128 v[16:19], v220 offset:4224 + ds_read_b128 v[48:51], v220 offset:4288 + ds_read_b128 v[20:23], v220 offset:4736 + ds_read_b128 v[52:55], v220 offset:4800 + ds_read_b128 v[24:27], v220 offset:8448 + ds_read_b128 v[56:59], v220 offset:8512 + ds_read_b128 v[28:31], v220 offset:8960 + ds_read_b128 v[60:63], v220 offset:9024 + ds_read_b128 v[32:35], v220 offset:12672 + ds_read_b128 v[64:67], v220 offset:12736 + ds_read_b128 v[36:39], v220 offset:13184 + ds_read_b128 v[68:71], v220 offset:13248 + ds_read_b32 v200, v224 + ds_read_b32 v201, v224 offset:256 + ds_read_b32 v202, v224 offset:512 + ds_read_b32 v203, v224 offset:768 + s_lshl_b32 s40, s40, 1 + s_mul_i32 s52, s47, 0x100 + s_mul_hi_u32 s53, s52, s40 + s_add_u32 s5, s5, s53 + s_mul_i32 s53, s52, s40 + s_add_u32 s4, s4, s53 + s_addc_u32 s5, 0, s5 + s_sub_i32 s52, s43, s52 + s_mul_i32 s52, s52, s40 + s_mov_b32 s6, s52 + v_and_b32_e64 v235, v0, 15 + v_mul_lo_u32 v235, v235, s40 + v_lshrrev_b32_e32 v4, 5, v0 + v_mul_i32_i24_e32 v4, 16, v4 + v_add_u32_e32 v235, v4, v235 + v_lshrrev_b32_e32 v4, 4, v0 + v_and_b32_e32 v4, 1, v4 + v_mul_i32_i24_e32 v4, 32, v4 + v_add_u32_e32 v235, v4, v235 + s_mul_i32 s52, s46, 0x100 + s_mul_i32 s53, s49, 64 + s_add_i32 s52, s52, s53 + s_lshl_b32 s52, s52, 1 + v_add_u32_e32 v235, s52, v235 + s_mul_i32 s53, s40, 16 + v_add_u32_e64 v236, v235, s53 + v_add_u32_e64 v237, v236, s53 + v_add_u32_e64 v238, v237, s53 + v_add_u32_e64 v239, v238, s53 + v_add_u32_e64 v240, v239, s53 + v_add_u32_e64 v241, v240, s53 + v_add_u32_e64 v242, v241, s53 + v_add_u32_e64 v243, v242, s53 + v_add_u32_e64 v244, v243, s53 + v_add_u32_e64 v245, v244, s53 + v_add_u32_e64 v246, v245, s53 + v_add_u32_e64 v247, v246, s53 + v_add_u32_e64 v248, v247, s53 + v_add_u32_e64 v249, v248, s53 + v_add_u32_e64 v250, v249, s53 + s_mov_b32 s50, 0 + s_mov_b32 s51, s45 + s_cmp_lt_u32 0x200, s51 + s_cselect_b32 s61, s61, 0 + s_cselect_b32 s63, s63, 0 + s_cmp_lt_u32 0x100, s51 + s_cselect_b32 s62, s62, 0 + s_cselect_b32 s64, s64, 0 + s_cmp_lt_i32 s49, 2 + s_cbranch_scc0 label_0971 + +label_041A: + s_waitcnt vmcnt(10) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[136:139], v[8:11], a[0:3], v208, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[136:139], v[12:15], a[4:7], v208, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[168:171], v225, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[140:143], v[8:11], a[32:35], v208, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[72:75], v220 offset:16896 + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[140:143], v[12:15], a[36:39], v208, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[136:139], v[16:19], a[8:11], v208, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[136:139], v[20:23], a[12:15], v208, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[172:175], v226, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[140:143], v[16:19], a[40:43], v208, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[104:107], v220 offset:16960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[140:143], v[20:23], a[44:47], v208, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[136:139], v[24:27], a[16:19], v208, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[136:139], v[28:31], a[20:23], v208, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[176:179], v227, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[140:143], v[24:27], a[48:51], v208, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[76:79], v220 offset:17408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[140:143], v[28:31], a[52:55], v208, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[136:139], v[32:35], a[24:27], v208, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[136:139], v[36:39], a[28:31], v208, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[180:183], v228, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[140:143], v[32:35], a[56:59], v208, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[108:111], v220 offset:17472 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[140:143], v[36:39], a[60:63], v208, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[144:147], v[8:11], a[64:67], v209, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[144:147], v[12:15], a[68:71], v209, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[184:187], v229, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[148:151], v[8:11], a[96:99], v209, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[80:83], v220 offset:21120 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[148:151], v[12:15], a[100:103], v209, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[144:147], v[16:19], a[72:75], v209, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[144:147], v[20:23], a[76:79], v209, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[188:191], v230, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[148:151], v[16:19], a[104:107], v209, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[112:115], v220 offset:21184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[148:151], v[20:23], a[108:111], v209, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[144:147], v[24:27], a[80:83], v209, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[144:147], v[28:31], a[84:87], v209, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[192:195], v231, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[148:151], v[24:27], a[112:115], v209, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[84:87], v220 offset:21632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[148:151], v[28:31], a[116:119], v209, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[144:147], v[32:35], a[88:91], v209, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[144:147], v[36:39], a[92:95], v209, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[196:199], v232, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[148:151], v[32:35], a[120:123], v209, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[116:119], v220 offset:21696 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[148:151], v[36:39], a[124:127], v209, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[152:155], v[40:43], a[0:3], v208, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[152:155], v[44:47], a[4:7], v208, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v210, v233, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[156:159], v[40:43], a[32:35], v208, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[88:91], v220 offset:25344 + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[156:159], v[44:47], a[36:39], v208, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[152:155], v[48:51], a[8:11], v208, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[152:155], v[52:55], a[12:15], v208, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v211, v234, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[156:159], v[48:51], a[40:43], v208, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[120:123], v220 offset:25408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[156:159], v[52:55], a[44:47], v208, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[152:155], v[56:59], a[16:19], v208, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s53, 0x200, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[152:155], v[60:63], a[20:23], v208, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[92:95], v220 offset:25856 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[156:159], v[56:59], a[48:51], v208, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s53, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[156:159], v[60:63], a[52:55], v208, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[124:127], v220 offset:25920 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[152:155], v[64:67], a[24:27], v208, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s62, s62, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[152:155], v[68:71], a[28:31], v208, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[96:99], v220 offset:29568 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[156:159], v[64:67], a[56:59], v208, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s64, s64, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[156:159], v[68:71], a[60:63], v208, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[128:131], v220 offset:29632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[160:163], v[40:43], a[64:67], v209, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s16, s62, s16 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[160:163], v[44:47], a[68:71], v209, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[100:103], v220 offset:30080 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[164:167], v[40:43], a[96:99], v209, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s17, 0, s17 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[164:167], v[44:47], a[100:103], v209, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[132:135], v220 offset:30144 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[160:163], v[48:51], a[72:75], v209, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s18, s18, s62 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[160:163], v[52:55], a[76:79], v209, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v204, v224 offset:1024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[164:167], v[48:51], a[104:107], v209, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s24, s64, s24 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[164:167], v[52:55], a[108:111], v209, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v205, v224 offset:1280 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[160:163], v[56:59], a[80:83], v209, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s25, 0, s25 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[160:163], v[60:63], a[84:87], v209, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v206, v224 offset:1536 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[164:167], v[56:59], a[112:115], v209, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s26, s26, s64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[164:167], v[60:63], a[116:119], v209, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v207, v224 offset:1792 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[160:163], v[64:67], a[88:91], v209, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[160:163], v[68:71], a[92:95], v209, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[164:167], v[64:67], a[120:123], v209, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[164:167], v[68:71], a[124:127], v209, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_waitcnt vmcnt(15) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[136:139], v[72:75], a[128:131], v208, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[136:139], v[76:79], a[132:135], v208, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[140:143], v[72:75], a[160:163], v208, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[8:11], v221 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[140:143], v[76:79], a[164:167], v208, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[136:139], v[80:83], a[136:139], v208, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[40:43], v221 offset:64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[136:139], v[84:87], a[140:143], v208, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x1080, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[140:143], v[80:83], a[168:171], v208, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[12:15], v221 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[140:143], v[84:87], a[172:175], v208, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[136:139], v[88:91], a[144:147], v208, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[44:47], v221 offset:576 + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[136:139], v[92:95], a[148:151], v208, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x2100, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[140:143], v[88:91], a[176:179], v208, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[16:19], v221 offset:4224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[140:143], v[92:95], a[180:183], v208, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[136:139], v[96:99], a[152:155], v208, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[48:51], v221 offset:4288 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[136:139], v[100:103], a[156:159], v208, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x3180, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[140:143], v[96:99], a[184:187], v208, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[20:23], v221 offset:4736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[140:143], v[100:103], a[188:191], v208, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[144:147], v[72:75], a[192:195], v209, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[52:55], v221 offset:4800 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[144:147], v[76:79], a[196:199], v209, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[148:151], v[72:75], a[224:227], v209, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[24:27], v221 offset:8448 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[148:151], v[76:79], a[228:231], v209, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dword v222, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[144:147], v[80:83], a[200:203], v209, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[56:59], v221 offset:8512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[144:147], v[84:87], a[204:207], v209, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x4200, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[148:151], v[80:83], a[232:235], v209, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[28:31], v221 offset:8960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[148:151], v[84:87], a[236:239], v209, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[144:147], v[88:91], a[208:211], v209, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[60:63], v221 offset:9024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[144:147], v[92:95], a[212:215], v209, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x5280, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[148:151], v[88:91], a[240:243], v209, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[32:35], v221 offset:12672 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[148:151], v[92:95], a[244:247], v209, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[144:147], v[96:99], a[216:219], v209, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[64:67], v221 offset:12736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[144:147], v[100:103], a[220:223], v209, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x6300, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[148:151], v[96:99], a[248:251], v209, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[36:39], v221 offset:13184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[148:151], v[100:103], a[252:255], v209, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[152:155], v[104:107], a[128:131], v208, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[68:71], v221 offset:13248 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[152:155], v[108:111], a[132:135], v208, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x7380, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[156:159], v[104:107], a[160:163], v208, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v200, v224 offset:2048 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[156:159], v[108:111], a[164:167], v208, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[152:155], v[112:115], a[136:139], v208, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v201, v224 offset:2304 + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[152:155], v[116:119], a[140:143], v208, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x400, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[156:159], v[112:115], a[168:171], v208, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v202, v224 offset:2560 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[156:159], v[116:119], a[172:175], v208, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v223, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[152:155], v[120:123], a[144:147], v208, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v203, v224 offset:2816 + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[152:155], v[124:127], a[148:151], v208, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s52, 0x300, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[156:159], v[120:123], a[176:179], v208, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[156:159], v[124:127], a[180:183], v208, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s52, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[152:155], v[128:131], a[152:155], v208, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[152:155], v[132:135], a[156:159], v208, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s61, s61, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[156:159], v[128:131], a[184:187], v208, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[156:159], v[132:135], a[188:191], v208, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s63, s63, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[160:163], v[104:107], a[192:195], v209, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[160:163], v[108:111], a[196:199], v209, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s12, s61, s12 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[164:167], v[104:107], a[224:227], v209, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[164:167], v[108:111], a[228:231], v209, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s13, 0, s13 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[160:163], v[112:115], a[200:203], v209, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[160:163], v[116:119], a[204:207], v209, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s14, s14, s61 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[164:167], v[112:115], a[232:235], v209, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[164:167], v[116:119], a[236:239], v209, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s20, s63, s20 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[160:163], v[120:123], a[208:211], v209, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[160:163], v[124:127], a[212:215], v209, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s21, 0, s21 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[164:167], v[120:123], a[240:243], v209, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[164:167], v[124:127], a[244:247], v209, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s22, s22, s63 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[160:163], v[128:131], a[216:219], v209, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addk_i32 s50, 0x100 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[160:163], v[132:135], a[220:223], v209, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_i32 s50, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[164:167], v[128:131], a[248:251], v209, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[164:167], v[132:135], a[252:255], v209, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cbranch_scc0 label_0EC7 + s_waitcnt vmcnt(10) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[168:171], v[8:11], a[0:3], v210, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[168:171], v[12:15], a[4:7], v210, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[136:139], v225, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[172:175], v[8:11], a[32:35], v210, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[72:75], v221 offset:16896 + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[172:175], v[12:15], a[36:39], v210, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[168:171], v[16:19], a[8:11], v210, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[168:171], v[20:23], a[12:15], v210, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[140:143], v226, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[172:175], v[16:19], a[40:43], v210, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[104:107], v221 offset:16960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[172:175], v[20:23], a[44:47], v210, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[168:171], v[24:27], a[16:19], v210, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[168:171], v[28:31], a[20:23], v210, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[144:147], v227, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[172:175], v[24:27], a[48:51], v210, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[76:79], v221 offset:17408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[172:175], v[28:31], a[52:55], v210, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[168:171], v[32:35], a[24:27], v210, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[168:171], v[36:39], a[28:31], v210, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[148:151], v228, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[172:175], v[32:35], a[56:59], v210, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[108:111], v221 offset:17472 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[172:175], v[36:39], a[60:63], v210, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[176:179], v[8:11], a[64:67], v211, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[176:179], v[12:15], a[68:71], v211, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[152:155], v229, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[180:183], v[8:11], a[96:99], v211, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[80:83], v221 offset:21120 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[180:183], v[12:15], a[100:103], v211, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[176:179], v[16:19], a[72:75], v211, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[176:179], v[20:23], a[76:79], v211, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[156:159], v230, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[180:183], v[16:19], a[104:107], v211, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[112:115], v221 offset:21184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[180:183], v[20:23], a[108:111], v211, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[176:179], v[24:27], a[80:83], v211, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[176:179], v[28:31], a[84:87], v211, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[160:163], v231, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[180:183], v[24:27], a[112:115], v211, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[84:87], v221 offset:21632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[180:183], v[28:31], a[116:119], v211, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[176:179], v[32:35], a[88:91], v211, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[176:179], v[36:39], a[92:95], v211, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[164:167], v232, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[180:183], v[32:35], a[120:123], v211, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[116:119], v221 offset:21696 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[180:183], v[36:39], a[124:127], v211, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[184:187], v[40:43], a[0:3], v210, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[184:187], v[44:47], a[4:7], v210, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v208, v233, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[188:191], v[40:43], a[32:35], v210, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[88:91], v221 offset:25344 + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[188:191], v[44:47], a[36:39], v210, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[184:187], v[48:51], a[8:11], v210, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[184:187], v[52:55], a[12:15], v210, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v209, v234, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[188:191], v[48:51], a[40:43], v210, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[120:123], v221 offset:25408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[188:191], v[52:55], a[44:47], v210, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[184:187], v[56:59], a[16:19], v210, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s53, 0x200, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[184:187], v[60:63], a[20:23], v210, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[92:95], v221 offset:25856 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[188:191], v[56:59], a[48:51], v210, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s53, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[188:191], v[60:63], a[52:55], v210, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[124:127], v221 offset:25920 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[184:187], v[64:67], a[24:27], v210, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s62, s62, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[184:187], v[68:71], a[28:31], v210, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[96:99], v221 offset:29568 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[188:191], v[64:67], a[56:59], v210, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s64, s64, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[188:191], v[68:71], a[60:63], v210, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[128:131], v221 offset:29632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[192:195], v[40:43], a[64:67], v211, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s16, s62, s16 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[192:195], v[44:47], a[68:71], v211, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[100:103], v221 offset:30080 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[196:199], v[40:43], a[96:99], v211, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s17, 0, s17 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[196:199], v[44:47], a[100:103], v211, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[132:135], v221 offset:30144 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[192:195], v[48:51], a[72:75], v211, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s18, s18, s62 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[192:195], v[52:55], a[76:79], v211, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v204, v224 offset:3072 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[196:199], v[48:51], a[104:107], v211, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s24, s64, s24 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[196:199], v[52:55], a[108:111], v211, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v205, v224 offset:3328 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[192:195], v[56:59], a[80:83], v211, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s25, 0, s25 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[192:195], v[60:63], a[84:87], v211, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v206, v224 offset:3584 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[196:199], v[56:59], a[112:115], v211, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s26, s26, s64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[196:199], v[60:63], a[116:119], v211, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v207, v224 offset:3840 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[192:195], v[64:67], a[88:91], v211, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[192:195], v[68:71], a[92:95], v211, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[196:199], v[64:67], a[120:123], v211, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[196:199], v[68:71], a[124:127], v211, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_waitcnt vmcnt(15) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[168:171], v[72:75], a[128:131], v210, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[168:171], v[76:79], a[132:135], v210, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x8400, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[172:175], v[72:75], a[160:163], v210, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[8:11], v220 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[172:175], v[76:79], a[164:167], v210, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[168:171], v[80:83], a[136:139], v210, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[40:43], v220 offset:64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[168:171], v[84:87], a[140:143], v210, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x9480, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[172:175], v[80:83], a[168:171], v210, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[12:15], v220 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[172:175], v[84:87], a[172:175], v210, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[168:171], v[88:91], a[144:147], v210, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[44:47], v220 offset:576 + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[168:171], v[92:95], a[148:151], v210, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xa500, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[172:175], v[88:91], a[176:179], v210, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[16:19], v220 offset:4224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[172:175], v[92:95], a[180:183], v210, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[168:171], v[96:99], a[152:155], v210, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[48:51], v220 offset:4288 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[168:171], v[100:103], a[156:159], v210, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xb580, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[172:175], v[96:99], a[184:187], v210, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[20:23], v220 offset:4736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[172:175], v[100:103], a[188:191], v210, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[176:179], v[72:75], a[192:195], v211, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[52:55], v220 offset:4800 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[176:179], v[76:79], a[196:199], v211, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x800, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[180:183], v[72:75], a[224:227], v211, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[24:27], v220 offset:8448 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[180:183], v[76:79], a[228:231], v211, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dword v222, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[176:179], v[80:83], a[200:203], v211, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[56:59], v220 offset:8512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[176:179], v[84:87], a[204:207], v211, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xc600, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[180:183], v[80:83], a[232:235], v211, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[28:31], v220 offset:8960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[180:183], v[84:87], a[236:239], v211, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[176:179], v[88:91], a[208:211], v211, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[60:63], v220 offset:9024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[176:179], v[92:95], a[212:215], v211, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xd680, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[180:183], v[88:91], a[240:243], v211, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[32:35], v220 offset:12672 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[180:183], v[92:95], a[244:247], v211, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[176:179], v[96:99], a[216:219], v211, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[64:67], v220 offset:12736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[176:179], v[100:103], a[220:223], v211, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xe700, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[180:183], v[96:99], a[248:251], v211, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[36:39], v220 offset:13184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[180:183], v[100:103], a[252:255], v211, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[184:187], v[104:107], a[128:131], v210, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[68:71], v220 offset:13248 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[184:187], v[108:111], a[132:135], v210, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xf780, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[188:191], v[104:107], a[160:163], v210, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v200, v224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[188:191], v[108:111], a[164:167], v210, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[184:187], v[112:115], a[136:139], v210, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v201, v224 offset:256 + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[184:187], v[116:119], a[140:143], v210, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xc00, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[188:191], v[112:115], a[168:171], v210, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v202, v224 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[188:191], v[116:119], a[172:175], v210, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v223, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[184:187], v[120:123], a[144:147], v210, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v203, v224 offset:768 + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[184:187], v[124:127], a[148:151], v210, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s52, 0x300, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[188:191], v[120:123], a[176:179], v210, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[188:191], v[124:127], a[180:183], v210, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s52, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[184:187], v[128:131], a[152:155], v210, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[184:187], v[132:135], a[156:159], v210, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s61, s61, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[188:191], v[128:131], a[184:187], v210, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[188:191], v[132:135], a[188:191], v210, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s63, s63, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[192:195], v[104:107], a[192:195], v211, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[192:195], v[108:111], a[196:199], v211, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s12, s61, s12 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[196:199], v[104:107], a[224:227], v211, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[196:199], v[108:111], a[228:231], v211, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s13, 0, s13 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[192:195], v[112:115], a[200:203], v211, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[192:195], v[116:119], a[204:207], v211, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s14, s14, s61 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[196:199], v[112:115], a[232:235], v211, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[196:199], v[116:119], a[236:239], v211, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s20, s63, s20 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[192:195], v[120:123], a[208:211], v211, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[192:195], v[124:127], a[212:215], v211, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s21, 0, s21 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[196:199], v[120:123], a[240:243], v211, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[196:199], v[124:127], a[244:247], v211, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s22, s22, s63 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[192:195], v[128:131], a[216:219], v211, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addk_i32 s50, 0x100 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[192:195], v[132:135], a[220:223], v211, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_i32 s50, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[196:199], v[128:131], a[248:251], v211, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[196:199], v[132:135], a[252:255], v211, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cbranch_scc0 label_0EC7 + s_branch label_041A + +label_0971: + s_nop 0 + +label_0972: + s_waitcnt vmcnt(10) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[136:139], v[8:11], a[0:3], v208, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[136:139], v[12:15], a[4:7], v208, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[72:75], v220 offset:16896 + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[140:143], v[8:11], a[32:35], v208, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[168:171], v225, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[140:143], v[12:15], a[36:39], v208, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[136:139], v[16:19], a[8:11], v208, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[136:139], v[20:23], a[12:15], v208, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[104:107], v220 offset:16960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[140:143], v[16:19], a[40:43], v208, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[172:175], v226, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[140:143], v[20:23], a[44:47], v208, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[136:139], v[24:27], a[16:19], v208, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[136:139], v[28:31], a[20:23], v208, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[76:79], v220 offset:17408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[140:143], v[24:27], a[48:51], v208, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[176:179], v227, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[140:143], v[28:31], a[52:55], v208, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[136:139], v[32:35], a[24:27], v208, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[136:139], v[36:39], a[28:31], v208, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[108:111], v220 offset:17472 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[140:143], v[32:35], a[56:59], v208, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[180:183], v228, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[140:143], v[36:39], a[60:63], v208, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[144:147], v[8:11], a[64:67], v209, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[144:147], v[12:15], a[68:71], v209, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[80:83], v220 offset:21120 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[148:151], v[8:11], a[96:99], v209, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[184:187], v229, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[148:151], v[12:15], a[100:103], v209, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[144:147], v[16:19], a[72:75], v209, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[144:147], v[20:23], a[76:79], v209, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[112:115], v220 offset:21184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[148:151], v[16:19], a[104:107], v209, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[188:191], v230, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[148:151], v[20:23], a[108:111], v209, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[144:147], v[24:27], a[80:83], v209, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[144:147], v[28:31], a[84:87], v209, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[84:87], v220 offset:21632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[148:151], v[24:27], a[112:115], v209, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[192:195], v231, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[148:151], v[28:31], a[116:119], v209, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[144:147], v[32:35], a[88:91], v209, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[144:147], v[36:39], a[92:95], v209, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[116:119], v220 offset:21696 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[148:151], v[32:35], a[120:123], v209, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[196:199], v232, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[148:151], v[36:39], a[124:127], v209, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[152:155], v[40:43], a[0:3], v208, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[152:155], v[44:47], a[4:7], v208, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[88:91], v220 offset:25344 + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[156:159], v[40:43], a[32:35], v208, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v210, v233, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[156:159], v[44:47], a[36:39], v208, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[152:155], v[48:51], a[8:11], v208, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[152:155], v[52:55], a[12:15], v208, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[120:123], v220 offset:25408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[156:159], v[48:51], a[40:43], v208, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v211, v234, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[156:159], v[52:55], a[44:47], v208, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[152:155], v[56:59], a[16:19], v208, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[92:95], v220 offset:25856 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[152:155], v[60:63], a[20:23], v208, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s53, 0x200, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[156:159], v[56:59], a[48:51], v208, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[124:127], v220 offset:25920 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[156:159], v[60:63], a[52:55], v208, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s53, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[152:155], v[64:67], a[24:27], v208, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[96:99], v220 offset:29568 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[152:155], v[68:71], a[28:31], v208, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s62, s62, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[156:159], v[64:67], a[56:59], v208, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[128:131], v220 offset:29632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[156:159], v[68:71], a[60:63], v208, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s64, s64, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[160:163], v[40:43], a[64:67], v209, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[100:103], v220 offset:30080 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[160:163], v[44:47], a[68:71], v209, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s16, s62, s16 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[164:167], v[40:43], a[96:99], v209, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[132:135], v220 offset:30144 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[164:167], v[44:47], a[100:103], v209, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s17, 0, s17 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[160:163], v[48:51], a[72:75], v209, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v204, v224 offset:1024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[160:163], v[52:55], a[76:79], v209, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s18, s18, s62 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[164:167], v[48:51], a[104:107], v209, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v205, v224 offset:1280 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[164:167], v[52:55], a[108:111], v209, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s24, s64, s24 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[160:163], v[56:59], a[80:83], v209, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v206, v224 offset:1536 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[160:163], v[60:63], a[84:87], v209, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s25, 0, s25 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[164:167], v[56:59], a[112:115], v209, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v207, v224 offset:1792 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[164:167], v[60:63], a[116:119], v209, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s26, s26, s64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[160:163], v[64:67], a[88:91], v209, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[160:163], v[68:71], a[92:95], v209, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[164:167], v[64:67], a[120:123], v209, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[164:167], v[68:71], a[124:127], v209, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_waitcnt vmcnt(15) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[136:139], v[72:75], a[128:131], v208, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[136:139], v[76:79], a[132:135], v208, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[8:11], v221 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[140:143], v[72:75], a[160:163], v208, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[140:143], v[76:79], a[164:167], v208, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[40:43], v221 offset:64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[136:139], v[80:83], a[136:139], v208, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[136:139], v[84:87], a[140:143], v208, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[12:15], v221 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[140:143], v[80:83], a[168:171], v208, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x1080, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[140:143], v[84:87], a[172:175], v208, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[44:47], v221 offset:576 + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[136:139], v[88:91], a[144:147], v208, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[136:139], v[92:95], a[148:151], v208, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[16:19], v221 offset:4224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[140:143], v[88:91], a[176:179], v208, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x2100, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[140:143], v[92:95], a[180:183], v208, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[48:51], v221 offset:4288 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[136:139], v[96:99], a[152:155], v208, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[136:139], v[100:103], a[156:159], v208, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[20:23], v221 offset:4736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[140:143], v[96:99], a[184:187], v208, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x3180, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[140:143], v[100:103], a[188:191], v208, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[52:55], v221 offset:4800 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[144:147], v[72:75], a[192:195], v209, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[144:147], v[76:79], a[196:199], v209, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[24:27], v221 offset:8448 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[148:151], v[72:75], a[224:227], v209, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[148:151], v[76:79], a[228:231], v209, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[56:59], v221 offset:8512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[144:147], v[80:83], a[200:203], v209, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dword v222, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[144:147], v[84:87], a[204:207], v209, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[28:31], v221 offset:8960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[148:151], v[80:83], a[232:235], v209, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x4200, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[148:151], v[84:87], a[236:239], v209, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[60:63], v221 offset:9024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[144:147], v[88:91], a[208:211], v209, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[144:147], v[92:95], a[212:215], v209, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[32:35], v221 offset:12672 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[148:151], v[88:91], a[240:243], v209, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x5280, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[148:151], v[92:95], a[244:247], v209, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[64:67], v221 offset:12736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[144:147], v[96:99], a[216:219], v209, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[144:147], v[100:103], a[220:223], v209, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[36:39], v221 offset:13184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[148:151], v[96:99], a[248:251], v209, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x6300, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[148:151], v[100:103], a[252:255], v209, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[68:71], v221 offset:13248 + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[152:155], v[104:107], a[128:131], v208, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[152:155], v[108:111], a[132:135], v208, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v200, v224 offset:2048 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[156:159], v[104:107], a[160:163], v208, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x7380, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[156:159], v[108:111], a[164:167], v208, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v201, v224 offset:2304 + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[152:155], v[112:115], a[136:139], v208, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[152:155], v[116:119], a[140:143], v208, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v202, v224 offset:2560 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[156:159], v[112:115], a[168:171], v208, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x400, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[156:159], v[116:119], a[172:175], v208, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v203, v224 offset:2816 + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[152:155], v[120:123], a[144:147], v208, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v223, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[152:155], v[124:127], a[148:151], v208, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[156:159], v[120:123], a[176:179], v208, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s52, 0x300, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[156:159], v[124:127], a[180:183], v208, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[152:155], v[128:131], a[152:155], v208, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s52, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[152:155], v[132:135], a[156:159], v208, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[156:159], v[128:131], a[184:187], v208, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s61, s61, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[156:159], v[132:135], a[188:191], v208, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[160:163], v[104:107], a[192:195], v209, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s63, s63, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[160:163], v[108:111], a[196:199], v209, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[164:167], v[104:107], a[224:227], v209, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s12, s61, s12 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[164:167], v[108:111], a[228:231], v209, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[160:163], v[112:115], a[200:203], v209, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s13, 0, s13 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[160:163], v[116:119], a[204:207], v209, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[164:167], v[112:115], a[232:235], v209, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s14, s14, s61 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[164:167], v[116:119], a[236:239], v209, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[160:163], v[120:123], a[208:211], v209, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s20, s63, s20 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[160:163], v[124:127], a[212:215], v209, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[164:167], v[120:123], a[240:243], v209, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s21, 0, s21 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[164:167], v[124:127], a[244:247], v209, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[160:163], v[128:131], a[216:219], v209, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addk_i32 s50, 0x100 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[160:163], v[132:135], a[220:223], v209, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_i32 s50, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[164:167], v[128:131], a[248:251], v209, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[164:167], v[132:135], a[252:255], v209, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cbranch_scc0 label_0EC7 + s_waitcnt vmcnt(10) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[168:171], v[8:11], a[0:3], v210, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[168:171], v[12:15], a[4:7], v210, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[72:75], v221 offset:16896 + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[172:175], v[8:11], a[32:35], v210, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[136:139], v225, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[172:175], v[12:15], a[36:39], v210, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[168:171], v[16:19], a[8:11], v210, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[168:171], v[20:23], a[12:15], v210, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[104:107], v221 offset:16960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[172:175], v[16:19], a[40:43], v210, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[140:143], v226, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[172:175], v[20:23], a[44:47], v210, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[168:171], v[24:27], a[16:19], v210, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[168:171], v[28:31], a[20:23], v210, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[76:79], v221 offset:17408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[172:175], v[24:27], a[48:51], v210, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[144:147], v227, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[172:175], v[28:31], a[52:55], v210, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[168:171], v[32:35], a[24:27], v210, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[168:171], v[36:39], a[28:31], v210, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[108:111], v221 offset:17472 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[172:175], v[32:35], a[56:59], v210, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[148:151], v228, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[172:175], v[36:39], a[60:63], v210, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[176:179], v[8:11], a[64:67], v211, v200 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[176:179], v[12:15], a[68:71], v211, v200 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[80:83], v221 offset:21120 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[180:183], v[8:11], a[96:99], v211, v200 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[152:155], v229, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[180:183], v[12:15], a[100:103], v211, v200 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[176:179], v[16:19], a[72:75], v211, v201 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[176:179], v[20:23], a[76:79], v211, v201 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[112:115], v221 offset:21184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[180:183], v[16:19], a[104:107], v211, v201 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[156:159], v230, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[180:183], v[20:23], a[108:111], v211, v201 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[176:179], v[24:27], a[80:83], v211, v202 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[176:179], v[28:31], a[84:87], v211, v202 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[84:87], v221 offset:21632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[180:183], v[24:27], a[112:115], v211, v202 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[160:163], v231, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[180:183], v[28:31], a[116:119], v211, v202 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[176:179], v[32:35], a[88:91], v211, v203 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[176:179], v[36:39], a[92:95], v211, v203 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[116:119], v221 offset:21696 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[180:183], v[32:35], a[120:123], v211, v203 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v[164:167], v232, s[16:19], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[180:183], v[36:39], a[124:127], v211, v203 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[0:3], v[184:187], v[40:43], a[0:3], v210, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[4:7], v[184:187], v[44:47], a[4:7], v210, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[88:91], v221 offset:25344 + v_mfma_scale_f32_16x16x128_f8f6f4 a[32:35], v[188:191], v[40:43], a[32:35], v210, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v208, v233, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[36:39], v[188:191], v[44:47], a[36:39], v210, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[8:11], v[184:187], v[48:51], a[8:11], v210, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[12:15], v[184:187], v[52:55], a[12:15], v210, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[120:123], v221 offset:25408 + v_mfma_scale_f32_16x16x128_f8f6f4 a[40:43], v[188:191], v[48:51], a[40:43], v210, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v209, v234, s[24:27], 0 offen + v_mfma_scale_f32_16x16x128_f8f6f4 a[44:47], v[188:191], v[52:55], a[44:47], v210, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[16:19], v[184:187], v[56:59], a[16:19], v210, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[92:95], v221 offset:25856 + v_mfma_scale_f32_16x16x128_f8f6f4 a[20:23], v[184:187], v[60:63], a[20:23], v210, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s53, 0x200, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[48:51], v[188:191], v[56:59], a[48:51], v210, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[124:127], v221 offset:25920 + v_mfma_scale_f32_16x16x128_f8f6f4 a[52:55], v[188:191], v[60:63], a[52:55], v210, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s53, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[24:27], v[184:187], v[64:67], a[24:27], v210, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[96:99], v221 offset:29568 + v_mfma_scale_f32_16x16x128_f8f6f4 a[28:31], v[184:187], v[68:71], a[28:31], v210, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s62, s62, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[56:59], v[188:191], v[64:67], a[56:59], v210, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[128:131], v221 offset:29632 + v_mfma_scale_f32_16x16x128_f8f6f4 a[60:63], v[188:191], v[68:71], a[60:63], v210, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s64, s64, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[64:67], v[192:195], v[40:43], a[64:67], v211, v200 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[100:103], v221 offset:30080 + v_mfma_scale_f32_16x16x128_f8f6f4 a[68:71], v[192:195], v[44:47], a[68:71], v211, v200 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s16, s62, s16 + v_mfma_scale_f32_16x16x128_f8f6f4 a[96:99], v[196:199], v[40:43], a[96:99], v211, v200 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b128 v[132:135], v221 offset:30144 + v_mfma_scale_f32_16x16x128_f8f6f4 a[100:103], v[196:199], v[44:47], a[100:103], v211, v200 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s17, 0, s17 + v_mfma_scale_f32_16x16x128_f8f6f4 a[72:75], v[192:195], v[48:51], a[72:75], v211, v201 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v204, v224 offset:3072 + v_mfma_scale_f32_16x16x128_f8f6f4 a[76:79], v[192:195], v[52:55], a[76:79], v211, v201 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s18, s18, s62 + v_mfma_scale_f32_16x16x128_f8f6f4 a[104:107], v[196:199], v[48:51], a[104:107], v211, v201 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v205, v224 offset:3328 + v_mfma_scale_f32_16x16x128_f8f6f4 a[108:111], v[196:199], v[52:55], a[108:111], v211, v201 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s24, s64, s24 + v_mfma_scale_f32_16x16x128_f8f6f4 a[80:83], v[192:195], v[56:59], a[80:83], v211, v202 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v206, v224 offset:3584 + v_mfma_scale_f32_16x16x128_f8f6f4 a[84:87], v[192:195], v[60:63], a[84:87], v211, v202 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s25, 0, s25 + v_mfma_scale_f32_16x16x128_f8f6f4 a[112:115], v[196:199], v[56:59], a[112:115], v211, v202 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v207, v224 offset:3840 + v_mfma_scale_f32_16x16x128_f8f6f4 a[116:119], v[196:199], v[60:63], a[116:119], v211, v202 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s26, s26, s64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[88:91], v[192:195], v[64:67], a[88:91], v211, v203 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[92:95], v[192:195], v[68:71], a[92:95], v211, v203 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[120:123], v[196:199], v[64:67], a[120:123], v211, v203 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[124:127], v[196:199], v[68:71], a[124:127], v211, v203 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_waitcnt vmcnt(15) lgkmcnt(0) + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[168:171], v[72:75], a[128:131], v210, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_barrier + s_nop 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[168:171], v[76:79], a[132:135], v210, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[8:11], v220 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[172:175], v[72:75], a[160:163], v210, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x8400, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[172:175], v[76:79], a[164:167], v210, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[40:43], v220 offset:64 + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[168:171], v[80:83], a[136:139], v210, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v212, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[168:171], v[84:87], a[140:143], v210, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[12:15], v220 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[172:175], v[80:83], a[168:171], v210, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x9480, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[172:175], v[84:87], a[172:175], v210, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[44:47], v220 offset:576 + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[168:171], v[88:91], a[144:147], v210, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v213, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[168:171], v[92:95], a[148:151], v210, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[16:19], v220 offset:4224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[172:175], v[88:91], a[176:179], v210, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xa500, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[172:175], v[92:95], a[180:183], v210, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[48:51], v220 offset:4288 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[168:171], v[96:99], a[152:155], v210, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v214, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[168:171], v[100:103], a[156:159], v210, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[20:23], v220 offset:4736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[172:175], v[96:99], a[184:187], v210, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xb580, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[172:175], v[100:103], a[188:191], v210, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[52:55], v220 offset:4800 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[176:179], v[72:75], a[192:195], v211, v204 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v215, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[176:179], v[76:79], a[196:199], v211, v204 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[24:27], v220 offset:8448 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[180:183], v[72:75], a[224:227], v211, v204 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0x800, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[180:183], v[76:79], a[228:231], v211, v204 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[56:59], v220 offset:8512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[176:179], v[80:83], a[200:203], v211, v205 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dword v222, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[176:179], v[84:87], a[204:207], v211, v205 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[28:31], v220 offset:8960 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[180:183], v[80:83], a[232:235], v211, v205 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xc600, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[180:183], v[84:87], a[236:239], v211, v205 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[60:63], v220 offset:9024 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[176:179], v[88:91], a[208:211], v211, v206 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v216, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[176:179], v[92:95], a[212:215], v211, v206 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[32:35], v220 offset:12672 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[180:183], v[88:91], a[240:243], v211, v206 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xd680, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[180:183], v[92:95], a[244:247], v211, v206 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[64:67], v220 offset:12736 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[176:179], v[96:99], a[216:219], v211, v207 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v217, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[176:179], v[100:103], a[220:223], v211, v207 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[36:39], v220 offset:13184 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[180:183], v[96:99], a[248:251], v211, v207 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xe700, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[180:183], v[100:103], a[252:255], v211, v207 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + ds_read_b128 v[68:71], v220 offset:13248 + v_mfma_scale_f32_16x16x128_f8f6f4 a[128:131], v[184:187], v[104:107], a[128:131], v210, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v218, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[132:135], v[184:187], v[108:111], a[132:135], v210, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v200, v224 + v_mfma_scale_f32_16x16x128_f8f6f4 a[160:163], v[188:191], v[104:107], a[160:163], v210, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xf780, s59 + v_mfma_scale_f32_16x16x128_f8f6f4 a[164:167], v[188:191], v[108:111], a[164:167], v210, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v201, v224 offset:256 + v_mfma_scale_f32_16x16x128_f8f6f4 a[136:139], v[184:187], v[112:115], a[136:139], v210, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dwordx4 v219, s[12:15], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[140:143], v[184:187], v[116:119], a[140:143], v210, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v202, v224 offset:512 + v_mfma_scale_f32_16x16x128_f8f6f4 a[168:171], v[188:191], v[112:115], a[168:171], v210, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 m0, 0xc00, s60 + v_mfma_scale_f32_16x16x128_f8f6f4 a[172:175], v[188:191], v[116:119], a[172:175], v210, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + ds_read_b32 v203, v224 offset:768 + v_mfma_scale_f32_16x16x128_f8f6f4 a[144:147], v[184:187], v[120:123], a[144:147], v210, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + buffer_load_dword v223, s[20:23], 0 offen lds + v_mfma_scale_f32_16x16x128_f8f6f4 a[148:151], v[184:187], v[124:127], a[148:151], v210, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[176:179], v[188:191], v[120:123], a[176:179], v210, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s52, 0x300, s50 + v_mfma_scale_f32_16x16x128_f8f6f4 a[180:183], v[188:191], v[124:127], a[180:183], v210, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[152:155], v[184:187], v[128:131], a[152:155], v210, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_u32 s52, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[156:159], v[184:187], v[132:135], a[156:159], v210, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[184:187], v[188:191], v[128:131], a[184:187], v210, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s61, s61, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[188:191], v[188:191], v[132:135], a[188:191], v210, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[192:195], v[192:195], v[104:107], a[192:195], v211, v204 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cselect_b32 s63, s63, 0 + v_mfma_scale_f32_16x16x128_f8f6f4 a[196:199], v[192:195], v[108:111], a[196:199], v211, v204 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[224:227], v[196:199], v[104:107], a[224:227], v211, v204 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s12, s61, s12 + v_mfma_scale_f32_16x16x128_f8f6f4 a[228:231], v[196:199], v[108:111], a[228:231], v211, v204 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[200:203], v[192:195], v[112:115], a[200:203], v211, v205 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s13, 0, s13 + v_mfma_scale_f32_16x16x128_f8f6f4 a[204:207], v[192:195], v[116:119], a[204:207], v211, v205 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[232:235], v[196:199], v[112:115], a[232:235], v211, v205 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_sub_u32 s14, s14, s61 + v_mfma_scale_f32_16x16x128_f8f6f4 a[236:239], v[196:199], v[116:119], a[236:239], v211, v205 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[208:211], v[192:195], v[120:123], a[208:211], v211, v206 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_add_u32 s20, s63, s20 + v_mfma_scale_f32_16x16x128_f8f6f4 a[212:215], v[192:195], v[124:127], a[212:215], v211, v206 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[240:243], v[196:199], v[120:123], a[240:243], v211, v206 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addc_u32 s21, 0, s21 + v_mfma_scale_f32_16x16x128_f8f6f4 a[244:247], v[196:199], v[124:127], a[244:247], v211, v206 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[216:219], v[192:195], v[128:131], a[216:219], v211, v207 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_addk_i32 s50, 0x100 + v_mfma_scale_f32_16x16x128_f8f6f4 a[220:223], v[192:195], v[132:135], a[220:223], v211, v207 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cmp_lt_i32 s50, s51 + v_mfma_scale_f32_16x16x128_f8f6f4 a[248:251], v[196:199], v[128:131], a[248:251], v211, v207 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_mfma_scale_f32_16x16x128_f8f6f4 a[252:255], v[196:199], v[132:135], a[252:255], v211, v207 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + s_cbranch_scc0 label_0EC7 + s_branch label_0972 + +label_0EC7: + s_waitcnt vmcnt(0) lgkmcnt(0) + s_barrier + s_cmp_eq_u32 s57, 0 + s_cbranch_scc1 label_14AC + v_accvgpr_read_b32 v8, a0 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a1 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a2 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a3 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a32 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a33 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a34 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a35 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v235, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v235, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v235, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v235, s[4:7], 0 offen offset:12 + v_add_i32 v235, v235, 64 + v_accvgpr_read_b32 v8, a64 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a65 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a66 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a67 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a96 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a97 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a98 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a99 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v235, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v235, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v235, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v235, s[4:7], 0 offen offset:12 + v_add_i32 v235, v235, 64 + v_accvgpr_read_b32 v8, a4 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a5 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a6 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a7 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a36 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a37 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a38 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a39 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v236, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v236, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v236, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v236, s[4:7], 0 offen offset:12 + v_add_i32 v236, v236, 64 + v_accvgpr_read_b32 v8, a68 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a69 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a70 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a71 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a100 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a101 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a102 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a103 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v236, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v236, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v236, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v236, s[4:7], 0 offen offset:12 + v_add_i32 v236, v236, 64 + v_accvgpr_read_b32 v8, a8 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a9 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a10 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a11 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a40 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a41 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a42 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a43 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v237, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v237, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v237, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v237, s[4:7], 0 offen offset:12 + v_add_i32 v237, v237, 64 + v_accvgpr_read_b32 v8, a72 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a73 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a74 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a75 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a104 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a105 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a106 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a107 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v237, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v237, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v237, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v237, s[4:7], 0 offen offset:12 + v_add_i32 v237, v237, 64 + v_accvgpr_read_b32 v8, a12 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a13 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a14 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a15 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a44 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a45 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a46 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a47 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v238, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v238, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v238, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v238, s[4:7], 0 offen offset:12 + v_add_i32 v238, v238, 64 + v_accvgpr_read_b32 v8, a76 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a77 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a78 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a79 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a108 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a109 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a110 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a111 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v238, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v238, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v238, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v238, s[4:7], 0 offen offset:12 + v_add_i32 v238, v238, 64 + v_accvgpr_read_b32 v8, a16 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a17 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a18 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a19 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a48 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a49 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a50 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a51 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v239, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v239, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v239, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v239, s[4:7], 0 offen offset:12 + v_add_i32 v239, v239, 64 + v_accvgpr_read_b32 v8, a80 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a81 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a82 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a83 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a112 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a113 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a114 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a115 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v239, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v239, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v239, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v239, s[4:7], 0 offen offset:12 + v_add_i32 v239, v239, 64 + v_accvgpr_read_b32 v8, a20 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a21 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a22 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a23 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a52 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a53 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a54 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a55 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v240, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v240, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v240, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v240, s[4:7], 0 offen offset:12 + v_add_i32 v240, v240, 64 + v_accvgpr_read_b32 v8, a84 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a85 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a86 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a87 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a116 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a117 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a118 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a119 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v240, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v240, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v240, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v240, s[4:7], 0 offen offset:12 + v_add_i32 v240, v240, 64 + v_accvgpr_read_b32 v8, a24 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a25 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a26 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a27 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a56 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a57 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a58 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a59 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v241, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v241, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v241, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v241, s[4:7], 0 offen offset:12 + v_add_i32 v241, v241, 64 + v_accvgpr_read_b32 v8, a88 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a89 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a90 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a91 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a120 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a121 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a122 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a123 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v241, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v241, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v241, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v241, s[4:7], 0 offen offset:12 + v_add_i32 v241, v241, 64 + v_accvgpr_read_b32 v8, a28 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a29 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a30 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a31 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a60 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a61 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a62 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a63 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v242, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v242, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v242, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v242, s[4:7], 0 offen offset:12 + v_add_i32 v242, v242, 64 + v_accvgpr_read_b32 v8, a92 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a93 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a94 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a95 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a124 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a125 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a126 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a127 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v242, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v242, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v242, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v242, s[4:7], 0 offen offset:12 + v_add_i32 v242, v242, 64 + v_accvgpr_read_b32 v8, a128 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a129 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a130 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a131 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a160 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a161 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a162 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a163 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v243, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v243, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v243, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v243, s[4:7], 0 offen offset:12 + v_add_i32 v243, v243, 64 + v_accvgpr_read_b32 v8, a192 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a193 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a194 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a195 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a224 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a225 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a226 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a227 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v243, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v243, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v243, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v243, s[4:7], 0 offen offset:12 + v_add_i32 v243, v243, 64 + v_accvgpr_read_b32 v8, a132 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a133 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a134 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a135 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a164 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a165 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a166 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a167 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v244, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v244, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v244, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v244, s[4:7], 0 offen offset:12 + v_add_i32 v244, v244, 64 + v_accvgpr_read_b32 v8, a196 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a197 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a198 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a199 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a228 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a229 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a230 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a231 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v244, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v244, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v244, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v244, s[4:7], 0 offen offset:12 + v_add_i32 v244, v244, 64 + v_accvgpr_read_b32 v8, a136 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a137 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a138 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a139 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a168 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a169 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a170 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a171 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v245, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v245, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v245, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v245, s[4:7], 0 offen offset:12 + v_add_i32 v245, v245, 64 + v_accvgpr_read_b32 v8, a200 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a201 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a202 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a203 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a232 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a233 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a234 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a235 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v245, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v245, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v245, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v245, s[4:7], 0 offen offset:12 + v_add_i32 v245, v245, 64 + v_accvgpr_read_b32 v8, a140 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a141 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a142 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a143 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a172 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a173 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a174 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a175 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v246, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v246, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v246, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v246, s[4:7], 0 offen offset:12 + v_add_i32 v246, v246, 64 + v_accvgpr_read_b32 v8, a204 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a205 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a206 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a207 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a236 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a237 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a238 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a239 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v246, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v246, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v246, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v246, s[4:7], 0 offen offset:12 + v_add_i32 v246, v246, 64 + v_accvgpr_read_b32 v8, a144 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a145 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a146 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a147 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a176 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a177 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a178 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a179 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v247, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v247, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v247, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v247, s[4:7], 0 offen offset:12 + v_add_i32 v247, v247, 64 + v_accvgpr_read_b32 v8, a208 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a209 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a210 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a211 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a240 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a241 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a242 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a243 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v247, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v247, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v247, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v247, s[4:7], 0 offen offset:12 + v_add_i32 v247, v247, 64 + v_accvgpr_read_b32 v8, a148 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a149 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a150 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a151 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a180 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a181 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a182 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a183 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v248, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v248, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v248, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v248, s[4:7], 0 offen offset:12 + v_add_i32 v248, v248, 64 + v_accvgpr_read_b32 v8, a212 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a213 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a214 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a215 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a244 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a245 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a246 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a247 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v248, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v248, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v248, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v248, s[4:7], 0 offen offset:12 + v_add_i32 v248, v248, 64 + v_accvgpr_read_b32 v8, a152 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a153 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a154 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a155 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a184 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a185 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a186 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a187 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v249, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v249, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v249, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v249, s[4:7], 0 offen offset:12 + v_add_i32 v249, v249, 64 + v_accvgpr_read_b32 v8, a216 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a217 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a218 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a219 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a248 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a249 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a250 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a251 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v249, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v249, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v249, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v249, s[4:7], 0 offen offset:12 + v_add_i32 v249, v249, 64 + v_accvgpr_read_b32 v8, a156 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a157 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a158 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a159 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a188 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a189 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a190 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a191 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v250, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v250, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v250, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v250, s[4:7], 0 offen offset:12 + v_add_i32 v250, v250, 64 + v_accvgpr_read_b32 v8, a220 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a221 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a222 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a223 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a252 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a253 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a254 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a255 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_atomic_pk_add_bf16 v16, v250, s[4:7], 0 offen + buffer_atomic_pk_add_bf16 v17, v250, s[4:7], 0 offen offset:4 + buffer_atomic_pk_add_bf16 v18, v250, s[4:7], 0 offen offset:8 + buffer_atomic_pk_add_bf16 v19, v250, s[4:7], 0 offen offset:12 + v_add_i32 v250, v250, 64 + s_branch label_19CC + +label_14AC: + v_accvgpr_read_b32 v8, a0 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a1 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a2 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a3 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a32 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a33 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a34 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a35 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v235, s[4:7], 0 offen + v_add_i32 v235, v235, 64 + v_accvgpr_read_b32 v8, a64 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a65 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a66 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a67 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a96 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a97 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a98 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a99 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v235, s[4:7], 0 offen + v_add_i32 v235, v235, 64 + v_accvgpr_read_b32 v8, a4 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a5 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a6 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a7 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a36 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a37 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a38 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a39 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v236, s[4:7], 0 offen + v_add_i32 v236, v236, 64 + v_accvgpr_read_b32 v8, a68 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a69 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a70 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a71 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a100 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a101 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a102 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a103 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v236, s[4:7], 0 offen + v_add_i32 v236, v236, 64 + v_accvgpr_read_b32 v8, a8 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a9 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a10 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a11 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a40 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a41 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a42 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a43 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v237, s[4:7], 0 offen + v_add_i32 v237, v237, 64 + v_accvgpr_read_b32 v8, a72 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a73 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a74 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a75 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a104 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a105 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a106 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a107 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v237, s[4:7], 0 offen + v_add_i32 v237, v237, 64 + v_accvgpr_read_b32 v8, a12 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a13 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a14 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a15 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a44 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a45 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a46 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a47 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v238, s[4:7], 0 offen + v_add_i32 v238, v238, 64 + v_accvgpr_read_b32 v8, a76 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a77 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a78 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a79 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a108 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a109 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a110 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a111 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v238, s[4:7], 0 offen + v_add_i32 v238, v238, 64 + v_accvgpr_read_b32 v8, a16 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a17 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a18 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a19 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a48 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a49 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a50 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a51 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v239, s[4:7], 0 offen + v_add_i32 v239, v239, 64 + v_accvgpr_read_b32 v8, a80 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a81 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a82 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a83 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a112 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a113 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a114 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a115 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v239, s[4:7], 0 offen + v_add_i32 v239, v239, 64 + v_accvgpr_read_b32 v8, a20 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a21 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a22 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a23 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a52 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a53 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a54 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a55 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v240, s[4:7], 0 offen + v_add_i32 v240, v240, 64 + v_accvgpr_read_b32 v8, a84 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a85 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a86 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a87 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a116 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a117 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a118 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a119 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v240, s[4:7], 0 offen + v_add_i32 v240, v240, 64 + v_accvgpr_read_b32 v8, a24 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a25 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a26 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a27 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a56 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a57 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a58 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a59 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v241, s[4:7], 0 offen + v_add_i32 v241, v241, 64 + v_accvgpr_read_b32 v8, a88 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a89 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a90 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a91 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a120 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a121 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a122 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a123 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v241, s[4:7], 0 offen + v_add_i32 v241, v241, 64 + v_accvgpr_read_b32 v8, a28 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a29 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a30 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a31 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a60 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a61 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a62 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a63 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v242, s[4:7], 0 offen + v_add_i32 v242, v242, 64 + v_accvgpr_read_b32 v8, a92 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a93 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a94 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a95 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a124 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a125 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a126 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a127 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v242, s[4:7], 0 offen + v_add_i32 v242, v242, 64 + v_accvgpr_read_b32 v8, a128 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a129 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a130 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a131 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a160 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a161 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a162 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a163 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v243, s[4:7], 0 offen + v_add_i32 v243, v243, 64 + v_accvgpr_read_b32 v8, a192 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a193 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a194 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a195 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a224 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a225 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a226 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a227 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v243, s[4:7], 0 offen + v_add_i32 v243, v243, 64 + v_accvgpr_read_b32 v8, a132 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a133 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a134 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a135 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a164 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a165 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a166 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a167 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v244, s[4:7], 0 offen + v_add_i32 v244, v244, 64 + v_accvgpr_read_b32 v8, a196 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a197 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a198 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a199 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a228 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a229 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a230 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a231 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v244, s[4:7], 0 offen + v_add_i32 v244, v244, 64 + v_accvgpr_read_b32 v8, a136 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a137 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a138 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a139 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a168 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a169 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a170 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a171 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v245, s[4:7], 0 offen + v_add_i32 v245, v245, 64 + v_accvgpr_read_b32 v8, a200 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a201 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a202 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a203 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a232 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a233 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a234 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a235 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v245, s[4:7], 0 offen + v_add_i32 v245, v245, 64 + v_accvgpr_read_b32 v8, a140 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a141 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a142 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a143 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a172 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a173 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a174 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a175 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v246, s[4:7], 0 offen + v_add_i32 v246, v246, 64 + v_accvgpr_read_b32 v8, a204 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a205 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a206 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a207 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a236 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a237 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a238 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a239 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v246, s[4:7], 0 offen + v_add_i32 v246, v246, 64 + v_accvgpr_read_b32 v8, a144 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a145 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a146 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a147 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a176 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a177 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a178 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a179 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v247, s[4:7], 0 offen + v_add_i32 v247, v247, 64 + v_accvgpr_read_b32 v8, a208 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a209 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a210 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a211 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a240 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a241 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a242 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a243 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v247, s[4:7], 0 offen + v_add_i32 v247, v247, 64 + v_accvgpr_read_b32 v8, a148 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a149 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a150 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a151 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a180 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a181 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a182 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a183 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v248, s[4:7], 0 offen + v_add_i32 v248, v248, 64 + v_accvgpr_read_b32 v8, a212 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a213 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a214 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a215 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a244 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a245 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a246 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a247 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v248, s[4:7], 0 offen + v_add_i32 v248, v248, 64 + v_accvgpr_read_b32 v8, a152 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a153 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a154 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a155 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a184 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a185 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a186 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a187 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v249, s[4:7], 0 offen + v_add_i32 v249, v249, 64 + v_accvgpr_read_b32 v8, a216 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a217 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a218 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a219 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a248 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a249 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a250 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a251 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v249, s[4:7], 0 offen + v_add_i32 v249, v249, 64 + v_accvgpr_read_b32 v8, a156 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a157 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a158 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a159 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a188 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a189 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a190 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a191 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v250, s[4:7], 0 offen + v_add_i32 v250, v250, 64 + v_accvgpr_read_b32 v8, a220 + v_mul_f32_e32 v8, s38, v8 + v_accvgpr_read_b32 v9, a221 + v_mul_f32_e32 v9, s38, v9 + v_accvgpr_read_b32 v10, a222 + v_mul_f32_e32 v10, s38, v10 + v_accvgpr_read_b32 v11, a223 + v_mul_f32_e32 v11, s38, v11 + v_accvgpr_read_b32 v12, a252 + v_mul_f32_e32 v12, s38, v12 + v_accvgpr_read_b32 v13, a253 + v_mul_f32_e32 v13, s38, v13 + v_accvgpr_read_b32 v14, a254 + v_mul_f32_e32 v14, s38, v14 + v_accvgpr_read_b32 v15, a255 + v_mul_f32_e32 v15, s38, v15 + v_cvt_pk_bf16_f32 v16, v8, v9 + v_cvt_pk_bf16_f32 v17, v10, v11 + v_cvt_pk_bf16_f32 v18, v12, v13 + v_cvt_pk_bf16_f32 v19, v14, v15 + s_nop 1 + v_permlane16_swap_b32_e32 v16, v18 + s_nop 1 + v_permlane16_swap_b32_e32 v17, v19 + s_nop 1 + buffer_store_dwordx4 v[16:19], v250, s[4:7], 0 offen + v_add_i32 v250, v250, 64 + +label_19CC: + s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) + s_endpgm + +// ===== Kernel Descriptor (generates .rodata) ===== +.rodata +.p2align 6 +.amdhsa_kernel _ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E + .amdhsa_next_free_vgpr 512 + .amdhsa_next_free_sgpr .amdgcn.next_free_sgpr + .amdhsa_group_segment_fixed_size 163840 + .amdhsa_accum_offset 256 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 1 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_vgpr_workitem_id 0 +.end_amdhsa_kernel + +// ===== AMDGPU Metadata ===== +.amdgpu_metadata +--- +amdhsa.kernels: + - .args: + - .actual_access: read_write + .address_space: global + .name: D + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 8 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: C + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 24 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: A + .offset: 32 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 40 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: B + .offset: 48 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 56 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .name: alpha + .offset: 64 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 68 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 72 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 76 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: beta + .offset: 80 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 84 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 88 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 92 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideD0 + .offset: 96 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 100 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 104 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 108 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideD1 + .offset: 112 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 116 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 120 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 124 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideC0 + .offset: 128 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 132 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 136 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 140 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideC1 + .offset: 144 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 148 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 152 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 156 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideA0 + .offset: 160 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 164 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 168 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 172 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideA1 + .offset: 176 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 180 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 184 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 188 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideB0 + .offset: 192 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 196 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 200 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 204 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideB1 + .offset: 208 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 212 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 216 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 220 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Mdim + .offset: 224 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 228 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 232 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 236 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Ndim + .offset: 240 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 244 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 248 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 252 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: Kdim + .offset: 256 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 260 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 264 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 268 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: ScaleA + .offset: 272 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 280 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .actual_access: read_only + .address_space: global + .name: ScaleB + .offset: 288 + .size: 8 + .value_kind: global_buffer + - .name: pad + .offset: 296 + .size: 8 + .value_kind: by_value + .value_type: i32 + - .name: strideScaleA0 + .offset: 304 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 308 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 312 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 316 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideScaleA1 + .offset: 320 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 324 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 328 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 332 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideScaleB0 + .offset: 336 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 340 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 344 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 348 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: strideScaleB1 + .offset: 352 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 356 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 360 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 364 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: log2_k_split + .offset: 368 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 372 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 376 + .size: 4 + .value_kind: by_value + .value_type: i32 + - .name: pad + .offset: 380 + .size: 4 + .value_kind: by_value + .value_type: i32 + .group_segment_fixed_size: 163840 + .kernarg_segment_align: 4 + .kernarg_segment_size: 384 + .max_flat_workgroup_size: 256 + .name: _ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E + .private_segment_fixed_size: 0 + .reqd_workgroup_size: + - 256 + - 1 + - 1 + .sgpr_count: 96 + .symbol: _ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.kd + .vgpr_count: 512 + .wavefront_size: 64 +amdhsa.version: + - 1 + - 0 +... +.end_amdgpu_metadata + diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Problem.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Problem.py index d4c956656add..4c8d9828d158 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Problem.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Problem.py @@ -573,6 +573,7 @@ def getRealDataTypeB(dataType): ("F8B8N", "F8N", "S"), ("B8F8N", "F8N", "S"), ("F4", "S", "S"), + ("F4", "B", "S"), ("F6", "S", "S"), ("B6", "S", "S"), ] @@ -587,6 +588,7 @@ def getRealDataTypeB(dataType): ("B6", "S", "S"), ("B6F6", "S", "S"), ("F4", "S", "S"), + ("F4", "B", "S"), ("F8", "H", "S"), ("F8B8", "H", "S"), ("B8", "H", "S"), diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index 1c8a238cea84..61f39cef914a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -16,19 +16,6 @@ GlobalParameters: PrintSolutionRejectionReason: True DeviceLDS: 163840 MaxLDS: 163840 - # PrintTensorA: 1 - # PrintTensorB: 1 - # PrintTensorD: 2 - # PrintTensorRef: 2 - # NumWarmups: 20 # eqvlnt to cold-iter for hipblaslt - # EnqueuesPerSync: 1000 - # DataInitTypeA: 12 # TrigSin (problem dependant) - # DataInitTypeB: 13 # TrigCos (problem dependant) - # KeepBuildTmp: True - # ClientLogLevel: 3 # Debug level - includes rejection reasons - # KernelTime: True - # BoundsCheck: 2 - # RotatingBufferSize: 512 BenchmarkProblems: - @@ -73,6 +60,7 @@ BenchmarkProblems: { type: uint32, semantic: SplitK, padding: 12 }, { type: uint32, semantic: OutputBF16, padding: 12 } ] macrotile: [256, 256, 64] + padProblemSizeToTile: [true, true] # M, N threads: [256, 1, 1] grid: [TilesX, TilesY, One] - MatrixInstruction: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml new file mode 100644 index 000000000000..c7089094897d --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -0,0 +1,118 @@ +TestParameters: + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + DeviceLDS: 163840 + MaxLDS: 163840 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: F4 + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + SwizzleTensorA: True + SwizzleTensorB: False + MXBlockA: 32 + MXBlockB: 32 + + - # BenchmarkProblemSizeGroup - Standard - All problem + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E" + args: [ { type: address, semantic: AddressD, padding: 8 }, + { type: address, semantic: AddressC, padding: 8 }, + { type: address, semantic: AddressB, padding: 8 }, + { type: address, semantic: AddressA, padding: 8 }, + { type: float32, semantic: Alpha, padding: 12 }, + { type: float32, semantic: Beta, padding: 12 }, + { type: uint32, semantic: StrideD0, padding: 12 }, + { type: uint32, semantic: StrideD1, padding: 12 }, + { type: uint32, semantic: StrideC0, padding: 12 }, + { type: uint32, semantic: StrideC1, padding: 12 }, + { type: uint32, semantic: StrideB0, padding: 12 }, + { type: uint32, semantic: StrideB1, padding: 12 }, + { type: uint32, semantic: StrideA0, padding: 12 }, + { type: uint32, semantic: StrideA1, padding: 12 }, + { type: uint32, semantic: SizeFree1, padding: 12 }, + { type: uint32, semantic: SizeFree0, padding: 12 }, + { type: uint32, semantic: SizeSum, padding: 12 }, + { type: address, semantic: AddressScaleB, padding: 8 }, + { type: address, semantic: AddressScaleA, padding: 8 }, + { type: uint32, semantic: StrideScaleB0, padding: 12 }, + { type: uint32, semantic: StrideScaleB1, padding: 12 }, + { type: uint32, semantic: StrideScaleA0, padding: 12 }, + { type: uint32, semantic: StrideScaleA1, padding: 12 }, + { type: uint32, semantic: SplitK, padding: 12 } ] + macrotile: [256, 256, 256] + padProblemSizeToTile: [true, true] # M, N + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + - MatrixInstruction: + - [16, 16, 128, 1, 1, 8, 8, 2, 2] # 256 x 256 + - PreloadKernArgs: [False] + - DepthU: [256] + - VectorWidthA: [-1] + - VectorWidthB: [-1] + - GlobalReadVectorWidthA: [-1] + - GlobalReadVectorWidthB: [-1] + - LocalReadVectorWidth: [-1] + - TransposeLDS: [-1] + - LdsBlockSizePerPadA: [-1] + - LdsBlockSizePerPadB: [-1] + - LdsPadA: [-1] + - LdsPadB: [-1] + - StaggerU: [16] + - StaggerUStride: [-1] + - WorkGroupMapping: [1] + - StaggerUMapping: [0] + - 1LDSBuffer: [-1] + - WorkGroupMappingXCC: [8] + - WorkGroupMappingXCCGroup: [-1] + - GlobalSplitU: [1] + - GlobalSplitUAlgorithm: ["MultipleBuffer"] + - GlobalReadPerMfma: [1] + - LocalWritePerMfma: [-1] + - StoreRemapVectorWidth: [0] + - StoreVectorWidth: [-1] + - SourceSwap: [1] + - NumElementsPerBatchStore: [16] + - ClusterLocalRead: [1] + - NonTemporalA: [0] + - NonTemporalB: [0] + - DirectToVgprA: [1] + - DirectToVgprB: [0] + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + - Exact: [4096, 4096, 1, 8192] + +LibraryLogic: + ScheduleName: "gfx950" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx950" + LibraryType: "GridBased" diff --git a/projects/hipblaslt/tensilelite/client/CMakeLists.txt b/projects/hipblaslt/tensilelite/client/CMakeLists.txt index c4c9901e898c..d397da2de381 100644 --- a/projects/hipblaslt/tensilelite/client/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/client/CMakeLists.txt @@ -5,12 +5,22 @@ add_executable(tensilelite-client "${CMAKE_CURRENT_SOURCE_DIR}/main.cpp") add_executable(cpu-gemm-driver "${CMAKE_CURRENT_SOURCE_DIR}/cpu_gemm_driver.cpp") +if(NOT TARGET roc::mxDataGenerator) + if(HIPBLASLT_ENABLE_THEROCK) + find_package(mxDataGenerator REQUIRED) + else() + add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/../../../../shared/mxdatagenerator" + "${CMAKE_CURRENT_BINARY_DIR}/mxdatagenerator") + endif() +endif() + set(COMMON_CLIENT_LIBS hip::device hip::host tensilelite::tensilelite-host rocisa::rocisa-cpp OpenMP::OpenMP_CXX + roc::mxDataGenerator ) if(NOT WIN32) @@ -30,7 +40,7 @@ foreach(target tensilelite-client cpu-gemm-driver) target_compile_definitions(${target} PRIVATE TENSILE_DEFAULT_SERIALIZATION) set_target_properties(${target} PROPERTIES - CXX_STANDARD 17 + CXX_STANDARD 20 CXX_STANDARD_REQUIRED ON CXX_EXTENSIONS OFF ) diff --git a/projects/hipblaslt/tensilelite/client/include/DataInitialization.hpp b/projects/hipblaslt/tensilelite/client/include/DataInitialization.hpp index b07bf7ca9444..eaa3dc7bae9d 100644 --- a/projects/hipblaslt/tensilelite/client/include/DataInitialization.hpp +++ b/projects/hipblaslt/tensilelite/client/include/DataInitialization.hpp @@ -2419,8 +2419,8 @@ namespace TensileLite Float4x2 value; } x; - uint8_t val0 = static_cast(rand() % 15); - uint8_t val1 = static_cast(rand() % 15); + uint8_t val0 = static_cast(rand() % 16); + uint8_t val1 = static_cast(rand() % 16); x.bits = (val1 << 4) | val0; return x.value; } diff --git a/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp b/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp index 5a9816a1dfb1..d35bb4d83bc6 100644 --- a/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp +++ b/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp @@ -95,6 +95,9 @@ namespace TensileLite size_t m_benchmarkRun = 0; bool m_runOnce = false; + + std::vector> m_originalProblemSizes; + size_t m_currentProblemIdx = 0; }; } // namespace Client } // namespace TensileLite diff --git a/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp b/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp index c3a65cf33aba..48f9920891a0 100644 --- a/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp +++ b/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp @@ -151,6 +151,9 @@ namespace TensileLite bool m_printTensorAmaxD; bool m_printAny; + std::vector> m_originalProblemSizes; + size_t m_currentProblemIdx = 0; + int m_numBenchmarkRuns = 0; bool m_validatedSolution = false; diff --git a/projects/hipblaslt/tensilelite/client/include/TypedId.hpp b/projects/hipblaslt/tensilelite/client/include/TypedId.hpp index 2fd1d8c2509d..d5c83c775537 100644 --- a/projects/hipblaslt/tensilelite/client/include/TypedId.hpp +++ b/projects/hipblaslt/tensilelite/client/include/TypedId.hpp @@ -244,6 +244,9 @@ namespace TensileLite #ifdef TENSILE_USE_FP4 using TypedGemm_F4_S_S = TypedGemm; #endif // TENSILE_USE_FP4 +#if defined(TENSILE_USE_FP4) && defined(TENSILE_USE_BF16) + using TypedGemm_F4_B_S = TypedGemm; +#endif // defined(TENSILE_USE_FP4) && defined(TENSILE_USE_BF16) #if defined(TENSILE_USE_FP4) && defined(TENSILE_USE_FP6) using TypedGemm_F4F6_S_S = TypedGemm; using TypedGemm_F6F4_S_S = TypedGemm; diff --git a/projects/hipblaslt/tensilelite/client/main.cpp b/projects/hipblaslt/tensilelite/client/main.cpp index a986f7e05060..c1f4a91ff0d7 100644 --- a/projects/hipblaslt/tensilelite/client/main.cpp +++ b/projects/hipblaslt/tensilelite/client/main.cpp @@ -300,6 +300,9 @@ namespace TensileLite ("problem-size,p", vector_default_empty(), "Specify a problem size. Comma-separated list of " "sizes, in the order of the Einstein notation.") + ("original-problem-size", vector_default_empty(), "Original problem sizes before macrotile padding. " + "When present, validation uses these sizes to slice output.") + ("prob-sol-map", vector_default_empty(), "[probIdx, solIdx]") ("a-strides", vector_default_empty(), "Unspecified means default stride " @@ -853,6 +856,7 @@ namespace TensileLite fix_data_types(args); parse_arg_ints(args, "problem-size"); + parse_arg_ints(args, "original-problem-size"); parse_arg_ints(args, "a-strides"); parse_arg_ints(args, "b-strides"); parse_arg_ints(args, "c-strides"); @@ -974,6 +978,8 @@ int main(int argc, const char* argv[]) std::shared_ptr dataInit; { + // Re-seed before data init: HIP runtime init above may consume rand() non-deterministically + srand(seed); ScopedTimer timer("data_init_setup"); dataInit = std::make_shared(args, problemFactory); } diff --git a/projects/hipblaslt/tensilelite/client/src/CMakeLists.txt b/projects/hipblaslt/tensilelite/client/src/CMakeLists.txt index 5ca2209319bd..4c02c094758d 100644 --- a/projects/hipblaslt/tensilelite/client/src/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/client/src/CMakeLists.txt @@ -21,11 +21,22 @@ set(COMMON_CLIENT_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/CSVStackFile.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/SolutionIterator.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/LibraryUpdateReporter.cpp" + "${CMAKE_CURRENT_SOURCE_DIR}/../../../clients/common/src/mxDataGen.cpp" ) target_sources(tensilelite-client PRIVATE ${COMMON_CLIENT_SOURCES}) target_sources(cpu-gemm-driver PRIVATE ${COMMON_CLIENT_SOURCES}) +target_include_directories(tensilelite-client + PRIVATE + "${CMAKE_CURRENT_SOURCE_DIR}/../../../clients/common/include" +) + +target_include_directories(cpu-gemm-driver + PRIVATE + "${CMAKE_CURRENT_SOURCE_DIR}/../../../clients/common/include" +) + if (TENSILELITE_CLIENT_ENABLE_ROCPROFSDK) target_sources(tensilelite-client diff --git a/projects/hipblaslt/tensilelite/client/src/DataInitialization.cpp b/projects/hipblaslt/tensilelite/client/src/DataInitialization.cpp index 533955e631aa..5c6a8329f12c 100644 --- a/projects/hipblaslt/tensilelite/client/src/DataInitialization.cpp +++ b/projects/hipblaslt/tensilelite/client/src/DataInitialization.cpp @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -135,6 +136,8 @@ namespace TensileLite case rocisa::DataType::E8: case rocisa::DataType::E5M3: return 8; + case rocisa::DataType::Float4: + return 4; default: throw std::runtime_error("unsupported datatype"); } @@ -378,6 +381,10 @@ namespace TensileLite MiK = 32; MiKv = 8; break; + case rocisa::DataType::Float4: + MiK = 32; + MiKv = 16; + break; default: throw std::runtime_error("unsupported datatype for swizzling"); } @@ -880,8 +887,8 @@ namespace TensileLite const auto m_n = desc.sizes()[1]; const auto b = desc.sizes()[2]; const auto swizzleK = miK * packK; - const auto paddedM_N = (m_n + miM_N - 1) / miM_N * miM_N; - const auto paddedK = (k + swizzleK - 1) / swizzleK * swizzleK; + const auto paddedM_N = DGen::roundUp(m_n, miM_N); + const auto paddedK = DGen::roundUp(k, swizzleK); return paddedM_N * paddedK * b; } @@ -2113,28 +2120,51 @@ namespace TensileLite if(needSwizzle) { using Tensor = Tensor::Manipulation::Tensor; - // currently, if A then it means MiM = 16, if B then it means MiN = 16 size_t MiM_N = 16, MiK = 0, MiKv = 0, PackK = 0; calculateKforSwizzling(desc.dataType(), MiK, MiKv, PackK); - auto unrolledSize = desc.sizes()[0]; - auto tiledSize = desc.sizes()[1]; + auto unrolledSize = desc.sizes()[0]; + auto tiledSize = desc.sizes()[1]; + + // Sub-byte types (e.g. FP4 = 0.5 bytes/elem) need special handling: + // The swizzle reshape/permute operates on byte-granularity tensors, so + // we convert element counts to byte counts and treat each byte as one + // "element" for the reshape dimensions. + bool isSubByte = (desc.elementBytes() < 1.0f); + float effectiveElem = isSubByte ? 1.0f : desc.elementBytes(); + size_t effUnrolled = isSubByte + ? multiplyElementSize(unrolledSize, desc.elementBytes()) + : unrolledSize; + size_t effMiK = isSubByte + ? size_t(MiK * PackK * desc.elementBytes()) : MiK; + size_t effMiKv = isSubByte + ? size_t(MiKv * PackK * desc.elementBytes()) : MiKv; + size_t effPackK = isSubByte ? size_t(1) : PackK; + ::Tensor::Manipulation::Shape paddedShape{ - ((tiledSize / MiM_N) + !!(tiledSize % MiM_N)) * MiM_N, - (unrolledSize / (MiK * PackK) + !!(unrolledSize % (MiK * PackK))) * MiK - * PackK}; + DGen::roundUp(tiledSize, MiM_N), + DGen::roundUp(effUnrolled, effMiK * effPackK)}; auto swizzleKey = std::make_tuple(toBitWidth(desc.dataType()), unrolledSize, tiledSize); + // Convert byte-granularity flat size back to native element count + // for the GPU copy (e.g. FP4: 2 elements per byte) + auto flatToNativeElems = [&](size_t flatSize) -> size_t { + return isSubByte + ? size_t(flatSize / desc.elementBytes()) + : flatSize; + }; + if(g_swizzleCache.count(swizzleKey)) { if(swizzleKey != g_swizzleCache.back()) { Tensor& permuted = g_swizzleCache.at(swizzleKey); - ptr = copyInputBuffers(desc, - p.gpuInput.valid.get(), - permuted.as(), - permuted.getDesc().flattenSize(), - hipMemcpyHostToDevice); + ptr = copyInputBuffers( + desc, + p.gpuInput.valid.get(), + permuted.as(), + flatToNativeElems(permuted.getDesc().flattenSize()), + hipMemcpyHostToDevice); } else { @@ -2143,25 +2173,25 @@ namespace TensileLite } else { - auto tmpTensor = Tensor({tiledSize, unrolledSize}, desc.elementBytes()); - - memcpy( - tmpTensor.as(), p.cpuInput.valid.get(), tmpTensor.getNumBytes()); - //Temporary hack + auto tmpTensor = Tensor({tiledSize, effUnrolled}, effectiveElem); + memcpy(tmpTensor.as(), + p.cpuInput.valid.get(), + tmpTensor.getNumBytes()); uint64_t padVal{}; auto paddedTensor = ::Tensor::Manipulation::pad( - tmpTensor, paddedShape, &padVal, tmpTensor.getElementSize()); + tmpTensor, paddedShape, &padVal, effectiveElem); paddedTensor.reshape({paddedShape[0] / MiM_N, MiM_N, - paddedShape[1] / (MiK * PackK), - MiK / MiKv, - MiKv * PackK}); + paddedShape[1] / (effMiK * effPackK), + effMiK / effMiKv, + effMiKv * effPackK}); Tensor permuted = permute(paddedTensor, {0, 2, 3, 1, 4}); - ptr = copyInputBuffers(desc, - p.gpuInput.valid.get(), - permuted.as(), - permuted.getDesc().flattenSize(), - hipMemcpyHostToDevice); + ptr = copyInputBuffers( + desc, + p.gpuInput.valid.get(), + permuted.as(), + flatToNativeElems(permuted.getDesc().flattenSize()), + hipMemcpyHostToDevice); g_swizzleCache.emplace(swizzleKey, std::move(permuted)); } } diff --git a/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp b/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp index 9a5524c59aa5..faed2f5b560f 100644 --- a/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp +++ b/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp @@ -39,6 +39,13 @@ namespace TensileLite ProgressListener::ProgressListener(po::variables_map const& args) : m_runOnce(args["selection-only"].as()) { + if(args.count("original-problem-size")) + { + auto const& parsed + = args["original-problem-size"].as>>(); + if(!parsed.empty()) + m_originalProblemSizes = parsed; + } } bool ProgressListener::needMoreBenchmarkRuns() const @@ -108,7 +115,21 @@ namespace TensileLite else if(auto gemmProblem = dynamic_cast(problem)) { writeReport(*gemmProblem); - m_reporter->report(ResultKey::ProblemSizes, gemmProblem->problemSizes()); + // Report the original (unpadded) problem sizes when macrotile padding + // was applied, also override LDD/LDC to keep strides consistent. + if(m_currentProblemIdx < m_originalProblemSizes.size()) + { + auto const& origSizes = m_originalProblemSizes[m_currentProblemIdx]; + m_reporter->report(ResultKey::ProblemSizes, origSizes); + if(origSizes.size() >= 1 + && origSizes[0] != gemmProblem->d().sizes()[0]) + { + m_reporter->report(ResultKey::LDD, origSizes[0]); + m_reporter->report(ResultKey::LDC, origSizes[0]); + } + } + else + m_reporter->report(ResultKey::ProblemSizes, gemmProblem->problemSizes()); } else { @@ -116,7 +137,10 @@ namespace TensileLite } } - void ProgressListener::postProblem() {} + void ProgressListener::postProblem() + { + m_currentProblemIdx++; + } void ProgressListener::preSolution(ContractionSolution* const solution) { diff --git a/projects/hipblaslt/tensilelite/client/src/Reference.cpp b/projects/hipblaslt/tensilelite/client/src/Reference.cpp index 50242538971c..72fc9677f64b 100644 --- a/projects/hipblaslt/tensilelite/client/src/Reference.cpp +++ b/projects/hipblaslt/tensilelite/client/src/Reference.cpp @@ -2409,6 +2409,13 @@ namespace TensileLite problem, inputs, elementsToValidate); } #endif //TENSILE_USE_FP4 +#if defined(TENSILE_USE_FP4) && defined(TENSILE_USE_BF16) + case TypedGemm_F4_B_S::TypeId(): + { + return ReferenceSolution::SolveCPU( + problem, inputs, elementsToValidate); + } +#endif // defined(TENSILE_USE_FP4) && defined(TENSILE_USE_BF16) #if defined(TENSILE_USE_FP4) && defined(TENSILE_USE_FP6) case TypedGemm_F4F6_S_S::TypeId(): { diff --git a/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp b/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp index 3a80f2de4060..3adbfe414a96 100644 --- a/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp +++ b/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp @@ -61,6 +61,14 @@ namespace TensileLite || m_printTensorRef || m_printTensorBias || m_printTensorAmaxD; m_enabled = m_elementsToValidate != 0 || m_printAny; + + if(args.count("original-problem-size")) + { + auto const& parsed + = args["original-problem-size"].as>>(); + if(!parsed.empty()) + m_originalProblemSizes = parsed; + } } bool ReferenceValidator::needMoreBenchmarkRuns() const @@ -485,13 +493,54 @@ namespace TensileLite throw std::runtime_error("Unrecognized output tensor."); } + // When macrotile padding was applied, the actual GPU tensor D is larger + // than the user-requested problem. Validate only the original (unpadded) + // region so that padding artefacts don't cause false mismatches. + TensorDescriptor const* validationTensor = &tensor; + TensorDescriptor slicedTensor; + + if(static_cast(i) + == ContractionProblemGemm::TENSOR::D + && m_currentProblemIdx < m_originalProblemSizes.size()) + { + auto const& origSizes = m_originalProblemSizes[m_currentProblemIdx]; + if(origSizes.size() >= 2 + && (origSizes[0] != tensor.sizes()[0] + || origSizes[1] != tensor.sizes()[1])) + { + auto newSizes = tensor.sizes(); + newSizes[0] = origSizes[0]; + newSizes[1] = origSizes[1]; + slicedTensor = TensorDescriptor(tensor.getName().c_str(), + tensor.dataType(), + newSizes.begin(), + newSizes.end(), + tensor.strides().begin(), + tensor.strides().end()); + slicedTensor.setAsOutput(tensor.isOutput()); + validationTensor = &slicedTensor; + + if(m_elementsToValidate > 0 + && m_elementsToValidate + < slicedTensor.totalLogicalElements()) + validationStride = NextPrime( + slicedTensor.totalAllocatedElements() + / m_elementsToValidate); + } + } + if(Debug::Instance().printTensorInfo()) - std::cout << "Validating tensor " << tensor.getName() << ", cpu pointer " - << refPtr << ", gpu pointer " << resPtr + std::cout << "Validating tensor " << validationTensor->getName() + << ", cpu pointer " << refPtr << ", gpu pointer " << resPtr << ", size = " << result.maxElements[i] << std::endl; - - rv &= checkResults( - tensor, refPtr, resPtr, result.maxElements[i], result.gpu, validationStride, threshold); + + rv &= checkResults(*validationTensor, + refPtr, + resPtr, + result.maxElements[i], + result.gpu, + validationStride, + threshold); } return rv; } @@ -845,7 +894,10 @@ namespace TensileLite m_errorInSolution = false; } - void ReferenceValidator::postProblem() {} + void ReferenceValidator::postProblem() + { + m_currentProblemIdx++; + } void ReferenceValidator::finalizeReport() {} diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 416c21a765e8..97da69de50d2 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -59,6 +59,8 @@ namespace TensileLite X_MACRO(AddressB) \ X_MACRO(AddressC) \ X_MACRO(AddressD) \ + X_MACRO(AddressScaleA) \ + X_MACRO(AddressScaleB) \ X_MACRO(StrideA0) \ X_MACRO(StrideA1) \ X_MACRO(StrideB0) \ @@ -67,14 +69,18 @@ namespace TensileLite X_MACRO(StrideC1) \ X_MACRO(StrideD0) \ X_MACRO(StrideD1) \ - X_MACRO(Alpha) \ - X_MACRO(Beta) \ - X_MACRO(SplitK) \ - X_MACRO(OutputBF16) \ + X_MACRO(StrideScaleA0) \ + X_MACRO(StrideScaleA1) \ + X_MACRO(StrideScaleB0) \ + X_MACRO(StrideScaleB1) \ X_MACRO(StrideA0Bytes) \ X_MACRO(StrideB0Bytes) \ X_MACRO(StrideC0Bytes) \ X_MACRO(StrideD0Bytes) \ + X_MACRO(Alpha) \ + X_MACRO(Beta) \ + X_MACRO(SplitK) \ + X_MACRO(OutputBF16) \ X_MACRO(Padding) \ X_MACRO(DebugPattern) @@ -85,7 +91,7 @@ namespace TensileLite #undef X_MACRO COUNT, }; - + std::string toString(CustomArgSemantic arg); CustomArgSemantic fromStringCustomArgSemantic(std::string& str); std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t); diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index e8ee28914470..08312ce62d1a 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -37,6 +37,7 @@ #include #include +#include #include #include @@ -63,7 +64,7 @@ namespace TensileLite }; return CustomArgSemanticStrings[static_cast(arg)]; } - + CustomArgSemantic fromStringCustomArgSemantic(std::string& str) { static const std::map CustomArgSemanticMap = { @@ -71,7 +72,7 @@ namespace TensileLite CustomArgSemantic_MACRO #undef X_MACRO }; - + auto it = CustomArgSemanticMap.find(str); if (it == CustomArgSemanticMap.end()) throw std::runtime_error(concatenate("Invalid CustomArgSemantic value: ", str)); @@ -1740,7 +1741,14 @@ namespace TensileLite break; case CustomArgSemantic::SplitK: { - uint32_t splitK = (sizeMapping.globalSplitU > 0) ? sizeMapping.globalSplitU : 0; + // AITER kernel expects log2(GSU) rather than the raw GSU value + uint32_t gsu = sizeMapping.globalSplitU; + uint32_t splitK = 0; + if(gsu > 1) + { + while(gsu >>= 1) + splitK++; + } rv.args.appendCustomType("SplitK", splitK, arg.type); break; } @@ -1773,6 +1781,40 @@ namespace TensileLite rv.args.template append("DebugPattern", debugPattern); ++debugPattern; break; + case CustomArgSemantic::AddressScaleA: + rv.args.template append("AddressScaleA", inputs.mxsa); + break; + case CustomArgSemantic::AddressScaleB: + rv.args.template append("AddressScaleB", inputs.mxsb); + break; + case CustomArgSemantic::StrideScaleA0: + { + size_t scaleStride = problem.boundSize(0) / problem.mxBlockA(); + rv.args.appendCustomType("StrideScaleA0", scaleStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleA1: + { + auto const& t = problem.mxsa(); + size_t batchStride + = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + rv.args.appendCustomType("StrideScaleA1", batchStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleB0: + { + size_t scaleStride = problem.boundSize(0) / problem.mxBlockB(); + rv.args.appendCustomType("StrideScaleB0", scaleStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleB1: + { + auto const& t = problem.mxsb(); + size_t batchStride + = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + rv.args.appendCustomType("StrideScaleB1", batchStride, arg.type); + break; + } default: throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); } @@ -3508,26 +3550,29 @@ namespace TensileLite auto cInfo = DataTypeInfo::Get(problemType.cType); auto dInfo = DataTypeInfo::Get(problemType.dType); - spm.memReadBytesA = multiplyElementSize((NumBatches * M * N * K) / MT1, aInfo.elementSize); - spm.memReadBytesB = multiplyElementSize((NumBatches * M * N * K) / MT0, bInfo.elementSize); - spm.memReadBytesC = multiplyElementSize((NumBatches * M * N) * betaReads, cInfo.elementSize); + spm.memReadBytesA = (NumBatches * M * N * K) * aInfo.elementSize / aInfo.packing / MT1; + spm.memReadBytesB = (NumBatches * M * N * K) * bInfo.elementSize / bInfo.packing / MT0; + spm.memReadBytesC = (NumBatches * M * N) * betaReads * cInfo.elementSize / cInfo.packing; if(GlobalSplitU == 1) - spm.memWriteBytesD = multiplyElementSize((NumBatches * M * N) * (1 + betaWrites), dInfo.elementSize); + { + spm.memWriteBytesD = (NumBatches * M * N) * (1 + betaWrites) * dInfo.elementSize; + } else { bool hardwareAtomic = false; // TODO-model double atomicOperations = hardwareAtomic ? 2 : 3; // read-mod-write or cas //TODO-model double atomicCollisions = 1.0; // TODO-could be based on K, GSU - spm.memWriteBytesD = multiplyElementSize((NumBatches * M * N) + spm.memWriteBytesD = (NumBatches * M * N) * (betaWrites + atomicOperations * atomicCollisions) - , dInfo.elementSize); + * dInfo.elementSize; } spm.memReadBytes = spm.memReadBytesA + spm.memReadBytesB + spm.memReadBytesC; - spm.memGlobalReads = divideElementSize(spm.memReadBytesA, aInfo.elementSize) - + divideElementSize(spm.memReadBytesB, bInfo.elementSize) - + divideElementSize(spm.memReadBytesC, cInfo.elementSize); - spm.memGlobalWrites = divideElementSize(spm.memWriteBytesD, dInfo.elementSize); + + spm.memGlobalReads = spm.memReadBytesA * aInfo.packing / aInfo.elementSize + + spm.memReadBytesB * bInfo.packing / bInfo.elementSize + + spm.memReadBytesC * cInfo.packing / cInfo.elementSize; + spm.memGlobalWrites = spm.memWriteBytesD / dInfo.elementSize; return spm; } diff --git a/projects/hipblaslt/tensilelite/src/DataTypes.cpp b/projects/hipblaslt/tensilelite/src/DataTypes.cpp index 3383785fb90a..b988cab47fc0 100644 --- a/projects/hipblaslt/tensilelite/src/DataTypes.cpp +++ b/projects/hipblaslt/tensilelite/src/DataTypes.cpp @@ -102,7 +102,7 @@ namespace rocisa case rocisa::DataType::E5M3: return "E5M3"; case rocisa::DataType::Count: - ; + return "Invalid"; } return "Invalid"; } @@ -178,7 +178,7 @@ namespace rocisa case rocisa::DataType::E5M3: return TensileLite::TypeInfo::ElementSize; case rocisa::DataType::Count: - ; + return 1; } return 1; } From c4f080b54766b1b378321d331b1b84533538e5ae Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Wed, 29 Apr 2026 21:12:53 +0000 Subject: [PATCH 27/58] Demo calling a stream-k kernel --- .../tensilelite/Tensile/Contractions.py | 18 +- ...k_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s | 17944 ++++++++++++++++ .../Tensile/SolutionStructs/Solution.py | 4 +- .../Tests/custom/custom_tensile_sk.yaml | 98 + .../include/Tensile/ContractionSolution.hpp | 43 + .../include/Tensile/Serialization/Base.hpp | 14 + .../Serialization/ContractionSolution.hpp | 3 + .../tensilelite/src/ContractionSolution.cpp | 276 +- 8 files changed, 18358 insertions(+), 42 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index 3914cf5f3df6..06d8c558b95d 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -607,11 +607,25 @@ def FromOriginalState(cls, d, problemType, morePreds=[]): return cls.And(predicates) class CustomKernel: - StateKeys = ['name', 'args', 'macrotile', 'threads', 'grid'] + StateKeys = ['name', + 'args', + 'macrotile', + 'threads', + 'grid', + 'workspaceType', + 'workspaceSizePerElemC', + 'workspaceSizePerElemBias'] @classmethod def FromOriginalState(cls, d): - return cls(name=d['name'], args=d['args'], macrotile=d['macrotile'], threads=d['threads'], grid=d['grid']) + return cls(name=d['name'], + args=d['args'], + macrotile=d['macrotile'], + threads=d['threads'], + grid=d['grid'], + workspaceType=d['workspaceType'], + workspaceSizePerElemC=d['workspaceSizePerElemC'], + workspaceSizePerElemBias=d['workspaceSizePerElemBias']) def __init__(self, **kwargs): for (key, value) in list(kwargs.items()): diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s new file mode 100644 index 000000000000..8359e145f020 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s @@ -0,0 +1,17944 @@ + +/******************************************/ +/* Begin Kernel */ +/******************************************/ +.amdgcn_target "amdgcn-amd-amdhsa--gfx942" +.text +.protected c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1 +.globl c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1 +.p2align 8 +.type c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1,@function +.section .rodata,#alloc +.p2align 6 +.amdhsa_kernel c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_accum_offset 256 // accvgpr offset + .amdhsa_next_free_vgpr 384 // vgprs + .amdhsa_next_free_sgpr 88 // sgprs + .amdhsa_group_segment_fixed_size 49152 // lds bytes + .amdhsa_private_segment_fixed_size 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 1 + .amdhsa_system_sgpr_workgroup_id_z 1 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_user_sgpr_count 13 + .amdhsa_user_sgpr_kernarg_preload_length 11 + .amdhsa_user_sgpr_kernarg_preload_offset 0 +.end_amdhsa_kernel +.text +/* Num VGPR =256 */ +/* Num AccVGPR=128 */ +/* Num SGPR =88 */ + +/******************************************/ +/* Optimizations and Config: */ +/******************************************/ +/* ThreadTile= 16 x 8 */ +/* SubGroup= 8 x 32 */ +/* VectorWidthA=4 */ +/* VectorWidthB=8 */ +/* GlobalReadVectorWidthA=8, GlobalReadVectorWidthB=8 */ +/* DirectToLdsA=False */ +/* DirectToLdsB=False */ +/* UseSgprForGRO=False */ +.amdgpu_metadata +--- +custom.config: + InternalSupportParams: + KernArgsVersion: 2 +amdhsa.version: + - 1 + - 1 +amdhsa.kernels: + - .name: c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1 + .symbol: 'c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.kd' + .language: OpenCL C + .language_version: + - 2 + - 0 + .args: + - .name: Gemm info + .size: 4 + .offset: 0 + .value_kind: by_value + .value_type: u32 + - .name: kernel info0 + .size: 4 + .offset: 4 + .value_kind: by_value + .value_type: u32 + - .name: kernel info1 + .size: 4 + .offset: 8 + .value_kind: by_value + .value_type: u32 + - .name: numWG + .size: 4 + .offset: 12 + .value_kind: by_value + .value_type: u32 + - .name: SizesFree0 + .size: 4 + .offset: 16 + .value_kind: by_value + .value_type: u32 + - .name: SizesFree1 + .size: 4 + .offset: 20 + .value_kind: by_value + .value_type: u32 + - .name: SizesFree2 + .size: 4 + .offset: 24 + .value_kind: by_value + .value_type: u32 + - .name: SizesSum0 + .size: 4 + .offset: 28 + .value_kind: by_value + .value_type: u32 + - .name: D + .size: 8 + .offset: 32 + .value_kind: global_buffer + .value_type: f16 + .address_space: generic + - .name: C + .size: 8 + .offset: 40 + .value_kind: global_buffer + .value_type: f16 + .address_space: generic + - .name: A + .size: 8 + .offset: 48 + .value_kind: global_buffer + .value_type: f16 + .address_space: generic + - .name: B + .size: 8 + .offset: 56 + .value_kind: global_buffer + .value_type: f16 + .address_space: generic + - .name: AddressWS + .size: 8 + .offset: 64 + .value_kind: global_buffer + .value_type: f32 + .address_space: generic + - .name: AddressFlags + .size: 8 + .offset: 72 + .value_kind: global_buffer + .value_type: f16 + .address_space: generic + - .name: strideD0 + .size: 4 + .offset: 80 + .value_kind: by_value + .value_type: u32 + - .name: strideD1 + .size: 4 + .offset: 84 + .value_kind: by_value + .value_type: u32 + - .name: strideC0 + .size: 4 + .offset: 88 + .value_kind: by_value + .value_type: u32 + - .name: strideC1 + .size: 4 + .offset: 92 + .value_kind: by_value + .value_type: u32 + - .name: strideA0 + .size: 4 + .offset: 96 + .value_kind: by_value + .value_type: u32 + - .name: strideA1 + .size: 4 + .offset: 100 + .value_kind: by_value + .value_type: u32 + - .name: strideB0 + .size: 4 + .offset: 104 + .value_kind: by_value + .value_type: u32 + - .name: strideB1 + .size: 4 + .offset: 108 + .value_kind: by_value + .value_type: u32 + - .name: alpha + .size: 4 + .offset: 112 + .value_kind: by_value + .value_type: f32 + - .name: beta + .size: 4 + .offset: 116 + .value_kind: by_value + .value_type: f32 + - .name: ItersPerTile + .size: 4 + .offset: 120 + .value_kind: by_value + .value_type: u32 + - .name: MagicNumberItersPerTile + .size: 4 + .offset: 124 + .value_kind: by_value + .value_type: u32 + - .name: MagicShiftItersPerTile + .size: 4 + .offset: 128 + .value_kind: by_value + .value_type: u32 + - .name: TotalIters + .size: 4 + .offset: 132 + .value_kind: by_value + .value_type: u32 + - .name: SKItersPerWG + .size: 4 + .offset: 136 + .value_kind: by_value + .value_type: u32 + - .name: skGrid + .size: 4 + .offset: 140 + .value_kind: by_value + .value_type: u32 + - .name: skTiles + .size: 4 + .offset: 144 + .value_kind: by_value + .value_type: u32 + .group_segment_fixed_size: 49152 + .kernarg_segment_align: 8 + .kernarg_segment_size: 152 + .max_flat_workgroup_size: 256 + .private_segment_fixed_size: 0 + .sgpr_count: 88 + .sgpr_spill_count: 0 + .vgpr_count: 256 + .vgpr_spill_count: 0 + .wavefront_size: 64 +... +.end_amdgpu_metadata +c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1: +label_ASM_Start: /// Main body of the asm kernel +.macro V_MAGIC_DIV vgprDstIdx:req, dividend:req, magicNumber:req, magicShift:req, magicA:req + v_mul_hi_u32 v[\vgprDstIdx+1], \dividend, \magicNumber + v_mul_lo_u32 v[\vgprDstIdx+0], \dividend, \magicA + v_add_u32 v[\vgprDstIdx+0], v[\vgprDstIdx+0], v[\vgprDstIdx+1] + v_lshrrev_b32 v[\vgprDstIdx+0], \magicShift, v[\vgprDstIdx+0] +.endm + +/******************************************/ +/* VGPR Assignments for MX */ +/******************************************/ +.set vgprMXSBase, 0 + +/******************************************/ +/* VGPR Macro Assignments for MX */ +/******************************************/ + +/******************************************/ +/* VGPR Assignments */ +/******************************************/ +/* ValuC range: [0-0), serializedStore enabled */ +.set vgprValuC, 0 +/* ValuA/B Xn=PLR buffer idx, In=InnerUnroll idx */ +.set vgprBase, 16 +.set vgprLocalWriteAddrA, 12 +.set vgprLocalWriteAddrB, 13 +.set vgprGlobalReadOffsetA, 0 +.set vgprGlobalReadOffsetB, 4 +.set vgprLocalReadAddrA, 14 +.set vgprLocalReadAddrB, 15 +.set vgprSerial, 184 + +/******************************************/ +/* VGPR Macro Assignments */ +/******************************************/ +.set vgprValuA_X0_I0_BASE, vgprBase+0 +.set vgprValuA_X0_I0_D0_PACK, vgprBase+8 +.set vgprValuB_X0_I0_BASE, vgprBase+40 +.set vgprValuB_X0_I0_D0_PACK, vgprBase+56 +.set vgprG2LA_BASE, vgprBase+120 +.set vgprG2LB_BASE, vgprBase+136 +.set vgprValuA_X0_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X1_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X2_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X3_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuB_X0_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X1_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X2_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X3_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuA_X0_I0_D0, vgprValuA_X0_I0_D0_PACK+0 +.set vgprValuA_X0_I0_D1, vgprValuA_X0_I0_D0_PACK+2 +.set vgprValuA_X0_I0_D2, vgprValuA_X0_I0_D0_PACK+4 +.set vgprValuA_X0_I0_D3, vgprValuA_X0_I0_D0_PACK+6 +.set vgprValuA_X1_I0_D0, vgprValuA_X0_I0_D0_PACK+8 +.set vgprValuA_X1_I0_D1, vgprValuA_X0_I0_D0_PACK+10 +.set vgprValuA_X1_I0_D2, vgprValuA_X0_I0_D0_PACK+12 +.set vgprValuA_X1_I0_D3, vgprValuA_X0_I0_D0_PACK+14 +.set vgprValuA_X2_I0_D0, vgprValuA_X0_I0_D0_PACK+16 +.set vgprValuA_X2_I0_D1, vgprValuA_X0_I0_D0_PACK+18 +.set vgprValuA_X2_I0_D2, vgprValuA_X0_I0_D0_PACK+20 +.set vgprValuA_X2_I0_D3, vgprValuA_X0_I0_D0_PACK+22 +.set vgprValuA_X3_I0_D0, vgprValuA_X0_I0_D0_PACK+24 +.set vgprValuA_X3_I0_D1, vgprValuA_X0_I0_D0_PACK+26 +.set vgprValuA_X3_I0_D2, vgprValuA_X0_I0_D0_PACK+28 +.set vgprValuA_X3_I0_D3, vgprValuA_X0_I0_D0_PACK+30 +.set vgprValuB_X0_I0_D0, vgprValuB_X0_I0_D0_PACK+0 +.set vgprValuB_X0_I0_D1, vgprValuB_X0_I0_D0_PACK+4 +.set vgprValuB_X0_I0_D2, vgprValuB_X0_I0_D0_PACK+8 +.set vgprValuB_X0_I0_D3, vgprValuB_X0_I0_D0_PACK+12 +.set vgprValuB_X1_I0_D0, vgprValuB_X0_I0_D0_PACK+16 +.set vgprValuB_X1_I0_D1, vgprValuB_X0_I0_D0_PACK+20 +.set vgprValuB_X1_I0_D2, vgprValuB_X0_I0_D0_PACK+24 +.set vgprValuB_X1_I0_D3, vgprValuB_X0_I0_D0_PACK+28 +.set vgprValuB_X2_I0_D0, vgprValuB_X0_I0_D0_PACK+32 +.set vgprValuB_X2_I0_D1, vgprValuB_X0_I0_D0_PACK+36 +.set vgprValuB_X2_I0_D2, vgprValuB_X0_I0_D0_PACK+40 +.set vgprValuB_X2_I0_D3, vgprValuB_X0_I0_D0_PACK+44 +.set vgprValuB_X3_I0_D0, vgprValuB_X0_I0_D0_PACK+48 +.set vgprValuB_X3_I0_D1, vgprValuB_X0_I0_D0_PACK+52 +.set vgprValuB_X3_I0_D2, vgprValuB_X0_I0_D0_PACK+56 +.set vgprValuB_X3_I0_D3, vgprValuB_X0_I0_D0_PACK+60 +.set vgprG2LA, vgprG2LA_BASE+0 +.set vgprG2LB, vgprG2LB_BASE+0 + +/******************************************/ +/* SGPR Assignments */ +/******************************************/ +.set sgprKernArgAddress, 0 +.set sgprWorkGroup0, 2 +.set sgprWorkGroup1, 3 +.set sgprWorkGroup2, 4 +.set sgprArgType, 5 +.set sgprStaggerU, 6 +.set sgprWGM, 7 +.set sgprLoopCounterL, 8 +.set sgprOrigLoopCounter, 9 +.set sgprSrdD, 12 +.set sgprSrdC, 16 +.set sgprNumWorkGroups0, 10 +.set sgprNumWorkGroups1, 11 +.set sgprSizesFree, 20 +.set sgprSizesSum, 23 +.set sgprAddressD, 24 +.set sgprAddressC, 26 +.set sgprAddressA, 28 +.set sgprAddressB, 30 +.set sgprAddressWS, 32 +.set sgprAddressFlags, 34 +.set sgprStridesD, 36 +.set sgprStridesC, 38 +.set sgprStridesA, 40 +.set sgprStridesB, 42 +.set sgprAlpha, 44 +.set sgprBeta, 45 +.set sgprItersPerTile, 46 +.set sgprMagicNumberItersPerTile, 47 +.set sgprMagicShiftItersPerTile, 48 +.set sgprTotalIters, 49 +.set sgprSKItersPerWG, 50 +.set sgprskGrid, 51 +.set sgprskTiles, 52 +.set sgprStreamKIdx, 53 +.set sgprStreamKIter, 54 +.set sgprStreamKIterEnd, 55 +.set sgprStreamKLocalStart, 56 +.set sgprStreamKLocalEnd, 57 +.set sgprSrdWS, 60 + +/* StreamK Parallel Reduction Assignments */ +.set sgprSkSplit, sgprskTiles+0 +.set sgprSkPartialIdx, sgprBeta+0 + +/* Size Assignments */ +.set sgprSizeI, sgprSizesFree+0 +.set sgprSizeJ, sgprSizesFree+1 +.set sgprSizeK, sgprSizesFree+2 +.set sgprSizeL, sgprSizesSum+0 + +/* Stride Assignments */ +.set constStrideD0I, 1 +.set sgprStrideD1J, sgprStridesD+0 +.set sgprStrideDK, sgprStridesD+1 +.set constStrideC0I, 1 +.set sgprStrideC1J, sgprStridesC+0 +.set sgprStrideCK, sgprStridesC+1 +.set constStrideA0I, 1 +.set sgprStrideAL, sgprStridesA+0 +.set sgprStrideAK, sgprStridesA+1 +.set constStrideB1J, 1 +.set sgprStrideBL, sgprStridesB+0 +.set sgprStrideBK, sgprStridesB+1 + +.set MT0, 128 +.set MT1, 256 +.set DepthU, 64 +/* Number of elements to shift-left SRD */ +.set SrdShiftLeftA, 8 +.set SrdShiftLeftB, 8 +/* 2GB limit - set offsets to -1 to exceed this and clamp */ +.set BufferLimit, 0xffffffff +.set BufferOOB, 0x80000000 + +/******************************************/ +/* Bits 127:96 of SRD. */ +/* hex: 0x20000 */ +/* dst_sel_x (3b): 0 */ +/* dst_sel_y (3b): 0 */ +/* dst_sel_z (3b): 0 */ +/* dst_sel_w (3b): 0 */ +/* num_format (3b): 0 */ +/* data_format (4b): 4 */ +/* user_vm_enable (1b): 0 */ +/* user_vm_mode (1b): 0 */ +/* index_stride (2b): 0 */ +/* add_tid_enable (1b): 0 */ +/* _unusedA (3b): 0 */ +/* nv (1b): 0 */ +/* _unusedB (2b): 0 */ +/* type (2b): 0 */ +/******************************************/ +.set Srd127_96, 0x20000 + +/* Global Offset A */ +.macro GLOBAL_OFFSET_A vgprAddr:req, vgprOffset0I:req, vgprOffsetL:req, vgprTmp:req + v_mul_lo_u32 v[\vgprTmp+0], s[sgprStrideAL], v[\vgprOffsetL] // mul d1 lower + v_add_co_u32 v[\vgprAddr+0], vcc, v[\vgprOffset0I], v[\vgprTmp+0] // accumulate K lower + v_add_u32 v[\vgprAddr+0], 0x8, v[\vgprAddr+0] // add prepad for pointer shift +.endm + +/* Global Offset B */ +.macro GLOBAL_OFFSET_B vgprAddr:req, vgprOffset1J:req, vgprOffsetL:req, vgprTmp:req + v_mul_lo_u32 v[\vgprTmp+0], s[sgprStrideBL], v[\vgprOffsetL] // mul d1 lower + v_add_co_u32 v[\vgprAddr+0], vcc, v[\vgprOffset1J], v[\vgprTmp+0] // accumulate K lower + v_add_u32 v[\vgprAddr+0], 0x8, v[\vgprAddr+0] // add prepad for pointer shift +.endm + +/******************************************/ +/* Allocate Resources */ +/******************************************/ + +/* Load num of Gemms */ +s_load_dword s16, s[sgprKernArgAddress:sgprKernArgAddress+1], 0 + +/* Load packed kernel args (StaggerU/GSU) */ +s_load_dword s18, s[sgprKernArgAddress:sgprKernArgAddress+1], 4 + +/* Load WGM data */ +s_load_dword s[sgprWGM], s[sgprKernArgAddress:sgprKernArgAddress+1], 8 + +/* Load num of WGs */ +s_load_dword s19, s[sgprKernArgAddress:sgprKernArgAddress+1], 12 +s_waitcnt lgkmcnt(0) // load args +s_lshr_b32 s17, s16, 0x1e // Get arg type +s_and_b32 s16, 0x3fffffff, s16 // Get nums of gemm +s_cmp_eq_u32 s17, 0 // Is kernel args +s_cbranch_scc0 label_HBMArgs +s_add_u32 s[sgprKernArgAddress], s[sgprKernArgAddress], 0x10 // Shift common args +s_addc_u32 s[sgprKernArgAddress+1], s[sgprKernArgAddress+1], 0 + +/* Load Kernel Args */ +s_load_dwordx16 s[20:35], s[sgprKernArgAddress:sgprKernArgAddress+1], 0 // 0 +s_load_dwordx16 s[36:51], s[sgprKernArgAddress:sgprKernArgAddress+1], 64 // 64 +s_load_dword s52, s[sgprKernArgAddress:sgprKernArgAddress+1], 128 // 128 +s_waitcnt lgkmcnt(0) // preload +s_branch label_LoadArgsEnd +label_HBMArgs: + +/* Load address of kernel arguments */ +s_load_dwordx2 s[sgprKernArgAddress:sgprKernArgAddress+1], s[sgprKernArgAddress:sgprKernArgAddress+1], 16 +s_waitcnt lgkmcnt(0) // wait for args to load +label_LoadArgsEnd: +s_branch label_common_kernel_entry + +/* pad 37 snops to satisfy 0x100 code size for Preload Backward Compatibility Prologue */ +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +s_nop 0 +label_Preload_Offset_Start: +s_and_b32 s16, 0x3fffffff, s2 // Get nums of gemm +s_lshr_b32 s17, s2, 0x1e // Get arg type +s_mov_b32 s18, s3 // Preload internal args +s_cmp_eq_u32 s17, 0 // Is kernel args +s_cbranch_scc0 label_Preload_HBMArgs +s_add_u32 s[sgprKernArgAddress], s[sgprKernArgAddress], 0x10 // Shift common args +s_addc_u32 s[sgprKernArgAddress+1], s[sgprKernArgAddress+1], 0 + +/* Load Kernel Args */ +s_load_dword s27, s[sgprKernArgAddress:sgprKernArgAddress+1], 28 // 28 +s_load_dwordx16 s[28:43], s[sgprKernArgAddress:sgprKernArgAddress+1], 32 // 32 +s_load_dwordx8 s[44:51], s[sgprKernArgAddress:sgprKernArgAddress+1], 96 // 96 +s_load_dword s52, s[sgprKernArgAddress:sgprKernArgAddress+1], 128 // 128 +s_mov_b64 s[20:21], s[6:7] // move preload data to correct sgpr +s_mov_b64 s[22:23], s[8:9] // move preload data to correct sgpr +s_mov_b64 s[24:25], s[10:11] // move preload data to correct sgpr +s_mov_b32 s26, s12 // move preload data to correct sgpr +s_branch label_Preload_LoadArgsEnd +label_Preload_HBMArgs: +s_mov_b64 s[sgprKernArgAddress:sgprKernArgAddress+1], s[6:7] // Load address of kernel arguments +label_Preload_LoadArgsEnd: +s_mov_b32 s[sgprWGM], s4 // Preload internal args2 +s_mov_b32 s19, s5 // Load num of WGs +label_common_kernel_entry: /// for both preload/non-preload common code +s_mov_b32 s[sgprWorkGroup0+0], s13 // restore workgroup id +s_mov_b32 s[sgprWorkGroup0+1], s14 // restore workgroup id +s_mov_b32 s[sgprWorkGroup0+2], s15 // restore workgroup id +s_and_b32 s[sgprStaggerU], s18, 0xffff0000 // Restore StaggerU related vars +s_lshr_b32 s[sgprStaggerU], s[sgprStaggerU], 0x10 +s_mov_b32 s[sgprArgType], s17 +s_mov_b32 m0, 0xc000 // LDS clamp at 49152 bytes +v_mov_b32 v[vgprSerial], v0 // thread serial id + +/* remap workgroup to XCCs */ +s_lshr_b32 s62, s[sgprWGM], 0x10 // Get WGMXCC +s_ff1_i32_b32 s62, s62 // Get log(WGMXCC) +s_lshr_b32 s63, s[sgprWGM], 0x16 // Get CU_Count +/* remap WGs if WGMXCC > 1 ( log(WGMXCC) > 0 ) */ +s_cmp_gt_i32 s62, 0 +s_cbranch_scc0 label_skip_WGMXCC +/* only remap WGs in the range */ +s_lshr_b32 s59, s19, s62 +s_lshl_b32 s59, s59, s62 +s_cmp_ge_u32 s[sgprWorkGroup0], s59 +s_cbranch_scc1 label_skip_WGMXCC +s_cmp_eq_u32 s63, 0 // CU_Count == 0 ? +s_cbranch_scc0 label_XCCG_nonzero +s_lshr_b32 s59, s[sgprWorkGroup0], s62 +s_bfm_b32 s60, s62, 0 +s_and_b32 s60, s[sgprWorkGroup0], s60 +s_lshr_b32 s61, s19, s62 +s_mul_i32 s60, s60, s61 +s_add_u32 s[sgprWorkGroup0], s59, s60 +s_branch label_skip_WGMXCC +label_XCCG_nonzero: +/* temp0 = (wg//CU_Count)*CU_Count */ +v_cvt_f64_u32 v[16:17], s63 // s59 = s[sgprWorkGroup0] / s63 +v_rcp_f64 v[16:17], v[16:17] // s59 = s[sgprWorkGroup0] / s63 +v_cvt_f64_u32 v[18:19], s[sgprWorkGroup0] // s59 = s[sgprWorkGroup0] / s63 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s59 = s[sgprWorkGroup0] / s63 +v_cvt_u32_f64 v16, v[16:17] // s59 = s[sgprWorkGroup0] / s63 +v_mul_lo_u32 v17, v16, s63 // s59 = s[sgprWorkGroup0] / s63 +v_sub_u32 v18, s[sgprWorkGroup0], v17 // s59 = s[sgprWorkGroup0] / s63 +v_cmpx_ge_u32 exec, v18, s63 // s59 = s[sgprWorkGroup0] / s63 +v_add_u32 v16, v16, 1 // s59 = s[sgprWorkGroup0] / s63 +s_mov_b64 exec, -1 // Reset exec +v_mul_lo_u32 v17, v16, s63 // s59 = s[sgprWorkGroup0] / s63 +v_sub_u32 v18, s[sgprWorkGroup0], v17 // s59 = s[sgprWorkGroup0] / s63 +v_readfirstlane_b32 s59, v16 // quotient +v_readfirstlane_b32 s60, v18 // remainder +s_mul_i32 s59, s59, s63 +/* temp1 = (wg%CU_Count)//WGMXCC */ +s_lshr_b32 s60, s60, s62 +/* temp0 = temp0 + temp1 */ +s_add_u32 s59, s59, s60 +/* temp1 = (wg%WGMXCC) * ((WGs - (WGs//CU_Count) * CU_Count) if (wg > (WGs//CU_Count) * CU_Count) else CU_Count)//WGMXCC */ +v_cvt_f64_u32 v[16:17], s63 // s60 = s19 / s63 +v_rcp_f64 v[16:17], v[16:17] // s60 = s19 / s63 +v_cvt_f64_u32 v[18:19], s19 // s60 = s19 / s63 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s60 = s19 / s63 +v_cvt_u32_f64 v16, v[16:17] // s60 = s19 / s63 +v_mul_lo_u32 v17, v16, s63 // s60 = s19 / s63 +v_sub_u32 v18, s19, v17 // s60 = s19 / s63 +v_cmpx_ge_u32 exec, v18, s63 // s60 = s19 / s63 +v_add_u32 v16, v16, 1 // s60 = s19 / s63 +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s60, v16 // quotient +s_mul_i32 s60, s60, s63 +s_sub_u32 s61, s19, s60 +s_cmp_gt_u32 s[sgprWorkGroup0], s60 +s_cselect_b32 s60, s61, s63 +s_lshr_b32 s60, s60, s62 +s_bfm_b32 s61, s62, 0 +s_and_b32 s61, s[sgprWorkGroup0], s61 +s_mul_i32 s60, s60, s61 +/* WorkGroup0 = temp0 + temp1 */ +s_add_u32 s[sgprWorkGroup0], s59, s60 +label_skip_WGMXCC: /// skip WGMXCC if no enough WGs to remap +s_cmp_eq_u32 s17, 0 +s_cbranch_scc0 label_MultiGemm +/* init: add vgpr [16...152) to pool */ +/* init: add vgpr [0...0) to pool */ +/* init: add agpr [0...128) to pool */ +v_mov_b32 v18, MT0 // set MT0 into sgpr +v_mov_b32 v17, s[sgprSizesFree+0] // set Free0 size +v_cvt_f32_u32 v16, v18 // v16 = ceil(v17 / v18) +v_rcp_iflag_f32 v16, v16 // v16 = ceil(v17 / v18) +v_cvt_f32_u32 v19, v17 // v16 = ceil(v17 / v18) +v_mul_f32 v16, v16, v19 // v16 = ceil(v17 / v18) +v_cvt_u32_f32 v16, v16 // v16 = ceil(v17 / v18) +v_mul_u32_u24 v19, v16, v18 // v16 = ceil(v17 / v18) +v_sub_u32 v19, v17, v19 // v16 = ceil(v17 / v18) +v_cmp_ne_u32 vcc, v19, 0 // v16 = ceil(v17 / v18) +v_addc_co_u32 v16, vcc, v16, 0, vcc // ceil +v_mov_b32 v18, MT1 // set MT1 into sgpr +v_mov_b32 v17, s[sgprSizesFree+1] // set Free1 size +v_readfirstlane_b32 s[sgprNumWorkGroups0], v16 // set back to numWorkGroup0 +v_cvt_f32_u32 v16, v18 // v16 = ceil(v17 / v18) +v_rcp_iflag_f32 v16, v16 // v16 = ceil(v17 / v18) +v_cvt_f32_u32 v19, v17 // v16 = ceil(v17 / v18) +v_mul_f32 v16, v16, v19 // v16 = ceil(v17 / v18) +v_cvt_u32_f32 v16, v16 // v16 = ceil(v17 / v18) +v_mul_u32_u24 v19, v16, v18 // v16 = ceil(v17 / v18) +v_sub_u32 v19, v17, v19 // v16 = ceil(v17 / v18) +v_cmp_ne_u32 vcc, v19, 0 // v16 = ceil(v17 / v18) +v_addc_co_u32 v16, vcc, v16, 0, vcc // ceil +s_nop 0 // 1 wait states +v_readfirstlane_b32 s[sgprNumWorkGroups1], v16 // set back to numWorkGroup1 +s_waitcnt lgkmcnt(0) // wait for 88/0 bytes of kern args +s_branch label_MultiGemmEnd +label_MultiGemm: + +/* Check if custom structure pointer is null */ +s_cmp_eq_u32 s[sgprArgType], 2 // ArgType == 2 ? +s_cbranch_scc1 label_IsExternalValid // branch if ArgType == 2 +s_mov_b32 s11, 132 +s_mul_i32 s64, s16, 4 +s_mov_b64 s[58:59], s[sgprKernArgAddress:sgprKernArgAddress+1] +s_branch label_IsExternalValidEnd +label_IsExternalValid: +s_mov_b32 s11, 224 +s_mov_b32 s64, 0 +s_mov_b64 s[58:59], s[sgprKernArgAddress:sgprKernArgAddress+1] +label_IsExternalValidEnd: + +/* Grouped Gemm:: prefetch 1 arg load */ +s_mov_b32 s10, 1 +s_mov_b32 s65, 0 +s_load_dwordx4 s[20:23], s[58:59], s64 +s_cmpk_eq_u32 s16, 1 // if gemm_count is 1? +s_cbranch_scc1 label_wgTable_noLoadLoop + +/* Grouped Gemm:: accumulate numTiles for each gemm */ +/* Grouped Gemm:: loop start */ +label_Loop_GemmCount: +s_waitcnt lgkmcnt(0) +s_lshr_b32 s62, s20, 7 // s62 = s20 / 128 +s_and_b32 s60, 127, s20 // s60 = s20 % 128 +s_addc_u32 s62, s62, 0 +s_lshr_b32 s63, s21, 8 // s63 = s21 / 256 +s_and_b32 s60, 255, s21 // s60 = s21 % 256 +s_addc_u32 s63, s63, 0 +s_mul_i32 s62, s62, s63 +s_mul_i32 s62, s62, s22 +s_add_u32 s65, s65, s62 +s_cmp_lt_u32 s[sgprWorkGroup0], s65 +s_cbranch_scc1 label_FOUND +s_add_u32 s64, s64, s11 +s_load_dwordx4 s[20:23], s[58:59], s64 +s_add_u32 s10, s10, 1 +s_cmp_lt_u32 s10, s16 +s_cbranch_scc1 label_Loop_GemmCount + +/* Grouped Gemm:: noLoadLoop */ +label_wgTable_noLoadLoop: +s_waitcnt lgkmcnt(0) +s_lshr_b32 s62, s20, 7 // s62 = s20 / 128 +s_and_b32 s60, 127, s20 // s60 = s20 % 128 +s_addc_u32 s62, s62, 0 +s_lshr_b32 s63, s21, 8 // s63 = s21 / 256 +s_and_b32 s60, 255, s21 // s60 = s21 % 256 +s_addc_u32 s63, s63, 0 +s_mul_i32 s62, s62, s63 +s_mul_i32 s62, s62, s22 +s_add_u32 s65, s65, s62 + +/* Grouped Gemm:: gemmIndex found */ +label_FOUND: +s_sub_u32 s59, s10, 1 +s_sub_u32 s58, s65, s62 +s_sub_u32 s[sgprWorkGroup0], s[sgprWorkGroup0], s58 +/* Check if custom structure pointer is null */ +s_cmp_eq_u32 s[sgprArgType], 2 // ArgType == 2 ? +s_cbranch_scc1 label_LoadExternalStruct // branch if ArgType == 2 + +/* Grouped Gemm: offset argument address to gemm */ +/* Grouped Gemm: offset address from wg_table_start to args_start */ +s_lshl2_add_u32 s[sgprKernArgAddress], s16, s[sgprKernArgAddress] +s_addc_u32 s[sgprKernArgAddress+1], s[sgprKernArgAddress+1], 0 +/* Grouped Gemm: offset address from args_start to gemm_start */ +s_mul_i32 s59, s59, 132 +s_add_u32 s[sgprKernArgAddress], s[sgprKernArgAddress], s59 +s_addc_u32 s[sgprKernArgAddress+1], s[sgprKernArgAddress+1], 0 + +/* Load Kernel Args */ +s_load_dwordx16 s[24:39], s[sgprKernArgAddress:sgprKernArgAddress+1], 16 // 16 +s_load_dwordx8 s[40:47], s[sgprKernArgAddress:sgprKernArgAddress+1], 80 // 80 +s_load_dwordx4 s[48:51], s[sgprKernArgAddress:sgprKernArgAddress+1], 112 // 112 +s_load_dword s52, s[sgprKernArgAddress:sgprKernArgAddress+1], 128 // 128 +s_branch label_LoadExternalStructEnd +label_LoadExternalStruct: +/* Grouped Gemm: offset address from args_start to gemm_start */ +s_mul_i32 s59, s59, 224 +s_add_u32 s[sgprKernArgAddress], s[sgprKernArgAddress], s59 +s_addc_u32 s[sgprKernArgAddress+1], s[sgprKernArgAddress+1], 0 +s_load_dwordx16 s[24:39], s[sgprKernArgAddress:sgprKernArgAddress+1], 16 // 16 +s_load_dwordx8 s[40:47], s[sgprKernArgAddress:sgprKernArgAddress+1], 80 // 80 +s_load_dwordx4 s[48:51], s[sgprKernArgAddress:sgprKernArgAddress+1], 112 // 112 +// Read Beta +s_load_dword s45, s[sgprKernArgAddress:sgprKernArgAddress+1], 140 // 140 +label_LoadExternalStructEnd: +/* init: add vgpr [16...152) to pool */ +/* init: add vgpr [0...0) to pool */ +/* init: add agpr [0...128) to pool */ +v_mov_b32 v18, MT0 // set MT0 into sgpr +v_mov_b32 v17, s[sgprSizesFree+0] // set Free0 size +v_cvt_f32_u32 v16, v18 // v16 = ceil(v17 / v18) +v_rcp_iflag_f32 v16, v16 // v16 = ceil(v17 / v18) +v_cvt_f32_u32 v19, v17 // v16 = ceil(v17 / v18) +v_mul_f32 v16, v16, v19 // v16 = ceil(v17 / v18) +v_cvt_u32_f32 v16, v16 // v16 = ceil(v17 / v18) +v_mul_u32_u24 v19, v16, v18 // v16 = ceil(v17 / v18) +v_sub_u32 v19, v17, v19 // v16 = ceil(v17 / v18) +v_cmp_ne_u32 vcc, v19, 0 // v16 = ceil(v17 / v18) +v_addc_co_u32 v16, vcc, v16, 0, vcc // ceil +v_mov_b32 v18, MT1 // set MT1 into sgpr +v_mov_b32 v17, s[sgprSizesFree+1] // set Free1 size +v_readfirstlane_b32 s[sgprNumWorkGroups0], v16 // set back to numWorkGroup0 +v_cvt_f32_u32 v16, v18 // v16 = ceil(v17 / v18) +v_rcp_iflag_f32 v16, v16 // v16 = ceil(v17 / v18) +v_cvt_f32_u32 v19, v17 // v16 = ceil(v17 / v18) +v_mul_f32 v16, v16, v19 // v16 = ceil(v17 / v18) +v_cvt_u32_f32 v16, v16 // v16 = ceil(v17 / v18) +v_mul_u32_u24 v19, v16, v18 // v16 = ceil(v17 / v18) +v_sub_u32 v19, v17, v19 // v16 = ceil(v17 / v18) +v_cmp_ne_u32 vcc, v19, 0 // v16 = ceil(v17 / v18) +v_addc_co_u32 v16, vcc, v16, 0, vcc // ceil +s_nop 0 // 1 wait states +v_readfirstlane_b32 s[sgprNumWorkGroups1], v16 // set back to numWorkGroup1 +s_waitcnt lgkmcnt(0) // wait for 88/0 bytes of kern args + +/* Early stop if N(SizeFreeJ) == 0 */ +s_cmp_eq_u32 s[sgprSizeJ], 0 +s_cbranch_scc0 label_NoEarlyStop_N0 +label_EarlyStop_if_N_is_0: +s_endpgm +label_NoEarlyStop_N0: + +label_MultiGemmEnd: +.set sgprSrdA, 64 +.set sgprSrdB, 68 +.set sgprShadowLimitA, 58 +.set sgprShadowLimitB, 72 +.set sgprStaggerUIter, 74 +.set sgprWrapUA, 75 +.set sgprWrapUB, 77 +.set sgprGlobalReadIncsA, 79 +.set sgprGlobalReadIncsB, 80 +.set sgprPackKForV0, 81 +.set sgprPackKForV1, 82 +s_mov_b32 s[sgprPackKForV0], 0x05040100 +s_mov_b32 s[sgprPackKForV1], 0x07060302 +s_sub_u32 s[sgprAddressA+0], s[sgprAddressA+0], 16 // pre-pad to make room for possible pointer shift +s_subb_u32 s[sgprAddressA+1], s[sgprAddressA+1], 0 // pre-pad to make room for possible pointer shift +s_sub_u32 s[sgprAddressB+0], s[sgprAddressB+0], 16 // pre-pad to make room for possible pointer shift +s_subb_u32 s[sgprAddressB+1], s[sgprAddressB+1], 0 // pre-pad to make room for possible pointer shift + +/* Short circuit condition if Alpha == 0, then sumDims=0 */ +v_cmp_eq_f32 vcc, s[sgprAlpha], 0.0 // s[Alpha] == 0.0f ? +s_cbranch_vccz label_AlphaNonZero // branch if s[Alpha] != 0 +s_mov_b32 s[sgprSizesSum+0], 0 // Set summation dim=0 if Alpha == 0 +label_AlphaNonZero: +s_mov_b32 s[sgprStreamKIdx], s[sgprWorkGroup0] // Save original StreamK index +s_cmp_eq_u64 s[sgprAddressFlags:sgprAddressFlags+1], 0x0 // Check for synchronizer +s_cbranch_scc0 label_SK_SplitInit // Jump to single kernel init +v_cvt_f32_u32 v16, s[sgprSkSplit] // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_rcp_iflag_f32 v16, v16 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_cvt_f32_u32 v17, s[sgprStreamKIdx] // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_mul_f32 v16, v16, v17 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_cvt_u32_f32 v16, v16 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_mul_u32_u24 v17, v16, s[sgprSkSplit] // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_sub_u32 v17, s[sgprStreamKIdx], v17 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_cmpx_eq_u32 exec, v17, s[sgprSkSplit] // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_add_u32 v16, 1, v16 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +v_mov_b32 v17, 0 // TileIdx = SKIdx // WGsPerTile, PartialIdx = SKIdx % WGsPerTile +s_mov_b64 exec, -1 // Reset exec +v_cmpx_gt_u32 exec, v17, s[sgprSkSplit] // overflow happened in remainder +v_sub_u32 v16, v16, 1 // quotient - 1 +v_mul_u32_u24 v17, v16, s[sgprSkSplit] // re-calculate remainder +v_sub_u32 v17, s[sgprStreamKIdx], v17 // re-calculate remainder +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s12, v16 // quotient +v_readfirstlane_b32 s13, v17 // remainder +s_mul_i32 s14, s[sgprSkSplit], s[sgprSKItersPerWG] +s_sub_u32 s14, s[sgprItersPerTile], s14 // extraIters = itersPerTile - SkSplit * skItersPerWG +s_mul_i32 s[sgprStreamKIter], s13, s[sgprSKItersPerWG] // StreamK starting iteration (case: after extra iters) +s_cmp_lt_u32 s13, s14 // Check if WG gets an extra iteration +s_cbranch_scc1 label_SK_HasExtra // Has extra iter +s_add_u32 s[sgprStreamKIter], s[sgprStreamKIter], s14 // This WG does not have an extra iteration +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIter], s[sgprSKItersPerWG] // StreamK ending iteration (case: after extra iters) +s_branch label_SK_DoneExtra // Done init for parallel reduction +label_SK_HasExtra: +s_add_u32 s[sgprStreamKIter], s[sgprStreamKIter], s13 // This WG has an extra iteration +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIter], s[sgprSKItersPerWG] // StreamK ending iteration (case: after extra iters) +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIterEnd], 1 // StreamK ending iteration (case: after extra iters) +label_SK_DoneExtra: +s_mul_i32 s12, s12, s[sgprItersPerTile] // Tile offset = tilesIdx * itersPerTile +s_add_u32 s[sgprStreamKIter], s[sgprStreamKIter], s12 // Offset to correct tile +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIterEnd], s12 // Offset to correct tile +s_mov_b32 s[sgprSkPartialIdx], s13 // Save partial idx for SrdD calculation +s_branch label_SK_InitDone // Done init for parallel reduction +label_SK_SplitInit: +s_mul_i32 s[sgprStreamKIter], s[sgprStreamKIdx], s[sgprItersPerTile] // DP starting iteration (case: DP work to do) +s_mov_b32 s[sgprStreamKIterEnd], s[sgprTotalIters] // DP ending iteration (case: only DP work to do) +s_mul_i32 s12, s[sgprskTiles], s[sgprItersPerTile] // Total SK iters +s_cmp_lt_u32 s12, s[sgprTotalIters] // Check if there are DP tiles to do +s_cbranch_scc1 label_SK_InitDone // Done init +s_mul_i32 s12, s[sgprskTiles], s[sgprItersPerTile] +s_mul_i32 s13, s[sgprSKItersPerWG], s[sgprskGrid] +s_sub_u32 s12, s12, s13 // skTiles * ItersPerTile - SKItersPerWG * skGrid +s_mul_i32 s[sgprStreamKIter], s[sgprStreamKIdx], s[sgprSKItersPerWG] // StreamK starting iteration (case: after extra iters) +s_add_u32 s[sgprStreamKIter], s[sgprStreamKIter], s12 // Add extra iters +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIter], s[sgprSKItersPerWG] // StreamK ending iteration (case: after extra iters) +s_add_u32 s14, s[sgprSKItersPerWG], 1 // Spread out extra iterations +s_mul_i32 s13, s[sgprStreamKIdx], s14 // StreamK starting iteration (case: before extra iters) +s_add_u32 s14, s13, s14 // StreamK ending iteration (case: before extra iters) +s_cmp_lt_u32 s[sgprStreamKIdx], s12 // Check if lane gets an extra iteration +s_cselect_b32 s[sgprStreamKIter], s13, s[sgprStreamKIter] // Set start iter +s_cselect_b32 s[sgprStreamKIterEnd], s14, s[sgprStreamKIterEnd] // Set end iter +s_mul_i32 s12, s[sgprskTiles], s[sgprItersPerTile] // Total SK iters +s_min_u32 s[sgprStreamKIterEnd], s[sgprStreamKIterEnd], s12 // Cap ending iter at total SK iters +label_SK_InitDone: +s_cmp_lt_u32 s[sgprStreamKIter], s[sgprTotalIters] // Make sure there's work to do +s_cbranch_scc1 label_NoBranch_T8JHFHKM7BO5OHXW // Only branch on scc0 +s_getpc_b64 s[12:13] // addr of next instr +s_add_i32 s14, label_KernelEnd, 4 // target branch offset +s_add_u32 s12, s12, s14 // add target branch offset +s_addc_u32 s13, s13, 0 // add high and carry +s_setpc_b64 s[12:13] // branch to label_KernelEnd +label_NoBranch_T8JHFHKM7BO5OHXW: + +/******************************************/ +/* Persistent Loop Start */ +/******************************************/ +label_PersistentLoopStart: + +/******************************************/ +/* Begin setupNewTile */ +/******************************************/ + +/* global read addresses: work-group */ +/* graWorkGroup mapping */ +/* StreamK calculate tile idx and map to WG */ +s_mul_hi_u32 s13, s[sgprStreamKIter], s[sgprMagicNumberItersPerTile] // s_magic mul, div alg 2 +s_lshr_b32 s14, s[sgprMagicShiftItersPerTile], 31 // tmpS = extract abit +s_mul_i32 s12, s[sgprStreamKIter], s14 // s_magic mul, div alg 2 +s_add_u32 s12, s12, s13 +s_and_b32 s14, s[sgprMagicShiftItersPerTile], 2147483647 // tmpS = remove abit to final shift +s_lshr_b32 s12, s12, s14 // sMagicDiv Alg 2 +s_mul_i32 s13, s12, s[sgprItersPerTile] // Tile start iteration +s_add_u32 s14, s13, s[sgprItersPerTile] // Tile end iteration +s_sub_u32 s[sgprStreamKLocalStart], s[sgprStreamKIter], s13 // Local iteration start +s_min_u32 s[sgprStreamKLocalEnd], s[sgprStreamKIterEnd], s14 // 1. (Local) iteration end (SK tile) +s_sub_u32 s[sgprStreamKLocalEnd], s[sgprStreamKLocalEnd], s13 // 2. Local iteration end (SK tile) +s_cmp_eq_u64 s[sgprAddressFlags:sgprAddressFlags+1], 0x0 // Check for synchronizer +s_cbranch_scc0 label_SK_SplitUpdate // Jump to single kernel update +s_mov_b32 s13, s[sgprStreamKIterEnd] // Parallel reduction, work contained to single partial tile +s_branch label_SK_UpdateDone // Done update for parallel reduction +label_SK_SplitUpdate: +s_mul_i32 s15, s[sgprskTiles], s[sgprItersPerTile] // Total SK iters +s_sub_u32 s15, s[sgprTotalIters], s15 // Offset to first SK tile +s_mul_i32 s13, s[sgprskGrid], s[sgprItersPerTile] // DP iterations shift +s_add_u32 s13, s13, s[sgprStreamKIter] // Add DP shift +s_cmp_lt_u32 s13, s15 // Check if still in DP section +s_cbranch_scc1 label_SK_UpdateDone // Done update +s_mov_b32 s13, s14 // SK iterations shift +s_cmp_le_u32 s15, s[sgprStreamKIter] // Check if continuing in SK section +s_cbranch_scc1 label_SK_UpdateDone // Done update +s_mul_i32 s16, s[sgprskTiles], s[sgprItersPerTile] +s_mul_i32 s17, s[sgprSKItersPerWG], s[sgprskGrid] +s_sub_u32 s16, s16, s17 // skTiles * ItersPerTile - SKItersPerWG * skGrid +s_mul_i32 s[sgprStreamKIter], s[sgprStreamKIdx], s[sgprSKItersPerWG] // StreamK starting iteration (case: after extra iters) +s_add_u32 s[sgprStreamKIter], s[sgprStreamKIter], s16 // Add extra iters +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIter], s[sgprSKItersPerWG] // StreamK ending iteration (case: after extra iters) +s_add_u32 s18, s[sgprSKItersPerWG], 1 // Spread out extra iterations +s_mul_i32 s17, s[sgprStreamKIdx], s18 // StreamK starting iteration (case: before extra iters) +s_add_u32 s18, s17, s18 // StreamK ending iteration (case: before extra iters) +s_cmp_lt_u32 s[sgprStreamKIdx], s16 // Check if lane gets an extra iteration +s_cselect_b32 s[sgprStreamKIter], s17, s[sgprStreamKIter] // Set start iter +s_cselect_b32 s[sgprStreamKIterEnd], s18, s[sgprStreamKIterEnd] // Set end iter +s_add_u32 s13, s[sgprStreamKIter], s15 // Offset to start of SK section +s_add_u32 s[sgprStreamKIterEnd], s[sgprStreamKIterEnd], s15 // Offset to start of SK section +s_min_u32 s[sgprStreamKIterEnd], s[sgprStreamKIterEnd], s[sgprTotalIters] // Cap ending iter at total SK iters +s_cmp_lt_u32 s[sgprStreamKIter], s[sgprTotalIters] // Make sure there's work to do +s_cbranch_scc1 label_NoBranch_S4FDBQ587JJL6NOU // Only branch on scc0 +s_getpc_b64 s[16:17] // addr of next instr +s_add_i32 s18, label_KernelEnd, 4 // target branch offset +s_add_u32 s16, s16, s18 // add target branch offset +s_addc_u32 s17, s17, 0 // add high and carry +s_setpc_b64 s[16:17] // branch to label_KernelEnd +label_NoBranch_S4FDBQ587JJL6NOU: +label_SK_UpdateDone: +s_mov_b32 s[sgprStreamKIter], s13 // Store current iteration +/* Map StreamK tile index to wg0/1/2 */ +s_mul_i32 s13, s[sgprNumWorkGroups0], s[sgprNumWorkGroups1] // Total tiles +v_cvt_f32_u32 v16, s13 // TileID // nWG0*nWG1 +v_rcp_iflag_f32 v16, v16 // TileID // nWG0*nWG1 +v_cvt_f32_u32 v17, s12 // TileID // nWG0*nWG1 +v_mul_f32 v16, v16, v17 // TileID // nWG0*nWG1 +v_cvt_u32_f32 v16, v16 // TileID // nWG0*nWG1 +v_mul_u32_u24 v17, v16, s13 // TileID // nWG0*nWG1 +v_sub_u32 v17, s12, v17 // TileID // nWG0*nWG1 +v_cmpx_eq_u32 exec, v17, s13 // TileID // nWG0*nWG1 +v_add_u32 v16, 1, v16 // TileID // nWG0*nWG1 +v_mov_b32 v17, 0 // TileID // nWG0*nWG1 +s_mov_b64 exec, -1 // Reset exec +v_cmpx_gt_u32 exec, v17, s13 // overflow happened in remainder +v_sub_u32 v16, v16, 1 // quotient - 1 +v_mul_u32_u24 v17, v16, s13 // re-calculate remainder +v_sub_u32 v17, s12, v17 // re-calculate remainder +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s[sgprWorkGroup2], v16 // quotient +v_readfirstlane_b32 s14, v17 // remainder +v_cvt_f32_u32 v16, s[sgprNumWorkGroups0] // TileID // nWG0 +v_rcp_iflag_f32 v16, v16 // TileID // nWG0 +v_cvt_f32_u32 v17, s14 // TileID // nWG0 +v_mul_f32 v16, v16, v17 // TileID // nWG0 +v_cvt_u32_f32 v16, v16 // TileID // nWG0 +v_mul_u32_u24 v17, v16, s[sgprNumWorkGroups0] // TileID // nWG0 +v_sub_u32 v17, s14, v17 // TileID // nWG0 +v_cmpx_eq_u32 exec, v17, s[sgprNumWorkGroups0] // TileID // nWG0 +v_add_u32 v16, 1, v16 // TileID // nWG0 +v_mov_b32 v17, 0 // TileID // nWG0 +s_mov_b64 exec, -1 // Reset exec +v_cmpx_gt_u32 exec, v17, s[sgprNumWorkGroups0] // overflow happened in remainder +v_sub_u32 v16, v16, 1 // quotient - 1 +v_mul_u32_u24 v17, v16, s[sgprNumWorkGroups0] // re-calculate remainder +v_sub_u32 v17, s14, v17 // re-calculate remainder +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s[sgprWorkGroup1], v16 // quotient +v_readfirstlane_b32 s[sgprWorkGroup0], v17 // remainder + +v_cmp_eq_f32 vcc, s[sgprAlpha], 0.0 // s[Alpha] == 0.0f ? +s_cbranch_vccz label_SKAlphaCheck // branch if s[Alpha] != 0 +s_cmp_eq_u32 s[sgprStreamKLocalStart], 0 // does wg start tile? +s_cbranch_scc1 label_NoBranch_UR8VN3A1SJCPC6PO // Only branch on scc0 +s_getpc_b64 s[16:17] // addr of next instr +s_add_i32 s18, label_SK_CloseLoop, 4 // target branch offset +s_add_u32 s16, s16, s18 // add target branch offset +s_addc_u32 s17, s17, 0 // add high and carry +s_setpc_b64 s[16:17] // branch to label_SK_CloseLoop +label_NoBranch_UR8VN3A1SJCPC6PO: +s_mov_b32 s[sgprStreamKLocalEnd], s[sgprItersPerTile] // Skip iterations +label_SKAlphaCheck: +/* WGM Calculation */ +s_mov_b32 s12, s[sgprWGM] // Restore WGM +s_sext_i32_i16 s12, s12 // Restore WGM +s_cmp_gt_i32 s12, 1 // WGM > 1 ? +s_cbranch_scc1 label_WGMPositive // branch if WGM > 1 +s_cmp_ge_i32 s12, 0 // WGM >= 0 ? +s_cbranch_scc1 label_WGM // branch if WGM >= 0 +s_abs_i32 s12, s12 // abs(WGM) +v_cvt_f64_u32 v[16:17], s12 // s13 = s[sgprWorkGroup0] / s12 +v_rcp_f64 v[16:17], v[16:17] // s13 = s[sgprWorkGroup0] / s12 +v_cvt_f64_u32 v[18:19], s[sgprWorkGroup0] // s13 = s[sgprWorkGroup0] / s12 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s13 = s[sgprWorkGroup0] / s12 +v_cvt_u32_f64 v16, v[16:17] // s13 = s[sgprWorkGroup0] / s12 +v_mul_lo_u32 v17, v16, s12 // s13 = s[sgprWorkGroup0] / s12 +v_sub_u32 v18, s[sgprWorkGroup0], v17 // s13 = s[sgprWorkGroup0] / s12 +v_cmpx_ge_u32 exec, v18, s12 // s13 = s[sgprWorkGroup0] / s12 +v_add_u32 v16, v16, 1 // s13 = s[sgprWorkGroup0] / s12 +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s13, v16 // quotient +s_mul_i32 s16, s13, s12 // quotient * non-magic divisor +s_sub_u32 s16, s[sgprWorkGroup0], s16 // WorkGroup0=remainder +s_mul_i32 s16, s16, s[sgprNumWorkGroups1] // (wg1 % WGM)*NumWorkGroups1 +s_add_u32 s16, s16, s[sgprWorkGroup1] // wgSerial = wg0 + (wg1 % WGM)*NumWorkGroups1 +v_cvt_f64_u32 v[16:17], s12 // s14 = s[sgprNumWorkGroups0] / s12 +v_rcp_f64 v[16:17], v[16:17] // s14 = s[sgprNumWorkGroups0] / s12 +v_cvt_f64_u32 v[18:19], s[sgprNumWorkGroups0] // s14 = s[sgprNumWorkGroups0] / s12 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s14 = s[sgprNumWorkGroups0] / s12 +v_cvt_u32_f64 v16, v[16:17] // s14 = s[sgprNumWorkGroups0] / s12 +v_mul_lo_u32 v17, v16, s12 // s14 = s[sgprNumWorkGroups0] / s12 +v_sub_u32 v18, s[sgprNumWorkGroups0], v17 // s14 = s[sgprNumWorkGroups0] / s12 +v_cmpx_ge_u32 exec, v18, s12 // s14 = s[sgprNumWorkGroups0] / s12 +v_add_u32 v16, v16, 1 // s14 = s[sgprNumWorkGroups0] / s12 +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s14, v16 // quotient +s_mul_i32 s15, s12, s14 // quotient * non-magic divisor +s_sub_u32 s15, s[sgprNumWorkGroups0], s15 // NumWorkGroups0=remainder +s_cmp_eq_u32 s15, 0 // remainder == 0 ? +s_cmov_b32 s15, s12 // remainder = WGM if remainder == 0 +s_cmp_ge_u32 s13, s14 // blockId >= numFullBlocks ? +s_cselect_b32 s14, s15, s12 +v_cvt_f64_u32 v[16:17], s14 // s[sgprWorkGroup1] = s16 / s14 +v_rcp_f64 v[16:17], v[16:17] // s[sgprWorkGroup1] = s16 / s14 +v_cvt_f64_u32 v[18:19], s16 // s[sgprWorkGroup1] = s16 / s14 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s[sgprWorkGroup1] = s16 / s14 +v_cvt_u32_f64 v16, v[16:17] // s[sgprWorkGroup1] = s16 / s14 +v_mul_lo_u32 v17, v16, s14 // s[sgprWorkGroup1] = s16 / s14 +v_sub_u32 v18, s16, v17 // s[sgprWorkGroup1] = s16 / s14 +v_cmpx_ge_u32 exec, v18, s14 // s[sgprWorkGroup1] = s16 / s14 +v_add_u32 v16, v16, 1 // s[sgprWorkGroup1] = s16 / s14 +s_mov_b64 exec, -1 // Reset exec +v_mul_lo_u32 v17, v16, s14 // s[sgprWorkGroup1] = s16 / s14 +v_sub_u32 v18, s16, v17 // s[sgprWorkGroup1] = s16 / s14 +v_readfirstlane_b32 s[sgprWorkGroup1], v16 // quotient +v_readfirstlane_b32 s[sgprWorkGroup0], v18 // remainder +s_mul_i32 s[sgprWorkGroup0], s[sgprWorkGroup1], s14 // quotient * non-magic divisor +s_sub_u32 s[sgprWorkGroup0], s16, s[sgprWorkGroup0] // WorkGroup0=remainder +s_mul_i32 s13, s13, s12 // blockId * WGM +s_add_u32 s[sgprWorkGroup0], s[sgprWorkGroup0], s13 // wg1 += blockId * WGM +s_branch label_WGM +label_WGMPositive: +s_mov_b32 s12, s12 // WGM +v_cvt_f64_u32 v[16:17], s12 // s13 = s[sgprWorkGroup1] / s12 +v_rcp_f64 v[16:17], v[16:17] // s13 = s[sgprWorkGroup1] / s12 +v_cvt_f64_u32 v[18:19], s[sgprWorkGroup1] // s13 = s[sgprWorkGroup1] / s12 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s13 = s[sgprWorkGroup1] / s12 +v_cvt_u32_f64 v16, v[16:17] // s13 = s[sgprWorkGroup1] / s12 +v_mul_lo_u32 v17, v16, s12 // s13 = s[sgprWorkGroup1] / s12 +v_sub_u32 v18, s[sgprWorkGroup1], v17 // s13 = s[sgprWorkGroup1] / s12 +v_cmpx_ge_u32 exec, v18, s12 // s13 = s[sgprWorkGroup1] / s12 +v_add_u32 v16, v16, 1 // s13 = s[sgprWorkGroup1] / s12 +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s13, v16 // quotient +s_mul_i32 s16, s13, s12 // quotient * non-magic divisor +s_sub_u32 s16, s[sgprWorkGroup1], s16 // WorkGroup1=remainder +s_mul_i32 s16, s16, s[sgprNumWorkGroups0] // (wg1 % WGM)*NumWorkGroups0 +s_add_u32 s16, s16, s[sgprWorkGroup0] // wgSerial = wg0 + (wg1 % WGM)*NumWorkGroups0 +v_cvt_f64_u32 v[16:17], s12 // s14 = s[sgprNumWorkGroups1] / s12 +v_rcp_f64 v[16:17], v[16:17] // s14 = s[sgprNumWorkGroups1] / s12 +v_cvt_f64_u32 v[18:19], s[sgprNumWorkGroups1] // s14 = s[sgprNumWorkGroups1] / s12 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s14 = s[sgprNumWorkGroups1] / s12 +v_cvt_u32_f64 v16, v[16:17] // s14 = s[sgprNumWorkGroups1] / s12 +v_mul_lo_u32 v17, v16, s12 // s14 = s[sgprNumWorkGroups1] / s12 +v_sub_u32 v18, s[sgprNumWorkGroups1], v17 // s14 = s[sgprNumWorkGroups1] / s12 +v_cmpx_ge_u32 exec, v18, s12 // s14 = s[sgprNumWorkGroups1] / s12 +v_add_u32 v16, v16, 1 // s14 = s[sgprNumWorkGroups1] / s12 +s_mov_b64 exec, -1 // Reset exec +v_readfirstlane_b32 s14, v16 // quotient +s_mul_i32 s15, s12, s14 // quotient * non-magic divisor +s_sub_u32 s15, s[sgprNumWorkGroups1], s15 // NumWorkGroups1=remainder +s_cmp_eq_u32 s15, 0 // remainder == 0 ? +s_cmov_b32 s15, s12 // remainder = WGM if remainder == 0 +s_cmp_ge_u32 s13, s14 // blockId >= numFullBlocks ? +s_cselect_b32 s14, s15, s12 +v_cvt_f64_u32 v[16:17], s14 // s[sgprWorkGroup0] = s16 / s14 +v_rcp_f64 v[16:17], v[16:17] // s[sgprWorkGroup0] = s16 / s14 +v_cvt_f64_u32 v[18:19], s16 // s[sgprWorkGroup0] = s16 / s14 +v_mul_f64 v[16:17], v[16:17], v[18:19] // s[sgprWorkGroup0] = s16 / s14 +v_cvt_u32_f64 v16, v[16:17] // s[sgprWorkGroup0] = s16 / s14 +v_mul_lo_u32 v17, v16, s14 // s[sgprWorkGroup0] = s16 / s14 +v_sub_u32 v18, s16, v17 // s[sgprWorkGroup0] = s16 / s14 +v_cmpx_ge_u32 exec, v18, s14 // s[sgprWorkGroup0] = s16 / s14 +v_add_u32 v16, v16, 1 // s[sgprWorkGroup0] = s16 / s14 +s_mov_b64 exec, -1 // Reset exec +v_mul_lo_u32 v17, v16, s14 // s[sgprWorkGroup0] = s16 / s14 +v_sub_u32 v18, s16, v17 // s[sgprWorkGroup0] = s16 / s14 +v_readfirstlane_b32 s[sgprWorkGroup0], v16 // quotient +v_readfirstlane_b32 s[sgprWorkGroup1], v18 // remainder +s_mul_i32 s[sgprWorkGroup1], s[sgprWorkGroup0], s14 // quotient * non-magic divisor +s_sub_u32 s[sgprWorkGroup1], s16, s[sgprWorkGroup1] // WorkGroup1=remainder +s_mul_i32 s13, s13, s12 // blockId * WGM +s_add_u32 s[sgprWorkGroup1], s[sgprWorkGroup1], s13 // wg1 += blockId * WGM +label_WGM: + +/******************************************/ +/* Local Read Addresses */ +/******************************************/ + +/* local read addresses: tile assignments a/b */ +/* lr0I */ +v_and_b32 v17, 63, v[vgprSerial] // 0. thread id in wave: wtid = tid % wavelength(64) +v_and_b32 v16, 15, v17 // 1. N offset: nIdx = wtid % MI_N(16) + // 1. N offset: nOffset = nIdx * nStride(1) (multiplier is 1, do nothing) +/* Skip. 2. block offset: bnOffset = 0 when num1DBlocks = 1 */ +v_lshlrev_b32 v16, 2, v16 // 4. apply VectorWidth: bnOffset = bnOffset * vw(4) +v_lshrrev_b32 v17, 4, v17 // 5. K offset: kIdx = wtid / (MIN(16) * MIBB(1)) +v_lshl_add_u32 v16, v17, 9, v16 // 5. K offset: lrKOffset = kIdx * mStride(512); 6. offset in wave: lrOffset = bnOffset + lrKOffset +v_lshrrev_b32 v20, 6, v[vgprSerial] // 7. wave offset in N dimen: wtid = tid / dividedForWaveId(64) +v_and_b32 v20, 1, v20 // 7. wave offset in M dimen: wtid0 = wtid / num1DWaves(2) +v_lshl_add_u32 v16, v20, 6, v16 // 7. wave offset in M dimen: wOffset = wtid0 * W0Stride(64); 7. final local read offset: flrOffset = lrOffset + WOffset +/* lr1J */ +v_and_b32 v18, 63, v[vgprSerial] // 0. thread id in wave: wtid = tid % wavelength(64) +v_and_b32 v17, 15, v18 // 1. N offset: nIdx = wtid % MI_N(16) + // 1. N offset: nOffset = nIdx * nStride(1) (multiplier is 1, do nothing) +/* Skip. 2. block offset: bnOffset = 0 when num1DBlocks = 1 */ +v_lshlrev_b32 v17, 3, v17 // 4. apply VectorWidth: bnOffset = bnOffset * vw(8) +v_lshrrev_b32 v18, 4, v18 // 5. K offset: kIdx = wtid / (MIN(16) * MIBB(1)) +v_lshl_add_u32 v17, v18, 10, v17 // 5. K offset: lrKOffset = kIdx * mStride(1024); 6. offset in wave: lrOffset = bnOffset + lrKOffset +v_lshrrev_b32 v19, 7, v[vgprSerial] // 7. wave offset in N dimen: wtid = tid / dividedForWaveId(128) +v_and_b32 v19, 1, v19 // 7. wave offset in M dimen: wtid0 = wtid / num1DWaves(2) +v_lshl_add_u32 v17, v19, 7, v17 // 7. wave offset in M dimen: wOffset = wtid0 * W0Stride(128); 7. final local read offset: flrOffset = lrOffset + WOffset + +/* local read addresses: final offsets a */ +v_lshrrev_b32 v18, 6, v[vgprSerial] // 18 = Serial / 64 +v_lshrrev_b32 v18, 2, v18 // LSU offset: Get LSU wave_id +s_mov_b32 s12, 8192 // LSU offset: stride = lsuStride(64)*(MT0(128) + PAD0(0)) +v_mul_lo_u32 v18, s12, v18 // LSU offset: lsuoffset = wave_id*lsuStride*(MT0+PAD) +v_add_u32 v[vgprLocalReadAddrA], v18, v16 // Final Offset: offset = (lro0+lsuoffset)*bpeDS +v_lshlrev_b32 v[vgprLocalReadAddrA], 1, v[vgprLocalReadAddrA] // (multiple bpe) + +/* local read addresses: final offsets b */ +v_lshrrev_b32 v16, 6, v[vgprSerial] // 16 = Serial / 64 +v_lshrrev_b32 v16, 2, v16 // LSU offset: Get LSU wave_id +s_mov_b32 s12, 16384 // LSU offset: stride = lsuStride(64)*(MT1(256) + PAD1(0)) +v_mul_lo_u32 v16, s12, v16 // LSU offset: lsuoffset = wave_id*lsuStride*(MT1+PAD) +v_add_u32 v[vgprLocalReadAddrB], v16, v17 // Final Offset: offset = (lro1+lsuoffset)*bpeDS +v_lshlrev_b32 v[vgprLocalReadAddrB], 1, v[vgprLocalReadAddrB] // (multiple bpe) + +/* local read addresses: declare addresses a */ + +/* local read addresses: declare addresses b */ +v_add_co_u32 v[vgprLocalReadAddrB+0], vcc, 0x4000, v[vgprLocalReadAddrB+0] // += LdsOffsetB (lower) + +/******************************************/ +/* Local Write Addresses */ +/******************************************/ +/* LVCA = 16 */ +/* v17 = A-unroll = serial/LVCA */ +v_lshrrev_b32 v17, 4, v[vgprSerial] // 17 = Serial / 16 +v_and_b32 v16, 15, v[vgprSerial] // 16 = Serial % 16 +/* tile *= glvw */ +v_lshlrev_b32 v16, 3, v16 // v16 = v16 * 8 +v_mov_b32 v20, v17 // copy for GlobalSplitU +/* LVCB = 32 */ +/* v19 = B-unroll = serial/LVCB */ +v_lshrrev_b32 v19, 5, v[vgprSerial] // 19 = Serial / 32 +v_and_b32 v18, 31, v[vgprSerial] // 18 = Serial % 32 +/* tile *= glvw */ +v_lshlrev_b32 v18, 3, v18 // v18 = v18 * 8 +v_mov_b32 v21, v19 // copy for GlobalSplitU +/* lwaUnrollAssignmentA = v20 */ +/* lwaUnrollAssignmentB = v21 */ + +/* local write addresses: first offset a */ +v_mul_u32_u24 v[vgprLocalWriteAddrA], 0x80, v20 // lwAL**(MTA + PAD) +v_add_u32 v[vgprLocalWriteAddrA], v16, v[vgprLocalWriteAddrA] // lwFOA = (lwAA + lwAL*(MT0I+PAD)) +v_lshlrev_b32 v[vgprLocalWriteAddrA], 1, v[vgprLocalWriteAddrA] // (multiple bpe) + +/* local write addresses: first offset b */ +v_mul_u32_u24 v[vgprLocalWriteAddrB], 0x100, v21 // lwBL**(MTB + PAD) +v_add_u32 v[vgprLocalWriteAddrB], v18, v[vgprLocalWriteAddrB] // lwFOB = (lwBB + lwBL*(MT1J+PAD)) +v_lshlrev_b32 v[vgprLocalWriteAddrB], 1, v[vgprLocalWriteAddrB] // (multiple bpe) +v_add_co_u32 v[vgprLocalWriteAddrB], vcc, 0x4000, v[vgprLocalWriteAddrB] // lwFOB = lw1J + lwL*MT1J + LDS_OFFSET_B=16384 + +/* global read addresses: tile offset assignment a */ +/* graTileAssignmentA = v16 */ + +/* global read addresses: tile offset assignment b */ +/* graTileAssignmentB = v18 */ + +/* global read addresses: unroll assignment a */ +/* v17 */ + +/* global read addresses: unroll assignment b */ +/* v19 */ + +/* global read addresses: other free assignments */ +/* s[sgprWorkGroup2] */ + +/* global read addresses: tile offsets a */ +v_mov_b32 v22, v16 // groA0I_0 + +/* global read addresses: tile offsets b */ +v_mov_b32 v23, v18 // groB1J_0 + +/* global read addresses: unroll offsets a */ +v_mov_b32 v24, v17 // groAL_0 +v_add_co_u32 v25, vcc, 16, v24 // groAL_1 + LSPA +v_add_co_u32 v26, vcc, 16, v25 // groAL_2 + LSPA +v_add_co_u32 v27, vcc, 16, v26 // groAL_3 + LSPA + +/* global read addresses: unroll offsets b */ +v_mov_b32 v28, v19 // groBL_0 +v_add_co_u32 v29, vcc, 8, v28 // groBL_1 + LSPB +v_add_co_u32 v30, vcc, 8, v29 // groBL_2 + LSPB +v_add_co_u32 v31, vcc, 8, v30 // groBL_3 + LSPB +v_add_co_u32 v32, vcc, 8, v31 // groBL_4 + LSPB +v_add_co_u32 v33, vcc, 8, v32 // groBL_5 + LSPB +v_add_co_u32 v34, vcc, 8, v33 // groBL_6 + LSPB +v_add_co_u32 v35, vcc, 8, v34 // groBL_7 + LSPB + +/* global read addresses: shift a */ +s_mul_i32 s12, s[sgprWorkGroup0], 128 // WorkGroup[01] * MT +s_sub_u32 s12, s[sgprSizeI], s12 // edge = Size0I - WG*MT +s_sub_u32 s12, s12, 8 // edge -= margin(8) +v_mov_b32 v36, s12 // edge vgpr = Size0I- WG*MT - margin(8) +v_min_i32 v22, v36, v22 // offset = (offset < edge) ? offset(v22) : edge(v36) + +/* global read addresses: shift b */ +s_mul_i32 s12, s[sgprWorkGroup1], 256 // WorkGroup[01] * MT +s_sub_u32 s12, s[sgprSizeJ], s12 // edge = Size1J - WG*MT +s_sub_u32 s12, s12, 8 // edge -= margin(8) +v_mov_b32 v36, s12 // edge vgpr = Size1J- WG*MT - margin(8) +v_min_i32 v23, v36, v23 // offset = (offset < edge) ? offset(v23) : edge(v36) + +/* global read addresses: addresses a */ +/* max read offset = size[n] * stride[n-1] */ +s_mul_hi_u32 s15, s[sgprWorkGroup0], 128 // WorkGroup[01] * MT +s_mul_i32 s14, s[sgprWorkGroup0], 128 // WorkGroup[01] * MT +s_mul_i32 s12, s[sgprStreamKLocalStart], 64 // StreamK tile start offset +s_mul_hi_u32 s13, s12, s[sgprStrideAL] // StreamK tile start offset +s_mul_i32 s12, s12, s[sgprStrideAL] // StreamK tile start offset +s_add_u32 s14, s14, s12 // accum GsuOffset term to tilestart +s_addc_u32 s15, s15, s13 // accum GsuOffset term to tilestart +s_mov_b64 s[sgprShadowLimitA+0:sgprShadowLimitA+0+1], 1 // Init tensor size +s_sub_u32 s12, s[sgprSizeI], 1 // (size-1) +s_mul_hi_u32 s13, constStrideA0I, s12 // stride x (size-1) +s_mul_i32 s12, constStrideA0I, s12 // stride x (size-1) +s_add_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s12 // sum tensor size +s_addc_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s13 // sum tensor size +s_sub_u32 s12, s[sgprSizeL], 1 // (size-1) +s_mul_hi_u32 s13, s[sgprStrideAL], s12 // stride x (size-1) +s_mul_i32 s12, s[sgprStrideAL], s12 // stride x (size-1) +s_add_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s12 // sum tensor size +s_addc_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s13 // sum tensor size +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s14 // sub tileStart +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s15 // sub tileStart +s_lshl_b64 s[sgprShadowLimitA:sgprShadowLimitA+1], s[sgprShadowLimitA:sgprShadowLimitA+1], 1 // Set limit to use bytes (multiple bpe) +s_add_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], 16 // extend limit for pre-pad +s_addc_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], 0 // extend limit for pre-pad +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 +s_mul_hi_u32 s13, s[sgprStrideAK], s[sgprWorkGroup2] // Stride*WG +s_mul_i32 s12, s[sgprStrideAK], s[sgprWorkGroup2] // Stride*WG +s_add_u32 s14, s14, s12 // accum wg term to tilestart +s_addc_u32 s15, s15, s13 // accum wg term to tilestart +s_lshl_b64 s[14:15], s[14:15], 1 // tileStart (multiple bpe) +s_add_u32 s[sgprSrdA+0], s[sgprAddressA+0], s14 // SRD base = Address+ tileStart0 +s_addc_u32 s[sgprSrdA+1], s[sgprAddressA+1], s15 // SRD base = Address+ tileStart1 +s_mov_b32 s[sgprSrdA+3], Srd127_96 // Set bits 127_96 in SRD + +/* global read addresses: addresses b */ +/* max read offset = size[n] * stride[n-1] */ +s_mul_hi_u32 s15, s[sgprWorkGroup1], 256 // WorkGroup[01] * MT +s_mul_i32 s14, s[sgprWorkGroup1], 256 // WorkGroup[01] * MT +s_mul_i32 s12, s[sgprStreamKLocalStart], 64 // StreamK tile start offset +s_mul_hi_u32 s13, s12, s[sgprStrideBL] // StreamK tile start offset +s_mul_i32 s12, s12, s[sgprStrideBL] // StreamK tile start offset +s_add_u32 s14, s14, s12 // accum GsuOffset term to tilestart +s_addc_u32 s15, s15, s13 // accum GsuOffset term to tilestart +s_mov_b64 s[sgprShadowLimitB+0:sgprShadowLimitB+0+1], 1 // Init tensor size +s_sub_u32 s12, s[sgprSizeJ], 1 // (size-1) +s_mul_hi_u32 s13, constStrideB1J, s12 // stride x (size-1) +s_mul_i32 s12, constStrideB1J, s12 // stride x (size-1) +s_add_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s12 // sum tensor size +s_addc_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s13 // sum tensor size +s_sub_u32 s12, s[sgprSizeL], 1 // (size-1) +s_mul_hi_u32 s13, s[sgprStrideBL], s12 // stride x (size-1) +s_mul_i32 s12, s[sgprStrideBL], s12 // stride x (size-1) +s_add_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s12 // sum tensor size +s_addc_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s13 // sum tensor size +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s14 // sub tileStart +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s15 // sub tileStart +s_lshl_b64 s[sgprShadowLimitB:sgprShadowLimitB+1], s[sgprShadowLimitB:sgprShadowLimitB+1], 1 // Set limit to use bytes (multiple bpe) +s_add_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], 16 // extend limit for pre-pad +s_addc_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], 0 // extend limit for pre-pad +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 +s_mul_hi_u32 s13, s[sgprStrideBK], s[sgprWorkGroup2] // Stride*WG +s_mul_i32 s12, s[sgprStrideBK], s[sgprWorkGroup2] // Stride*WG +s_add_u32 s14, s14, s12 // accum wg term to tilestart +s_addc_u32 s15, s15, s13 // accum wg term to tilestart +s_lshl_b64 s[14:15], s[14:15], 1 // tileStart (multiple bpe) +s_add_u32 s[sgprSrdB+0], s[sgprAddressB+0], s14 // SRD base = Address+ tileStart0 +s_addc_u32 s[sgprSrdB+1], s[sgprAddressB+1], s15 // SRD base = Address+ tileStart1 +s_mov_b32 s[sgprSrdB+3], Srd127_96 // Set bits 127_96 in SRD + +/* global read addresses: final offsets a */ +/* ============================================================= */ +GLOBAL_OFFSET_A vgprGlobalReadOffsetA+0, 22, 24, 36 // gROA_0_0_0_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetA+0], 1, v[vgprGlobalReadOffsetA+0] // (multiple bpe) +GLOBAL_OFFSET_A vgprGlobalReadOffsetA+1, 22, 25, 36 // gROA_0_0_1_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetA+1], 1, v[vgprGlobalReadOffsetA+1] // (multiple bpe) +GLOBAL_OFFSET_A vgprGlobalReadOffsetA+2, 22, 26, 36 // gROA_0_0_2_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetA+2], 1, v[vgprGlobalReadOffsetA+2] // (multiple bpe) +GLOBAL_OFFSET_A vgprGlobalReadOffsetA+3, 22, 27, 36 // gROA_0_0_3_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetA+3], 1, v[vgprGlobalReadOffsetA+3] // (multiple bpe) +/* ============================================================= */ + +/* global read addresses: final offsets b */ +/* ============================================================= */ +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+0, 23, 28, 24 // gROB_0_0_0_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+0], 1, v[vgprGlobalReadOffsetB+0] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+1, 23, 29, 24 // gROB_0_0_1_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+1], 1, v[vgprGlobalReadOffsetB+1] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+2, 23, 30, 24 // gROB_0_0_2_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+2], 1, v[vgprGlobalReadOffsetB+2] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+3, 23, 31, 24 // gROB_0_0_3_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+3], 1, v[vgprGlobalReadOffsetB+3] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+4, 23, 32, 24 // gROB_0_0_4_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+4], 1, v[vgprGlobalReadOffsetB+4] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+5, 23, 33, 24 // gROB_0_0_5_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+5], 1, v[vgprGlobalReadOffsetB+5] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+6, 23, 34, 24 // gROB_0_0_6_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+6], 1, v[vgprGlobalReadOffsetB+6] // (multiple bpe) +GLOBAL_OFFSET_B vgprGlobalReadOffsetB+7, 23, 35, 24 // gROB_0_0_7_0 +v_lshlrev_b32 v[vgprGlobalReadOffsetB+7], 1, v[vgprGlobalReadOffsetB+7] // (multiple bpe) +/* ============================================================= */ + +/* global read addresses: increments a */ +s_mul_i32 s[sgprGlobalReadIncsA+0], 128, s[sgprStrideAL] // incrA unrollIdx) + +/* global read addresses: increments b */ +s_mul_i32 s[sgprGlobalReadIncsB+0], 128, s[sgprStrideBL] // incrB unrollIdx) +/* declare loop num iterations */ +s_sub_u32 s[sgprLoopCounterL], s[sgprStreamKLocalEnd], s[sgprStreamKLocalStart] // StreamK loop counter = localEnd - localStart +v_cmp_eq_f32 vcc, s[sgprAlpha], 0.0 // s[Alpha] == 0.0f ? +s_cbranch_vccz label_SKAlphaCheck2 // branch if s[Alpha] != 0 +s_mov_b32 s[sgprLoopCounterL], 0 // Skip iterations +label_SKAlphaCheck2: +s_and_b32 s13, 63, s[sgprSizesSum+0] // s13 = s[sgprSizesSum+0] % 64 +s_cmp_eq_u32 s13, 0 // numIterL == 0 +s_cselect_b32 s12, 0, 1 // check if size uses tail loop +s_cmp_eq_u32 s[sgprStreamKLocalEnd], s[sgprItersPerTile] // Check if WG processes final iteration of tile +s_cselect_b32 s12, s12, 0 // this WG runs tail loop +s_sub_u32 s[sgprLoopCounterL], s[sgprLoopCounterL], s12 // Adjust loop counter for tail loop +s_max_i32 s[sgprLoopCounterL], s[sgprLoopCounterL], 0 // Avoid setting negative value to loopCounter +s_mov_b32 s[sgprOrigLoopCounter], s[sgprLoopCounterL] // copy loop counter +s_and_b32 s14, s[sgprStaggerU], 0x1f00 +s_lshr_b32 s14, s14, 0x8 +s_and_b32 s15, s[sgprStaggerU], 0xe000 +s_and_b32 s[sgprStaggerU], s[sgprStaggerU], 0xff +s_mov_b32 s12, s[sgprStaggerU] // init staggerU +label_beginStaggerUIter: +s_lshl_b32 s13, s12, s14 // shift by StaggerUStride +s_cmp_ge_u32 s[sgprOrigLoopCounter], s13 // loopCount >= current shift Count +s_cbranch_scc1 label_endStaggerUIter // jump to end +s_lshr_b32 s12, s12, 1 // step down to smaller stagger +s_branch label_beginStaggerUIter // jump to begin +label_endStaggerUIter: +s_sub_u32 s13, s12, 1 // staggerU mask +s_cmp_ge_u32 s12, 1 // if current staggerU >= 1 +s_cselect_b32 s[sgprStaggerUIter], s13, 0 // set Mask +s_cmp_eq_u32 s15, 0x0 +s_cbranch_scc0 label_StaggerUMapping_1 +s_mov_b32 s12, s[sgprWorkGroup0] +s_branch label_staggerInputEnd +label_StaggerUMapping_1: +s_cmp_eq_u32 s15, 0x2000 +s_cbranch_scc0 label_StaggerUMapping_2 +s_mov_b32 s12, s[sgprWorkGroup1] +s_branch label_staggerInputEnd +label_StaggerUMapping_2: +s_cmp_eq_u32 s15, 0x4000 +s_cbranch_scc0 label_StaggerUMapping_3 +s_mov_b32 s12, -0x1 +s_branch label_staggerInputEnd +label_StaggerUMapping_3: +s_cmp_eq_u32 s15, 0x6000 +s_cbranch_scc0 label_StaggerUMapping_4 +s_mul_i32 s13, s[sgprNumWorkGroups0], s[sgprWorkGroup1] +s_add_u32 s12, s12, s13 +s_add_u32 s12, s12, s[sgprWorkGroup0] +s_branch label_staggerInputEnd +label_StaggerUMapping_4: +s_cmp_eq_u32 s15, 0x8000 +s_cbranch_scc0 label_staggerInputEnd +s_mov_b32 s12, -0x1 +s_branch label_staggerInputEnd +label_staggerInputEnd: +s_and_b32 s[sgprStaggerUIter], s[sgprStaggerUIter], s12 // Compute actual stagger start for this tile +s_lshl_b32 s[sgprStaggerUIter], s[sgprStaggerUIter], s14 // shift by StaggerUStride +s_cmp_gt_u32 s[sgprStreamKLocalStart], 0 // does wg start tile? +s_cmov_b32 s[sgprStaggerUIter], 0 // set stagger=0 for partial tiles +s_cmp_lt_u32 s[sgprStreamKLocalEnd], s[sgprItersPerTile] // does wg finish tile? +s_cmov_b32 s[sgprStaggerUIter], 0 // set stagger=0 for partial tiles + +/* SRDs += (StaggerUIter) * GlobalReadIncsA+0 */ +s_mul_hi_i32 s13, s[sgprStaggerUIter], s[sgprGlobalReadIncsA+0] // stagger byte offset +s_mul_i32 s12, s[sgprStaggerUIter], s[sgprGlobalReadIncsA+0] // stagger byte offset +s_mul_hi_i32 s[sgprWrapUA+1], s[sgprLoopCounterL], s[sgprGlobalReadIncsA+0] // Number of bytes accessed by the unroll loop +s_mul_i32 s[sgprWrapUA+0], s[sgprLoopCounterL], s[sgprGlobalReadIncsA+0] // Number of bytes accessed by the unroll loop +s_sub_u32 s[sgprWrapUA+0], s[sgprGlobalReadIncsA+0], s[sgprWrapUA+0] // remove one iteration +s_subb_u32 s[sgprWrapUA+1], 0, s[sgprWrapUA+1] // remove one iteration +s_add_u32 s[sgprSrdA+0], s[sgprSrdA+0], s12 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdA+1], s[sgprSrdA+1], s13 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s12 // limit -= inc) +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s13 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 + +/* SRDs += (StaggerUIter) * GlobalReadIncsB+0 */ +s_mul_hi_i32 s13, s[sgprStaggerUIter], s[sgprGlobalReadIncsB+0] // stagger byte offset +s_mul_i32 s12, s[sgprStaggerUIter], s[sgprGlobalReadIncsB+0] // stagger byte offset +s_mul_hi_i32 s[sgprWrapUB+1], s[sgprLoopCounterL], s[sgprGlobalReadIncsB+0] // Number of bytes accessed by the unroll loop +s_mul_i32 s[sgprWrapUB+0], s[sgprLoopCounterL], s[sgprGlobalReadIncsB+0] // Number of bytes accessed by the unroll loop +s_sub_u32 s[sgprWrapUB+0], s[sgprGlobalReadIncsB+0], s[sgprWrapUB+0] // remove one iteration +s_subb_u32 s[sgprWrapUB+1], 0, s[sgprWrapUB+1] // remove one iteration +s_add_u32 s[sgprSrdB+0], s[sgprSrdB+0], s12 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdB+1], s[sgprSrdB+1], s13 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s12 // limit -= inc) +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s13 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 +s_add_u32 s[sgprStaggerUIter], s[sgprStaggerUIter], 2 // Subtract (PGR-1); StaggerUIter now contains target iteration to wrap +/* local read addresses: init pointers a */ + +/* localReadInitPointers */ +/* local read addresses: init pointers b */ + +/* localReadInitPointers */ + +/* prefetch: global -> local */ +s_cmp_eq_u32 s[sgprLoopCounterL], 0 // at last iteration? +s_cbranch_scc1 label_ShadowInitStart // skip to ShadowInitStart iter b/c numIter==0 +buffer_load_dwordx4 v[vgprG2LA+0:vgprG2LA+0+3], v[vgprGlobalReadOffsetA+0], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LA+4:vgprG2LA+4+3], v[vgprGlobalReadOffsetA+1], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LA+8:vgprG2LA+8+3], v[vgprGlobalReadOffsetA+2], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LA+12:vgprG2LA+12+3], v[vgprGlobalReadOffsetA+3], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +buffer_load_dwordx4 v[vgprG2LB+0:vgprG2LB+0+3], v[vgprGlobalReadOffsetB+0], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LB+4:vgprG2LB+4+3], v[vgprGlobalReadOffsetB+1], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LB+8:vgprG2LB+8+3], v[vgprGlobalReadOffsetB+2], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LB+12:vgprG2LB+12+3], v[vgprGlobalReadOffsetB+3], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +buffer_load_dwordx4 v[vgprG2LB+16:vgprG2LB+16+3], v[vgprGlobalReadOffsetB+4], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_4_0 +buffer_load_dwordx4 v[vgprG2LB+20:vgprG2LB+20+3], v[vgprGlobalReadOffsetB+5], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_5_0 +buffer_load_dwordx4 v[vgprG2LB+24:vgprG2LB+24+3], v[vgprGlobalReadOffsetB+6], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_6_0 +buffer_load_dwordx4 v[vgprG2LB+28:vgprG2LB+28+3], v[vgprGlobalReadOffsetB+7], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_7_0 + +/* global read inc A loopL */ +s_add_u32 s14, s[sgprLoopCounterL], 1 // remove pf(1) +s_cmp_eq_u32 s[sgprStaggerUIter], s14 // Is this wrapIter? (pf) +s_cselect_b32 s12, s[sgprWrapUA+0], s[sgprGlobalReadIncsA+0] // incLower <- ? +s_cselect_b32 s13, s[sgprWrapUA+1], 0 // incUpper <- ? +s_add_u32 s[sgprSrdA+0], s[sgprSrdA+0], s12 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdA+1], s[sgprSrdA+1], s13 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s12 // limit -= inc) +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s13 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 + +/* global read inc B loopL */ +s_add_u32 s14, s[sgprLoopCounterL], 1 // remove pf(1) +s_cmp_eq_u32 s[sgprStaggerUIter], s14 // Is this wrapIter? (pf) +s_cselect_b32 s12, s[sgprWrapUB+0], s[sgprGlobalReadIncsB+0] // incLower <- ? +s_cselect_b32 s13, s[sgprWrapUB+1], 0 // incUpper <- ? +s_add_u32 s[sgprSrdB+0], s[sgprSrdB+0], s12 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdB+1], s[sgprSrdB+1], s13 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s12 // limit -= inc) +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s13 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 + +/******************************************/ +/* End setupNewTile */ +/******************************************/ +label_ShadowInitStart: +s_mov_b64 s[sgprSrdD+0:sgprSrdD+0+1], s[sgprAddressD+0:sgprAddressD+0+1] // init SRD base address +s_mov_b32 s[sgprSrdD+2], BufferOOB +s_mov_b32 s[sgprSrdD+3], Srd127_96 // Set bits 127_96 in post-loop SRD + +s_mov_b64 s[sgprSrdC+0:sgprSrdC+0+1], s[sgprAddressC+0:sgprAddressC+0+1] // init SRD base address +s_mov_b32 s[sgprSrdC+2], BufferOOB +s_mov_b32 s[sgprSrdC+3], Srd127_96 // Set bits 127_96 in post-loop SRD + +s_mov_b32 s60, 1 +s_mov_b32 s61, 1 +s_cmp_eq_u64 s[sgprAddressFlags:sgprAddressFlags+1], 0x0 // Check for synchronizer +s_cbranch_scc0 label_BPEDone // If synchronizer, use regular output BPE +s_cmp_eq_u32 s[sgprskTiles], 1 // split == 1 ? +s_cbranch_scc1 label_BPEDone // If split == 1, use reguler output BPE +s_mov_b32 s60, 1 +s_mov_b32 s61, 2 +label_BPEDone: + +s_mul_i32 s86, MT1, s[sgprWorkGroup1] // <- wg1*MT1 +s_mul_hi_u32 s85, s86, s[sgprStrideC1J] // ScaleC s86 by Stride +s_mul_i32 s84, s86, s[sgprStrideC1J] // ScaleC s86 by Stride +s_lshl_b64 s[84:85], s[84:85], s60 // scale by bpe +s_add_u32 s[sgprSrdC+0], s[sgprAddressC+0], s84 // add lo to SRD +s_addc_u32 s[sgprSrdC+1], s[sgprAddressC+1], s85 // add hi to SRD +s_mul_hi_u32 s85, s86, s[sgprStrideD1J] // ScaleD s86 by Stride +s_mul_i32 s84, s86, s[sgprStrideD1J] // ScaleD s86 by Stride +s_lshl_b64 s[84:85], s[84:85], s61 // scale by bpe +s_add_u32 s[sgprSrdD+0], s[sgprAddressD+0], s84 // add lo to SRD +s_addc_u32 s[sgprSrdD+1], s[sgprAddressD+1], s85 // add hi to SRD + +s_mul_hi_u32 s85, s[sgprWorkGroup2], s[sgprStrideCK] // ScaleC s[sgprWorkGroup2] by Stride +s_mul_i32 s84, s[sgprWorkGroup2], s[sgprStrideCK] // ScaleC s[sgprWorkGroup2] by Stride +s_lshl_b64 s[84:85], s[84:85], s60 // scale by bpe +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s84 // add lo to SRD +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], s85 // add hi to SRD +s_mul_hi_u32 s85, s[sgprWorkGroup2], s[sgprStrideDK] // ScaleD s[sgprWorkGroup2] by Stride +s_mul_i32 s84, s[sgprWorkGroup2], s[sgprStrideDK] // ScaleD s[sgprWorkGroup2] by Stride +s_lshl_b64 s[84:85], s[84:85], s61 // scale by bpe +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s84 // add lo to SRD +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], s85 // add hi to SRD + +s_cmp_eq_u64 s[sgprAddressFlags:sgprAddressFlags+1], 0x0 // Check for synchronizer +s_cbranch_scc0 label_SK_SplitSrd // Skip this block if using single-kernel stream-k fixup +s_cmp_eq_u32 s[sgprskTiles], 1 // split == 1 ? +s_cbranch_scc1 label_SK_SplitSrd // branch if split == 1 +// Split Output Buffer offset: Free0 + (Free1-1)*StrideC1J + (Free2-1)*StrideCK * SplitIdx * bpe%s +s_mul_hi_u32 s85, s[sgprSizesFree+0], s[sgprSkPartialIdx] // Free0 +s_mul_i32 s84, s[sgprSizesFree+0], s[sgprSkPartialIdx] // Free0 +s_sub_u32 s83, s[sgprSizesFree+1], 1 // Free1 +s_mul_i32 s83, s83, s[sgprSkPartialIdx] // Free1 +s_mul_hi_u32 s86, s83, s[sgprStrideC1J] // Free1 +s_mul_i32 s83, s83, s[sgprStrideC1J] // Free1 +s_add_u32 s84, s84, s83 // Free1 +s_addc_u32 s85, s85, s86 // Free1 +s_sub_u32 s83, s[sgprSizesFree+2], 1 // Free2 +s_mul_i32 s83, s83, s[sgprSkPartialIdx] // Free2 +s_mul_hi_u32 s86, s83, s[sgprStrideCK] // Free2 +s_mul_i32 s83, s83, s[sgprStrideCK] // Free2 +s_add_u32 s84, s84, s83 // Free2 +s_addc_u32 s85, s85, s86 // Free2 +s_lshl_b64 s[84:85], s[84:85], 2 // scale by bpe +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s84 // add lo GSU offset to SRD +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], s85 // add hi GSU offset to SRD +label_SK_SplitSrd: + +/* initC: remove ValuC vgpr buffer [0...0) from pool */ + +/* initC: remove acc vgpr buffer [0...128) from pool */ + +/* initC: remove ValuA/B vgpr buffer [16...136) from pool */ +v_accvgpr_write acc0, 0 // initC +v_accvgpr_write acc1, 0 // initC +v_accvgpr_write acc2, 0 // initC +v_accvgpr_write acc3, 0 // initC +v_accvgpr_write acc4, 0 // initC +v_accvgpr_write acc5, 0 // initC +v_accvgpr_write acc6, 0 // initC +v_accvgpr_write acc7, 0 // initC +v_accvgpr_write acc8, 0 // initC +v_accvgpr_write acc9, 0 // initC +v_accvgpr_write acc10, 0 // initC +v_accvgpr_write acc11, 0 // initC +v_accvgpr_write acc12, 0 // initC +v_accvgpr_write acc13, 0 // initC +v_accvgpr_write acc14, 0 // initC +v_accvgpr_write acc15, 0 // initC +v_accvgpr_write acc16, 0 // initC +v_accvgpr_write acc17, 0 // initC +v_accvgpr_write acc18, 0 // initC +v_accvgpr_write acc19, 0 // initC +v_accvgpr_write acc20, 0 // initC +v_accvgpr_write acc21, 0 // initC +v_accvgpr_write acc22, 0 // initC +v_accvgpr_write acc23, 0 // initC +v_accvgpr_write acc24, 0 // initC +v_accvgpr_write acc25, 0 // initC +v_accvgpr_write acc26, 0 // initC +v_accvgpr_write acc27, 0 // initC +v_accvgpr_write acc28, 0 // initC +v_accvgpr_write acc29, 0 // initC +v_accvgpr_write acc30, 0 // initC +v_accvgpr_write acc31, 0 // initC +v_accvgpr_write acc32, 0 // initC +v_accvgpr_write acc33, 0 // initC +v_accvgpr_write acc34, 0 // initC +v_accvgpr_write acc35, 0 // initC +v_accvgpr_write acc36, 0 // initC +v_accvgpr_write acc37, 0 // initC +v_accvgpr_write acc38, 0 // initC +v_accvgpr_write acc39, 0 // initC +v_accvgpr_write acc40, 0 // initC +v_accvgpr_write acc41, 0 // initC +v_accvgpr_write acc42, 0 // initC +v_accvgpr_write acc43, 0 // initC +v_accvgpr_write acc44, 0 // initC +v_accvgpr_write acc45, 0 // initC +v_accvgpr_write acc46, 0 // initC +v_accvgpr_write acc47, 0 // initC +v_accvgpr_write acc48, 0 // initC +v_accvgpr_write acc49, 0 // initC +v_accvgpr_write acc50, 0 // initC +v_accvgpr_write acc51, 0 // initC +v_accvgpr_write acc52, 0 // initC +v_accvgpr_write acc53, 0 // initC +v_accvgpr_write acc54, 0 // initC +v_accvgpr_write acc55, 0 // initC +v_accvgpr_write acc56, 0 // initC +v_accvgpr_write acc57, 0 // initC +v_accvgpr_write acc58, 0 // initC +v_accvgpr_write acc59, 0 // initC +v_accvgpr_write acc60, 0 // initC +v_accvgpr_write acc61, 0 // initC +v_accvgpr_write acc62, 0 // initC +v_accvgpr_write acc63, 0 // initC +v_accvgpr_write acc64, 0 // initC +v_accvgpr_write acc65, 0 // initC +v_accvgpr_write acc66, 0 // initC +v_accvgpr_write acc67, 0 // initC +v_accvgpr_write acc68, 0 // initC +v_accvgpr_write acc69, 0 // initC +v_accvgpr_write acc70, 0 // initC +v_accvgpr_write acc71, 0 // initC +v_accvgpr_write acc72, 0 // initC +v_accvgpr_write acc73, 0 // initC +v_accvgpr_write acc74, 0 // initC +v_accvgpr_write acc75, 0 // initC +v_accvgpr_write acc76, 0 // initC +v_accvgpr_write acc77, 0 // initC +v_accvgpr_write acc78, 0 // initC +v_accvgpr_write acc79, 0 // initC +v_accvgpr_write acc80, 0 // initC +v_accvgpr_write acc81, 0 // initC +v_accvgpr_write acc82, 0 // initC +v_accvgpr_write acc83, 0 // initC +v_accvgpr_write acc84, 0 // initC +v_accvgpr_write acc85, 0 // initC +v_accvgpr_write acc86, 0 // initC +v_accvgpr_write acc87, 0 // initC +v_accvgpr_write acc88, 0 // initC +v_accvgpr_write acc89, 0 // initC +v_accvgpr_write acc90, 0 // initC +v_accvgpr_write acc91, 0 // initC +v_accvgpr_write acc92, 0 // initC +v_accvgpr_write acc93, 0 // initC +v_accvgpr_write acc94, 0 // initC +v_accvgpr_write acc95, 0 // initC +v_accvgpr_write acc96, 0 // initC +v_accvgpr_write acc97, 0 // initC +v_accvgpr_write acc98, 0 // initC +v_accvgpr_write acc99, 0 // initC +v_accvgpr_write acc100, 0 // initC +v_accvgpr_write acc101, 0 // initC +v_accvgpr_write acc102, 0 // initC +v_accvgpr_write acc103, 0 // initC +v_accvgpr_write acc104, 0 // initC +v_accvgpr_write acc105, 0 // initC +v_accvgpr_write acc106, 0 // initC +v_accvgpr_write acc107, 0 // initC +v_accvgpr_write acc108, 0 // initC +v_accvgpr_write acc109, 0 // initC +v_accvgpr_write acc110, 0 // initC +v_accvgpr_write acc111, 0 // initC +v_accvgpr_write acc112, 0 // initC +v_accvgpr_write acc113, 0 // initC +v_accvgpr_write acc114, 0 // initC +v_accvgpr_write acc115, 0 // initC +v_accvgpr_write acc116, 0 // initC +v_accvgpr_write acc117, 0 // initC +v_accvgpr_write acc118, 0 // initC +v_accvgpr_write acc119, 0 // initC +v_accvgpr_write acc120, 0 // initC +v_accvgpr_write acc121, 0 // initC +v_accvgpr_write acc122, 0 // initC +v_accvgpr_write acc123, 0 // initC +v_accvgpr_write acc124, 0 // initC +v_accvgpr_write acc125, 0 // initC +v_accvgpr_write acc126, 0 // initC +v_accvgpr_write acc127, 0 // initC +s_cmp_eq_u32 s[sgprLoopCounterL], 0 // at last iteration? + +/* after InitC, skip to end of prefetch last iter if numIter==0 */ +s_cbranch_scc0 label_NoBranch_8S4L1KCK9VFC7AQU // Only branch on scc1 +s_getpc_b64 s[60:61] // addr of next instr +s_add_i32 s62, label_PrefetchGlobalLastIterEnd, 4 // target branch offset +s_add_u32 s60, s60, s62 // add target branch offset +s_addc_u32 s61, s61, 0 // add high and carry +s_setpc_b64 s[60:61] // branch to label_PrefetchGlobalLastIterEnd +label_NoBranch_8S4L1KCK9VFC7AQU: +s_waitcnt vmcnt(0) // wait for global read +s_barrier // For stream-k / persistent loop + +/* local write a */ +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+0:vgprG2LA+0+3] offset:0 // lwoA_0_0_0_0 = (0*LSCA) + (0*LSPA)(*MT0I+PAD) = 0 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+4:vgprG2LA+4+3] offset:4096 // lwoA_0_0_1_0 = (0*LSCA) + (1*LSPA)(*MT0I+PAD) = 4096 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+8:vgprG2LA+8+3] offset:8192 // lwoA_0_0_2_0 = (0*LSCA) + (2*LSPA)(*MT0I+PAD) = 8192 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+12:vgprG2LA+12+3] offset:12288 // lwoA_0_0_3_0 = (0*LSCA) + (3*LSPA)(*MT0I+PAD) = 12288 + +/* local write b */ +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+0:vgprG2LB+0+3] offset:0 // lwoB_0_0_0_0 = (0*LSCB) + (0*LSPB)(*MT1J+PAD) = 0 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+4:vgprG2LB+4+3] offset:4096 // lwoB_0_0_1_0 = (0*LSCB) + (1*LSPB)(*MT1J+PAD) = 4096 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+8:vgprG2LB+8+3] offset:8192 // lwoB_0_0_2_0 = (0*LSCB) + (2*LSPB)(*MT1J+PAD) = 8192 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+12:vgprG2LB+12+3] offset:12288 // lwoB_0_0_3_0 = (0*LSCB) + (3*LSPB)(*MT1J+PAD) = 12288 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+16:vgprG2LB+16+3] offset:16384 // lwoB_0_0_4_0 = (0*LSCB) + (4*LSPB)(*MT1J+PAD) = 16384 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+20:vgprG2LB+20+3] offset:20480 // lwoB_0_0_5_0 = (0*LSCB) + (5*LSPB)(*MT1J+PAD) = 20480 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+24:vgprG2LB+24+3] offset:24576 // lwoB_0_0_6_0 = (0*LSCB) + (6*LSPB)(*MT1J+PAD) = 24576 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+28:vgprG2LB+28+3] offset:28672 // lwoB_0_0_7_0 = (0*LSCB) + (7*LSPB)(*MT1J+PAD) = 28672 + +/* local write swap a */ + +/* local write swap b */ +s_cmp_eq_u32 s[sgprLoopCounterL], 0x1 // PGR=2 but only 1 loop +s_cbranch_scc1 label_skipPGR2_1 // PGR=2 but only 1 loop +buffer_load_dwordx4 v[vgprG2LA+0:vgprG2LA+0+3], v[vgprGlobalReadOffsetA+0], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LA+4:vgprG2LA+4+3], v[vgprGlobalReadOffsetA+1], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LA+8:vgprG2LA+8+3], v[vgprGlobalReadOffsetA+2], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LA+12:vgprG2LA+12+3], v[vgprGlobalReadOffsetA+3], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +buffer_load_dwordx4 v[vgprG2LB+0:vgprG2LB+0+3], v[vgprGlobalReadOffsetB+0], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LB+4:vgprG2LB+4+3], v[vgprGlobalReadOffsetB+1], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LB+8:vgprG2LB+8+3], v[vgprGlobalReadOffsetB+2], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LB+12:vgprG2LB+12+3], v[vgprGlobalReadOffsetB+3], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +buffer_load_dwordx4 v[vgprG2LB+16:vgprG2LB+16+3], v[vgprGlobalReadOffsetB+4], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_4_0 +buffer_load_dwordx4 v[vgprG2LB+20:vgprG2LB+20+3], v[vgprGlobalReadOffsetB+5], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_5_0 +buffer_load_dwordx4 v[vgprG2LB+24:vgprG2LB+24+3], v[vgprGlobalReadOffsetB+6], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_6_0 +buffer_load_dwordx4 v[vgprG2LB+28:vgprG2LB+28+3], v[vgprGlobalReadOffsetB+7], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_7_0 +s_branch label_skipPGR2_2 // jump to PGR=2 label +label_skipPGR2_1: +label_skipPGR2_2: +s_waitcnt lgkmcnt(0) // 0prefetch wait for local write +// Skip force waitcnt0 +s_barrier // LW to PLR, sync LDS0 + +/* local read prefetch a */ +ds_read_b64 v[vgprValuA_X0_I0_D0+0:vgprValuA_X0_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D1+0:vgprValuA_X0_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:256 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D2+0:vgprValuA_X0_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D3+0:vgprValuA_X0_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:768 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 + +/* local read prefetch b */ +ds_read_b128 v[vgprValuB_X0_I0_D0+0:vgprValuB_X0_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D1+0:vgprValuB_X0_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D2+0:vgprValuB_X0_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:1024 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D3+0:vgprValuB_X0_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:1536 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 + +/* local read inc a */ +/* N/A, lro->2048 */ +/* localReadDoCntA 1 localReadDoCntMXSA 0 localReadDoCntB 1 localReadDoCntMXSB 0 localReadDoCntM 0 */ + +/* local read inc b */ +/* N/A, lro->4096 */ +/* localReadDoCntA 1 localReadDoCntMXSA 0 localReadDoCntB 1 localReadDoCntMXSB 0 localReadDoCntM 0 */ + +/******************************************/ +/* Unrolled Loop(s) - Begin */ +/******************************************/ +label_openLoopL: +s_cmp_eq_u32 s[sgprLoopCounterL], 0x1 // LoopCounterL < EndCounter +s_cbranch_scc1 label_toPGR1 // PGR=2 but only 1 loop, toPGR1 +s_cmp_le_u32 s[sgprLoopCounterL], 0x2 // LoopCounterL < EndCounter +s_cbranch_scc1 label_LoopEndL // do not enter LoopL +.align 16 +label_LoopBeginL: + +/******************************************/ +/* Unrolled Loop 1/1 - Begin */ +/******************************************/ + +/* Begin Each Unroll: Check VGPR.checkin for INT8 LW */ + +/* iter 0 */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:0 */ +s_waitcnt lgkmcnt(0) // wait for prior local read local write old=0, new=0 newLW=0 newLR=0 for iteration == 0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+0], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+1], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+0], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+1], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+2], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+3], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:1 */ +ds_read_b64 v[vgprValuA_X1_I0_D0+0:vgprValuA_X1_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:4096 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 + +/* global read inc A loopL */ +s_cmp_eq_u32 s[sgprLoopCounterL], s[sgprStaggerUIter] // Is this the wrapIter? +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+4], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+5], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+6], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+7], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:2 */ +ds_read_b64 v[vgprValuA_X1_I0_D1+0:vgprValuA_X1_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:4352 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cselect_b32 s60, s[sgprWrapUA+0], s[sgprGlobalReadIncsA+0] // incLower <- ? +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+2], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+3], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+4], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+5], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:3 */ +ds_read_b64 v[vgprValuA_X1_I0_D2+0:vgprValuA_X1_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:4608 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cselect_b32 s61, s[sgprWrapUA+1], 0 // incUpper <- ? +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+6], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+7], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+8], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+9], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:4 */ +ds_read_b64 v[vgprValuA_X1_I0_D3+0:vgprValuA_X1_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:4864 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +s_add_u32 s[sgprSrdA+0], s[sgprSrdA+0], s60 // gra SRD += inc(lower) +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+10], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+11], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+12], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+13], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:5 */ +ds_read_b128 v[vgprValuB_X1_I0_D0+0:vgprValuB_X1_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 +s_addc_u32 s[sgprSrdA+1], s[sgprSrdA+1], s61 // gra SRD += inc(upper) +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+14], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+15], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:6 */ +ds_read_b128 v[vgprValuB_X1_I0_D1+0:vgprValuB_X1_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s60 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:7 */ +ds_read_b128 v[vgprValuB_X1_I0_D2+0:vgprValuB_X1_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:9216 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s61 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:8 */ +ds_read_b128 v[vgprValuB_X1_I0_D3+0:vgprValuB_X1_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:9728 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:9 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D0+0:vgprValuA_X2_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:10 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D1+0:vgprValuA_X2_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:8448 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 + +/* global read inc B loopL */ +s_cmp_eq_u32 s[sgprLoopCounterL], s[sgprStaggerUIter] // Is this the wrapIter? +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:11 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D2+0:vgprValuA_X2_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s60, s[sgprWrapUB+0], s[sgprGlobalReadIncsB+0] // incLower <- ? +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:12 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D3+0:vgprValuA_X2_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:8960 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s61, s[sgprWrapUB+1], 0 // incUpper <- ? +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:13 */ +/* localReadsVacancy: latencyLeft 2 */ +s_add_u32 s[sgprSrdB+0], s[sgprSrdB+0], s60 // gra SRD += inc(lower) +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:14 */ +/* localReadsVacancy: latencyLeft 2 */ +s_addc_u32 s[sgprSrdB+1], s[sgprSrdB+1], s61 // gra SRD += inc(upper) +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:15 */ +/* localReadsVacancy: latencyLeft 2 */ +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s60 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:16 */ +/* localReadsVacancy: latencyLeft 2 */ +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s61 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:17 */ +/* localReadsVacancy: latencyLeft 2 */ +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:18 */ +/* localReadsVacancy: latencyLeft 2 */ +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:19 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:20 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:21 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:22 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:23 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:24 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:25 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:26 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:27 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:28 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:29 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:30 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:31 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=-1 numReadsIterA=1 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=-1 numReadsIterB=1 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 1 */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:32 */ +ds_read_b128 v[vgprValuB_X2_I0_D0+0:vgprValuB_X2_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:16384 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +s_waitcnt lgkmcnt(5) // wait for prior local read local write old=4, new=5 newLW=0 newLR=1 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+0], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+1], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+0], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+1], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+2], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+3], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:33 */ +ds_read_b128 v[vgprValuB_X2_I0_D1+0:vgprValuB_X2_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:16896 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+4], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+5], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+6], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+7], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:34 */ +ds_read_b128 v[vgprValuB_X2_I0_D2+0:vgprValuB_X2_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:17408 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+2], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+3], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+4], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+5], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:35 */ +ds_read_b128 v[vgprValuB_X2_I0_D3+0:vgprValuB_X2_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:17920 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+6], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+7], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+8], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+9], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:36 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D0+0:vgprValuA_X3_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:12288 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+10], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+11], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+12], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+13], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:37 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D1+0:vgprValuA_X3_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:12544 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+14], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+15], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:38 */ +/* schedule remaining localreads for one buffer scheduling */ +ds_read_b64 v[vgprValuA_X3_I0_D2+0:vgprValuA_X3_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:12800 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X3_I0_D3+0:vgprValuA_X3_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:13056 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D0+0:vgprValuB_X3_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:24576 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D1+0:vgprValuB_X3_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:25088 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D2+0:vgprValuB_X3_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:25600 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D3+0:vgprValuB_X3_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:26112 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +/* localReadsVacancy: latencyLeft 2 */ +/* 1 LDS buffer: read-sync-write */ +s_waitcnt lgkmcnt(0) +s_barrier +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:39 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+0:vgprG2LA+0+3] offset:0 // lwoA_0_0_0_0 = (0*LSCA) + (0*LSPA)(*MT0I+PAD) = 0 +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:40 */ +buffer_load_dwordx4 v[vgprG2LA+0:vgprG2LA+0+3], v[vgprGlobalReadOffsetA+0], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:41 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:42 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:43 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:44 */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:45 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+4:vgprG2LA+4+3] offset:4096 // lwoA_0_0_1_0 = (0*LSCA) + (1*LSPA)(*MT0I+PAD) = 4096 +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:46 */ +buffer_load_dwordx4 v[vgprG2LA+4:vgprG2LA+4+3], v[vgprGlobalReadOffsetA+1], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:47 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:48 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:49 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:50 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:51 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+8:vgprG2LA+8+3] offset:8192 // lwoA_0_0_2_0 = (0*LSCA) + (2*LSPA)(*MT0I+PAD) = 8192 +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:52 */ +buffer_load_dwordx4 v[vgprG2LA+8:vgprG2LA+8+3], v[vgprGlobalReadOffsetA+2], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:53 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:54 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:55 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:56 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:57 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+12:vgprG2LA+12+3] offset:12288 // lwoA_0_0_3_0 = (0*LSCA) + (3*LSPA)(*MT0I+PAD) = 12288 +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:58 */ +buffer_load_dwordx4 v[vgprG2LA+12:vgprG2LA+12+3], v[vgprGlobalReadOffsetA+3], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:59 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:60 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:61 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:62 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:63 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=0 numReadsIterA=2 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=0 numReadsIterB=2 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 2 (reset local read pointers iteration) (swap local read pointers iteration) */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:64 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+0:vgprG2LB+0+3] offset:0 // lwoB_0_0_0_0 = (0*LSCB) + (0*LSPB)(*MT1J+PAD) = 0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+0], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+1], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+0], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+1], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+2], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+3], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:65 */ +buffer_load_dwordx4 v[vgprG2LB+0:vgprG2LB+0+3], v[vgprGlobalReadOffsetB+0], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+4], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+5], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+6], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+7], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:66 */ +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+2], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+3], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+4], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+5], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:67 */ +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+6], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+7], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+8], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+9], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:68 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+10], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+11], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+12], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+13], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:69 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+14], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+15], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:70 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+4:vgprG2LB+4+3] offset:4096 // lwoB_0_0_1_0 = (0*LSCB) + (1*LSPB)(*MT1J+PAD) = 4096 +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:71 */ +buffer_load_dwordx4 v[vgprG2LB+4:vgprG2LB+4+3], v[vgprGlobalReadOffsetB+1], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:72 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:73 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:74 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:75 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:76 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+8:vgprG2LB+8+3] offset:8192 // lwoB_0_0_2_0 = (0*LSCB) + (2*LSPB)(*MT1J+PAD) = 8192 +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:77 */ +buffer_load_dwordx4 v[vgprG2LB+8:vgprG2LB+8+3], v[vgprGlobalReadOffsetB+2], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:78 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:79 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:80 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:81 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:82 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+12:vgprG2LB+12+3] offset:12288 // lwoB_0_0_3_0 = (0*LSCB) + (3*LSPB)(*MT1J+PAD) = 12288 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:83 */ +buffer_load_dwordx4 v[vgprG2LB+12:vgprG2LB+12+3], v[vgprGlobalReadOffsetB+3], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:84 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:85 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:86 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:87 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:88 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:89 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+16:vgprG2LB+16+3] offset:16384 // lwoB_0_0_4_0 = (0*LSCB) + (4*LSPB)(*MT1J+PAD) = 16384 +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:90 */ +buffer_load_dwordx4 v[vgprG2LB+16:vgprG2LB+16+3], v[vgprGlobalReadOffsetB+4], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_4_0 +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:91 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:92 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:93 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:94 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:95 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+20:vgprG2LB+20+3] offset:20480 // lwoB_0_0_5_0 = (0*LSCB) + (5*LSPB)(*MT1J+PAD) = 20480 + +/* local read swap offsets a */ + +/* local read swap offsets b */ + +/* local read init pointers a */ + +/* localReadInitPointers */ + +/* local read init pointers b */ + +/* localReadInitPointers */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] + +/* iter 3 (swap and reset local write pointers iteration) */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:96 */ +buffer_load_dwordx4 v[vgprG2LB+20:vgprG2LB+20+3], v[vgprGlobalReadOffsetB+5], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_5_0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+0], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+1], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+0], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+1], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+2], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+3], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:97 */ +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+4], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+5], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+6], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+7], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:98 */ +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+2], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+3], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+4], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+5], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:99 */ +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+6], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+7], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+8], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+9], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:100 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+10], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+11], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+12], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+13], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:101 */ +/* sched write - iter 3 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+24:vgprG2LB+24+3] offset:24576 // lwoB_0_0_6_0 = (0*LSCB) + (6*LSPB)(*MT1J+PAD) = 24576 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+14], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+15], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:102 */ +buffer_load_dwordx4 v[vgprG2LB+24:vgprG2LB+24+3], v[vgprGlobalReadOffsetB+6], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_6_0 +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:103 */ +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:104 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:105 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:106 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:107 */ +/* sched write - iter 3 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+28:vgprG2LB+28+3] offset:28672 // lwoB_0_0_7_0 = (0*LSCB) + (7*LSPB)(*MT1J+PAD) = 28672 +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:108 */ +buffer_load_dwordx4 v[vgprG2LB+28:vgprG2LB+28+3], v[vgprGlobalReadOffsetB+7], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_7_0 + +/* local write swap offsets a */ + +/* local write swap offsets b */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:109 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:110 */ +s_waitcnt lgkmcnt(0) // 3wait for local write +// Skip force waitcnt0 +s_barrier // PGR, and wait until LW done to sync LDS1 +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:111 */ +ds_read_b64 v[vgprValuA_X0_I0_D0+0:vgprValuA_X0_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:112 */ +ds_read_b64 v[vgprValuA_X0_I0_D1+0:vgprValuA_X0_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:256 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:113 */ +ds_read_b64 v[vgprValuA_X0_I0_D2+0:vgprValuA_X0_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:114 */ +ds_read_b64 v[vgprValuA_X0_I0_D3+0:vgprValuA_X0_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:768 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:115 */ +ds_read_b128 v[vgprValuB_X0_I0_D0+0:vgprValuB_X0_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:116 */ +ds_read_b128 v[vgprValuB_X0_I0_D1+0:vgprValuB_X0_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:117 */ +ds_read_b128 v[vgprValuB_X0_I0_D2+0:vgprValuB_X0_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:1024 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:118 */ +ds_read_b128 v[vgprValuB_X0_I0_D3+0:vgprValuB_X0_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:1536 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:119 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:120 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:121 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:122 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:123 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:124 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:125 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:126 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:127 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] + +/******************************************/ +/* Unrolled Loop - End */ +/******************************************/ + +/* closeLoop loopL finalLoop=1 tailLoop=0 */ +s_sub_u32 s[sgprLoopCounterL], s[sgprLoopCounterL], 1 // dec counterL +s_cmp_eq_i32 s[sgprLoopCounterL], 0x2 // counterL==2 +s_cbranch_scc0 label_LoopBeginL // restart LoopL +label_LoopEndL: + +/* Before NLL: Check VGPR.checkin for INT8 LW */ + +/******************************************/ +/* Ord. NoGlobalLoadLoop_1 - Begin */ +/******************************************/ + +/* iter 0 */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:0 */ +s_waitcnt lgkmcnt(0) // wait for prior local read local write old=0, new=0 newLW=0 newLR=0 for iteration == 0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+0], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+1], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+0], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+1], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+2], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+3], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:1 */ +ds_read_b64 v[vgprValuA_X1_I0_D0+0:vgprValuA_X1_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:4096 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 + +/* global read inc A loopL */ +s_cmp_eq_u32 s[sgprLoopCounterL], s[sgprStaggerUIter] // Is this the wrapIter? +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+4], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+5], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+6], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+7], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:2 */ +ds_read_b64 v[vgprValuA_X1_I0_D1+0:vgprValuA_X1_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:4352 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cselect_b32 s60, s[sgprWrapUA+0], s[sgprGlobalReadIncsA+0] // incLower <- ? +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+2], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+3], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+4], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+5], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:3 */ +ds_read_b64 v[vgprValuA_X1_I0_D2+0:vgprValuA_X1_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:4608 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cselect_b32 s61, s[sgprWrapUA+1], 0 // incUpper <- ? +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+6], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+7], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+8], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+9], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:4 */ +ds_read_b64 v[vgprValuA_X1_I0_D3+0:vgprValuA_X1_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:4864 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +s_add_u32 s[sgprSrdA+0], s[sgprSrdA+0], s60 // gra SRD += inc(lower) +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+10], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+11], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+12], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+13], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:5 */ +ds_read_b128 v[vgprValuB_X1_I0_D0+0:vgprValuB_X1_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 +s_addc_u32 s[sgprSrdA+1], s[sgprSrdA+1], s61 // gra SRD += inc(upper) +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+14], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+15], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:6 */ +ds_read_b128 v[vgprValuB_X1_I0_D1+0:vgprValuB_X1_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s60 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:7 */ +ds_read_b128 v[vgprValuB_X1_I0_D2+0:vgprValuB_X1_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:9216 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s61 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:8 */ +ds_read_b128 v[vgprValuB_X1_I0_D3+0:vgprValuB_X1_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:9728 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:9 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D0+0:vgprValuA_X2_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:10 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D1+0:vgprValuA_X2_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:8448 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 + +/* global read inc B loopL */ +s_cmp_eq_u32 s[sgprLoopCounterL], s[sgprStaggerUIter] // Is this the wrapIter? +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:11 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D2+0:vgprValuA_X2_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s60, s[sgprWrapUB+0], s[sgprGlobalReadIncsB+0] // incLower <- ? +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:12 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D3+0:vgprValuA_X2_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:8960 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +s_cselect_b32 s61, s[sgprWrapUB+1], 0 // incUpper <- ? +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:13 */ +/* localReadsVacancy: latencyLeft 2 */ +s_add_u32 s[sgprSrdB+0], s[sgprSrdB+0], s60 // gra SRD += inc(lower) +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:14 */ +/* localReadsVacancy: latencyLeft 2 */ +s_addc_u32 s[sgprSrdB+1], s[sgprSrdB+1], s61 // gra SRD += inc(upper) +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:15 */ +/* localReadsVacancy: latencyLeft 2 */ +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s60 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:16 */ +/* localReadsVacancy: latencyLeft 2 */ +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s61 // limit -= inc) +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:17 */ +/* localReadsVacancy: latencyLeft 2 */ +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:18 */ +/* localReadsVacancy: latencyLeft 2 */ +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:19 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:20 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:21 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:22 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:23 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:24 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:25 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:26 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:27 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:28 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:29 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:30 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:31 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=-1 numReadsIterA=1 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=-1 numReadsIterB=1 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 1 */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:32 */ +ds_read_b128 v[vgprValuB_X2_I0_D0+0:vgprValuB_X2_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:16384 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +s_waitcnt lgkmcnt(5) // wait for prior local read local write old=4, new=5 newLW=0 newLR=1 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+0], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+1], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+0], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+1], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+2], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+3], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:33 */ +ds_read_b128 v[vgprValuB_X2_I0_D1+0:vgprValuB_X2_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:16896 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+4], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+5], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+6], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+7], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:34 */ +ds_read_b128 v[vgprValuB_X2_I0_D2+0:vgprValuB_X2_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:17408 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+2], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+3], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+4], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+5], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:35 */ +ds_read_b128 v[vgprValuB_X2_I0_D3+0:vgprValuB_X2_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:17920 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+6], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+7], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+8], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+9], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:36 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D0+0:vgprValuA_X3_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:12288 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+10], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+11], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+12], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+13], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:37 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D1+0:vgprValuA_X3_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:12544 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+14], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+15], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:38 */ +/* schedule remaining localreads for one buffer scheduling */ +ds_read_b64 v[vgprValuA_X3_I0_D2+0:vgprValuA_X3_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:12800 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X3_I0_D3+0:vgprValuA_X3_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:13056 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D0+0:vgprValuB_X3_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:24576 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D1+0:vgprValuB_X3_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:25088 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D2+0:vgprValuB_X3_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:25600 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X3_I0_D3+0:vgprValuB_X3_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:26112 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +/* localReadsVacancy: latencyLeft 2 */ +/* 1 LDS buffer: read-sync-write */ +s_waitcnt lgkmcnt(0) +s_barrier +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:39 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(11) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+0:vgprG2LA+0+3] offset:0 // lwoA_0_0_0_0 = (0*LSCA) + (0*LSPA)(*MT0I+PAD) = 0 +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:40 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:41 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:42 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:43 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:44 */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:45 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(10) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+4:vgprG2LA+4+3] offset:4096 // lwoA_0_0_1_0 = (0*LSCA) + (1*LSPA)(*MT0I+PAD) = 4096 +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:46 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:47 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:48 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:49 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:50 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:51 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(9) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+8:vgprG2LA+8+3] offset:8192 // lwoA_0_0_2_0 = (0*LSCA) + (2*LSPA)(*MT0I+PAD) = 8192 +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:52 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:53 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:54 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:55 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:56 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:57 */ +/* sched write - iter 1 writesPerItem=1 */ +s_waitcnt vmcnt(8) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+12:vgprG2LA+12+3] offset:12288 // lwoA_0_0_3_0 = (0*LSCA) + (3*LSPA)(*MT0I+PAD) = 12288 +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:58 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:59 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:60 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:61 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:62 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:63 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=0 numReadsIterA=2 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=0 numReadsIterB=2 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 2 (reset local read pointers iteration) (swap local read pointers iteration) */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:64 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(7) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+0:vgprG2LB+0+3] offset:0 // lwoB_0_0_0_0 = (0*LSCB) + (0*LSPB)(*MT1J+PAD) = 0 +s_waitcnt lgkmcnt(13) // wait for prior local read local write old=8, new=13 newLW=5 newLR=0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+0], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+1], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+0], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+1], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+2], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+3], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:65 */ +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+4], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+5], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+6], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+7], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:66 */ +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+2], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+3], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+4], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+5], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:67 */ +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+6], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+7], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+8], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+9], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:68 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+10], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+11], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+12], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+13], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:69 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+14], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+15], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:70 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(6) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+4:vgprG2LB+4+3] offset:4096 // lwoB_0_0_1_0 = (0*LSCB) + (1*LSPB)(*MT1J+PAD) = 4096 +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:71 */ +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:72 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:73 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:74 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:75 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:76 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(5) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+8:vgprG2LB+8+3] offset:8192 // lwoB_0_0_2_0 = (0*LSCB) + (2*LSPB)(*MT1J+PAD) = 8192 +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:77 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:78 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:79 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:80 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:81 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:82 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(4) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+12:vgprG2LB+12+3] offset:12288 // lwoB_0_0_3_0 = (0*LSCB) + (3*LSPB)(*MT1J+PAD) = 12288 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:83 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:84 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:85 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:86 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:87 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:88 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:89 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(3) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+16:vgprG2LB+16+3] offset:16384 // lwoB_0_0_4_0 = (0*LSCB) + (4*LSPB)(*MT1J+PAD) = 16384 +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:90 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:91 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:92 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:93 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:94 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:95 */ +/* sched write - iter 2 writesPerItem=1 */ +s_waitcnt vmcnt(2) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+20:vgprG2LB+20+3] offset:20480 // lwoB_0_0_5_0 = (0*LSCB) + (5*LSPB)(*MT1J+PAD) = 20480 + +/* local read swap offsets a */ + +/* local read swap offsets b */ + +/* local read init pointers a */ + +/* localReadInitPointers */ + +/* local read init pointers b */ + +/* localReadInitPointers */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=1 numReadsIterA=3 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=1 numReadsIterB=3 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 3 (swap and reset local write pointers iteration) */ +/* grEndMfmaIndex:18, lwStartMfmaIndex:39, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:38 */ +/* mfmaIndex:96 */ +s_waitcnt lgkmcnt(6) // wait for prior local read local write old=0, new=6 newLW=6 newLR=0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+0], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+1], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+0], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+1], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+2], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+3], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:97 */ +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+4], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+5], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+6], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+7], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:98 */ +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+2], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+3], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+4], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+5], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:99 */ +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+6], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+7], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+8], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+9], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:100 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+10], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+11], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+12], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+13], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:101 */ +/* sched write - iter 3 writesPerItem=1 */ +s_waitcnt vmcnt(1) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+24:vgprG2LB+24+3] offset:24576 // lwoB_0_0_6_0 = (0*LSCB) + (6*LSPB)(*MT1J+PAD) = 24576 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+14], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+15], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:102 */ +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:103 */ +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:104 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:105 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:106 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:107 */ +/* sched write - iter 3 writesPerItem=1 */ +s_waitcnt vmcnt(0) // wait for global read before writing to local +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+28:vgprG2LB+28+3] offset:28672 // lwoB_0_0_7_0 = (0*LSCB) + (7*LSPB)(*MT1J+PAD) = 28672 +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:108 */ + +/* local write swap offsets a */ + +/* local write swap offsets b */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:109 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:110 */ +s_waitcnt lgkmcnt(0) // 3wait for local write +// Skip force waitcnt0 +s_barrier // noLoadLoop sync LDS0 +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:111 */ +ds_read_b64 v[vgprValuA_X0_I0_D0+0:vgprValuA_X0_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:112 */ +ds_read_b64 v[vgprValuA_X0_I0_D1+0:vgprValuA_X0_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:256 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:113 */ +ds_read_b64 v[vgprValuA_X0_I0_D2+0:vgprValuA_X0_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:114 */ +ds_read_b64 v[vgprValuA_X0_I0_D3+0:vgprValuA_X0_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:768 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:115 */ +ds_read_b128 v[vgprValuB_X0_I0_D0+0:vgprValuB_X0_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:116 */ +ds_read_b128 v[vgprValuB_X0_I0_D1+0:vgprValuB_X0_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:117 */ +ds_read_b128 v[vgprValuB_X0_I0_D2+0:vgprValuB_X0_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:1024 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:118 */ +ds_read_b128 v[vgprValuB_X0_I0_D3+0:vgprValuB_X0_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:1536 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:119 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:120 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:121 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:122 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:123 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:124 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:125 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:126 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:127 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=1 */ +/* dataAtIterA=2 numReadsIterA=3 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=2 numReadsIterB=3 skipReadsIterB=1 readsPerIterB=4 */ +label_toPGR1: + +/******************************************/ +/* Ord. NoLoadLoop - Begin */ +/******************************************/ + +/* iter 0 (last unrolled loop) */ +/* grEndMfmaIndex:0, lwStartMfmaIndex:108, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:107 */ +/* mfmaIndex:0 */ +s_waitcnt lgkmcnt(0) // wait for prior local read local write old=0, new=0 newLW=0 newLR=0 for iteration == 0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+0], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+1], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+0], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+1], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+2], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+3], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:1 */ +ds_read_b64 v[vgprValuA_X1_I0_D0+0:vgprValuA_X1_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:4096 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X0_I0+4], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+5], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+6], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+7], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:2 */ +ds_read_b64 v[vgprValuA_X1_I0_D1+0:vgprValuA_X1_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:4352 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+2], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+3], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+4], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+5], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:3 */ +ds_read_b64 v[vgprValuA_X1_I0_D2+0:vgprValuA_X1_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:4608 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X0_I0+6], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+7], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+8], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+9], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:4 */ +ds_read_b64 v[vgprValuA_X1_I0_D3+0:vgprValuA_X1_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:4864 // L -> Reg lro=2048 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+10], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+11], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+12], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+13], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:5 */ +ds_read_b128 v[vgprValuB_X1_I0_D0+0:vgprValuB_X1_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=1 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X0_I0+14], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+15], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:6 */ +ds_read_b128 v[vgprValuB_X1_I0_D1+0:vgprValuB_X1_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=1 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:7 */ +ds_read_b128 v[vgprValuB_X1_I0_D2+0:vgprValuB_X1_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:9216 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=1 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:8 */ +ds_read_b128 v[vgprValuB_X1_I0_D3+0:vgprValuB_X1_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:9728 // L -> Reg lro=4096 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=1 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:9 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D0+0:vgprValuA_X2_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:8192 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:10 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D1+0:vgprValuA_X2_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:8448 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:11 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D2+0:vgprValuA_X2_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:8704 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:12 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X2_I0_D3+0:vgprValuA_X2_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:8960 // L -> Reg lro=4096 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:13 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:14 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:15 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:16 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:17 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:18 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:19 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:20 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:21 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:22 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:23 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:24 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:25 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:26 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:27 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:28 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:29 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:30 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:31 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=-1 numReadsIterA=1 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=-1 numReadsIterB=1 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 1 (last unrolled loop) */ +/* grEndMfmaIndex:0, lwStartMfmaIndex:108, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:107 */ +/* mfmaIndex:32 */ +ds_read_b128 v[vgprValuB_X2_I0_D0+0:vgprValuB_X2_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:16384 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=2 iui=0 sync LDS0 +s_waitcnt lgkmcnt(5) // wait for prior local read local write old=4, new=5 newLW=0 newLR=1 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+0], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+1], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+0], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+1], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+2], v[vgprValuA_X1_I0_D1+0], v[vgprValuA_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+3], v[vgprValuA_X1_I0_D3+0], v[vgprValuA_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:33 */ +ds_read_b128 v[vgprValuB_X2_I0_D1+0:vgprValuB_X2_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:16896 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X1_I0+4], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+5], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X1_I0+6], v[vgprValuA_X1_I0_D1+1], v[vgprValuA_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X1_I0+7], v[vgprValuA_X1_I0_D3+1], v[vgprValuA_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:34 */ +ds_read_b128 v[vgprValuB_X2_I0_D2+0:vgprValuB_X2_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:17408 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+2], v[vgprValuB_X1_I0_D1+0], v[vgprValuB_X1_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+3], v[vgprValuB_X1_I0_D3+0], v[vgprValuB_X1_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+4], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+5], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:35 */ +ds_read_b128 v[vgprValuB_X2_I0_D3+0:vgprValuB_X2_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:17920 // L -> Reg lro=8192 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=2 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X1_I0+6], v[vgprValuB_X1_I0_D1+1], v[vgprValuB_X1_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+7], v[vgprValuB_X1_I0_D3+1], v[vgprValuB_X1_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+8], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+9], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X1_I0+0+0+0:vgprValuB_X1_I0+0+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:36 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D0+0:vgprValuA_X3_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:12288 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+10], v[vgprValuB_X1_I0_D1+2], v[vgprValuB_X1_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+11], v[vgprValuB_X1_I0_D3+2], v[vgprValuB_X1_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+12], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X1_I0+13], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:37 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D1+0:vgprValuA_X3_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:12544 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X1_I0+14], v[vgprValuB_X1_I0_D1+3], v[vgprValuB_X1_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X1_I0+15], v[vgprValuB_X1_I0_D3+3], v[vgprValuB_X1_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:38 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D2+0:vgprValuA_X3_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:12800 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:39 */ +/* localReadsVacancy: latencyLeft 2 */ +ds_read_b64 v[vgprValuA_X3_I0_D3+0:vgprValuA_X3_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:13056 // L -> Reg lro=6144 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X1_I0+2+0+0:vgprValuB_X1_I0+2+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:40 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:41 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:42 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:43 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X1_I0+4+0+0:vgprValuB_X1_I0+4+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:44 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:45 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:46 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:47 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X1_I0+6+0+0:vgprValuB_X1_I0+6+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:48 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:49 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:50 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:51 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X1_I0+8+0+0:vgprValuB_X1_I0+8+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:52 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:53 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:54 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:55 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X1_I0+10+0+0:vgprValuB_X1_I0+10+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:56 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:57 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:58 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:59 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X1_I0+12+0+0:vgprValuB_X1_I0+12+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:60 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+0+0+0:vgprValuA_X1_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:61 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+2+0+0:vgprValuA_X1_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:62 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+4+0+0:vgprValuA_X1_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:63 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X1_I0+14+0+0:vgprValuB_X1_I0+14+0+0+1], v[vgprValuA_X1_I0+6+0+0:vgprValuA_X1_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=0 numReadsIterA=2 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=0 numReadsIterB=2 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 2 (last unrolled loop) */ +/* grEndMfmaIndex:0, lwStartMfmaIndex:108, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:107 */ +/* mfmaIndex:64 */ +ds_read_b128 v[vgprValuB_X3_I0_D0+0:vgprValuB_X3_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:24576 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=3 iui=0 sync LDS0 +s_waitcnt lgkmcnt(5) // wait for prior local read local write old=4, new=5 newLW=0 newLR=1 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+0], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+1], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+0], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+1], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+2], v[vgprValuA_X2_I0_D1+0], v[vgprValuA_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+3], v[vgprValuA_X2_I0_D3+0], v[vgprValuA_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:65 */ +ds_read_b128 v[vgprValuB_X3_I0_D1+0:vgprValuB_X3_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:25088 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X2_I0+4], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+5], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X2_I0+6], v[vgprValuA_X2_I0_D1+1], v[vgprValuA_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X2_I0+7], v[vgprValuA_X2_I0_D3+1], v[vgprValuA_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:66 */ +ds_read_b128 v[vgprValuB_X3_I0_D2+0:vgprValuB_X3_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:25600 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+2], v[vgprValuB_X2_I0_D1+0], v[vgprValuB_X2_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+3], v[vgprValuB_X2_I0_D3+0], v[vgprValuB_X2_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+4], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+5], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:67 */ +ds_read_b128 v[vgprValuB_X3_I0_D3+0:vgprValuB_X3_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:26112 // L -> Reg lro=12288 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=3 iui=0 sync LDS0 +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X2_I0+6], v[vgprValuB_X2_I0_D1+1], v[vgprValuB_X2_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+7], v[vgprValuB_X2_I0_D3+1], v[vgprValuB_X2_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+8], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+9], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X2_I0+0+0+0:vgprValuB_X2_I0+0+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:68 */ +/* localReadsVacancy: latencyLeft 2 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+10], v[vgprValuB_X2_I0_D1+2], v[vgprValuB_X2_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+11], v[vgprValuB_X2_I0_D3+2], v[vgprValuB_X2_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+12], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X2_I0+13], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:69 */ +/* localReadsVacancy: latencyLeft 2 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X2_I0+14], v[vgprValuB_X2_I0_D1+3], v[vgprValuB_X2_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X2_I0+15], v[vgprValuB_X2_I0_D3+3], v[vgprValuB_X2_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:70 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:71 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X2_I0+2+0+0:vgprValuB_X2_I0+2+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:72 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:73 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:74 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:75 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X2_I0+4+0+0:vgprValuB_X2_I0+4+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:76 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:77 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:78 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:79 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X2_I0+6+0+0:vgprValuB_X2_I0+6+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:80 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:81 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:82 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:83 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X2_I0+8+0+0:vgprValuB_X2_I0+8+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:84 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:85 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:86 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:87 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X2_I0+10+0+0:vgprValuB_X2_I0+10+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:88 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:89 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:90 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:91 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X2_I0+12+0+0:vgprValuB_X2_I0+12+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:92 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+0+0+0:vgprValuA_X2_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:93 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+2+0+0:vgprValuA_X2_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:94 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+4+0+0:vgprValuA_X2_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:95 */ +/* localReadsVacancy: latencyLeft 2 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X2_I0+14+0+0:vgprValuB_X2_I0+14+0+0+1], v[vgprValuA_X2_I0+6+0+0:vgprValuA_X2_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=1 numReadsIterA=3 skipReadsIterA=1 readsPerIterA=4 */ +/* dataAtIterB=1 numReadsIterB=3 skipReadsIterB=1 readsPerIterB=4 */ + +/* iter 3 (last unrolled loop) */ +/* grEndMfmaIndex:0, lwStartMfmaIndex:108, lwEndMfmaIndex:108 */ +/* numMfmaForLR:17, syncPlrMfmaIndex:110 , sync1LdsMfmaIndex:107 */ +/* mfmaIndex:96 */ +s_waitcnt lgkmcnt(0) // wait for prior local read local write old=0, new=0 newLW=0 newLR=0 +/* pack scheduling: packAIdx:2, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+0], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+1], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+0], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+1], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+2], v[vgprValuA_X3_I0_D1+0], v[vgprValuA_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+3], v[vgprValuA_X3_I0_D3+0], v[vgprValuA_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +/* mfmaIndex:97 */ +/* pack scheduling: packAIdx:4, packBIdx:2 */ +v_perm_b32 v[vgprValuA_X3_I0+4], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+5], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X3_I0+6], v[vgprValuA_X3_I0_D1+1], v[vgprValuA_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X3_I0+7], v[vgprValuA_X3_I0_D3+1], v[vgprValuA_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +/* mfmaIndex:98 */ +/* pack scheduling: packAIdx:6, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+2], v[vgprValuB_X3_I0_D1+0], v[vgprValuB_X3_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+3], v[vgprValuB_X3_I0_D3+0], v[vgprValuB_X3_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+4], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+5], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +/* mfmaIndex:99 */ +/* pack scheduling: packAIdx:8, packBIdx:2 */ +v_perm_b32 v[vgprValuB_X3_I0+6], v[vgprValuB_X3_I0_D1+1], v[vgprValuB_X3_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+7], v[vgprValuB_X3_I0_D3+1], v[vgprValuB_X3_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+8], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+9], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X3_I0+0+0+0:vgprValuB_X3_I0+0+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +/* mfmaIndex:100 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+10], v[vgprValuB_X3_I0_D1+2], v[vgprValuB_X3_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+11], v[vgprValuB_X3_I0_D3+2], v[vgprValuB_X3_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+12], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X3_I0+13], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +/* mfmaIndex:101 */ +/* pack scheduling: packAIdx:8, packBIdx:4 */ +v_perm_b32 v[vgprValuB_X3_I0+14], v[vgprValuB_X3_I0_D1+3], v[vgprValuB_X3_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X3_I0+15], v[vgprValuB_X3_I0_D3+3], v[vgprValuB_X3_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +/* mfmaIndex:102 */ +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +/* mfmaIndex:103 */ +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X3_I0+2+0+0:vgprValuB_X3_I0+2+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +/* mfmaIndex:104 */ +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +/* mfmaIndex:105 */ +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +/* mfmaIndex:106 */ +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +/* mfmaIndex:107 */ +/* schedule remaining localreads for one buffer scheduling */ +/* 1 LDS buffer: read-sync-write */ +s_waitcnt lgkmcnt(0) +s_barrier +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X3_I0+4+0+0:vgprValuB_X3_I0+4+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +/* mfmaIndex:108 */ +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +/* mfmaIndex:109 */ +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +/* mfmaIndex:110 */ +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +/* mfmaIndex:111 */ +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X3_I0+6+0+0:vgprValuB_X3_I0+6+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +/* mfmaIndex:112 */ +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +/* mfmaIndex:113 */ +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +/* mfmaIndex:114 */ +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +/* mfmaIndex:115 */ +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X3_I0+8+0+0:vgprValuB_X3_I0+8+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +/* mfmaIndex:116 */ +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +/* mfmaIndex:117 */ +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +/* mfmaIndex:118 */ +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +/* mfmaIndex:119 */ +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X3_I0+10+0+0:vgprValuB_X3_I0+10+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +/* mfmaIndex:120 */ +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +/* mfmaIndex:121 */ +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +/* mfmaIndex:122 */ +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +/* mfmaIndex:123 */ +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X3_I0+12+0+0:vgprValuB_X3_I0+12+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +/* mfmaIndex:124 */ +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+0+0+0:vgprValuA_X3_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +/* mfmaIndex:125 */ +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+2+0+0:vgprValuA_X3_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +/* mfmaIndex:126 */ +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+4+0+0:vgprValuA_X3_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +/* mfmaIndex:127 */ +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X3_I0+14+0+0:vgprValuB_X3_I0+14+0+0+1], v[vgprValuA_X3_I0+6+0+0:vgprValuA_X3_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] +/* numPrefetchIter=0 */ +/* dataAtIterA=2 numReadsIterA=3 skipReadsIterA=0 readsPerIterA=4 */ +/* dataAtIterB=2 numReadsIterB=3 skipReadsIterB=0 readsPerIterB=4 */ +label_toPGR1end_OrdNLL: +label_PrefetchGlobalLastIterEnd: + +/* Tail: add ValuA/B vgpr buffer [16...136) to pool */ + +/* Tail: add address/G2L vgpr [136...184) to pool */ + +/******************************************/ +/* Tail Loop */ +/******************************************/ + +/* local write reset offsets a */ + +/* local write reset offsets b */ +/* Check out VGPR (numG2LA,numG2LB,numG2LMetadata) = (16,32,0) */ +.set vgprG2LA_BASE, 16 +.set vgprG2LA, vgprG2LA_BASE+0 +.set vgprG2LB_BASE, 32 +.set vgprG2LB, vgprG2LB_BASE+0 + +// numIterL = LOCAL_SPLITU * min(sizeL % LOCAL_DEPTHU, DEPTHU / LOCAL_SPLITU) +s_and_b32 s[sgprLoopCounterL], 63, s[sgprSizesSum+0] // s[sgprLoopCounterL] = s[sgprSizesSum+0] % 64 +s_cmp_lt_u32 s[sgprStreamKLocalEnd], s[sgprItersPerTile] // Check if WG processes final iteration of tile +s_cmov_b32 s[sgprLoopCounterL], 0 // This WG not completing tile +s_cmp_eq_u32 s[sgprLoopCounterL], 0 // numIterL == 0 +s_mov_b32 s[sgprOrigLoopCounter], 0 // repurpose to count each localRead increment +s_cbranch_scc1 label_SkipTailLoopL // skip to end of tail loop b/c numIter==0 + +/* remove stagger offsets for tail loop */ +// removeStagger A +s_sub_i32 s84, 3, s[sgprStaggerUIter] +s_cmp_ge_i32 s84, 0 +s_cbranch_scc0 label_Negative_J5DQFVGFWLXU2DUR +s_mul_hi_u32 s85, s84, s[sgprGlobalReadIncsA+0] // start offset S in bytes +s_mul_i32 s84, s84, s[sgprGlobalReadIncsA+0] // start offset S in bytes +s_branch label_MultiplyDone_DLSAQLEVYLOBCPNL +label_Negative_J5DQFVGFWLXU2DUR: +s_abs_i32 s84, s84 +s_mul_hi_u32 s85, s84, s[sgprGlobalReadIncsA+0] // start offset S in bytes +s_mul_i32 s84, s84, s[sgprGlobalReadIncsA+0] // start offset S in bytes +s_xor_b32 s84, s84, 0xffffffff +s_xor_b32 s85, s85, 0xffffffff +s_add_u32 s84, s84, 0x1 +s_addc_u32 s85, s85, 0 +label_MultiplyDone_DLSAQLEVYLOBCPNL: +s_sub_u32 s84, s84, s[sgprWrapUA] // S - WrapU +s_subb_u32 s85, s85, s[sgprWrapUA+1] // S - WrapU +s_add_u32 s[sgprSrdA+0], s[sgprSrdA+0], s84 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdA+1], s[sgprSrdA+1], s85 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitA+0], s[sgprShadowLimitA+0], s84 // limit -= inc) +s_subb_u32 s[sgprShadowLimitA+1], s[sgprShadowLimitA+1], s85 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitA+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdA+2], s[sgprShadowLimitA+0], BufferLimit // Move shadow to real if we are within 2^32 +// removeStagger B +s_sub_i32 s84, 3, s[sgprStaggerUIter] +s_cmp_ge_i32 s84, 0 +s_cbranch_scc0 label_Negative_LQI6BOBE0EY8XIP1 +s_mul_hi_u32 s85, s84, s[sgprGlobalReadIncsB+0] // start offset S in bytes +s_mul_i32 s84, s84, s[sgprGlobalReadIncsB+0] // start offset S in bytes +s_branch label_MultiplyDone_9N1QELR2XL4Z0HRB +label_Negative_LQI6BOBE0EY8XIP1: +s_abs_i32 s84, s84 +s_mul_hi_u32 s85, s84, s[sgprGlobalReadIncsB+0] // start offset S in bytes +s_mul_i32 s84, s84, s[sgprGlobalReadIncsB+0] // start offset S in bytes +s_xor_b32 s84, s84, 0xffffffff +s_xor_b32 s85, s85, 0xffffffff +s_add_u32 s84, s84, 0x1 +s_addc_u32 s85, s85, 0 +label_MultiplyDone_9N1QELR2XL4Z0HRB: +s_sub_u32 s84, s84, s[sgprWrapUB] // S - WrapU +s_subb_u32 s85, s85, s[sgprWrapUB+1] // S - WrapU +s_add_u32 s[sgprSrdB+0], s[sgprSrdB+0], s84 // gra SRD += inc(lower) +s_addc_u32 s[sgprSrdB+1], s[sgprSrdB+1], s85 // gra SRD += inc(upper) +s_sub_u32 s[sgprShadowLimitB+0], s[sgprShadowLimitB+0], s84 // limit -= inc) +s_subb_u32 s[sgprShadowLimitB+1], s[sgprShadowLimitB+1], s85 // limit -= inc) +s_cmp_eq_u32 s[sgprShadowLimitB+1], 0 // are we within 2^32? +s_cselect_b32 s[sgprSrdB+2], s[sgprShadowLimitB+0], BufferLimit // Move shadow to real if we are within 2^32 + +/* Update M0 for DTLDS */ + +/* Tail global read A */ +buffer_load_dwordx4 v[vgprG2LA+0:vgprG2LA+0+3], v[vgprGlobalReadOffsetA+0], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LA+4:vgprG2LA+4+3], v[vgprGlobalReadOffsetA+1], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LA+8:vgprG2LA+8+3], v[vgprGlobalReadOffsetA+2], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LA+12:vgprG2LA+12+3], v[vgprGlobalReadOffsetA+3], s[sgprSrdA:sgprSrdA+3], 0 offen offset:0 // G -> Reg 0_0_3_0 + +/* Update M0 for DTLDS */ + +/* Tail global read B */ +buffer_load_dwordx4 v[vgprG2LB+0:vgprG2LB+0+3], v[vgprGlobalReadOffsetB+0], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_0_0 +buffer_load_dwordx4 v[vgprG2LB+4:vgprG2LB+4+3], v[vgprGlobalReadOffsetB+1], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_1_0 +buffer_load_dwordx4 v[vgprG2LB+8:vgprG2LB+8+3], v[vgprGlobalReadOffsetB+2], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_2_0 +buffer_load_dwordx4 v[vgprG2LB+12:vgprG2LB+12+3], v[vgprGlobalReadOffsetB+3], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_3_0 +buffer_load_dwordx4 v[vgprG2LB+16:vgprG2LB+16+3], v[vgprGlobalReadOffsetB+4], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_4_0 +buffer_load_dwordx4 v[vgprG2LB+20:vgprG2LB+20+3], v[vgprGlobalReadOffsetB+5], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_5_0 +buffer_load_dwordx4 v[vgprG2LB+24:vgprG2LB+24+3], v[vgprGlobalReadOffsetB+6], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_6_0 +buffer_load_dwordx4 v[vgprG2LB+28:vgprG2LB+28+3], v[vgprGlobalReadOffsetB+7], s[sgprSrdB:sgprSrdB+3], 0 offen offset:0 // G -> Reg 0_0_7_0 +s_waitcnt vmcnt(0) // 2wait for global read +// Skip force waitcnt0 +s_barrier + +/* local write a */ +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+0:vgprG2LA+0+3] offset:0 // lwoA_0_0_0_0 = (0*LSCA) + (0*LSPA)(*MT0I+PAD) = 0 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+4:vgprG2LA+4+3] offset:4096 // lwoA_0_0_1_0 = (0*LSCA) + (1*LSPA)(*MT0I+PAD) = 4096 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+8:vgprG2LA+8+3] offset:8192 // lwoA_0_0_2_0 = (0*LSCA) + (2*LSPA)(*MT0I+PAD) = 8192 +ds_write_b128 v[vgprLocalWriteAddrA+0], v[vgprG2LA+12:vgprG2LA+12+3] offset:12288 // lwoA_0_0_3_0 = (0*LSCA) + (3*LSPA)(*MT0I+PAD) = 12288 + +/* local write b */ +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+0:vgprG2LB+0+3] offset:0 // lwoB_0_0_0_0 = (0*LSCB) + (0*LSPB)(*MT1J+PAD) = 0 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+4:vgprG2LB+4+3] offset:4096 // lwoB_0_0_1_0 = (0*LSCB) + (1*LSPB)(*MT1J+PAD) = 4096 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+8:vgprG2LB+8+3] offset:8192 // lwoB_0_0_2_0 = (0*LSCB) + (2*LSPB)(*MT1J+PAD) = 8192 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+12:vgprG2LB+12+3] offset:12288 // lwoB_0_0_3_0 = (0*LSCB) + (3*LSPB)(*MT1J+PAD) = 12288 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+16:vgprG2LB+16+3] offset:16384 // lwoB_0_0_4_0 = (0*LSCB) + (4*LSPB)(*MT1J+PAD) = 16384 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+20:vgprG2LB+20+3] offset:20480 // lwoB_0_0_5_0 = (0*LSCB) + (5*LSPB)(*MT1J+PAD) = 20480 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+24:vgprG2LB+24+3] offset:24576 // lwoB_0_0_6_0 = (0*LSCB) + (6*LSPB)(*MT1J+PAD) = 24576 +ds_write_b128 v[vgprLocalWriteAddrB+0], v[vgprG2LB+28:vgprG2LB+28+3] offset:28672 // lwoB_0_0_7_0 = (0*LSCB) + (7*LSPB)(*MT1J+PAD) = 28672 + +/* Recalc local read offsets */ +s_waitcnt lgkmcnt(0) // 5wait for local write +// Skip force waitcnt0 +s_barrier // Tail loop LW->LR, sync LDS0 +.set vgprG2LA_BASE, UNDEF +.set vgprG2LA, UNDEF +.set vgprG2LB_BASE, UNDEF +.set vgprG2LB, UNDEF +.set vgprValuA_X0_I0_BASE, 16 +.set vgprValuA_X0_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X1_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X2_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X3_I0, vgprValuA_X0_I0_BASE+0 +.set vgprValuA_X0_I0_D0_PACK, 24 +.set vgprValuA_X0_I0_D0, vgprValuA_X0_I0_D0_PACK+0 +.set vgprValuA_X0_I0_D1, vgprValuA_X0_I0_D0_PACK+2 +.set vgprValuA_X0_I0_D2, vgprValuA_X0_I0_D0_PACK+4 +.set vgprValuA_X0_I0_D3, vgprValuA_X0_I0_D0_PACK+6 +.set vgprValuA_X1_I0_D0, vgprValuA_X0_I0_D0_PACK+8 +.set vgprValuA_X1_I0_D1, vgprValuA_X0_I0_D0_PACK+10 +.set vgprValuA_X1_I0_D2, vgprValuA_X0_I0_D0_PACK+12 +.set vgprValuA_X1_I0_D3, vgprValuA_X0_I0_D0_PACK+14 +.set vgprValuA_X2_I0_D0, vgprValuA_X0_I0_D0_PACK+16 +.set vgprValuA_X2_I0_D1, vgprValuA_X0_I0_D0_PACK+18 +.set vgprValuA_X2_I0_D2, vgprValuA_X0_I0_D0_PACK+20 +.set vgprValuA_X2_I0_D3, vgprValuA_X0_I0_D0_PACK+22 +.set vgprValuA_X3_I0_D0, vgprValuA_X0_I0_D0_PACK+24 +.set vgprValuA_X3_I0_D1, vgprValuA_X0_I0_D0_PACK+26 +.set vgprValuA_X3_I0_D2, vgprValuA_X0_I0_D0_PACK+28 +.set vgprValuA_X3_I0_D3, vgprValuA_X0_I0_D0_PACK+30 +.set vgprValuB_X0_I0_BASE, 56 +.set vgprValuB_X0_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X1_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X2_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X3_I0, vgprValuB_X0_I0_BASE+0 +.set vgprValuB_X0_I0_D0_PACK, 72 +.set vgprValuB_X0_I0_D0, vgprValuB_X0_I0_D0_PACK+0 +.set vgprValuB_X0_I0_D1, vgprValuB_X0_I0_D0_PACK+4 +.set vgprValuB_X0_I0_D2, vgprValuB_X0_I0_D0_PACK+8 +.set vgprValuB_X0_I0_D3, vgprValuB_X0_I0_D0_PACK+12 +.set vgprValuB_X1_I0_D0, vgprValuB_X0_I0_D0_PACK+16 +.set vgprValuB_X1_I0_D1, vgprValuB_X0_I0_D0_PACK+20 +.set vgprValuB_X1_I0_D2, vgprValuB_X0_I0_D0_PACK+24 +.set vgprValuB_X1_I0_D3, vgprValuB_X0_I0_D0_PACK+28 +.set vgprValuB_X2_I0_D0, vgprValuB_X0_I0_D0_PACK+32 +.set vgprValuB_X2_I0_D1, vgprValuB_X0_I0_D0_PACK+36 +.set vgprValuB_X2_I0_D2, vgprValuB_X0_I0_D0_PACK+40 +.set vgprValuB_X2_I0_D3, vgprValuB_X0_I0_D0_PACK+44 +.set vgprValuB_X3_I0_D0, vgprValuB_X0_I0_D0_PACK+48 +.set vgprValuB_X3_I0_D1, vgprValuB_X0_I0_D0_PACK+52 +.set vgprValuB_X3_I0_D2, vgprValuB_X0_I0_D0_PACK+56 +.set vgprValuB_X3_I0_D3, vgprValuB_X0_I0_D0_PACK+60 + +/* Tail: local read reset offsets a */ + +/* Tail: local read reset offsets b */ + +/* Tail: local read init pointers a */ + +/* localReadInitPointers */ + +/* Tail: local read init pointers b */ + +/* localReadInitPointers */ + +/* tail loop: macs */ +.align 16 +label_TailLoopBeginL: + +/* local read a */ +ds_read_b64 v[vgprValuA_X0_I0_D0+0:vgprValuA_X0_I0_D0+0+1], v[vgprLocalReadAddrA+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D1+0:vgprValuA_X0_I0_D1+0+1], v[vgprLocalReadAddrA+0] offset:256 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D2+0:vgprValuA_X0_I0_D2+0+1], v[vgprLocalReadAddrA+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b64 v[vgprValuA_X0_I0_D3+0:vgprValuA_X0_I0_D3+0+1], v[vgprLocalReadAddrA+0] offset:768 // L -> Reg lro=0 swapByteOffset=0 ti=128 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 + +/* local read b */ +ds_read_b128 v[vgprValuB_X0_I0_D0+0:vgprValuB_X0_I0_D0+0+3], v[vgprLocalReadAddrB+0] offset:0 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=0 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D1+0:vgprValuB_X0_I0_D1+0+3], v[vgprLocalReadAddrB+0] offset:512 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=1 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D2+0:vgprValuB_X0_I0_D2+0+3], v[vgprLocalReadAddrB+0] offset:1024 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=2 oIdx=0 buffer=0 iui=0 sync LDS0 +ds_read_b128 v[vgprValuB_X0_I0_D3+0:vgprValuB_X0_I0_D3+0+3], v[vgprLocalReadAddrB+0] offset:1536 // L -> Reg lro=0 swapByteOffset=0 ti=256 vIdx=0 eIdx=0 rIdx=3 oIdx=0 buffer=0 iui=0 sync LDS0 + +/* local read inc a */ +s_mov_b32 s83, 4096 // inc +v_add_co_u32 v[vgprLocalReadAddrA+0], vcc, s83, v[vgprLocalReadAddrA+0] // lrA += 4096 ((MT+PAD)*bpeDS) + +/* local read inc b */ +s_mov_b32 s83, 8192 // inc +v_add_co_u32 v[vgprLocalReadAddrB+0], vcc, s83, v[vgprLocalReadAddrB+0] // lrB += 8192 ((MT+PAD)*bpeDS) +s_waitcnt lgkmcnt(0) // 4wait for local read +v_perm_b32 v[vgprValuA_X0_I0+0], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+1], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+2], v[vgprValuA_X0_I0_D1+0], v[vgprValuA_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+3], v[vgprValuA_X0_I0_D3+0], v[vgprValuA_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+4], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+5], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuA_X0_I0+6], v[vgprValuA_X0_I0_D1+1], v[vgprValuA_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuA_X0_I0+7], v[vgprValuA_X0_I0_D3+1], v[vgprValuA_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+0], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+1], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+2], v[vgprValuB_X0_I0_D1+0], v[vgprValuB_X0_I0_D0+0], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+3], v[vgprValuB_X0_I0_D3+0], v[vgprValuB_X0_I0_D2+0], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+4], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+5], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+6], v[vgprValuB_X0_I0_D1+1], v[vgprValuB_X0_I0_D0+1], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+7], v[vgprValuB_X0_I0_D3+1], v[vgprValuB_X0_I0_D2+1], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+8], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+9], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+10], v[vgprValuB_X0_I0_D1+2], v[vgprValuB_X0_I0_D0+2], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+11], v[vgprValuB_X0_I0_D3+2], v[vgprValuB_X0_I0_D2+2], s[sgprPackKForV1] // select K=23 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+12], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV0] // select K=01 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+13], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV0] // select K=23 for vector=0 +v_perm_b32 v[vgprValuB_X0_I0+14], v[vgprValuB_X0_I0_D1+3], v[vgprValuB_X0_I0_D0+3], s[sgprPackKForV1] // select K=01 for vector=1 +v_perm_b32 v[vgprValuB_X0_I0+15], v[vgprValuB_X0_I0_D3+3], v[vgprValuB_X0_I0_D2+3], s[sgprPackKForV1] // select K=23 for vector=1 +v_and_b32 v136, 63, v[vgprSerial] // v136 = v[vgprSerial] % 64 +v_lshrrev_b32 v136, 4, v136 // 136 = 136 / 16 +v_lshlrev_b32 v136, 2, v136 // v136 = v136 * 4 +v_cmp_ge_i32 s[84:85], v136, s[sgprLoopCounterL] // check K index >= Size L +v_cndmask_b32 v[vgprValuA_X0_I0+0+0+0+0], v[vgprValuA_X0_I0+0+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+2+0+0+0], v[vgprValuA_X0_I0+2+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+4+0+0+0], v[vgprValuA_X0_I0+4+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+6+0+0+0], v[vgprValuA_X0_I0+6+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuA_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+0+0+0+0], v[vgprValuB_X0_I0+0+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+2+0+0+0], v[vgprValuB_X0_I0+2+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+4+0+0+0], v[vgprValuB_X0_I0+4+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+6+0+0+0], v[vgprValuB_X0_I0+6+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+8+0+0+0], v[vgprValuB_X0_I0+8+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+10+0+0+0], v[vgprValuB_X0_I0+10+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+12+0+0+0], v[vgprValuB_X0_I0+12+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+14+0+0+0], v[vgprValuB_X0_I0+14+0+0+0], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+0+0+0+1], v[vgprValuB_X0_I0+0+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+2+0+0+1], v[vgprValuB_X0_I0+2+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+4+0+0+1], v[vgprValuB_X0_I0+4+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+6+0+0+1], v[vgprValuB_X0_I0+6+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+8+0+0+1], v[vgprValuB_X0_I0+8+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+10+0+0+1], v[vgprValuB_X0_I0+10+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+12+0+0+1], v[vgprValuB_X0_I0+12+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_cndmask_b32 v[vgprValuB_X0_I0+14+0+0+1], v[vgprValuB_X0_I0+14+0+0+1], 0, s[84:85] // set 0 if K_idx >= sizeL +v_sub_u32 v137, s[sgprLoopCounterL], v136 // get distance between size and k index +v_cmp_lt_i32 s[84:85], v137, 4 // set partial 0 if distance less than input per thread +s_and_b32 s83, s[sgprSizeL], 7 // if summation is multiple of 8, skip masking +s_cmp_eq_u32 s83, 0 +s_cbranch_scc1 label_TailLoop_SkipZeroOutMask_DZOUDPYJU2HHRCOQ // skip mask +s_and_b32 s83, s[sgprLoopCounterL], 3 // get inputs for edge thread +s_sub_u32 s83, 4, s83 // use shift to fill 0 for outside element +s_lshl_b32 s83, s83, 4 // use shift to fill 0 for outside element +v_lshlrev_b64 v[138:139], s83, v[vgprValuA_X0_I0+0+0+0+0:vgprValuA_X0_I0+0+0+0+0+1] +v_cndmask_b32 v[vgprValuA_X0_I0+0+0+0+0], v[vgprValuA_X0_I0+0+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuA_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuA_X0_I0+2+0+0+0:vgprValuA_X0_I0+2+0+0+0+1] +v_cndmask_b32 v[vgprValuA_X0_I0+2+0+0+0], v[vgprValuA_X0_I0+2+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuA_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuA_X0_I0+4+0+0+0:vgprValuA_X0_I0+4+0+0+0+1] +v_cndmask_b32 v[vgprValuA_X0_I0+4+0+0+0], v[vgprValuA_X0_I0+4+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuA_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuA_X0_I0+6+0+0+0:vgprValuA_X0_I0+6+0+0+0+1] +v_cndmask_b32 v[vgprValuA_X0_I0+6+0+0+0], v[vgprValuA_X0_I0+6+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuA_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+0+0+0+0:vgprValuB_X0_I0+0+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+0+0+0+0], v[vgprValuB_X0_I0+0+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+0+0+0+1], v[vgprValuB_X0_I0+0+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+2+0+0+0:vgprValuB_X0_I0+2+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+2+0+0+0], v[vgprValuB_X0_I0+2+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+2+0+0+1], v[vgprValuB_X0_I0+2+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+4+0+0+0:vgprValuB_X0_I0+4+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+4+0+0+0], v[vgprValuB_X0_I0+4+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+4+0+0+1], v[vgprValuB_X0_I0+4+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+6+0+0+0:vgprValuB_X0_I0+6+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+6+0+0+0], v[vgprValuB_X0_I0+6+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+6+0+0+1], v[vgprValuB_X0_I0+6+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+8+0+0+0:vgprValuB_X0_I0+8+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+8+0+0+0], v[vgprValuB_X0_I0+8+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+8+0+0+1], v[vgprValuB_X0_I0+8+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+10+0+0+0:vgprValuB_X0_I0+10+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+10+0+0+0], v[vgprValuB_X0_I0+10+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+10+0+0+1], v[vgprValuB_X0_I0+10+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+12+0+0+0:vgprValuB_X0_I0+12+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+12+0+0+0], v[vgprValuB_X0_I0+12+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+12+0+0+1], v[vgprValuB_X0_I0+12+0+0+1], v139, s[84:85] +v_lshlrev_b64 v[138:139], s83, v[vgprValuB_X0_I0+14+0+0+0:vgprValuB_X0_I0+14+0+0+0+1] +v_cndmask_b32 v[vgprValuB_X0_I0+14+0+0+0], v[vgprValuB_X0_I0+14+0+0+0], v138, s[84:85] +v_cndmask_b32 v[vgprValuB_X0_I0+14+0+0+1], v[vgprValuB_X0_I0+14+0+0+1], v139, s[84:85] +label_TailLoop_SkipZeroOutMask_DZOUDPYJU2HHRCOQ: +s_nop 1 +v_mfma_f32_16x16x16_f16 acc[0:3], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[0:3] // left value = acc[0+0:3+0] +v_mfma_f32_16x16x16_f16 acc[4:7], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[4:7] // left value = acc[4+0:7+0] +v_mfma_f32_16x16x16_f16 acc[8:11], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[8:11] // left value = acc[8+0:11+0] +v_mfma_f32_16x16x16_f16 acc[12:15], v[vgprValuB_X0_I0+0+0+0:vgprValuB_X0_I0+0+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[12:15] // left value = acc[12+0:15+0] +v_mfma_f32_16x16x16_f16 acc[16:19], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[16:19] // left value = acc[16+0:19+0] +v_mfma_f32_16x16x16_f16 acc[20:23], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[20:23] // left value = acc[20+0:23+0] +v_mfma_f32_16x16x16_f16 acc[24:27], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[24:27] // left value = acc[24+0:27+0] +v_mfma_f32_16x16x16_f16 acc[28:31], v[vgprValuB_X0_I0+2+0+0:vgprValuB_X0_I0+2+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[28:31] // left value = acc[28+0:31+0] +v_mfma_f32_16x16x16_f16 acc[32:35], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[32:35] // left value = acc[32+0:35+0] +v_mfma_f32_16x16x16_f16 acc[36:39], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[36:39] // left value = acc[36+0:39+0] +v_mfma_f32_16x16x16_f16 acc[40:43], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[40:43] // left value = acc[40+0:43+0] +v_mfma_f32_16x16x16_f16 acc[44:47], v[vgprValuB_X0_I0+4+0+0:vgprValuB_X0_I0+4+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[44:47] // left value = acc[44+0:47+0] +v_mfma_f32_16x16x16_f16 acc[48:51], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[48:51] // left value = acc[48+0:51+0] +v_mfma_f32_16x16x16_f16 acc[52:55], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[52:55] // left value = acc[52+0:55+0] +v_mfma_f32_16x16x16_f16 acc[56:59], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[56:59] // left value = acc[56+0:59+0] +v_mfma_f32_16x16x16_f16 acc[60:63], v[vgprValuB_X0_I0+6+0+0:vgprValuB_X0_I0+6+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[60:63] // left value = acc[60+0:63+0] +v_mfma_f32_16x16x16_f16 acc[64:67], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[64:67] // left value = acc[64+0:67+0] +v_mfma_f32_16x16x16_f16 acc[68:71], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[68:71] // left value = acc[68+0:71+0] +v_mfma_f32_16x16x16_f16 acc[72:75], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[72:75] // left value = acc[72+0:75+0] +v_mfma_f32_16x16x16_f16 acc[76:79], v[vgprValuB_X0_I0+8+0+0:vgprValuB_X0_I0+8+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[76:79] // left value = acc[76+0:79+0] +v_mfma_f32_16x16x16_f16 acc[80:83], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[80:83] // left value = acc[80+0:83+0] +v_mfma_f32_16x16x16_f16 acc[84:87], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[84:87] // left value = acc[84+0:87+0] +v_mfma_f32_16x16x16_f16 acc[88:91], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[88:91] // left value = acc[88+0:91+0] +v_mfma_f32_16x16x16_f16 acc[92:95], v[vgprValuB_X0_I0+10+0+0:vgprValuB_X0_I0+10+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[92:95] // left value = acc[92+0:95+0] +v_mfma_f32_16x16x16_f16 acc[96:99], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[96:99] // left value = acc[96+0:99+0] +v_mfma_f32_16x16x16_f16 acc[100:103], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[100:103] // left value = acc[100+0:103+0] +v_mfma_f32_16x16x16_f16 acc[104:107], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[104:107] // left value = acc[104+0:107+0] +v_mfma_f32_16x16x16_f16 acc[108:111], v[vgprValuB_X0_I0+12+0+0:vgprValuB_X0_I0+12+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[108:111] // left value = acc[108+0:111+0] +v_mfma_f32_16x16x16_f16 acc[112:115], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+0+0+0:vgprValuA_X0_I0+0+0+0+1], acc[112:115] // left value = acc[112+0:115+0] +v_mfma_f32_16x16x16_f16 acc[116:119], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+2+0+0:vgprValuA_X0_I0+2+0+0+1], acc[116:119] // left value = acc[116+0:119+0] +v_mfma_f32_16x16x16_f16 acc[120:123], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+4+0+0:vgprValuA_X0_I0+4+0+0+1], acc[120:123] // left value = acc[120+0:123+0] +v_mfma_f32_16x16x16_f16 acc[124:127], v[vgprValuB_X0_I0+14+0+0:vgprValuB_X0_I0+14+0+0+1], v[vgprValuA_X0_I0+6+0+0:vgprValuA_X0_I0+6+0+0+1], acc[124:127] // left value = acc[124+0:127+0] + +/* closeLoop loopL finalLoop=1 tailLoop=1 */ +s_sub_i32 s[sgprLoopCounterL], s[sgprLoopCounterL], 0x10 // dec counterL (tailLoop) +s_add_u32 s[sgprOrigLoopCounter], s[sgprOrigLoopCounter], 0x10 // inc counterL +s_cmp_le_i32 s[sgprLoopCounterL], 0x0 // counterL<=0 +s_cbranch_scc0 label_TailLoopBeginL // restart LoopL +label_TailLoopEndL: +s_mov_b32 s83, 256 // tailloop lds offset +s_mul_i32 s83, s[sgprOrigLoopCounter], s83 // scale by mul +v_sub_u32 v[vgprLocalReadAddrA], v[vgprLocalReadAddrA], s83 // remove lro damage +s_mov_b32 s83, 512 // tailloop lds offset +s_mul_i32 s83, s[sgprOrigLoopCounter], s83 // scale by mul +v_sub_u32 v[vgprLocalReadAddrB], v[vgprLocalReadAddrB], s83 // remove lro damage +label_SkipTailLoopL: +.set vgprValuA_X0_I0_BASE, UNDEF +.set vgprValuA_X0_I0, UNDEF +.set vgprValuA_X1_I0, UNDEF +.set vgprValuA_X2_I0, UNDEF +.set vgprValuA_X3_I0, UNDEF +.set vgprValuA_X0_I0_D0_PACK, UNDEF +.set vgprValuA_X0_I0_D0, UNDEF +.set vgprValuA_X0_I0_D1, UNDEF +.set vgprValuA_X0_I0_D2, UNDEF +.set vgprValuA_X0_I0_D3, UNDEF +.set vgprValuA_X1_I0_D0, UNDEF +.set vgprValuA_X1_I0_D1, UNDEF +.set vgprValuA_X1_I0_D2, UNDEF +.set vgprValuA_X1_I0_D3, UNDEF +.set vgprValuA_X2_I0_D0, UNDEF +.set vgprValuA_X2_I0_D1, UNDEF +.set vgprValuA_X2_I0_D2, UNDEF +.set vgprValuA_X2_I0_D3, UNDEF +.set vgprValuA_X3_I0_D0, UNDEF +.set vgprValuA_X3_I0_D1, UNDEF +.set vgprValuA_X3_I0_D2, UNDEF +.set vgprValuA_X3_I0_D3, UNDEF +.set vgprValuB_X0_I0_BASE, UNDEF +.set vgprValuB_X0_I0, UNDEF +.set vgprValuB_X1_I0, UNDEF +.set vgprValuB_X2_I0, UNDEF +.set vgprValuB_X3_I0, UNDEF +.set vgprValuB_X0_I0_D0_PACK, UNDEF +.set vgprValuB_X0_I0_D0, UNDEF +.set vgprValuB_X0_I0_D1, UNDEF +.set vgprValuB_X0_I0_D2, UNDEF +.set vgprValuB_X0_I0_D3, UNDEF +.set vgprValuB_X1_I0_D0, UNDEF +.set vgprValuB_X1_I0_D1, UNDEF +.set vgprValuB_X1_I0_D2, UNDEF +.set vgprValuB_X1_I0_D3, UNDEF +.set vgprValuB_X2_I0_D0, UNDEF +.set vgprValuB_X2_I0_D1, UNDEF +.set vgprValuB_X2_I0_D2, UNDEF +.set vgprValuB_X2_I0_D3, UNDEF +.set vgprValuB_X3_I0_D0, UNDEF +.set vgprValuB_X3_I0_D1, UNDEF +.set vgprValuB_X3_I0_D2, UNDEF +.set vgprValuB_X3_I0_D3, UNDEF + +/* Tail: add MISC Vgpr [0...16) to pool */ +label_Summation_End_QWMA7J3AUDGL0X23: +.set sgprLoopCounterL, UNDEF +.set sgprOrigLoopCounter, UNDEF +.set sgprShadowLimitA, UNDEF +.set sgprSrdA, UNDEF +.set sgprSrdB, UNDEF +.set sgprShadowLimitB, UNDEF +.set sgprStaggerUIter, UNDEF +.set sgprWrapUA, UNDEF +.set sgprWrapUB, UNDEF +.set sgprGlobalReadIncsA, UNDEF +.set sgprGlobalReadIncsB, UNDEF +/* load store sgprs */ + +/* Mapping of Acc register -> C Vgpr register */ + +/* shift vector components d0 */ +v_mov_b32 v3, s[sgprWorkGroup0] +v_mul_i32_i24 v3, -0x80, v3 // wg*MT +v_add_co_u32 v3, vcc, s[sgprSizesFree+0], v3 // wgMT = Size - wg*MT +v_mov_b32 v4, 0x80 // MT +v_cmp_lt_u32 s[8:9], v3, v4 // wgMT < MT +v_cndmask_b32 v3, v4, v3, s[8:9] // wgMT = (wgMT < MT) ? wgMT : MT +v_lshrrev_b32 v5, 6, v[vgprSerial] // 5 = Serial / 64 +v_and_b32 v5, 1, v5 // v5 = v5 % 2 +v_lshrrev_b32 v6, 6, v3 // 6 = 3 / 64 +v_and_b32 v6, 1, v6 // v6 = v6 % 2 +v_cmp_eq_u32 s[8:9], v6, v5 // wave_id == block_belong_to_wave? +v_cndmask_b32 v3, v4, v3, s[8:9] // wgMT = (wgMT < MT) ? wgMT : MT + +/* mbReg: which mb block need to shift, mb(matrixInstCoal(16) * VectorWidth(4)) */ +v_lshrrev_b32 v4, 6, v3 // 4 = 3 / 64 +v_lshlrev_b32 v6, 0, v5 // v6 = v5 * 1 +v_sub_u32 v4, v4, v6 + +/* gbReg: glvw block id */ +v_lshrrev_b32 v6, 3, v3 // 6 = 3 / 8 + +/* tgbReg: glvw block id */ +v_lshrrev_b32 v7, 0, v[vgprSerial] // 7 = Serial / 1 +v_and_b32 v7, 15, v7 // v7 = v7 % 16 +v_lshlrev_b32 v7, 2, v7 // v7 = v7 * 4 +v_lshrrev_b32 v7, 3, v7 // 7 = 7 / 8 +v_lshlrev_b32 v5, 3, v5 // v5 = v5 * 8 +v_add_co_u32 v7, vcc, v5, v7 // tgbReg = (tid_coal * continOut) / GLVW +v_sub_u32 v6, v6, v7 + +/* vwReg: glvw in which vw block? */ +v_and_b32 v5, 3, v3 // permute register between threads +v_lshrrev_b32 v5, 3, v5 // permute register between threads + +/* rReg : reminder of M_size % GlobalReadVectorWidth */ +v_and_b32 v7, 7, v3 // v7 = v3 % 8 +v_cmp_eq_u32 vcc, v7, 0x1 // wgMT%VW == 1 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW1 // branch to shift d0 r=1 +v_cmp_eq_u32 vcc, v7, 0x2 // wgMT%VW == 2 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW2 // branch to shift d0 r=2 +v_cmp_eq_u32 vcc, v7, 0x3 // wgMT%VW == 3 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW3 // branch to shift d0 r=3 +v_cmp_eq_u32 vcc, v7, 0x4 // wgMT%VW == 4 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW4 // branch to shift d0 r=4 +v_cmp_eq_u32 vcc, v7, 0x5 // wgMT%VW == 5 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW5 // branch to shift d0 r=5 +v_cmp_eq_u32 vcc, v7, 0x6 // wgMT%VW == 6 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW6 // branch to shift d0 r=6 +v_cmp_eq_u32 vcc, v7, 0x7 // wgMT%VW == 7 +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW7 // branch to shift d0 r=7 + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + +/******************************************/ +/* shift d0 r=1 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW1: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r1 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW1_BM0 + +/******************************************/ +/* shift d0 r=2 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW2: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r2 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW2_BM0 + +/******************************************/ +/* shift d0 r=3 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW3: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r3 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW3_BM0 + +/******************************************/ +/* shift d0 r=4 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW4: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r4 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW4_BM0 + +/******************************************/ +/* shift d0 r=5 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW5: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r5 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW5_BM0 + +/******************************************/ +/* shift d0 r=6 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW6: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r6 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW6_BM0 + +/******************************************/ +/* shift d0 r=7 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW7: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d0 r7 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW7_BM0 + +/******************************************/ +/* shift d0 r=1 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW1_BM0: /// r1 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r1 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW1_BM0_VW0 + +/******************************************/ +/* shift d0 r=2 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW2_BM0: /// r2 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r2 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW2_BM0_VW0 + +/******************************************/ +/* shift d0 r=3 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW3_BM0: /// r3 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r3 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW3_BM0_VW0 + +/******************************************/ +/* shift d0 r=4 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW4_BM0: /// r4 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r4 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW4_BM0_VW0 + +/******************************************/ +/* shift d0 r=5 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW5_BM0: /// r5 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r5 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW5_BM0_VW0 + +/******************************************/ +/* shift d0 r=6 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW6_BM0: /// r6 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r6 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW6_BM0_VW0 + +/******************************************/ +/* shift d0 r=7 mb=0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW7_BM0: /// r7 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d0 r7 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents0_GLVW7_BM0_VW0 + +/******************************************/ +/* shift d0 r=1 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW1_BM0_VW0: /// r1 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc12 // glvw 1 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_read_b32 v7, acc28 // glvw 1 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_read_b32 v7, acc44 // glvw 1 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_read_b32 v7, acc60 // glvw 1 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_read_b32 v7, acc76 // glvw 1 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_read_b32 v7, acc92 // glvw 1 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_read_b32 v7, acc108 // glvw 1 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_read_b32 v7, acc124 // glvw 1 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_read_b32 v7, acc13 // glvw 1 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_read_b32 v7, acc29 // glvw 1 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_read_b32 v7, acc45 // glvw 1 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_read_b32 v7, acc61 // glvw 1 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_read_b32 v7, acc77 // glvw 1 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_read_b32 v7, acc93 // glvw 1 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_read_b32 v7, acc109 // glvw 1 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_read_b32 v7, acc125 // glvw 1 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_read_b32 v7, acc14 // glvw 1 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_read_b32 v7, acc30 // glvw 1 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_read_b32 v7, acc46 // glvw 1 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_read_b32 v7, acc62 // glvw 1 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_read_b32 v7, acc78 // glvw 1 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_read_b32 v7, acc94 // glvw 1 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_read_b32 v7, acc110 // glvw 1 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_read_b32 v7, acc126 // glvw 1 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_read_b32 v7, acc15 // glvw 1 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_read_b32 v7, acc31 // glvw 1 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_read_b32 v7, acc47 // glvw 1 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_read_b32 v7, acc63 // glvw 1 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_read_b32 v7, acc79 // glvw 1 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_read_b32 v7, acc95 // glvw 1 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_read_b32 v7, acc111 // glvw 1 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_read_b32 v7, acc127 // glvw 1 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=2 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW2_BM0_VW0: /// r2 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc8 // glvw 2 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc12 // glvw 2 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_read_b32 v7, acc24 // glvw 2 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc28 // glvw 2 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_read_b32 v7, acc40 // glvw 2 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc44 // glvw 2 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_read_b32 v7, acc56 // glvw 2 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc60 // glvw 2 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_read_b32 v7, acc72 // glvw 2 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc76 // glvw 2 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_read_b32 v7, acc88 // glvw 2 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc92 // glvw 2 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_read_b32 v7, acc104 // glvw 2 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc108 // glvw 2 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_read_b32 v7, acc120 // glvw 2 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc124 // glvw 2 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_read_b32 v7, acc9 // glvw 2 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc13 // glvw 2 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_read_b32 v7, acc25 // glvw 2 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc29 // glvw 2 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_read_b32 v7, acc41 // glvw 2 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc45 // glvw 2 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_read_b32 v7, acc57 // glvw 2 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc61 // glvw 2 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_read_b32 v7, acc73 // glvw 2 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc77 // glvw 2 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_read_b32 v7, acc89 // glvw 2 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc93 // glvw 2 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_read_b32 v7, acc105 // glvw 2 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc109 // glvw 2 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_read_b32 v7, acc121 // glvw 2 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc125 // glvw 2 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_read_b32 v7, acc10 // glvw 2 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc14 // glvw 2 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_read_b32 v7, acc26 // glvw 2 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc30 // glvw 2 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_read_b32 v7, acc42 // glvw 2 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc46 // glvw 2 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_read_b32 v7, acc58 // glvw 2 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc62 // glvw 2 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_read_b32 v7, acc74 // glvw 2 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc78 // glvw 2 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_read_b32 v7, acc90 // glvw 2 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc94 // glvw 2 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_read_b32 v7, acc106 // glvw 2 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc110 // glvw 2 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_read_b32 v7, acc122 // glvw 2 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc126 // glvw 2 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_read_b32 v7, acc11 // glvw 2 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc15 // glvw 2 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_read_b32 v7, acc27 // glvw 2 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc31 // glvw 2 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_read_b32 v7, acc43 // glvw 2 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc47 // glvw 2 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_read_b32 v7, acc59 // glvw 2 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc63 // glvw 2 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_read_b32 v7, acc75 // glvw 2 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc79 // glvw 2 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_read_b32 v7, acc91 // glvw 2 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc95 // glvw 2 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_read_b32 v7, acc107 // glvw 2 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc111 // glvw 2 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_read_b32 v7, acc123 // glvw 2 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc127 // glvw 2 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=3 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW3_BM0_VW0: /// r3 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc4 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc8 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc12 // glvw 3 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_write_b32 acc8, v9 +v_accvgpr_read_b32 v7, acc20 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc24 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc28 // glvw 3 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc24, v9 +v_accvgpr_read_b32 v7, acc36 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc40 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc44 // glvw 3 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_read_b32 v7, acc52 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc56 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc60 // glvw 3 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_write_b32 acc56, v9 +v_accvgpr_read_b32 v7, acc68 // glvw 3 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc72 // glvw 3 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v9, acc76 // glvw 3 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_write_b32 acc72, v9 +v_accvgpr_read_b32 v7, acc84 // glvw 3 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc88 // glvw 3 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v9, acc92 // glvw 3 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_write_b32 acc88, v9 +v_accvgpr_read_b32 v7, acc100 // glvw 3 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc104 // glvw 3 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v9, acc108 // glvw 3 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_write_b32 acc104, v9 +v_accvgpr_read_b32 v7, acc116 // glvw 3 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc120 // glvw 3 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v9, acc124 // glvw 3 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_write_b32 acc120, v9 +v_accvgpr_read_b32 v7, acc5 // glvw 3 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc9 // glvw 3 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v9, acc13 // glvw 3 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_write_b32 acc9, v9 +v_accvgpr_read_b32 v7, acc21 // glvw 3 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc25 // glvw 3 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v9, acc29 // glvw 3 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc25, v9 +v_accvgpr_read_b32 v7, acc37 // glvw 3 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc41 // glvw 3 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v9, acc45 // glvw 3 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_read_b32 v7, acc53 // glvw 3 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc57 // glvw 3 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v9, acc61 // glvw 3 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_write_b32 acc57, v9 +v_accvgpr_read_b32 v7, acc69 // glvw 3 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc73 // glvw 3 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v9, acc77 // glvw 3 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_write_b32 acc73, v9 +v_accvgpr_read_b32 v7, acc85 // glvw 3 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc89 // glvw 3 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v9, acc93 // glvw 3 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_write_b32 acc89, v9 +v_accvgpr_read_b32 v7, acc101 // glvw 3 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc105 // glvw 3 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v9, acc109 // glvw 3 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_write_b32 acc105, v9 +v_accvgpr_read_b32 v7, acc117 // glvw 3 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc121 // glvw 3 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v9, acc125 // glvw 3 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_write_b32 acc121, v9 +v_accvgpr_read_b32 v7, acc6 // glvw 3 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc10 // glvw 3 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v9, acc14 // glvw 3 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_write_b32 acc10, v9 +v_accvgpr_read_b32 v7, acc22 // glvw 3 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc26 // glvw 3 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v9, acc30 // glvw 3 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc26, v9 +v_accvgpr_read_b32 v7, acc38 // glvw 3 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc42 // glvw 3 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v9, acc46 // glvw 3 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_read_b32 v7, acc54 // glvw 3 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc58 // glvw 3 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v9, acc62 // glvw 3 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_write_b32 acc58, v9 +v_accvgpr_read_b32 v7, acc70 // glvw 3 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc74 // glvw 3 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v9, acc78 // glvw 3 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_write_b32 acc74, v9 +v_accvgpr_read_b32 v7, acc86 // glvw 3 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc90 // glvw 3 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v9, acc94 // glvw 3 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_write_b32 acc90, v9 +v_accvgpr_read_b32 v7, acc102 // glvw 3 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc106 // glvw 3 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v9, acc110 // glvw 3 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_write_b32 acc106, v9 +v_accvgpr_read_b32 v7, acc118 // glvw 3 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc122 // glvw 3 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v9, acc126 // glvw 3 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_write_b32 acc122, v9 +v_accvgpr_read_b32 v7, acc7 // glvw 3 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc11 // glvw 3 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v9, acc15 // glvw 3 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_write_b32 acc11, v9 +v_accvgpr_read_b32 v7, acc23 // glvw 3 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc27 // glvw 3 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v9, acc31 // glvw 3 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc27, v9 +v_accvgpr_read_b32 v7, acc39 // glvw 3 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc43 // glvw 3 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v9, acc47 // glvw 3 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_read_b32 v7, acc55 // glvw 3 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc59 // glvw 3 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v9, acc63 // glvw 3 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_write_b32 acc59, v9 +v_accvgpr_read_b32 v7, acc71 // glvw 3 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc75 // glvw 3 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v9, acc79 // glvw 3 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_write_b32 acc75, v9 +v_accvgpr_read_b32 v7, acc87 // glvw 3 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc91 // glvw 3 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v9, acc95 // glvw 3 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_write_b32 acc91, v9 +v_accvgpr_read_b32 v7, acc103 // glvw 3 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc107 // glvw 3 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v9, acc111 // glvw 3 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_write_b32 acc107, v9 +v_accvgpr_read_b32 v7, acc119 // glvw 3 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc123 // glvw 3 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v9, acc127 // glvw 3 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +v_accvgpr_write_b32 acc123, v9 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=4 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW4_BM0_VW0: /// r4 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc0 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc4 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc8 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc12 // glvw 4 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_write_b32 acc8, v9 +v_accvgpr_write_b32 acc12, v10 +v_accvgpr_read_b32 v7, acc16 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc20 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc24 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc28 // glvw 4 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc24, v9 +v_accvgpr_write_b32 acc28, v10 +v_accvgpr_read_b32 v7, acc32 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc36 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc40 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc44 // glvw 4 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc44, v10 +v_accvgpr_read_b32 v7, acc48 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc52 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc56 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc60 // glvw 4 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_write_b32 acc56, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_read_b32 v7, acc64 // glvw 4 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc68 // glvw 4 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v9, acc72 // glvw 4 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v10, acc76 // glvw 4 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_write_b32 acc72, v9 +v_accvgpr_write_b32 acc76, v10 +v_accvgpr_read_b32 v7, acc80 // glvw 4 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc84 // glvw 4 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v9, acc88 // glvw 4 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v10, acc92 // glvw 4 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_write_b32 acc88, v9 +v_accvgpr_write_b32 acc92, v10 +v_accvgpr_read_b32 v7, acc96 // glvw 4 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc100 // glvw 4 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v9, acc104 // glvw 4 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v10, acc108 // glvw 4 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_write_b32 acc104, v9 +v_accvgpr_write_b32 acc108, v10 +v_accvgpr_read_b32 v7, acc112 // glvw 4 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc116 // glvw 4 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v9, acc120 // glvw 4 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v10, acc124 // glvw 4 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_write_b32 acc120, v9 +v_accvgpr_write_b32 acc124, v10 +v_accvgpr_read_b32 v7, acc1 // glvw 4 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc5 // glvw 4 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v9, acc9 // glvw 4 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v10, acc13 // glvw 4 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_write_b32 acc9, v9 +v_accvgpr_write_b32 acc13, v10 +v_accvgpr_read_b32 v7, acc17 // glvw 4 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc21 // glvw 4 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v9, acc25 // glvw 4 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v10, acc29 // glvw 4 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc25, v9 +v_accvgpr_write_b32 acc29, v10 +v_accvgpr_read_b32 v7, acc33 // glvw 4 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc37 // glvw 4 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v9, acc41 // glvw 4 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v10, acc45 // glvw 4 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc45, v10 +v_accvgpr_read_b32 v7, acc49 // glvw 4 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc53 // glvw 4 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v9, acc57 // glvw 4 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v10, acc61 // glvw 4 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_write_b32 acc57, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_read_b32 v7, acc65 // glvw 4 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc69 // glvw 4 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v9, acc73 // glvw 4 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v10, acc77 // glvw 4 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_write_b32 acc73, v9 +v_accvgpr_write_b32 acc77, v10 +v_accvgpr_read_b32 v7, acc81 // glvw 4 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc85 // glvw 4 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v9, acc89 // glvw 4 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v10, acc93 // glvw 4 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_write_b32 acc89, v9 +v_accvgpr_write_b32 acc93, v10 +v_accvgpr_read_b32 v7, acc97 // glvw 4 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc101 // glvw 4 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v9, acc105 // glvw 4 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v10, acc109 // glvw 4 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_write_b32 acc105, v9 +v_accvgpr_write_b32 acc109, v10 +v_accvgpr_read_b32 v7, acc113 // glvw 4 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc117 // glvw 4 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v9, acc121 // glvw 4 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v10, acc125 // glvw 4 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_write_b32 acc121, v9 +v_accvgpr_write_b32 acc125, v10 +v_accvgpr_read_b32 v7, acc2 // glvw 4 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc6 // glvw 4 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v9, acc10 // glvw 4 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v10, acc14 // glvw 4 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_write_b32 acc10, v9 +v_accvgpr_write_b32 acc14, v10 +v_accvgpr_read_b32 v7, acc18 // glvw 4 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc22 // glvw 4 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v9, acc26 // glvw 4 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v10, acc30 // glvw 4 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc26, v9 +v_accvgpr_write_b32 acc30, v10 +v_accvgpr_read_b32 v7, acc34 // glvw 4 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc38 // glvw 4 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v9, acc42 // glvw 4 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v10, acc46 // glvw 4 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc46, v10 +v_accvgpr_read_b32 v7, acc50 // glvw 4 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc54 // glvw 4 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v9, acc58 // glvw 4 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v10, acc62 // glvw 4 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_write_b32 acc58, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_read_b32 v7, acc66 // glvw 4 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc70 // glvw 4 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v9, acc74 // glvw 4 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v10, acc78 // glvw 4 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_write_b32 acc74, v9 +v_accvgpr_write_b32 acc78, v10 +v_accvgpr_read_b32 v7, acc82 // glvw 4 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc86 // glvw 4 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v9, acc90 // glvw 4 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v10, acc94 // glvw 4 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_write_b32 acc90, v9 +v_accvgpr_write_b32 acc94, v10 +v_accvgpr_read_b32 v7, acc98 // glvw 4 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc102 // glvw 4 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v9, acc106 // glvw 4 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v10, acc110 // glvw 4 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_write_b32 acc106, v9 +v_accvgpr_write_b32 acc110, v10 +v_accvgpr_read_b32 v7, acc114 // glvw 4 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc118 // glvw 4 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v9, acc122 // glvw 4 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v10, acc126 // glvw 4 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_write_b32 acc122, v9 +v_accvgpr_write_b32 acc126, v10 +v_accvgpr_read_b32 v7, acc3 // glvw 4 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc7 // glvw 4 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v9, acc11 // glvw 4 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v10, acc15 // glvw 4 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_write_b32 acc11, v9 +v_accvgpr_write_b32 acc15, v10 +v_accvgpr_read_b32 v7, acc19 // glvw 4 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc23 // glvw 4 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v9, acc27 // glvw 4 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v10, acc31 // glvw 4 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc27, v9 +v_accvgpr_write_b32 acc31, v10 +v_accvgpr_read_b32 v7, acc35 // glvw 4 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc39 // glvw 4 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v9, acc43 // glvw 4 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v10, acc47 // glvw 4 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc47, v10 +v_accvgpr_read_b32 v7, acc51 // glvw 4 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc55 // glvw 4 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v9, acc59 // glvw 4 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v10, acc63 // glvw 4 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_write_b32 acc59, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_read_b32 v7, acc67 // glvw 4 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc71 // glvw 4 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v9, acc75 // glvw 4 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v10, acc79 // glvw 4 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_write_b32 acc75, v9 +v_accvgpr_write_b32 acc79, v10 +v_accvgpr_read_b32 v7, acc83 // glvw 4 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc87 // glvw 4 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v9, acc91 // glvw 4 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v10, acc95 // glvw 4 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_write_b32 acc91, v9 +v_accvgpr_write_b32 acc95, v10 +v_accvgpr_read_b32 v7, acc99 // glvw 4 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc103 // glvw 4 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v9, acc107 // glvw 4 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v10, acc111 // glvw 4 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_write_b32 acc107, v9 +v_accvgpr_write_b32 acc111, v10 +v_accvgpr_read_b32 v7, acc115 // glvw 4 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc119 // glvw 4 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v9, acc123 // glvw 4 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v10, acc127 // glvw 4 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v7, v0, v7 offset:4 // permute edge values +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +v_accvgpr_write_b32 acc123, v9 +v_accvgpr_write_b32 acc127, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=5 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW5_BM0_VW0: /// r5 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc12 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc0 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc4 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc8 // glvw 5 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_write_b32 acc8, v9 +v_accvgpr_write_b32 acc12, v10 +v_accvgpr_read_b32 v7, acc28 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc16 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc20 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc24 // glvw 5 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc24, v9 +v_accvgpr_write_b32 acc28, v10 +v_accvgpr_read_b32 v7, acc44 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc32 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc36 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc40 // glvw 5 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc44, v10 +v_accvgpr_read_b32 v7, acc60 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc48 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc52 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc56 // glvw 5 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_write_b32 acc56, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_read_b32 v7, acc76 // glvw 5 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc64 // glvw 5 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v9, acc68 // glvw 5 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v10, acc72 // glvw 5 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_write_b32 acc72, v9 +v_accvgpr_write_b32 acc76, v10 +v_accvgpr_read_b32 v7, acc92 // glvw 5 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc80 // glvw 5 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v9, acc84 // glvw 5 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v10, acc88 // glvw 5 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_write_b32 acc88, v9 +v_accvgpr_write_b32 acc92, v10 +v_accvgpr_read_b32 v7, acc108 // glvw 5 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc96 // glvw 5 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v9, acc100 // glvw 5 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v10, acc104 // glvw 5 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_write_b32 acc104, v9 +v_accvgpr_write_b32 acc108, v10 +v_accvgpr_read_b32 v7, acc124 // glvw 5 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc112 // glvw 5 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v9, acc116 // glvw 5 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v10, acc120 // glvw 5 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_write_b32 acc120, v9 +v_accvgpr_write_b32 acc124, v10 +v_accvgpr_read_b32 v7, acc13 // glvw 5 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc1 // glvw 5 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v9, acc5 // glvw 5 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v10, acc9 // glvw 5 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_write_b32 acc9, v9 +v_accvgpr_write_b32 acc13, v10 +v_accvgpr_read_b32 v7, acc29 // glvw 5 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc17 // glvw 5 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v9, acc21 // glvw 5 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v10, acc25 // glvw 5 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc25, v9 +v_accvgpr_write_b32 acc29, v10 +v_accvgpr_read_b32 v7, acc45 // glvw 5 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc33 // glvw 5 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v9, acc37 // glvw 5 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v10, acc41 // glvw 5 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc45, v10 +v_accvgpr_read_b32 v7, acc61 // glvw 5 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc49 // glvw 5 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v9, acc53 // glvw 5 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v10, acc57 // glvw 5 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_write_b32 acc57, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_read_b32 v7, acc77 // glvw 5 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc65 // glvw 5 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v9, acc69 // glvw 5 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v10, acc73 // glvw 5 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_write_b32 acc73, v9 +v_accvgpr_write_b32 acc77, v10 +v_accvgpr_read_b32 v7, acc93 // glvw 5 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc81 // glvw 5 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v9, acc85 // glvw 5 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v10, acc89 // glvw 5 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_write_b32 acc89, v9 +v_accvgpr_write_b32 acc93, v10 +v_accvgpr_read_b32 v7, acc109 // glvw 5 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc97 // glvw 5 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v9, acc101 // glvw 5 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v10, acc105 // glvw 5 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_write_b32 acc105, v9 +v_accvgpr_write_b32 acc109, v10 +v_accvgpr_read_b32 v7, acc125 // glvw 5 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc113 // glvw 5 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v9, acc117 // glvw 5 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v10, acc121 // glvw 5 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_write_b32 acc121, v9 +v_accvgpr_write_b32 acc125, v10 +v_accvgpr_read_b32 v7, acc14 // glvw 5 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc2 // glvw 5 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v9, acc6 // glvw 5 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v10, acc10 // glvw 5 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_write_b32 acc10, v9 +v_accvgpr_write_b32 acc14, v10 +v_accvgpr_read_b32 v7, acc30 // glvw 5 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc18 // glvw 5 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v9, acc22 // glvw 5 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v10, acc26 // glvw 5 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc26, v9 +v_accvgpr_write_b32 acc30, v10 +v_accvgpr_read_b32 v7, acc46 // glvw 5 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc34 // glvw 5 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v9, acc38 // glvw 5 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v10, acc42 // glvw 5 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc46, v10 +v_accvgpr_read_b32 v7, acc62 // glvw 5 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc50 // glvw 5 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v9, acc54 // glvw 5 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v10, acc58 // glvw 5 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_write_b32 acc58, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_read_b32 v7, acc78 // glvw 5 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc66 // glvw 5 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v9, acc70 // glvw 5 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v10, acc74 // glvw 5 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_write_b32 acc74, v9 +v_accvgpr_write_b32 acc78, v10 +v_accvgpr_read_b32 v7, acc94 // glvw 5 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc82 // glvw 5 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v9, acc86 // glvw 5 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v10, acc90 // glvw 5 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_write_b32 acc90, v9 +v_accvgpr_write_b32 acc94, v10 +v_accvgpr_read_b32 v7, acc110 // glvw 5 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc98 // glvw 5 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v9, acc102 // glvw 5 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v10, acc106 // glvw 5 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_write_b32 acc106, v9 +v_accvgpr_write_b32 acc110, v10 +v_accvgpr_read_b32 v7, acc126 // glvw 5 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc114 // glvw 5 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v9, acc118 // glvw 5 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v10, acc122 // glvw 5 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_write_b32 acc122, v9 +v_accvgpr_write_b32 acc126, v10 +v_accvgpr_read_b32 v7, acc15 // glvw 5 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc3 // glvw 5 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v9, acc7 // glvw 5 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v10, acc11 // glvw 5 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_write_b32 acc11, v9 +v_accvgpr_write_b32 acc15, v10 +v_accvgpr_read_b32 v7, acc31 // glvw 5 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc19 // glvw 5 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v9, acc23 // glvw 5 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v10, acc27 // glvw 5 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc27, v9 +v_accvgpr_write_b32 acc31, v10 +v_accvgpr_read_b32 v7, acc47 // glvw 5 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc35 // glvw 5 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v9, acc39 // glvw 5 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v10, acc43 // glvw 5 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc47, v10 +v_accvgpr_read_b32 v7, acc63 // glvw 5 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc51 // glvw 5 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v9, acc55 // glvw 5 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v10, acc59 // glvw 5 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_write_b32 acc59, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_read_b32 v7, acc79 // glvw 5 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc67 // glvw 5 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v9, acc71 // glvw 5 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v10, acc75 // glvw 5 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_write_b32 acc75, v9 +v_accvgpr_write_b32 acc79, v10 +v_accvgpr_read_b32 v7, acc95 // glvw 5 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc83 // glvw 5 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v9, acc87 // glvw 5 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v10, acc91 // glvw 5 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_write_b32 acc91, v9 +v_accvgpr_write_b32 acc95, v10 +v_accvgpr_read_b32 v7, acc111 // glvw 5 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc99 // glvw 5 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v9, acc103 // glvw 5 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v10, acc107 // glvw 5 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_write_b32 acc107, v9 +v_accvgpr_write_b32 acc111, v10 +v_accvgpr_read_b32 v7, acc127 // glvw 5 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc115 // glvw 5 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v9, acc119 // glvw 5 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v10, acc123 // glvw 5 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v8, v0, v8 offset:4 // permute edge values +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +v_accvgpr_write_b32 acc123, v9 +v_accvgpr_write_b32 acc127, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=6 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW6_BM0_VW0: /// r6 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc8 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc12 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc0 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc4 // glvw 6 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_write_b32 acc8, v9 +v_accvgpr_write_b32 acc12, v10 +v_accvgpr_read_b32 v7, acc24 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc28 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc16 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc20 // glvw 6 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc24, v9 +v_accvgpr_write_b32 acc28, v10 +v_accvgpr_read_b32 v7, acc40 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc44 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc32 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc36 // glvw 6 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc44, v10 +v_accvgpr_read_b32 v7, acc56 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc60 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc48 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc52 // glvw 6 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_write_b32 acc56, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_read_b32 v7, acc72 // glvw 6 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc76 // glvw 6 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v9, acc64 // glvw 6 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v10, acc68 // glvw 6 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_write_b32 acc72, v9 +v_accvgpr_write_b32 acc76, v10 +v_accvgpr_read_b32 v7, acc88 // glvw 6 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc92 // glvw 6 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v9, acc80 // glvw 6 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v10, acc84 // glvw 6 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_write_b32 acc88, v9 +v_accvgpr_write_b32 acc92, v10 +v_accvgpr_read_b32 v7, acc104 // glvw 6 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc108 // glvw 6 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v9, acc96 // glvw 6 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v10, acc100 // glvw 6 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_write_b32 acc104, v9 +v_accvgpr_write_b32 acc108, v10 +v_accvgpr_read_b32 v7, acc120 // glvw 6 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc124 // glvw 6 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v9, acc112 // glvw 6 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v10, acc116 // glvw 6 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_write_b32 acc120, v9 +v_accvgpr_write_b32 acc124, v10 +v_accvgpr_read_b32 v7, acc9 // glvw 6 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc13 // glvw 6 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v9, acc1 // glvw 6 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v10, acc5 // glvw 6 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_write_b32 acc9, v9 +v_accvgpr_write_b32 acc13, v10 +v_accvgpr_read_b32 v7, acc25 // glvw 6 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc29 // glvw 6 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v9, acc17 // glvw 6 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v10, acc21 // glvw 6 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc25, v9 +v_accvgpr_write_b32 acc29, v10 +v_accvgpr_read_b32 v7, acc41 // glvw 6 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc45 // glvw 6 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v9, acc33 // glvw 6 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v10, acc37 // glvw 6 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc45, v10 +v_accvgpr_read_b32 v7, acc57 // glvw 6 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc61 // glvw 6 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v9, acc49 // glvw 6 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v10, acc53 // glvw 6 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_write_b32 acc57, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_read_b32 v7, acc73 // glvw 6 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc77 // glvw 6 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v9, acc65 // glvw 6 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v10, acc69 // glvw 6 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_write_b32 acc73, v9 +v_accvgpr_write_b32 acc77, v10 +v_accvgpr_read_b32 v7, acc89 // glvw 6 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc93 // glvw 6 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v9, acc81 // glvw 6 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v10, acc85 // glvw 6 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_write_b32 acc89, v9 +v_accvgpr_write_b32 acc93, v10 +v_accvgpr_read_b32 v7, acc105 // glvw 6 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc109 // glvw 6 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v9, acc97 // glvw 6 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v10, acc101 // glvw 6 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_write_b32 acc105, v9 +v_accvgpr_write_b32 acc109, v10 +v_accvgpr_read_b32 v7, acc121 // glvw 6 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc125 // glvw 6 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v9, acc113 // glvw 6 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v10, acc117 // glvw 6 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_write_b32 acc121, v9 +v_accvgpr_write_b32 acc125, v10 +v_accvgpr_read_b32 v7, acc10 // glvw 6 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc14 // glvw 6 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v9, acc2 // glvw 6 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v10, acc6 // glvw 6 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_write_b32 acc10, v9 +v_accvgpr_write_b32 acc14, v10 +v_accvgpr_read_b32 v7, acc26 // glvw 6 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc30 // glvw 6 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v9, acc18 // glvw 6 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v10, acc22 // glvw 6 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc26, v9 +v_accvgpr_write_b32 acc30, v10 +v_accvgpr_read_b32 v7, acc42 // glvw 6 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc46 // glvw 6 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v9, acc34 // glvw 6 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v10, acc38 // glvw 6 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc46, v10 +v_accvgpr_read_b32 v7, acc58 // glvw 6 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc62 // glvw 6 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v9, acc50 // glvw 6 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v10, acc54 // glvw 6 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_write_b32 acc58, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_read_b32 v7, acc74 // glvw 6 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc78 // glvw 6 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v9, acc66 // glvw 6 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v10, acc70 // glvw 6 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_write_b32 acc74, v9 +v_accvgpr_write_b32 acc78, v10 +v_accvgpr_read_b32 v7, acc90 // glvw 6 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc94 // glvw 6 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v9, acc82 // glvw 6 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v10, acc86 // glvw 6 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_write_b32 acc90, v9 +v_accvgpr_write_b32 acc94, v10 +v_accvgpr_read_b32 v7, acc106 // glvw 6 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc110 // glvw 6 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v9, acc98 // glvw 6 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v10, acc102 // glvw 6 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_write_b32 acc106, v9 +v_accvgpr_write_b32 acc110, v10 +v_accvgpr_read_b32 v7, acc122 // glvw 6 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc126 // glvw 6 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v9, acc114 // glvw 6 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v10, acc118 // glvw 6 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_write_b32 acc122, v9 +v_accvgpr_write_b32 acc126, v10 +v_accvgpr_read_b32 v7, acc11 // glvw 6 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc15 // glvw 6 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v9, acc3 // glvw 6 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v10, acc7 // glvw 6 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_write_b32 acc11, v9 +v_accvgpr_write_b32 acc15, v10 +v_accvgpr_read_b32 v7, acc27 // glvw 6 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc31 // glvw 6 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v9, acc19 // glvw 6 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v10, acc23 // glvw 6 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc27, v9 +v_accvgpr_write_b32 acc31, v10 +v_accvgpr_read_b32 v7, acc43 // glvw 6 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc47 // glvw 6 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v9, acc35 // glvw 6 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v10, acc39 // glvw 6 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc47, v10 +v_accvgpr_read_b32 v7, acc59 // glvw 6 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc63 // glvw 6 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v9, acc51 // glvw 6 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v10, acc55 // glvw 6 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_write_b32 acc59, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_read_b32 v7, acc75 // glvw 6 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc79 // glvw 6 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v9, acc67 // glvw 6 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v10, acc71 // glvw 6 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_write_b32 acc75, v9 +v_accvgpr_write_b32 acc79, v10 +v_accvgpr_read_b32 v7, acc91 // glvw 6 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc95 // glvw 6 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v9, acc83 // glvw 6 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v10, acc87 // glvw 6 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_write_b32 acc91, v9 +v_accvgpr_write_b32 acc95, v10 +v_accvgpr_read_b32 v7, acc107 // glvw 6 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc111 // glvw 6 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v9, acc99 // glvw 6 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v10, acc103 // glvw 6 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_write_b32 acc107, v9 +v_accvgpr_write_b32 acc111, v10 +v_accvgpr_read_b32 v7, acc123 // glvw 6 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc127 // glvw 6 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v9, acc115 // glvw 6 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v10, acc119 // glvw 6 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v9, v0, v9 offset:4 // permute edge values +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +v_accvgpr_write_b32 acc123, v9 +v_accvgpr_write_b32 acc127, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + + +/******************************************/ +/* shift d0 r=7 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents0_GLVW7_BM0_VW0: /// r7 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc4 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc8 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc12 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc0 // glvw 7 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc4, v8 +v_accvgpr_write_b32 acc8, v9 +v_accvgpr_write_b32 acc12, v10 +v_accvgpr_read_b32 v7, acc20 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc24 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc28 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc16 // glvw 7 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc16, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc24, v9 +v_accvgpr_write_b32 acc28, v10 +v_accvgpr_read_b32 v7, acc36 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc40 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc44 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc32 // glvw 7 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc32, v7 +v_accvgpr_write_b32 acc36, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc44, v10 +v_accvgpr_read_b32 v7, acc52 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc56 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc60 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc48 // glvw 7 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc48, v7 +v_accvgpr_write_b32 acc52, v8 +v_accvgpr_write_b32 acc56, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_read_b32 v7, acc68 // glvw 7 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v8, acc72 // glvw 7 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v9, acc76 // glvw 7 mb 0 tt1 4 r 0 +v_accvgpr_read_b32 v10, acc64 // glvw 7 mb 0 tt1 4 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc64, v7 +v_accvgpr_write_b32 acc68, v8 +v_accvgpr_write_b32 acc72, v9 +v_accvgpr_write_b32 acc76, v10 +v_accvgpr_read_b32 v7, acc84 // glvw 7 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v8, acc88 // glvw 7 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v9, acc92 // glvw 7 mb 0 tt1 5 r 0 +v_accvgpr_read_b32 v10, acc80 // glvw 7 mb 0 tt1 5 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc80, v7 +v_accvgpr_write_b32 acc84, v8 +v_accvgpr_write_b32 acc88, v9 +v_accvgpr_write_b32 acc92, v10 +v_accvgpr_read_b32 v7, acc100 // glvw 7 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v8, acc104 // glvw 7 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v9, acc108 // glvw 7 mb 0 tt1 6 r 0 +v_accvgpr_read_b32 v10, acc96 // glvw 7 mb 0 tt1 6 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc96, v7 +v_accvgpr_write_b32 acc100, v8 +v_accvgpr_write_b32 acc104, v9 +v_accvgpr_write_b32 acc108, v10 +v_accvgpr_read_b32 v7, acc116 // glvw 7 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v8, acc120 // glvw 7 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v9, acc124 // glvw 7 mb 0 tt1 7 r 0 +v_accvgpr_read_b32 v10, acc112 // glvw 7 mb 0 tt1 7 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc112, v7 +v_accvgpr_write_b32 acc116, v8 +v_accvgpr_write_b32 acc120, v9 +v_accvgpr_write_b32 acc124, v10 +v_accvgpr_read_b32 v7, acc5 // glvw 7 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v8, acc9 // glvw 7 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v9, acc13 // glvw 7 mb 0 tt1 8 r 0 +v_accvgpr_read_b32 v10, acc1 // glvw 7 mb 0 tt1 8 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc5, v8 +v_accvgpr_write_b32 acc9, v9 +v_accvgpr_write_b32 acc13, v10 +v_accvgpr_read_b32 v7, acc21 // glvw 7 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v8, acc25 // glvw 7 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v9, acc29 // glvw 7 mb 0 tt1 9 r 0 +v_accvgpr_read_b32 v10, acc17 // glvw 7 mb 0 tt1 9 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc17, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc25, v9 +v_accvgpr_write_b32 acc29, v10 +v_accvgpr_read_b32 v7, acc37 // glvw 7 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v8, acc41 // glvw 7 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v9, acc45 // glvw 7 mb 0 tt1 10 r 0 +v_accvgpr_read_b32 v10, acc33 // glvw 7 mb 0 tt1 10 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc33, v7 +v_accvgpr_write_b32 acc37, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc45, v10 +v_accvgpr_read_b32 v7, acc53 // glvw 7 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v8, acc57 // glvw 7 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v9, acc61 // glvw 7 mb 0 tt1 11 r 0 +v_accvgpr_read_b32 v10, acc49 // glvw 7 mb 0 tt1 11 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc49, v7 +v_accvgpr_write_b32 acc53, v8 +v_accvgpr_write_b32 acc57, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_read_b32 v7, acc69 // glvw 7 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v8, acc73 // glvw 7 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v9, acc77 // glvw 7 mb 0 tt1 12 r 0 +v_accvgpr_read_b32 v10, acc65 // glvw 7 mb 0 tt1 12 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc65, v7 +v_accvgpr_write_b32 acc69, v8 +v_accvgpr_write_b32 acc73, v9 +v_accvgpr_write_b32 acc77, v10 +v_accvgpr_read_b32 v7, acc85 // glvw 7 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v8, acc89 // glvw 7 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v9, acc93 // glvw 7 mb 0 tt1 13 r 0 +v_accvgpr_read_b32 v10, acc81 // glvw 7 mb 0 tt1 13 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc81, v7 +v_accvgpr_write_b32 acc85, v8 +v_accvgpr_write_b32 acc89, v9 +v_accvgpr_write_b32 acc93, v10 +v_accvgpr_read_b32 v7, acc101 // glvw 7 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v8, acc105 // glvw 7 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v9, acc109 // glvw 7 mb 0 tt1 14 r 0 +v_accvgpr_read_b32 v10, acc97 // glvw 7 mb 0 tt1 14 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc97, v7 +v_accvgpr_write_b32 acc101, v8 +v_accvgpr_write_b32 acc105, v9 +v_accvgpr_write_b32 acc109, v10 +v_accvgpr_read_b32 v7, acc117 // glvw 7 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v8, acc121 // glvw 7 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v9, acc125 // glvw 7 mb 0 tt1 15 r 0 +v_accvgpr_read_b32 v10, acc113 // glvw 7 mb 0 tt1 15 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc113, v7 +v_accvgpr_write_b32 acc117, v8 +v_accvgpr_write_b32 acc121, v9 +v_accvgpr_write_b32 acc125, v10 +v_accvgpr_read_b32 v7, acc6 // glvw 7 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v8, acc10 // glvw 7 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v9, acc14 // glvw 7 mb 0 tt1 16 r 0 +v_accvgpr_read_b32 v10, acc2 // glvw 7 mb 0 tt1 16 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc6, v8 +v_accvgpr_write_b32 acc10, v9 +v_accvgpr_write_b32 acc14, v10 +v_accvgpr_read_b32 v7, acc22 // glvw 7 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v8, acc26 // glvw 7 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v9, acc30 // glvw 7 mb 0 tt1 17 r 0 +v_accvgpr_read_b32 v10, acc18 // glvw 7 mb 0 tt1 17 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc18, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc26, v9 +v_accvgpr_write_b32 acc30, v10 +v_accvgpr_read_b32 v7, acc38 // glvw 7 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v8, acc42 // glvw 7 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v9, acc46 // glvw 7 mb 0 tt1 18 r 0 +v_accvgpr_read_b32 v10, acc34 // glvw 7 mb 0 tt1 18 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc34, v7 +v_accvgpr_write_b32 acc38, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc46, v10 +v_accvgpr_read_b32 v7, acc54 // glvw 7 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v8, acc58 // glvw 7 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v9, acc62 // glvw 7 mb 0 tt1 19 r 0 +v_accvgpr_read_b32 v10, acc50 // glvw 7 mb 0 tt1 19 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc50, v7 +v_accvgpr_write_b32 acc54, v8 +v_accvgpr_write_b32 acc58, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_read_b32 v7, acc70 // glvw 7 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v8, acc74 // glvw 7 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v9, acc78 // glvw 7 mb 0 tt1 20 r 0 +v_accvgpr_read_b32 v10, acc66 // glvw 7 mb 0 tt1 20 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc66, v7 +v_accvgpr_write_b32 acc70, v8 +v_accvgpr_write_b32 acc74, v9 +v_accvgpr_write_b32 acc78, v10 +v_accvgpr_read_b32 v7, acc86 // glvw 7 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v8, acc90 // glvw 7 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v9, acc94 // glvw 7 mb 0 tt1 21 r 0 +v_accvgpr_read_b32 v10, acc82 // glvw 7 mb 0 tt1 21 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc82, v7 +v_accvgpr_write_b32 acc86, v8 +v_accvgpr_write_b32 acc90, v9 +v_accvgpr_write_b32 acc94, v10 +v_accvgpr_read_b32 v7, acc102 // glvw 7 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v8, acc106 // glvw 7 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v9, acc110 // glvw 7 mb 0 tt1 22 r 0 +v_accvgpr_read_b32 v10, acc98 // glvw 7 mb 0 tt1 22 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc98, v7 +v_accvgpr_write_b32 acc102, v8 +v_accvgpr_write_b32 acc106, v9 +v_accvgpr_write_b32 acc110, v10 +v_accvgpr_read_b32 v7, acc118 // glvw 7 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v8, acc122 // glvw 7 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v9, acc126 // glvw 7 mb 0 tt1 23 r 0 +v_accvgpr_read_b32 v10, acc114 // glvw 7 mb 0 tt1 23 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc114, v7 +v_accvgpr_write_b32 acc118, v8 +v_accvgpr_write_b32 acc122, v9 +v_accvgpr_write_b32 acc126, v10 +v_accvgpr_read_b32 v7, acc7 // glvw 7 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v8, acc11 // glvw 7 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v9, acc15 // glvw 7 mb 0 tt1 24 r 0 +v_accvgpr_read_b32 v10, acc3 // glvw 7 mb 0 tt1 24 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc7, v8 +v_accvgpr_write_b32 acc11, v9 +v_accvgpr_write_b32 acc15, v10 +v_accvgpr_read_b32 v7, acc23 // glvw 7 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v8, acc27 // glvw 7 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v9, acc31 // glvw 7 mb 0 tt1 25 r 0 +v_accvgpr_read_b32 v10, acc19 // glvw 7 mb 0 tt1 25 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc19, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc27, v9 +v_accvgpr_write_b32 acc31, v10 +v_accvgpr_read_b32 v7, acc39 // glvw 7 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v8, acc43 // glvw 7 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v9, acc47 // glvw 7 mb 0 tt1 26 r 0 +v_accvgpr_read_b32 v10, acc35 // glvw 7 mb 0 tt1 26 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc35, v7 +v_accvgpr_write_b32 acc39, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc47, v10 +v_accvgpr_read_b32 v7, acc55 // glvw 7 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v8, acc59 // glvw 7 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v9, acc63 // glvw 7 mb 0 tt1 27 r 0 +v_accvgpr_read_b32 v10, acc51 // glvw 7 mb 0 tt1 27 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc51, v7 +v_accvgpr_write_b32 acc55, v8 +v_accvgpr_write_b32 acc59, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_read_b32 v7, acc71 // glvw 7 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v8, acc75 // glvw 7 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v9, acc79 // glvw 7 mb 0 tt1 28 r 0 +v_accvgpr_read_b32 v10, acc67 // glvw 7 mb 0 tt1 28 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc67, v7 +v_accvgpr_write_b32 acc71, v8 +v_accvgpr_write_b32 acc75, v9 +v_accvgpr_write_b32 acc79, v10 +v_accvgpr_read_b32 v7, acc87 // glvw 7 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v8, acc91 // glvw 7 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v9, acc95 // glvw 7 mb 0 tt1 29 r 0 +v_accvgpr_read_b32 v10, acc83 // glvw 7 mb 0 tt1 29 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc83, v7 +v_accvgpr_write_b32 acc87, v8 +v_accvgpr_write_b32 acc91, v9 +v_accvgpr_write_b32 acc95, v10 +v_accvgpr_read_b32 v7, acc103 // glvw 7 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v8, acc107 // glvw 7 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v9, acc111 // glvw 7 mb 0 tt1 30 r 0 +v_accvgpr_read_b32 v10, acc99 // glvw 7 mb 0 tt1 30 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc99, v7 +v_accvgpr_write_b32 acc103, v8 +v_accvgpr_write_b32 acc107, v9 +v_accvgpr_write_b32 acc111, v10 +v_accvgpr_read_b32 v7, acc119 // glvw 7 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v8, acc123 // glvw 7 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v9, acc127 // glvw 7 mb 0 tt1 31 r 0 +v_accvgpr_read_b32 v10, acc115 // glvw 7 mb 0 tt1 31 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +ds_bpermute_b32 v10, v0, v10 offset:4 // permute edge values +s_waitcnt 0 // (Wait all) +v_accvgpr_write_b32 acc115, v7 +v_accvgpr_write_b32 acc119, v8 +v_accvgpr_write_b32 acc123, v9 +v_accvgpr_write_b32 acc127, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents0_GLVW0 + +label_ShiftVectorComponents0_GLVW0: /// end shift0 + +/* shift vector components d1 */ +v_mov_b32 v3, s[sgprWorkGroup1] +v_mul_i32_i24 v3, -0x100, v3 // wg*MT +v_add_co_u32 v3, vcc, s[sgprSizesFree+1], v3 // wgMT = Size - wg*MT +v_mov_b32 v4, 0x100 // MT +v_cmp_lt_u32 s[8:9], v3, v4 // wgMT < MT +v_cndmask_b32 v3, v4, v3, s[8:9] // wgMT = (wgMT < MT) ? wgMT : MT +v_lshrrev_b32 v5, 7, v[vgprSerial] // 5 = Serial / 128 +v_and_b32 v5, 1, v5 // v5 = v5 % 2 +v_lshrrev_b32 v6, 7, v3 // 6 = 3 / 128 +v_and_b32 v6, 1, v6 // v6 = v6 % 2 +v_cmp_eq_u32 s[8:9], v6, v5 // wave_id == block_belong_to_wave? +v_cndmask_b32 v3, v4, v3, s[8:9] // wgMT = (wgMT < MT) ? wgMT : MT + +/* mbReg: which mb block need to shift, mb(matrixInstCoal(16) * VectorWidth(8)) */ +v_lshrrev_b32 v4, 7, v3 // 4 = 3 / 128 +v_lshlrev_b32 v6, 0, v5 // v6 = v5 * 1 +v_sub_u32 v4, v4, v6 + +/* gbReg: glvw block id */ +v_lshrrev_b32 v6, 3, v3 // 6 = 3 / 8 + +/* tgbReg: glvw block id */ +v_lshrrev_b32 v7, 4, v[vgprSerial] // 7 = Serial / 16 +v_and_b32 v7, 3, v7 // v7 = v7 % 4 +v_lshlrev_b32 v7, 5, v7 // v7 = v7 * 32 +v_lshrrev_b32 v7, 3, v7 // 7 = 7 / 8 +v_lshlrev_b32 v5, 4, v5 // v5 = v5 * 16 +v_add_co_u32 v7, vcc, v5, v7 // tgbReg = (tid_coal * continOut) / GLVW +v_sub_u32 v6, v6, v7 + +/* vwReg: glvw in which vw block? */ +v_and_b32 v5, 31, v3 // permute register between threads +v_lshrrev_b32 v5, 3, v5 // permute register between threads + +/* rReg : reminder of M_size % GlobalReadVectorWidth */ +v_and_b32 v7, 7, v3 // v7 = v3 % 8 +v_cmp_eq_u32 vcc, v7, 0x1 // wgMT%VW == 1 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1 // branch to shift d1 r=1 +v_cmp_eq_u32 vcc, v7, 0x2 // wgMT%VW == 2 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2 // branch to shift d1 r=2 +v_cmp_eq_u32 vcc, v7, 0x3 // wgMT%VW == 3 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3 // branch to shift d1 r=3 +v_cmp_eq_u32 vcc, v7, 0x4 // wgMT%VW == 4 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4 // branch to shift d1 r=4 +v_cmp_eq_u32 vcc, v7, 0x5 // wgMT%VW == 5 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5 // branch to shift d1 r=5 +v_cmp_eq_u32 vcc, v7, 0x6 // wgMT%VW == 6 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6 // branch to shift d1 r=6 +v_cmp_eq_u32 vcc, v7, 0x7 // wgMT%VW == 7 +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7 // branch to shift d1 r=7 + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + +/******************************************/ +/* shift d1 r=1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r1 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1_BM0 + +/******************************************/ +/* shift d1 r=2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r2 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2_BM0 + +/******************************************/ +/* shift d1 r=3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r3 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3_BM0 + +/******************************************/ +/* shift d1 r=4 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r4 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4_BM0 + +/******************************************/ +/* shift d1 r=5 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r5 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5_BM0 + +/******************************************/ +/* shift d1 r=6 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r6 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6_BM0 + +/******************************************/ +/* shift d1 r=7 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7: +v_cmp_eq_u32 vcc, v4, 0x0 + +/* branch to shift d1 r7 mb0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7_BM0 + +/******************************************/ +/* shift d1 r=1 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1_BM0: /// r1 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r1 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r1 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r1 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r1 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW1_BM0_VW3 + +/******************************************/ +/* shift d1 r=2 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2_BM0: /// r2 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r2 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r2 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r2 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r2 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW2_BM0_VW3 + +/******************************************/ +/* shift d1 r=3 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3_BM0: /// r3 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r3 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r3 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r3 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r3 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW3_BM0_VW3 + +/******************************************/ +/* shift d1 r=4 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4_BM0: /// r4 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r4 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r4 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r4 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r4 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW4_BM0_VW3 + +/******************************************/ +/* shift d1 r=5 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5_BM0: /// r5 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r5 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r5 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r5 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r5 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW5_BM0_VW3 + +/******************************************/ +/* shift d1 r=6 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6_BM0: /// r6 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r6 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r6 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r6 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r6 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW6_BM0_VW3 + +/******************************************/ +/* shift d1 r=7 mb=0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7_BM0: /// r7 mb0 +v_cmp_eq_u32 vcc, v5, 0x0 + +/* branch to shift d1 r7 mb0 vw0 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7_BM0_VW0 +v_cmp_eq_u32 vcc, v5, 0x1 + +/* branch to shift d1 r7 mb0 vw1 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7_BM0_VW1 +v_cmp_eq_u32 vcc, v5, 0x2 + +/* branch to shift d1 r7 mb0 vw2 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7_BM0_VW2 +v_cmp_eq_u32 vcc, v5, 0x3 + +/* branch to shift d1 r7 mb0 vw3 */ +s_cbranch_vccnz label_ShiftVectorComponents1_GLVW7_BM0_VW3 + +/******************************************/ +/* shift d1 r=1 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1_BM0_VW0: /// r1 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc112 // glvw 1 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_read_b32 v7, acc116 // glvw 1 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_read_b32 v7, acc120 // glvw 1 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_read_b32 v7, acc124 // glvw 1 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=1 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1_BM0_VW1: /// r1 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc113 // glvw 1 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_read_b32 v7, acc117 // glvw 1 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_read_b32 v7, acc121 // glvw 1 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_read_b32 v7, acc125 // glvw 1 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=1 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1_BM0_VW2: /// r1 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc114 // glvw 1 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_read_b32 v7, acc118 // glvw 1 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_read_b32 v7, acc122 // glvw 1 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_read_b32 v7, acc126 // glvw 1 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=1 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW1_BM0_VW3: /// r1 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc115 // glvw 1 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_read_b32 v7, acc119 // glvw 1 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_read_b32 v7, acc123 // glvw 1 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_read_b32 v7, acc127 // glvw 1 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=2 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2_BM0_VW0: /// r2 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc96 // glvw 2 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc112 // glvw 2 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_read_b32 v7, acc100 // glvw 2 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc116 // glvw 2 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_read_b32 v7, acc104 // glvw 2 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc120 // glvw 2 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_read_b32 v7, acc108 // glvw 2 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc124 // glvw 2 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=2 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2_BM0_VW1: /// r2 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc97 // glvw 2 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc113 // glvw 2 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_read_b32 v7, acc101 // glvw 2 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc117 // glvw 2 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_read_b32 v7, acc105 // glvw 2 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc121 // glvw 2 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_read_b32 v7, acc109 // glvw 2 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc125 // glvw 2 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=2 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2_BM0_VW2: /// r2 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc98 // glvw 2 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc114 // glvw 2 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_read_b32 v7, acc102 // glvw 2 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc118 // glvw 2 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_read_b32 v7, acc106 // glvw 2 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc122 // glvw 2 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_read_b32 v7, acc110 // glvw 2 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc126 // glvw 2 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=2 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW2_BM0_VW3: /// r2 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc99 // glvw 2 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc115 // glvw 2 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_read_b32 v7, acc103 // glvw 2 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc119 // glvw 2 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_read_b32 v7, acc107 // glvw 2 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc123 // glvw 2 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_read_b32 v7, acc111 // glvw 2 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc127 // glvw 2 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=3 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3_BM0_VW0: /// r3 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc80 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc96 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc112 // glvw 3 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_write_b32 acc32, v9 +v_accvgpr_read_b32 v7, acc84 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc100 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc116 // glvw 3 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc36, v9 +v_accvgpr_read_b32 v7, acc88 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc104 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc120 // glvw 3 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_read_b32 v7, acc92 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc108 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc124 // glvw 3 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +v_accvgpr_write_b32 acc44, v9 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=3 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3_BM0_VW1: /// r3 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc81 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc97 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc113 // glvw 3 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_write_b32 acc33, v9 +v_accvgpr_read_b32 v7, acc85 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc101 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc117 // glvw 3 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc37, v9 +v_accvgpr_read_b32 v7, acc89 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc105 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc121 // glvw 3 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_read_b32 v7, acc93 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc109 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc125 // glvw 3 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +v_accvgpr_write_b32 acc45, v9 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=3 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3_BM0_VW2: /// r3 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc82 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc98 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc114 // glvw 3 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_write_b32 acc34, v9 +v_accvgpr_read_b32 v7, acc86 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc102 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc118 // glvw 3 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc38, v9 +v_accvgpr_read_b32 v7, acc90 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc106 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc122 // glvw 3 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_read_b32 v7, acc94 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc110 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc126 // glvw 3 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +v_accvgpr_write_b32 acc46, v9 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=3 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW3_BM0_VW3: /// r3 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc83 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc99 // glvw 3 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc115 // glvw 3 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_write_b32 acc35, v9 +v_accvgpr_read_b32 v7, acc87 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc103 // glvw 3 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc119 // glvw 3 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc39, v9 +v_accvgpr_read_b32 v7, acc91 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc107 // glvw 3 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc123 // glvw 3 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_read_b32 v7, acc95 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc111 // glvw 3 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc127 // glvw 3 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +v_accvgpr_write_b32 acc47, v9 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=4 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4_BM0_VW0: /// r4 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc64 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc80 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc96 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc112 // glvw 4 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_write_b32 acc32, v9 +v_accvgpr_write_b32 acc48, v10 +v_accvgpr_read_b32 v7, acc68 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc84 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc100 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc116 // glvw 4 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc36, v9 +v_accvgpr_write_b32 acc52, v10 +v_accvgpr_read_b32 v7, acc72 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc88 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc104 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc120 // glvw 4 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc56, v10 +v_accvgpr_read_b32 v7, acc76 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc92 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc108 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc124 // glvw 4 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +v_accvgpr_write_b32 acc44, v9 +v_accvgpr_write_b32 acc60, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=4 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4_BM0_VW1: /// r4 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc65 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc81 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc97 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc113 // glvw 4 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_write_b32 acc33, v9 +v_accvgpr_write_b32 acc49, v10 +v_accvgpr_read_b32 v7, acc69 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc85 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc101 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc117 // glvw 4 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc37, v9 +v_accvgpr_write_b32 acc53, v10 +v_accvgpr_read_b32 v7, acc73 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc89 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc105 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc121 // glvw 4 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc57, v10 +v_accvgpr_read_b32 v7, acc77 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc93 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc109 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc125 // glvw 4 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +v_accvgpr_write_b32 acc45, v9 +v_accvgpr_write_b32 acc61, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=4 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4_BM0_VW2: /// r4 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc66 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc82 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc98 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc114 // glvw 4 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_write_b32 acc34, v9 +v_accvgpr_write_b32 acc50, v10 +v_accvgpr_read_b32 v7, acc70 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc86 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc102 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc118 // glvw 4 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc38, v9 +v_accvgpr_write_b32 acc54, v10 +v_accvgpr_read_b32 v7, acc74 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc90 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc106 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc122 // glvw 4 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc58, v10 +v_accvgpr_read_b32 v7, acc78 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc94 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc110 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc126 // glvw 4 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +v_accvgpr_write_b32 acc46, v9 +v_accvgpr_write_b32 acc62, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=4 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW4_BM0_VW3: /// r4 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc67 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc83 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc99 // glvw 4 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc115 // glvw 4 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_write_b32 acc35, v9 +v_accvgpr_write_b32 acc51, v10 +v_accvgpr_read_b32 v7, acc71 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc87 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc103 // glvw 4 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc119 // glvw 4 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc39, v9 +v_accvgpr_write_b32 acc55, v10 +v_accvgpr_read_b32 v7, acc75 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc91 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc107 // glvw 4 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc123 // glvw 4 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc59, v10 +v_accvgpr_read_b32 v7, acc79 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc95 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc111 // glvw 4 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc127 // glvw 4 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +v_accvgpr_write_b32 acc47, v9 +v_accvgpr_write_b32 acc63, v10 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=5 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5_BM0_VW0: /// r5 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc48 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc64 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc80 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc96 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc112 // glvw 5 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_write_b32 acc32, v9 +v_accvgpr_write_b32 acc48, v10 +v_accvgpr_write_b32 acc64, v11 +v_accvgpr_read_b32 v7, acc52 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc68 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc84 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc100 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc116 // glvw 5 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc36, v9 +v_accvgpr_write_b32 acc52, v10 +v_accvgpr_write_b32 acc68, v11 +v_accvgpr_read_b32 v7, acc56 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc72 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc88 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc104 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc120 // glvw 5 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc56, v10 +v_accvgpr_write_b32 acc72, v11 +v_accvgpr_read_b32 v7, acc60 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc76 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc92 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc108 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc124 // glvw 5 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +v_accvgpr_write_b32 acc44, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_write_b32 acc76, v11 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=5 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5_BM0_VW1: /// r5 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc49 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc65 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc81 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc97 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc113 // glvw 5 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_write_b32 acc33, v9 +v_accvgpr_write_b32 acc49, v10 +v_accvgpr_write_b32 acc65, v11 +v_accvgpr_read_b32 v7, acc53 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc69 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc85 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc101 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc117 // glvw 5 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc37, v9 +v_accvgpr_write_b32 acc53, v10 +v_accvgpr_write_b32 acc69, v11 +v_accvgpr_read_b32 v7, acc57 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc73 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc89 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc105 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc121 // glvw 5 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc57, v10 +v_accvgpr_write_b32 acc73, v11 +v_accvgpr_read_b32 v7, acc61 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc77 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc93 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc109 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc125 // glvw 5 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +v_accvgpr_write_b32 acc45, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_write_b32 acc77, v11 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=5 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5_BM0_VW2: /// r5 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc50 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc66 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc82 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc98 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc114 // glvw 5 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_write_b32 acc34, v9 +v_accvgpr_write_b32 acc50, v10 +v_accvgpr_write_b32 acc66, v11 +v_accvgpr_read_b32 v7, acc54 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc70 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc86 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc102 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc118 // glvw 5 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc38, v9 +v_accvgpr_write_b32 acc54, v10 +v_accvgpr_write_b32 acc70, v11 +v_accvgpr_read_b32 v7, acc58 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc74 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc90 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc106 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc122 // glvw 5 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc58, v10 +v_accvgpr_write_b32 acc74, v11 +v_accvgpr_read_b32 v7, acc62 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc78 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc94 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc110 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc126 // glvw 5 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +v_accvgpr_write_b32 acc46, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_write_b32 acc78, v11 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=5 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW5_BM0_VW3: /// r5 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc51 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc67 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc83 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc99 // glvw 5 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc115 // glvw 5 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_write_b32 acc35, v9 +v_accvgpr_write_b32 acc51, v10 +v_accvgpr_write_b32 acc67, v11 +v_accvgpr_read_b32 v7, acc55 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc71 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc87 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc103 // glvw 5 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc119 // glvw 5 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc39, v9 +v_accvgpr_write_b32 acc55, v10 +v_accvgpr_write_b32 acc71, v11 +v_accvgpr_read_b32 v7, acc59 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc75 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc91 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc107 // glvw 5 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc123 // glvw 5 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc59, v10 +v_accvgpr_write_b32 acc75, v11 +v_accvgpr_read_b32 v7, acc63 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc79 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc95 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc111 // glvw 5 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc127 // glvw 5 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +v_accvgpr_write_b32 acc47, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_write_b32 acc79, v11 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=6 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6_BM0_VW0: /// r6 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc32 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc48 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc64 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc80 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc96 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc112 // glvw 6 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_write_b32 acc32, v9 +v_accvgpr_write_b32 acc48, v10 +v_accvgpr_write_b32 acc64, v11 +v_accvgpr_write_b32 acc80, v12 +v_accvgpr_read_b32 v7, acc36 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc52 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc68 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc84 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc100 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc116 // glvw 6 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc36, v9 +v_accvgpr_write_b32 acc52, v10 +v_accvgpr_write_b32 acc68, v11 +v_accvgpr_write_b32 acc84, v12 +v_accvgpr_read_b32 v7, acc40 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc56 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc72 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc88 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc104 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc120 // glvw 6 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc56, v10 +v_accvgpr_write_b32 acc72, v11 +v_accvgpr_write_b32 acc88, v12 +v_accvgpr_read_b32 v7, acc44 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc60 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc76 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc92 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc108 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc124 // glvw 6 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +v_accvgpr_write_b32 acc44, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_write_b32 acc76, v11 +v_accvgpr_write_b32 acc92, v12 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=6 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6_BM0_VW1: /// r6 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc33 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc49 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc65 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc81 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc97 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc113 // glvw 6 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_write_b32 acc33, v9 +v_accvgpr_write_b32 acc49, v10 +v_accvgpr_write_b32 acc65, v11 +v_accvgpr_write_b32 acc81, v12 +v_accvgpr_read_b32 v7, acc37 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc53 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc69 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc85 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc101 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc117 // glvw 6 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc37, v9 +v_accvgpr_write_b32 acc53, v10 +v_accvgpr_write_b32 acc69, v11 +v_accvgpr_write_b32 acc85, v12 +v_accvgpr_read_b32 v7, acc41 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc57 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc73 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc89 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc105 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc121 // glvw 6 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc57, v10 +v_accvgpr_write_b32 acc73, v11 +v_accvgpr_write_b32 acc89, v12 +v_accvgpr_read_b32 v7, acc45 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc61 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc77 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc93 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc109 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc125 // glvw 6 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +v_accvgpr_write_b32 acc45, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_write_b32 acc77, v11 +v_accvgpr_write_b32 acc93, v12 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=6 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6_BM0_VW2: /// r6 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc34 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc50 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc66 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc82 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc98 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc114 // glvw 6 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_write_b32 acc34, v9 +v_accvgpr_write_b32 acc50, v10 +v_accvgpr_write_b32 acc66, v11 +v_accvgpr_write_b32 acc82, v12 +v_accvgpr_read_b32 v7, acc38 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc54 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc70 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc86 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc102 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc118 // glvw 6 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc38, v9 +v_accvgpr_write_b32 acc54, v10 +v_accvgpr_write_b32 acc70, v11 +v_accvgpr_write_b32 acc86, v12 +v_accvgpr_read_b32 v7, acc42 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc58 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc74 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc90 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc106 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc122 // glvw 6 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc58, v10 +v_accvgpr_write_b32 acc74, v11 +v_accvgpr_write_b32 acc90, v12 +v_accvgpr_read_b32 v7, acc46 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc62 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc78 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc94 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc110 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc126 // glvw 6 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +v_accvgpr_write_b32 acc46, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_write_b32 acc78, v11 +v_accvgpr_write_b32 acc94, v12 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=6 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW6_BM0_VW3: /// r6 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc35 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc51 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc67 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc83 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc99 // glvw 6 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc115 // glvw 6 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_write_b32 acc35, v9 +v_accvgpr_write_b32 acc51, v10 +v_accvgpr_write_b32 acc67, v11 +v_accvgpr_write_b32 acc83, v12 +v_accvgpr_read_b32 v7, acc39 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc55 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc71 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc87 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc103 // glvw 6 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc119 // glvw 6 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc39, v9 +v_accvgpr_write_b32 acc55, v10 +v_accvgpr_write_b32 acc71, v11 +v_accvgpr_write_b32 acc87, v12 +v_accvgpr_read_b32 v7, acc43 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc59 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc75 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc91 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc107 // glvw 6 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc123 // glvw 6 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc59, v10 +v_accvgpr_write_b32 acc75, v11 +v_accvgpr_write_b32 acc91, v12 +v_accvgpr_read_b32 v7, acc47 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc63 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc79 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc95 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc111 // glvw 6 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc127 // glvw 6 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +v_accvgpr_write_b32 acc47, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_write_b32 acc79, v11 +v_accvgpr_write_b32 acc95, v12 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=7 mb=0 vw0 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7_BM0_VW0: /// r7 mb0 vw0 +s_mov_b32 s8, 0 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc16 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc32 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc48 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc64 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc80 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc96 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v13, acc112 // glvw 7 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc0, v7 +v_accvgpr_write_b32 acc16, v8 +v_accvgpr_write_b32 acc32, v9 +v_accvgpr_write_b32 acc48, v10 +v_accvgpr_write_b32 acc64, v11 +v_accvgpr_write_b32 acc80, v12 +v_accvgpr_write_b32 acc96, v13 +v_accvgpr_read_b32 v7, acc20 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc36 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc52 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc68 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc84 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc100 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v13, acc116 // glvw 7 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc4, v7 +v_accvgpr_write_b32 acc20, v8 +v_accvgpr_write_b32 acc36, v9 +v_accvgpr_write_b32 acc52, v10 +v_accvgpr_write_b32 acc68, v11 +v_accvgpr_write_b32 acc84, v12 +v_accvgpr_write_b32 acc100, v13 +v_accvgpr_read_b32 v7, acc24 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc40 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc56 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc72 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc88 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc104 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v13, acc120 // glvw 7 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc8, v7 +v_accvgpr_write_b32 acc24, v8 +v_accvgpr_write_b32 acc40, v9 +v_accvgpr_write_b32 acc56, v10 +v_accvgpr_write_b32 acc72, v11 +v_accvgpr_write_b32 acc88, v12 +v_accvgpr_write_b32 acc104, v13 +v_accvgpr_read_b32 v7, acc28 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc44 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc60 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc76 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc92 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc108 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v13, acc124 // glvw 7 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc12, v7 +v_accvgpr_write_b32 acc28, v8 +v_accvgpr_write_b32 acc44, v9 +v_accvgpr_write_b32 acc60, v10 +v_accvgpr_write_b32 acc76, v11 +v_accvgpr_write_b32 acc92, v12 +v_accvgpr_write_b32 acc108, v13 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=7 mb=0 vw1 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7_BM0_VW1: /// r7 mb0 vw1 +s_mov_b32 s8, 1 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc17 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc33 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc49 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc65 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc81 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc97 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v13, acc113 // glvw 7 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc1, v7 +v_accvgpr_write_b32 acc17, v8 +v_accvgpr_write_b32 acc33, v9 +v_accvgpr_write_b32 acc49, v10 +v_accvgpr_write_b32 acc65, v11 +v_accvgpr_write_b32 acc81, v12 +v_accvgpr_write_b32 acc97, v13 +v_accvgpr_read_b32 v7, acc21 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc37 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc53 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc69 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc85 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc101 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v13, acc117 // glvw 7 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc5, v7 +v_accvgpr_write_b32 acc21, v8 +v_accvgpr_write_b32 acc37, v9 +v_accvgpr_write_b32 acc53, v10 +v_accvgpr_write_b32 acc69, v11 +v_accvgpr_write_b32 acc85, v12 +v_accvgpr_write_b32 acc101, v13 +v_accvgpr_read_b32 v7, acc25 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc41 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc57 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc73 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc89 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc105 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v13, acc121 // glvw 7 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc9, v7 +v_accvgpr_write_b32 acc25, v8 +v_accvgpr_write_b32 acc41, v9 +v_accvgpr_write_b32 acc57, v10 +v_accvgpr_write_b32 acc73, v11 +v_accvgpr_write_b32 acc89, v12 +v_accvgpr_write_b32 acc105, v13 +v_accvgpr_read_b32 v7, acc29 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc45 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc61 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc77 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc93 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc109 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v13, acc125 // glvw 7 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc13, v7 +v_accvgpr_write_b32 acc29, v8 +v_accvgpr_write_b32 acc45, v9 +v_accvgpr_write_b32 acc61, v10 +v_accvgpr_write_b32 acc77, v11 +v_accvgpr_write_b32 acc93, v12 +v_accvgpr_write_b32 acc109, v13 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=7 mb=0 vw2 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7_BM0_VW2: /// r7 mb0 vw2 +s_mov_b32 s8, 2 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc18 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc34 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc50 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc66 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc82 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc98 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v13, acc114 // glvw 7 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc2, v7 +v_accvgpr_write_b32 acc18, v8 +v_accvgpr_write_b32 acc34, v9 +v_accvgpr_write_b32 acc50, v10 +v_accvgpr_write_b32 acc66, v11 +v_accvgpr_write_b32 acc82, v12 +v_accvgpr_write_b32 acc98, v13 +v_accvgpr_read_b32 v7, acc22 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc38 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc54 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc70 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc86 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc102 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v13, acc118 // glvw 7 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc6, v7 +v_accvgpr_write_b32 acc22, v8 +v_accvgpr_write_b32 acc38, v9 +v_accvgpr_write_b32 acc54, v10 +v_accvgpr_write_b32 acc70, v11 +v_accvgpr_write_b32 acc86, v12 +v_accvgpr_write_b32 acc102, v13 +v_accvgpr_read_b32 v7, acc26 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc42 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc58 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc74 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc90 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc106 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v13, acc122 // glvw 7 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc10, v7 +v_accvgpr_write_b32 acc26, v8 +v_accvgpr_write_b32 acc42, v9 +v_accvgpr_write_b32 acc58, v10 +v_accvgpr_write_b32 acc74, v11 +v_accvgpr_write_b32 acc90, v12 +v_accvgpr_write_b32 acc106, v13 +v_accvgpr_read_b32 v7, acc30 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc46 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc62 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc78 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc94 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc110 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v13, acc126 // glvw 7 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc14, v7 +v_accvgpr_write_b32 acc30, v8 +v_accvgpr_write_b32 acc46, v9 +v_accvgpr_write_b32 acc62, v10 +v_accvgpr_write_b32 acc78, v11 +v_accvgpr_write_b32 acc94, v12 +v_accvgpr_write_b32 acc110, v13 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + + +/******************************************/ +/* shift d1 r=7 mb=0 vw3 */ +/******************************************/ +label_ShiftVectorComponents1_GLVW7_BM0_VW3: /// r7 mb0 vw3 +s_mov_b32 s8, 3 +v_cmpx_eq_u32 s[8:9], v6, s8 // is thread in edge glvw region +v_and_b32 v0, 63, v[vgprSerial] // permute register between threads +v_lshlrev_b32 v0, 2, v0 // permute register between threads +v_accvgpr_read_b32 v7, acc19 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v8, acc35 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v9, acc51 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v10, acc67 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v11, acc83 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v12, acc99 // glvw 7 mb 0 tt1 0 r 0 +v_accvgpr_read_b32 v13, acc115 // glvw 7 mb 0 tt1 0 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc3, v7 +v_accvgpr_write_b32 acc19, v8 +v_accvgpr_write_b32 acc35, v9 +v_accvgpr_write_b32 acc51, v10 +v_accvgpr_write_b32 acc67, v11 +v_accvgpr_write_b32 acc83, v12 +v_accvgpr_write_b32 acc99, v13 +v_accvgpr_read_b32 v7, acc23 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v8, acc39 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v9, acc55 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v10, acc71 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v11, acc87 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v12, acc103 // glvw 7 mb 0 tt1 1 r 0 +v_accvgpr_read_b32 v13, acc119 // glvw 7 mb 0 tt1 1 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc7, v7 +v_accvgpr_write_b32 acc23, v8 +v_accvgpr_write_b32 acc39, v9 +v_accvgpr_write_b32 acc55, v10 +v_accvgpr_write_b32 acc71, v11 +v_accvgpr_write_b32 acc87, v12 +v_accvgpr_write_b32 acc103, v13 +v_accvgpr_read_b32 v7, acc27 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v8, acc43 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v9, acc59 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v10, acc75 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v11, acc91 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v12, acc107 // glvw 7 mb 0 tt1 2 r 0 +v_accvgpr_read_b32 v13, acc123 // glvw 7 mb 0 tt1 2 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc11, v7 +v_accvgpr_write_b32 acc27, v8 +v_accvgpr_write_b32 acc43, v9 +v_accvgpr_write_b32 acc59, v10 +v_accvgpr_write_b32 acc75, v11 +v_accvgpr_write_b32 acc91, v12 +v_accvgpr_write_b32 acc107, v13 +v_accvgpr_read_b32 v7, acc31 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v8, acc47 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v9, acc63 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v10, acc79 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v11, acc95 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v12, acc111 // glvw 7 mb 0 tt1 3 r 0 +v_accvgpr_read_b32 v13, acc127 // glvw 7 mb 0 tt1 3 r 0 +s_nop 1 // v_accvgpr read vgpr after write vgpr: 2 wait states +v_accvgpr_write_b32 acc15, v7 +v_accvgpr_write_b32 acc31, v8 +v_accvgpr_write_b32 acc47, v9 +v_accvgpr_write_b32 acc63, v10 +v_accvgpr_write_b32 acc79, v11 +v_accvgpr_write_b32 acc95, v12 +v_accvgpr_write_b32 acc111, v13 +s_mov_b64 s[8:9], 0xFFFFFFFFFFFFFFFF // to restore all threads active +s_or_saveexec_b64 vcc, s[8:9] // all threads active + +/* no shifting */ +s_branch label_ShiftVectorComponents1_GLVW0 + +label_ShiftVectorComponents1_GLVW0: /// end shift0 + +/* not-LocalSplitU: global write indices */ +/* computeStoreVgprs */ +v_lshrrev_b32 v4, 6, v[vgprSerial] // 4 = Serial / 64 +v_lshrrev_b32 v5, 1, v4 // 5 = 4 / 2 +v_mul_lo_u32 v5, 0x10, v5 // wave coordination offset 1 +v_and_b32 v1, 63, v[vgprSerial] // v1 = v[vgprSerial] % 64 +v_lshrrev_b32 v1, 4, v1 // 1 = 1 / 16 +v_lshlrev_b32 v1, 2, v1 // thread0 * continuous_output +v_add_lshl_u32 v1, v5, v1, 3 // coordination 1 = vwB *(wave_id1 + tid1) +v_mul_lo_u32 v2, v1, s[sgprStrideC1J] // offset 1 +v_mul_lo_u32 v3, v1, s[sgprStrideD1J] // offset 1 +v_and_b32 v0, 1, v4 // v0 = v4 % 2 +v_mul_lo_u32 v0, 0x10, v0 // wave coordination offset 0 +v_and_b32 v5, 15, v[vgprSerial] // v5 = v[vgprSerial] % 16 +v_add_lshl_u32 v0, v5, v0, 2 // coordination 0 = vwA * (wave_id0 + tid0) +s_mul_i32 s8, 128, s[sgprWorkGroup0] // wgp0 * MT0 +v_add_u32 v0, s8, v0 // coord 0 = (tid0/MI_m)*4 + waveG0*MIB_m + MT0*SG0 +s_mul_i32 s8, 256, s[sgprWorkGroup1] // wgp1 * MT1 +v_add_u32 v1, s8, v1 // coord 1 = (tid0%MI_m) + waveG1*MIB_n + MT1*SG1 + +/* not-LocalSplitU: global write */ + +/******************************************/ +/* Global Write Elements */ +/******************************************/ +s_cmp_eq_u64 s[sgprAddressFlags:sgprAddressFlags+1], 0x0 // Check for synchronizer +s_cbranch_scc0 label_GSU // Branch to stream-k store code +s_cmp_eq_u32 s[sgprskTiles], 1 // split == 1 ? +s_cbranch_scc1 label_GSU // branch if split == 1 +label_GW_B0: +label_GW_B0_FD0: +s_and_b32 s64, 127, s[sgprSizeI] // s64 = s[sgprSizeI] % 128 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups0] +s_cmp_ge_u32 s[sgprWorkGroup0], s65 // wg0 >= nwg0-1 ? +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B0_FD0_VW4_Else // jump if edges required +s_and_b32 s64, 255, s[sgprSizeJ] // s64 = s[sgprSizeJ] % 256 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups1] +s_cmp_ge_u32 s[sgprWorkGroup1], s65 // wg1 >= nwg1-1 +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B0_FD0_VW4_Then // jump if edges required +label_GW_B0_FD0_VW4_NonEdge: + +/* edge=0, allocate 2 sgpr. perBatchTmpS=2 perBatchMaskS=0 perElementMaskS=0 elementsPerBatch=60 */ +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 factorDim=0 */ + +/******************************************/ +/* Global Write Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_lshl_u32 v7, v3, v0, 2 // optSingleColVgpr scaleToBpe: sharedAddrVgpr <- cinRowPtr + coord0, scaled by BPE. BSHERE:coord0=0, coord0Vgpr=0 (multiple bpe) +v_accvgpr_read_b32 v[vgprValuC+12], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+13], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+14], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+15], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+16], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+17], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+18], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+19], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+20], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+21], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+22], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+23], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+24], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+25], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+26], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+27], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+28], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+29], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+30], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+31], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+32], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+33], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+34], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+35], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+36], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+37], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+38], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+39], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+40], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+41], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+42], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+43], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+44], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+45], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+46], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+47], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+48], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+49], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+50], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+51], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+52], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+53], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+54], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+55], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+56], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+57], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+58], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+59], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+60], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+61], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+62], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+63], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+64], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+65], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+66], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+67], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+68], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+69], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+70], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+71], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+72], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+73], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+74], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+75], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+76], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+77], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+78], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+79], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+80], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+81], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+82], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+83], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+84], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+85], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+86], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+87], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+88], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+89], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+90], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+91], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+92], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+93], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+94], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+95], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+96], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+97], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+98], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+99], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+100], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+101], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+102], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+103], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+104], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+105], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+106], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+107], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+108], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+109], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+110], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+111], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+112], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+113], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+114], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+115], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+116], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+117], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+118], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+119], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+120], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+121], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+122], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+123], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+124], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+125], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+126], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+127], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+128], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+129], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+130], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+131], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+132], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+133], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+134], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+135], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+136], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+137], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+138], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+139], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ + +/* apply mask, calc new C and issue writes */ +buffer_store_dwordx4 v[12:15], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[16:19], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[20:23], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[24:27], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[28:31], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[32:35], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[36:39], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[40:43], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[44:47], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[48:51], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[52:55], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[56:59], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[60:63], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[64:67], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[68:71], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[72:75], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[76:79], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[80:83], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[84:87], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[88:91], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[92:95], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[96:99], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[100:103], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[104:107], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[108:111], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[112:115], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[116:119], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[120:123], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[124:127], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[128:131], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[132:135], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_lshl_b32 s8, s[sgprStrideD1J], 2 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx4 v[136:139], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End // jump to end +label_GW_B0_FD0_VW4_NonEdgeEnd: +label_GW_B0_FD0_VW4_Then: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=48 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v7, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v7, v6, v7, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v137, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v137, v6, v137, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v139, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v139, v6, v139, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v141, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v143, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v143, v6, v143, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v145, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v145, v6, v145, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v147, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v148, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v149, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v149, v6, v149, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v150, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v151, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v151, v6, v151, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v153, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v154, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v155, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v155, v6, v155, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v156, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v157, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v157, v6, v157, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v159, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v160, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v161, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v161, v6, v161, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v162, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v163, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v163, v6, v163, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v165, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v166, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+8], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+9], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+10], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+11], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+12], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+13], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+14], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+15], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+16], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+17], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+18], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+19], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+20], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+21], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+22], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+23], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+24], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+25], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+26], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+27], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+28], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+29], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+30], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+31], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+32], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+33], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+34], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+35], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+36], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+37], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+38], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+39], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+40], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+41], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+42], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+43], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+44], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+45], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+46], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+47], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+48], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+49], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+50], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+51], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+52], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+53], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+54], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+55], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+56], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+57], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+58], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+59], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+60], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+61], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+62], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+63], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+64], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+65], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+66], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+67], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+68], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+69], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+70], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+71], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+72], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+73], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+74], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+75], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+76], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+77], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+78], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+79], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+80], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+81], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+82], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+83], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+84], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+85], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+86], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+87], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+88], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+89], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+90], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+91], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+92], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+93], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+94], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+95], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+96], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+97], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+98], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+99], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+100], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+101], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+102], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+103], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+104], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+105], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+106], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+107], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+108], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+109], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+110], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+111], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+112], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+113], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+114], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+115], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+116], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+117], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+118], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+119], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+120], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+121], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+122], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+123], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+124], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+125], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+126], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+127], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+128], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+129], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+130], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+131], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+132], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+133], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+134], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+135], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ + +/* apply mask, calc new C and issue writes */ +buffer_store_dwordx4 v[8:11], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[12:15], v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[16:19], v137, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[20:23], v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[24:27], v139, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[28:31], v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[32:35], v141, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[36:39], v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[40:43], v143, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[44:47], v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[48:51], v145, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[52:55], v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[56:59], v147, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[60:63], v148, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[64:67], v149, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[68:71], v150, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[72:75], v151, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[76:79], v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[80:83], v153, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[84:87], v154, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[88:91], v155, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[92:95], v156, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[96:99], v157, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[100:103], v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[104:107], v159, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[108:111], v160, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[112:115], v161, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[116:119], v162, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[120:123], v163, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[124:127], v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[128:131], v165, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dwordx4 v[132:135], v166, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End // jump to end +label_GW_B0_FD0_VW4_Else: +label_GW_B0_FD0_VW1_Else: +label_GW_B0_FD0_VW1_Then: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=122 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw1); (0,0,0,1:vw1); (0,0,0,2:vw1); (0,0,0,3:vw1); (0,0,1,0:vw1); (0,0,1,1:vw1); (0,0,1,2:vw1); (0,0,1,3:vw1); (0,0,2,0:vw1); (0,0,2,1:vw1); (0,0,2,2:vw1); (0,0,2,3:vw1); (0,0,3,0:vw1); (0,0,3,1:vw1); (0,0,3,2:vw1); (0,0,3,3:vw1); (0,0,4,0:vw1); (0,0,4,1:vw1); (0,0,4,2:vw1); (0,0,4,3:vw1); (0,0,5,0:vw1); (0,0,5,1:vw1); (0,0,5,2:vw1); (0,0,5,3:vw1); (0,0,6,0:vw1); (0,0,6,1:vw1); (0,0,6,2:vw1); (0,0,6,3:vw1); (0,0,7,0:vw1); (0,0,7,1:vw1); (0,0,7,2:vw1); (0,0,7,3:vw1); (0,0,8,0:vw1); (0,0,8,1:vw1); (0,0,8,2:vw1); (0,0,8,3:vw1); (0,0,9,0:vw1); (0,0,9,1:vw1); (0,0,9,2:vw1); (0,0,9,3:vw1); (0,0,10,0:vw1); (0,0,10,1:vw1); (0,0,10,2:vw1); (0,0,10,3:vw1); (0,0,11,0:vw1); (0,0,11,1:vw1); (0,0,11,2:vw1); (0,0,11,3:vw1); (0,0,12,0:vw1); (0,0,12,1:vw1); (0,0,12,2:vw1); (0,0,12,3:vw1); (0,0,13,0:vw1); (0,0,13,1:vw1); (0,0,13,2:vw1); (0,0,13,3:vw1); (0,0,14,0:vw1); (0,0,14,1:vw1); (0,0,14,2:vw1); (0,0,14,3:vw1); (0,0,15,0:vw1); (0,0,15,1:vw1); (0,0,15,2:vw1); (0,0,15,3:vw1); (0,0,16,0:vw1); (0,0,16,1:vw1); (0,0,16,2:vw1); (0,0,16,3:vw1); (0,0,17,0:vw1); (0,0,17,1:vw1); (0,0,17,2:vw1); (0,0,17,3:vw1); (0,0,18,0:vw1); (0,0,18,1:vw1); (0,0,18,2:vw1); (0,0,18,3:vw1); (0,0,19,0:vw1); (0,0,19,1:vw1); (0,0,19,2:vw1); (0,0,19,3:vw1); (0,0,20,0:vw1); (0,0,20,1:vw1); (0,0,20,2:vw1); (0,0,20,3:vw1); (0,0,21,0:vw1); (0,0,21,1:vw1); (0,0,21,2:vw1); (0,0,21,3:vw1); (0,0,22,0:vw1); (0,0,22,1:vw1); (0,0,22,2:vw1); (0,0,22,3:vw1); (0,0,23,0:vw1); (0,0,23,1:vw1); (0,0,23,2:vw1); (0,0,23,3:vw1); (0,0,24,0:vw1); (0,0,24,1:vw1); (0,0,24,2:vw1); (0,0,24,3:vw1); (0,0,25,0:vw1); (0,0,25,1:vw1); (0,0,25,2:vw1); (0,0,25,3:vw1); (0,0,26,0:vw1); (0,0,26,1:vw1); (0,0,26,2:vw1); (0,0,26,3:vw1); (0,0,27,0:vw1); (0,0,27,1:vw1); (0,0,27,2:vw1); (0,0,27,3:vw1); (0,0,28,0:vw1); (0,0,28,1:vw1); (0,0,28,2:vw1); (0,0,28,3:vw1); (0,0,29,0:vw1); (0,0,29,1:vw1); (0,0,29,2:vw1); (0,0,29,3:vw1); (0,0,30,0:vw1); (0,0,30,1:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v129, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v129, v6, v129, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v130, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v131, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v131, v6, v131, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v132, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v133, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v133, v6, v133, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v134, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v135, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v135, v6, v135, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v137, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v137, v6, v137, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v139, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v139, v6, v139, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v141, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v143, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v143, v6, v143, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v145, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v145, v6, v145, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v147, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v148, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v149, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v149, v6, v149, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v150, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v151, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v151, v6, v151, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v153, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v154, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v155, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v155, v6, v155, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v156, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v157, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v157, v6, v157, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v159, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v160, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v161, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v161, v6, v161, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v162, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v163, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v163, v6, v163, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v165, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v166, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v167, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v167, v6, v167, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v168, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v168, v6, v168, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v169, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v169, v6, v169, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v170, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v171, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v171, v6, v171, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v172, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v172, v6, v172, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v173, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v173, v6, v173, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v174, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v174, v6, v174, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v175, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v175, v6, v175, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v176, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v177, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v177, v6, v177, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v178, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v178, v6, v178, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v179, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v179, v6, v179, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v180, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v180, v6, v180, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v181, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v181, v6, v181, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v182, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v183, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v183, v6, v183, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v185, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v186, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v186, v6, v186, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v187, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v187, v6, v187, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v188, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v188, v6, v188, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v189, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v189, v6, v189, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v190, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v190, v6, v190, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v191, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v191, v6, v191, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v192, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v192, v6, v192, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v193, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v194, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v194, v6, v194, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v195, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v195, v6, v195, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v196, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v196, v6, v196, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v197, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v197, v6, v197, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v198, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v198, v6, v198, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v199, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v200, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v200, v6, v200, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v201, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v201, v6, v201, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v202, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v202, v6, v202, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v203, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v203, v6, v203, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v204, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v204, v6, v204, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v205, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v206, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v206, v6, v206, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v207, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v207, v6, v207, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v208, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v208, v6, v208, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v209, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v209, v6, v209, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v210, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v210, v6, v210, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v211, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v212, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v212, v6, v212, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v213, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v213, v6, v213, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v214, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v214, v6, v214, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v215, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v215, v6, v215, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v216, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v216, v6, v216, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v217, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v218, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v218, v6, v218, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v219, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v219, v6, v219, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v220, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v220, v6, v220, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v221, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v221, v6, v221, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v222, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v222, v6, v222, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v223, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v224, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v224, v6, v224, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v225, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v225, v6, v225, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v226, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v226, v6, v226, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v227, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v227, v6, v227, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v228, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v228, v6, v228, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v229, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v230, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v230, v6, v230, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v231, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v231, v6, v231, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v232, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v232, v6, v232, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v233, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v233, v6, v233, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v234, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v234, v6, v234, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v235, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v235, v6, v235, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v236, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v236, v6, v236, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v237, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v237, v6, v237, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v238, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v238, v6, v238, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v239, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v239, v6, v239, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v240, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v240, v6, v240, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v241, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v241, v6, v241, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v242, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v242, v6, v242, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v243, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v243, v6, v243, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v244, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v244, v6, v244, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v245, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v245, v6, v245, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v246, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v246, v6, v246, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v247, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v247, v6, v247, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v248, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v248, v6, v248, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v249, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v249, v6, v249, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v250, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v250, v6, v250, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v251, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v251, v6, v251, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+8], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+9], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+10], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+11], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+12], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+13], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+14], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+15], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+16], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+17], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+18], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+19], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+20], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+21], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+22], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+23], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+24], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+25], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+26], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+27], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+28], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+29], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+30], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+31], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+32], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+33], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+34], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+35], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+36], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+37], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+38], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+39], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+40], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+41], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+42], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+43], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+44], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+45], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+46], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+47], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+48], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+49], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+50], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+51], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+52], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+53], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+54], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+55], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+56], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+57], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+58], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+59], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+60], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+61], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+62], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+63], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+64], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+65], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+66], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+67], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+68], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+69], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+70], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+71], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+72], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+73], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+74], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+75], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+76], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+77], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+78], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+79], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+80], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+81], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+82], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+83], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+84], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+85], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+86], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+87], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+88], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+89], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+90], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+91], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+92], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+93], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+94], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+95], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+96], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+97], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+98], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+99], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+100], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+101], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+102], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+103], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+104], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+105], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+106], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+107], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+108], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+109], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+110], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+111], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+112], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+113], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+114], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+115], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+116], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+117], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+118], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+119], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+120], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+121], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+122], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+123], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+124], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+125], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+126], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+127], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+128], acc103 // copy acc to vreg[121] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 0, 2), (0, 0, 0, 3), (0, 0, 1, 0), (0, 0, 1, 1), (0, 0, 1, 2), (0, 0, 1, 3), (0, 0, 2, 0), (0, 0, 2, 1), (0, 0, 2, 2), (0, 0, 2, 3), (0, 0, 3, 0), (0, 0, 3, 1), (0, 0, 3, 2), (0, 0, 3, 3), (0, 0, 4, 0), (0, 0, 4, 1), (0, 0, 4, 2), (0, 0, 4, 3), (0, 0, 5, 0), (0, 0, 5, 1), (0, 0, 5, 2), (0, 0, 5, 3), (0, 0, 6, 0), (0, 0, 6, 1), (0, 0, 6, 2), (0, 0, 6, 3), (0, 0, 7, 0), (0, 0, 7, 1), (0, 0, 7, 2), (0, 0, 7, 3), (0, 0, 8, 0), (0, 0, 8, 1), (0, 0, 8, 2), (0, 0, 8, 3), (0, 0, 9, 0), (0, 0, 9, 1), (0, 0, 9, 2), (0, 0, 9, 3), (0, 0, 10, 0), (0, 0, 10, 1), (0, 0, 10, 2), (0, 0, 10, 3), (0, 0, 11, 0), (0, 0, 11, 1), (0, 0, 11, 2), (0, 0, 11, 3), (0, 0, 12, 0), (0, 0, 12, 1), (0, 0, 12, 2), (0, 0, 12, 3), (0, 0, 13, 0), (0, 0, 13, 1), (0, 0, 13, 2), (0, 0, 13, 3), (0, 0, 14, 0), (0, 0, 14, 1), (0, 0, 14, 2), (0, 0, 14, 3), (0, 0, 15, 0), (0, 0, 15, 1), (0, 0, 15, 2), (0, 0, 15, 3), (0, 0, 16, 0), (0, 0, 16, 1), (0, 0, 16, 2), (0, 0, 16, 3), (0, 0, 17, 0), (0, 0, 17, 1), (0, 0, 17, 2), (0, 0, 17, 3), (0, 0, 18, 0), (0, 0, 18, 1), (0, 0, 18, 2), (0, 0, 18, 3), (0, 0, 19, 0), (0, 0, 19, 1), (0, 0, 19, 2), (0, 0, 19, 3), (0, 0, 20, 0), (0, 0, 20, 1), (0, 0, 20, 2), (0, 0, 20, 3), (0, 0, 21, 0), (0, 0, 21, 1), (0, 0, 21, 2), (0, 0, 21, 3), (0, 0, 22, 0), (0, 0, 22, 1), (0, 0, 22, 2), (0, 0, 22, 3), (0, 0, 23, 0), (0, 0, 23, 1), (0, 0, 23, 2), (0, 0, 23, 3), (0, 0, 24, 0), (0, 0, 24, 1), (0, 0, 24, 2), (0, 0, 24, 3), (0, 0, 25, 0), (0, 0, 25, 1), (0, 0, 25, 2), (0, 0, 25, 3), (0, 0, 26, 0), (0, 0, 26, 1), (0, 0, 26, 2), (0, 0, 26, 3), (0, 0, 27, 0), (0, 0, 27, 1), (0, 0, 27, 2), (0, 0, 27, 3), (0, 0, 28, 0), (0, 0, 28, 1), (0, 0, 28, 2), (0, 0, 28, 3), (0, 0, 29, 0), (0, 0, 29, 1), (0, 0, 29, 2), (0, 0, 29, 3), (0, 0, 30, 0), (0, 0, 30, 1)] */ + +/* apply mask, calc new C and issue writes */ +buffer_store_dword v7, v129, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v8, v130, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v9, v131, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v10, v132, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v11, v133, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v12, v134, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v13, v135, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v14, v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v15, v137, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v16, v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v17, v139, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v18, v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v19, v141, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v20, v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v21, v143, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v22, v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v23, v145, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v24, v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v25, v147, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v26, v148, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v27, v149, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v28, v150, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v29, v151, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v30, v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v31, v153, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v32, v154, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v33, v155, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v34, v156, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v35, v157, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v36, v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v37, v159, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v38, v160, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v39, v161, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v40, v162, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v41, v163, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v42, v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v43, v165, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v44, v166, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v45, v167, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v46, v168, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v47, v169, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v48, v170, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v49, v171, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v50, v172, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v51, v173, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v52, v174, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v53, v175, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v54, v176, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v55, v177, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v56, v178, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v57, v179, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v58, v180, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v59, v181, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v60, v182, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v61, v183, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v62, v185, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v63, v186, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v64, v187, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v65, v188, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v66, v189, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v67, v190, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v68, v191, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v69, v192, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v70, v193, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v71, v194, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v72, v195, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v73, v196, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v74, v197, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v75, v198, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v76, v199, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v77, v200, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v78, v201, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v79, v202, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v80, v203, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v81, v204, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v82, v205, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v83, v206, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v84, v207, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v85, v208, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v86, v209, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v87, v210, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v88, v211, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v89, v212, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v90, v213, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v91, v214, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v92, v215, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v93, v216, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v94, v217, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v95, v218, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v96, v219, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v97, v220, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v98, v221, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v99, v222, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v100, v223, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v101, v224, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v102, v225, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v103, v226, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v104, v227, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v105, v228, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v106, v229, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v107, v230, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v108, v231, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v109, v232, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v110, v233, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v111, v234, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v112, v235, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v113, v236, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v114, v237, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v115, v238, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v116, v239, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v117, v240, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v118, v241, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v119, v242, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v120, v243, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v121, v244, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v122, v245, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v123, v246, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v124, v247, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v125, v248, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v126, v249, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v127, v250, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v128, v251, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #1 (d1,d0,vc1,vc0) = */ +/* (0,0,30,2:vw1); (0,0,30,3:vw1); (0,0,31,0:vw1); (0,0,31,1:vw1); (0,0,31,2:vw1); (0,0,31,3:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,30,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v13, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v13, v6, v13, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v14, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v14, v6, v14, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v15, v3, v0, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v15, v6, v15, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v16, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v16, v6, v16, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v17, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v17, v6, v17, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v18, v3, v4, 2 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v18, v6, v18, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+8], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+9], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+10], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+11], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+12], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 30, 2), (0, 0, 30, 3), (0, 0, 31, 0), (0, 0, 31, 1), (0, 0, 31, 2), (0, 0, 31, 3)] */ + +/* apply mask, calc new C and issue writes */ +buffer_store_dword v7, v13, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v8, v14, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v9, v15, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v10, v16, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v11, v17, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +buffer_store_dword v12, v18, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End // jump to end +label_GW_End: +s_getpc_b64 s[64:65] // addr of next instr +s_add_i32 s66, label_KernelEnd, 4 // target branch offset +s_add_u32 s64, s64, s66 // add target branch offset +s_addc_u32 s65, s65, 0 // add high and carry +s_setpc_b64 s[64:65] // branch to label_KernelEnd +label_GSU: +s_cmp_eq_u32 s[sgprStreamKLocalStart], 0 // does wg start tile? +s_cbranch_scc1 label_NoBranch_2G3LC8VCGIZD1EUX // Only branch on scc0 +s_getpc_b64 s[68:69] // addr of next instr +s_add_i32 s70, label_SK_Partials_1, 4 // target branch offset +s_add_u32 s68, s68, s70 // add target branch offset +s_addc_u32 s69, s69, 0 // add high and carry +s_setpc_b64 s[68:69] // branch to label_SK_Partials_1 +label_NoBranch_2G3LC8VCGIZD1EUX: +s_cmp_eq_u32 s[sgprStreamKLocalEnd], s[sgprItersPerTile] // does wg finish tile? +s_cbranch_scc1 label_SK_Store // Branch if started and finished tile, go to regular store code +s_add_u32 s8, s[sgprStreamKIdx], 1 // input partial tile index +s_mul_hi_u32 s65, s[sgprStreamKIterEnd], s[sgprMagicNumberItersPerTile] // s_magic mul, div alg 2 +s_lshr_b32 s66, s[sgprMagicShiftItersPerTile], 31 // tmpS = extract abit +s_mul_i32 s64, s[sgprStreamKIterEnd], s66 // s_magic mul, div alg 2 +s_add_u32 s64, s64, s65 +s_and_b32 s66, s[sgprMagicShiftItersPerTile], 2147483647 // tmpS = remove abit to final shift +s_lshr_b32 s64, s64, s66 // sMagicDiv Alg 2 +s_mul_i32 s64, s64, s[sgprItersPerTile] // start iteration of partial tile +s_sub_u32 s9, s[sgprStreamKIterEnd], s64 // calc iterations completed by this WG +label_SK_Fixup: +s_lshl_b32 s64, s8, 2 // flag offset based on CTA index +s_load_dword s66, s[sgprAddressFlags:sgprAddressFlags+1], s64 glc // get flag +s_waitcnt lgkmcnt(0) // wait for flag load +s_cmp_eq_u32 s66, 1 // check if ready +s_cbranch_scc0 label_SK_Fixup // if flag not set, wait and check again +s_barrier // wait for all workgroups before resetting flag +v_readfirstlane_b32 s66, v[vgprSerial] // Wave 0 updates flags +s_cmp_eq_u32 s66, 0 // Check for wave 0 +s_cbranch_scc0 label_SK_SkipFlagReset // Skip flag reset +s_store_dword s66, s[sgprAddressFlags:sgprAddressFlags+1], s64 glc // reset flag +label_SK_SkipFlagReset: +label_Fixup_E0: + +/* edge=0, allocate 2 sgpr. perBatchTmpS=2 perBatchMaskS=0 perElementMaskS=0 elementsPerBatch=28 */ +s_mov_b64 s[sgprSrdWS+0:sgprSrdWS+0+1], s[sgprAddressWS+0:sgprAddressWS+0+1] // init SRD base address +s_mov_b32 s[sgprSrdWS+2], BufferOOB +s_mov_b32 s[sgprSrdWS+3], Srd127_96 // Set bits 127_96 in post-loop SRD + +s_mul_i32 s58, 0x20000, s8 // Offset to correct partials tile +s_add_u32 s[sgprSrdWS+0], s[sgprSrdWS+0], s58 // add lo to SRD +s_addc_u32 s[sgprSrdWS+1], s[sgprSrdWS+1], 0 // add hi to SRD +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 */ + +/******************************************/ +/* Fixup Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_lshlrev_b32 v8, 4, v[vgprSerial] // v8 = v[vgprSerial] * 16 +s_mov_b32 s58, 0 // Init sgpr offset +buffer_load_dwordx4 v[124:127], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[128:131], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[132:135], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[136:139], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[140:143], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[144:147], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[148:151], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[152:155], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[156:159], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[160:163], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[164:167], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[168:171], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[172:175], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[176:179], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[180:183], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[188:191], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[192:195], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[196:199], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[200:203], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[204:207], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[208:211], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[212:215], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[216:219], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[220:223], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[224:227], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[228:231], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[232:235], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[236:239], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +v_accvgpr_read_b32 v[vgprValuC+12], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+13], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+14], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+15], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+16], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+17], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+18], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+19], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+20], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+21], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+22], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+23], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+24], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+25], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+26], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+27], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+28], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+29], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+30], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+31], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+32], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+33], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+34], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+35], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+36], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+37], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+38], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+39], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+40], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+41], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+42], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+43], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+44], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+45], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+46], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+47], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+48], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+49], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+50], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+51], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+52], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+53], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+54], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+55], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+56], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+57], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+58], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+59], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+60], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+61], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+62], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+63], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+64], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+65], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+66], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+67], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+68], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+69], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+70], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+71], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+72], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+73], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+74], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+75], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+76], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+77], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+78], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+79], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+80], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+81], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+82], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+83], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+84], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+85], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+86], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+87], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+88], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+89], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+90], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+91], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+92], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+93], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+94], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+95], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+96], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+97], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+98], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+99], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+100], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+101], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+102], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+103], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+104], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+105], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+106], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+107], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+108], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+109], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+110], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+111], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+112], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+113], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+114], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+115], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+116], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+117], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+118], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+119], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+120], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+121], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+122], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+123], acc63 // copy acc to vreg[111] +s_nop 1 // 2 wait states required before reading vgpr + +/* apply mask, calc new C and issue writes */ + +s_waitcnt vmcnt(27) // wait C (interleaved) 27 = 28 - 0 + 0 - 1 +v_add_f32 v[vgprValuC+12], v[vgprValuC+12], v124 // accum partials +v_add_f32 v[vgprValuC+13], v[vgprValuC+13], v125 // accum partials +v_add_f32 v[vgprValuC+14], v[vgprValuC+14], v126 // accum partials +v_add_f32 v[vgprValuC+15], v[vgprValuC+15], v127 // accum partials + +s_waitcnt vmcnt(26) // wait C (interleaved) 26 = 28 - 1 + 0 - 1 +v_add_f32 v[vgprValuC+16], v[vgprValuC+16], v128 // accum partials +v_add_f32 v[vgprValuC+17], v[vgprValuC+17], v129 // accum partials +v_add_f32 v[vgprValuC+18], v[vgprValuC+18], v130 // accum partials +v_add_f32 v[vgprValuC+19], v[vgprValuC+19], v131 // accum partials + +s_waitcnt vmcnt(25) // wait C (interleaved) 25 = 28 - 2 + 0 - 1 +v_add_f32 v[vgprValuC+20], v[vgprValuC+20], v132 // accum partials +v_add_f32 v[vgprValuC+21], v[vgprValuC+21], v133 // accum partials +v_add_f32 v[vgprValuC+22], v[vgprValuC+22], v134 // accum partials +v_add_f32 v[vgprValuC+23], v[vgprValuC+23], v135 // accum partials + +s_waitcnt vmcnt(24) // wait C (interleaved) 24 = 28 - 3 + 0 - 1 +v_add_f32 v[vgprValuC+24], v[vgprValuC+24], v136 // accum partials +v_add_f32 v[vgprValuC+25], v[vgprValuC+25], v137 // accum partials +v_add_f32 v[vgprValuC+26], v[vgprValuC+26], v138 // accum partials +v_add_f32 v[vgprValuC+27], v[vgprValuC+27], v139 // accum partials + +s_waitcnt vmcnt(23) // wait C (interleaved) 23 = 28 - 4 + 0 - 1 +v_add_f32 v[vgprValuC+28], v[vgprValuC+28], v140 // accum partials +v_add_f32 v[vgprValuC+29], v[vgprValuC+29], v141 // accum partials +v_add_f32 v[vgprValuC+30], v[vgprValuC+30], v142 // accum partials +v_add_f32 v[vgprValuC+31], v[vgprValuC+31], v143 // accum partials + +s_waitcnt vmcnt(22) // wait C (interleaved) 22 = 28 - 5 + 0 - 1 +v_add_f32 v[vgprValuC+32], v[vgprValuC+32], v144 // accum partials +v_add_f32 v[vgprValuC+33], v[vgprValuC+33], v145 // accum partials +v_add_f32 v[vgprValuC+34], v[vgprValuC+34], v146 // accum partials +v_add_f32 v[vgprValuC+35], v[vgprValuC+35], v147 // accum partials + +s_waitcnt vmcnt(21) // wait C (interleaved) 21 = 28 - 6 + 0 - 1 +v_add_f32 v[vgprValuC+36], v[vgprValuC+36], v148 // accum partials +v_add_f32 v[vgprValuC+37], v[vgprValuC+37], v149 // accum partials +v_add_f32 v[vgprValuC+38], v[vgprValuC+38], v150 // accum partials +v_add_f32 v[vgprValuC+39], v[vgprValuC+39], v151 // accum partials + +s_waitcnt vmcnt(20) // wait C (interleaved) 20 = 28 - 7 + 0 - 1 +v_add_f32 v[vgprValuC+40], v[vgprValuC+40], v152 // accum partials +v_add_f32 v[vgprValuC+41], v[vgprValuC+41], v153 // accum partials +v_add_f32 v[vgprValuC+42], v[vgprValuC+42], v154 // accum partials +v_add_f32 v[vgprValuC+43], v[vgprValuC+43], v155 // accum partials + +s_waitcnt vmcnt(19) // wait C (interleaved) 19 = 28 - 8 + 0 - 1 +v_add_f32 v[vgprValuC+44], v[vgprValuC+44], v156 // accum partials +v_add_f32 v[vgprValuC+45], v[vgprValuC+45], v157 // accum partials +v_add_f32 v[vgprValuC+46], v[vgprValuC+46], v158 // accum partials +v_add_f32 v[vgprValuC+47], v[vgprValuC+47], v159 // accum partials + +s_waitcnt vmcnt(18) // wait C (interleaved) 18 = 28 - 9 + 0 - 1 +v_add_f32 v[vgprValuC+48], v[vgprValuC+48], v160 // accum partials +v_add_f32 v[vgprValuC+49], v[vgprValuC+49], v161 // accum partials +v_add_f32 v[vgprValuC+50], v[vgprValuC+50], v162 // accum partials +v_add_f32 v[vgprValuC+51], v[vgprValuC+51], v163 // accum partials + +s_waitcnt vmcnt(17) // wait C (interleaved) 17 = 28 - 10 + 0 - 1 +v_add_f32 v[vgprValuC+52], v[vgprValuC+52], v164 // accum partials +v_add_f32 v[vgprValuC+53], v[vgprValuC+53], v165 // accum partials +v_add_f32 v[vgprValuC+54], v[vgprValuC+54], v166 // accum partials +v_add_f32 v[vgprValuC+55], v[vgprValuC+55], v167 // accum partials + +s_waitcnt vmcnt(16) // wait C (interleaved) 16 = 28 - 11 + 0 - 1 +v_add_f32 v[vgprValuC+56], v[vgprValuC+56], v168 // accum partials +v_add_f32 v[vgprValuC+57], v[vgprValuC+57], v169 // accum partials +v_add_f32 v[vgprValuC+58], v[vgprValuC+58], v170 // accum partials +v_add_f32 v[vgprValuC+59], v[vgprValuC+59], v171 // accum partials + +s_waitcnt vmcnt(15) // wait C (interleaved) 15 = 28 - 12 + 0 - 1 +v_add_f32 v[vgprValuC+60], v[vgprValuC+60], v172 // accum partials +v_add_f32 v[vgprValuC+61], v[vgprValuC+61], v173 // accum partials +v_add_f32 v[vgprValuC+62], v[vgprValuC+62], v174 // accum partials +v_add_f32 v[vgprValuC+63], v[vgprValuC+63], v175 // accum partials + +s_waitcnt vmcnt(14) // wait C (interleaved) 14 = 28 - 13 + 0 - 1 +v_add_f32 v[vgprValuC+64], v[vgprValuC+64], v176 // accum partials +v_add_f32 v[vgprValuC+65], v[vgprValuC+65], v177 // accum partials +v_add_f32 v[vgprValuC+66], v[vgprValuC+66], v178 // accum partials +v_add_f32 v[vgprValuC+67], v[vgprValuC+67], v179 // accum partials + +s_waitcnt vmcnt(13) // wait C (interleaved) 13 = 28 - 14 + 0 - 1 +v_add_f32 v[vgprValuC+68], v[vgprValuC+68], v180 // accum partials +v_add_f32 v[vgprValuC+69], v[vgprValuC+69], v181 // accum partials +v_add_f32 v[vgprValuC+70], v[vgprValuC+70], v182 // accum partials +v_add_f32 v[vgprValuC+71], v[vgprValuC+71], v183 // accum partials + +s_waitcnt vmcnt(12) // wait C (interleaved) 12 = 28 - 15 + 0 - 1 +v_add_f32 v[vgprValuC+72], v[vgprValuC+72], v188 // accum partials +v_add_f32 v[vgprValuC+73], v[vgprValuC+73], v189 // accum partials +v_add_f32 v[vgprValuC+74], v[vgprValuC+74], v190 // accum partials +v_add_f32 v[vgprValuC+75], v[vgprValuC+75], v191 // accum partials + +s_waitcnt vmcnt(11) // wait C (interleaved) 11 = 28 - 16 + 0 - 1 +v_add_f32 v[vgprValuC+76], v[vgprValuC+76], v192 // accum partials +v_add_f32 v[vgprValuC+77], v[vgprValuC+77], v193 // accum partials +v_add_f32 v[vgprValuC+78], v[vgprValuC+78], v194 // accum partials +v_add_f32 v[vgprValuC+79], v[vgprValuC+79], v195 // accum partials + +s_waitcnt vmcnt(10) // wait C (interleaved) 10 = 28 - 17 + 0 - 1 +v_add_f32 v[vgprValuC+80], v[vgprValuC+80], v196 // accum partials +v_add_f32 v[vgprValuC+81], v[vgprValuC+81], v197 // accum partials +v_add_f32 v[vgprValuC+82], v[vgprValuC+82], v198 // accum partials +v_add_f32 v[vgprValuC+83], v[vgprValuC+83], v199 // accum partials + +s_waitcnt vmcnt(9) // wait C (interleaved) 9 = 28 - 18 + 0 - 1 +v_add_f32 v[vgprValuC+84], v[vgprValuC+84], v200 // accum partials +v_add_f32 v[vgprValuC+85], v[vgprValuC+85], v201 // accum partials +v_add_f32 v[vgprValuC+86], v[vgprValuC+86], v202 // accum partials +v_add_f32 v[vgprValuC+87], v[vgprValuC+87], v203 // accum partials + +s_waitcnt vmcnt(8) // wait C (interleaved) 8 = 28 - 19 + 0 - 1 +v_add_f32 v[vgprValuC+88], v[vgprValuC+88], v204 // accum partials +v_add_f32 v[vgprValuC+89], v[vgprValuC+89], v205 // accum partials +v_add_f32 v[vgprValuC+90], v[vgprValuC+90], v206 // accum partials +v_add_f32 v[vgprValuC+91], v[vgprValuC+91], v207 // accum partials + +s_waitcnt vmcnt(7) // wait C (interleaved) 7 = 28 - 20 + 0 - 1 +v_add_f32 v[vgprValuC+92], v[vgprValuC+92], v208 // accum partials +v_add_f32 v[vgprValuC+93], v[vgprValuC+93], v209 // accum partials +v_add_f32 v[vgprValuC+94], v[vgprValuC+94], v210 // accum partials +v_add_f32 v[vgprValuC+95], v[vgprValuC+95], v211 // accum partials + +s_waitcnt vmcnt(6) // wait C (interleaved) 6 = 28 - 21 + 0 - 1 +v_add_f32 v[vgprValuC+96], v[vgprValuC+96], v212 // accum partials +v_add_f32 v[vgprValuC+97], v[vgprValuC+97], v213 // accum partials +v_add_f32 v[vgprValuC+98], v[vgprValuC+98], v214 // accum partials +v_add_f32 v[vgprValuC+99], v[vgprValuC+99], v215 // accum partials + +s_waitcnt vmcnt(5) // wait C (interleaved) 5 = 28 - 22 + 0 - 1 +v_add_f32 v[vgprValuC+100], v[vgprValuC+100], v216 // accum partials +v_add_f32 v[vgprValuC+101], v[vgprValuC+101], v217 // accum partials +v_add_f32 v[vgprValuC+102], v[vgprValuC+102], v218 // accum partials +v_add_f32 v[vgprValuC+103], v[vgprValuC+103], v219 // accum partials + +s_waitcnt vmcnt(4) // wait C (interleaved) 4 = 28 - 23 + 0 - 1 +v_add_f32 v[vgprValuC+104], v[vgprValuC+104], v220 // accum partials +v_add_f32 v[vgprValuC+105], v[vgprValuC+105], v221 // accum partials +v_add_f32 v[vgprValuC+106], v[vgprValuC+106], v222 // accum partials +v_add_f32 v[vgprValuC+107], v[vgprValuC+107], v223 // accum partials + +s_waitcnt vmcnt(3) // wait C (interleaved) 3 = 28 - 24 + 0 - 1 +v_add_f32 v[vgprValuC+108], v[vgprValuC+108], v224 // accum partials +v_add_f32 v[vgprValuC+109], v[vgprValuC+109], v225 // accum partials +v_add_f32 v[vgprValuC+110], v[vgprValuC+110], v226 // accum partials +v_add_f32 v[vgprValuC+111], v[vgprValuC+111], v227 // accum partials + +s_waitcnt vmcnt(2) // wait C (interleaved) 2 = 28 - 25 + 0 - 1 +v_add_f32 v[vgprValuC+112], v[vgprValuC+112], v228 // accum partials +v_add_f32 v[vgprValuC+113], v[vgprValuC+113], v229 // accum partials +v_add_f32 v[vgprValuC+114], v[vgprValuC+114], v230 // accum partials +v_add_f32 v[vgprValuC+115], v[vgprValuC+115], v231 // accum partials + +s_waitcnt vmcnt(1) // wait C (interleaved) 1 = 28 - 26 + 0 - 1 +v_add_f32 v[vgprValuC+116], v[vgprValuC+116], v232 // accum partials +v_add_f32 v[vgprValuC+117], v[vgprValuC+117], v233 // accum partials +v_add_f32 v[vgprValuC+118], v[vgprValuC+118], v234 // accum partials +v_add_f32 v[vgprValuC+119], v[vgprValuC+119], v235 // accum partials + +s_waitcnt vmcnt(0) // wait C (interleaved) 0 = 28 - 27 + 0 - 1 +v_add_f32 v[vgprValuC+120], v[vgprValuC+120], v236 // accum partials +v_add_f32 v[vgprValuC+121], v[vgprValuC+121], v237 // accum partials +v_add_f32 v[vgprValuC+122], v[vgprValuC+122], v238 // accum partials +v_add_f32 v[vgprValuC+123], v[vgprValuC+123], v239 // accum partials +v_accvgpr_write_b32 acc0, v[vgprValuC+12] // copy vreg[0] to acc +v_accvgpr_write_b32 acc4, v[vgprValuC+13] // copy vreg[1] to acc +v_accvgpr_write_b32 acc8, v[vgprValuC+14] // copy vreg[2] to acc +v_accvgpr_write_b32 acc12, v[vgprValuC+15] // copy vreg[3] to acc +v_accvgpr_write_b32 acc16, v[vgprValuC+16] // copy vreg[4] to acc +v_accvgpr_write_b32 acc20, v[vgprValuC+17] // copy vreg[5] to acc +v_accvgpr_write_b32 acc24, v[vgprValuC+18] // copy vreg[6] to acc +v_accvgpr_write_b32 acc28, v[vgprValuC+19] // copy vreg[7] to acc +v_accvgpr_write_b32 acc32, v[vgprValuC+20] // copy vreg[8] to acc +v_accvgpr_write_b32 acc36, v[vgprValuC+21] // copy vreg[9] to acc +v_accvgpr_write_b32 acc40, v[vgprValuC+22] // copy vreg[10] to acc +v_accvgpr_write_b32 acc44, v[vgprValuC+23] // copy vreg[11] to acc +v_accvgpr_write_b32 acc48, v[vgprValuC+24] // copy vreg[12] to acc +v_accvgpr_write_b32 acc52, v[vgprValuC+25] // copy vreg[13] to acc +v_accvgpr_write_b32 acc56, v[vgprValuC+26] // copy vreg[14] to acc +v_accvgpr_write_b32 acc60, v[vgprValuC+27] // copy vreg[15] to acc +v_accvgpr_write_b32 acc64, v[vgprValuC+28] // copy vreg[16] to acc +v_accvgpr_write_b32 acc68, v[vgprValuC+29] // copy vreg[17] to acc +v_accvgpr_write_b32 acc72, v[vgprValuC+30] // copy vreg[18] to acc +v_accvgpr_write_b32 acc76, v[vgprValuC+31] // copy vreg[19] to acc +v_accvgpr_write_b32 acc80, v[vgprValuC+32] // copy vreg[20] to acc +v_accvgpr_write_b32 acc84, v[vgprValuC+33] // copy vreg[21] to acc +v_accvgpr_write_b32 acc88, v[vgprValuC+34] // copy vreg[22] to acc +v_accvgpr_write_b32 acc92, v[vgprValuC+35] // copy vreg[23] to acc +v_accvgpr_write_b32 acc96, v[vgprValuC+36] // copy vreg[24] to acc +v_accvgpr_write_b32 acc100, v[vgprValuC+37] // copy vreg[25] to acc +v_accvgpr_write_b32 acc104, v[vgprValuC+38] // copy vreg[26] to acc +v_accvgpr_write_b32 acc108, v[vgprValuC+39] // copy vreg[27] to acc +v_accvgpr_write_b32 acc112, v[vgprValuC+40] // copy vreg[28] to acc +v_accvgpr_write_b32 acc116, v[vgprValuC+41] // copy vreg[29] to acc +v_accvgpr_write_b32 acc120, v[vgprValuC+42] // copy vreg[30] to acc +v_accvgpr_write_b32 acc124, v[vgprValuC+43] // copy vreg[31] to acc +v_accvgpr_write_b32 acc1, v[vgprValuC+44] // copy vreg[32] to acc +v_accvgpr_write_b32 acc5, v[vgprValuC+45] // copy vreg[33] to acc +v_accvgpr_write_b32 acc9, v[vgprValuC+46] // copy vreg[34] to acc +v_accvgpr_write_b32 acc13, v[vgprValuC+47] // copy vreg[35] to acc +v_accvgpr_write_b32 acc17, v[vgprValuC+48] // copy vreg[36] to acc +v_accvgpr_write_b32 acc21, v[vgprValuC+49] // copy vreg[37] to acc +v_accvgpr_write_b32 acc25, v[vgprValuC+50] // copy vreg[38] to acc +v_accvgpr_write_b32 acc29, v[vgprValuC+51] // copy vreg[39] to acc +v_accvgpr_write_b32 acc33, v[vgprValuC+52] // copy vreg[40] to acc +v_accvgpr_write_b32 acc37, v[vgprValuC+53] // copy vreg[41] to acc +v_accvgpr_write_b32 acc41, v[vgprValuC+54] // copy vreg[42] to acc +v_accvgpr_write_b32 acc45, v[vgprValuC+55] // copy vreg[43] to acc +v_accvgpr_write_b32 acc49, v[vgprValuC+56] // copy vreg[44] to acc +v_accvgpr_write_b32 acc53, v[vgprValuC+57] // copy vreg[45] to acc +v_accvgpr_write_b32 acc57, v[vgprValuC+58] // copy vreg[46] to acc +v_accvgpr_write_b32 acc61, v[vgprValuC+59] // copy vreg[47] to acc +v_accvgpr_write_b32 acc65, v[vgprValuC+60] // copy vreg[48] to acc +v_accvgpr_write_b32 acc69, v[vgprValuC+61] // copy vreg[49] to acc +v_accvgpr_write_b32 acc73, v[vgprValuC+62] // copy vreg[50] to acc +v_accvgpr_write_b32 acc77, v[vgprValuC+63] // copy vreg[51] to acc +v_accvgpr_write_b32 acc81, v[vgprValuC+64] // copy vreg[52] to acc +v_accvgpr_write_b32 acc85, v[vgprValuC+65] // copy vreg[53] to acc +v_accvgpr_write_b32 acc89, v[vgprValuC+66] // copy vreg[54] to acc +v_accvgpr_write_b32 acc93, v[vgprValuC+67] // copy vreg[55] to acc +v_accvgpr_write_b32 acc97, v[vgprValuC+68] // copy vreg[56] to acc +v_accvgpr_write_b32 acc101, v[vgprValuC+69] // copy vreg[57] to acc +v_accvgpr_write_b32 acc105, v[vgprValuC+70] // copy vreg[58] to acc +v_accvgpr_write_b32 acc109, v[vgprValuC+71] // copy vreg[59] to acc +v_accvgpr_write_b32 acc113, v[vgprValuC+72] // copy vreg[60] to acc +v_accvgpr_write_b32 acc117, v[vgprValuC+73] // copy vreg[61] to acc +v_accvgpr_write_b32 acc121, v[vgprValuC+74] // copy vreg[62] to acc +v_accvgpr_write_b32 acc125, v[vgprValuC+75] // copy vreg[63] to acc +v_accvgpr_write_b32 acc2, v[vgprValuC+76] // copy vreg[64] to acc +v_accvgpr_write_b32 acc6, v[vgprValuC+77] // copy vreg[65] to acc +v_accvgpr_write_b32 acc10, v[vgprValuC+78] // copy vreg[66] to acc +v_accvgpr_write_b32 acc14, v[vgprValuC+79] // copy vreg[67] to acc +v_accvgpr_write_b32 acc18, v[vgprValuC+80] // copy vreg[68] to acc +v_accvgpr_write_b32 acc22, v[vgprValuC+81] // copy vreg[69] to acc +v_accvgpr_write_b32 acc26, v[vgprValuC+82] // copy vreg[70] to acc +v_accvgpr_write_b32 acc30, v[vgprValuC+83] // copy vreg[71] to acc +v_accvgpr_write_b32 acc34, v[vgprValuC+84] // copy vreg[72] to acc +v_accvgpr_write_b32 acc38, v[vgprValuC+85] // copy vreg[73] to acc +v_accvgpr_write_b32 acc42, v[vgprValuC+86] // copy vreg[74] to acc +v_accvgpr_write_b32 acc46, v[vgprValuC+87] // copy vreg[75] to acc +v_accvgpr_write_b32 acc50, v[vgprValuC+88] // copy vreg[76] to acc +v_accvgpr_write_b32 acc54, v[vgprValuC+89] // copy vreg[77] to acc +v_accvgpr_write_b32 acc58, v[vgprValuC+90] // copy vreg[78] to acc +v_accvgpr_write_b32 acc62, v[vgprValuC+91] // copy vreg[79] to acc +v_accvgpr_write_b32 acc66, v[vgprValuC+92] // copy vreg[80] to acc +v_accvgpr_write_b32 acc70, v[vgprValuC+93] // copy vreg[81] to acc +v_accvgpr_write_b32 acc74, v[vgprValuC+94] // copy vreg[82] to acc +v_accvgpr_write_b32 acc78, v[vgprValuC+95] // copy vreg[83] to acc +v_accvgpr_write_b32 acc82, v[vgprValuC+96] // copy vreg[84] to acc +v_accvgpr_write_b32 acc86, v[vgprValuC+97] // copy vreg[85] to acc +v_accvgpr_write_b32 acc90, v[vgprValuC+98] // copy vreg[86] to acc +v_accvgpr_write_b32 acc94, v[vgprValuC+99] // copy vreg[87] to acc +v_accvgpr_write_b32 acc98, v[vgprValuC+100] // copy vreg[88] to acc +v_accvgpr_write_b32 acc102, v[vgprValuC+101] // copy vreg[89] to acc +v_accvgpr_write_b32 acc106, v[vgprValuC+102] // copy vreg[90] to acc +v_accvgpr_write_b32 acc110, v[vgprValuC+103] // copy vreg[91] to acc +v_accvgpr_write_b32 acc114, v[vgprValuC+104] // copy vreg[92] to acc +v_accvgpr_write_b32 acc118, v[vgprValuC+105] // copy vreg[93] to acc +v_accvgpr_write_b32 acc122, v[vgprValuC+106] // copy vreg[94] to acc +v_accvgpr_write_b32 acc126, v[vgprValuC+107] // copy vreg[95] to acc +v_accvgpr_write_b32 acc3, v[vgprValuC+108] // copy vreg[96] to acc +v_accvgpr_write_b32 acc7, v[vgprValuC+109] // copy vreg[97] to acc +v_accvgpr_write_b32 acc11, v[vgprValuC+110] // copy vreg[98] to acc +v_accvgpr_write_b32 acc15, v[vgprValuC+111] // copy vreg[99] to acc +v_accvgpr_write_b32 acc19, v[vgprValuC+112] // copy vreg[100] to acc +v_accvgpr_write_b32 acc23, v[vgprValuC+113] // copy vreg[101] to acc +v_accvgpr_write_b32 acc27, v[vgprValuC+114] // copy vreg[102] to acc +v_accvgpr_write_b32 acc31, v[vgprValuC+115] // copy vreg[103] to acc +v_accvgpr_write_b32 acc35, v[vgprValuC+116] // copy vreg[104] to acc +v_accvgpr_write_b32 acc39, v[vgprValuC+117] // copy vreg[105] to acc +v_accvgpr_write_b32 acc43, v[vgprValuC+118] // copy vreg[106] to acc +v_accvgpr_write_b32 acc47, v[vgprValuC+119] // copy vreg[107] to acc +v_accvgpr_write_b32 acc51, v[vgprValuC+120] // copy vreg[108] to acc +v_accvgpr_write_b32 acc55, v[vgprValuC+121] // copy vreg[109] to acc +v_accvgpr_write_b32 acc59, v[vgprValuC+122] // copy vreg[110] to acc +v_accvgpr_write_b32 acc63, v[vgprValuC+123] // copy vreg[111] to acc +s_nop 1 // 2 wait states required before reading vgpr +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 */ + +/******************************************/ +/* Fixup Batch #1 (d1,d0,vc1,vc0) = */ +/* (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[28:31], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[32:35], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[36:39], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +s_add_u32 s58, s58, 4096 // Inc sgpr offset +buffer_load_dwordx4 v[40:43], v8, s[sgprSrdWS:sgprSrdWS+3], s58 offen offset:0 // load WS +v_accvgpr_read_b32 v[vgprValuC+12], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+13], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+14], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+15], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+16], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+17], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+18], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+19], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+20], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+21], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+22], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+23], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+24], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+25], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+26], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+27], acc127 // copy acc to vreg[127] +s_nop 1 // 2 wait states required before reading vgpr + +/* apply mask, calc new C and issue writes */ + +s_waitcnt vmcnt(3) // wait C (interleaved) 3 = 4 - 0 + 0 - 1 +v_add_f32 v[vgprValuC+12], v[vgprValuC+12], v28 // accum partials +v_add_f32 v[vgprValuC+13], v[vgprValuC+13], v29 // accum partials +v_add_f32 v[vgprValuC+14], v[vgprValuC+14], v30 // accum partials +v_add_f32 v[vgprValuC+15], v[vgprValuC+15], v31 // accum partials + +s_waitcnt vmcnt(2) // wait C (interleaved) 2 = 4 - 1 + 0 - 1 +v_add_f32 v[vgprValuC+16], v[vgprValuC+16], v32 // accum partials +v_add_f32 v[vgprValuC+17], v[vgprValuC+17], v33 // accum partials +v_add_f32 v[vgprValuC+18], v[vgprValuC+18], v34 // accum partials +v_add_f32 v[vgprValuC+19], v[vgprValuC+19], v35 // accum partials + +s_waitcnt vmcnt(1) // wait C (interleaved) 1 = 4 - 2 + 0 - 1 +v_add_f32 v[vgprValuC+20], v[vgprValuC+20], v36 // accum partials +v_add_f32 v[vgprValuC+21], v[vgprValuC+21], v37 // accum partials +v_add_f32 v[vgprValuC+22], v[vgprValuC+22], v38 // accum partials +v_add_f32 v[vgprValuC+23], v[vgprValuC+23], v39 // accum partials + +s_waitcnt vmcnt(0) // wait C (interleaved) 0 = 4 - 3 + 0 - 1 +v_add_f32 v[vgprValuC+24], v[vgprValuC+24], v40 // accum partials +v_add_f32 v[vgprValuC+25], v[vgprValuC+25], v41 // accum partials +v_add_f32 v[vgprValuC+26], v[vgprValuC+26], v42 // accum partials +v_add_f32 v[vgprValuC+27], v[vgprValuC+27], v43 // accum partials +v_accvgpr_write_b32 acc67, v[vgprValuC+12] // copy vreg[112] to acc +v_accvgpr_write_b32 acc71, v[vgprValuC+13] // copy vreg[113] to acc +v_accvgpr_write_b32 acc75, v[vgprValuC+14] // copy vreg[114] to acc +v_accvgpr_write_b32 acc79, v[vgprValuC+15] // copy vreg[115] to acc +v_accvgpr_write_b32 acc83, v[vgprValuC+16] // copy vreg[116] to acc +v_accvgpr_write_b32 acc87, v[vgprValuC+17] // copy vreg[117] to acc +v_accvgpr_write_b32 acc91, v[vgprValuC+18] // copy vreg[118] to acc +v_accvgpr_write_b32 acc95, v[vgprValuC+19] // copy vreg[119] to acc +v_accvgpr_write_b32 acc99, v[vgprValuC+20] // copy vreg[120] to acc +v_accvgpr_write_b32 acc103, v[vgprValuC+21] // copy vreg[121] to acc +v_accvgpr_write_b32 acc107, v[vgprValuC+22] // copy vreg[122] to acc +v_accvgpr_write_b32 acc111, v[vgprValuC+23] // copy vreg[123] to acc +v_accvgpr_write_b32 acc115, v[vgprValuC+24] // copy vreg[124] to acc +v_accvgpr_write_b32 acc119, v[vgprValuC+25] // copy vreg[125] to acc +v_accvgpr_write_b32 acc123, v[vgprValuC+26] // copy vreg[126] to acc +v_accvgpr_write_b32 acc127, v[vgprValuC+27] // copy vreg[127] to acc +s_nop 1 // 2 wait states required before reading vgpr +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_mul_i32 s58, s[sgprskTiles], s[sgprItersPerTile] +s_mul_i32 s59, s[sgprSKItersPerWG], s[sgprskGrid] +s_sub_u32 s58, s58, s59 // skTiles * ItersPerTile - SKItersPerWG * skGrid +s_add_u32 s59, s[sgprSKItersPerWG], 1 // Add extra iter +s_cmp_lt_u32 s8, s58 // Check if next WG had an extra iteration +s_cselect_b32 s59, s59, s[sgprSKItersPerWG] // Select correct number of iterations for next WG +s_add_u32 s9, s9, s59 // next partial tile iteration +s_add_u32 s8, s8, 1 // next partial tile index +s_cmp_lt_u32 s9, s[sgprItersPerTile] // done loading partial tiles? +s_cbranch_scc1 label_SK_Fixup // Branch to continue fixup loop +label_SK_Store: +s_cmpk_eq_u32 s[sgprBeta], 0 // Beta == 0 +s_cbranch_scc0 label_GW_B1 // Branch if Beta is not zero + +label_GW_B0_1: +label_GW_B0_FD0_1: +s_and_b32 s64, 127, s[sgprSizeI] // s64 = s[sgprSizeI] % 128 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups0] +s_cmp_ge_u32 s[sgprWorkGroup0], s65 // wg0 >= nwg0-1 ? +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B0_FD0_VW4_Else_1 // jump if edges required +s_and_b32 s64, 255, s[sgprSizeJ] // s64 = s[sgprSizeJ] % 256 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups1] +s_cmp_ge_u32 s[sgprWorkGroup1], s65 // wg1 >= nwg1-1 +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B0_FD0_VW4_Then_1 // jump if edges required +label_GW_B0_FD0_VW4_NonEdge_1: + +/* edge=0, allocate 2 sgpr. perBatchTmpS=2 perBatchMaskS=0 perElementMaskS=0 elementsPerBatch=60 */ +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 factorDim=0 */ + +/******************************************/ +/* Global Write Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_lshl_u32 v7, v3, v0, 1 // optSingleColVgpr scaleToBpe: sharedAddrVgpr <- cinRowPtr + coord0, scaled by BPE. BSHERE:coord0=0, coord0Vgpr=0 (multiple bpe) +v_accvgpr_read_b32 v[vgprValuC+12], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+13], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+14], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+15], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+16], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+17], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+18], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+19], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+20], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+21], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+22], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+23], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+24], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+25], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+26], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+27], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+28], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+29], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+30], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+31], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+32], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+33], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+34], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+35], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+36], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+37], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+38], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+39], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+40], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+41], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+42], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+43], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+44], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+45], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+46], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+47], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+48], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+49], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+50], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+51], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+52], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+53], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+54], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+55], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+56], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+57], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+58], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+59], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+60], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+61], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+62], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+63], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+64], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+65], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+66], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+67], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+68], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+69], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+70], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+71], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+72], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+73], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+74], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+75], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+76], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+77], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+78], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+79], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+80], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+81], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+82], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+83], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+84], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+85], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+86], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+87], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+88], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+89], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+90], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+91], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+92], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+93], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+94], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+95], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+96], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+97], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+98], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+99], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+100], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+101], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+102], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+103], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+104], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+105], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+106], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+107], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+108], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+109], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+110], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+111], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+112], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+113], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+114], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+115], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+116], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+117], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+118], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+119], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+120], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+121], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+122], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+123], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+124], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+125], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+126], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+127], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+128], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+129], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+130], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+131], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+132], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+133], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+134], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+135], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+136], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+137], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+138], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+139], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+88:vgprValuC+88+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+88:vgprValuC+88+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+90:vgprValuC+90+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+90:vgprValuC+90+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+92:vgprValuC+92+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+92:vgprValuC+92+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+94:vgprValuC+94+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+94:vgprValuC+94+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+96:vgprValuC+96+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+96:vgprValuC+96+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+98:vgprValuC+98+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+98:vgprValuC+98+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+100:vgprValuC+100+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+100:vgprValuC+100+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+102:vgprValuC+102+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+102:vgprValuC+102+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+104:vgprValuC+104+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+104:vgprValuC+104+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+106:vgprValuC+106+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+106:vgprValuC+106+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+108:vgprValuC+108+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+108:vgprValuC+108+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+110:vgprValuC+110+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+110:vgprValuC+110+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+112:vgprValuC+112+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+112:vgprValuC+112+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+114:vgprValuC+114+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+114:vgprValuC+114+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+116:vgprValuC+116+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+116:vgprValuC+116+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+118:vgprValuC+118+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+118:vgprValuC+118+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+120:vgprValuC+120+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+120:vgprValuC+120+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+122:vgprValuC+122+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+122:vgprValuC+122+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+124:vgprValuC+124+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+124:vgprValuC+124+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+126:vgprValuC+126+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+126:vgprValuC+126+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+128:vgprValuC+128+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+128:vgprValuC+128+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+130:vgprValuC+130+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+130:vgprValuC+130+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+132:vgprValuC+132+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+132:vgprValuC+132+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+134:vgprValuC+134+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+134:vgprValuC+134+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+136:vgprValuC+136+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+136:vgprValuC+136+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+138:vgprValuC+138+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+138:vgprValuC+138+1] op_sel_hi:[0,1,1] // *= alpha (pk) + +/* apply mask, calc new C and issue writes */ +v_cvt_f16_f32 v[vgprValuC+12], v[vgprValuC+12] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+13], v[vgprValuC+13] // convert C to fp16 +v_pack_b32_f16 v12, v[vgprValuC+12], v[vgprValuC+13] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+14], v[vgprValuC+14] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+15], v[vgprValuC+15] // convert C to fp16 +v_pack_b32_f16 v13, v[vgprValuC+14], v[vgprValuC+15] // Pack with neighbor +buffer_store_dwordx2 v[12:13], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+16], v[vgprValuC+16] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+17], v[vgprValuC+17] // convert C to fp16 +v_pack_b32_f16 v16, v[vgprValuC+16], v[vgprValuC+17] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+18], v[vgprValuC+18] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+19], v[vgprValuC+19] // convert C to fp16 +v_pack_b32_f16 v17, v[vgprValuC+18], v[vgprValuC+19] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[16:17], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+20], v[vgprValuC+20] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+21], v[vgprValuC+21] // convert C to fp16 +v_pack_b32_f16 v20, v[vgprValuC+20], v[vgprValuC+21] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+22], v[vgprValuC+22] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+23], v[vgprValuC+23] // convert C to fp16 +v_pack_b32_f16 v21, v[vgprValuC+22], v[vgprValuC+23] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[20:21], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+24], v[vgprValuC+24] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+25], v[vgprValuC+25] // convert C to fp16 +v_pack_b32_f16 v24, v[vgprValuC+24], v[vgprValuC+25] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+26], v[vgprValuC+26] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+27], v[vgprValuC+27] // convert C to fp16 +v_pack_b32_f16 v25, v[vgprValuC+26], v[vgprValuC+27] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[24:25], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+28], v[vgprValuC+28] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+29], v[vgprValuC+29] // convert C to fp16 +v_pack_b32_f16 v28, v[vgprValuC+28], v[vgprValuC+29] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+30], v[vgprValuC+30] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+31], v[vgprValuC+31] // convert C to fp16 +v_pack_b32_f16 v29, v[vgprValuC+30], v[vgprValuC+31] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[28:29], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+32], v[vgprValuC+32] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+33], v[vgprValuC+33] // convert C to fp16 +v_pack_b32_f16 v32, v[vgprValuC+32], v[vgprValuC+33] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+34], v[vgprValuC+34] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+35], v[vgprValuC+35] // convert C to fp16 +v_pack_b32_f16 v33, v[vgprValuC+34], v[vgprValuC+35] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[32:33], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+36], v[vgprValuC+36] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+37], v[vgprValuC+37] // convert C to fp16 +v_pack_b32_f16 v36, v[vgprValuC+36], v[vgprValuC+37] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+38], v[vgprValuC+38] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+39], v[vgprValuC+39] // convert C to fp16 +v_pack_b32_f16 v37, v[vgprValuC+38], v[vgprValuC+39] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[36:37], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+40], v[vgprValuC+40] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+41], v[vgprValuC+41] // convert C to fp16 +v_pack_b32_f16 v40, v[vgprValuC+40], v[vgprValuC+41] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+42], v[vgprValuC+42] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+43], v[vgprValuC+43] // convert C to fp16 +v_pack_b32_f16 v41, v[vgprValuC+42], v[vgprValuC+43] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[40:41], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+44], v[vgprValuC+44] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+45], v[vgprValuC+45] // convert C to fp16 +v_pack_b32_f16 v44, v[vgprValuC+44], v[vgprValuC+45] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+46], v[vgprValuC+46] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+47], v[vgprValuC+47] // convert C to fp16 +v_pack_b32_f16 v45, v[vgprValuC+46], v[vgprValuC+47] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[44:45], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+48], v[vgprValuC+48] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+49], v[vgprValuC+49] // convert C to fp16 +v_pack_b32_f16 v48, v[vgprValuC+48], v[vgprValuC+49] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+50], v[vgprValuC+50] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+51], v[vgprValuC+51] // convert C to fp16 +v_pack_b32_f16 v49, v[vgprValuC+50], v[vgprValuC+51] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[48:49], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+52], v[vgprValuC+52] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+53], v[vgprValuC+53] // convert C to fp16 +v_pack_b32_f16 v52, v[vgprValuC+52], v[vgprValuC+53] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+54], v[vgprValuC+54] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+55], v[vgprValuC+55] // convert C to fp16 +v_pack_b32_f16 v53, v[vgprValuC+54], v[vgprValuC+55] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[52:53], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+56], v[vgprValuC+56] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+57], v[vgprValuC+57] // convert C to fp16 +v_pack_b32_f16 v56, v[vgprValuC+56], v[vgprValuC+57] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+58], v[vgprValuC+58] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+59], v[vgprValuC+59] // convert C to fp16 +v_pack_b32_f16 v57, v[vgprValuC+58], v[vgprValuC+59] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[56:57], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+60], v[vgprValuC+60] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+61], v[vgprValuC+61] // convert C to fp16 +v_pack_b32_f16 v60, v[vgprValuC+60], v[vgprValuC+61] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+62], v[vgprValuC+62] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+63], v[vgprValuC+63] // convert C to fp16 +v_pack_b32_f16 v61, v[vgprValuC+62], v[vgprValuC+63] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[60:61], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+64], v[vgprValuC+64] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+65], v[vgprValuC+65] // convert C to fp16 +v_pack_b32_f16 v64, v[vgprValuC+64], v[vgprValuC+65] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+66], v[vgprValuC+66] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+67], v[vgprValuC+67] // convert C to fp16 +v_pack_b32_f16 v65, v[vgprValuC+66], v[vgprValuC+67] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[64:65], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+68], v[vgprValuC+68] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+69], v[vgprValuC+69] // convert C to fp16 +v_pack_b32_f16 v68, v[vgprValuC+68], v[vgprValuC+69] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+70], v[vgprValuC+70] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+71], v[vgprValuC+71] // convert C to fp16 +v_pack_b32_f16 v69, v[vgprValuC+70], v[vgprValuC+71] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[68:69], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+72], v[vgprValuC+72] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+73], v[vgprValuC+73] // convert C to fp16 +v_pack_b32_f16 v72, v[vgprValuC+72], v[vgprValuC+73] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+74], v[vgprValuC+74] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+75], v[vgprValuC+75] // convert C to fp16 +v_pack_b32_f16 v73, v[vgprValuC+74], v[vgprValuC+75] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[72:73], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+76], v[vgprValuC+76] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+77], v[vgprValuC+77] // convert C to fp16 +v_pack_b32_f16 v76, v[vgprValuC+76], v[vgprValuC+77] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+78], v[vgprValuC+78] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+79], v[vgprValuC+79] // convert C to fp16 +v_pack_b32_f16 v77, v[vgprValuC+78], v[vgprValuC+79] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[76:77], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+80], v[vgprValuC+80] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+81], v[vgprValuC+81] // convert C to fp16 +v_pack_b32_f16 v80, v[vgprValuC+80], v[vgprValuC+81] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+82], v[vgprValuC+82] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+83], v[vgprValuC+83] // convert C to fp16 +v_pack_b32_f16 v81, v[vgprValuC+82], v[vgprValuC+83] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[80:81], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+84], v[vgprValuC+84] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+85], v[vgprValuC+85] // convert C to fp16 +v_pack_b32_f16 v84, v[vgprValuC+84], v[vgprValuC+85] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+86], v[vgprValuC+86] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+87], v[vgprValuC+87] // convert C to fp16 +v_pack_b32_f16 v85, v[vgprValuC+86], v[vgprValuC+87] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[84:85], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+88], v[vgprValuC+88] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+89], v[vgprValuC+89] // convert C to fp16 +v_pack_b32_f16 v88, v[vgprValuC+88], v[vgprValuC+89] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+90], v[vgprValuC+90] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+91], v[vgprValuC+91] // convert C to fp16 +v_pack_b32_f16 v89, v[vgprValuC+90], v[vgprValuC+91] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[88:89], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+92], v[vgprValuC+92] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+93], v[vgprValuC+93] // convert C to fp16 +v_pack_b32_f16 v92, v[vgprValuC+92], v[vgprValuC+93] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+94], v[vgprValuC+94] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+95], v[vgprValuC+95] // convert C to fp16 +v_pack_b32_f16 v93, v[vgprValuC+94], v[vgprValuC+95] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[92:93], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+96], v[vgprValuC+96] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+97], v[vgprValuC+97] // convert C to fp16 +v_pack_b32_f16 v96, v[vgprValuC+96], v[vgprValuC+97] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+98], v[vgprValuC+98] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+99], v[vgprValuC+99] // convert C to fp16 +v_pack_b32_f16 v97, v[vgprValuC+98], v[vgprValuC+99] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[96:97], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+100], v[vgprValuC+100] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+101], v[vgprValuC+101] // convert C to fp16 +v_pack_b32_f16 v100, v[vgprValuC+100], v[vgprValuC+101] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+102], v[vgprValuC+102] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+103], v[vgprValuC+103] // convert C to fp16 +v_pack_b32_f16 v101, v[vgprValuC+102], v[vgprValuC+103] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[100:101], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+104], v[vgprValuC+104] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+105], v[vgprValuC+105] // convert C to fp16 +v_pack_b32_f16 v104, v[vgprValuC+104], v[vgprValuC+105] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+106], v[vgprValuC+106] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+107], v[vgprValuC+107] // convert C to fp16 +v_pack_b32_f16 v105, v[vgprValuC+106], v[vgprValuC+107] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[104:105], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+108], v[vgprValuC+108] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+109], v[vgprValuC+109] // convert C to fp16 +v_pack_b32_f16 v108, v[vgprValuC+108], v[vgprValuC+109] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+110], v[vgprValuC+110] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+111], v[vgprValuC+111] // convert C to fp16 +v_pack_b32_f16 v109, v[vgprValuC+110], v[vgprValuC+111] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[108:109], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+112], v[vgprValuC+112] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+113], v[vgprValuC+113] // convert C to fp16 +v_pack_b32_f16 v112, v[vgprValuC+112], v[vgprValuC+113] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+114], v[vgprValuC+114] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+115], v[vgprValuC+115] // convert C to fp16 +v_pack_b32_f16 v113, v[vgprValuC+114], v[vgprValuC+115] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[112:113], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+116], v[vgprValuC+116] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+117], v[vgprValuC+117] // convert C to fp16 +v_pack_b32_f16 v116, v[vgprValuC+116], v[vgprValuC+117] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+118], v[vgprValuC+118] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+119], v[vgprValuC+119] // convert C to fp16 +v_pack_b32_f16 v117, v[vgprValuC+118], v[vgprValuC+119] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[116:117], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+120], v[vgprValuC+120] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+121], v[vgprValuC+121] // convert C to fp16 +v_pack_b32_f16 v120, v[vgprValuC+120], v[vgprValuC+121] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+122], v[vgprValuC+122] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+123], v[vgprValuC+123] // convert C to fp16 +v_pack_b32_f16 v121, v[vgprValuC+122], v[vgprValuC+123] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[120:121], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+124], v[vgprValuC+124] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+125], v[vgprValuC+125] // convert C to fp16 +v_pack_b32_f16 v124, v[vgprValuC+124], v[vgprValuC+125] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+126], v[vgprValuC+126] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+127], v[vgprValuC+127] // convert C to fp16 +v_pack_b32_f16 v125, v[vgprValuC+126], v[vgprValuC+127] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[124:125], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+128], v[vgprValuC+128] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+129], v[vgprValuC+129] // convert C to fp16 +v_pack_b32_f16 v128, v[vgprValuC+128], v[vgprValuC+129] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+130], v[vgprValuC+130] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+131], v[vgprValuC+131] // convert C to fp16 +v_pack_b32_f16 v129, v[vgprValuC+130], v[vgprValuC+131] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[128:129], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+132], v[vgprValuC+132] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+133], v[vgprValuC+133] // convert C to fp16 +v_pack_b32_f16 v132, v[vgprValuC+132], v[vgprValuC+133] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+134], v[vgprValuC+134] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+135], v[vgprValuC+135] // convert C to fp16 +v_pack_b32_f16 v133, v[vgprValuC+134], v[vgprValuC+135] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[132:133], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+136], v[vgprValuC+136] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+137], v[vgprValuC+137] // convert C to fp16 +v_pack_b32_f16 v136, v[vgprValuC+136], v[vgprValuC+137] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+138], v[vgprValuC+138] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+139], v[vgprValuC+139] // convert C to fp16 +v_pack_b32_f16 v137, v[vgprValuC+138], v[vgprValuC+139] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[136:137], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_GW_B0_FD0_VW4_NonEdgeEnd_1: +label_GW_B0_FD0_VW4_Then_1: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=48 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v7, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v7, v6, v7, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v137, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v137, v6, v137, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v139, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v139, v6, v139, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v141, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v143, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v143, v6, v143, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v145, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v145, v6, v145, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v147, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v148, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v149, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v149, v6, v149, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v150, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v151, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v151, v6, v151, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v153, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v154, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v155, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v155, v6, v155, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v156, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v157, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v157, v6, v157, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v159, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v160, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v161, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v161, v6, v161, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v162, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v163, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v163, v6, v163, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v165, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v166, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+8], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+9], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+10], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+11], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+12], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+13], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+14], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+15], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+16], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+17], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+18], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+19], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+20], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+21], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+22], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+23], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+24], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+25], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+26], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+27], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+28], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+29], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+30], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+31], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+32], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+33], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+34], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+35], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+36], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+37], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+38], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+39], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+40], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+41], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+42], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+43], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+44], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+45], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+46], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+47], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+48], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+49], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+50], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+51], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+52], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+53], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+54], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+55], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+56], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+57], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+58], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+59], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+60], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+61], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+62], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+63], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+64], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+65], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+66], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+67], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+68], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+69], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+70], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+71], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+72], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+73], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+74], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+75], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+76], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+77], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+78], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+79], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+80], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+81], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+82], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+83], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+84], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+85], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+86], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+87], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+88], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+89], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+90], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+91], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+92], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+93], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+94], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+95], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+96], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+97], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+98], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+99], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+100], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+101], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+102], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+103], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+104], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+105], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+106], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+107], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+108], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+109], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+110], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+111], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+112], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+113], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+114], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+115], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+116], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+117], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+118], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+119], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+120], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+121], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+122], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+123], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+124], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+125], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+126], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+127], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+128], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+129], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+130], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+131], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+132], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+133], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+134], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+135], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+88:vgprValuC+88+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+88:vgprValuC+88+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+90:vgprValuC+90+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+90:vgprValuC+90+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+92:vgprValuC+92+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+92:vgprValuC+92+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+94:vgprValuC+94+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+94:vgprValuC+94+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+96:vgprValuC+96+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+96:vgprValuC+96+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+98:vgprValuC+98+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+98:vgprValuC+98+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+100:vgprValuC+100+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+100:vgprValuC+100+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+102:vgprValuC+102+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+102:vgprValuC+102+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+104:vgprValuC+104+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+104:vgprValuC+104+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+106:vgprValuC+106+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+106:vgprValuC+106+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+108:vgprValuC+108+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+108:vgprValuC+108+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+110:vgprValuC+110+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+110:vgprValuC+110+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+112:vgprValuC+112+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+112:vgprValuC+112+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+114:vgprValuC+114+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+114:vgprValuC+114+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+116:vgprValuC+116+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+116:vgprValuC+116+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+118:vgprValuC+118+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+118:vgprValuC+118+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+120:vgprValuC+120+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+120:vgprValuC+120+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+122:vgprValuC+122+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+122:vgprValuC+122+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+124:vgprValuC+124+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+124:vgprValuC+124+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+126:vgprValuC+126+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+126:vgprValuC+126+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+128:vgprValuC+128+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+128:vgprValuC+128+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+130:vgprValuC+130+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+130:vgprValuC+130+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+132:vgprValuC+132+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+132:vgprValuC+132+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+134:vgprValuC+134+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+134:vgprValuC+134+1] op_sel_hi:[0,1,1] // *= alpha (pk) + +/* apply mask, calc new C and issue writes */ +v_cvt_f16_f32 v[vgprValuC+8], v[vgprValuC+8] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+9], v[vgprValuC+9] // convert C to fp16 +v_pack_b32_f16 v8, v[vgprValuC+8], v[vgprValuC+9] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+10], v[vgprValuC+10] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+11], v[vgprValuC+11] // convert C to fp16 +v_pack_b32_f16 v9, v[vgprValuC+10], v[vgprValuC+11] // Pack with neighbor +buffer_store_dwordx2 v[8:9], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+12], v[vgprValuC+12] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+13], v[vgprValuC+13] // convert C to fp16 +v_pack_b32_f16 v12, v[vgprValuC+12], v[vgprValuC+13] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+14], v[vgprValuC+14] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+15], v[vgprValuC+15] // convert C to fp16 +v_pack_b32_f16 v13, v[vgprValuC+14], v[vgprValuC+15] // Pack with neighbor +buffer_store_dwordx2 v[12:13], v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+16], v[vgprValuC+16] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+17], v[vgprValuC+17] // convert C to fp16 +v_pack_b32_f16 v16, v[vgprValuC+16], v[vgprValuC+17] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+18], v[vgprValuC+18] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+19], v[vgprValuC+19] // convert C to fp16 +v_pack_b32_f16 v17, v[vgprValuC+18], v[vgprValuC+19] // Pack with neighbor +buffer_store_dwordx2 v[16:17], v137, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+20], v[vgprValuC+20] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+21], v[vgprValuC+21] // convert C to fp16 +v_pack_b32_f16 v20, v[vgprValuC+20], v[vgprValuC+21] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+22], v[vgprValuC+22] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+23], v[vgprValuC+23] // convert C to fp16 +v_pack_b32_f16 v21, v[vgprValuC+22], v[vgprValuC+23] // Pack with neighbor +buffer_store_dwordx2 v[20:21], v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+24], v[vgprValuC+24] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+25], v[vgprValuC+25] // convert C to fp16 +v_pack_b32_f16 v24, v[vgprValuC+24], v[vgprValuC+25] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+26], v[vgprValuC+26] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+27], v[vgprValuC+27] // convert C to fp16 +v_pack_b32_f16 v25, v[vgprValuC+26], v[vgprValuC+27] // Pack with neighbor +buffer_store_dwordx2 v[24:25], v139, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+28], v[vgprValuC+28] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+29], v[vgprValuC+29] // convert C to fp16 +v_pack_b32_f16 v28, v[vgprValuC+28], v[vgprValuC+29] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+30], v[vgprValuC+30] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+31], v[vgprValuC+31] // convert C to fp16 +v_pack_b32_f16 v29, v[vgprValuC+30], v[vgprValuC+31] // Pack with neighbor +buffer_store_dwordx2 v[28:29], v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+32], v[vgprValuC+32] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+33], v[vgprValuC+33] // convert C to fp16 +v_pack_b32_f16 v32, v[vgprValuC+32], v[vgprValuC+33] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+34], v[vgprValuC+34] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+35], v[vgprValuC+35] // convert C to fp16 +v_pack_b32_f16 v33, v[vgprValuC+34], v[vgprValuC+35] // Pack with neighbor +buffer_store_dwordx2 v[32:33], v141, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+36], v[vgprValuC+36] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+37], v[vgprValuC+37] // convert C to fp16 +v_pack_b32_f16 v36, v[vgprValuC+36], v[vgprValuC+37] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+38], v[vgprValuC+38] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+39], v[vgprValuC+39] // convert C to fp16 +v_pack_b32_f16 v37, v[vgprValuC+38], v[vgprValuC+39] // Pack with neighbor +buffer_store_dwordx2 v[36:37], v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+40], v[vgprValuC+40] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+41], v[vgprValuC+41] // convert C to fp16 +v_pack_b32_f16 v40, v[vgprValuC+40], v[vgprValuC+41] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+42], v[vgprValuC+42] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+43], v[vgprValuC+43] // convert C to fp16 +v_pack_b32_f16 v41, v[vgprValuC+42], v[vgprValuC+43] // Pack with neighbor +buffer_store_dwordx2 v[40:41], v143, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+44], v[vgprValuC+44] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+45], v[vgprValuC+45] // convert C to fp16 +v_pack_b32_f16 v44, v[vgprValuC+44], v[vgprValuC+45] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+46], v[vgprValuC+46] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+47], v[vgprValuC+47] // convert C to fp16 +v_pack_b32_f16 v45, v[vgprValuC+46], v[vgprValuC+47] // Pack with neighbor +buffer_store_dwordx2 v[44:45], v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+48], v[vgprValuC+48] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+49], v[vgprValuC+49] // convert C to fp16 +v_pack_b32_f16 v48, v[vgprValuC+48], v[vgprValuC+49] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+50], v[vgprValuC+50] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+51], v[vgprValuC+51] // convert C to fp16 +v_pack_b32_f16 v49, v[vgprValuC+50], v[vgprValuC+51] // Pack with neighbor +buffer_store_dwordx2 v[48:49], v145, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+52], v[vgprValuC+52] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+53], v[vgprValuC+53] // convert C to fp16 +v_pack_b32_f16 v52, v[vgprValuC+52], v[vgprValuC+53] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+54], v[vgprValuC+54] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+55], v[vgprValuC+55] // convert C to fp16 +v_pack_b32_f16 v53, v[vgprValuC+54], v[vgprValuC+55] // Pack with neighbor +buffer_store_dwordx2 v[52:53], v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+56], v[vgprValuC+56] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+57], v[vgprValuC+57] // convert C to fp16 +v_pack_b32_f16 v56, v[vgprValuC+56], v[vgprValuC+57] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+58], v[vgprValuC+58] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+59], v[vgprValuC+59] // convert C to fp16 +v_pack_b32_f16 v57, v[vgprValuC+58], v[vgprValuC+59] // Pack with neighbor +buffer_store_dwordx2 v[56:57], v147, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+60], v[vgprValuC+60] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+61], v[vgprValuC+61] // convert C to fp16 +v_pack_b32_f16 v60, v[vgprValuC+60], v[vgprValuC+61] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+62], v[vgprValuC+62] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+63], v[vgprValuC+63] // convert C to fp16 +v_pack_b32_f16 v61, v[vgprValuC+62], v[vgprValuC+63] // Pack with neighbor +buffer_store_dwordx2 v[60:61], v148, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+64], v[vgprValuC+64] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+65], v[vgprValuC+65] // convert C to fp16 +v_pack_b32_f16 v64, v[vgprValuC+64], v[vgprValuC+65] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+66], v[vgprValuC+66] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+67], v[vgprValuC+67] // convert C to fp16 +v_pack_b32_f16 v65, v[vgprValuC+66], v[vgprValuC+67] // Pack with neighbor +buffer_store_dwordx2 v[64:65], v149, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+68], v[vgprValuC+68] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+69], v[vgprValuC+69] // convert C to fp16 +v_pack_b32_f16 v68, v[vgprValuC+68], v[vgprValuC+69] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+70], v[vgprValuC+70] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+71], v[vgprValuC+71] // convert C to fp16 +v_pack_b32_f16 v69, v[vgprValuC+70], v[vgprValuC+71] // Pack with neighbor +buffer_store_dwordx2 v[68:69], v150, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+72], v[vgprValuC+72] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+73], v[vgprValuC+73] // convert C to fp16 +v_pack_b32_f16 v72, v[vgprValuC+72], v[vgprValuC+73] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+74], v[vgprValuC+74] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+75], v[vgprValuC+75] // convert C to fp16 +v_pack_b32_f16 v73, v[vgprValuC+74], v[vgprValuC+75] // Pack with neighbor +buffer_store_dwordx2 v[72:73], v151, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+76], v[vgprValuC+76] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+77], v[vgprValuC+77] // convert C to fp16 +v_pack_b32_f16 v76, v[vgprValuC+76], v[vgprValuC+77] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+78], v[vgprValuC+78] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+79], v[vgprValuC+79] // convert C to fp16 +v_pack_b32_f16 v77, v[vgprValuC+78], v[vgprValuC+79] // Pack with neighbor +buffer_store_dwordx2 v[76:77], v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+80], v[vgprValuC+80] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+81], v[vgprValuC+81] // convert C to fp16 +v_pack_b32_f16 v80, v[vgprValuC+80], v[vgprValuC+81] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+82], v[vgprValuC+82] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+83], v[vgprValuC+83] // convert C to fp16 +v_pack_b32_f16 v81, v[vgprValuC+82], v[vgprValuC+83] // Pack with neighbor +buffer_store_dwordx2 v[80:81], v153, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+84], v[vgprValuC+84] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+85], v[vgprValuC+85] // convert C to fp16 +v_pack_b32_f16 v84, v[vgprValuC+84], v[vgprValuC+85] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+86], v[vgprValuC+86] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+87], v[vgprValuC+87] // convert C to fp16 +v_pack_b32_f16 v85, v[vgprValuC+86], v[vgprValuC+87] // Pack with neighbor +buffer_store_dwordx2 v[84:85], v154, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+88], v[vgprValuC+88] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+89], v[vgprValuC+89] // convert C to fp16 +v_pack_b32_f16 v88, v[vgprValuC+88], v[vgprValuC+89] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+90], v[vgprValuC+90] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+91], v[vgprValuC+91] // convert C to fp16 +v_pack_b32_f16 v89, v[vgprValuC+90], v[vgprValuC+91] // Pack with neighbor +buffer_store_dwordx2 v[88:89], v155, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+92], v[vgprValuC+92] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+93], v[vgprValuC+93] // convert C to fp16 +v_pack_b32_f16 v92, v[vgprValuC+92], v[vgprValuC+93] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+94], v[vgprValuC+94] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+95], v[vgprValuC+95] // convert C to fp16 +v_pack_b32_f16 v93, v[vgprValuC+94], v[vgprValuC+95] // Pack with neighbor +buffer_store_dwordx2 v[92:93], v156, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+96], v[vgprValuC+96] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+97], v[vgprValuC+97] // convert C to fp16 +v_pack_b32_f16 v96, v[vgprValuC+96], v[vgprValuC+97] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+98], v[vgprValuC+98] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+99], v[vgprValuC+99] // convert C to fp16 +v_pack_b32_f16 v97, v[vgprValuC+98], v[vgprValuC+99] // Pack with neighbor +buffer_store_dwordx2 v[96:97], v157, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+100], v[vgprValuC+100] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+101], v[vgprValuC+101] // convert C to fp16 +v_pack_b32_f16 v100, v[vgprValuC+100], v[vgprValuC+101] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+102], v[vgprValuC+102] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+103], v[vgprValuC+103] // convert C to fp16 +v_pack_b32_f16 v101, v[vgprValuC+102], v[vgprValuC+103] // Pack with neighbor +buffer_store_dwordx2 v[100:101], v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+104], v[vgprValuC+104] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+105], v[vgprValuC+105] // convert C to fp16 +v_pack_b32_f16 v104, v[vgprValuC+104], v[vgprValuC+105] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+106], v[vgprValuC+106] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+107], v[vgprValuC+107] // convert C to fp16 +v_pack_b32_f16 v105, v[vgprValuC+106], v[vgprValuC+107] // Pack with neighbor +buffer_store_dwordx2 v[104:105], v159, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+108], v[vgprValuC+108] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+109], v[vgprValuC+109] // convert C to fp16 +v_pack_b32_f16 v108, v[vgprValuC+108], v[vgprValuC+109] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+110], v[vgprValuC+110] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+111], v[vgprValuC+111] // convert C to fp16 +v_pack_b32_f16 v109, v[vgprValuC+110], v[vgprValuC+111] // Pack with neighbor +buffer_store_dwordx2 v[108:109], v160, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+112], v[vgprValuC+112] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+113], v[vgprValuC+113] // convert C to fp16 +v_pack_b32_f16 v112, v[vgprValuC+112], v[vgprValuC+113] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+114], v[vgprValuC+114] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+115], v[vgprValuC+115] // convert C to fp16 +v_pack_b32_f16 v113, v[vgprValuC+114], v[vgprValuC+115] // Pack with neighbor +buffer_store_dwordx2 v[112:113], v161, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+116], v[vgprValuC+116] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+117], v[vgprValuC+117] // convert C to fp16 +v_pack_b32_f16 v116, v[vgprValuC+116], v[vgprValuC+117] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+118], v[vgprValuC+118] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+119], v[vgprValuC+119] // convert C to fp16 +v_pack_b32_f16 v117, v[vgprValuC+118], v[vgprValuC+119] // Pack with neighbor +buffer_store_dwordx2 v[116:117], v162, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+120], v[vgprValuC+120] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+121], v[vgprValuC+121] // convert C to fp16 +v_pack_b32_f16 v120, v[vgprValuC+120], v[vgprValuC+121] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+122], v[vgprValuC+122] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+123], v[vgprValuC+123] // convert C to fp16 +v_pack_b32_f16 v121, v[vgprValuC+122], v[vgprValuC+123] // Pack with neighbor +buffer_store_dwordx2 v[120:121], v163, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+124], v[vgprValuC+124] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+125], v[vgprValuC+125] // convert C to fp16 +v_pack_b32_f16 v124, v[vgprValuC+124], v[vgprValuC+125] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+126], v[vgprValuC+126] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+127], v[vgprValuC+127] // convert C to fp16 +v_pack_b32_f16 v125, v[vgprValuC+126], v[vgprValuC+127] // Pack with neighbor +buffer_store_dwordx2 v[124:125], v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+128], v[vgprValuC+128] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+129], v[vgprValuC+129] // convert C to fp16 +v_pack_b32_f16 v128, v[vgprValuC+128], v[vgprValuC+129] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+130], v[vgprValuC+130] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+131], v[vgprValuC+131] // convert C to fp16 +v_pack_b32_f16 v129, v[vgprValuC+130], v[vgprValuC+131] // Pack with neighbor +buffer_store_dwordx2 v[128:129], v165, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v[vgprValuC+132], v[vgprValuC+132] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+133], v[vgprValuC+133] // convert C to fp16 +v_pack_b32_f16 v132, v[vgprValuC+132], v[vgprValuC+133] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+134], v[vgprValuC+134] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+135], v[vgprValuC+135] // convert C to fp16 +v_pack_b32_f16 v133, v[vgprValuC+134], v[vgprValuC+135] // Pack with neighbor +buffer_store_dwordx2 v[132:133], v166, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_GW_B0_FD0_VW4_Else_1: +label_GW_B0_FD0_VW1_Else_1: +label_GW_B0_FD0_VW1_Then_1: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=122 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw1); (0,0,0,1:vw1); (0,0,0,2:vw1); (0,0,0,3:vw1); (0,0,1,0:vw1); (0,0,1,1:vw1); (0,0,1,2:vw1); (0,0,1,3:vw1); (0,0,2,0:vw1); (0,0,2,1:vw1); (0,0,2,2:vw1); (0,0,2,3:vw1); (0,0,3,0:vw1); (0,0,3,1:vw1); (0,0,3,2:vw1); (0,0,3,3:vw1); (0,0,4,0:vw1); (0,0,4,1:vw1); (0,0,4,2:vw1); (0,0,4,3:vw1); (0,0,5,0:vw1); (0,0,5,1:vw1); (0,0,5,2:vw1); (0,0,5,3:vw1); (0,0,6,0:vw1); (0,0,6,1:vw1); (0,0,6,2:vw1); (0,0,6,3:vw1); (0,0,7,0:vw1); (0,0,7,1:vw1); (0,0,7,2:vw1); (0,0,7,3:vw1); (0,0,8,0:vw1); (0,0,8,1:vw1); (0,0,8,2:vw1); (0,0,8,3:vw1); (0,0,9,0:vw1); (0,0,9,1:vw1); (0,0,9,2:vw1); (0,0,9,3:vw1); (0,0,10,0:vw1); (0,0,10,1:vw1); (0,0,10,2:vw1); (0,0,10,3:vw1); (0,0,11,0:vw1); (0,0,11,1:vw1); (0,0,11,2:vw1); (0,0,11,3:vw1); (0,0,12,0:vw1); (0,0,12,1:vw1); (0,0,12,2:vw1); (0,0,12,3:vw1); (0,0,13,0:vw1); (0,0,13,1:vw1); (0,0,13,2:vw1); (0,0,13,3:vw1); (0,0,14,0:vw1); (0,0,14,1:vw1); (0,0,14,2:vw1); (0,0,14,3:vw1); (0,0,15,0:vw1); (0,0,15,1:vw1); (0,0,15,2:vw1); (0,0,15,3:vw1); (0,0,16,0:vw1); (0,0,16,1:vw1); (0,0,16,2:vw1); (0,0,16,3:vw1); (0,0,17,0:vw1); (0,0,17,1:vw1); (0,0,17,2:vw1); (0,0,17,3:vw1); (0,0,18,0:vw1); (0,0,18,1:vw1); (0,0,18,2:vw1); (0,0,18,3:vw1); (0,0,19,0:vw1); (0,0,19,1:vw1); (0,0,19,2:vw1); (0,0,19,3:vw1); (0,0,20,0:vw1); (0,0,20,1:vw1); (0,0,20,2:vw1); (0,0,20,3:vw1); (0,0,21,0:vw1); (0,0,21,1:vw1); (0,0,21,2:vw1); (0,0,21,3:vw1); (0,0,22,0:vw1); (0,0,22,1:vw1); (0,0,22,2:vw1); (0,0,22,3:vw1); (0,0,23,0:vw1); (0,0,23,1:vw1); (0,0,23,2:vw1); (0,0,23,3:vw1); (0,0,24,0:vw1); (0,0,24,1:vw1); (0,0,24,2:vw1); (0,0,24,3:vw1); (0,0,25,0:vw1); (0,0,25,1:vw1); (0,0,25,2:vw1); (0,0,25,3:vw1); (0,0,26,0:vw1); (0,0,26,1:vw1); (0,0,26,2:vw1); (0,0,26,3:vw1); (0,0,27,0:vw1); (0,0,27,1:vw1); (0,0,27,2:vw1); (0,0,27,3:vw1); (0,0,28,0:vw1); (0,0,28,1:vw1); (0,0,28,2:vw1); (0,0,28,3:vw1); (0,0,29,0:vw1); (0,0,29,1:vw1); (0,0,29,2:vw1); (0,0,29,3:vw1); (0,0,30,0:vw1); (0,0,30,1:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v129, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v129, v6, v129, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v130, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v131, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v131, v6, v131, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v132, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v133, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v133, v6, v133, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v134, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v135, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v135, v6, v135, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v137, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v137, v6, v137, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v139, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v139, v6, v139, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v141, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v143, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v143, v6, v143, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v145, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v145, v6, v145, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v147, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v148, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v149, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v149, v6, v149, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v150, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v151, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v151, v6, v151, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v153, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v154, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v155, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v155, v6, v155, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v156, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v157, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v157, v6, v157, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v159, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v160, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v161, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v161, v6, v161, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v162, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v163, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v163, v6, v163, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v165, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v166, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v167, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v167, v6, v167, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v168, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v168, v6, v168, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v169, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v169, v6, v169, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v170, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v171, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v171, v6, v171, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v172, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v172, v6, v172, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v173, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v173, v6, v173, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v174, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v174, v6, v174, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v175, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v175, v6, v175, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v176, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v177, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v177, v6, v177, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v178, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v178, v6, v178, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v179, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v179, v6, v179, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v180, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v180, v6, v180, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v181, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v181, v6, v181, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v182, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v183, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v183, v6, v183, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v185, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v186, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v186, v6, v186, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v187, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v187, v6, v187, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v188, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v188, v6, v188, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v189, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v189, v6, v189, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v190, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v190, v6, v190, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v191, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v191, v6, v191, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v192, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v192, v6, v192, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v193, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v194, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v194, v6, v194, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v195, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v195, v6, v195, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v196, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v196, v6, v196, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v197, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v197, v6, v197, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v198, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v198, v6, v198, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v199, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v200, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v200, v6, v200, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v201, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v201, v6, v201, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v202, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v202, v6, v202, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v203, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v203, v6, v203, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v204, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v204, v6, v204, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v205, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v206, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v206, v6, v206, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v207, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v207, v6, v207, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v208, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v208, v6, v208, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v209, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v209, v6, v209, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v210, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v210, v6, v210, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v211, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v212, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v212, v6, v212, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v213, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v213, v6, v213, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v214, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v214, v6, v214, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v215, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v215, v6, v215, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v216, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v216, v6, v216, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v217, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v218, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v218, v6, v218, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v219, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v219, v6, v219, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v220, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v220, v6, v220, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v221, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v221, v6, v221, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v222, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v222, v6, v222, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v223, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v224, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v224, v6, v224, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v225, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v225, v6, v225, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v226, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v226, v6, v226, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v227, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v227, v6, v227, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v228, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v228, v6, v228, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v229, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v230, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v230, v6, v230, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v231, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v231, v6, v231, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v232, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v232, v6, v232, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v233, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v233, v6, v233, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v234, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v234, v6, v234, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v235, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v235, v6, v235, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v236, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v236, v6, v236, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v237, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v237, v6, v237, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v238, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v238, v6, v238, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v239, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v239, v6, v239, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v240, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v240, v6, v240, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v241, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v241, v6, v241, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v242, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v242, v6, v242, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v243, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v243, v6, v243, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v244, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v244, v6, v244, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v245, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v245, v6, v245, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v246, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v246, v6, v246, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v247, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v247, v6, v247, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v248, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v248, v6, v248, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v249, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v249, v6, v249, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v250, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v250, v6, v250, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v251, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v251, v6, v251, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+8], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+9], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+10], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+11], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+12], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+13], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+14], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+15], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+16], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+17], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+18], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+19], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+20], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+21], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+22], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+23], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+24], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+25], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+26], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+27], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+28], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+29], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+30], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+31], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+32], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+33], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+34], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+35], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+36], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+37], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+38], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+39], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+40], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+41], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+42], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+43], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+44], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+45], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+46], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+47], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+48], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+49], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+50], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+51], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+52], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+53], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+54], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+55], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+56], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+57], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+58], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+59], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+60], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+61], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+62], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+63], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+64], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+65], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+66], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+67], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+68], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+69], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+70], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+71], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+72], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+73], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+74], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+75], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+76], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+77], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+78], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+79], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+80], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+81], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+82], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+83], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+84], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+85], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+86], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+87], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+88], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+89], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+90], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+91], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+92], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+93], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+94], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+95], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+96], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+97], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+98], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+99], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+100], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+101], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+102], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+103], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+104], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+105], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+106], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+107], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+108], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+109], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+110], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+111], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+112], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+113], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+114], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+115], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+116], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+117], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+118], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+119], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+120], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+121], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+122], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+123], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+124], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+125], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+126], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+127], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+128], acc103 // copy acc to vreg[121] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 0, 2), (0, 0, 0, 3), (0, 0, 1, 0), (0, 0, 1, 1), (0, 0, 1, 2), (0, 0, 1, 3), (0, 0, 2, 0), (0, 0, 2, 1), (0, 0, 2, 2), (0, 0, 2, 3), (0, 0, 3, 0), (0, 0, 3, 1), (0, 0, 3, 2), (0, 0, 3, 3), (0, 0, 4, 0), (0, 0, 4, 1), (0, 0, 4, 2), (0, 0, 4, 3), (0, 0, 5, 0), (0, 0, 5, 1), (0, 0, 5, 2), (0, 0, 5, 3), (0, 0, 6, 0), (0, 0, 6, 1), (0, 0, 6, 2), (0, 0, 6, 3), (0, 0, 7, 0), (0, 0, 7, 1), (0, 0, 7, 2), (0, 0, 7, 3), (0, 0, 8, 0), (0, 0, 8, 1), (0, 0, 8, 2), (0, 0, 8, 3), (0, 0, 9, 0), (0, 0, 9, 1), (0, 0, 9, 2), (0, 0, 9, 3), (0, 0, 10, 0), (0, 0, 10, 1), (0, 0, 10, 2), (0, 0, 10, 3), (0, 0, 11, 0), (0, 0, 11, 1), (0, 0, 11, 2), (0, 0, 11, 3), (0, 0, 12, 0), (0, 0, 12, 1), (0, 0, 12, 2), (0, 0, 12, 3), (0, 0, 13, 0), (0, 0, 13, 1), (0, 0, 13, 2), (0, 0, 13, 3), (0, 0, 14, 0), (0, 0, 14, 1), (0, 0, 14, 2), (0, 0, 14, 3), (0, 0, 15, 0), (0, 0, 15, 1), (0, 0, 15, 2), (0, 0, 15, 3), (0, 0, 16, 0), (0, 0, 16, 1), (0, 0, 16, 2), (0, 0, 16, 3), (0, 0, 17, 0), (0, 0, 17, 1), (0, 0, 17, 2), (0, 0, 17, 3), (0, 0, 18, 0), (0, 0, 18, 1), (0, 0, 18, 2), (0, 0, 18, 3), (0, 0, 19, 0), (0, 0, 19, 1), (0, 0, 19, 2), (0, 0, 19, 3), (0, 0, 20, 0), (0, 0, 20, 1), (0, 0, 20, 2), (0, 0, 20, 3), (0, 0, 21, 0), (0, 0, 21, 1), (0, 0, 21, 2), (0, 0, 21, 3), (0, 0, 22, 0), (0, 0, 22, 1), (0, 0, 22, 2), (0, 0, 22, 3), (0, 0, 23, 0), (0, 0, 23, 1), (0, 0, 23, 2), (0, 0, 23, 3), (0, 0, 24, 0), (0, 0, 24, 1), (0, 0, 24, 2), (0, 0, 24, 3), (0, 0, 25, 0), (0, 0, 25, 1), (0, 0, 25, 2), (0, 0, 25, 3), (0, 0, 26, 0), (0, 0, 26, 1), (0, 0, 26, 2), (0, 0, 26, 3), (0, 0, 27, 0), (0, 0, 27, 1), (0, 0, 27, 2), (0, 0, 27, 3), (0, 0, 28, 0), (0, 0, 28, 1), (0, 0, 28, 2), (0, 0, 28, 3), (0, 0, 29, 0), (0, 0, 29, 1), (0, 0, 29, 2), (0, 0, 29, 3), (0, 0, 30, 0), (0, 0, 30, 1)] */ +v_mul_f32 v[vgprValuC+7], s[sgprAlpha], v[vgprValuC+7] // *= alpha +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+88:vgprValuC+88+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+88:vgprValuC+88+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+90:vgprValuC+90+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+90:vgprValuC+90+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+92:vgprValuC+92+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+92:vgprValuC+92+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+94:vgprValuC+94+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+94:vgprValuC+94+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+96:vgprValuC+96+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+96:vgprValuC+96+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+98:vgprValuC+98+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+98:vgprValuC+98+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+100:vgprValuC+100+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+100:vgprValuC+100+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+102:vgprValuC+102+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+102:vgprValuC+102+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+104:vgprValuC+104+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+104:vgprValuC+104+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+106:vgprValuC+106+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+106:vgprValuC+106+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+108:vgprValuC+108+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+108:vgprValuC+108+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+110:vgprValuC+110+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+110:vgprValuC+110+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+112:vgprValuC+112+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+112:vgprValuC+112+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+114:vgprValuC+114+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+114:vgprValuC+114+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+116:vgprValuC+116+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+116:vgprValuC+116+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+118:vgprValuC+118+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+118:vgprValuC+118+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+120:vgprValuC+120+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+120:vgprValuC+120+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+122:vgprValuC+122+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+122:vgprValuC+122+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+124:vgprValuC+124+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+124:vgprValuC+124+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+126:vgprValuC+126+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+126:vgprValuC+126+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_mul_f32 v[vgprValuC+128], s[sgprAlpha], v[vgprValuC+128] // *= alpha + +/* apply mask, calc new C and issue writes */ +v_cvt_f16_f32 v7, v[vgprValuC+7] // convert C to fp16 +buffer_store_short v7, v129, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v8, v[vgprValuC+8] // convert C to fp16 +buffer_store_short v8, v130, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v9, v[vgprValuC+9] // convert C to fp16 +buffer_store_short v9, v131, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v10, v[vgprValuC+10] // convert C to fp16 +buffer_store_short v10, v132, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v11, v[vgprValuC+11] // convert C to fp16 +buffer_store_short v11, v133, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v12, v[vgprValuC+12] // convert C to fp16 +buffer_store_short v12, v134, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v13, v[vgprValuC+13] // convert C to fp16 +buffer_store_short v13, v135, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v14, v[vgprValuC+14] // convert C to fp16 +buffer_store_short v14, v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v15, v[vgprValuC+15] // convert C to fp16 +buffer_store_short v15, v137, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v16, v[vgprValuC+16] // convert C to fp16 +buffer_store_short v16, v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v17, v[vgprValuC+17] // convert C to fp16 +buffer_store_short v17, v139, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v18, v[vgprValuC+18] // convert C to fp16 +buffer_store_short v18, v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v19, v[vgprValuC+19] // convert C to fp16 +buffer_store_short v19, v141, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v20, v[vgprValuC+20] // convert C to fp16 +buffer_store_short v20, v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v21, v[vgprValuC+21] // convert C to fp16 +buffer_store_short v21, v143, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v22, v[vgprValuC+22] // convert C to fp16 +buffer_store_short v22, v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v23, v[vgprValuC+23] // convert C to fp16 +buffer_store_short v23, v145, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v24, v[vgprValuC+24] // convert C to fp16 +buffer_store_short v24, v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v25, v[vgprValuC+25] // convert C to fp16 +buffer_store_short v25, v147, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v26, v[vgprValuC+26] // convert C to fp16 +buffer_store_short v26, v148, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v27, v[vgprValuC+27] // convert C to fp16 +buffer_store_short v27, v149, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v28, v[vgprValuC+28] // convert C to fp16 +buffer_store_short v28, v150, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v29, v[vgprValuC+29] // convert C to fp16 +buffer_store_short v29, v151, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v30, v[vgprValuC+30] // convert C to fp16 +buffer_store_short v30, v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v31, v[vgprValuC+31] // convert C to fp16 +buffer_store_short v31, v153, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v32, v[vgprValuC+32] // convert C to fp16 +buffer_store_short v32, v154, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v33, v[vgprValuC+33] // convert C to fp16 +buffer_store_short v33, v155, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v34, v[vgprValuC+34] // convert C to fp16 +buffer_store_short v34, v156, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v35, v[vgprValuC+35] // convert C to fp16 +buffer_store_short v35, v157, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v36, v[vgprValuC+36] // convert C to fp16 +buffer_store_short v36, v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v37, v[vgprValuC+37] // convert C to fp16 +buffer_store_short v37, v159, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v38, v[vgprValuC+38] // convert C to fp16 +buffer_store_short v38, v160, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v39, v[vgprValuC+39] // convert C to fp16 +buffer_store_short v39, v161, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v40, v[vgprValuC+40] // convert C to fp16 +buffer_store_short v40, v162, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v41, v[vgprValuC+41] // convert C to fp16 +buffer_store_short v41, v163, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v42, v[vgprValuC+42] // convert C to fp16 +buffer_store_short v42, v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v43, v[vgprValuC+43] // convert C to fp16 +buffer_store_short v43, v165, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v44, v[vgprValuC+44] // convert C to fp16 +buffer_store_short v44, v166, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v45, v[vgprValuC+45] // convert C to fp16 +buffer_store_short v45, v167, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v46, v[vgprValuC+46] // convert C to fp16 +buffer_store_short v46, v168, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v47, v[vgprValuC+47] // convert C to fp16 +buffer_store_short v47, v169, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v48, v[vgprValuC+48] // convert C to fp16 +buffer_store_short v48, v170, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v49, v[vgprValuC+49] // convert C to fp16 +buffer_store_short v49, v171, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v50, v[vgprValuC+50] // convert C to fp16 +buffer_store_short v50, v172, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v51, v[vgprValuC+51] // convert C to fp16 +buffer_store_short v51, v173, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v52, v[vgprValuC+52] // convert C to fp16 +buffer_store_short v52, v174, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v53, v[vgprValuC+53] // convert C to fp16 +buffer_store_short v53, v175, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v54, v[vgprValuC+54] // convert C to fp16 +buffer_store_short v54, v176, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v55, v[vgprValuC+55] // convert C to fp16 +buffer_store_short v55, v177, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v56, v[vgprValuC+56] // convert C to fp16 +buffer_store_short v56, v178, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v57, v[vgprValuC+57] // convert C to fp16 +buffer_store_short v57, v179, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v58, v[vgprValuC+58] // convert C to fp16 +buffer_store_short v58, v180, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v59, v[vgprValuC+59] // convert C to fp16 +buffer_store_short v59, v181, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v60, v[vgprValuC+60] // convert C to fp16 +buffer_store_short v60, v182, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v61, v[vgprValuC+61] // convert C to fp16 +buffer_store_short v61, v183, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v62, v[vgprValuC+62] // convert C to fp16 +buffer_store_short v62, v185, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v63, v[vgprValuC+63] // convert C to fp16 +buffer_store_short v63, v186, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v64, v[vgprValuC+64] // convert C to fp16 +buffer_store_short v64, v187, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v65, v[vgprValuC+65] // convert C to fp16 +buffer_store_short v65, v188, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v66, v[vgprValuC+66] // convert C to fp16 +buffer_store_short v66, v189, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v67, v[vgprValuC+67] // convert C to fp16 +buffer_store_short v67, v190, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v68, v[vgprValuC+68] // convert C to fp16 +buffer_store_short v68, v191, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v69, v[vgprValuC+69] // convert C to fp16 +buffer_store_short v69, v192, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v70, v[vgprValuC+70] // convert C to fp16 +buffer_store_short v70, v193, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v71, v[vgprValuC+71] // convert C to fp16 +buffer_store_short v71, v194, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v72, v[vgprValuC+72] // convert C to fp16 +buffer_store_short v72, v195, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v73, v[vgprValuC+73] // convert C to fp16 +buffer_store_short v73, v196, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v74, v[vgprValuC+74] // convert C to fp16 +buffer_store_short v74, v197, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v75, v[vgprValuC+75] // convert C to fp16 +buffer_store_short v75, v198, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v76, v[vgprValuC+76] // convert C to fp16 +buffer_store_short v76, v199, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v77, v[vgprValuC+77] // convert C to fp16 +buffer_store_short v77, v200, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v78, v[vgprValuC+78] // convert C to fp16 +buffer_store_short v78, v201, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v79, v[vgprValuC+79] // convert C to fp16 +buffer_store_short v79, v202, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v80, v[vgprValuC+80] // convert C to fp16 +buffer_store_short v80, v203, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v81, v[vgprValuC+81] // convert C to fp16 +buffer_store_short v81, v204, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v82, v[vgprValuC+82] // convert C to fp16 +buffer_store_short v82, v205, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v83, v[vgprValuC+83] // convert C to fp16 +buffer_store_short v83, v206, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v84, v[vgprValuC+84] // convert C to fp16 +buffer_store_short v84, v207, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v85, v[vgprValuC+85] // convert C to fp16 +buffer_store_short v85, v208, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v86, v[vgprValuC+86] // convert C to fp16 +buffer_store_short v86, v209, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v87, v[vgprValuC+87] // convert C to fp16 +buffer_store_short v87, v210, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v88, v[vgprValuC+88] // convert C to fp16 +buffer_store_short v88, v211, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v89, v[vgprValuC+89] // convert C to fp16 +buffer_store_short v89, v212, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v90, v[vgprValuC+90] // convert C to fp16 +buffer_store_short v90, v213, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v91, v[vgprValuC+91] // convert C to fp16 +buffer_store_short v91, v214, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v92, v[vgprValuC+92] // convert C to fp16 +buffer_store_short v92, v215, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v93, v[vgprValuC+93] // convert C to fp16 +buffer_store_short v93, v216, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v94, v[vgprValuC+94] // convert C to fp16 +buffer_store_short v94, v217, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v95, v[vgprValuC+95] // convert C to fp16 +buffer_store_short v95, v218, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v96, v[vgprValuC+96] // convert C to fp16 +buffer_store_short v96, v219, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v97, v[vgprValuC+97] // convert C to fp16 +buffer_store_short v97, v220, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v98, v[vgprValuC+98] // convert C to fp16 +buffer_store_short v98, v221, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v99, v[vgprValuC+99] // convert C to fp16 +buffer_store_short v99, v222, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v100, v[vgprValuC+100] // convert C to fp16 +buffer_store_short v100, v223, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v101, v[vgprValuC+101] // convert C to fp16 +buffer_store_short v101, v224, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v102, v[vgprValuC+102] // convert C to fp16 +buffer_store_short v102, v225, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v103, v[vgprValuC+103] // convert C to fp16 +buffer_store_short v103, v226, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v104, v[vgprValuC+104] // convert C to fp16 +buffer_store_short v104, v227, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v105, v[vgprValuC+105] // convert C to fp16 +buffer_store_short v105, v228, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v106, v[vgprValuC+106] // convert C to fp16 +buffer_store_short v106, v229, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v107, v[vgprValuC+107] // convert C to fp16 +buffer_store_short v107, v230, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v108, v[vgprValuC+108] // convert C to fp16 +buffer_store_short v108, v231, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v109, v[vgprValuC+109] // convert C to fp16 +buffer_store_short v109, v232, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v110, v[vgprValuC+110] // convert C to fp16 +buffer_store_short v110, v233, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v111, v[vgprValuC+111] // convert C to fp16 +buffer_store_short v111, v234, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v112, v[vgprValuC+112] // convert C to fp16 +buffer_store_short v112, v235, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v113, v[vgprValuC+113] // convert C to fp16 +buffer_store_short v113, v236, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v114, v[vgprValuC+114] // convert C to fp16 +buffer_store_short v114, v237, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v115, v[vgprValuC+115] // convert C to fp16 +buffer_store_short v115, v238, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v116, v[vgprValuC+116] // convert C to fp16 +buffer_store_short v116, v239, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v117, v[vgprValuC+117] // convert C to fp16 +buffer_store_short v117, v240, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v118, v[vgprValuC+118] // convert C to fp16 +buffer_store_short v118, v241, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v119, v[vgprValuC+119] // convert C to fp16 +buffer_store_short v119, v242, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v120, v[vgprValuC+120] // convert C to fp16 +buffer_store_short v120, v243, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v121, v[vgprValuC+121] // convert C to fp16 +buffer_store_short v121, v244, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v122, v[vgprValuC+122] // convert C to fp16 +buffer_store_short v122, v245, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v123, v[vgprValuC+123] // convert C to fp16 +buffer_store_short v123, v246, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v124, v[vgprValuC+124] // convert C to fp16 +buffer_store_short v124, v247, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v125, v[vgprValuC+125] // convert C to fp16 +buffer_store_short v125, v248, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v126, v[vgprValuC+126] // convert C to fp16 +buffer_store_short v126, v249, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v127, v[vgprValuC+127] // convert C to fp16 +buffer_store_short v127, v250, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v128, v[vgprValuC+128] // convert C to fp16 +buffer_store_short v128, v251, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Edge Batch #1 (d1,d0,vc1,vc0) = */ +/* (0,0,30,2:vw1); (0,0,30,3:vw1); (0,0,31,0:vw1); (0,0,31,1:vw1); (0,0,31,2:vw1); (0,0,31,3:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,30,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v13, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v13, v6, v13, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v14, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v14, v6, v14, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v15, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v15, v6, v15, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v16, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v16, v6, v16, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v17, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v17, v6, v17, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v18, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v18, v6, v18, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+8], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+9], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+10], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+11], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+12], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 30, 2), (0, 0, 30, 3), (0, 0, 31, 0), (0, 0, 31, 1), (0, 0, 31, 2), (0, 0, 31, 3)] */ +v_mul_f32 v[vgprValuC+7], s[sgprAlpha], v[vgprValuC+7] // *= alpha +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_mul_f32 v[vgprValuC+12], s[sgprAlpha], v[vgprValuC+12] // *= alpha + +/* apply mask, calc new C and issue writes */ +v_cvt_f16_f32 v7, v[vgprValuC+7] // convert C to fp16 +buffer_store_short v7, v13, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v8, v[vgprValuC+8] // convert C to fp16 +buffer_store_short v8, v14, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v9, v[vgprValuC+9] // convert C to fp16 +buffer_store_short v9, v15, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v10, v[vgprValuC+10] // convert C to fp16 +buffer_store_short v10, v16, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v11, v[vgprValuC+11] // convert C to fp16 +buffer_store_short v11, v17, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_cvt_f16_f32 v12, v[vgprValuC+12] // convert C to fp16 +buffer_store_short v12, v18, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_GW_B1: +label_GW_B1_FD0: +s_and_b32 s64, 127, s[sgprSizeI] // s64 = s[sgprSizeI] % 128 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups0] +s_cmp_ge_u32 s[sgprWorkGroup0], s65 // wg0 >= nwg0-1 ? +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B1_FD0_VW4_Else // jump if edges required +s_and_b32 s64, 255, s[sgprSizeJ] // s64 = s[sgprSizeJ] % 256 +s_add_u32 s65, -0x1, s[sgprNumWorkGroups1] +s_cmp_ge_u32 s[sgprWorkGroup1], s65 // wg1 >= nwg1-1 +s_cselect_b32 s64, s64, 0 // set rem +s_cmpk_gt_u32 s64, 0 // rem > 0 +s_cbranch_scc1 label_GW_B1_FD0_VW4_Then // jump if edges required +label_GW_B1_FD0_VW4_NonEdge: + +/* edge=0, allocate 2 sgpr. perBatchTmpS=2 perBatchMaskS=0 perElementMaskS=0 elementsPerBatch=38 */ +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 factorDim=0 */ + +/******************************************/ +/* Global Write Beta Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_add_lshl_u32 v8, v2, v0, 1 // optSingleColVgpr scaleToBpe: sharedAddrVgpr <- cinRowPtr + coord0, scaled by BPE. BSHERE:coord0=0, coord0Vgpr=0 (multiple bpe) +buffer_load_dwordx2 v[10:11], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[140:141], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[142:143], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[144:145], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[146:147], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[148:149], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[150:151], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[152:153], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[154:155], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[156:157], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[158:159], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[160:161], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[162:163], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[164:165], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[166:167], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[168:169], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[170:171], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[172:173], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[174:175], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[176:177], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[178:179], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[180:181], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[182:183], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[186:187], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[188:189], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[190:191], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[192:193], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[194:195], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[196:197], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[198:199], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[200:201], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +s_lshl_b32 s8, s[sgprStrideC1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdC+0], s[sgprSrdC+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdC+1], s[sgprSrdC+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_load_dwordx2 v[202:203], v8, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v7, v3, v0, 1 // optSingleColVgpr scaleToBpe: sharedAddrVgpr <- cinRowPtr + coord0, scaled by BPE. BSHERE:coord0=0, coord0Vgpr=0 (multiple bpe) +v_accvgpr_read_b32 v[vgprValuC+12], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+13], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+14], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+15], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+16], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+17], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+18], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+19], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+20], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+21], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+22], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+23], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+24], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+25], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+26], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+27], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+28], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+29], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+30], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+31], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+32], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+33], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+34], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+35], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+36], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+37], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+38], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+39], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+40], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+41], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+42], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+43], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+44], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+45], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+46], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+47], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+48], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+49], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+50], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+51], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+52], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+53], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+54], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+55], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+56], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+57], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+58], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+59], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+60], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+61], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+62], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+63], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+64], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+65], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+66], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+67], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+68], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+69], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+70], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+71], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+72], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+73], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+74], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+75], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+76], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+77], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+78], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+79], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+80], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+81], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+82], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+83], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+84], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+85], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+86], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+87], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+88], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+89], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+90], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+91], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+92], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+93], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+94], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+95], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+96], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+97], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+98], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+99], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+100], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+101], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+102], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+103], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+104], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+105], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+106], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+107], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+108], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+109], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+110], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+111], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+112], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+113], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+114], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+115], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+116], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+117], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+118], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+119], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+120], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+121], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+122], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+123], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+124], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+125], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+126], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+127], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+128], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+129], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+130], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+131], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+132], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+133], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+134], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+135], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+136], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+137], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+138], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+139], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+88:vgprValuC+88+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+88:vgprValuC+88+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+90:vgprValuC+90+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+90:vgprValuC+90+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+92:vgprValuC+92+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+92:vgprValuC+92+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+94:vgprValuC+94+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+94:vgprValuC+94+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+96:vgprValuC+96+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+96:vgprValuC+96+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+98:vgprValuC+98+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+98:vgprValuC+98+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+100:vgprValuC+100+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+100:vgprValuC+100+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+102:vgprValuC+102+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+102:vgprValuC+102+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+104:vgprValuC+104+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+104:vgprValuC+104+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+106:vgprValuC+106+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+106:vgprValuC+106+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+108:vgprValuC+108+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+108:vgprValuC+108+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+110:vgprValuC+110+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+110:vgprValuC+110+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+112:vgprValuC+112+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+112:vgprValuC+112+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+114:vgprValuC+114+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+114:vgprValuC+114+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+116:vgprValuC+116+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+116:vgprValuC+116+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+118:vgprValuC+118+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+118:vgprValuC+118+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+120:vgprValuC+120+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+120:vgprValuC+120+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+122:vgprValuC+122+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+122:vgprValuC+122+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+124:vgprValuC+124+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+124:vgprValuC+124+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+126:vgprValuC+126+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+126:vgprValuC+126+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+128:vgprValuC+128+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+128:vgprValuC+128+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+130:vgprValuC+130+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+130:vgprValuC+130+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+132:vgprValuC+132+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+132:vgprValuC+132+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+134:vgprValuC+134+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+134:vgprValuC+134+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+136:vgprValuC+136+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+136:vgprValuC+136+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+138:vgprValuC+138+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+138:vgprValuC+138+1] op_sel_hi:[0,1,1] // *= alpha (pk) + +/* apply mask, calc new C and issue writes */ + +s_waitcnt vmcnt(31) // vlcnt(31) = 32 - 1 (beta) vscnt(0) (interleaved) +v_fma_mix_f32 v[vgprValuC+12], s[sgprBeta], v10, v[vgprValuC+12] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+13], s[sgprBeta], v10, v[vgprValuC+13] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+14], s[sgprBeta], v11, v[vgprValuC+14] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+15], s[sgprBeta], v11, v[vgprValuC+15] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+12], v[vgprValuC+12] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+13], v[vgprValuC+13] // convert C to fp16 +v_pack_b32_f16 v12, v[vgprValuC+12], v[vgprValuC+13] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+14], v[vgprValuC+14] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+15], v[vgprValuC+15] // convert C to fp16 +v_pack_b32_f16 v13, v[vgprValuC+14], v[vgprValuC+15] // Pack with neighbor +buffer_store_dwordx2 v[12:13], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(30) = 32 - 2 (beta) vscnt(1) (interleaved) +v_fma_mix_f32 v[vgprValuC+16], s[sgprBeta], v140, v[vgprValuC+16] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+17], s[sgprBeta], v140, v[vgprValuC+17] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+18], s[sgprBeta], v141, v[vgprValuC+18] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+19], s[sgprBeta], v141, v[vgprValuC+19] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+16], v[vgprValuC+16] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+17], v[vgprValuC+17] // convert C to fp16 +v_pack_b32_f16 v16, v[vgprValuC+16], v[vgprValuC+17] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+18], v[vgprValuC+18] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+19], v[vgprValuC+19] // convert C to fp16 +v_pack_b32_f16 v17, v[vgprValuC+18], v[vgprValuC+19] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[16:17], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(29) = 32 - 3 (beta) vscnt(2) (interleaved) +v_fma_mix_f32 v[vgprValuC+20], s[sgprBeta], v142, v[vgprValuC+20] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+21], s[sgprBeta], v142, v[vgprValuC+21] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+22], s[sgprBeta], v143, v[vgprValuC+22] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+23], s[sgprBeta], v143, v[vgprValuC+23] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+20], v[vgprValuC+20] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+21], v[vgprValuC+21] // convert C to fp16 +v_pack_b32_f16 v20, v[vgprValuC+20], v[vgprValuC+21] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+22], v[vgprValuC+22] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+23], v[vgprValuC+23] // convert C to fp16 +v_pack_b32_f16 v21, v[vgprValuC+22], v[vgprValuC+23] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[20:21], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(28) = 32 - 4 (beta) vscnt(3) (interleaved) +v_fma_mix_f32 v[vgprValuC+24], s[sgprBeta], v144, v[vgprValuC+24] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+25], s[sgprBeta], v144, v[vgprValuC+25] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+26], s[sgprBeta], v145, v[vgprValuC+26] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+27], s[sgprBeta], v145, v[vgprValuC+27] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+24], v[vgprValuC+24] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+25], v[vgprValuC+25] // convert C to fp16 +v_pack_b32_f16 v24, v[vgprValuC+24], v[vgprValuC+25] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+26], v[vgprValuC+26] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+27], v[vgprValuC+27] // convert C to fp16 +v_pack_b32_f16 v25, v[vgprValuC+26], v[vgprValuC+27] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[24:25], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(27) = 32 - 5 (beta) vscnt(4) (interleaved) +v_fma_mix_f32 v[vgprValuC+28], s[sgprBeta], v146, v[vgprValuC+28] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+29], s[sgprBeta], v146, v[vgprValuC+29] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+30], s[sgprBeta], v147, v[vgprValuC+30] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+31], s[sgprBeta], v147, v[vgprValuC+31] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+28], v[vgprValuC+28] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+29], v[vgprValuC+29] // convert C to fp16 +v_pack_b32_f16 v28, v[vgprValuC+28], v[vgprValuC+29] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+30], v[vgprValuC+30] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+31], v[vgprValuC+31] // convert C to fp16 +v_pack_b32_f16 v29, v[vgprValuC+30], v[vgprValuC+31] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[28:29], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(26) = 32 - 6 (beta) vscnt(5) (interleaved) +v_fma_mix_f32 v[vgprValuC+32], s[sgprBeta], v148, v[vgprValuC+32] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+33], s[sgprBeta], v148, v[vgprValuC+33] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+34], s[sgprBeta], v149, v[vgprValuC+34] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+35], s[sgprBeta], v149, v[vgprValuC+35] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+32], v[vgprValuC+32] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+33], v[vgprValuC+33] // convert C to fp16 +v_pack_b32_f16 v32, v[vgprValuC+32], v[vgprValuC+33] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+34], v[vgprValuC+34] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+35], v[vgprValuC+35] // convert C to fp16 +v_pack_b32_f16 v33, v[vgprValuC+34], v[vgprValuC+35] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[32:33], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(25) = 32 - 7 (beta) vscnt(6) (interleaved) +v_fma_mix_f32 v[vgprValuC+36], s[sgprBeta], v150, v[vgprValuC+36] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+37], s[sgprBeta], v150, v[vgprValuC+37] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+38], s[sgprBeta], v151, v[vgprValuC+38] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+39], s[sgprBeta], v151, v[vgprValuC+39] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+36], v[vgprValuC+36] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+37], v[vgprValuC+37] // convert C to fp16 +v_pack_b32_f16 v36, v[vgprValuC+36], v[vgprValuC+37] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+38], v[vgprValuC+38] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+39], v[vgprValuC+39] // convert C to fp16 +v_pack_b32_f16 v37, v[vgprValuC+38], v[vgprValuC+39] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[36:37], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(24) = 32 - 8 (beta) vscnt(7) (interleaved) +v_fma_mix_f32 v[vgprValuC+40], s[sgprBeta], v152, v[vgprValuC+40] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+41], s[sgprBeta], v152, v[vgprValuC+41] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+42], s[sgprBeta], v153, v[vgprValuC+42] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+43], s[sgprBeta], v153, v[vgprValuC+43] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+40], v[vgprValuC+40] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+41], v[vgprValuC+41] // convert C to fp16 +v_pack_b32_f16 v40, v[vgprValuC+40], v[vgprValuC+41] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+42], v[vgprValuC+42] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+43], v[vgprValuC+43] // convert C to fp16 +v_pack_b32_f16 v41, v[vgprValuC+42], v[vgprValuC+43] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[40:41], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(23) = 32 - 9 (beta) vscnt(8) (interleaved) +v_fma_mix_f32 v[vgprValuC+44], s[sgprBeta], v154, v[vgprValuC+44] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+45], s[sgprBeta], v154, v[vgprValuC+45] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+46], s[sgprBeta], v155, v[vgprValuC+46] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+47], s[sgprBeta], v155, v[vgprValuC+47] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+44], v[vgprValuC+44] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+45], v[vgprValuC+45] // convert C to fp16 +v_pack_b32_f16 v44, v[vgprValuC+44], v[vgprValuC+45] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+46], v[vgprValuC+46] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+47], v[vgprValuC+47] // convert C to fp16 +v_pack_b32_f16 v45, v[vgprValuC+46], v[vgprValuC+47] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[44:45], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(22) = 32 - 10 (beta) vscnt(9) (interleaved) +v_fma_mix_f32 v[vgprValuC+48], s[sgprBeta], v156, v[vgprValuC+48] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+49], s[sgprBeta], v156, v[vgprValuC+49] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+50], s[sgprBeta], v157, v[vgprValuC+50] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+51], s[sgprBeta], v157, v[vgprValuC+51] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+48], v[vgprValuC+48] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+49], v[vgprValuC+49] // convert C to fp16 +v_pack_b32_f16 v48, v[vgprValuC+48], v[vgprValuC+49] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+50], v[vgprValuC+50] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+51], v[vgprValuC+51] // convert C to fp16 +v_pack_b32_f16 v49, v[vgprValuC+50], v[vgprValuC+51] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[48:49], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(21) = 32 - 11 (beta) vscnt(10) (interleaved) +v_fma_mix_f32 v[vgprValuC+52], s[sgprBeta], v158, v[vgprValuC+52] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+53], s[sgprBeta], v158, v[vgprValuC+53] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+54], s[sgprBeta], v159, v[vgprValuC+54] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+55], s[sgprBeta], v159, v[vgprValuC+55] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+52], v[vgprValuC+52] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+53], v[vgprValuC+53] // convert C to fp16 +v_pack_b32_f16 v52, v[vgprValuC+52], v[vgprValuC+53] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+54], v[vgprValuC+54] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+55], v[vgprValuC+55] // convert C to fp16 +v_pack_b32_f16 v53, v[vgprValuC+54], v[vgprValuC+55] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[52:53], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(20) = 32 - 12 (beta) vscnt(11) (interleaved) +v_fma_mix_f32 v[vgprValuC+56], s[sgprBeta], v160, v[vgprValuC+56] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+57], s[sgprBeta], v160, v[vgprValuC+57] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+58], s[sgprBeta], v161, v[vgprValuC+58] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+59], s[sgprBeta], v161, v[vgprValuC+59] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+56], v[vgprValuC+56] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+57], v[vgprValuC+57] // convert C to fp16 +v_pack_b32_f16 v56, v[vgprValuC+56], v[vgprValuC+57] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+58], v[vgprValuC+58] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+59], v[vgprValuC+59] // convert C to fp16 +v_pack_b32_f16 v57, v[vgprValuC+58], v[vgprValuC+59] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[56:57], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(19) = 32 - 13 (beta) vscnt(12) (interleaved) +v_fma_mix_f32 v[vgprValuC+60], s[sgprBeta], v162, v[vgprValuC+60] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+61], s[sgprBeta], v162, v[vgprValuC+61] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+62], s[sgprBeta], v163, v[vgprValuC+62] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+63], s[sgprBeta], v163, v[vgprValuC+63] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+60], v[vgprValuC+60] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+61], v[vgprValuC+61] // convert C to fp16 +v_pack_b32_f16 v60, v[vgprValuC+60], v[vgprValuC+61] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+62], v[vgprValuC+62] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+63], v[vgprValuC+63] // convert C to fp16 +v_pack_b32_f16 v61, v[vgprValuC+62], v[vgprValuC+63] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[60:61], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(18) = 32 - 14 (beta) vscnt(13) (interleaved) +v_fma_mix_f32 v[vgprValuC+64], s[sgprBeta], v164, v[vgprValuC+64] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+65], s[sgprBeta], v164, v[vgprValuC+65] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+66], s[sgprBeta], v165, v[vgprValuC+66] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+67], s[sgprBeta], v165, v[vgprValuC+67] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+64], v[vgprValuC+64] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+65], v[vgprValuC+65] // convert C to fp16 +v_pack_b32_f16 v64, v[vgprValuC+64], v[vgprValuC+65] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+66], v[vgprValuC+66] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+67], v[vgprValuC+67] // convert C to fp16 +v_pack_b32_f16 v65, v[vgprValuC+66], v[vgprValuC+67] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[64:65], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(17) = 32 - 15 (beta) vscnt(14) (interleaved) +v_fma_mix_f32 v[vgprValuC+68], s[sgprBeta], v166, v[vgprValuC+68] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+69], s[sgprBeta], v166, v[vgprValuC+69] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+70], s[sgprBeta], v167, v[vgprValuC+70] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+71], s[sgprBeta], v167, v[vgprValuC+71] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+68], v[vgprValuC+68] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+69], v[vgprValuC+69] // convert C to fp16 +v_pack_b32_f16 v68, v[vgprValuC+68], v[vgprValuC+69] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+70], v[vgprValuC+70] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+71], v[vgprValuC+71] // convert C to fp16 +v_pack_b32_f16 v69, v[vgprValuC+70], v[vgprValuC+71] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[68:69], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(16) = 32 - 16 (beta) vscnt(15) (interleaved) +v_fma_mix_f32 v[vgprValuC+72], s[sgprBeta], v168, v[vgprValuC+72] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+73], s[sgprBeta], v168, v[vgprValuC+73] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+74], s[sgprBeta], v169, v[vgprValuC+74] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+75], s[sgprBeta], v169, v[vgprValuC+75] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+72], v[vgprValuC+72] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+73], v[vgprValuC+73] // convert C to fp16 +v_pack_b32_f16 v72, v[vgprValuC+72], v[vgprValuC+73] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+74], v[vgprValuC+74] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+75], v[vgprValuC+75] // convert C to fp16 +v_pack_b32_f16 v73, v[vgprValuC+74], v[vgprValuC+75] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[72:73], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(15) = 32 - 17 (beta) vscnt(16) (interleaved) +v_fma_mix_f32 v[vgprValuC+76], s[sgprBeta], v170, v[vgprValuC+76] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+77], s[sgprBeta], v170, v[vgprValuC+77] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+78], s[sgprBeta], v171, v[vgprValuC+78] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+79], s[sgprBeta], v171, v[vgprValuC+79] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+76], v[vgprValuC+76] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+77], v[vgprValuC+77] // convert C to fp16 +v_pack_b32_f16 v76, v[vgprValuC+76], v[vgprValuC+77] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+78], v[vgprValuC+78] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+79], v[vgprValuC+79] // convert C to fp16 +v_pack_b32_f16 v77, v[vgprValuC+78], v[vgprValuC+79] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[76:77], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(14) = 32 - 18 (beta) vscnt(17) (interleaved) +v_fma_mix_f32 v[vgprValuC+80], s[sgprBeta], v172, v[vgprValuC+80] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+81], s[sgprBeta], v172, v[vgprValuC+81] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+82], s[sgprBeta], v173, v[vgprValuC+82] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+83], s[sgprBeta], v173, v[vgprValuC+83] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+80], v[vgprValuC+80] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+81], v[vgprValuC+81] // convert C to fp16 +v_pack_b32_f16 v80, v[vgprValuC+80], v[vgprValuC+81] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+82], v[vgprValuC+82] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+83], v[vgprValuC+83] // convert C to fp16 +v_pack_b32_f16 v81, v[vgprValuC+82], v[vgprValuC+83] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[80:81], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(13) = 32 - 19 (beta) vscnt(18) (interleaved) +v_fma_mix_f32 v[vgprValuC+84], s[sgprBeta], v174, v[vgprValuC+84] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+85], s[sgprBeta], v174, v[vgprValuC+85] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+86], s[sgprBeta], v175, v[vgprValuC+86] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+87], s[sgprBeta], v175, v[vgprValuC+87] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+84], v[vgprValuC+84] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+85], v[vgprValuC+85] // convert C to fp16 +v_pack_b32_f16 v84, v[vgprValuC+84], v[vgprValuC+85] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+86], v[vgprValuC+86] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+87], v[vgprValuC+87] // convert C to fp16 +v_pack_b32_f16 v85, v[vgprValuC+86], v[vgprValuC+87] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[84:85], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(12) = 32 - 20 (beta) vscnt(19) (interleaved) +v_fma_mix_f32 v[vgprValuC+88], s[sgprBeta], v176, v[vgprValuC+88] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+89], s[sgprBeta], v176, v[vgprValuC+89] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+90], s[sgprBeta], v177, v[vgprValuC+90] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+91], s[sgprBeta], v177, v[vgprValuC+91] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+88], v[vgprValuC+88] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+89], v[vgprValuC+89] // convert C to fp16 +v_pack_b32_f16 v88, v[vgprValuC+88], v[vgprValuC+89] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+90], v[vgprValuC+90] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+91], v[vgprValuC+91] // convert C to fp16 +v_pack_b32_f16 v89, v[vgprValuC+90], v[vgprValuC+91] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[88:89], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(11) = 32 - 21 (beta) vscnt(20) (interleaved) +v_fma_mix_f32 v[vgprValuC+92], s[sgprBeta], v178, v[vgprValuC+92] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+93], s[sgprBeta], v178, v[vgprValuC+93] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+94], s[sgprBeta], v179, v[vgprValuC+94] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+95], s[sgprBeta], v179, v[vgprValuC+95] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+92], v[vgprValuC+92] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+93], v[vgprValuC+93] // convert C to fp16 +v_pack_b32_f16 v92, v[vgprValuC+92], v[vgprValuC+93] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+94], v[vgprValuC+94] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+95], v[vgprValuC+95] // convert C to fp16 +v_pack_b32_f16 v93, v[vgprValuC+94], v[vgprValuC+95] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[92:93], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(10) = 32 - 22 (beta) vscnt(21) (interleaved) +v_fma_mix_f32 v[vgprValuC+96], s[sgprBeta], v180, v[vgprValuC+96] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+97], s[sgprBeta], v180, v[vgprValuC+97] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+98], s[sgprBeta], v181, v[vgprValuC+98] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+99], s[sgprBeta], v181, v[vgprValuC+99] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+96], v[vgprValuC+96] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+97], v[vgprValuC+97] // convert C to fp16 +v_pack_b32_f16 v96, v[vgprValuC+96], v[vgprValuC+97] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+98], v[vgprValuC+98] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+99], v[vgprValuC+99] // convert C to fp16 +v_pack_b32_f16 v97, v[vgprValuC+98], v[vgprValuC+99] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[96:97], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(9) = 32 - 23 (beta) vscnt(22) (interleaved) +v_fma_mix_f32 v[vgprValuC+100], s[sgprBeta], v182, v[vgprValuC+100] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+101], s[sgprBeta], v182, v[vgprValuC+101] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+102], s[sgprBeta], v183, v[vgprValuC+102] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+103], s[sgprBeta], v183, v[vgprValuC+103] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+100], v[vgprValuC+100] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+101], v[vgprValuC+101] // convert C to fp16 +v_pack_b32_f16 v100, v[vgprValuC+100], v[vgprValuC+101] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+102], v[vgprValuC+102] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+103], v[vgprValuC+103] // convert C to fp16 +v_pack_b32_f16 v101, v[vgprValuC+102], v[vgprValuC+103] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[100:101], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(8) = 32 - 24 (beta) vscnt(23) (interleaved) +v_fma_mix_f32 v[vgprValuC+104], s[sgprBeta], v186, v[vgprValuC+104] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+105], s[sgprBeta], v186, v[vgprValuC+105] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+106], s[sgprBeta], v187, v[vgprValuC+106] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+107], s[sgprBeta], v187, v[vgprValuC+107] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+104], v[vgprValuC+104] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+105], v[vgprValuC+105] // convert C to fp16 +v_pack_b32_f16 v104, v[vgprValuC+104], v[vgprValuC+105] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+106], v[vgprValuC+106] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+107], v[vgprValuC+107] // convert C to fp16 +v_pack_b32_f16 v105, v[vgprValuC+106], v[vgprValuC+107] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[104:105], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(7) = 32 - 25 (beta) vscnt(24) (interleaved) +v_fma_mix_f32 v[vgprValuC+108], s[sgprBeta], v188, v[vgprValuC+108] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+109], s[sgprBeta], v188, v[vgprValuC+109] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+110], s[sgprBeta], v189, v[vgprValuC+110] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+111], s[sgprBeta], v189, v[vgprValuC+111] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+108], v[vgprValuC+108] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+109], v[vgprValuC+109] // convert C to fp16 +v_pack_b32_f16 v108, v[vgprValuC+108], v[vgprValuC+109] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+110], v[vgprValuC+110] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+111], v[vgprValuC+111] // convert C to fp16 +v_pack_b32_f16 v109, v[vgprValuC+110], v[vgprValuC+111] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[108:109], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(6) = 32 - 26 (beta) vscnt(25) (interleaved) +v_fma_mix_f32 v[vgprValuC+112], s[sgprBeta], v190, v[vgprValuC+112] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+113], s[sgprBeta], v190, v[vgprValuC+113] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+114], s[sgprBeta], v191, v[vgprValuC+114] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+115], s[sgprBeta], v191, v[vgprValuC+115] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+112], v[vgprValuC+112] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+113], v[vgprValuC+113] // convert C to fp16 +v_pack_b32_f16 v112, v[vgprValuC+112], v[vgprValuC+113] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+114], v[vgprValuC+114] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+115], v[vgprValuC+115] // convert C to fp16 +v_pack_b32_f16 v113, v[vgprValuC+114], v[vgprValuC+115] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[112:113], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(5) = 32 - 27 (beta) vscnt(26) (interleaved) +v_fma_mix_f32 v[vgprValuC+116], s[sgprBeta], v192, v[vgprValuC+116] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+117], s[sgprBeta], v192, v[vgprValuC+117] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+118], s[sgprBeta], v193, v[vgprValuC+118] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+119], s[sgprBeta], v193, v[vgprValuC+119] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+116], v[vgprValuC+116] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+117], v[vgprValuC+117] // convert C to fp16 +v_pack_b32_f16 v116, v[vgprValuC+116], v[vgprValuC+117] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+118], v[vgprValuC+118] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+119], v[vgprValuC+119] // convert C to fp16 +v_pack_b32_f16 v117, v[vgprValuC+118], v[vgprValuC+119] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[116:117], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(4) = 32 - 28 (beta) vscnt(27) (interleaved) +v_fma_mix_f32 v[vgprValuC+120], s[sgprBeta], v194, v[vgprValuC+120] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+121], s[sgprBeta], v194, v[vgprValuC+121] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+122], s[sgprBeta], v195, v[vgprValuC+122] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+123], s[sgprBeta], v195, v[vgprValuC+123] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+120], v[vgprValuC+120] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+121], v[vgprValuC+121] // convert C to fp16 +v_pack_b32_f16 v120, v[vgprValuC+120], v[vgprValuC+121] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+122], v[vgprValuC+122] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+123], v[vgprValuC+123] // convert C to fp16 +v_pack_b32_f16 v121, v[vgprValuC+122], v[vgprValuC+123] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[120:121], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(3) = 32 - 29 (beta) vscnt(28) (interleaved) +v_fma_mix_f32 v[vgprValuC+124], s[sgprBeta], v196, v[vgprValuC+124] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+125], s[sgprBeta], v196, v[vgprValuC+125] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+126], s[sgprBeta], v197, v[vgprValuC+126] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+127], s[sgprBeta], v197, v[vgprValuC+127] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+124], v[vgprValuC+124] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+125], v[vgprValuC+125] // convert C to fp16 +v_pack_b32_f16 v124, v[vgprValuC+124], v[vgprValuC+125] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+126], v[vgprValuC+126] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+127], v[vgprValuC+127] // convert C to fp16 +v_pack_b32_f16 v125, v[vgprValuC+126], v[vgprValuC+127] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[124:125], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(2) = 32 - 30 (beta) vscnt(29) (interleaved) +v_fma_mix_f32 v[vgprValuC+128], s[sgprBeta], v198, v[vgprValuC+128] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+129], s[sgprBeta], v198, v[vgprValuC+129] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+130], s[sgprBeta], v199, v[vgprValuC+130] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+131], s[sgprBeta], v199, v[vgprValuC+131] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+128], v[vgprValuC+128] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+129], v[vgprValuC+129] // convert C to fp16 +v_pack_b32_f16 v128, v[vgprValuC+128], v[vgprValuC+129] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+130], v[vgprValuC+130] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+131], v[vgprValuC+131] // convert C to fp16 +v_pack_b32_f16 v129, v[vgprValuC+130], v[vgprValuC+131] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[128:129], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(1) = 32 - 31 (beta) vscnt(30) (interleaved) +v_fma_mix_f32 v[vgprValuC+132], s[sgprBeta], v200, v[vgprValuC+132] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+133], s[sgprBeta], v200, v[vgprValuC+133] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+134], s[sgprBeta], v201, v[vgprValuC+134] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+135], s[sgprBeta], v201, v[vgprValuC+135] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+132], v[vgprValuC+132] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+133], v[vgprValuC+133] // convert C to fp16 +v_pack_b32_f16 v132, v[vgprValuC+132], v[vgprValuC+133] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+134], v[vgprValuC+134] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+135], v[vgprValuC+135] // convert C to fp16 +v_pack_b32_f16 v133, v[vgprValuC+134], v[vgprValuC+135] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[132:133], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D + +s_waitcnt vmcnt(31) // vlcnt(0) = 32 - 32 (beta) vscnt(31) (interleaved) +v_fma_mix_f32 v[vgprValuC+136], s[sgprBeta], v202, v[vgprValuC+136] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+137], s[sgprBeta], v202, v[vgprValuC+137] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+138], s[sgprBeta], v203, v[vgprValuC+138] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+139], s[sgprBeta], v203, v[vgprValuC+139] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+136], v[vgprValuC+136] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+137], v[vgprValuC+137] // convert C to fp16 +v_pack_b32_f16 v136, v[vgprValuC+136], v[vgprValuC+137] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+138], v[vgprValuC+138] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+139], v[vgprValuC+139] // convert C to fp16 +v_pack_b32_f16 v137, v[vgprValuC+138], v[vgprValuC+139] // Pack with neighbor +s_lshl_b32 s8, s[sgprStrideD1J], 1 // incToNextRow: Scale by BPE +s_add_u32 s[sgprSrdD+0], s[sgprSrdD+0], s8 // incToNextRow: gra SRD += inc(lower) +s_addc_u32 s[sgprSrdD+1], s[sgprSrdD+1], 0 // incToNextRow: gra SRD += inc(upper) +buffer_store_dwordx2 v[136:137], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_GW_B1_FD0_VW4_NonEdgeEnd: +label_GW_B1_FD0_VW4_Then: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=34 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Beta Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v7, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v7, v6, v7, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[136:137], v7, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v7, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v7, v6, v7, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[138:139], v140, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v140, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v141, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[142:143], v141, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v141, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v141, v6, v141, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[144:145], v146, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v146, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v147, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[148:149], v147, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v147, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v147, v6, v147, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[150:151], v152, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v152, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v153, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[154:155], v153, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v153, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v153, v6, v153, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[156:157], v158, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v158, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v159, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[160:161], v159, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v159, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v159, v6, v159, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[162:163], v164, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v164, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v165, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[166:167], v165, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v165, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v165, v6, v165, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v170, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[168:169], v170, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v170, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v171, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v171, v6, v171, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[172:173], v171, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v171, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v171, v6, v171, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v176, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[174:175], v176, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v176, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v177, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v177, v6, v177, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[178:179], v177, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v177, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v177, v6, v177, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v182, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[180:181], v182, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v182, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v183, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v183, v6, v183, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[186:187], v183, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v183, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v183, v6, v183, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v185, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[188:189], v185, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v185, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v192, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v192, v6, v192, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[190:191], v192, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v192, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v192, v6, v192, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v193, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[194:195], v193, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v193, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v198, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v198, v6, v198, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[196:197], v198, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v198, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v198, v6, v198, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v199, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[200:201], v199, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v199, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v204, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v204, v6, v204, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[202:203], v204, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v204, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v204, v6, v204, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v205, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[206:207], v205, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v205, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v210, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v210, v6, v210, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[208:209], v210, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v210, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v210, v6, v210, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v211, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[212:213], v211, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v211, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v216, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v216, v6, v216, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[214:215], v216, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v216, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v216, v6, v216, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v217, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[218:219], v217, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v217, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v222, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v222, v6, v222, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[220:221], v222, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v222, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v222, v6, v222, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v223, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[224:225], v223, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v223, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v228, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v228, v6, v228, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[226:227], v228, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v228, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v228, v6, v228, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v229, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDC clip if OOB. offset +buffer_load_dwordx2 v[230:231], v229, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v229, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+8], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+9], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+10], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+11], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+12], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+13], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+14], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+15], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+16], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+17], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+18], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+19], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+20], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+21], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+22], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+23], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+24], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+25], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+26], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+27], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+28], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+29], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+30], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+31], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+32], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+33], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+34], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+35], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+36], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+37], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+38], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+39], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+40], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+41], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+42], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+43], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+44], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+45], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+46], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+47], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+48], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+49], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+50], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+51], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+52], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+53], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+54], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+55], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+56], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+57], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+58], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+59], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+60], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+61], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+62], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+63], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+64], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+65], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+66], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+67], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+68], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+69], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+70], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+71], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+72], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+73], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+74], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+75], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+76], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+77], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+78], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+79], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+80], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+81], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+82], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+83], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+84], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+85], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+86], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+87], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+88], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+89], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+90], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+91], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+92], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+93], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+94], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+95], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+96], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+97], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+98], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+99], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+100], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+101], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+102], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+103], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+104], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+105], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+106], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+107], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+108], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+109], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+110], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+111], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+112], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+113], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+114], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+115], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+116], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+117], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+118], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+119], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+120], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+121], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+122], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+123], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+124], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+125], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+126], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+127], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+128], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+129], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+130], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+131], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+132], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+133], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+134], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+135], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 1, 0), (0, 0, 2, 0), (0, 0, 3, 0), (0, 0, 4, 0), (0, 0, 5, 0), (0, 0, 6, 0), (0, 0, 7, 0), (0, 0, 8, 0), (0, 0, 9, 0), (0, 0, 10, 0), (0, 0, 11, 0), (0, 0, 12, 0), (0, 0, 13, 0), (0, 0, 14, 0), (0, 0, 15, 0), (0, 0, 16, 0), (0, 0, 17, 0), (0, 0, 18, 0), (0, 0, 19, 0), (0, 0, 20, 0), (0, 0, 21, 0), (0, 0, 22, 0), (0, 0, 23, 0), (0, 0, 24, 0), (0, 0, 25, 0), (0, 0, 26, 0), (0, 0, 27, 0), (0, 0, 28, 0), (0, 0, 29, 0), (0, 0, 30, 0), (0, 0, 31, 0)] */ +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+88:vgprValuC+88+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+88:vgprValuC+88+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+90:vgprValuC+90+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+90:vgprValuC+90+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+92:vgprValuC+92+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+92:vgprValuC+92+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+94:vgprValuC+94+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+94:vgprValuC+94+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+96:vgprValuC+96+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+96:vgprValuC+96+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+98:vgprValuC+98+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+98:vgprValuC+98+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+100:vgprValuC+100+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+100:vgprValuC+100+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+102:vgprValuC+102+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+102:vgprValuC+102+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+104:vgprValuC+104+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+104:vgprValuC+104+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+106:vgprValuC+106+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+106:vgprValuC+106+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+108:vgprValuC+108+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+108:vgprValuC+108+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+110:vgprValuC+110+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+110:vgprValuC+110+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+112:vgprValuC+112+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+112:vgprValuC+112+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+114:vgprValuC+114+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+114:vgprValuC+114+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+116:vgprValuC+116+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+116:vgprValuC+116+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+118:vgprValuC+118+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+118:vgprValuC+118+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+120:vgprValuC+120+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+120:vgprValuC+120+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+122:vgprValuC+122+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+122:vgprValuC+122+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+124:vgprValuC+124+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+124:vgprValuC+124+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+126:vgprValuC+126+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+126:vgprValuC+126+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+128:vgprValuC+128+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+128:vgprValuC+128+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+130:vgprValuC+130+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+130:vgprValuC+130+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+132:vgprValuC+132+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+132:vgprValuC+132+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+134:vgprValuC+134+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+134:vgprValuC+134+1] op_sel_hi:[0,1,1] // *= alpha (pk) +s_waitcnt vmcnt(0) // wait for Beta + +/* apply mask, calc new C and issue writes */ +v_fma_mix_f32 v[vgprValuC+8], s[sgprBeta], v136, v[vgprValuC+8] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+9], s[sgprBeta], v136, v[vgprValuC+9] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+10], s[sgprBeta], v137, v[vgprValuC+10] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+11], s[sgprBeta], v137, v[vgprValuC+11] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+8], v[vgprValuC+8] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+9], v[vgprValuC+9] // convert C to fp16 +v_pack_b32_f16 v8, v[vgprValuC+8], v[vgprValuC+9] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+10], v[vgprValuC+10] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+11], v[vgprValuC+11] // convert C to fp16 +v_pack_b32_f16 v9, v[vgprValuC+10], v[vgprValuC+11] // Pack with neighbor +buffer_store_dwordx2 v[8:9], v7, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+12], s[sgprBeta], v138, v[vgprValuC+12] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+13], s[sgprBeta], v138, v[vgprValuC+13] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+14], s[sgprBeta], v139, v[vgprValuC+14] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+15], s[sgprBeta], v139, v[vgprValuC+15] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+12], v[vgprValuC+12] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+13], v[vgprValuC+13] // convert C to fp16 +v_pack_b32_f16 v12, v[vgprValuC+12], v[vgprValuC+13] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+14], v[vgprValuC+14] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+15], v[vgprValuC+15] // convert C to fp16 +v_pack_b32_f16 v13, v[vgprValuC+14], v[vgprValuC+15] // Pack with neighbor +buffer_store_dwordx2 v[12:13], v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+16], s[sgprBeta], v142, v[vgprValuC+16] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+17], s[sgprBeta], v142, v[vgprValuC+17] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+18], s[sgprBeta], v143, v[vgprValuC+18] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+19], s[sgprBeta], v143, v[vgprValuC+19] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+16], v[vgprValuC+16] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+17], v[vgprValuC+17] // convert C to fp16 +v_pack_b32_f16 v16, v[vgprValuC+16], v[vgprValuC+17] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+18], v[vgprValuC+18] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+19], v[vgprValuC+19] // convert C to fp16 +v_pack_b32_f16 v17, v[vgprValuC+18], v[vgprValuC+19] // Pack with neighbor +buffer_store_dwordx2 v[16:17], v141, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+20], s[sgprBeta], v144, v[vgprValuC+20] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+21], s[sgprBeta], v144, v[vgprValuC+21] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+22], s[sgprBeta], v145, v[vgprValuC+22] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+23], s[sgprBeta], v145, v[vgprValuC+23] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+20], v[vgprValuC+20] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+21], v[vgprValuC+21] // convert C to fp16 +v_pack_b32_f16 v20, v[vgprValuC+20], v[vgprValuC+21] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+22], v[vgprValuC+22] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+23], v[vgprValuC+23] // convert C to fp16 +v_pack_b32_f16 v21, v[vgprValuC+22], v[vgprValuC+23] // Pack with neighbor +buffer_store_dwordx2 v[20:21], v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+24], s[sgprBeta], v148, v[vgprValuC+24] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+25], s[sgprBeta], v148, v[vgprValuC+25] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+26], s[sgprBeta], v149, v[vgprValuC+26] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+27], s[sgprBeta], v149, v[vgprValuC+27] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+24], v[vgprValuC+24] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+25], v[vgprValuC+25] // convert C to fp16 +v_pack_b32_f16 v24, v[vgprValuC+24], v[vgprValuC+25] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+26], v[vgprValuC+26] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+27], v[vgprValuC+27] // convert C to fp16 +v_pack_b32_f16 v25, v[vgprValuC+26], v[vgprValuC+27] // Pack with neighbor +buffer_store_dwordx2 v[24:25], v147, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+28], s[sgprBeta], v150, v[vgprValuC+28] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+29], s[sgprBeta], v150, v[vgprValuC+29] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+30], s[sgprBeta], v151, v[vgprValuC+30] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+31], s[sgprBeta], v151, v[vgprValuC+31] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+28], v[vgprValuC+28] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+29], v[vgprValuC+29] // convert C to fp16 +v_pack_b32_f16 v28, v[vgprValuC+28], v[vgprValuC+29] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+30], v[vgprValuC+30] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+31], v[vgprValuC+31] // convert C to fp16 +v_pack_b32_f16 v29, v[vgprValuC+30], v[vgprValuC+31] // Pack with neighbor +buffer_store_dwordx2 v[28:29], v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+32], s[sgprBeta], v154, v[vgprValuC+32] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+33], s[sgprBeta], v154, v[vgprValuC+33] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+34], s[sgprBeta], v155, v[vgprValuC+34] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+35], s[sgprBeta], v155, v[vgprValuC+35] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+32], v[vgprValuC+32] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+33], v[vgprValuC+33] // convert C to fp16 +v_pack_b32_f16 v32, v[vgprValuC+32], v[vgprValuC+33] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+34], v[vgprValuC+34] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+35], v[vgprValuC+35] // convert C to fp16 +v_pack_b32_f16 v33, v[vgprValuC+34], v[vgprValuC+35] // Pack with neighbor +buffer_store_dwordx2 v[32:33], v153, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+36], s[sgprBeta], v156, v[vgprValuC+36] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+37], s[sgprBeta], v156, v[vgprValuC+37] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+38], s[sgprBeta], v157, v[vgprValuC+38] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+39], s[sgprBeta], v157, v[vgprValuC+39] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+36], v[vgprValuC+36] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+37], v[vgprValuC+37] // convert C to fp16 +v_pack_b32_f16 v36, v[vgprValuC+36], v[vgprValuC+37] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+38], v[vgprValuC+38] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+39], v[vgprValuC+39] // convert C to fp16 +v_pack_b32_f16 v37, v[vgprValuC+38], v[vgprValuC+39] // Pack with neighbor +buffer_store_dwordx2 v[36:37], v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+40], s[sgprBeta], v160, v[vgprValuC+40] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+41], s[sgprBeta], v160, v[vgprValuC+41] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+42], s[sgprBeta], v161, v[vgprValuC+42] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+43], s[sgprBeta], v161, v[vgprValuC+43] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+40], v[vgprValuC+40] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+41], v[vgprValuC+41] // convert C to fp16 +v_pack_b32_f16 v40, v[vgprValuC+40], v[vgprValuC+41] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+42], v[vgprValuC+42] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+43], v[vgprValuC+43] // convert C to fp16 +v_pack_b32_f16 v41, v[vgprValuC+42], v[vgprValuC+43] // Pack with neighbor +buffer_store_dwordx2 v[40:41], v159, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+44], s[sgprBeta], v162, v[vgprValuC+44] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+45], s[sgprBeta], v162, v[vgprValuC+45] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+46], s[sgprBeta], v163, v[vgprValuC+46] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+47], s[sgprBeta], v163, v[vgprValuC+47] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+44], v[vgprValuC+44] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+45], v[vgprValuC+45] // convert C to fp16 +v_pack_b32_f16 v44, v[vgprValuC+44], v[vgprValuC+45] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+46], v[vgprValuC+46] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+47], v[vgprValuC+47] // convert C to fp16 +v_pack_b32_f16 v45, v[vgprValuC+46], v[vgprValuC+47] // Pack with neighbor +buffer_store_dwordx2 v[44:45], v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+48], s[sgprBeta], v166, v[vgprValuC+48] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+49], s[sgprBeta], v166, v[vgprValuC+49] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+50], s[sgprBeta], v167, v[vgprValuC+50] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+51], s[sgprBeta], v167, v[vgprValuC+51] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+48], v[vgprValuC+48] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+49], v[vgprValuC+49] // convert C to fp16 +v_pack_b32_f16 v48, v[vgprValuC+48], v[vgprValuC+49] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+50], v[vgprValuC+50] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+51], v[vgprValuC+51] // convert C to fp16 +v_pack_b32_f16 v49, v[vgprValuC+50], v[vgprValuC+51] // Pack with neighbor +buffer_store_dwordx2 v[48:49], v165, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+52], s[sgprBeta], v168, v[vgprValuC+52] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+53], s[sgprBeta], v168, v[vgprValuC+53] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+54], s[sgprBeta], v169, v[vgprValuC+54] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+55], s[sgprBeta], v169, v[vgprValuC+55] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+52], v[vgprValuC+52] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+53], v[vgprValuC+53] // convert C to fp16 +v_pack_b32_f16 v52, v[vgprValuC+52], v[vgprValuC+53] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+54], v[vgprValuC+54] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+55], v[vgprValuC+55] // convert C to fp16 +v_pack_b32_f16 v53, v[vgprValuC+54], v[vgprValuC+55] // Pack with neighbor +buffer_store_dwordx2 v[52:53], v170, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+56], s[sgprBeta], v172, v[vgprValuC+56] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+57], s[sgprBeta], v172, v[vgprValuC+57] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+58], s[sgprBeta], v173, v[vgprValuC+58] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+59], s[sgprBeta], v173, v[vgprValuC+59] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+56], v[vgprValuC+56] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+57], v[vgprValuC+57] // convert C to fp16 +v_pack_b32_f16 v56, v[vgprValuC+56], v[vgprValuC+57] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+58], v[vgprValuC+58] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+59], v[vgprValuC+59] // convert C to fp16 +v_pack_b32_f16 v57, v[vgprValuC+58], v[vgprValuC+59] // Pack with neighbor +buffer_store_dwordx2 v[56:57], v171, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+60], s[sgprBeta], v174, v[vgprValuC+60] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+61], s[sgprBeta], v174, v[vgprValuC+61] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+62], s[sgprBeta], v175, v[vgprValuC+62] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+63], s[sgprBeta], v175, v[vgprValuC+63] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+60], v[vgprValuC+60] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+61], v[vgprValuC+61] // convert C to fp16 +v_pack_b32_f16 v60, v[vgprValuC+60], v[vgprValuC+61] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+62], v[vgprValuC+62] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+63], v[vgprValuC+63] // convert C to fp16 +v_pack_b32_f16 v61, v[vgprValuC+62], v[vgprValuC+63] // Pack with neighbor +buffer_store_dwordx2 v[60:61], v176, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+64], s[sgprBeta], v178, v[vgprValuC+64] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+65], s[sgprBeta], v178, v[vgprValuC+65] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+66], s[sgprBeta], v179, v[vgprValuC+66] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+67], s[sgprBeta], v179, v[vgprValuC+67] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+64], v[vgprValuC+64] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+65], v[vgprValuC+65] // convert C to fp16 +v_pack_b32_f16 v64, v[vgprValuC+64], v[vgprValuC+65] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+66], v[vgprValuC+66] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+67], v[vgprValuC+67] // convert C to fp16 +v_pack_b32_f16 v65, v[vgprValuC+66], v[vgprValuC+67] // Pack with neighbor +buffer_store_dwordx2 v[64:65], v177, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+68], s[sgprBeta], v180, v[vgprValuC+68] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+69], s[sgprBeta], v180, v[vgprValuC+69] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+70], s[sgprBeta], v181, v[vgprValuC+70] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+71], s[sgprBeta], v181, v[vgprValuC+71] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+68], v[vgprValuC+68] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+69], v[vgprValuC+69] // convert C to fp16 +v_pack_b32_f16 v68, v[vgprValuC+68], v[vgprValuC+69] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+70], v[vgprValuC+70] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+71], v[vgprValuC+71] // convert C to fp16 +v_pack_b32_f16 v69, v[vgprValuC+70], v[vgprValuC+71] // Pack with neighbor +buffer_store_dwordx2 v[68:69], v182, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+72], s[sgprBeta], v186, v[vgprValuC+72] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+73], s[sgprBeta], v186, v[vgprValuC+73] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+74], s[sgprBeta], v187, v[vgprValuC+74] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+75], s[sgprBeta], v187, v[vgprValuC+75] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+72], v[vgprValuC+72] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+73], v[vgprValuC+73] // convert C to fp16 +v_pack_b32_f16 v72, v[vgprValuC+72], v[vgprValuC+73] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+74], v[vgprValuC+74] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+75], v[vgprValuC+75] // convert C to fp16 +v_pack_b32_f16 v73, v[vgprValuC+74], v[vgprValuC+75] // Pack with neighbor +buffer_store_dwordx2 v[72:73], v183, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+76], s[sgprBeta], v188, v[vgprValuC+76] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+77], s[sgprBeta], v188, v[vgprValuC+77] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+78], s[sgprBeta], v189, v[vgprValuC+78] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+79], s[sgprBeta], v189, v[vgprValuC+79] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+76], v[vgprValuC+76] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+77], v[vgprValuC+77] // convert C to fp16 +v_pack_b32_f16 v76, v[vgprValuC+76], v[vgprValuC+77] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+78], v[vgprValuC+78] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+79], v[vgprValuC+79] // convert C to fp16 +v_pack_b32_f16 v77, v[vgprValuC+78], v[vgprValuC+79] // Pack with neighbor +buffer_store_dwordx2 v[76:77], v185, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+80], s[sgprBeta], v190, v[vgprValuC+80] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+81], s[sgprBeta], v190, v[vgprValuC+81] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+82], s[sgprBeta], v191, v[vgprValuC+82] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+83], s[sgprBeta], v191, v[vgprValuC+83] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+80], v[vgprValuC+80] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+81], v[vgprValuC+81] // convert C to fp16 +v_pack_b32_f16 v80, v[vgprValuC+80], v[vgprValuC+81] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+82], v[vgprValuC+82] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+83], v[vgprValuC+83] // convert C to fp16 +v_pack_b32_f16 v81, v[vgprValuC+82], v[vgprValuC+83] // Pack with neighbor +buffer_store_dwordx2 v[80:81], v192, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+84], s[sgprBeta], v194, v[vgprValuC+84] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+85], s[sgprBeta], v194, v[vgprValuC+85] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+86], s[sgprBeta], v195, v[vgprValuC+86] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+87], s[sgprBeta], v195, v[vgprValuC+87] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+84], v[vgprValuC+84] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+85], v[vgprValuC+85] // convert C to fp16 +v_pack_b32_f16 v84, v[vgprValuC+84], v[vgprValuC+85] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+86], v[vgprValuC+86] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+87], v[vgprValuC+87] // convert C to fp16 +v_pack_b32_f16 v85, v[vgprValuC+86], v[vgprValuC+87] // Pack with neighbor +buffer_store_dwordx2 v[84:85], v193, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+88], s[sgprBeta], v196, v[vgprValuC+88] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+89], s[sgprBeta], v196, v[vgprValuC+89] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+90], s[sgprBeta], v197, v[vgprValuC+90] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+91], s[sgprBeta], v197, v[vgprValuC+91] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+88], v[vgprValuC+88] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+89], v[vgprValuC+89] // convert C to fp16 +v_pack_b32_f16 v88, v[vgprValuC+88], v[vgprValuC+89] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+90], v[vgprValuC+90] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+91], v[vgprValuC+91] // convert C to fp16 +v_pack_b32_f16 v89, v[vgprValuC+90], v[vgprValuC+91] // Pack with neighbor +buffer_store_dwordx2 v[88:89], v198, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+92], s[sgprBeta], v200, v[vgprValuC+92] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+93], s[sgprBeta], v200, v[vgprValuC+93] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+94], s[sgprBeta], v201, v[vgprValuC+94] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+95], s[sgprBeta], v201, v[vgprValuC+95] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+92], v[vgprValuC+92] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+93], v[vgprValuC+93] // convert C to fp16 +v_pack_b32_f16 v92, v[vgprValuC+92], v[vgprValuC+93] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+94], v[vgprValuC+94] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+95], v[vgprValuC+95] // convert C to fp16 +v_pack_b32_f16 v93, v[vgprValuC+94], v[vgprValuC+95] // Pack with neighbor +buffer_store_dwordx2 v[92:93], v199, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+96], s[sgprBeta], v202, v[vgprValuC+96] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+97], s[sgprBeta], v202, v[vgprValuC+97] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+98], s[sgprBeta], v203, v[vgprValuC+98] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+99], s[sgprBeta], v203, v[vgprValuC+99] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+96], v[vgprValuC+96] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+97], v[vgprValuC+97] // convert C to fp16 +v_pack_b32_f16 v96, v[vgprValuC+96], v[vgprValuC+97] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+98], v[vgprValuC+98] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+99], v[vgprValuC+99] // convert C to fp16 +v_pack_b32_f16 v97, v[vgprValuC+98], v[vgprValuC+99] // Pack with neighbor +buffer_store_dwordx2 v[96:97], v204, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+100], s[sgprBeta], v206, v[vgprValuC+100] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+101], s[sgprBeta], v206, v[vgprValuC+101] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+102], s[sgprBeta], v207, v[vgprValuC+102] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+103], s[sgprBeta], v207, v[vgprValuC+103] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+100], v[vgprValuC+100] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+101], v[vgprValuC+101] // convert C to fp16 +v_pack_b32_f16 v100, v[vgprValuC+100], v[vgprValuC+101] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+102], v[vgprValuC+102] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+103], v[vgprValuC+103] // convert C to fp16 +v_pack_b32_f16 v101, v[vgprValuC+102], v[vgprValuC+103] // Pack with neighbor +buffer_store_dwordx2 v[100:101], v205, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+104], s[sgprBeta], v208, v[vgprValuC+104] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+105], s[sgprBeta], v208, v[vgprValuC+105] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+106], s[sgprBeta], v209, v[vgprValuC+106] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+107], s[sgprBeta], v209, v[vgprValuC+107] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+104], v[vgprValuC+104] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+105], v[vgprValuC+105] // convert C to fp16 +v_pack_b32_f16 v104, v[vgprValuC+104], v[vgprValuC+105] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+106], v[vgprValuC+106] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+107], v[vgprValuC+107] // convert C to fp16 +v_pack_b32_f16 v105, v[vgprValuC+106], v[vgprValuC+107] // Pack with neighbor +buffer_store_dwordx2 v[104:105], v210, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+108], s[sgprBeta], v212, v[vgprValuC+108] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+109], s[sgprBeta], v212, v[vgprValuC+109] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+110], s[sgprBeta], v213, v[vgprValuC+110] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+111], s[sgprBeta], v213, v[vgprValuC+111] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+108], v[vgprValuC+108] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+109], v[vgprValuC+109] // convert C to fp16 +v_pack_b32_f16 v108, v[vgprValuC+108], v[vgprValuC+109] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+110], v[vgprValuC+110] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+111], v[vgprValuC+111] // convert C to fp16 +v_pack_b32_f16 v109, v[vgprValuC+110], v[vgprValuC+111] // Pack with neighbor +buffer_store_dwordx2 v[108:109], v211, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+112], s[sgprBeta], v214, v[vgprValuC+112] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+113], s[sgprBeta], v214, v[vgprValuC+113] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+114], s[sgprBeta], v215, v[vgprValuC+114] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+115], s[sgprBeta], v215, v[vgprValuC+115] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+112], v[vgprValuC+112] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+113], v[vgprValuC+113] // convert C to fp16 +v_pack_b32_f16 v112, v[vgprValuC+112], v[vgprValuC+113] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+114], v[vgprValuC+114] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+115], v[vgprValuC+115] // convert C to fp16 +v_pack_b32_f16 v113, v[vgprValuC+114], v[vgprValuC+115] // Pack with neighbor +buffer_store_dwordx2 v[112:113], v216, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+116], s[sgprBeta], v218, v[vgprValuC+116] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+117], s[sgprBeta], v218, v[vgprValuC+117] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+118], s[sgprBeta], v219, v[vgprValuC+118] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+119], s[sgprBeta], v219, v[vgprValuC+119] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+116], v[vgprValuC+116] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+117], v[vgprValuC+117] // convert C to fp16 +v_pack_b32_f16 v116, v[vgprValuC+116], v[vgprValuC+117] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+118], v[vgprValuC+118] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+119], v[vgprValuC+119] // convert C to fp16 +v_pack_b32_f16 v117, v[vgprValuC+118], v[vgprValuC+119] // Pack with neighbor +buffer_store_dwordx2 v[116:117], v217, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+120], s[sgprBeta], v220, v[vgprValuC+120] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+121], s[sgprBeta], v220, v[vgprValuC+121] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+122], s[sgprBeta], v221, v[vgprValuC+122] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+123], s[sgprBeta], v221, v[vgprValuC+123] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+120], v[vgprValuC+120] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+121], v[vgprValuC+121] // convert C to fp16 +v_pack_b32_f16 v120, v[vgprValuC+120], v[vgprValuC+121] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+122], v[vgprValuC+122] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+123], v[vgprValuC+123] // convert C to fp16 +v_pack_b32_f16 v121, v[vgprValuC+122], v[vgprValuC+123] // Pack with neighbor +buffer_store_dwordx2 v[120:121], v222, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+124], s[sgprBeta], v224, v[vgprValuC+124] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+125], s[sgprBeta], v224, v[vgprValuC+125] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+126], s[sgprBeta], v225, v[vgprValuC+126] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+127], s[sgprBeta], v225, v[vgprValuC+127] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+124], v[vgprValuC+124] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+125], v[vgprValuC+125] // convert C to fp16 +v_pack_b32_f16 v124, v[vgprValuC+124], v[vgprValuC+125] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+126], v[vgprValuC+126] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+127], v[vgprValuC+127] // convert C to fp16 +v_pack_b32_f16 v125, v[vgprValuC+126], v[vgprValuC+127] // Pack with neighbor +buffer_store_dwordx2 v[124:125], v223, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+128], s[sgprBeta], v226, v[vgprValuC+128] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+129], s[sgprBeta], v226, v[vgprValuC+129] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+130], s[sgprBeta], v227, v[vgprValuC+130] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+131], s[sgprBeta], v227, v[vgprValuC+131] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+128], v[vgprValuC+128] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+129], v[vgprValuC+129] // convert C to fp16 +v_pack_b32_f16 v128, v[vgprValuC+128], v[vgprValuC+129] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+130], v[vgprValuC+130] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+131], v[vgprValuC+131] // convert C to fp16 +v_pack_b32_f16 v129, v[vgprValuC+130], v[vgprValuC+131] // Pack with neighbor +buffer_store_dwordx2 v[128:129], v228, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+132], s[sgprBeta], v230, v[vgprValuC+132] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+133], s[sgprBeta], v230, v[vgprValuC+133] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+134], s[sgprBeta], v231, v[vgprValuC+134] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_fma_mix_f32 v[vgprValuC+135], s[sgprBeta], v231, v[vgprValuC+135] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v[vgprValuC+132], v[vgprValuC+132] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+133], v[vgprValuC+133] // convert C to fp16 +v_pack_b32_f16 v132, v[vgprValuC+132], v[vgprValuC+133] // Pack with neighbor +v_cvt_f16_f32 v[vgprValuC+134], v[vgprValuC+134] // convert C to fp16 +v_cvt_f16_f32 v[vgprValuC+135], v[vgprValuC+135] // convert C to fp16 +v_pack_b32_f16 v133, v[vgprValuC+134], v[vgprValuC+135] // Pack with neighbor +buffer_store_dwordx2 v[132:133], v229, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_GW_B1_FD0_VW4_Else: +label_GW_B1_FD0_VW1_Else: +label_GW_B1_FD0_VW1_Then: + +/* edge=1, allocate 6 sgpr. perBatchTmpS=4 perBatchMaskS=2 perElementMaskS=0 elementsPerBatch=82 */ +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Beta Edge Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw1); (0,0,0,1:vw1); (0,0,0,2:vw1); (0,0,0,3:vw1); (0,0,1,0:vw1); (0,0,1,1:vw1); (0,0,1,2:vw1); (0,0,1,3:vw1); (0,0,2,0:vw1); (0,0,2,1:vw1); (0,0,2,2:vw1); (0,0,2,3:vw1); (0,0,3,0:vw1); (0,0,3,1:vw1); (0,0,3,2:vw1); (0,0,3,3:vw1); (0,0,4,0:vw1); (0,0,4,1:vw1); (0,0,4,2:vw1); (0,0,4,3:vw1); (0,0,5,0:vw1); (0,0,5,1:vw1); (0,0,5,2:vw1); (0,0,5,3:vw1); (0,0,6,0:vw1); (0,0,6,1:vw1); (0,0,6,2:vw1); (0,0,6,3:vw1); (0,0,7,0:vw1); (0,0,7,1:vw1); (0,0,7,2:vw1); (0,0,7,3:vw1); (0,0,8,0:vw1); (0,0,8,1:vw1); (0,0,8,2:vw1); (0,0,8,3:vw1); (0,0,9,0:vw1); (0,0,9,1:vw1); (0,0,9,2:vw1); (0,0,9,3:vw1); (0,0,10,0:vw1); (0,0,10,1:vw1); (0,0,10,2:vw1); (0,0,10,3:vw1); (0,0,11,0:vw1); (0,0,11,1:vw1); (0,0,11,2:vw1); (0,0,11,3:vw1); (0,0,12,0:vw1); (0,0,12,1:vw1); (0,0,12,2:vw1); (0,0,12,3:vw1); (0,0,13,0:vw1); (0,0,13,1:vw1); (0,0,13,2:vw1); (0,0,13,3:vw1); (0,0,14,0:vw1); (0,0,14,1:vw1); (0,0,14,2:vw1); (0,0,14,3:vw1); (0,0,15,0:vw1); (0,0,15,1:vw1); (0,0,15,2:vw1); (0,0,15,3:vw1); (0,0,16,0:vw1); (0,0,16,1:vw1); (0,0,16,2:vw1); (0,0,16,3:vw1); (0,0,17,0:vw1); (0,0,17,1:vw1); (0,0,17,2:vw1); (0,0,17,3:vw1); (0,0,18,0:vw1); (0,0,18,1:vw1); (0,0,18,2:vw1); (0,0,18,3:vw1); (0,0,19,0:vw1); (0,0,19,1:vw1); (0,0,19,2:vw1); (0,0,19,3:vw1); (0,0,20,0:vw1); (0,0,20,1:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,0,0,0) */ +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v90, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v90, v6, v90, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v89, v90, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v90, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v90, v6, v90, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v92, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v92, v6, v92, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v91, v92, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v92, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v92, v6, v92, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v94, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v94, v6, v94, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v93, v94, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v94, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v94, v6, v94, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,0,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v96, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v96, v6, v96, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v95, v96, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v96, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v96, v6, v96, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v98, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v98, v6, v98, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v97, v98, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v98, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v98, v6, v98, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v100, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v100, v6, v100, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v99, v100, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v100, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v100, v6, v100, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v102, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v102, v6, v102, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v101, v102, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v102, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v102, v6, v102, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,1,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v104, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v104, v6, v104, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v103, v104, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v104, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v104, v6, v104, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v106, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v106, v6, v106, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v105, v106, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v106, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v106, v6, v106, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v108, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v108, v6, v108, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v107, v108, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v108, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v108, v6, v108, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v110, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v110, v6, v110, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v109, v110, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v110, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v110, v6, v110, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,2,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v112, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v112, v6, v112, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v111, v112, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v112, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v112, v6, v112, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v114, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v114, v6, v114, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v113, v114, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v114, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v114, v6, v114, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v116, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v116, v6, v116, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v115, v116, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v116, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v116, v6, v116, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v118, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v118, v6, v118, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v117, v118, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v118, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v118, v6, v118, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,3,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v120, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v120, v6, v120, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v119, v120, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v120, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v120, v6, v120, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v122, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v122, v6, v122, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v121, v122, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v122, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v122, v6, v122, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v124, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v124, v6, v124, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v123, v124, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v124, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v124, v6, v124, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v126, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v126, v6, v126, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v125, v126, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v126, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v126, v6, v126, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,4,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v128, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v128, v6, v128, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v127, v128, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v128, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v128, v6, v128, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v130, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v129, v130, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v130, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v132, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v131, v132, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v132, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v134, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v133, v134, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v134, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,5,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v135, v136, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v136, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v137, v138, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v138, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v139, v140, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v140, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v141, v142, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v142, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,6,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v143, v144, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v144, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v146, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v145, v146, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v146, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v146, v6, v146, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v148, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v147, v148, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v148, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v148, v6, v148, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v150, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v149, v150, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v150, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v150, v6, v150, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,7,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v152, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v151, v152, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v152, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v152, v6, v152, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v154, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v153, v154, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v154, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v154, v6, v154, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v156, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v155, v156, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v156, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v156, v6, v156, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v158, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v157, v158, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v158, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v158, v6, v158, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,8,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v160, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v159, v160, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v160, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v160, v6, v160, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v162, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v161, v162, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v162, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v162, v6, v162, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v164, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v163, v164, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v164, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v164, v6, v164, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v166, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v165, v166, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v166, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v166, v6, v166, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,9,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v168, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v168, v6, v168, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v167, v168, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v168, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v168, v6, v168, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v170, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v169, v170, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v170, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v170, v6, v170, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v172, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v172, v6, v172, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v171, v172, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v172, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v172, v6, v172, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v174, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v174, v6, v174, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v173, v174, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v174, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v174, v6, v174, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,10,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v176, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v175, v176, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v176, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v176, v6, v176, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v178, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v178, v6, v178, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v177, v178, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v178, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v178, v6, v178, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v180, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v180, v6, v180, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v179, v180, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v180, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v180, v6, v180, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v182, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v181, v182, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v182, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v182, v6, v182, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,11,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v185, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v183, v185, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v185, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v185, v6, v185, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v187, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v187, v6, v187, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v186, v187, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v187, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v187, v6, v187, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v189, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v189, v6, v189, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v188, v189, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v189, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v189, v6, v189, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v191, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v191, v6, v191, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v190, v191, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v191, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v191, v6, v191, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,12,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v193, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v192, v193, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v193, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v193, v6, v193, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v195, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v195, v6, v195, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v194, v195, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v195, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v195, v6, v195, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v197, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v197, v6, v197, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v196, v197, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v197, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v197, v6, v197, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v199, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v198, v199, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v199, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v199, v6, v199, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,13,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v201, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v201, v6, v201, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v200, v201, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v201, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v201, v6, v201, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v203, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v203, v6, v203, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v202, v203, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v203, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v203, v6, v203, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v205, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v204, v205, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v205, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v205, v6, v205, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v207, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v207, v6, v207, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v206, v207, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v207, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v207, v6, v207, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,14,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v209, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v209, v6, v209, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v208, v209, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v209, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v209, v6, v209, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v211, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v210, v211, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v211, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v211, v6, v211, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v213, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v213, v6, v213, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v212, v213, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v213, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v213, v6, v213, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v215, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v215, v6, v215, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v214, v215, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v215, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v215, v6, v215, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,15,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v217, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v216, v217, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v217, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v217, v6, v217, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v219, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v219, v6, v219, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v218, v219, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v219, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v219, v6, v219, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v221, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v221, v6, v221, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v220, v221, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v221, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v221, v6, v221, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v223, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v222, v223, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v223, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v223, v6, v223, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,16,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v225, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v225, v6, v225, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v224, v225, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v225, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v225, v6, v225, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v227, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v227, v6, v227, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v226, v227, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v227, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v227, v6, v227, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v229, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v228, v229, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v229, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v229, v6, v229, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v231, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v231, v6, v231, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v230, v231, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v231, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v231, v6, v231, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,17,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v233, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v233, v6, v233, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v232, v233, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v233, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v233, v6, v233, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v235, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v235, v6, v235, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v234, v235, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v235, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v235, v6, v235, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v237, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v237, v6, v237, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v236, v237, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v237, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v237, v6, v237, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v239, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v239, v6, v239, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v238, v239, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v239, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v239, v6, v239, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,18,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v241, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v241, v6, v241, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v240, v241, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v241, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v241, v6, v241, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v243, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v243, v6, v243, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v242, v243, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v243, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v243, v6, v243, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v245, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v245, v6, v245, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v244, v245, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v245, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v245, v6, v245, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v247, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v247, v6, v247, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v246, v247, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v247, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v247, v6, v247, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,19,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v249, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v249, v6, v249, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v248, v249, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v249, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v249, v6, v249, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v251, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v251, v6, v251, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v250, v251, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v251, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v251, v6, v251, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v253, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v253, v6, v253, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v252, v253, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v253, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v253, v6, v253, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+8], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+9], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+10], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+11], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+12], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+13], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+14], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+15], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+16], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+17], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+18], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+19], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+20], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+21], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+22], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+23], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+24], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+25], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+26], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+27], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+28], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+29], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+30], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+31], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+32], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+33], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+34], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+35], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+36], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+37], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+38], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+39], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+40], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+41], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+42], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+43], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+44], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+45], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+46], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+47], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+48], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+49], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+50], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+51], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+52], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+53], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+54], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+55], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+56], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+57], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+58], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+59], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+60], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+61], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+62], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+63], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+64], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+65], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+66], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+67], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+68], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+69], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+70], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+71], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+72], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+73], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+74], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+75], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+76], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+77], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+78], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+79], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+80], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+81], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+82], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+83], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+84], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+85], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+86], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+87], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+88], acc70 // copy acc to vreg[81] + +/* rC *= alpha batchElements=[(0, 0, 0, 0), (0, 0, 0, 1), (0, 0, 0, 2), (0, 0, 0, 3), (0, 0, 1, 0), (0, 0, 1, 1), (0, 0, 1, 2), (0, 0, 1, 3), (0, 0, 2, 0), (0, 0, 2, 1), (0, 0, 2, 2), (0, 0, 2, 3), (0, 0, 3, 0), (0, 0, 3, 1), (0, 0, 3, 2), (0, 0, 3, 3), (0, 0, 4, 0), (0, 0, 4, 1), (0, 0, 4, 2), (0, 0, 4, 3), (0, 0, 5, 0), (0, 0, 5, 1), (0, 0, 5, 2), (0, 0, 5, 3), (0, 0, 6, 0), (0, 0, 6, 1), (0, 0, 6, 2), (0, 0, 6, 3), (0, 0, 7, 0), (0, 0, 7, 1), (0, 0, 7, 2), (0, 0, 7, 3), (0, 0, 8, 0), (0, 0, 8, 1), (0, 0, 8, 2), (0, 0, 8, 3), (0, 0, 9, 0), (0, 0, 9, 1), (0, 0, 9, 2), (0, 0, 9, 3), (0, 0, 10, 0), (0, 0, 10, 1), (0, 0, 10, 2), (0, 0, 10, 3), (0, 0, 11, 0), (0, 0, 11, 1), (0, 0, 11, 2), (0, 0, 11, 3), (0, 0, 12, 0), (0, 0, 12, 1), (0, 0, 12, 2), (0, 0, 12, 3), (0, 0, 13, 0), (0, 0, 13, 1), (0, 0, 13, 2), (0, 0, 13, 3), (0, 0, 14, 0), (0, 0, 14, 1), (0, 0, 14, 2), (0, 0, 14, 3), (0, 0, 15, 0), (0, 0, 15, 1), (0, 0, 15, 2), (0, 0, 15, 3), (0, 0, 16, 0), (0, 0, 16, 1), (0, 0, 16, 2), (0, 0, 16, 3), (0, 0, 17, 0), (0, 0, 17, 1), (0, 0, 17, 2), (0, 0, 17, 3), (0, 0, 18, 0), (0, 0, 18, 1), (0, 0, 18, 2), (0, 0, 18, 3), (0, 0, 19, 0), (0, 0, 19, 1), (0, 0, 19, 2), (0, 0, 19, 3), (0, 0, 20, 0), (0, 0, 20, 1)] */ +v_mul_f32 v[vgprValuC+7], s[sgprAlpha], v[vgprValuC+7] // *= alpha +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+52:vgprValuC+52+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+52:vgprValuC+52+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+54:vgprValuC+54+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+54:vgprValuC+54+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+56:vgprValuC+56+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+56:vgprValuC+56+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+58:vgprValuC+58+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+58:vgprValuC+58+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+60:vgprValuC+60+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+60:vgprValuC+60+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+62:vgprValuC+62+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+62:vgprValuC+62+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+64:vgprValuC+64+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+64:vgprValuC+64+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+66:vgprValuC+66+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+66:vgprValuC+66+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+68:vgprValuC+68+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+68:vgprValuC+68+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+70:vgprValuC+70+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+70:vgprValuC+70+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+72:vgprValuC+72+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+72:vgprValuC+72+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+74:vgprValuC+74+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+74:vgprValuC+74+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+76:vgprValuC+76+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+76:vgprValuC+76+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+78:vgprValuC+78+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+78:vgprValuC+78+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+80:vgprValuC+80+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+80:vgprValuC+80+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+82:vgprValuC+82+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+82:vgprValuC+82+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+84:vgprValuC+84+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+84:vgprValuC+84+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+86:vgprValuC+86+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+86:vgprValuC+86+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_mul_f32 v[vgprValuC+88], s[sgprAlpha], v[vgprValuC+88] // *= alpha +s_waitcnt vmcnt(0) // wait for Beta + +/* apply mask, calc new C and issue writes */ +v_fma_mix_f32 v[vgprValuC+7], s[sgprBeta], v89, v[vgprValuC+7] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v7, v[vgprValuC+7] // convert C to fp16 +buffer_store_short v7, v90, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+8], s[sgprBeta], v91, v[vgprValuC+8] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v8, v[vgprValuC+8] // convert C to fp16 +buffer_store_short v8, v92, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+9], s[sgprBeta], v93, v[vgprValuC+9] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v9, v[vgprValuC+9] // convert C to fp16 +buffer_store_short v9, v94, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+10], s[sgprBeta], v95, v[vgprValuC+10] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v10, v[vgprValuC+10] // convert C to fp16 +buffer_store_short v10, v96, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+11], s[sgprBeta], v97, v[vgprValuC+11] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v11, v[vgprValuC+11] // convert C to fp16 +buffer_store_short v11, v98, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+12], s[sgprBeta], v99, v[vgprValuC+12] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v12, v[vgprValuC+12] // convert C to fp16 +buffer_store_short v12, v100, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+13], s[sgprBeta], v101, v[vgprValuC+13] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v13, v[vgprValuC+13] // convert C to fp16 +buffer_store_short v13, v102, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+14], s[sgprBeta], v103, v[vgprValuC+14] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v14, v[vgprValuC+14] // convert C to fp16 +buffer_store_short v14, v104, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+15], s[sgprBeta], v105, v[vgprValuC+15] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v15, v[vgprValuC+15] // convert C to fp16 +buffer_store_short v15, v106, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+16], s[sgprBeta], v107, v[vgprValuC+16] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v16, v[vgprValuC+16] // convert C to fp16 +buffer_store_short v16, v108, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+17], s[sgprBeta], v109, v[vgprValuC+17] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v17, v[vgprValuC+17] // convert C to fp16 +buffer_store_short v17, v110, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+18], s[sgprBeta], v111, v[vgprValuC+18] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v18, v[vgprValuC+18] // convert C to fp16 +buffer_store_short v18, v112, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+19], s[sgprBeta], v113, v[vgprValuC+19] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v19, v[vgprValuC+19] // convert C to fp16 +buffer_store_short v19, v114, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+20], s[sgprBeta], v115, v[vgprValuC+20] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v20, v[vgprValuC+20] // convert C to fp16 +buffer_store_short v20, v116, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+21], s[sgprBeta], v117, v[vgprValuC+21] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v21, v[vgprValuC+21] // convert C to fp16 +buffer_store_short v21, v118, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+22], s[sgprBeta], v119, v[vgprValuC+22] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v22, v[vgprValuC+22] // convert C to fp16 +buffer_store_short v22, v120, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+23], s[sgprBeta], v121, v[vgprValuC+23] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v23, v[vgprValuC+23] // convert C to fp16 +buffer_store_short v23, v122, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+24], s[sgprBeta], v123, v[vgprValuC+24] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v24, v[vgprValuC+24] // convert C to fp16 +buffer_store_short v24, v124, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+25], s[sgprBeta], v125, v[vgprValuC+25] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v25, v[vgprValuC+25] // convert C to fp16 +buffer_store_short v25, v126, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+26], s[sgprBeta], v127, v[vgprValuC+26] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v26, v[vgprValuC+26] // convert C to fp16 +buffer_store_short v26, v128, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+27], s[sgprBeta], v129, v[vgprValuC+27] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v27, v[vgprValuC+27] // convert C to fp16 +buffer_store_short v27, v130, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+28], s[sgprBeta], v131, v[vgprValuC+28] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v28, v[vgprValuC+28] // convert C to fp16 +buffer_store_short v28, v132, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+29], s[sgprBeta], v133, v[vgprValuC+29] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v29, v[vgprValuC+29] // convert C to fp16 +buffer_store_short v29, v134, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+30], s[sgprBeta], v135, v[vgprValuC+30] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v30, v[vgprValuC+30] // convert C to fp16 +buffer_store_short v30, v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+31], s[sgprBeta], v137, v[vgprValuC+31] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v31, v[vgprValuC+31] // convert C to fp16 +buffer_store_short v31, v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+32], s[sgprBeta], v139, v[vgprValuC+32] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v32, v[vgprValuC+32] // convert C to fp16 +buffer_store_short v32, v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+33], s[sgprBeta], v141, v[vgprValuC+33] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v33, v[vgprValuC+33] // convert C to fp16 +buffer_store_short v33, v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+34], s[sgprBeta], v143, v[vgprValuC+34] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v34, v[vgprValuC+34] // convert C to fp16 +buffer_store_short v34, v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+35], s[sgprBeta], v145, v[vgprValuC+35] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v35, v[vgprValuC+35] // convert C to fp16 +buffer_store_short v35, v146, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+36], s[sgprBeta], v147, v[vgprValuC+36] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v36, v[vgprValuC+36] // convert C to fp16 +buffer_store_short v36, v148, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+37], s[sgprBeta], v149, v[vgprValuC+37] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v37, v[vgprValuC+37] // convert C to fp16 +buffer_store_short v37, v150, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+38], s[sgprBeta], v151, v[vgprValuC+38] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v38, v[vgprValuC+38] // convert C to fp16 +buffer_store_short v38, v152, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+39], s[sgprBeta], v153, v[vgprValuC+39] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v39, v[vgprValuC+39] // convert C to fp16 +buffer_store_short v39, v154, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+40], s[sgprBeta], v155, v[vgprValuC+40] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v40, v[vgprValuC+40] // convert C to fp16 +buffer_store_short v40, v156, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+41], s[sgprBeta], v157, v[vgprValuC+41] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v41, v[vgprValuC+41] // convert C to fp16 +buffer_store_short v41, v158, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+42], s[sgprBeta], v159, v[vgprValuC+42] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v42, v[vgprValuC+42] // convert C to fp16 +buffer_store_short v42, v160, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+43], s[sgprBeta], v161, v[vgprValuC+43] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v43, v[vgprValuC+43] // convert C to fp16 +buffer_store_short v43, v162, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+44], s[sgprBeta], v163, v[vgprValuC+44] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v44, v[vgprValuC+44] // convert C to fp16 +buffer_store_short v44, v164, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+45], s[sgprBeta], v165, v[vgprValuC+45] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v45, v[vgprValuC+45] // convert C to fp16 +buffer_store_short v45, v166, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+46], s[sgprBeta], v167, v[vgprValuC+46] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v46, v[vgprValuC+46] // convert C to fp16 +buffer_store_short v46, v168, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+47], s[sgprBeta], v169, v[vgprValuC+47] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v47, v[vgprValuC+47] // convert C to fp16 +buffer_store_short v47, v170, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+48], s[sgprBeta], v171, v[vgprValuC+48] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v48, v[vgprValuC+48] // convert C to fp16 +buffer_store_short v48, v172, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+49], s[sgprBeta], v173, v[vgprValuC+49] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v49, v[vgprValuC+49] // convert C to fp16 +buffer_store_short v49, v174, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+50], s[sgprBeta], v175, v[vgprValuC+50] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v50, v[vgprValuC+50] // convert C to fp16 +buffer_store_short v50, v176, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+51], s[sgprBeta], v177, v[vgprValuC+51] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v51, v[vgprValuC+51] // convert C to fp16 +buffer_store_short v51, v178, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+52], s[sgprBeta], v179, v[vgprValuC+52] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v52, v[vgprValuC+52] // convert C to fp16 +buffer_store_short v52, v180, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+53], s[sgprBeta], v181, v[vgprValuC+53] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v53, v[vgprValuC+53] // convert C to fp16 +buffer_store_short v53, v182, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+54], s[sgprBeta], v183, v[vgprValuC+54] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v54, v[vgprValuC+54] // convert C to fp16 +buffer_store_short v54, v185, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+55], s[sgprBeta], v186, v[vgprValuC+55] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v55, v[vgprValuC+55] // convert C to fp16 +buffer_store_short v55, v187, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+56], s[sgprBeta], v188, v[vgprValuC+56] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v56, v[vgprValuC+56] // convert C to fp16 +buffer_store_short v56, v189, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+57], s[sgprBeta], v190, v[vgprValuC+57] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v57, v[vgprValuC+57] // convert C to fp16 +buffer_store_short v57, v191, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+58], s[sgprBeta], v192, v[vgprValuC+58] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v58, v[vgprValuC+58] // convert C to fp16 +buffer_store_short v58, v193, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+59], s[sgprBeta], v194, v[vgprValuC+59] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v59, v[vgprValuC+59] // convert C to fp16 +buffer_store_short v59, v195, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+60], s[sgprBeta], v196, v[vgprValuC+60] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v60, v[vgprValuC+60] // convert C to fp16 +buffer_store_short v60, v197, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+61], s[sgprBeta], v198, v[vgprValuC+61] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v61, v[vgprValuC+61] // convert C to fp16 +buffer_store_short v61, v199, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+62], s[sgprBeta], v200, v[vgprValuC+62] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v62, v[vgprValuC+62] // convert C to fp16 +buffer_store_short v62, v201, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+63], s[sgprBeta], v202, v[vgprValuC+63] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v63, v[vgprValuC+63] // convert C to fp16 +buffer_store_short v63, v203, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+64], s[sgprBeta], v204, v[vgprValuC+64] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v64, v[vgprValuC+64] // convert C to fp16 +buffer_store_short v64, v205, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+65], s[sgprBeta], v206, v[vgprValuC+65] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v65, v[vgprValuC+65] // convert C to fp16 +buffer_store_short v65, v207, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+66], s[sgprBeta], v208, v[vgprValuC+66] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v66, v[vgprValuC+66] // convert C to fp16 +buffer_store_short v66, v209, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+67], s[sgprBeta], v210, v[vgprValuC+67] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v67, v[vgprValuC+67] // convert C to fp16 +buffer_store_short v67, v211, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+68], s[sgprBeta], v212, v[vgprValuC+68] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v68, v[vgprValuC+68] // convert C to fp16 +buffer_store_short v68, v213, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+69], s[sgprBeta], v214, v[vgprValuC+69] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v69, v[vgprValuC+69] // convert C to fp16 +buffer_store_short v69, v215, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+70], s[sgprBeta], v216, v[vgprValuC+70] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v70, v[vgprValuC+70] // convert C to fp16 +buffer_store_short v70, v217, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+71], s[sgprBeta], v218, v[vgprValuC+71] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v71, v[vgprValuC+71] // convert C to fp16 +buffer_store_short v71, v219, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+72], s[sgprBeta], v220, v[vgprValuC+72] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v72, v[vgprValuC+72] // convert C to fp16 +buffer_store_short v72, v221, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+73], s[sgprBeta], v222, v[vgprValuC+73] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v73, v[vgprValuC+73] // convert C to fp16 +buffer_store_short v73, v223, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+74], s[sgprBeta], v224, v[vgprValuC+74] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v74, v[vgprValuC+74] // convert C to fp16 +buffer_store_short v74, v225, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+75], s[sgprBeta], v226, v[vgprValuC+75] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v75, v[vgprValuC+75] // convert C to fp16 +buffer_store_short v75, v227, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+76], s[sgprBeta], v228, v[vgprValuC+76] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v76, v[vgprValuC+76] // convert C to fp16 +buffer_store_short v76, v229, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+77], s[sgprBeta], v230, v[vgprValuC+77] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v77, v[vgprValuC+77] // convert C to fp16 +buffer_store_short v77, v231, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+78], s[sgprBeta], v232, v[vgprValuC+78] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v78, v[vgprValuC+78] // convert C to fp16 +buffer_store_short v78, v233, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+79], s[sgprBeta], v234, v[vgprValuC+79] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v79, v[vgprValuC+79] // convert C to fp16 +buffer_store_short v79, v235, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+80], s[sgprBeta], v236, v[vgprValuC+80] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v80, v[vgprValuC+80] // convert C to fp16 +buffer_store_short v80, v237, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+81], s[sgprBeta], v238, v[vgprValuC+81] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v81, v[vgprValuC+81] // convert C to fp16 +buffer_store_short v81, v239, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+82], s[sgprBeta], v240, v[vgprValuC+82] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v82, v[vgprValuC+82] // convert C to fp16 +buffer_store_short v82, v241, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+83], s[sgprBeta], v242, v[vgprValuC+83] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v83, v[vgprValuC+83] // convert C to fp16 +buffer_store_short v83, v243, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+84], s[sgprBeta], v244, v[vgprValuC+84] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v84, v[vgprValuC+84] // convert C to fp16 +buffer_store_short v84, v245, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+85], s[sgprBeta], v246, v[vgprValuC+85] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v85, v[vgprValuC+85] // convert C to fp16 +buffer_store_short v85, v247, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+86], s[sgprBeta], v248, v[vgprValuC+86] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v86, v[vgprValuC+86] // convert C to fp16 +buffer_store_short v86, v249, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+87], s[sgprBeta], v250, v[vgprValuC+87] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v87, v[vgprValuC+87] // convert C to fp16 +buffer_store_short v87, v251, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+88], s[sgprBeta], v252, v[vgprValuC+88] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v88, v[vgprValuC+88] // convert C to fp16 +buffer_store_short v88, v253, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +/* optSingleColVgpr=0 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Edge_Mask optSrdIncForRow=0 factorDim=0 */ + +/******************************************/ +/* Global Write Beta Edge Batch #1 (d1,d0,vc1,vc0) = */ +/* (0,0,20,2:vw1); (0,0,20,3:vw1); (0,0,21,0:vw1); (0,0,21,1:vw1); (0,0,21,2:vw1); (0,0,21,3:vw1); (0,0,22,0:vw1); (0,0,22,1:vw1); (0,0,22,2:vw1); (0,0,22,3:vw1); (0,0,23,0:vw1); (0,0,23,1:vw1); (0,0,23,2:vw1); (0,0,23,3:vw1); (0,0,24,0:vw1); (0,0,24,1:vw1); (0,0,24,2:vw1); (0,0,24,3:vw1); (0,0,25,0:vw1); (0,0,25,1:vw1); (0,0,25,2:vw1); (0,0,25,3:vw1); (0,0,26,0:vw1); (0,0,26,1:vw1); (0,0,26,2:vw1); (0,0,26,3:vw1); (0,0,27,0:vw1); (0,0,27,1:vw1); (0,0,27,2:vw1); (0,0,27,3:vw1); (0,0,28,0:vw1); (0,0,28,1:vw1); (0,0,28,2:vw1); (0,0,28,3:vw1); (0,0,29,0:vw1); (0,0,29,1:vw1); (0,0,29,2:vw1); (0,0,29,3:vw1); (0,0,30,0:vw1); (0,0,30,1:vw1); (0,0,30,2:vw1); (0,0,30,3:vw1); (0,0,31,0:vw1); (0,0,31,1:vw1); (0,0,31,2:vw1); (0,0,31,3:vw1) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_mov_b32 v6, BufferOOB +/* (d1,vc1,d0,vc0)=(0,20,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v54, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v54, v6, v54, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v53, v54, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v54, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v54, v6, v54, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,20,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v56, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v56, v6, v56, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v55, v56, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v56, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v56, v6, v56, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v58, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v58, v6, v58, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v57, v58, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v58, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v58, v6, v58, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v60, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v60, v6, v60, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v59, v60, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v60, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v60, v6, v60, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v62, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v62, v6, v62, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v61, v62, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v62, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v62, v6, v62, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,21,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v64, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v64, v6, v64, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v63, v64, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v64, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v64, v6, v64, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v66, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v66, v6, v66, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v65, v66, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v66, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v66, v6, v66, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v68, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v68, v6, v68, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v67, v68, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v68, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v68, v6, v68, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v70, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v70, v6, v70, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v69, v70, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v70, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v70, v6, v70, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,22,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v72, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v72, v6, v72, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v71, v72, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v72, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v72, v6, v72, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v74, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v74, v6, v74, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v73, v74, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v74, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v74, v6, v74, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v76, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v76, v6, v76, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v75, v76, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v76, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v76, v6, v76, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v78, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v78, v6, v78, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v77, v78, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v78, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v78, v6, v78, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,23,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v80, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v80, v6, v80, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v79, v80, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v80, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v80, v6, v80, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v82, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v82, v6, v82, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v81, v82, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v82, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v82, v6, v82, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v84, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v84, v6, v84, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v83, v84, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v84, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v84, v6, v84, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v86, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v86, v6, v86, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v85, v86, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v86, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v86, v6, v86, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,24,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v88, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v88, v6, v88, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v87, v88, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v88, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v88, v6, v88, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v90, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v90, v6, v90, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v89, v90, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v90, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v90, v6, v90, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v92, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v92, v6, v92, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v91, v92, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v92, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v92, v6, v92, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v94, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v94, v6, v94, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v93, v94, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v94, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v94, v6, v94, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,25,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v96, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v96, v6, v96, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v95, v96, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v96, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v96, v6, v96, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v98, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v98, v6, v98, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v97, v98, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v98, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v98, v6, v98, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v100, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v100, v6, v100, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v99, v100, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v100, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v100, v6, v100, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v102, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v102, v6, v102, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v101, v102, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v102, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v102, v6, v102, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,26,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v104, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v104, v6, v104, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v103, v104, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v104, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v104, v6, v104, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v106, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v106, v6, v106, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v105, v106, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v106, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v106, v6, v106, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v108, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v108, v6, v108, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v107, v108, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v108, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v108, v6, v108, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v110, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v110, v6, v110, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v109, v110, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v110, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v110, v6, v110, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,27,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v112, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v112, v6, v112, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v111, v112, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v112, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v112, v6, v112, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v114, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v114, v6, v114, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v113, v114, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v114, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v114, v6, v114, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v116, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v116, v6, v116, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v115, v116, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v116, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v116, v6, v116, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v118, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v118, v6, v118, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v117, v118, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v118, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v118, v6, v118, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,28,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v120, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v120, v6, v120, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v119, v120, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v120, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v120, v6, v120, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v122, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v122, v6, v122, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v121, v122, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v122, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v122, v6, v122, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v124, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v124, v6, v124, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v123, v124, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v124, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v124, v6, v124, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v126, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v126, v6, v126, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v125, v126, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v126, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v126, v6, v126, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,29,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v128, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v128, v6, v128, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v127, v128, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v128, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v128, v6, v128, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v130, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v129, v130, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v130, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v130, v6, v130, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v132, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v131, v132, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v132, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v132, v6, v132, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v134, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v133, v134, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v134, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v134, v6, v134, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,30,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v136, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v135, v136, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v136, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v136, v6, v136, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,0) */ +v_add_co_u32 v1, vcc, v1, 1 // coord1.1: coord1Vgpr += d1*sg1*VW + vc1 + +/* Fix for UseInitialStridesCD, emitAddressSetupCode */ +v_add_u32 v2, v2, s[sgprStrideC1J] // ROWINC- Move cinRowPtr to next row +v_add_u32 v3, v3, s[sgprStrideD1J] // Move coutRowPtrD to next row +v_cmp_lt_u32 s[64:65], v0, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v138, v2, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v137, v138, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v138, v3, v0, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v138, v6, v138, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,1) */ +v_add_co_u32 v4, vcc, v0, 1 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v140, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v139, v140, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v140, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v140, v6, v140, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,2) */ +v_add_co_u32 v4, vcc, v0, 2 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v142, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16 v141, v142, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v142, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v142, v6, v142, s[68:69] // LDD clip if OOB. offset +/* (d1,vc1,d0,vc0)=(0,31,0,3) */ +v_add_co_u32 v4, vcc, v0, 3 // coord0.1: coord0 += d0*sg0*VW + vc0 +v_cmp_lt_u32 s[64:65], v4, s[sgprSizeI] // coord0 < size0 +v_cmp_lt_u32 s[68:69], v1, s[sgprSizeJ] // coord1 < size1 +s_and_b64 s[68:69], s[64:65], s[68:69] // in0 && in1 +v_add_lshl_u32 v144, v2, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDC clip if OOB. offset +buffer_load_short_d16_hi v143, v144, s[sgprSrdC:sgprSrdC+3], 0 offen offset:0 // load C +v_add_lshl_u32 v144, v3, v4, 1 // scaleToBpe: accumulate d0 lower and *= bpe into Cin addr (multiple bpe) +v_cndmask_b32 v144, v6, v144, s[68:69] // LDD clip if OOB. offset +v_accvgpr_read_b32 v[vgprValuC+7], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+8], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+9], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+10], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+11], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+12], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+13], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+14], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+15], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+16], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+17], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+18], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+19], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+20], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+21], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+22], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+23], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+24], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+25], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+26], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+27], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+28], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+29], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+30], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+31], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+32], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+33], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+34], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+35], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+36], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+37], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+38], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+39], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+40], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+41], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+42], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+43], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+44], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+45], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+46], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+47], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+48], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+49], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+50], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+51], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+52], acc127 // copy acc to vreg[127] + +/* rC *= alpha batchElements=[(0, 0, 20, 2), (0, 0, 20, 3), (0, 0, 21, 0), (0, 0, 21, 1), (0, 0, 21, 2), (0, 0, 21, 3), (0, 0, 22, 0), (0, 0, 22, 1), (0, 0, 22, 2), (0, 0, 22, 3), (0, 0, 23, 0), (0, 0, 23, 1), (0, 0, 23, 2), (0, 0, 23, 3), (0, 0, 24, 0), (0, 0, 24, 1), (0, 0, 24, 2), (0, 0, 24, 3), (0, 0, 25, 0), (0, 0, 25, 1), (0, 0, 25, 2), (0, 0, 25, 3), (0, 0, 26, 0), (0, 0, 26, 1), (0, 0, 26, 2), (0, 0, 26, 3), (0, 0, 27, 0), (0, 0, 27, 1), (0, 0, 27, 2), (0, 0, 27, 3), (0, 0, 28, 0), (0, 0, 28, 1), (0, 0, 28, 2), (0, 0, 28, 3), (0, 0, 29, 0), (0, 0, 29, 1), (0, 0, 29, 2), (0, 0, 29, 3), (0, 0, 30, 0), (0, 0, 30, 1), (0, 0, 30, 2), (0, 0, 30, 3), (0, 0, 31, 0), (0, 0, 31, 1), (0, 0, 31, 2), (0, 0, 31, 3)] */ +v_mul_f32 v[vgprValuC+7], s[sgprAlpha], v[vgprValuC+7] // *= alpha +v_pk_mul_f32 v[vgprValuC+8:vgprValuC+8+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+8:vgprValuC+8+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+10:vgprValuC+10+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+10:vgprValuC+10+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+12:vgprValuC+12+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+12:vgprValuC+12+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+14:vgprValuC+14+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+14:vgprValuC+14+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+16:vgprValuC+16+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+16:vgprValuC+16+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+18:vgprValuC+18+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+18:vgprValuC+18+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+20:vgprValuC+20+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+20:vgprValuC+20+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+22:vgprValuC+22+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+22:vgprValuC+22+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+24:vgprValuC+24+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+24:vgprValuC+24+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+26:vgprValuC+26+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+26:vgprValuC+26+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+28:vgprValuC+28+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+28:vgprValuC+28+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+30:vgprValuC+30+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+30:vgprValuC+30+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+32:vgprValuC+32+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+32:vgprValuC+32+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+34:vgprValuC+34+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+34:vgprValuC+34+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+36:vgprValuC+36+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+36:vgprValuC+36+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+38:vgprValuC+38+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+38:vgprValuC+38+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+40:vgprValuC+40+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+40:vgprValuC+40+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+42:vgprValuC+42+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+42:vgprValuC+42+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+44:vgprValuC+44+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+44:vgprValuC+44+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+46:vgprValuC+46+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+46:vgprValuC+46+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+48:vgprValuC+48+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+48:vgprValuC+48+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_pk_mul_f32 v[vgprValuC+50:vgprValuC+50+1], s[sgprAlpha:sgprAlpha+1], v[vgprValuC+50:vgprValuC+50+1] op_sel_hi:[0,1,1] // *= alpha (pk) +v_mul_f32 v[vgprValuC+52], s[sgprAlpha], v[vgprValuC+52] // *= alpha +s_waitcnt vmcnt(0) // wait for Beta + +/* apply mask, calc new C and issue writes */ +v_fma_mix_f32 v[vgprValuC+7], s[sgprBeta], v53, v[vgprValuC+7] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v7, v[vgprValuC+7] // convert C to fp16 +buffer_store_short v7, v54, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+8], s[sgprBeta], v55, v[vgprValuC+8] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v8, v[vgprValuC+8] // convert C to fp16 +buffer_store_short v8, v56, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+9], s[sgprBeta], v57, v[vgprValuC+9] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v9, v[vgprValuC+9] // convert C to fp16 +buffer_store_short v9, v58, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+10], s[sgprBeta], v59, v[vgprValuC+10] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v10, v[vgprValuC+10] // convert C to fp16 +buffer_store_short v10, v60, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+11], s[sgprBeta], v61, v[vgprValuC+11] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v11, v[vgprValuC+11] // convert C to fp16 +buffer_store_short v11, v62, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+12], s[sgprBeta], v63, v[vgprValuC+12] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v12, v[vgprValuC+12] // convert C to fp16 +buffer_store_short v12, v64, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+13], s[sgprBeta], v65, v[vgprValuC+13] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v13, v[vgprValuC+13] // convert C to fp16 +buffer_store_short v13, v66, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+14], s[sgprBeta], v67, v[vgprValuC+14] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v14, v[vgprValuC+14] // convert C to fp16 +buffer_store_short v14, v68, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+15], s[sgprBeta], v69, v[vgprValuC+15] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v15, v[vgprValuC+15] // convert C to fp16 +buffer_store_short v15, v70, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+16], s[sgprBeta], v71, v[vgprValuC+16] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v16, v[vgprValuC+16] // convert C to fp16 +buffer_store_short v16, v72, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+17], s[sgprBeta], v73, v[vgprValuC+17] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v17, v[vgprValuC+17] // convert C to fp16 +buffer_store_short v17, v74, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+18], s[sgprBeta], v75, v[vgprValuC+18] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v18, v[vgprValuC+18] // convert C to fp16 +buffer_store_short v18, v76, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+19], s[sgprBeta], v77, v[vgprValuC+19] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v19, v[vgprValuC+19] // convert C to fp16 +buffer_store_short v19, v78, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+20], s[sgprBeta], v79, v[vgprValuC+20] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v20, v[vgprValuC+20] // convert C to fp16 +buffer_store_short v20, v80, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+21], s[sgprBeta], v81, v[vgprValuC+21] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v21, v[vgprValuC+21] // convert C to fp16 +buffer_store_short v21, v82, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+22], s[sgprBeta], v83, v[vgprValuC+22] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v22, v[vgprValuC+22] // convert C to fp16 +buffer_store_short v22, v84, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+23], s[sgprBeta], v85, v[vgprValuC+23] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v23, v[vgprValuC+23] // convert C to fp16 +buffer_store_short v23, v86, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+24], s[sgprBeta], v87, v[vgprValuC+24] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v24, v[vgprValuC+24] // convert C to fp16 +buffer_store_short v24, v88, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+25], s[sgprBeta], v89, v[vgprValuC+25] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v25, v[vgprValuC+25] // convert C to fp16 +buffer_store_short v25, v90, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+26], s[sgprBeta], v91, v[vgprValuC+26] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v26, v[vgprValuC+26] // convert C to fp16 +buffer_store_short v26, v92, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+27], s[sgprBeta], v93, v[vgprValuC+27] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v27, v[vgprValuC+27] // convert C to fp16 +buffer_store_short v27, v94, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+28], s[sgprBeta], v95, v[vgprValuC+28] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v28, v[vgprValuC+28] // convert C to fp16 +buffer_store_short v28, v96, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+29], s[sgprBeta], v97, v[vgprValuC+29] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v29, v[vgprValuC+29] // convert C to fp16 +buffer_store_short v29, v98, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+30], s[sgprBeta], v99, v[vgprValuC+30] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v30, v[vgprValuC+30] // convert C to fp16 +buffer_store_short v30, v100, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+31], s[sgprBeta], v101, v[vgprValuC+31] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v31, v[vgprValuC+31] // convert C to fp16 +buffer_store_short v31, v102, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+32], s[sgprBeta], v103, v[vgprValuC+32] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v32, v[vgprValuC+32] // convert C to fp16 +buffer_store_short v32, v104, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+33], s[sgprBeta], v105, v[vgprValuC+33] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v33, v[vgprValuC+33] // convert C to fp16 +buffer_store_short v33, v106, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+34], s[sgprBeta], v107, v[vgprValuC+34] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v34, v[vgprValuC+34] // convert C to fp16 +buffer_store_short v34, v108, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+35], s[sgprBeta], v109, v[vgprValuC+35] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v35, v[vgprValuC+35] // convert C to fp16 +buffer_store_short v35, v110, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+36], s[sgprBeta], v111, v[vgprValuC+36] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v36, v[vgprValuC+36] // convert C to fp16 +buffer_store_short v36, v112, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+37], s[sgprBeta], v113, v[vgprValuC+37] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v37, v[vgprValuC+37] // convert C to fp16 +buffer_store_short v37, v114, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+38], s[sgprBeta], v115, v[vgprValuC+38] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v38, v[vgprValuC+38] // convert C to fp16 +buffer_store_short v38, v116, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+39], s[sgprBeta], v117, v[vgprValuC+39] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v39, v[vgprValuC+39] // convert C to fp16 +buffer_store_short v39, v118, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+40], s[sgprBeta], v119, v[vgprValuC+40] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v40, v[vgprValuC+40] // convert C to fp16 +buffer_store_short v40, v120, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+41], s[sgprBeta], v121, v[vgprValuC+41] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v41, v[vgprValuC+41] // convert C to fp16 +buffer_store_short v41, v122, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+42], s[sgprBeta], v123, v[vgprValuC+42] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v42, v[vgprValuC+42] // convert C to fp16 +buffer_store_short v42, v124, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+43], s[sgprBeta], v125, v[vgprValuC+43] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v43, v[vgprValuC+43] // convert C to fp16 +buffer_store_short v43, v126, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+44], s[sgprBeta], v127, v[vgprValuC+44] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v44, v[vgprValuC+44] // convert C to fp16 +buffer_store_short v44, v128, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+45], s[sgprBeta], v129, v[vgprValuC+45] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v45, v[vgprValuC+45] // convert C to fp16 +buffer_store_short v45, v130, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+46], s[sgprBeta], v131, v[vgprValuC+46] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v46, v[vgprValuC+46] // convert C to fp16 +buffer_store_short v46, v132, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+47], s[sgprBeta], v133, v[vgprValuC+47] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v47, v[vgprValuC+47] // convert C to fp16 +buffer_store_short v47, v134, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+48], s[sgprBeta], v135, v[vgprValuC+48] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v48, v[vgprValuC+48] // convert C to fp16 +buffer_store_short v48, v136, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+49], s[sgprBeta], v137, v[vgprValuC+49] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v49, v[vgprValuC+49] // convert C to fp16 +buffer_store_short v49, v138, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+50], s[sgprBeta], v139, v[vgprValuC+50] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v50, v[vgprValuC+50] // convert C to fp16 +buffer_store_short v50, v140, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+51], s[sgprBeta], v141, v[vgprValuC+51] op_sel:[0,0,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v51, v[vgprValuC+51] // convert C to fp16 +buffer_store_short v51, v142, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +v_fma_mix_f32 v[vgprValuC+52], s[sgprBeta], v143, v[vgprValuC+52] op_sel:[0,1,0] op_sel_hi:[0,1,0] // //C*=beta +v_cvt_f16_f32 v52, v[vgprValuC+52] // convert C to fp16 +buffer_store_short v52, v144, s[sgprSrdD:sgprSrdD+3], 0 offen offset:0 // store D +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_branch label_GW_End_1 // jump to end +label_SK_Partials_1: +label_GW_Partials_E0: +s_mov_b64 s[sgprSrdWS+0:sgprSrdWS+0+1], s[sgprAddressWS+0:sgprAddressWS+0+1] // init SRD base address +s_mov_b32 s[sgprSrdWS+2], BufferOOB +s_mov_b32 s[sgprSrdWS+3], Srd127_96 // Set bits 127_96 in post-loop SRD + +s_mul_i32 s8, 0x20000, s[sgprStreamKIdx] // Offset to correct partials tile +s_add_u32 s[sgprSrdWS+0], s[sgprSrdWS+0], s8 // add lo to SRD +s_addc_u32 s[sgprSrdWS+1], s[sgprSrdWS+1], 0 // add hi to SRD + +/* edge=0, allocate 2 sgpr. perBatchTmpS=2 perBatchMaskS=0 perElementMaskS=0 elementsPerBatch=60 */ +/* optSingleColVgpr=1 optSharedColVgpr=0 optSGPRUsage=BufferLoad_Mask optSrdIncForRow=1 */ + +/******************************************/ +/* Partials Write Batch #0 (d1,d0,vc1,vc0) = */ +/* (0,0,0,0:vw4); (0,0,1,0:vw4); (0,0,2,0:vw4); (0,0,3,0:vw4); (0,0,4,0:vw4); (0,0,5,0:vw4); (0,0,6,0:vw4); (0,0,7,0:vw4); (0,0,8,0:vw4); (0,0,9,0:vw4); (0,0,10,0:vw4); (0,0,11,0:vw4); (0,0,12,0:vw4); (0,0,13,0:vw4); (0,0,14,0:vw4); (0,0,15,0:vw4); (0,0,16,0:vw4); (0,0,17,0:vw4); (0,0,18,0:vw4); (0,0,19,0:vw4); (0,0,20,0:vw4); (0,0,21,0:vw4); (0,0,22,0:vw4); (0,0,23,0:vw4); (0,0,24,0:vw4); (0,0,25,0:vw4); (0,0,26,0:vw4); (0,0,27,0:vw4); (0,0,28,0:vw4); (0,0,29,0:vw4); (0,0,30,0:vw4); (0,0,31,0:vw4) */ +/******************************************/ + +/* calc coords, apply mask, and issue loads (if necessary) */ +v_accvgpr_read_b32 v[vgprValuC+12], acc0 // copy acc to vreg[0] +v_accvgpr_read_b32 v[vgprValuC+13], acc4 // copy acc to vreg[1] +v_accvgpr_read_b32 v[vgprValuC+14], acc8 // copy acc to vreg[2] +v_accvgpr_read_b32 v[vgprValuC+15], acc12 // copy acc to vreg[3] +v_accvgpr_read_b32 v[vgprValuC+16], acc16 // copy acc to vreg[4] +v_accvgpr_read_b32 v[vgprValuC+17], acc20 // copy acc to vreg[5] +v_accvgpr_read_b32 v[vgprValuC+18], acc24 // copy acc to vreg[6] +v_accvgpr_read_b32 v[vgprValuC+19], acc28 // copy acc to vreg[7] +v_accvgpr_read_b32 v[vgprValuC+20], acc32 // copy acc to vreg[8] +v_accvgpr_read_b32 v[vgprValuC+21], acc36 // copy acc to vreg[9] +v_accvgpr_read_b32 v[vgprValuC+22], acc40 // copy acc to vreg[10] +v_accvgpr_read_b32 v[vgprValuC+23], acc44 // copy acc to vreg[11] +v_accvgpr_read_b32 v[vgprValuC+24], acc48 // copy acc to vreg[12] +v_accvgpr_read_b32 v[vgprValuC+25], acc52 // copy acc to vreg[13] +v_accvgpr_read_b32 v[vgprValuC+26], acc56 // copy acc to vreg[14] +v_accvgpr_read_b32 v[vgprValuC+27], acc60 // copy acc to vreg[15] +v_accvgpr_read_b32 v[vgprValuC+28], acc64 // copy acc to vreg[16] +v_accvgpr_read_b32 v[vgprValuC+29], acc68 // copy acc to vreg[17] +v_accvgpr_read_b32 v[vgprValuC+30], acc72 // copy acc to vreg[18] +v_accvgpr_read_b32 v[vgprValuC+31], acc76 // copy acc to vreg[19] +v_accvgpr_read_b32 v[vgprValuC+32], acc80 // copy acc to vreg[20] +v_accvgpr_read_b32 v[vgprValuC+33], acc84 // copy acc to vreg[21] +v_accvgpr_read_b32 v[vgprValuC+34], acc88 // copy acc to vreg[22] +v_accvgpr_read_b32 v[vgprValuC+35], acc92 // copy acc to vreg[23] +v_accvgpr_read_b32 v[vgprValuC+36], acc96 // copy acc to vreg[24] +v_accvgpr_read_b32 v[vgprValuC+37], acc100 // copy acc to vreg[25] +v_accvgpr_read_b32 v[vgprValuC+38], acc104 // copy acc to vreg[26] +v_accvgpr_read_b32 v[vgprValuC+39], acc108 // copy acc to vreg[27] +v_accvgpr_read_b32 v[vgprValuC+40], acc112 // copy acc to vreg[28] +v_accvgpr_read_b32 v[vgprValuC+41], acc116 // copy acc to vreg[29] +v_accvgpr_read_b32 v[vgprValuC+42], acc120 // copy acc to vreg[30] +v_accvgpr_read_b32 v[vgprValuC+43], acc124 // copy acc to vreg[31] +v_accvgpr_read_b32 v[vgprValuC+44], acc1 // copy acc to vreg[32] +v_accvgpr_read_b32 v[vgprValuC+45], acc5 // copy acc to vreg[33] +v_accvgpr_read_b32 v[vgprValuC+46], acc9 // copy acc to vreg[34] +v_accvgpr_read_b32 v[vgprValuC+47], acc13 // copy acc to vreg[35] +v_accvgpr_read_b32 v[vgprValuC+48], acc17 // copy acc to vreg[36] +v_accvgpr_read_b32 v[vgprValuC+49], acc21 // copy acc to vreg[37] +v_accvgpr_read_b32 v[vgprValuC+50], acc25 // copy acc to vreg[38] +v_accvgpr_read_b32 v[vgprValuC+51], acc29 // copy acc to vreg[39] +v_accvgpr_read_b32 v[vgprValuC+52], acc33 // copy acc to vreg[40] +v_accvgpr_read_b32 v[vgprValuC+53], acc37 // copy acc to vreg[41] +v_accvgpr_read_b32 v[vgprValuC+54], acc41 // copy acc to vreg[42] +v_accvgpr_read_b32 v[vgprValuC+55], acc45 // copy acc to vreg[43] +v_accvgpr_read_b32 v[vgprValuC+56], acc49 // copy acc to vreg[44] +v_accvgpr_read_b32 v[vgprValuC+57], acc53 // copy acc to vreg[45] +v_accvgpr_read_b32 v[vgprValuC+58], acc57 // copy acc to vreg[46] +v_accvgpr_read_b32 v[vgprValuC+59], acc61 // copy acc to vreg[47] +v_accvgpr_read_b32 v[vgprValuC+60], acc65 // copy acc to vreg[48] +v_accvgpr_read_b32 v[vgprValuC+61], acc69 // copy acc to vreg[49] +v_accvgpr_read_b32 v[vgprValuC+62], acc73 // copy acc to vreg[50] +v_accvgpr_read_b32 v[vgprValuC+63], acc77 // copy acc to vreg[51] +v_accvgpr_read_b32 v[vgprValuC+64], acc81 // copy acc to vreg[52] +v_accvgpr_read_b32 v[vgprValuC+65], acc85 // copy acc to vreg[53] +v_accvgpr_read_b32 v[vgprValuC+66], acc89 // copy acc to vreg[54] +v_accvgpr_read_b32 v[vgprValuC+67], acc93 // copy acc to vreg[55] +v_accvgpr_read_b32 v[vgprValuC+68], acc97 // copy acc to vreg[56] +v_accvgpr_read_b32 v[vgprValuC+69], acc101 // copy acc to vreg[57] +v_accvgpr_read_b32 v[vgprValuC+70], acc105 // copy acc to vreg[58] +v_accvgpr_read_b32 v[vgprValuC+71], acc109 // copy acc to vreg[59] +v_accvgpr_read_b32 v[vgprValuC+72], acc113 // copy acc to vreg[60] +v_accvgpr_read_b32 v[vgprValuC+73], acc117 // copy acc to vreg[61] +v_accvgpr_read_b32 v[vgprValuC+74], acc121 // copy acc to vreg[62] +v_accvgpr_read_b32 v[vgprValuC+75], acc125 // copy acc to vreg[63] +v_accvgpr_read_b32 v[vgprValuC+76], acc2 // copy acc to vreg[64] +v_accvgpr_read_b32 v[vgprValuC+77], acc6 // copy acc to vreg[65] +v_accvgpr_read_b32 v[vgprValuC+78], acc10 // copy acc to vreg[66] +v_accvgpr_read_b32 v[vgprValuC+79], acc14 // copy acc to vreg[67] +v_accvgpr_read_b32 v[vgprValuC+80], acc18 // copy acc to vreg[68] +v_accvgpr_read_b32 v[vgprValuC+81], acc22 // copy acc to vreg[69] +v_accvgpr_read_b32 v[vgprValuC+82], acc26 // copy acc to vreg[70] +v_accvgpr_read_b32 v[vgprValuC+83], acc30 // copy acc to vreg[71] +v_accvgpr_read_b32 v[vgprValuC+84], acc34 // copy acc to vreg[72] +v_accvgpr_read_b32 v[vgprValuC+85], acc38 // copy acc to vreg[73] +v_accvgpr_read_b32 v[vgprValuC+86], acc42 // copy acc to vreg[74] +v_accvgpr_read_b32 v[vgprValuC+87], acc46 // copy acc to vreg[75] +v_accvgpr_read_b32 v[vgprValuC+88], acc50 // copy acc to vreg[76] +v_accvgpr_read_b32 v[vgprValuC+89], acc54 // copy acc to vreg[77] +v_accvgpr_read_b32 v[vgprValuC+90], acc58 // copy acc to vreg[78] +v_accvgpr_read_b32 v[vgprValuC+91], acc62 // copy acc to vreg[79] +v_accvgpr_read_b32 v[vgprValuC+92], acc66 // copy acc to vreg[80] +v_accvgpr_read_b32 v[vgprValuC+93], acc70 // copy acc to vreg[81] +v_accvgpr_read_b32 v[vgprValuC+94], acc74 // copy acc to vreg[82] +v_accvgpr_read_b32 v[vgprValuC+95], acc78 // copy acc to vreg[83] +v_accvgpr_read_b32 v[vgprValuC+96], acc82 // copy acc to vreg[84] +v_accvgpr_read_b32 v[vgprValuC+97], acc86 // copy acc to vreg[85] +v_accvgpr_read_b32 v[vgprValuC+98], acc90 // copy acc to vreg[86] +v_accvgpr_read_b32 v[vgprValuC+99], acc94 // copy acc to vreg[87] +v_accvgpr_read_b32 v[vgprValuC+100], acc98 // copy acc to vreg[88] +v_accvgpr_read_b32 v[vgprValuC+101], acc102 // copy acc to vreg[89] +v_accvgpr_read_b32 v[vgprValuC+102], acc106 // copy acc to vreg[90] +v_accvgpr_read_b32 v[vgprValuC+103], acc110 // copy acc to vreg[91] +v_accvgpr_read_b32 v[vgprValuC+104], acc114 // copy acc to vreg[92] +v_accvgpr_read_b32 v[vgprValuC+105], acc118 // copy acc to vreg[93] +v_accvgpr_read_b32 v[vgprValuC+106], acc122 // copy acc to vreg[94] +v_accvgpr_read_b32 v[vgprValuC+107], acc126 // copy acc to vreg[95] +v_accvgpr_read_b32 v[vgprValuC+108], acc3 // copy acc to vreg[96] +v_accvgpr_read_b32 v[vgprValuC+109], acc7 // copy acc to vreg[97] +v_accvgpr_read_b32 v[vgprValuC+110], acc11 // copy acc to vreg[98] +v_accvgpr_read_b32 v[vgprValuC+111], acc15 // copy acc to vreg[99] +v_accvgpr_read_b32 v[vgprValuC+112], acc19 // copy acc to vreg[100] +v_accvgpr_read_b32 v[vgprValuC+113], acc23 // copy acc to vreg[101] +v_accvgpr_read_b32 v[vgprValuC+114], acc27 // copy acc to vreg[102] +v_accvgpr_read_b32 v[vgprValuC+115], acc31 // copy acc to vreg[103] +v_accvgpr_read_b32 v[vgprValuC+116], acc35 // copy acc to vreg[104] +v_accvgpr_read_b32 v[vgprValuC+117], acc39 // copy acc to vreg[105] +v_accvgpr_read_b32 v[vgprValuC+118], acc43 // copy acc to vreg[106] +v_accvgpr_read_b32 v[vgprValuC+119], acc47 // copy acc to vreg[107] +v_accvgpr_read_b32 v[vgprValuC+120], acc51 // copy acc to vreg[108] +v_accvgpr_read_b32 v[vgprValuC+121], acc55 // copy acc to vreg[109] +v_accvgpr_read_b32 v[vgprValuC+122], acc59 // copy acc to vreg[110] +v_accvgpr_read_b32 v[vgprValuC+123], acc63 // copy acc to vreg[111] +v_accvgpr_read_b32 v[vgprValuC+124], acc67 // copy acc to vreg[112] +v_accvgpr_read_b32 v[vgprValuC+125], acc71 // copy acc to vreg[113] +v_accvgpr_read_b32 v[vgprValuC+126], acc75 // copy acc to vreg[114] +v_accvgpr_read_b32 v[vgprValuC+127], acc79 // copy acc to vreg[115] +v_accvgpr_read_b32 v[vgprValuC+128], acc83 // copy acc to vreg[116] +v_accvgpr_read_b32 v[vgprValuC+129], acc87 // copy acc to vreg[117] +v_accvgpr_read_b32 v[vgprValuC+130], acc91 // copy acc to vreg[118] +v_accvgpr_read_b32 v[vgprValuC+131], acc95 // copy acc to vreg[119] +v_accvgpr_read_b32 v[vgprValuC+132], acc99 // copy acc to vreg[120] +v_accvgpr_read_b32 v[vgprValuC+133], acc103 // copy acc to vreg[121] +v_accvgpr_read_b32 v[vgprValuC+134], acc107 // copy acc to vreg[122] +v_accvgpr_read_b32 v[vgprValuC+135], acc111 // copy acc to vreg[123] +v_accvgpr_read_b32 v[vgprValuC+136], acc115 // copy acc to vreg[124] +v_accvgpr_read_b32 v[vgprValuC+137], acc119 // copy acc to vreg[125] +v_accvgpr_read_b32 v[vgprValuC+138], acc123 // copy acc to vreg[126] +v_accvgpr_read_b32 v[vgprValuC+139], acc127 // copy acc to vreg[127] +s_nop 1 // 2 wait states required before reading vgpr + +/* apply mask, calc new C and issue writes */ +v_lshlrev_b32 v7, 4, v[vgprSerial] // v7 = v[vgprSerial] * 16 +s_mov_b32 s8, 0 // Init sgpr offset +buffer_store_dwordx4 v[12:15], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[16:19], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[20:23], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[24:27], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[28:31], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[32:35], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[36:39], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[40:43], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[44:47], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[48:51], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[52:55], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[56:59], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[60:63], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[64:67], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[68:71], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[72:75], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[76:79], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[80:83], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[84:87], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[88:91], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[92:95], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[96:99], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[100:103], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[104:107], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[108:111], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[112:115], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[116:119], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[120:123], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[124:127], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[128:131], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[132:135], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_add_u32 s8, s8, 4096 // Inc sgpr offset +buffer_store_dwordx4 v[136:139], v7, s[sgprSrdWS:sgprSrdWS+3], s8 offen offset:0 sc0 sc1 // addStore +s_nop 0 // 1 wait state required when next inst writes vgprs held by previous dwordx4 store inst +s_waitcnt vmcnt(0) // wait for data store +s_barrier // store all data before setting flag +s_lshl_b32 s8, s[sgprStreamKIdx], 2 // flag offset based on CTA index +v_readfirstlane_b32 s58, v[vgprSerial] // Wave 0 updates flags +s_cmp_eq_u32 s58, 0 // Check for wave 0 +s_cbranch_scc0 label_SK_SkipFlagSet // Skip flag set +s_mov_b32 s58, 1 // flag data +s_store_dword s58, s[sgprAddressFlags:sgprAddressFlags+1], s8 glc // set flag +label_SK_SkipFlagSet: +s_waitcnt lgkmcnt(0) // wait for flag +s_branch label_GW_End_1 // jump to end +label_GW_End_1: +label_SK_CloseLoop: +s_cmp_ge_u32 s[sgprStreamKIter], s[sgprStreamKIterEnd] // Check if done all StreamK iterations +s_cbranch_scc1 label_NoBranch_MIQ4GR62GC67G6AM // Only branch on scc0 +s_getpc_b64 s[64:65] // addr of next instr +s_add_i32 s66, label_PersistentLoopStart, 4 // target branch offset +s_abs_i32 s66, s66 // abs offset +s_sub_u32 s64, s64, s66 // sub target branch offset +s_subb_u32 s65, s65, 0 // sub high and carry +s_setpc_b64 s[64:65] // branch to label_PersistentLoopStart +label_NoBranch_MIQ4GR62GC67G6AM: +label_KernelEnd: +s_endpgm // Kernel End +label_ASM_End: /// The end of the kernel diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 89281bafb745..48126465ea82 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -1132,10 +1132,10 @@ def assignCustomKernelParameters(state): # TODO Override workspace info for custom kernel computeBytes = state["ProblemType"]["ComputeDataType"].numBytes() - state["_WorkspaceSizePerElemC"] = computeBytes + state["_WorkspaceSizePerElemC"] = state["CustomKernel"]["workspaceSizePerElemC"] state["_WorkspaceSizePerElemBias"] = 0 if state["ProblemType"]["UseBias"] and state["ProblemType"]["Gradient"]: - state["_WorkspaceSizePerElemBias"] = computeBytes + state["_WorkspaceSizePerElemBias"] = state["CustomKernel"]["workspaceSizePerElemBias"] # state["WorkspaceCheck"] = [state["_WorkspaceSizePerElemC"], state["_WorkspaceSizePerElemBias"], state["GlobalSplitU"] if (state["GlobalSplitUAlgorithm"] == 'MultipleBuffer' or state["_GlobalAccumulation"] == 'MultipleBufferSingleKernel') else 1] # state["MIWaveGroup"] = [state["SubGroup0"] // state["WavefrontSize"], state["SubGroup1"]] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml new file mode 100644 index 000000000000..227d5e6ca0fe --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml @@ -0,0 +1,98 @@ +TestParameters: + marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + NewClient: 2 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + PrintSolutionRejectionReason: True + + # PrintTensorA: 1 + # PrintTensorB: 1 + # PrintTensorD: 2 + # PrintTensorRef: 2 + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 0 + TransposeB: 1 + UseBeta: True + Batched: True + UseBias: 0 + Batched: True + Activation: False + UseScaleAlphaVec: 0 + + - # BenchmarkProblemSizeGroup - Standard - All problem + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1" + args: [ { type: uint32, semantic: GemmCount }, + { type: uint32, semantic: TensileInternalArg0 }, + { type: uint32, semantic: TensileInternalArg1 }, + { type: uint32, semantic: NumWorkGroups }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeFree2 }, + { type: uint32, semantic: SizeSum }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressC }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressB }, + { type: address, semantic: AddressWorkspace }, + { type: address, semantic: AddressSynchronizer }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideD1 }, + { type: uint32, semantic: StrideC0 }, + { type: uint32, semantic: StrideC1 }, + { type: uint32, semantic: StrideA0 }, + { type: uint32, semantic: StrideA1 }, + { type: uint32, semantic: StrideB0 }, + { type: uint32, semantic: StrideB1 }, + { type: float32, semantic: Alpha }, + { type: float32, semantic: Beta }, + { type: uint32, semantic: ItersPerTile }, + { type: uint32, semantic: MagicNumberItersPerTile }, + { type: uint32, semantic: MagicShiftItersPerTile }, + { type: uint32, semantic: TotalIters }, + { type: uint32, semantic: SKItersPerWG }, + { type: uint32, semantic: SKGrid }, + { type: uint32, semantic: SKTilesAndSplit } ] + # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] + macrotile: [128, 256, 64] + threads: [256, 1, 1] + grid: [TilesXYBatch, One, One] + workspaceType: StreamK + workspaceSizePerElemC: 4 + workspaceSizePerElemBias: 4 + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] + # - Exact: [256, 256, 1, 256] + # - Exact: [2048, 4096, 1, 1024] + - Exact: [4103, 4103, 1, 1031] + # - Exact: [3328, 4096, 1, 4096] + +LibraryLogic: + ScheduleName: "aquavanjaram" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx942" + LibraryType: "GridBased" \ No newline at end of file diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 657c849dd49d..3eacff2f88e5 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -51,6 +51,8 @@ namespace TensileLite { #define CustomArgSemantic_MACRO \ + X_MACRO(GemmCount) \ + X_MACRO(NumWorkGroups) \ X_MACRO(SizeFree0) \ X_MACRO(SizeFree1) \ X_MACRO(SizeFree2) \ @@ -59,6 +61,8 @@ namespace TensileLite X_MACRO(AddressB) \ X_MACRO(AddressC) \ X_MACRO(AddressD) \ + X_MACRO(AddressWorkspace) \ + X_MACRO(AddressSynchronizer) \ X_MACRO(StrideA0) \ X_MACRO(StrideA1) \ X_MACRO(StrideB0) \ @@ -75,6 +79,15 @@ namespace TensileLite X_MACRO(StrideB0Bytes) \ X_MACRO(StrideC0Bytes) \ X_MACRO(StrideD0Bytes) \ + X_MACRO(TensileInternalArg0) \ + X_MACRO(TensileInternalArg1) \ + X_MACRO(ItersPerTile) \ + X_MACRO(MagicNumberItersPerTile) \ + X_MACRO(MagicShiftItersPerTile) \ + X_MACRO(TotalIters) \ + X_MACRO(SKGrid) \ + X_MACRO(SKTilesAndSplit) \ + X_MACRO(SKItersPerWG) \ X_MACRO(Padding) \ X_MACRO(DebugPattern) @@ -121,6 +134,20 @@ namespace TensileLite std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t); std::istream& operator>>(std::istream& stream, CustomGridSize& t); + enum CustomWorkspaceType + { + None, + SplitK, + StreamK, + StreamKWithReduction, + CustomWorkspaceType_Count, + }; + + std::string toString(CustomWorkspaceType type); + CustomWorkspaceType fromStringCustomWorkspaceType(std::string& str); + std::ostream& operator<<(std::ostream& stream, const CustomWorkspaceType& t); + std::istream& operator>>(std::istream& stream, CustomWorkspaceType& t); + struct CustomKernel { std::string name; @@ -128,6 +155,9 @@ namespace TensileLite dim3 macrotile; dim3 threads; vector3 grid; + CustomWorkspaceType workspaceType; + size_t workspaceSizePerElemC; + size_t workspaceSizePerElemBias; }; template @@ -506,6 +536,19 @@ namespace TensileLite KA& args, StreamKSettings const& sk) const; + template + void calculateInternalArgs(uint32_t& internalArg0, + uint32_t& internalArg1, + Hardware const* hardware, + const ContractionProblemParameters& param, + int32_t autoWGM, + size_t autoWGMXCC, + size_t autoWGMXCCCHUNK, + size_t autoStaggerUMapping, + size_t autoStaggerU, + size_t autoStaggerUStrideShift, + uint32_t autoGsuVal) const; + // Common kernel related arguments (e.g. gemm_count, arg type, MT, GSU...) template void kernelArgs(uint32_t gemmCount, diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp index d60222736e1a..aa1e3fd9c235 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/Base.hpp @@ -411,6 +411,20 @@ namespace TensileLite } }; + template + struct EnumTraits + { + using iot = IOTraits; + static void enumeration(IO& io, CustomWorkspaceType& value) + { + for(int i = 0; i < static_cast(CustomWorkspaceType::CustomWorkspaceType_Count); i++) + { + auto const& info = static_cast(i); + iot::enumCase(io, value, TensileLite::toString(info).c_str(), info); + } + } + }; + template struct EnumTraits { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 6001e796b074..5f50600e7ea5 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -85,6 +85,9 @@ namespace TensileLite iot::mapOptional(io, "macrotile", s.macrotile); iot::mapOptional(io, "threads", s.threads); iot::mapOptional(io, "grid", s.grid); + iot::mapOptional(io, "workspaceType", s.workspaceType); + iot::mapOptional(io, "workspaceSizePerElemC", s.workspaceSizePerElemC); + iot::mapOptional(io, "workspaceSizePerElemBias", s.workspaceSizePerElemBias); } const static bool flow = false; diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index f9a07672e7dc..a37b545eb8a9 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -176,6 +176,53 @@ namespace TensileLite return stream; } + std::string toString(CustomWorkspaceType type) + { + switch(type) + { + case CustomWorkspaceType::None: + return "None"; + case CustomWorkspaceType::SplitK: + return "SplitK"; + case CustomWorkspaceType::StreamK: + return "StreamK"; + case CustomWorkspaceType::StreamKWithReduction: + return "StreamKWithReduction"; + case CustomWorkspaceType::CustomWorkspaceType_Count: + break; + } + + throw std::runtime_error(concatenate("Invalid CustomWorkspaceType value: ", static_cast(type))); + } + + CustomWorkspaceType fromStringCustomWorkspaceType(std::string& str) + { + if(str == toString(CustomWorkspaceType::None)) + return CustomWorkspaceType::None; + else if(str == toString(CustomWorkspaceType::SplitK)) + return CustomWorkspaceType::SplitK; + else if(str == toString(CustomWorkspaceType::StreamK)) + return CustomWorkspaceType::StreamK; + else if(str == toString(CustomWorkspaceType::StreamKWithReduction)) + return CustomWorkspaceType::StreamKWithReduction; + else + throw std::runtime_error(concatenate("Invalid CustomWorkspaceType value: ", str)); + return CustomWorkspaceType::CustomWorkspaceType_Count; + } + + std::ostream& operator<<(std::ostream& stream, const CustomWorkspaceType& t) + { + return stream << toString(t); + } + + std::istream& operator>>(std::istream& stream, CustomWorkspaceType& t) + { + std::string strValue; + stream >> strValue; + t = fromStringCustomWorkspaceType(strValue); + return stream; + } + enum class KERNELARGTYPE { NORMAL = 0, @@ -1371,29 +1418,19 @@ namespace TensileLite return gsuVal; } - template - void ContractionSolution::kernelArgs(uint32_t gemmCount, - uint32_t argType, - KA& args, - uint32_t numWorkGroups, - Hardware const* hardware, - const ContractionProblemParameters& param, - int32_t autoWGM, - size_t autoWGMXCC, - size_t autoWGMXCCCHUNK, - size_t autoStaggerUMapping, - size_t autoStaggerU, - size_t autoStaggerUStrideShift, - uint32_t autoGsuVal) const + template + void ContractionSolution::calculateInternalArgs(uint32_t& internalArg0, + uint32_t& internalArg1, + Hardware const* hardware, + const ContractionProblemParameters& param, + int32_t autoWGM, + size_t autoWGMXCC, + size_t autoWGMXCCCHUNK, + size_t autoStaggerUMapping, + size_t autoStaggerU, + size_t autoStaggerUStrideShift, + uint32_t autoGsuVal) const { - if constexpr(!Legacy) - { - gemmCount = gemmCount & 0x3FFFFFFF; - // Currently 0 for kernel args, 1 for args located in HBM. This is a temporary slot. - gemmCount = gemmCount | (argType << 30); - args.template append("gemm_count", gemmCount); - } - uint32_t gsu = param.gsu() > 0 ? param.gsu() : autoGsuVal; bool gsuc = false; // initialized false bool gsuwgmrr = false; // initialized false @@ -1407,8 +1444,9 @@ namespace TensileLite const uint32_t mask16 = 0xFFFF; const uint32_t mask14 = 0x3FFF; const uint32_t mask8 = 0xFF; - uint32_t internalArg0 = 0; - uint32_t internalArg1 = 0; + + internalArg0 = 0; + internalArg1 = 0; if(internalArgsSupport.wgm && internalArgsSupport.version == 0) { @@ -1478,6 +1516,34 @@ namespace TensileLite } else if(T_Debug && Debug::Instance().disableStaggerU()) std::cout << "solution doesn't support configurable staggerU" << std::endl; + } + + template + void ContractionSolution::kernelArgs(uint32_t gemmCount, + uint32_t argType, + KA& args, + uint32_t numWorkGroups, + Hardware const* hardware, + const ContractionProblemParameters& param, + int32_t autoWGM, + size_t autoWGMXCC, + size_t autoWGMXCCCHUNK, + size_t autoStaggerUMapping, + size_t autoStaggerU, + size_t autoStaggerUStrideShift, + uint32_t autoGsuVal) const + { + if constexpr(!Legacy) + { + gemmCount = gemmCount & 0x3FFFFFFF; + // Currently 0 for kernel args, 1 for args located in HBM. This is a temporary slot. + gemmCount = gemmCount | (argType << 30); + args.template append("gemm_count", gemmCount); + } + + uint32_t internalArg0; + uint32_t internalArg1; + calculateInternalArgs(internalArg0, internalArg1, hardware, param, autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal); args.template append("internalArgs", internalArg0); @@ -1571,7 +1637,7 @@ namespace TensileLite rv.args = KernelArguments(T_Debug); rv.args.reserve(1024, 128); rv.kernelName = kernelName; - + AMDGPU const* pAMDGPU = dynamic_cast(&hardware); assert(pAMDGPU); @@ -1657,6 +1723,54 @@ namespace TensileLite // uint32_t numWorkGroups = getNumWorkGroups(rv); // rv.args.template append("numWorkGroups", numWorkGroups); + uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); + auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] = calculateAutoWGM(problem, &hardware, sk.grid); + auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); + uint32_t internalArg0 = 0; + uint32_t internalArg1 = 0; + calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal); + + auto itersPerTile = max(1, problem.getItersPerTile(sizeMapping)); + uint32_t magicNumberItersPerTile; + uint32_t magicShiftItersPerTile; + magicNumberItersPerTile = magicNumber(2, itersPerTile, &magicShiftItersPerTile); + + auto totalTiles = tiles.x * tiles.y * tiles.z; + uint32_t totalIters = totalTiles * itersPerTile; + + uint32_t skSplit = 0; + uint32_t skTiles = 0; + uint32_t skItersPerWG = 0; + if(sk.grid > 0) + { + if(sk.reduction == origami::reduction_t::parallel) + { + skSplit = sk.grid / totalTiles; + skItersPerWG = itersPerTile / skSplit; + } + else + { + int fullTiles = pAMDGPU->skFullTiles; + bool bigEnough = totalTiles > sk.grid; + // skTiles is number of Stream-K tiles to complete + // Two-tile algorithm causes each WG to run an even number of Stream-K iterations, + // followed by an even number of data-parllel tiles. + // If total tiles is evenly divisble by grid size, + // then no Stream-K tiles are needed, all data-parallel + skTiles = sk.grid; + // If not evenly divisible, determine number of Stream-K tiles + if(totalTiles % sk.grid != 0) + { + // Number of data-parallel tiles on each workgroup would be: + // dpTilesPerWG = bigEnough ? (tiles - skTiles) / skGrid : 0; + skTiles = bigEnough ? sk.grid * fullTiles + totalTiles % sk.grid : totalTiles; + // Cap Stream-K tiles at total number of tiles in case of large multiplier + skTiles = min(skTiles, totalTiles); + } + skItersPerWG = skTiles * itersPerTile / sk.grid; + } + } + uint32_t debugPattern = 0xDB000001; if(T_Debug) @@ -1669,6 +1783,16 @@ namespace TensileLite switch(arg.semantic) { + case CustomArgSemantic::GemmCount: + // TODO GroupedGemm support + rv.args.appendCustomType("GemmCount", 1, arg.type); + break; + case CustomArgSemantic::NumWorkGroups: + { + uint32_t numWGs = getNumWorkGroups(rv); + rv.args.appendCustomType("NumWorkGroups", numWGs, arg.type); + break; + } case CustomArgSemantic::SizeFree0: rv.args.appendCustomType("SizeFree0", problem.problemSizes()[0], arg.type); break; @@ -1693,6 +1817,12 @@ namespace TensileLite case CustomArgSemantic::AddressD: rv.args.template append("AddressD", inputs.d); break; + case CustomArgSemantic::AddressWorkspace: + rv.args.template append("AddressWorkspace", inputs.ws); + break; + case CustomArgSemantic::AddressSynchronizer: + rv.args.template append("AddressSynchronizer", inputs.Synchronizer); + break; case CustomArgSemantic::StrideA0: rv.args.appendCustomType("StrideA0", problem.a().strides()[1], arg.type); break; @@ -1751,6 +1881,36 @@ namespace TensileLite rv.args.appendCustomType("StrideD0Bytes", problem.d().strides()[1] * problem.d().elementBytes(), arg.type); break; + case CustomArgSemantic::TensileInternalArg0: + rv.args.appendCustomType("TensileInternalArg0", internalArg0, arg.type); + break; + case CustomArgSemantic::TensileInternalArg1: + rv.args.appendCustomType("TensileInternalArg1", internalArg1, arg.type); + break; + case CustomArgSemantic::ItersPerTile: + rv.args.appendCustomType("ItersPerTile", itersPerTile, arg.type); + break; + case CustomArgSemantic::MagicNumberItersPerTile: + rv.args.appendCustomType("MagicNumberItersPerTile", magicNumberItersPerTile, arg.type); + break; + case CustomArgSemantic::MagicShiftItersPerTile: + rv.args.appendCustomType("MagicShiftItersPerTile", magicShiftItersPerTile, arg.type); + break; + case CustomArgSemantic::TotalIters: + rv.args.appendCustomType("TotalIters", totalIters, arg.type); + break; + case CustomArgSemantic::SKGrid: + rv.args.appendCustomType("SKGrid", sk.grid, arg.type); + break; + case CustomArgSemantic::SKTilesAndSplit: + if(sk.reduction == origami::reduction_t::parallel) + rv.args.appendCustomType("SKTilesAndSplit", skSplit, arg.type); + else + rv.args.appendCustomType("SKTilesAndSplit", skTiles, arg.type); + break; + case CustomArgSemantic::SKItersPerWG: + rv.args.appendCustomType("SKItersPerWG", skItersPerWG, arg.type); + break; case CustomArgSemantic::Padding: rv.args.template append("Padding", 0); break; @@ -3120,10 +3280,19 @@ namespace TensileLite } StreamKSettings sk; - if(sizeMapping.streamK > 0) + bool customStreamK = customKernel.workspaceType == CustomWorkspaceType::StreamK || customKernel.workspaceType == CustomWorkspaceType::StreamKWithReduction; + if(sizeMapping.streamK > 0 || customStreamK) { sk.reduction = getSKReduction(problem, hardware); - auto tiles = problem.getNumTiles(sizeMapping, 1); + size_t tiles = 0; + if (customKernel.name.empty()) + tiles = problem.getNumTiles(sizeMapping, 1); + else + { + dim3 dimTiles; + calculateTiles(dimTiles, problem); + tiles = dimTiles.x * dimTiles.y * dimTiles.z; + } sk.grid = getSKGrid(problem, hardware, tiles, sk.reduction); const bool streamKDP = Debug::Instance().useStreamKDataParrallel(); if(sk.grid > 0 @@ -3165,8 +3334,6 @@ namespace TensileLite rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); } - - if(((sizeMapping.globalAccumulation != 3) && gsu > 1 && sizeMapping.globalAccumulation) || sk.reduction == origami::reduction_t::parallel) { @@ -3534,7 +3701,18 @@ namespace TensileLite size_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : sizeMapping.globalSplitU; - if(sizeMapping.streamK > 0 && sizeMapping.streamKAtomic == 0) + CustomWorkspaceType workspaceType = CustomWorkspaceType::None; + if(customKernel.name.empty()) + { + if(sizeMapping.streamK > 0 && sizeMapping.streamKAtomic == 0) + workspaceType = CustomWorkspaceType::StreamKWithReduction; + else + workspaceType = CustomWorkspaceType::SplitK; + } + else + workspaceType = customKernel.workspaceType; + + if(workspaceType == CustomWorkspaceType::StreamK || workspaceType == CustomWorkspaceType::StreamKWithReduction) { // SK doesn't care gsu if(gsu > 1) @@ -3544,11 +3722,22 @@ namespace TensileLite gsu = 1; } const bool streamKDP = Debug::Instance().useStreamKDataParrallel(); - auto tiles = problem.getNumTiles(sizeMapping, 1); + size_t tiles = 0; + if (customKernel.name.empty()) + tiles = problem.getNumTiles(sizeMapping, 1); + else + { + dim3 dimTiles; + calculateTiles(dimTiles, problem); + tiles = dimTiles.x * dimTiles.y * dimTiles.z; + } + if(tiles > 0) // Grouped GEMM reports 0 tiles { - auto reductionStrat = getSKReduction(problem, hardware); - size_t skGrid = getSKGrid(problem, hardware, tiles, reductionStrat); + auto reductionStrat = origami::reduction_t::tree; + if(workspaceType == CustomWorkspaceType::StreamKWithReduction) + reductionStrat = getSKReduction(problem, hardware); + size_t skGrid = getSKGrid(problem, hardware, tiles, reductionStrat); // Get space required for partial tiles= if(reductionStrat == origami::reduction_t::parallel) { @@ -3568,7 +3757,7 @@ namespace TensileLite } } } - else + else if(workspaceType == CustomWorkspaceType::SplitK) { // TODO: Pass GSU from problem and change value[2] to gsu if gsu != default value size_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() @@ -3587,8 +3776,18 @@ namespace TensileLite size_t gsuMultiplier = gsu > 1 ? gsu : 0; size_t batch = problem.d().sizes()[2]; size_t tiles = problem.getNumTiles(sizeMapping, gsu) * batch; - size_t tileSize - = sizeMapping.macroTile.x * sizeMapping.macroTile.y * sizeMapping.workspaceSizePerElemC; + size_t tileSize = 0; + size_t workspaceSizePerElemBias = 0; + if(customKernel.name.empty()) + { + tileSize = sizeMapping.macroTile.x * sizeMapping.macroTile.y * sizeMapping.workspaceSizePerElemC; + workspaceSizePerElemBias = sizeMapping.workspaceSizePerElemBias; + } + else + { + tileSize = customKernel.macrotile.x * customKernel.macrotile.y * customKernel.workspaceSizePerElemC; + workspaceSizePerElemBias = customKernel.workspaceSizePerElemBias; + } size_t bufSize = gsu > 1 ? tiles * tileSize : 0; size += bufSize; @@ -3597,11 +3796,11 @@ namespace TensileLite { if(problem.biasSrc() == ContractionProblemGemm::TENSOR::A) { - size += problem.freeSizeA(0) * sizeMapping.workspaceSizePerElemBias * gsuMultiplier; + size += problem.freeSizeA(0) * workspaceSizePerElemBias * gsuMultiplier; } else if(problem.biasSrc() == ContractionProblemGemm::TENSOR::B) { - size += problem.freeSizeB(0) * sizeMapping.workspaceSizePerElemBias * gsuMultiplier; + size += problem.freeSizeB(0) * workspaceSizePerElemBias * gsuMultiplier; } else if(problem.biasSrc() == ContractionProblemGemm::TENSOR::D && (gsuMultiplier == 0)) { @@ -3612,6 +3811,7 @@ namespace TensileLite // workspace for amaxD if(problemType.outputAmaxD) { + // TODO custom kernel support for AmaxD auto numWGS = getNumWorkGroups(problem, sizeMapping); size += multiplyElementSize(numWGS, problem.amaxd().elementBytes()); } From 66b9fd32916f3cee5185ae237a058b73b96dce9b Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 29 Apr 2026 21:22:54 -0700 Subject: [PATCH 28/58] [hipblaslt] Eliminate duplicate kernel argument configuration (#6092) The kernel launch mechanism in TensileLite previously maintained argument configuration in two places: the Python code generator (which knows the kernel interface) and the C++ host code (generateSingleCall, which reconstructed it from tuning parameters). Any change to the kernel interface required synchronized updates in both locations. **Python codegen (single source of truth)** - `_registerKernelArgs` in `KernelWriter.py` builds the complete argument list at code-generation time, grouped by category (header, sizes, addresses, strides, magic divisors, alpha/beta, StreamK, scale, bias, activation, amax, MBSK) in kernarg-buffer-layout order. - The `CustomKernel` dict (`args`, `macrotile`, `threads`, `grid`) is attached to each kernel and carried through serialization. A `generated` flag distinguishes these from handwritten custom kernels. **C++ host (semantic dispatch)** - `CustomArgSemantic` enum extended with all kernel argument types (header args, extended sizes/strides, metadata/WS/flags addresses, StreamK scalars, magic divisors, scale/bias/E/activation/amax/MBSK args). - `generateCustomCall` handles the full vocabulary. Logic previously in `generateSingleCall` (WS redirect for C/D addresses, magic number computation, StreamK iteration math, GSU grid sizing) is migrated into the corresponding semantic cases. - Enum-to-string / string-to-enum functions refactored from if-else chains to `unordered_map` lookups. - New `TilesXYBatchGSU` grid size mode for generated kernels that receive `NumWorkGroups` as an argument. **Handwritten custom kernel support** - Handwritten custom kernels (`.s` files) that lack an explicit `CustomKernel` section now get one auto-generated by parsing their `amdgpu_metadata` `.args` section (`_buildCustomKernelFromMetadata` in `CustomKernels.py`). **Other changes** - `SizeSum` semantic fixed from hardcoded problem-size index 3 to `problemSizes.size() - 1` (correct for varying numbers of free/batch dimensions). - `CustomArgDefinition` gains an `index` field for semantics that are per-dimension (e.g. `MagicNumberSize`, `MagicShiftSize`, `ActivationArg`). - Solution initialization (`Solution.py`) saves and restores the codegen-produced `CustomKernel` dict around `assignDerivedParameters` so generated kernels go through full validation while preserving their argument metadata. - StreamK parallel reduction no longer gated behind `customKernel.name.empty()`. No regression on the tests of `hipblaslt-test` and `Tensile/Tests/common/gemm/` on both `gfx950` and `gfx942` --- .../tensilelite/Tensile/Contractions.py | 6 +- .../tensilelite/Tensile/CustomKernels.py | 198 ++++- .../tensilelite/Tensile/KernelWriter.py | 164 +++- .../tensilelite/Tensile/LibraryIO.py | 11 +- .../Tensile/SolutionStructs/Naming.py | 3 +- .../Tensile/SolutionStructs/Solution.py | 59 +- .../Tensile/TensileCreateLibrary/Run.py | 19 +- .../TensileLogic/HandleCustomKernel.py | 5 +- .../Tensile/Tests/custom/custom_aiter_f4.yaml | 4 +- .../Tests/custom/custom_wave_bf16.yaml | 2 +- .../include/Tensile/ContractionSolution.hpp | 89 ++- .../Serialization/ContractionSolution.hpp | 1 + .../tensilelite/src/ContractionSolution.cpp | 747 ++++++++++-------- 13 files changed, 896 insertions(+), 412 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index d71390a49c74..4054df1d340e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -623,9 +623,9 @@ def FromOriginalState(cls, d): macrotile=d['macrotile'], threads=d['threads'], grid=d['grid'], - workspaceType=d['workspaceType'], - workspaceSizePerElemC=d['workspaceSizePerElemC'], - workspaceSizePerElemBias=d['workspaceSizePerElemBias']) + workspaceType=d.get('workspaceType', 'None'), + workspaceSizePerElemC=d.get('workspaceSizePerElemC', 0), + workspaceSizePerElemBias=d.get('workspaceSizePerElemBias', 0)) def __init__(self, **kwargs): for (key, value) in list(kwargs.items()): diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 1c6c432f4452..e9cb68dabbac 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -25,12 +25,70 @@ from . import CUSTOM_KERNEL_PATH from Tensile.Common.ValidParameters import checkParametersAreValid, validParameters, newMIValidParameters +import re import yaml import os +# --------------------------------------------------------------------------- +# Mapping from amdgpu_metadata arg .name -> CustomArgSemantic string +# --------------------------------------------------------------------------- +_METADATA_NAME_TO_SEMANTIC = { + "Gemm info": "GemmInfo", + "kernel info": "InternalArgs", + "kernel info0": "InternalArgs", + "kernel info1": "InternalArgs1", + "internalArgs": "InternalArgs", + "numWG": "NumWorkGroups", + "D": "AddressD", + "C": "AddressC", + "A": "AddressA", + "B": "AddressB", + "MetaData": "AddressMetadata", + "AddressDbg": "DebugBuffer", + "AddressWS": "AddressWorkspace", + "AddressFlags": "AddressFlags", + "alpha": "Alpha", + "beta": "Beta", + "AddressScaleA": "AddressScaleA", + "AddressScaleB": "AddressScaleB", + "AddressScaleC": "AddressScaleC", + "AddressScaleD": "AddressScaleD", + "AddressMXScaleA": "AddressMXScaleA", + "AddressMXScaleB": "AddressMXScaleB", + "AddressScaleAlphaVec": "AddressScaleAlphaVec", + "bias": "AddressBias", + "biasType": "BiasType", + "StrideBias": "StrideBias", + "factorDim": "FactorDim", + "E": "AddressE", + "activationType": "ActivationTypeArg", + "AddrAmaxOut": "AddressAmaxOut", + "AmaxWS": "AmaxWS", + "AmaxSync": "AmaxSync", + "dstD": "AddressTD", + "Synchronizer": "Synchronizer", + "GSUSync": "GSUSync", + "ItersPerTile": "ItersPerTile", + "MagicNumberItersPerTile": "MagicNumberItersPerTile", + "MagicShiftItersPerTile": "MagicShiftItersPerTile", + "TotalIters": "TotalIters", + "SKItersPerWG": "SKItersPerWG", + "skGrid": "SKGrid", + "skTiles": "SKTilesAndSplit", +} + +_ACTIVATION_ARG_INDEX = { + "activationAlpha": 0, + "activationBeta": 1, + "activationGamma": 2, + "activationDelta": 3, +} + def isCustomKernelConfig(config): if "CustomKernel" in config and config["CustomKernel"]["name"]: + if config["CustomKernel"].get("generated", False): + return False return True return bool(config.get("CustomKernelName", "")) @@ -78,6 +136,132 @@ def readCustomKernelConfig(name, directory=CUSTOM_KERNEL_PATH): except yaml.scanner.ScannerError as e: raise RuntimeError("Failed to read configuration for custom kernel: {0}\nDetails:\n{1}".format(name, e)) +def _readFullYaml(name, directory=CUSTOM_KERNEL_PATH): + """Read and return the full parsed YAML (all sections) from a custom kernel .s file.""" + rawConfig, _ = getCustomKernelConfigAndAssembly(name, directory) + try: + return yaml.safe_load(rawConfig) + except yaml.scanner.ScannerError as e: + raise RuntimeError("Failed to read YAML for custom kernel: {0}\nDetails:\n{1}".format(name, e)) + +def _metadataArgToCustomArg(metaArg): + """Convert a single amdgpu_metadata .args entry to a CustomKernel arg dict.""" + name = metaArg[".name"] + size = metaArg[".size"] + valueKind = metaArg[".value_kind"] + + if valueKind == "global_buffer": + argType = "address" + elif size == 8: + argType = "float64" + else: + argType = "uint32" + + if name in _METADATA_NAME_TO_SEMANTIC: + return {"type": argType, "semantic": _METADATA_NAME_TO_SEMANTIC[name]} + + if name in _ACTIVATION_ARG_INDEX: + actType = "float64" if size > 4 else "float32" + entry = {"type": actType, "semantic": "ActivationArg"} + idx = _ACTIVATION_ARG_INDEX[name] + if idx: + entry["index"] = idx + return entry + + m = re.match(r"SizesFree(\d+)", name) + if m: + return {"type": argType, "semantic": "SizeFree%s" % m.group(1)} + + m = re.match(r"SizesSum(\d+)", name) + if m: + idx = int(m.group(1)) + return {"type": argType, "semantic": "SizeSum" if idx == 0 else "SizeSum%d" % idx} + + m = re.match(r"stride([A-Z])(\d+)", name) + if m: + return {"type": argType, "semantic": "Stride%s%s" % (m.group(1), m.group(2))} + + m = re.match(r"strideMetadata(\d+)", name) + if m: + return {"type": argType, "semantic": "StrideMetadata%s" % m.group(1)} + + m = re.match(r"StrideE(\d+)", name) + if m: + return {"type": argType, "semantic": "StrideE%s" % m.group(1)} + + m = re.match(r"(MagicNumberSize|MagicShiftSize)(\w)", name) + if m: + from Tensile.Common.Constants import INDEX_CHARS + idx = INDEX_CHARS.index(m.group(2)) + return {"type": argType, "semantic": m.group(1), "index": idx} + + raise RuntimeError("Unknown metadata arg name: '%s'" % name) + +_HEADER_SEMANTIC_ORDER = { + "GemmInfo": 0, "InternalArgs": 1, "InternalArgs1": 2, "NumWorkGroups": 3, +} + +def _buildCustomKernelFromMetadata(kernelName, fullYaml, kernelConfig): + """Build a CustomKernel dict from the amdgpu_metadata and custom.config sections.""" + kernelMeta = fullYaml["amdhsa.kernels"][0] + + args = [_metadataArgToCustomArg(a) for a in kernelMeta[".args"]] + + # UseUniversalArgs kernels expect a header (GemmInfo, InternalArgs, ...) at + # the start of the kernel argument buffer, followed by the data args. The + # .amdgpu_metadata declares them at interior offsets, so reorder here to + # match the actual runtime layout the assembly prologue depends on. + isp = kernelConfig.get("InternalSupportParams", {}) + if isp.get("UseUniversalArgs", True): + headerArgs = [a for a in args if a["semantic"] in _HEADER_SEMANTIC_ORDER] + dataArgs = [a for a in args if a["semantic"] not in _HEADER_SEMANTIC_ORDER] + headerArgs.sort(key=lambda a: _HEADER_SEMANTIC_ORDER[a["semantic"]]) + args = headerArgs + dataArgs + + mi = kernelConfig.get("MatrixInstruction", kernelConfig.get("MIBlock", [0,0,0,0])) + if len(mi) >= 9 and "MIWaveTile" not in kernelConfig: + wt = [mi[5], mi[6]] + wg = [mi[7], mi[8]] + else: + wt = kernelConfig.get("MIWaveTile", [1, 1]) + wg = kernelConfig.get("MIWaveGroup", [1, 1]) + depthU = kernelConfig.get("DepthU", 0) + macrotile = [mi[0] * wt[0] * wg[0], mi[1] * wt[1] * wg[1], depthU] + + # Fallback: parse macrotile from kernel name if computed values are zero + if macrotile[0] == 0 or macrotile[1] == 0: + m = re.search(r'MT(\d+)x(\d+)x(\d+)', kernelName) + if m: + macrotile = [int(m.group(1)), int(m.group(2)), int(m.group(3))] + + threads = [kernelMeta.get(".max_flat_workgroup_size", 256), 1, 1] + + streamK = kernelConfig.get("StreamK", 0) + hasNumWGArg = any(a.get("semantic") == "NumWorkGroups" for a in args) + + if streamK: + batched = kernelConfig.get("ProblemType", {}).get("Batched", False) + grid = ["StreamKWithBatch" if batched else "StreamKNoBatch", "One", "One"] + elif hasNumWGArg: + # Version >= 1 kernels receive numWorkGroups as arg and decompose + # the flat 1-D work-group index internally. + grid = ["TilesXYBatchGSU", "One", "One"] + else: + # Version 0 kernels rely on hardware gridDim for tile decomposition, + # so the grid must be multi-dimensional. + grid = ["TilesX", "TilesY", "Batch"] + + return { + "name": kernelName, + "args": args, + "macrotile": macrotile, + "threads": threads, + "grid": grid, + "workspaceType": "None", + "workspaceSizePerElemC": 0, + "workspaceSizePerElemBias": 0, + } + def getCustomKernelConfig( kernelName: str, internalSupportParams: dict, directory: str = CUSTOM_KERNEL_PATH ) -> dict: @@ -114,9 +298,15 @@ def getCustomKernelConfig( checkParametersAreValid((k, [v]), validParameters) kernelConfig["KernelLanguage"] = "Assembly" - if "CustomKernel" in kernelConfig: - kernelConfig["CustomKernel"]["name"] = kernelName - else: - kernelConfig["CustomKernelName"] = kernelName + + if "CustomKernel" not in kernelConfig: + fullYaml = _readFullYaml(kernelName, directory) + kernelConfig["CustomKernel"] = _buildCustomKernelFromMetadata(kernelName, fullYaml, kernelConfig) + + kernelConfig["CustomKernel"]["name"] = kernelName + kernelConfig["CustomKernel"].setdefault("workspaceType", "None") + kernelConfig["CustomKernel"].setdefault("workspaceSizePerElemC", 0) + kernelConfig["CustomKernel"].setdefault("workspaceSizePerElemBias", 0) + kernelConfig["CustomKernelName"] = kernelName return kernelConfig diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py index 901f83f8581b..c7eea385bfd2 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py @@ -260,7 +260,7 @@ class StateValues: startVgprSerial: int = -1 startVgprSKConsts: int = -1 numVgprSKConsts: int = 0 - startVgprIdentityMatrix: int = -1 + startVgprIdentityMatrix: int = -1 numSgprSizesSum: int = 0 numSgprSizesFree: int = 0 @@ -5449,6 +5449,7 @@ def _initKernel(self, kernel, tensorParametersA, tensorParametersB): self.states = StateValues(version=version, kernel=kernel, kernelName=getKernelNameMin(kernel, self.debugConfig.splitGSU)) self.vgprs = StateVgprs() self.sgprs = collections.OrderedDict() + self.kernelArgDefs = [] self.codes = CodeModules() self.labels = LabelManager() @@ -8013,7 +8014,6 @@ def checkVregOverflowTF32Emu(vgprIdx, numV): storeSgprLoad += self.states.numActivationTypeArgSize + self.states.numactivationArgTotalSize self.states.numStoreSgprToLoad = storeSgprLoad - if self.db["InitLds"] : print ("\n***WARNING: InitLds enabled, may impact performance\n") if self.db["InitSgpr"] : print ("\n***WARNING: InitSgpr enabled, may impact performance\n") if self.db["InitVgpr"] : print ("\n***WARNING: InitVgpr enabled, may impact performance\n") @@ -8626,6 +8626,149 @@ def _syncThreads(self, kernel, comment="", skipForceWaitcnt0=False, memoryToken= ############################################################################## + def _registerKernelArgs(self, kernel): + """Register all kernel arguments for the CustomKernel definition. + + Populates self.kernelArgDefs in kernarg-buffer-layout order + (matching Signature.py). Must be called after _initKernel so that + self.states is fully set up.""" + + def _reg(argType, semantic, index=0): + entry = {"type": argType, "semantic": semantic} + if index: + entry["index"] = index + self.kernelArgDefs.append(entry) + + # -- Header ---------------------------------------------------------------- + _reg("uint32", "GemmInfo") + _reg("uint32", "InternalArgs") + if kernel["InternalSupportParams"]["KernArgsVersion"] >= 1: + _reg("uint32", "InternalArgs1") + _reg("uint32", "NumWorkGroups") + + # -- Sizes ----------------------------------------------------------------- + for i in range(self.states.numSgprSizesFree): + _reg("uint32", "SizeFree%d" % i) + for i in range(self.states.numSgprSizesSum): + _reg("uint32", "SizeSum" if i == 0 else "SizeSum%d" % i) + + # -- Debug buffer ---------------------------------------------------------- + if self.debugConfig.debugKernel: + _reg("address", "DebugBuffer") + + # -- Tensor addresses ------------------------------------------------------ + _reg("address", "AddressD") + _reg("address", "AddressC") + _reg("address", "AddressA") + if kernel["ProblemType"]["MXBlockA"]: + _reg("address", "AddressMXScaleA") + _reg("address", "AddressB") + if kernel["ProblemType"]["MXBlockB"]: + _reg("address", "AddressMXScaleB") + if kernel["ProblemType"]["Sparse"]: + _reg("address", "AddressMetadata") + if kernel["StreamK"] > 0 and kernel["StreamKAtomic"] == 0: + _reg("address", "AddressWorkspace") + _reg("address", "AddressFlags") + + # -- Strides --------------------------------------------------------------- + for i in range(self.states.d.numSgprStrides): + _reg("uint32", "StrideD%d" % i) + for i in range(self.states.c.numSgprStrides): + _reg("uint32", "StrideC%d" % i) + for i in range(self.states.a.numSgprStrides): + _reg("uint32", "StrideA%d" % i) + if kernel["ProblemType"]["MXBlockA"]: + for i in range(self.states.mxsa.numSgprStrides): + _reg("uint32", "StrideScaleA%d" % i) + for i in range(self.states.b.numSgprStrides): + _reg("uint32", "StrideB%d" % i) + if kernel["ProblemType"]["MXBlockB"]: + for i in range(self.states.mxsb.numSgprStrides): + _reg("uint32", "StrideScaleB%d" % i) + if kernel["ProblemType"]["Sparse"]: + for i in range(self.states.m.numSgprStrides): + _reg("uint32", "StrideMetadata%d" % i) + + # -- Packed-batch magic divisors ------------------------------------------- + for i, _ in enumerate(kernel["PackedC0IdxChars"][:-1]): + idx = kernel["PackedC0IndicesX"][i] + _reg("uint32", "MagicNumberSize", idx) + _reg("uint32", "MagicShiftSize", idx) + for i, _ in enumerate(kernel["PackedC1IdxChars"][:-1]): + idx = kernel["PackedC1IndicesX"][i] + _reg("uint32", "MagicNumberSize", idx) + _reg("uint32", "MagicShiftSize", idx) + + # -- Alpha / Beta ---------------------------------------------------------- + numSgprAlpha = max(1, int(self.states.bpeCinternal / 4)) + _reg("float64" if numSgprAlpha > 1 else "uint32", "Alpha") + if kernel["ProblemType"]["UseBeta"]: + numSgprBeta = max(1, int(self.states.bpeCinternal / 4)) + _reg("float64" if numSgprBeta > 1 else "uint32", "Beta") + + # -- StreamK scalar args --------------------------------------------------- + if kernel["StreamK"]: + _reg("uint32", "ItersPerTile") + _reg("uint32", "MagicNumberItersPerTile") + _reg("uint32", "MagicShiftItersPerTile") + _reg("uint32", "SKItersPerWG") + if kernel["StreamK"] >= 2: + _reg("uint32", "SKGrid") + _reg("uint32", "SKTilesAndSplit") + + # -- Scale addresses ------------------------------------------------------- + if kernel["ProblemType"]["UseScaleAB"]: + _reg("address", "AddressScaleA") + _reg("address", "AddressScaleB") + if kernel["ProblemType"]["UseScaleCD"]: + _reg("address", "AddressScaleC") + _reg("address", "AddressScaleD") + if kernel["ProblemType"]["UseScaleAlphaVec"]: + _reg("address", "AddressScaleAlphaVec") + + # -- Bias ------------------------------------------------------------------ + if self.states.useBias != DataDirection.NONE: + _reg("address", "AddressBias") + if self.states.needBiasType: + _reg("uint32", "BiasType") + _reg("uint32", "StrideBias") + + # -- FactorDim ------------------------------------------------------------- + enableFactorDim = False + if kernel["ProblemType"]["UseScaleAlphaVec"] == 3: + enableFactorDim = True + if self.states.needBiasType and kernel["ProblemType"]["UseBias"] == 3: + enableFactorDim = True + if enableFactorDim: + _reg("uint32", "FactorDim") + + # -- E tensor -------------------------------------------------------------- + if kernel["ProblemType"]["UseE"]: + _reg("address", "AddressE") + for i in range(self.states.e.numSgprStrides): + _reg("uint32", "StrideE%d" % i) + + # -- Activation args ------------------------------------------------------- + if ((kernel["ProblemType"]["ActivationType"] != 'none') and kernel["ActivationFused"]): + actArgType = "float64" if self.states.numActivationArgSize > 1 else "float32" + for idx in range(len(kernel["ProblemType"]["ActivationType"].getAdditionalArgStringList())): + _reg(actArgType, "ActivationArg", idx) + if kernel["ProblemType"]["ActivationType"] in ['all', 'hipblaslt_all']: + _reg("uint32", "ActivationTypeArg") + + # -- Amax output ----------------------------------------------------------- + if kernel["ProblemType"]["OutputAmaxD"]: + _reg("address", "AddressAmaxOut") + _reg("address", "AmaxWS") + _reg("address", "AmaxSync") + + # -- MBSK (MultipleBufferSingleKernel) ------------------------------------- + if kernel["GlobalSplitUAlgorithm"] == 'MultipleBufferSingleKernel': + _reg("address", "AddressTD") + _reg("address", "Synchronizer") + _reg("uint32", "GSUSync") + def _getKernelSource(self, kernel: Solution): """ Returns the source of the kernel, either C++ or assembly. @@ -8635,6 +8778,23 @@ def _getKernelSource(self, kernel: Solution): tensorParametersA = {} tensorParametersB = {} self._initKernel(kernel, tensorParametersA, tensorParametersB) + + self._registerKernelArgs(kernel) + gridX = "TilesXYBatchGSU" + if kernel["StreamK"]: + gridX = "StreamKWithBatch" if kernel["ProblemType"]["NumIndicesC"] > 2 else "StreamKNoBatch" + kernel["CustomKernel"] = { + "name": self.states.kernelName, + "args": self.kernelArgDefs, + "macrotile": [kernel["MacroTile0"], kernel["MacroTile1"], kernel["DepthU"]], + "threads": [kernel["NumThreads"], 1, 1], + "grid": [gridX, "One", "One"], + "workspaceType": "None", + "workspaceSizePerElemC": 0, + "workspaceSizePerElemBias": 0, + "generated": True, + } + self.stringIdx = 0 (error, kb) = self.kernelBody(kernel, tensorParametersA, tensorParametersB) fileString += str(kb) diff --git a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py index 4fc0c88c23ce..25479ad3cfbf 100644 --- a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py +++ b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py @@ -398,11 +398,18 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Solution: # force redo the deriving of parameters, make sure old version logic yamls can be validated solutionState["AssignedProblemIndependentDerivedParameters"] = False solutionState["AssignedDerivedParameters"] = False - if "CustomKernel" in solutionState and solutionState["CustomKernel"]["name"]: + customKernelName = None + if "CustomKernel" in solutionState and solutionState["CustomKernel"]["name"] \ + and not solutionState["CustomKernel"].get("generated", False): + customKernelName = solutionState["CustomKernel"]["name"] + elif solutionState.get("CustomKernelName", ""): + customKernelName = solutionState["CustomKernelName"] + + if customKernelName: isp = {} if "InternalSupportParams" in solutionState: isp = solutionState["InternalSupportParams"] - customConfig = getCustomKernelConfig(solutionState["CustomKernel"]["name"], isp) + customConfig = getCustomKernelConfig(customKernelName, isp) for key, value in customConfig.items(): solutionState[key] = value diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py index c3a2d3ef695c..232e70db282a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py @@ -222,7 +222,8 @@ def shortenFileBase(splitGSU, kernel): def getKernelFileBase(splitGSU: bool, kernel): - if "CustomKernel" in kernel and kernel["CustomKernel"]["name"]: + if "CustomKernel" in kernel and kernel["CustomKernel"]["name"] \ + and not kernel["CustomKernel"].get("generated", False): fileBase = kernel["CustomKernel"]["name"] elif kernel.get("CustomKernelName", ""): fileBase = kernel["CustomKernelName"] diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 0cc4d6c5666d..f30a5550115a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -356,7 +356,7 @@ def __init__( for key in defaultInternalSupportParams: assignParameterWithDefault(self["InternalSupportParams"], key, config["InternalSupportParams"], defaultInternalSupportParams) else: - self["InternalSupportParams"] = defaultInternalSupportParams + self["InternalSupportParams"] = dict(defaultInternalSupportParams) # Assign solution state from config, filling missing from the defaultSolution for key in defaultSolution: @@ -394,7 +394,15 @@ def __init__( self["AssignedProblemIndependentDerivedParameters"] = False if "AssignedDerivedParameters" not in self._state: self["AssignedDerivedParameters"] = False - if "CustomKernel" not in self._state: + isHandwrittenCustomKernel = ("CustomKernel" in self._state + and self._state["CustomKernel"].get("name", "") + and not self._state["CustomKernel"].get("generated", False)) + + if isHandwrittenCustomKernel: + Solution._assignCustomKernelParameters(self._state) + self._name = self._state["CustomKernel"]["name"] + else: + savedCustomKernel = self._state.pop("CustomKernel", None) if "CustomKernel" in self._state else None Solution.assignDerivedParameters( self._state, splitGSU, @@ -403,9 +411,9 @@ def __init__( isaInfoMap, assembler.rocm_version ) - else: - Solution.assignCustomKernelParameters(self._state) - self._name = config["CustomKernel"]["name"] if "CustomKernel" in config and config["CustomKernel"]["name"] else None + if savedCustomKernel: + self._state["CustomKernel"] = savedCustomKernel + self._name = None # these keys are copied from ProblemType to internal that may be overridden InternalKeys = ["UseSgprForGRO","VectorStore"] @@ -1135,51 +1143,42 @@ def getDivisorName(state, tC): return divisorName @staticmethod - def assignCustomKernelParameters(state): - # Store values in state so they can be saved in SizeMapping - # Not all SizeMapping values will be needed (or applicable) for custom kernels + def _assignCustomKernelParameters(state): + """Minimal parameter setup for handwritten custom kernels. - state["MacroTile0"] = state["CustomKernel"]["macrotile"][0] - state["MacroTile1"] = state["CustomKernel"]["macrotile"][1] - state["DepthU"] = state["CustomKernel"]["macrotile"][2] + These kernels carry their own argument layout and don't go through the + full assignDerivedParameters validation (which would reject them for + missing MatrixInstruction, etc.).""" + ck = state["CustomKernel"] + state["MacroTile0"] = ck["macrotile"][0] + state["MacroTile1"] = ck["macrotile"][1] + state["DepthU"] = ck["macrotile"][2] - # TODO Temp values to allow serializing SizeMapping state["_GlobalAccumulation"] = None state["CUOccupancy"] = -1 state["MathClocksUnrolledLoop"] = 0 state["PackedC0IndicesX"] = [] state["ThreadTile0"] = 0 state["ThreadTile1"] = 0 - state["NumThreads"] = state["CustomKernel"]["threads"][0] * state["CustomKernel"]["threads"][1] * state["CustomKernel"]["threads"][2] + state["NumThreads"] = ck["threads"][0] * ck["threads"][1] * ck["threads"][2] - # TODO LSU - # numElementsPerWorkGroup = state["MacroTile0"]*state["MacroTile1"]*state["NumWaveSplitK"] numElementsPerWorkGroup = state["MacroTile0"] * state["MacroTile1"] state["NumElementsPerThread"] = numElementsPerWorkGroup // state["NumThreads"] - # TODO Check what DTL affects in SizeMapping state["DirectToLdsA"] = state["DirectToLds"] == 1 or state["DirectToLds"] == 2 state["DirectToLdsB"] = state["DirectToLds"] == 1 or state["DirectToLds"] == 3 - # TODO Override workspace info for custom kernel - computeBytes = state["ProblemType"]["ComputeDataType"].numBytes() - state["_WorkspaceSizePerElemC"] = state["CustomKernel"]["workspaceSizePerElemC"] + state["_WorkspaceSizePerElemC"] = ck.get("workspaceSizePerElemC", 0) state["_WorkspaceSizePerElemBias"] = 0 if state["ProblemType"]["UseBias"] and state["ProblemType"]["Gradient"]: - state["_WorkspaceSizePerElemBias"] = state["CustomKernel"]["workspaceSizePerElemBias"] - # state["WorkspaceCheck"] = [state["_WorkspaceSizePerElemC"], state["_WorkspaceSizePerElemBias"], state["GlobalSplitU"] if (state["GlobalSplitUAlgorithm"] == 'MultipleBuffer' or state["_GlobalAccumulation"] == 'MultipleBufferSingleKernel') else 1] + state["_WorkspaceSizePerElemBias"] = ck.get("workspaceSizePerElemBias", 0) - # state["MIWaveGroup"] = [state["SubGroup0"] // state["WavefrontSize"], state["SubGroup1"]] state["MIWaveGroup"] = [0, 0] - - # state["LocalSplitU"] = state["WorkGroup"][2] state["LocalSplitU"] = 1 - state["GlobalReadVectorWidthA"] = 1 state["GlobalReadVectorWidthB"] = 1 state["StoreVectorWidth"] = 1 - ######################################## # assign all derived parameters @staticmethod @@ -1255,9 +1254,8 @@ def assignDerivedParameters( #del state[s] # Force update _GlobalAccumulation - computeBytes = int(state["ProblemType"]["ComputeDataType"].numBytes()) state["_GlobalAccumulation"] = None - computeName = state["ProblemType"]["ComputeDataType"].toName() + computeName = state["ProblemType"]["ComputeDataType"].toName() if state["UseDotInstruction"] and state["GlobalSplitUAlgorithm"] == 'MultipleBufferSingleKernel': # dot2 kernel does not support MBSK state["GlobalSplitUAlgorithm"] = 'MultipleBuffer' @@ -3636,7 +3634,10 @@ def subCheckLdsBlockSizePerPad(tc, idx): else: reject(state, printRejectionReason, "%s's padded address is inconisstent"%tc) - if(not ("CustomKernel" in state and state["CustomKernel"]["name"] != "")): #don't check the custom kernel. + isActualCustomKernel = bool(state.get("CustomKernelName", "")) or \ + ("CustomKernel" in state and state["CustomKernel"]["name"] != "" + and not state["CustomKernel"].get("generated", False)) + if(not isActualCustomKernel): checkLdsBlockSizePerPad("A") checkLdsBlockSizePerPad("B") diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/Run.py b/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/Run.py index f1d68f4f81c4..32640b0b3144 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/Run.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileCreateLibrary/Run.py @@ -106,6 +106,7 @@ class KernelCodeGenResult(NamedTuple): cuoccupancy: int pgr: int mathclk: int + customKernelDef: Optional[dict] = None class KernelMinResult(NamedTuple): err: int @@ -133,10 +134,12 @@ def processKernelSource(kernelWriterAssembly, data, outOptions, splitGSU, kernel header = kernelWriter.getHeaderFileString(kernel) objFilename = kernel._state.get("codeObjectFile", None) pgr = int(kernel["PrefetchGlobalRead"]) + customKernelDef = kernel._state.get("CustomKernel", None) return KernelCodeGenResult( err, src, header, asmFilename, objFilename, tuple(kernel["ISA"]), \ kernel["WavefrontSize"], kernel["CUOccupancy"], \ - pgr, kernel["MathClocksUnrolledLoop"] + pgr, kernel["MathClocksUnrolledLoop"], \ + customKernelDef ) def _checkInvalidSolutionsAndKernels(errorTolerant, result, kernel): @@ -204,6 +207,18 @@ def passPostKernelInfoToSolution(results, kernels, solutions, splitGSU: bool): solution._state["CUOccupancy"] = result.cuoccupancy solution._state["PrefetchGlobalRead"] = result.pgr solution._state["MathClocksUnrolledLoop"] = result.mathclk + if result.customKernelDef is not None: + solution._state["CustomKernel"] = result.customKernelDef + +def _applyCustomKernelDefToSol(sol, result): + """Copy codegen-emitted CustomKernel definition from a KernelCodeGenResult to a + Contractions.Solution, updating both the originalSolution state and the + Contractions-level customKernel attribute.""" + ckDef = getattr(result, 'customKernelDef', None) + if ckDef is not None: + sol.originalSolution._state["CustomKernel"] = ckDef + from Tensile.Contractions import CustomKernel as CK + sol.customKernel = CK.FromOriginalState(ckDef) def passPostKernelInfoToLibrary(results, kernels, masterLibraries, splitGSU: bool): resultDict = {} @@ -228,6 +243,7 @@ def passPostKernelInfoToLibrary(results, kernels, masterLibraries, splitGSU: boo sol.sizeMapping.UnrollLoopSwapGlobalReadOrder = sol.originalSolution._state['UnrollLoopSwapGlobalReadOrder'] sol.sizeMapping.DirectToVgprA = bool(sol.originalSolution._state['DirectToVgprA']) sol.sizeMapping.DirectToVgprB = bool(sol.originalSolution._state['DirectToVgprB']) + _applyCustomKernelDefToSol(sol, result) except KeyError: print(f"\n{'='*80}") print(f"ERROR: KeyError in masterLibrary.solutions") @@ -257,6 +273,7 @@ def passPostKernelInfoToLibrary(results, kernels, masterLibraries, splitGSU: boo sol.sizeMapping.UnrollLoopSwapGlobalReadOrder = sol.originalSolution._state['UnrollLoopSwapGlobalReadOrder'] sol.sizeMapping.DirectToVgprA = bool(sol.originalSolution._state['DirectToVgprA']) sol.sizeMapping.DirectToVgprB = bool(sol.originalSolution._state['DirectToVgprB']) + _applyCustomKernelDefToSol(sol, result) except KeyError: print(f"\n{'='*80}") print(f"ERROR: KeyError in lazyLibrary") diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py index 9597e4de2ff6..b029ab93867f 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py @@ -49,7 +49,10 @@ def handleCustomKernel(sol: dict, isaInfoMap: Dict[IsaVersion, IsaInfo]) -> Tupl if not isCustomKernelConfig(sol): return sol, False - name = sol["CustomKernel"]["name"] + if "CustomKernel" in sol and sol["CustomKernel"]["name"]: + name = sol["CustomKernel"]["name"] + else: + name = sol.get("CustomKernelName", "") dir = CUSTOM_KERNEL_PATH config = getCustomKernelConfig(name, {}, dir) sol.update(config) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml index c7089094897d..905b014c0545 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -61,8 +61,8 @@ BenchmarkProblems: { type: uint32, semantic: SizeFree1, padding: 12 }, { type: uint32, semantic: SizeFree0, padding: 12 }, { type: uint32, semantic: SizeSum, padding: 12 }, - { type: address, semantic: AddressScaleB, padding: 8 }, - { type: address, semantic: AddressScaleA, padding: 8 }, + { type: address, semantic: AddressMXScaleB, padding: 8 }, + { type: address, semantic: AddressMXScaleA, padding: 8 }, { type: uint32, semantic: StrideScaleB0, padding: 12 }, { type: uint32, semantic: StrideScaleB1, padding: 12 }, { type: uint32, semantic: StrideScaleA0, padding: 12 }, diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml index 6ce94f319071..a8fa67f59c47 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml @@ -89,7 +89,7 @@ BenchmarkProblems: BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: - - Exact: [4096, 4096, 1, 4096] + - Exact: [4096, 4096, 1, 8192] LibraryLogic: ScheduleName: "gfx950" diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 10cf26935378..bbe68a77978c 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -51,31 +51,28 @@ namespace TensileLite { #define CustomArgSemantic_MACRO \ - X_MACRO(GemmCount) \ - X_MACRO(NumWorkGroups) \ + /* Core GEMM problem args */ \ X_MACRO(SizeFree0) \ X_MACRO(SizeFree1) \ X_MACRO(SizeFree2) \ + X_MACRO(SizeFree3) \ X_MACRO(SizeSum) \ - X_MACRO(AddressA) \ - X_MACRO(AddressB) \ - X_MACRO(AddressC) \ - X_MACRO(AddressD) \ -<<<<<<< HEAD - X_MACRO(AddressScaleA) \ - X_MACRO(AddressScaleB) \ -======= - X_MACRO(AddressWorkspace) \ - X_MACRO(AddressSynchronizer) \ ->>>>>>> GemmFromAnywhere_StreamKDemo + X_MACRO(SizeSum1) \ + X_MACRO(SizeSum2) \ X_MACRO(StrideA0) \ X_MACRO(StrideA1) \ + X_MACRO(StrideA2) \ X_MACRO(StrideB0) \ X_MACRO(StrideB1) \ + X_MACRO(StrideB2) \ X_MACRO(StrideC0) \ X_MACRO(StrideC1) \ + X_MACRO(StrideC2) \ X_MACRO(StrideD0) \ X_MACRO(StrideD1) \ + X_MACRO(StrideD2) \ + X_MACRO(StrideE0) \ + X_MACRO(StrideE1) \ X_MACRO(StrideScaleA0) \ X_MACRO(StrideScaleA1) \ X_MACRO(StrideScaleB0) \ @@ -84,24 +81,66 @@ namespace TensileLite X_MACRO(StrideB0Bytes) \ X_MACRO(StrideC0Bytes) \ X_MACRO(StrideD0Bytes) \ -<<<<<<< HEAD + X_MACRO(StrideMetadata0) \ + X_MACRO(StrideMetadata1) \ X_MACRO(Alpha) \ X_MACRO(Beta) \ X_MACRO(SplitK) \ X_MACRO(OutputBF16) \ -======= + X_MACRO(Padding) \ + X_MACRO(DebugPattern) \ + /* Pointer args */ \ + X_MACRO(AddressA) \ + X_MACRO(AddressB) \ + X_MACRO(AddressC) \ + X_MACRO(AddressD) \ + X_MACRO(AddressE) \ + X_MACRO(AddressMetadata) \ + X_MACRO(AddressWorkspace) \ + X_MACRO(AddressFlags) \ + X_MACRO(AddressSynchronizer) \ + X_MACRO(AddressTD) \ + X_MACRO(AddressScaleA) \ + X_MACRO(AddressScaleB) \ + X_MACRO(AddressScaleC) \ + X_MACRO(AddressScaleD) \ + X_MACRO(AddressMXScaleA) \ + X_MACRO(AddressMXScaleB) \ + X_MACRO(AddressScaleAlphaVec) \ + X_MACRO(AddressBias) \ + X_MACRO(AddressAmaxOut) \ + X_MACRO(AmaxWS) \ + X_MACRO(AmaxSync) \ + X_MACRO(Synchronizer) \ + X_MACRO(DebugBuffer) \ + /* Kernel metadata args */ \ + X_MACRO(GemmInfo) \ + X_MACRO(GemmCount) \ + X_MACRO(InternalArgs) \ + X_MACRO(InternalArgs1) \ X_MACRO(TensileInternalArg0) \ X_MACRO(TensileInternalArg1) \ + X_MACRO(NumWorkGroups) \ + /* StreamK scheduling args */ \ X_MACRO(ItersPerTile) \ X_MACRO(MagicNumberItersPerTile) \ X_MACRO(MagicShiftItersPerTile) \ X_MACRO(TotalIters) \ + X_MACRO(SKItersPerWG) \ X_MACRO(SKGrid) \ X_MACRO(SKTilesAndSplit) \ - X_MACRO(SKItersPerWG) \ ->>>>>>> GemmFromAnywhere_StreamKDemo - X_MACRO(Padding) \ - X_MACRO(DebugPattern) + /* Packed batch dimension divisors */ \ + X_MACRO(MagicNumberSize) \ + X_MACRO(MagicShiftSize) \ + /* Epilogue control args */ \ + X_MACRO(BiasType) \ + X_MACRO(StrideBias) \ + X_MACRO(FactorDim) \ + X_MACRO(ActivationTypeArg) \ + X_MACRO(ActivationArg) \ + X_MACRO(GSUSync) \ + /* Random seed args */ \ + X_MACRO(RNDSeed) enum class CustomArgSemantic { @@ -121,6 +160,7 @@ namespace TensileLite CustomArgType type; CustomArgSemantic semantic; size_t padding = 0; + size_t index = 0; }; std::string toString(CustomArgDefinition arg); @@ -137,7 +177,7 @@ namespace TensileLite TilesXYBatch, StreamKWithBatch, StreamKNoBatch, - // TODO SplitK + TilesXYBatchGSU, CustomGridSize_Count, }; @@ -596,13 +636,6 @@ namespace TensileLite Hardware const& hardware, StreamKSettings const& sk) const; - template - KernelInvocation generateSingleCall(Problem const& problem, - ContractionInputs const& inputs, - Hardware const& hardware, - StreamKSettings const& sk, - GSUSettings const& gsuSettings) const; - template KernelInvocation generateSingleCallGroupedGemm(std::vector const& problems, GroupedInputs const& inputs, @@ -627,7 +660,7 @@ namespace TensileLite KA& args, StreamKSettings const& sk, uint32_t autoGsuVal, - uint32_t additionalPaddingPerBatchGeneralBatch=0) const; + uint32_t additionalPaddingPerBatchGeneralBatch=0) const; template inline void calculateConversionCallWorkGroupItems( diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 3a5391dda301..86bc5855db6e 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -102,6 +102,7 @@ namespace TensileLite iot::mapRequired(io, "type", s.type); iot::mapRequired(io, "semantic", s.semantic); iot::mapOptional(io, "padding", s.padding); + iot::mapOptional(io, "index", s.index); } const static bool flow = true; }; diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index a3c0fecace54..50b58aa3f28d 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -45,6 +45,7 @@ #include #include #include +#include #ifdef ENABLE_ROCTX #include @@ -119,22 +120,15 @@ namespace TensileLite { switch(size) { - case CustomGridSize::One: - return "One"; - case CustomGridSize::TilesX: - return "TilesX"; - case CustomGridSize::TilesY: - return "TilesY"; - case CustomGridSize::Batch: - return "Batch"; - case CustomGridSize::TilesXY: - return "TilesXY"; - case CustomGridSize::TilesXYBatch: - return "TilesXYBatch"; - case CustomGridSize::StreamKWithBatch: - return "StreamKWithBatch"; - case CustomGridSize::StreamKNoBatch: - return "StreamKNoBatch"; + case CustomGridSize::One: return "One"; + case CustomGridSize::TilesX: return "TilesX"; + case CustomGridSize::TilesY: return "TilesY"; + case CustomGridSize::Batch: return "Batch"; + case CustomGridSize::TilesXY: return "TilesXY"; + case CustomGridSize::TilesXYBatch: return "TilesXYBatch"; + case CustomGridSize::StreamKWithBatch: return "StreamKWithBatch"; + case CustomGridSize::StreamKNoBatch: return "StreamKNoBatch"; + case CustomGridSize::TilesXYBatchGSU: return "TilesXYBatchGSU"; case CustomGridSize::CustomGridSize_Count: break; } @@ -144,25 +138,23 @@ namespace TensileLite CustomGridSize fromStringCustomGridSize(std::string& str) { - if(str == toString(CustomGridSize::One)) - return CustomGridSize::One; - else if(str == toString(CustomGridSize::TilesX)) - return CustomGridSize::TilesX; - else if(str == toString(CustomGridSize::TilesY)) - return CustomGridSize::TilesY; - else if(str == toString(CustomGridSize::Batch)) - return CustomGridSize::Batch; - else if(str == toString(CustomGridSize::TilesXY)) - return CustomGridSize::TilesXY; - else if(str == toString(CustomGridSize::TilesXYBatch)) - return CustomGridSize::TilesXYBatch; - else if(str == toString(CustomGridSize::StreamKWithBatch)) - return CustomGridSize::StreamKWithBatch; - else if(str == toString(CustomGridSize::StreamKNoBatch)) - return CustomGridSize::StreamKNoBatch; - else - throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", str)); - return CustomGridSize::CustomGridSize_Count; + static const std::unordered_map lookup = { + {"One", CustomGridSize::One}, + {"TilesX", CustomGridSize::TilesX}, + {"TilesY", CustomGridSize::TilesY}, + {"Batch", CustomGridSize::Batch}, + {"TilesXY", CustomGridSize::TilesXY}, + {"TilesXYBatch", CustomGridSize::TilesXYBatch}, + {"StreamKWithBatch", CustomGridSize::StreamKWithBatch}, + {"StreamKNoBatch", CustomGridSize::StreamKNoBatch}, + {"TilesXYBatchGSU", CustomGridSize::TilesXYBatchGSU}, + }; + + auto it = lookup.find(str); + if(it != lookup.end()) + return it->second; + + throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", str)); } std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t) @@ -1641,7 +1633,7 @@ namespace TensileLite numWorkGroups.x = CeilDivide(numWorkGroups.x, sizeMapping.macroTile.x); numWorkGroups.y = CeilDivide(numWorkGroups.y, sizeMapping.macroTile.y); } - + template KernelInvocation ContractionSolution::generateCustomCall(ContractionSolution::Problem const& problem, ContractionInputs const& inputs, @@ -1657,31 +1649,84 @@ namespace TensileLite AMDGPU const* pAMDGPU = dynamic_cast(&hardware); assert(pAMDGPU); - int wavefrontSize = pAMDGPU->wavefrontSize; - // rv.workGroupSize.x = customKernel.waves.x * wavefrontSize; - // rv.workGroupSize.y = customKernel.waves.y * wavefrontSize; - // rv.workGroupSize.z = customKernel.waves.z * wavefrontSize; + if(customKernel.threads.x == 0 || customKernel.macrotile.x == 0) + throw std::runtime_error( + concatenate("Solution ", kernelName, " has uninitialized customKernel metadata")); + + dim3 tiles; + calculateTiles(tiles, problem); + + uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); + uint32_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : autoGsuVal; + + uint32_t skItersPerTile = 0; + uint32_t skTotalIters = 0; + uint32_t skMagicNumberItersPerTile = 0; + uint32_t skMagicShiftItersPerTile = 0; + uint32_t skItersPerWG = 0; + uint32_t skTotalTiles = 0; + if(sk.grid > 0) + { + size_t numTiles = tiles.x * tiles.y * tiles.z; + skItersPerTile = static_cast(max(size_t(1), problem.getItersPerTile(sizeMapping))); + skTotalIters = static_cast(numTiles * skItersPerTile); + skMagicNumberItersPerTile = magicNumber(2, skItersPerTile, &skMagicShiftItersPerTile); + + bool twoTileStreamK = sizeMapping.streamK >= 2 + || customKernel.workspaceType == CustomWorkspaceType::StreamK + || customKernel.workspaceType == CustomWorkspaceType::StreamKWithReduction; + + if(sizeMapping.streamK == 1) // Basic SK + { + skItersPerWG = static_cast(CeilDivide(size_t(skTotalIters), sk.grid)); + } + else if(twoTileStreamK) // Two-tile SK + { + if(sk.reduction == origami::reduction_t::parallel) + { + uint32_t skSplit = static_cast(sk.grid / numTiles); + skItersPerWG = skItersPerTile / max(skSplit, uint32_t(1)); + skTotalTiles = skSplit; + } + else + { + int fullTiles = pAMDGPU->skFullTiles; + bool bigEnough = numTiles > sk.grid; + + // skTotalTiles is the number of Stream-K tiles to complete. + // Two-tile SK gives each WG an even number of Stream-K iterations, + // followed by an even number of data-parallel tiles. + skTotalTiles = static_cast(sk.grid); + if(numTiles % sk.grid != 0) + { + // If tiles are not evenly divisible, determine the number of + // Stream-K tiles and cap it at the total tile count. + size_t skT = bigEnough ? sk.grid * fullTiles + numTiles % sk.grid : numTiles; + skTotalTiles = static_cast(min(skT, numTiles)); + } + skItersPerWG = skTotalTiles * skItersPerTile / max(uint32_t(1), static_cast(sk.grid)); + } + } + } + rv.workGroupSize.x = customKernel.threads.x; rv.workGroupSize.y = customKernel.threads.y; rv.workGroupSize.z = customKernel.threads.z; if(T_Debug) { - std::cout << "Wavefront size: " << wavefrontSize << std::endl; + std::cout << "Wavefront size: " << pAMDGPU->wavefrontSize << std::endl; std::cout << "Threads: " << customKernel.threads.x << ", " << customKernel.threads.y << ", " << customKernel.threads.z << std::endl; std::cout << "Work group size: " << rv.workGroupSize.x << ", " << rv.workGroupSize.y << ", " << rv.workGroupSize.z << std::endl; std::cout << "Macrotile: " << customKernel.macrotile.x << ", " << customKernel.macrotile.y << ", " << customKernel.macrotile.z << std::endl; } - dim3 tiles; - calculateTiles(tiles, problem); - if(T_Debug) { std::cout << "Tiles: " << tiles.x << ", " << tiles.y << ", " << tiles.z << std::endl; } - auto assignGridSize = [tiles](size_t& dim, CustomGridSize size) { + auto assignGridSize = [&](size_t& dim, CustomGridSize size) { switch(size) { case CustomGridSize::One: @@ -1702,12 +1747,15 @@ namespace TensileLite case CustomGridSize::TilesXYBatch: dim = tiles.x * tiles.y * tiles.z; break; - // case CustomGridSize::StreamKWithBatch: - // dim = TODO - // break; - // case CustomGridSize::StreamKNoBatch: - // dim = TODO - // break; + case CustomGridSize::TilesXYBatchGSU: + dim = tiles.x * tiles.y * tiles.z * (gsu > 0 ? gsu : 1); + break; + case CustomGridSize::StreamKWithBatch: + dim = sk.grid * tiles.z; + break; + case CustomGridSize::StreamKNoBatch: + dim = sk.grid; + break; default: throw std::runtime_error(concatenate("Invalid CustomGridSize value: ", static_cast(size))); break; @@ -1718,6 +1766,16 @@ namespace TensileLite assignGridSize(rv.numWorkGroups.y, customKernel.grid.y); assignGridSize(rv.numWorkGroups.z, customKernel.grid.z); + bool hasNumWorkGroupsArg = std::any_of( + customKernel.args.begin(), customKernel.args.end(), + [](auto const& a) { return a.semantic == CustomArgSemantic::NumWorkGroups; }); + if(hasNumWorkGroupsArg && internalArgsSupport.version >= 1) + { + rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + rv.numWorkGroups.y = 1; + rv.numWorkGroups.z = 1; + } + if(T_Debug) { std::cout << "Num work groups: " << rv.numWorkGroups.x << ", " << rv.numWorkGroups.y << ", " << rv.numWorkGroups.z << std::endl; @@ -1727,67 +1785,16 @@ namespace TensileLite rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; - // Temporarily set internal args manually - // uint32_t gemmCount = 1; - // gemmCount = gemmCount & 0x3FFFFFFF; - // rv.args.template append("gemm_count", gemmCount); - // uint32_t internalArg0 = 1048577; - // rv.args.template append("internalArgs", internalArg0); - // int32_t internalArg1 = 436731905; - // rv.args.template append("internalArgs1", internalArg1); - - // uint32_t numWorkGroups = getNumWorkGroups(rv); - // rv.args.template append("numWorkGroups", numWorkGroups); + rv.sharedMemBytes = 0; - uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] = calculateAutoWGM(problem, &hardware, sk.grid); auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); uint32_t internalArg0 = 0; uint32_t internalArg1 = 0; calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal); - auto itersPerTile = max(1, problem.getItersPerTile(sizeMapping)); - uint32_t magicNumberItersPerTile; - uint32_t magicShiftItersPerTile; - magicNumberItersPerTile = magicNumber(2, itersPerTile, &magicShiftItersPerTile); - - auto totalTiles = tiles.x * tiles.y * tiles.z; - uint32_t totalIters = totalTiles * itersPerTile; - - uint32_t skSplit = 0; - uint32_t skTiles = 0; - uint32_t skItersPerWG = 0; - if(sk.grid > 0) - { - if(sk.reduction == origami::reduction_t::parallel) - { - skSplit = sk.grid / totalTiles; - skItersPerWG = itersPerTile / skSplit; - } - else - { - int fullTiles = pAMDGPU->skFullTiles; - bool bigEnough = totalTiles > sk.grid; - // skTiles is number of Stream-K tiles to complete - // Two-tile algorithm causes each WG to run an even number of Stream-K iterations, - // followed by an even number of data-parllel tiles. - // If total tiles is evenly divisble by grid size, - // then no Stream-K tiles are needed, all data-parallel - skTiles = sk.grid; - // If not evenly divisible, determine number of Stream-K tiles - if(totalTiles % sk.grid != 0) - { - // Number of data-parallel tiles on each workgroup would be: - // dpTilesPerWG = bigEnough ? (tiles - skTiles) / skGrid : 0; - skTiles = bigEnough ? sk.grid * fullTiles + totalTiles % sk.grid : totalTiles; - // Cap Stream-K tiles at total number of tiles in case of large multiplier - skTiles = min(skTiles, totalTiles); - } - skItersPerWG = skTiles * itersPerTile / sk.grid; - } - } - uint32_t debugPattern = 0xDB000001; + bool appendedInternalArgs = false; if(T_Debug) std::cout << "Custom call arguments:" << std::endl; @@ -1799,16 +1806,7 @@ namespace TensileLite switch(arg.semantic) { - case CustomArgSemantic::GemmCount: - // TODO GroupedGemm support - rv.args.appendCustomType("GemmCount", 1, arg.type); - break; - case CustomArgSemantic::NumWorkGroups: - { - uint32_t numWGs = getNumWorkGroups(rv); - rv.args.appendCustomType("NumWorkGroups", numWGs, arg.type); - break; - } + // ---- Core GEMM problem args ---- case CustomArgSemantic::SizeFree0: rv.args.appendCustomType("SizeFree0", problem.problemSizes()[0], arg.type); break; @@ -1818,26 +1816,17 @@ namespace TensileLite case CustomArgSemantic::SizeFree2: rv.args.appendCustomType("SizeFree2", problem.problemSizes()[2], arg.type); break; - case CustomArgSemantic::SizeSum: - rv.args.appendCustomType("SizeSum", problem.problemSizes()[3], arg.type); - break; - case CustomArgSemantic::AddressA: - rv.args.template append("AddressA", inputs.a); - break; - case CustomArgSemantic::AddressB: - rv.args.template append("AddressB", inputs.b); - break; - case CustomArgSemantic::AddressC: - rv.args.template append("AddressC", inputs.c); + case CustomArgSemantic::SizeFree3: + rv.args.appendCustomType("SizeFree3", problem.problemSizes()[3], arg.type); break; - case CustomArgSemantic::AddressD: - rv.args.template append("AddressD", inputs.d); + case CustomArgSemantic::SizeSum: + rv.args.appendCustomType("SizeSum", problem.problemSizes()[problem.problemSizes().size() - 1], arg.type); break; - case CustomArgSemantic::AddressWorkspace: - rv.args.template append("AddressWorkspace", inputs.ws); + case CustomArgSemantic::SizeSum1: + rv.args.appendCustomType("SizeSum1", problem.problemSizes()[problem.problemSizes().size() - 2], arg.type); break; - case CustomArgSemantic::AddressSynchronizer: - rv.args.template append("AddressSynchronizer", inputs.Synchronizer); + case CustomArgSemantic::SizeSum2: + rv.args.appendCustomType("SizeSum2", problem.problemSizes()[problem.problemSizes().size() - 3], arg.type); break; case CustomArgSemantic::StrideA0: rv.args.appendCustomType("StrideA0", problem.a().strides()[1], arg.type); @@ -1845,29 +1834,101 @@ namespace TensileLite case CustomArgSemantic::StrideA1: rv.args.appendCustomType("StrideA1", problem.a().strides()[2], arg.type); break; + case CustomArgSemantic::StrideA2: + rv.args.appendCustomType("StrideA2", problem.a().strides()[3], arg.type); + break; case CustomArgSemantic::StrideB0: rv.args.appendCustomType("StrideB0", problem.b().strides()[1], arg.type); break; case CustomArgSemantic::StrideB1: rv.args.appendCustomType("StrideB1", problem.b().strides()[2], arg.type); break; + case CustomArgSemantic::StrideB2: + rv.args.appendCustomType("StrideB2", problem.b().strides()[3], arg.type); + break; case CustomArgSemantic::StrideC0: rv.args.appendCustomType("StrideC0", problem.c().strides()[1], arg.type); break; case CustomArgSemantic::StrideC1: rv.args.appendCustomType("StrideC1", problem.c().strides()[2], arg.type); break; + case CustomArgSemantic::StrideC2: + rv.args.appendCustomType("StrideC2", problem.c().strides()[3], arg.type); + break; case CustomArgSemantic::StrideD0: rv.args.appendCustomType("StrideD0", problem.d().strides()[1], arg.type); break; case CustomArgSemantic::StrideD1: rv.args.appendCustomType("StrideD1", problem.d().strides()[2], arg.type); break; + case CustomArgSemantic::StrideD2: + rv.args.appendCustomType("StrideD2", problem.d().strides()[3], arg.type); + break; + case CustomArgSemantic::StrideE0: + rv.args.appendCustomType("StrideE0", problem.tensor(ContractionProblemGemm::TENSOR::E).strides()[1], arg.type); + break; + case CustomArgSemantic::StrideE1: + rv.args.appendCustomType("StrideE1", problem.tensor(ContractionProblemGemm::TENSOR::E).strides()[2], arg.type); + break; + case CustomArgSemantic::StrideScaleA0: + { + size_t scaleStride = problem.boundSize(0) / problem.mxBlockA(); + rv.args.appendCustomType("StrideScaleA0", scaleStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleA1: + { + auto const& t = problem.mxsa(); + size_t batchStride + = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + rv.args.appendCustomType("StrideScaleA1", batchStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleB0: + { + size_t scaleStride = problem.boundSize(0) / problem.mxBlockB(); + rv.args.appendCustomType("StrideScaleB0", scaleStride, arg.type); + break; + } + case CustomArgSemantic::StrideScaleB1: + { + auto const& t = problem.mxsb(); + size_t batchStride + = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + rv.args.appendCustomType("StrideScaleB1", batchStride, arg.type); + break; + } + case CustomArgSemantic::StrideA0Bytes: + rv.args.appendCustomType("StrideA0Bytes", + problem.a().strides()[1] * problem.a().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideB0Bytes: + rv.args.appendCustomType("StrideB0Bytes", + problem.b().strides()[1] * problem.b().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideC0Bytes: + rv.args.appendCustomType("StrideC0Bytes", + problem.c().strides()[1] * problem.c().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideD0Bytes: + rv.args.appendCustomType("StrideD0Bytes", + problem.d().strides()[1] * problem.d().elementBytes(), arg.type); + break; + case CustomArgSemantic::StrideMetadata0: + rv.args.appendCustomType("StrideMetadata0", problem.metadata().strides()[1], arg.type); + break; + case CustomArgSemantic::StrideMetadata1: + rv.args.appendCustomType("StrideMetadata1", problem.metadata().strides()[2], arg.type); + break; case CustomArgSemantic::Alpha: - rv.args.appendCustomType("Alpha", inputs.alpha, arg.type); + rv.args.append("Alpha", inputs.alpha, problem.alphaType()); + if(problem.alphaType() == rocisa::DataType::Half) + rv.args.append("Alpha_2", inputs.alpha, problem.alphaType()); break; case CustomArgSemantic::Beta: - rv.args.appendCustomType("Beta", inputs.beta, arg.type); + rv.args.append("Beta", inputs.beta, problem.betaType()); + if(problem.betaType() == rocisa::DataType::Half) + rv.args.append("Beta_2", inputs.beta, problem.betaType()); break; case CustomArgSemantic::SplitK: { @@ -1888,93 +1949,249 @@ namespace TensileLite rv.args.appendCustomType("OutputBF16", isBF16, arg.type); break; } - case CustomArgSemantic::StrideA0Bytes: - rv.args.appendCustomType("StrideA0Bytes", - problem.a().strides()[1] * problem.a().elementBytes(), arg.type); + case CustomArgSemantic::Padding: + rv.args.template append("Padding", 0); break; - case CustomArgSemantic::StrideB0Bytes: - rv.args.appendCustomType("StrideB0Bytes", - problem.b().strides()[1] * problem.b().elementBytes(), arg.type); + case CustomArgSemantic::DebugPattern: + rv.args.template append("DebugPattern", debugPattern); + ++debugPattern; break; - case CustomArgSemantic::StrideC0Bytes: - rv.args.appendCustomType("StrideC0Bytes", - problem.c().strides()[1] * problem.c().elementBytes(), arg.type); + + // ---- Pointer args ---- + case CustomArgSemantic::AddressA: + rv.args.template append("AddressA", inputs.a); break; - case CustomArgSemantic::StrideD0Bytes: - rv.args.appendCustomType("StrideD0Bytes", - problem.d().strides()[1] * problem.d().elementBytes(), arg.type); + case CustomArgSemantic::AddressB: + rv.args.template append("AddressB", inputs.b); + break; + case CustomArgSemantic::AddressC: + { + bool useWsC = false; + if(gsu > 1 && sizeMapping.streamK == 0) + { + bool singleWSD = (sizeMapping.globalAccumulation == 1 + && (problemType.computeType != problemType.dType + || problemType.activationType != ActivationType::None)); + if((singleWSD || sizeMapping.globalAccumulation == 2) + && sizeMapping.globalAccumulation != 3) + useWsC = true; + } + if(sizeMapping.streamK > 0 + && sk.reduction == origami::reduction_t::parallel) + useWsC = true; + if(useWsC) + rv.args.template append("AddressC", inputs.ws); + else + rv.args.template append("AddressC", inputs.c); + break; + } + case CustomArgSemantic::AddressD: + { + bool useWsD = false; + if(gsu > 1 && sizeMapping.streamK == 0) + { + bool singleWSD = (sizeMapping.globalAccumulation == 1 + && (problemType.computeType != problemType.dType + || problemType.activationType != ActivationType::None)); + if(singleWSD || sizeMapping.globalAccumulation == 2 + || sizeMapping.globalAccumulation == 3) + useWsD = true; + } + if(sizeMapping.streamK > 0 + && sk.reduction == origami::reduction_t::parallel) + useWsD = true; + if(useWsD) + rv.args.template append("AddressD", inputs.ws); + else + rv.args.template append("AddressD", inputs.d); + break; + } + case CustomArgSemantic::AddressE: + rv.args.template append("AddressE", inputs.e); + break; + case CustomArgSemantic::AddressMetadata: + rv.args.template append("AddressMetadata", inputs.metadata); + break; + case CustomArgSemantic::AddressWorkspace: + rv.args.template append(toString(arg.semantic), inputs.ws); + break; + case CustomArgSemantic::AddressFlags: + if(sk.reduction == origami::reduction_t::parallel) + rv.args.template append("AddressFlags", nullptr); + else + rv.args.template append("AddressFlags", inputs.Synchronizer); + break; + case CustomArgSemantic::AddressSynchronizer: + rv.args.template append("AddressSynchronizer", inputs.Synchronizer); + break; + case CustomArgSemantic::AddressTD: + rv.args.template append("AddressTD", inputs.d); + break; + case CustomArgSemantic::AddressScaleA: + rv.args.template append("AddressScaleA", inputs.scaleA); + break; + case CustomArgSemantic::AddressScaleB: + rv.args.template append("AddressScaleB", inputs.scaleB); + break; + case CustomArgSemantic::AddressScaleC: + rv.args.template append("AddressScaleC", inputs.scaleC); + break; + case CustomArgSemantic::AddressScaleD: + rv.args.template append("AddressScaleD", inputs.scaleD); + break; + case CustomArgSemantic::AddressMXScaleA: + rv.args.template append("AddressMXScaleA", inputs.mxsa); + break; + case CustomArgSemantic::AddressMXScaleB: + rv.args.template append("AddressMXScaleB", inputs.mxsb); + break; + case CustomArgSemantic::AddressScaleAlphaVec: + rv.args.template append("AddressScaleAlphaVec", inputs.scaleAlphaVec); + break; + case CustomArgSemantic::AddressBias: + if(problemType.useGradient + && problem.biasSrc() == ContractionProblemGemm::TENSOR::D + && inputs.bias != nullptr) + rv.args.template append("AddressBias", inputs.ws); + else + rv.args.template append("AddressBias", inputs.bias); + break; + case CustomArgSemantic::AddressAmaxOut: + rv.args.template append("AddressAmaxOut", inputs.amaxD); + break; + case CustomArgSemantic::AmaxWS: + rv.args.template append("AmaxWS", inputs.ws); + break; + case CustomArgSemantic::AmaxSync: + case CustomArgSemantic::Synchronizer: + rv.args.template append(toString(arg.semantic), inputs.Synchronizer); + break; + case CustomArgSemantic::DebugBuffer: + rv.args.template append("DebugBuffer", nullptr); + break; + + // ---- Kernel metadata args ---- + case CustomArgSemantic::GemmInfo: + { + uint32_t gemmCount = 1; + gemmCount = gemmCount & 0x3FFFFFFF; + rv.args.template append("gemm_count", gemmCount); + break; + } + case CustomArgSemantic::GemmCount: + rv.args.appendCustomType("GemmCount", 1, arg.type); + break; + case CustomArgSemantic::InternalArgs: + { + auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] + = calculateAutoWGM(problem, &hardware, sk.grid); + auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] + = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); + kernelArgs(1, 0, rv.args, getNumWorkGroups(rv), + &hardware, problem.getParams(), + autoWGM, autoWGMXCC, autoWGMXCCCHUNK, + autoStaggerUMapping, autoStaggerU, + autoStaggerUStrideShift, autoGsuVal); + appendedInternalArgs = true; break; + } + case CustomArgSemantic::InternalArgs1: + if(!appendedInternalArgs) + rv.args.appendCustomType("InternalArgs1", internalArg1, arg.type); + break; // handled by InternalArgs via kernelArgs when present case CustomArgSemantic::TensileInternalArg0: rv.args.appendCustomType("TensileInternalArg0", internalArg0, arg.type); break; case CustomArgSemantic::TensileInternalArg1: rv.args.appendCustomType("TensileInternalArg1", internalArg1, arg.type); break; + case CustomArgSemantic::NumWorkGroups: + if(!appendedInternalArgs) + rv.args.appendCustomType("NumWorkGroups", getNumWorkGroups(rv), arg.type); + break; // handled by InternalArgs via kernelArgs when present + + // ---- StreamK scheduling args ---- case CustomArgSemantic::ItersPerTile: - rv.args.appendCustomType("ItersPerTile", itersPerTile, arg.type); + rv.args.template append("ItersPerTile", skItersPerTile); break; case CustomArgSemantic::MagicNumberItersPerTile: - rv.args.appendCustomType("MagicNumberItersPerTile", magicNumberItersPerTile, arg.type); + rv.args.template append("MagicNumberItersPerTile", skMagicNumberItersPerTile); break; case CustomArgSemantic::MagicShiftItersPerTile: - rv.args.appendCustomType("MagicShiftItersPerTile", magicShiftItersPerTile, arg.type); + rv.args.template append("MagicShiftItersPerTile", skMagicShiftItersPerTile); break; case CustomArgSemantic::TotalIters: - rv.args.appendCustomType("TotalIters", totalIters, arg.type); - break; - case CustomArgSemantic::SKGrid: - rv.args.appendCustomType("SKGrid", sk.grid, arg.type); - break; - case CustomArgSemantic::SKTilesAndSplit: - if(sk.reduction == origami::reduction_t::parallel) - rv.args.appendCustomType("SKTilesAndSplit", skSplit, arg.type); - else - rv.args.appendCustomType("SKTilesAndSplit", skTiles, arg.type); + rv.args.template append("TotalIters", skTotalIters); break; case CustomArgSemantic::SKItersPerWG: - rv.args.appendCustomType("SKItersPerWG", skItersPerWG, arg.type); + rv.args.template append("SKItersPerWG", skItersPerWG); break; - case CustomArgSemantic::Padding: - rv.args.template append("Padding", 0); - break; - case CustomArgSemantic::DebugPattern: - rv.args.template append("DebugPattern", debugPattern); - ++debugPattern; + case CustomArgSemantic::SKGrid: + rv.args.template append("SKGrid", static_cast(sk.grid)); break; - case CustomArgSemantic::AddressScaleA: - rv.args.template append("AddressScaleA", inputs.mxsa); + case CustomArgSemantic::SKTilesAndSplit: + rv.args.appendCustomType(toString(arg.semantic), skTotalTiles, arg.type); break; - case CustomArgSemantic::AddressScaleB: - rv.args.template append("AddressScaleB", inputs.mxsb); + + // ---- Packed batch dimension divisors ---- + case CustomArgSemantic::MagicNumberSize: + { + uint32_t dimSize = problem.problemSizes()[arg.index]; + uint32_t magicShift; + uint32_t magicNum = magicNumber(sizeMapping.magicDivAlg, dimSize, &magicShift); + rv.args.template append("MagicNumberSize", magicNum); break; - case CustomArgSemantic::StrideScaleA0: + } + case CustomArgSemantic::MagicShiftSize: { - size_t scaleStride = problem.boundSize(0) / problem.mxBlockA(); - rv.args.appendCustomType("StrideScaleA0", scaleStride, arg.type); + uint32_t dimSize = problem.problemSizes()[arg.index]; + uint32_t magicShift; + magicNumber(sizeMapping.magicDivAlg, dimSize, &magicShift); + rv.args.template append("MagicShiftSize", magicShift); break; } - case CustomArgSemantic::StrideScaleA1: + + // ---- Epilogue control args ---- + case CustomArgSemantic::BiasType: + rv.args.template append("BiasType", static_cast(problem.bias().dataType())); + break; + case CustomArgSemantic::StrideBias: { - auto const& t = problem.mxsa(); - size_t batchStride - = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); - rv.args.appendCustomType("StrideScaleA1", batchStride, arg.type); + TensorDescriptor const& bias = problem.tensor(ContractionProblemGemm::TENSOR::BIAS); + uint32_t strideBias = static_cast( + problem.useBias() && bias.dimensions() ? bias.strides()[bias.dimensions() - 1] : 0); + rv.args.template append("StrideBias", strideBias); break; } - case CustomArgSemantic::StrideScaleB0: + case CustomArgSemantic::FactorDim: + rv.args.template append("FactorDim", problem.getParams().factorDim()); + break; + case CustomArgSemantic::ActivationTypeArg: + rv.args.template append("ActivationType", + static_cast(problem.getParams().activationEnum())); + break; + case CustomArgSemantic::ActivationArg: { - size_t scaleStride = problem.boundSize(0) / problem.mxBlockB(); - rv.args.appendCustomType("StrideScaleB0", scaleStride, arg.type); + if(arg.index < inputs.activationArgs.size()) + rv.args.appendCustomType("ActivationArg", inputs.activationArgs[arg.index], arg.type); + else + rv.args.template append("ActivationArg", 0); break; } - case CustomArgSemantic::StrideScaleB1: + case CustomArgSemantic::GSUSync: + rv.args.template append("GSUSync", 0); + break; + + // ---- Random seed args ---- + case CustomArgSemantic::RNDSeed: { - auto const& t = problem.mxsb(); - size_t batchStride - = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); - rv.args.appendCustomType("StrideScaleB1", batchStride, arg.type); + std::random_device rd; + std::mt19937 gen(rd()); + std::uniform_int_distribution distribution(0, 0xFFFFFFFF); + rv.args.template append("RNDSeed", distribution(gen)); break; } + default: throw std::runtime_error(concatenate("Invalid kernel argument type: ", arg)); } @@ -1982,136 +2199,7 @@ namespace TensileLite if(arg.padding > 0) rv.args.appendPadding(arg.padding); } - return rv; - } - - template - KernelInvocation - ContractionSolution::generateSingleCall(ContractionSolution::Problem const& problem, - ContractionInputs const& inputs, - Hardware const& hardware, - StreamKSettings const& sk, - GSUSettings const& gsuSettings) const - { - KernelInvocation rv; - - rv.isSingleCall = true; - - rv.args = KernelArguments(T_Debug); - - rv.args.reserve(1024, 128); - - rv.kernelName = kernelName; - - calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); - - dim3 problemNumGroupTiles = rv.numWorkGroups; - - uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); - uint32_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : autoGsuVal; - if(gsu > 0) - rv.numWorkGroups.y *= gsu; - - if(sizeMapping.streamK != 0) - { - rv.numWorkGroups.x = sk.grid; - rv.numWorkGroups.y = 1; - rv.numWorkGroups.z = 1; - } - - // Use arch from existing hardware to avoid repeated hipGetDeviceProperties - auto removePrefix = [](const std::string& s) { - size_t pos = s.find("gfx"); - if(pos != std::string::npos) - { - return s.substr(pos + 3); - } - return s; - }; - auto gpu_arch_no_prefix = removePrefix(hardware.archName()); - if(internalArgsSupport.version >= 1) - { - rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); - rv.numWorkGroups.y = 1; - rv.numWorkGroups.z = 1; - } - - rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; - rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; - rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; - rv.sharedMemBytes = 0; - - if(internalArgsSupport.useUniversalArgs) - { - auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] - = calculateAutoWGM(problem, &hardware, sk.grid); - auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] - = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); - if(T_Debug) - { - std::cout << "WGM: " << autoWGM << ", WGMXCC: " << autoWGMXCC - << ", WGMXCCCHUNK: " << autoWGMXCCCHUNK << std::endl; - std::cout << "StaggerUMapping: " << autoStaggerUMapping - << ", StaggerU: " << autoStaggerU - << ", StaggerUStrideShift: " << autoStaggerUStrideShift << std::endl; - } - if(problem.batchMode() == ContractionProblemGemm::BATCHMODE::POINTER_ARRAY) - { - kernelArgs( 1, - 3, - rv.args, - getNumWorkGroups(rv), - &hardware, - problem.getParams(), - autoWGM, - autoWGMXCC, - autoWGMXCCCHUNK, - autoStaggerUMapping, - autoStaggerU, - autoStaggerUStrideShift, - autoGsuVal); - } - else - { - kernelArgs( 1, - 0, - rv.args, - getNumWorkGroups(rv), - &hardware, - problem.getParams(), - autoWGM, - autoWGMXCC, - autoWGMXCCCHUNK, - autoStaggerUMapping, - autoStaggerU, - autoStaggerUStrideShift, - autoGsuVal); - } - } - singleCallArgs( - problem, inputs, 0, &hardware, problemNumGroupTiles, rv.numWorkGroups, rv.args, sk); - - if(gsuSettings.globalAccumulation == 3 || sizeMapping.adaptiveGemmGSUA == 1) // MBSK or MB with AdaptiveGemmGSUA - { - rv.args.append("dstD", inputs.d); - // MBSK: synchronizer address, MB: null address - rv.args.append("Synchronizer", - gsuSettings.globalAccumulation == 3 - ? inputs.Synchronizer - : NULL); - rv.args.append("GSUSync", 0); - } - - if(problemType.stochasticRounding) - { - // generate seed from random generator - std::random_device rd; - std::mt19937 gen(rd()); - std::uniform_int_distribution distribution(0, 0xFFFFFFFF); - uint32_t seed = distribution(gen); - rv.args.append("RNDSeed", seed); - } rv.codeObjectFile = codeObjectFilename.load(); return rv; } @@ -2522,7 +2610,7 @@ namespace TensileLite KA& args, StreamKSettings const& sk, uint32_t autoGsuVal, - uint32_t additionalPaddingPerBatchGeneralBatch) const + uint32_t additionalPaddingPerBatchGeneralBatch) const { TensorDescriptor const& c = problem.c(); TensorDescriptor const& d = problem.d(); @@ -2691,13 +2779,13 @@ namespace TensileLite { args.template append("factorDim", (uint32_t)problem.getParams().factorDim()); } - // Adding the batchmode kernel argument for post GSU kernel to determine + // Adding the batchmode kernel argument for post GSU kernel to determine // how to index the batch dimension in Strided Batch versus General Batched. if(problemType.groupedGemm == false) { ContractionProblemGemm::BATCHMODE batchMode = problem.batchMode(); args.template append("batchMode", static_cast(batchMode)); - args.template append("additionalPaddingPerBatch", additionalPaddingPerBatchGeneralBatch); + args.template append("additionalPaddingPerBatch", additionalPaddingPerBatchGeneralBatch); } } @@ -3420,22 +3508,10 @@ namespace TensileLite GSUSettings gsuSettings; gsuSettings.globalAccumulation = problem.getAccumulation(hardware, sizeMapping, gsu); - if(customKernel.name.empty()) - { - // Regular generated kernel - if(debug) - rv.push_back(generateSingleCall(problem, inputs, hardware, sk, gsuSettings)); - else - rv.push_back(generateSingleCall(problem, inputs, hardware, sk, gsuSettings)); - } + if(debug) + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); else - { - // Custom kernel - if(debug) - rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); - else - rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); - } + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); if((gsu > 1 && gsuSettings.globalAccumulation && gsuSettings.globalAccumulation != 3) || sk.reduction == origami::reduction_t::parallel) @@ -3991,12 +4067,7 @@ namespace TensileLite AMDGPU const* pAMDGPU = dynamic_cast(&hardware); assert(pAMDGPU != nullptr && pAMDGPU->computeUnitCount != 0); - if(!customKernel.name.empty()) - { - // Custom kernel currently only supports single-kernel reduction - reductionStrat = origami::reduction_t::tree; - } - else if(pAMDGPU->skDynamicGrid > 0) + if(pAMDGPU->skDynamicGrid > 0) { size_t x = 1; size_t y = 1; From 05404a69515463fe8de29249f08153dc7872f97f Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Wed, 29 Apr 2026 23:49:42 -0700 Subject: [PATCH 29/58] [hipblaslt] Versioning info in custom kernel metadata (#5539) Make a standard way of including versioning and build instructions for a kernel in the metadata so we can recreate kernels, or identify ones that need to be replaced as new features are developed. There was no content hash, no source version, no build parameter recording, and no feature-flag tracking. The kernel name was the sole identity. If the underlying assembly changes, nothing detects it. Metadata is now embedded directly inside each assembly file's .amdgpu_metadata YAML section as a custom.config block. This keeps provenance and build instructions co-located with the kernel they describe. **External kernels** (aiter, ck, rocroller, wave) carry a full `custom.config` with source provenance. This enables them to participate alongside Tensile kernels through the unified `CustomKernels:` list path. **Tensile-generated kernels** already embed `custom.config` with `InternalSupportParams` and (for newer kernels) full `ProblemType` and tuning parameters. Their metadata is inferred from naming conventions at runtime. When you add a new custom kernel, run ``` python -m Tensile.AddCustomConfig --yaml ``` To validate all kernels have metadata: ``` python -m Tensile.ValidateMetadata --strict ``` There are three ways to enable validation: - `--debug` flag - Explicit flag: `--global-parameters ValidateMetadata=True` - add `ValidateManifests: True` under GlobalParameters in YAML If `custom.config` is missing: - Build of tensilelite / hipblaslt: No effect. The file sits there unused. - Tensile benchmark with `CustomKernels: ["my_new_kernel"]`: The kernel gets a visible warning and is skipped. Other kernels in the list still run. No crash. - `python -m Tensile.ValidateMetadata --strict`: Reports the kernel as an error. This is the CI gate. - `ValidateMetadata: True` in the YAML: Warnings are now visible at default verbosity. AIGECORE-211 --- .../tensilelite/Tensile/AddCustomConfig.py | 435 ++++++++++++++++++ .../tensilelite/Tensile/BenchmarkProblems.py | 30 +- .../Tensile/Common/GlobalParameters.py | 1 + .../tensilelite/Tensile/Common/Utilities.py | 24 + .../tensilelite/Tensile/CustomKernels.py | 256 +++++++++-- .../Tensile/CustomKernels/README.md | 135 +++++- .../_ZN5aiter24bf16gemm_bf16_tn_256x256E.s | 52 +++ ...emm_bf16_per1x32Fp4_BpreShuffle_256x256E.s | 62 +++ ..._gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s | 51 ++ ...leSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s | 48 ++ ...k_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s | 72 +++ .../wave/wave_bf16_gemm_256x256x64.s | 42 ++ .../tensilelite/Tensile/LibraryIO.py | 15 +- .../Tensile/SolutionStructs/Solution.py | 18 +- .../hipblaslt/tensilelite/Tensile/Tensile.py | 5 + .../TensileLogic/HandleCustomKernel.py | 8 +- .../Tests/custom/custom_aiter_bf16.yaml | 7 +- .../Tensile/Tests/custom/custom_aiter_f4.yaml | 5 +- .../Tensile/Tests/custom/custom_ck.yaml | 21 +- .../Tensile/Tests/custom/custom_rr.yaml | 27 +- .../Tests/custom/custom_tensile_sk.yaml | 11 +- .../Tests/custom/custom_wave_bf16.yaml | 5 +- .../Tests/unit/test_CustomKernelMetadata.py | 192 ++++++++ .../tensilelite/Tensile/Toolchain/Assembly.py | 40 +- .../tensilelite/Tensile/ValidateMetadata.py | 112 +++++ .../include/Tensile/ContractionSolution.hpp | 1 + 26 files changed, 1543 insertions(+), 132 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py create mode 100644 projects/hipblaslt/tensilelite/Tensile/ValidateMetadata.py diff --git a/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py b/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py new file mode 100644 index 000000000000..7569f3dfe3f9 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py @@ -0,0 +1,435 @@ +################################################################################ +# +# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +################################################################################ + +"""Adds a custom.config block to an external custom kernel .s file. + +External kernels (non-Tensile) need a custom.config section in their +.amdgpu_metadata YAML to carry source/version/feature metadata AND the +Tensile interface (args, macrotile, threads, grid, ProblemType, etc.). + +The config is extracted directly from a Tensile test YAML that already +has the kernel's ForkParameters (CustomKernel, MatrixInstruction, etc.). + +Auto-detected from the .s file (override with CLI flags): + - origin: parent directory name + - wavefront-size: .wavefront_size from amdhsa.kernels metadata + - threads: .reqd_workgroup_size from amdhsa.kernels metadata + +Usage: + python -m Tensile.AddCustomConfig --yaml + +Examples: + # Extract config from test YAML and inject into .s file + python -m Tensile.AddCustomConfig CustomKernels/aiter/kernel.s \\ + --yaml Tests/custom/custom_aiter_bf16.yaml + + # Provenance-only (no --yaml -- kernel won't be usable + # through CustomKernels: list path until interface is added) + python -m Tensile.AddCustomConfig CustomKernels/aiter/kernel.s + + # Preview without modifying the file + python -m Tensile.AddCustomConfig kernel.s --yaml test.yaml --dry-run +""" + +import argparse +import os +import sys + +from Tensile.Common.Utilities import deriveWaveParams + + +FEATURE_FLAGS = [ + "SupportsUserArgs", + "SupportsBias", + "SupportsActivation", + "SupportsScaleAlpha", + "SupportsGSU", +] + + +def _parse_tensile_yaml(path, kernel_name=None): + """Extract ProblemType, CustomKernel, and MatrixInstruction from a Tensile test YAML. + + Args: + path: Path to the Tensile test YAML file. + kernel_name: If provided, match this kernel name in the ForkParameters. + If None, use the first CustomKernel found. + + Returns: + dict with ProblemType, CustomKernel, MatrixInstruction, WavefrontSize (if found). + """ + import yaml + with open(path) as f: + try: + data = yaml.safe_load(f) + except yaml.YAMLError as e: + raise RuntimeError(f"Failed to parse Tensile YAML '{path}': {e}") from e + + try: + bp = data["BenchmarkProblems"][0] + problem_type = bp[0] + bench = bp[1] + except (KeyError, IndexError, TypeError) as e: + raise RuntimeError( + f"Tensile YAML '{path}' does not contain BenchmarkProblems[0] " + "with ProblemType and ForkParameters" + ) from e + + config = {"ProblemType": problem_type} + + fork_params = bench.get("ForkParameters", []) + available_kernels = [] + for entry in fork_params: + if not isinstance(entry, dict): + continue + + if "CustomKernel" in entry: + for ck in entry["CustomKernel"]: + if not isinstance(ck, dict) or "name" not in ck: + continue + available_kernels.append(ck["name"]) + if kernel_name and ck["name"] != kernel_name: + continue + config["CustomKernel"] = { + k: v for k, v in ck.items() if k != "name" + } + break + + if "MatrixInstruction" in entry: + mi_list = entry["MatrixInstruction"] + if mi_list and isinstance(mi_list[0], list): + config["MatrixInstruction"] = mi_list[0][:4] + + if "WavefrontSize" in entry: + wf_list = entry["WavefrontSize"] + if wf_list: + config["WavefrontSize"] = wf_list[0] + + if kernel_name and "CustomKernel" not in config: + raise RuntimeError( + f"Kernel '{kernel_name}' not found in {path}. " + f"Available: {available_kernels or 'none'}" + ) + + if "CustomKernel" not in config: + raise RuntimeError(f"No CustomKernel entry found in {path}") + + return config + + +def _fmt_yaml_scalar(value): + """Format a scalar for the compact YAML style used in custom.config.""" + if isinstance(value, bool): + return str(value).lower() + if value is None: + return "null" + return str(value) + + +def _fmt_yaml_inline(value): + """Format simple YAML values inline without quoting strings.""" + if isinstance(value, list): + return "[" + ", ".join(_fmt_yaml_inline(v) for v in value) + "]" + if isinstance(value, dict): + pairs = ", ".join( + f"{k}: {_fmt_yaml_inline(v)}" for k, v in value.items() + ) + return "{ " + pairs + " }" + return _fmt_yaml_scalar(value) + + +def _fmt_yaml_args(args, indent=4): + """Format an args list as multi-line YAML flow mappings. + + Produces output like: + args: [ { type: address, semantic: AddressD, padding: 8 }, + { type: address, semantic: AddressA, padding: 8 } ] + """ + if not args: + return "args: []" + prefix = " " * indent + "args: " + continuation = " " * len(prefix) + formatted = [] + for arg in args: + pairs = ", ".join( + f"{k}: {_fmt_yaml_inline(v)}" for k, v in arg.items() + ) + formatted.append("{ " + pairs + " }") + if len(formatted) == 1: + return prefix + "[ " + formatted[0] + " ]" + first = prefix + "[ " + formatted[0] + "," + middle = [continuation + " " + f + "," for f in formatted[1:-1]] + last = continuation + " " + formatted[-1] + " ]" + return "\n".join([first] + middle + [last]) + + +def build_custom_config_yaml(origin, config, repository=None, version="1.0.0"): + """Builds the custom.config YAML block string. + + Args: + origin: Source origin name (e.g. "aiter", "wave"). + config: Dict with ProblemType, CustomKernel, MatrixInstruction, etc. + May be None for provenance-only injection. Treated as read-only. + repository: Optional source repository URL. + version: Kernel version string. + """ + # Take local copies so we never mutate caller-supplied dicts. + features = dict((config or {}).get("Features", {})) + for flag in FEATURE_FLAGS: + features.setdefault(flag, False) + + isp = dict((config or {}).get("InternalSupportParams", {})) + isp.setdefault("KernArgsVersion", 0) + + wavefront_size = (config or {}).get("WavefrontSize", 64) + + lines = ["custom.config:"] + lines.append(" Source:") + lines.append(f" Origin: {origin}") + if repository: + lines.append(f" Repository: {repository}") + lines.append(f" Version: {version}") + lines.append(" Features:") + for flag in FEATURE_FLAGS: + lines.append(f" {flag}: {str(features[flag]).lower()}") + + lines.append(" InternalSupportParams:") + for k, v in isp.items(): + lines.append(f" {k}: {v}") + + if config and "ProblemType" in config: + lines.append(" ProblemType:") + for k, v in config["ProblemType"].items(): + lines.append(f" {k}: {v}") + + if config and "CustomKernel" in config: + ck = config["CustomKernel"] + lines.append(" CustomKernel:") + for key, value in ck.items(): + if key == "args": + lines.append(_fmt_yaml_args(value)) + else: + lines.append(f" {key}: {_fmt_yaml_inline(value)}") + + if config and "MatrixInstruction" in config: + mi = config["MatrixInstruction"] + lines.append(f" MatrixInstruction: {_fmt_yaml_inline(mi)}") + + macrotile = config.get("CustomKernel", {}).get("macrotile") + threads = config.get("CustomKernel", {}).get("threads") + if len(mi) >= 4 and macrotile and threads: + lines.append(" EnableMatrixInstruction: True") + num_threads = threads[0] * threads[1] * threads[2] + _, mi_wave_tile = deriveWaveParams(mi, num_threads, macrotile, wavefront_size) + lines.append(f" MIWaveTile: {_fmt_yaml_inline(mi_wave_tile)}") + + lines.append(f" WavefrontSize: {wavefront_size}") + + return "\n".join(lines) + + +def _read_asm_file(filepath): + """Reads an .s file once, returning all info needed by the pipeline. + + Returns a dict with: + lines: list of raw line strings (with newlines) + has_custom_config: bool + insert_idx: line index after '---' in .amdgpu_metadata (or None) + origin: parent directory name + detected: dict with auto-detected threads and wavefront_size + """ + import yaml + + with open(filepath, "r") as f: + lines = f.readlines() + + result = { + "lines": lines, + "has_custom_config": False, + "insert_idx": None, + "origin": os.path.basename(os.path.dirname(os.path.abspath(filepath))), + "detected": {}, + } + + in_metadata = False + in_yaml = False + yaml_lines = [] + + for i, line in enumerate(lines): + stripped = line.strip() + if stripped == ".amdgpu_metadata": + in_metadata = True + continue + if in_metadata and stripped == "---": + in_yaml = True + result["insert_idx"] = i + 1 + continue + if in_metadata and stripped == "...": + break + if in_metadata and stripped.startswith("custom.config"): + result["has_custom_config"] = True + if in_yaml: + yaml_lines.append(line) + + if not yaml_lines: + return result + + try: + metadata = yaml.safe_load("\n".join(yaml_lines)) + except yaml.YAMLError as e: + raise RuntimeError(f"Failed to parse .amdgpu_metadata YAML in {filepath}: {e}") from e + + if not metadata: + return result + + kernels = metadata.get("amdhsa.kernels", []) + if kernels: + k = kernels[0] + wgs = k.get(".reqd_workgroup_size") + if wgs and isinstance(wgs, list): + result["detected"]["threads"] = wgs + wf = k.get(".wavefront_size") + if wf: + result["detected"]["wavefront_size"] = int(wf) + + return result + + +def inject_custom_config(file_info, filepath, config_yaml, dry_run=False): + """Injects the custom.config block using pre-read file data.""" + insert_idx = file_info["insert_idx"] + + if insert_idx is None: + print("ERROR: No .amdgpu_metadata / --- section found in the file.", + file=sys.stderr) + print("The file must have an .amdgpu_metadata section to inject into.", + file=sys.stderr) + return False + + config_lines = [l + "\n" for l in config_yaml.split("\n")] + + if dry_run: + print("--- custom.config block that would be inserted ---") + print(config_yaml) + print(f"--- at line {insert_idx + 1} of {filepath} ---") + return True + + lines = file_info["lines"] + new_lines = lines[:insert_idx] + config_lines + lines[insert_idx:] + + with open(filepath, "w") as f: + f.writelines(new_lines) + + print(f"Injected custom.config into {filepath} at line {insert_idx + 1}") + return True + + +def main(): + parser = argparse.ArgumentParser( + description="Add custom.config metadata to an external custom kernel .s file", + epilog="Auto-detected from the .s file: origin (parent directory), " + "wavefront-size, threads (.reqd_workgroup_size). " + "Override any auto-detected value with CLI flags." + ) + parser.add_argument("file", help="Path to the .s assembly file") + parser.add_argument("--yaml", default=None, + help="Tensile test YAML with ForkParameters " + "(ProblemType, CustomKernel, MatrixInstruction extracted automatically)") + parser.add_argument("--origin", default=None, + help="Source origin name (default: auto-detect from parent directory)") + parser.add_argument("--repository", default=None, + help="Source repository URL") + parser.add_argument("--version", default="1.0.0", + help="Kernel version (default: 1.0.0)") + parser.add_argument("--dry-run", action="store_true", + help="Show what would be injected without modifying the file") + + args = parser.parse_args() + + filepath = os.path.abspath(args.file) + if not os.path.isfile(filepath): + print(f"ERROR: File not found: {filepath}", file=sys.stderr) + sys.exit(1) + + if not filepath.endswith(".s"): + print(f"WARNING: {filepath} does not end with .s", file=sys.stderr) + + try: + file_info = _read_asm_file(filepath) + except RuntimeError as e: + print(f"ERROR: {e}", file=sys.stderr) + sys.exit(1) + + if file_info["has_custom_config"]: + print(f"ERROR: {filepath} already has a custom.config block.", file=sys.stderr) + print("Remove the existing block first if you want to regenerate it.", + file=sys.stderr) + sys.exit(1) + + detected = file_info["detected"] + origin = args.origin or file_info["origin"] + if not origin: + print("ERROR: Could not detect origin. Pass --origin explicitly.", file=sys.stderr) + sys.exit(1) + + config = None + if args.yaml: + kernel_name = os.path.basename(filepath)[:-2] + try: + config = _parse_tensile_yaml(args.yaml, kernel_name) + except RuntimeError as e: + print(f"ERROR: {e}", file=sys.stderr) + sys.exit(1) + + if config: + ck = config.get("CustomKernel", {}) + if "threads" not in ck and "threads" in detected: + ck["threads"] = detected["threads"] + config["CustomKernel"] = ck + if "WavefrontSize" not in config and "wavefront_size" in detected: + config["WavefrontSize"] = detected["wavefront_size"] + + auto_info = [] + if not args.origin and file_info["origin"]: + auto_info.append(f"origin={file_info['origin']}") + if "wavefront_size" in detected: + auto_info.append(f"wavefront_size={detected['wavefront_size']}") + if "threads" in detected: + auto_info.append(f"threads={detected['threads']}") + if auto_info: + print(f"Auto-detected: {', '.join(auto_info)}") + + config_yaml = build_custom_config_yaml( + origin=origin, + config=config, + repository=args.repository, + version=args.version, + ) + + if not inject_custom_config(file_info, filepath, config_yaml, dry_run=args.dry_run): + sys.exit(1) + + +if __name__ == "__main__": + main() diff --git a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py index 670c680bdc35..af5e5a384b00 100644 --- a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py +++ b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py @@ -161,6 +161,24 @@ def _getCustomKernelSolutionObj( return sol +def _hashableProblemTypeKV(k, v): + """Make (k, v) hashable for set-difference comparisons of ProblemType. + + Lists become tuples; otherwise we fall back to repr(v) for unhashable + nested values (e.g. dict-valued problem-type fields). Note: repr is + insertion-order-sensitive for dicts, so equivalent dicts with different + insertion orders compare as different. Acceptable for the diagnostic + "differing parameters" message produced below. + """ + if isinstance(v, list): + return (k, tuple(v)) + try: + hash(v) + return (k, v) + except TypeError: + return (k, repr(v)) + + def _generateCustomKernelSolutions( problemType, customKernels, @@ -174,17 +192,19 @@ def _generateCustomKernelSolutions( solutions = [] for kernelName in customKernels: print1("# Processing custom kernel {}".format(kernelName)) - solution = _getCustomKernelSolutionObj(kernelName, internalSupportParams, assembler, debugConfig, isaInfoMap) + try: + solution = _getCustomKernelSolutionObj(kernelName, internalSupportParams, assembler, debugConfig, isaInfoMap) + except (RuntimeError, KeyError, TypeError) as e: + printWarning(f"Skipping custom kernel '{kernelName}': missing or invalid custom.config ({e})") + continue # The ActivationType setting in YAML is meaningless in customKernel case. # Therefore, we override the customKernel setting with the ActivationType value from ProblemType to avoid false alarms during subsequent problemType checks. solution["ProblemType"]["ActivationType"] = problemType["ActivationType"] if solution["ProblemType"] != problemType: # Raise error if this kernel was specifically requested and problem type doesn't match if failOnMismatch: - benchmarkSet = set([(k,tuple(v)) if type(v) is list else (k,v) \ - for k,v in problemType.items()]) - customSet = set([(k,tuple(v)) if type(v) is list else (k,v) \ - for k,v in solution["ProblemType"].items()]) + benchmarkSet = {_hashableProblemTypeKV(k, v) for k, v in problemType.items()} + customSet = {_hashableProblemTypeKV(k, v) for k, v in solution["ProblemType"].items()} msg = "The problem type in the config file does not match " \ "that of the custom kernel, {}.".format(kernelName) \ diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py index 41a6798dc168..9b5b3ac6ee45 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/GlobalParameters.py @@ -301,6 +301,7 @@ globalParameters["AsmDebug"] = ( False # Set to True to keep debug information for compiled code objects ) +globalParameters["ValidateMetadata"] = False # Set to True to validate custom.config metadata at build time globalParameters["UseEffLike"] = True # Set to False to use winnerGFlops as the performance metric diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/Utilities.py b/projects/hipblaslt/tensilelite/Tensile/Common/Utilities.py index 685ce17c5e58..d794875db2eb 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/Utilities.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/Utilities.py @@ -395,6 +395,30 @@ def choose_multiplier(d, N, p): shPost -=1 return mhigh, shPost, l +def deriveWaveParams(mi, num_threads, macrotile, wavefront_size=64): + """Derives MIWaveGroup and MIWaveTile from matrix-instruction geometry. + + Args: + mi: MatrixInstruction list, at least [miM, miN, ...]. + num_threads: Total thread count (product of workgroup dimensions). + macrotile: [MT0, MT1] or [MT0, MT1, depthU]. + wavefront_size: Wavefront width (default 64). + + Returns: + (wave_group, wave_tile) where each is a two-element list [M, N]. + """ + num_waves = max(1, num_threads // wavefront_size) + wgM = math.isqrt(num_waves) + while wgM > 0 and num_waves % wgM != 0: + wgM -= 1 + wgM = max(1, wgM) + wgN = num_waves // wgM + wave_group = [wgM, wgN] + wave_tile = [max(1, macrotile[0] // (mi[0] * wgM)), + max(1, macrotile[1] // (mi[1] * wgN))] + return wave_group, wave_tile + + def wmmaV3InputVgprLayout(wmma: Sequence[int], dtypeBitWidth: Optional[int] = None) -> Tuple[int]: # wmmaV3InputVgprLayout: (numReadsUnroll, numVecTile, numVecUnroll, NumElementPerRead) wmma = tuple(wmma) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index e9cb68dabbac..090421418d73 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -85,6 +85,19 @@ "activationDelta": 3, } +# Top-level custom.config keys that are not in validParameters but must survive +# the parameter-validation/strip pass in getCustomKernelConfig. +# +# These two are consumed structurally by Tensile (ProblemType drives the +# solution; InternalSupportParams threads through to the kernel writer) and +# would otherwise be popped because they're not tunable parameters. +# +# Provenance-only keys (Source, Version, Features) are deliberately NOT in this +# set: getCustomKernelConfig drops them so they don't pollute the solution +# dict, while validateCustomKernelMetadata still sees them via its independent +# readCustomKernelConfig call. +_PASSTHROUGH_KEYS = {"ProblemType", "InternalSupportParams"} + def isCustomKernelConfig(config): if "CustomKernel" in config and config["CustomKernel"]["name"]: if config["CustomKernel"].get("generated", False): @@ -96,59 +109,76 @@ def getCustomKernelFilepath(name, directory=CUSTOM_KERNEL_PATH): flat = os.path.join(directory, (name + ".s")) if os.path.isfile(flat): return flat - for root, _, files in os.walk(directory): - if (name + ".s") in files: - return os.path.join(root, (name + ".s")) + for path in iterCustomKernelFiles(directory): + if os.path.basename(path) == (name + ".s"): + return path return flat -def getAllCustomKernelNames(directory=CUSTOM_KERNEL_PATH): - names = [] - for root, _, files in os.walk(directory): - for fname in files: +def iterCustomKernelFiles(directory=CUSTOM_KERNEL_PATH): + """Yield custom kernel assembly files using the same recursive discovery as the loader.""" + for root, dirs, files in os.walk(directory): + dirs.sort() + for fname in sorted(files): if fname.endswith(".s"): - names.append(fname[:-2]) - return names + yield os.path.join(root, fname) + +def getAllCustomKernelNames(directory=CUSTOM_KERNEL_PATH): + return [os.path.basename(path)[:-2] for path in iterCustomKernelFiles(directory)] def getCustomKernelContents(name, directory=CUSTOM_KERNEL_PATH): try: with open(getCustomKernelFilepath(name, directory)) as f: return f.read() - except: - raise RuntimeError("Failed to find custom kernel: {}".format(os.path.join(directory, name))) - -def getCustomKernelConfigAndAssembly(name, directory=CUSTOM_KERNEL_PATH): - contents = getCustomKernelContents(name, directory) - config = "\n" #Yaml configuration properties - assembly = "" - inConfig = False - for line in contents.splitlines(): - if line == "---": inConfig = True #Beginning of yaml section - elif line == "...": inConfig = False #End of yaml section - elif inConfig: config += line + "\n" - else : assembly += line + "\n"; config += "\n" #Second statement to keep line numbers consistent for yaml errors + except OSError as e: + raise RuntimeError("Failed to find custom kernel: {}".format(os.path.join(directory, name))) from e - return (config, assembly) +def _readEmbeddedYaml(name, directory=CUSTOM_KERNEL_PATH): + """Parse the YAML payload between '---' and '...' inside .amdgpu_metadata. -def readCustomKernelConfig(name, directory=CUSTOM_KERNEL_PATH): - rawConfig, _ = getCustomKernelConfigAndAssembly(name, directory) - try: - return yaml.safe_load(rawConfig)["custom.config"] - except yaml.scanner.ScannerError as e: - raise RuntimeError("Failed to read configuration for custom kernel: {0}\nDetails:\n{1}".format(name, e)) - -def _readFullYaml(name, directory=CUSTOM_KERNEL_PATH): - """Read and return the full parsed YAML (all sections) from a custom kernel .s file.""" - rawConfig, _ = getCustomKernelConfigAndAssembly(name, directory) + The .s files emitted under this branch contain exactly one such block; + we stop at the first '...' and return whatever yaml.safe_load returns + (typically a mapping with 'custom.config' and 'amdhsa.kernels' keys). + """ + contents = getCustomKernelContents(name, directory) + inYaml = False + yamlLines = [] + for line in contents.splitlines(): + if line == "---": + inYaml = True + continue + if line == "..." and inYaml: + break + if inYaml: + yamlLines.append(line) try: - return yaml.safe_load(rawConfig) - except yaml.scanner.ScannerError as e: - raise RuntimeError("Failed to read YAML for custom kernel: {0}\nDetails:\n{1}".format(name, e)) + return yaml.safe_load("\n".join(yamlLines)) + except yaml.YAMLError as e: + raise RuntimeError(f"Failed to parse YAML for custom kernel '{name}': {e}") from e -def _metadataArgToCustomArg(metaArg): - """Convert a single amdgpu_metadata .args entry to a CustomKernel arg dict.""" - name = metaArg[".name"] - size = metaArg[".size"] - valueKind = metaArg[".value_kind"] +def readCustomKernelConfig(name, directory=CUSTOM_KERNEL_PATH): + parsed = _readEmbeddedYaml(name, directory) + if not isinstance(parsed, dict) or "custom.config" not in parsed: + raise RuntimeError(f"Custom kernel '{name}' has no custom.config in its .amdgpu_metadata") + config = parsed["custom.config"] + if not isinstance(config, dict): + raise RuntimeError(f"Custom kernel '{name}' custom.config must be a YAML mapping") + return config + +def _metadataArgToCustomArg(metaArg, kernelName=None): + """Convert a single amdgpu_metadata .args entry to a CustomKernel arg dict. + + Raises RuntimeError with an actionable message if the arg name is not + recognized (which can only happen when auto-inferring a CustomKernel + block for a kernel that does not declare one explicitly). + """ + name = metaArg.get(".name") + size = metaArg.get(".size") + valueKind = metaArg.get(".value_kind") + if name is None or size is None or valueKind is None: + raise RuntimeError( + f"amdgpu_metadata arg entry missing required field " + f"(.name/.size/.value_kind): {metaArg}" + ) if valueKind == "global_buffer": argType = "address" @@ -195,7 +225,13 @@ def _metadataArgToCustomArg(metaArg): idx = INDEX_CHARS.index(m.group(2)) return {"type": argType, "semantic": m.group(1), "index": idx} - raise RuntimeError("Unknown metadata arg name: '%s'" % name) + where = f" in kernel '{kernelName}'" if kernelName else "" + raise RuntimeError( + f"Unknown amdgpu_metadata arg name '{name}'{where} while auto-inferring " + f"a CustomKernel block. Either add an explicit CustomKernel: section " + f"to custom.config, or extend _METADATA_NAME_TO_SEMANTIC in " + f"Tensile/CustomKernels.py." + ) _HEADER_SEMANTIC_ORDER = { "GemmInfo": 0, "InternalArgs": 1, "InternalArgs1": 2, "NumWorkGroups": 3, @@ -203,9 +239,24 @@ def _metadataArgToCustomArg(metaArg): def _buildCustomKernelFromMetadata(kernelName, fullYaml, kernelConfig): """Build a CustomKernel dict from the amdgpu_metadata and custom.config sections.""" - kernelMeta = fullYaml["amdhsa.kernels"][0] - - args = [_metadataArgToCustomArg(a) for a in kernelMeta[".args"]] + if not isinstance(fullYaml, dict): + raise RuntimeError(f"Custom kernel '{kernelName}' has no parseable .amdgpu_metadata YAML") + kernels = fullYaml.get("amdhsa.kernels") or [] + if not kernels: + raise RuntimeError( + f"Custom kernel '{kernelName}' has no amdhsa.kernels entries; cannot " + f"auto-infer a CustomKernel block. Add an explicit CustomKernel: " + f"section to custom.config." + ) + kernelMeta = kernels[0] + if ".args" not in kernelMeta: + raise RuntimeError( + f"Custom kernel '{kernelName}' amdhsa.kernels[0] has no .args; cannot " + f"auto-infer a CustomKernel block. Add an explicit CustomKernel: " + f"section to custom.config." + ) + + args = [_metadataArgToCustomArg(a, kernelName) for a in kernelMeta[".args"]] # UseUniversalArgs kernels expect a header (GemmInfo, InternalArgs, ...) at # the start of the kernel argument buffer, followed by the data args. The @@ -291,16 +342,25 @@ def getCustomKernelConfig( if key not in kernelIsp: kernelIsp[key] = internalSupportParams[key] - validParameters.update(newMIValidParameters) + # Compute a merged validParameters set locally; do NOT mutate the global + # validParameters dict (that leaks state across calls and into unit tests + # via the precomputed _expectedParamTypes cache in test_validateParameterTypes). + mergedValid = {**validParameters, **newMIValidParameters} for k, v in kernelConfig.items(): - if k != "ProblemType": - checkParametersAreValid((k, [v]), validParameters) + if k in _PASSTHROUGH_KEYS: + continue + if k in mergedValid: + checkParametersAreValid((k, [v]), mergedValid) + + metadata_keys = [k for k in kernelConfig if k not in mergedValid and k not in _PASSTHROUGH_KEYS] + for k in metadata_keys: + kernelConfig.pop(k) kernelConfig["KernelLanguage"] = "Assembly" if "CustomKernel" not in kernelConfig: - fullYaml = _readFullYaml(kernelName, directory) + fullYaml = _readEmbeddedYaml(kernelName, directory) kernelConfig["CustomKernel"] = _buildCustomKernelFromMetadata(kernelName, fullYaml, kernelConfig) kernelConfig["CustomKernel"]["name"] = kernelName @@ -310,3 +370,101 @@ def getCustomKernelConfig( kernelConfig["CustomKernelName"] = kernelName return kernelConfig + + +################################################################################ +# Embedded metadata validation functions +################################################################################ + +_EXTERNAL_HINT = ( + "External kernels carry their full Tensile-side interface in custom.config. " + "To inject one from a Tensile test YAML, run:\n" + " python -m Tensile.AddCustomConfig --yaml \n" +) + +_TENSILE_HINT = ( + "Tensile-generated kernels only need InternalSupportParams.KernArgsVersion in " + "custom.config; ProblemType and tuning state come from the consuming logic file " + "or test YAML. If the field is missing, regenerate the kernel with the current " + "kernel writer." +) + +def _requiredFieldsMissing(config, fields): + return [field for field in fields if field not in config] + +def _missingMetadataMessage(kind, name, filepath, missing): + hint = _EXTERNAL_HINT if kind == "External" else _TENSILE_HINT + return ( + f"{kind} kernel '{name}' has custom.config but is missing required fields:\n" + f" Missing: {', '.join(missing)}\n" + f" File: {filepath}\n" + f"{hint}" + ) + +def validateCustomKernelMetadata(name, directory=CUSTOM_KERNEL_PATH): + """Validates that a kernel has an embedded custom.config with required fields. + + Tensile-generated kernels (no Source.Origin) only need + InternalSupportParams.KernArgsVersion -- the only field + `getCustomKernelConfig` actually requires at runtime. Their ProblemType and + tuning state live in the consuming logic file or test YAML and are merged + on top of custom.config there. + + External kernels (Source.Origin present) carry their full Tensile-side + interface and provenance in custom.config: Source, Features, Version, + InternalSupportParams.KernArgsVersion, ProblemType, MatrixInstruction, and + a CustomKernel block with args/macrotile/threads/grid. + + Whether failures are reported as errors or warnings is the caller's + decision (see ValidateMetadata.validate_all and + Toolchain.Assembly.validateCustomKernelMetadataAtBuild). + + Returns: + (bool, str): A tuple of (is_valid, message). + """ + filepath = getCustomKernelFilepath(name, directory) + + try: + config = readCustomKernelConfig(name, directory) + except RuntimeError as e: + # Use the external hint here -- a kernel without any custom.config is + # almost always an external kernel that hasn't been migrated yet. + return False, ( + f"Cannot read custom.config for '{name}' ({filepath}): {e}\n" + f"{_EXTERNAL_HINT}" + ) + + is_external = "Source" in config + missing = [] + + if "InternalSupportParams" not in config: + missing.append("InternalSupportParams") + elif not isinstance(config["InternalSupportParams"], dict): + missing.append("InternalSupportParams (mapping)") + elif "KernArgsVersion" not in config["InternalSupportParams"]: + missing.append("InternalSupportParams.KernArgsVersion") + + if is_external: + source = config.get("Source") + if not isinstance(source, dict) or "Origin" not in source: + missing.append("Source.Origin") + if "Features" not in config or not isinstance(config["Features"], dict): + missing.append("Features") + missing.extend(_requiredFieldsMissing( + config, + ["Version", "ProblemType", "CustomKernel", "MatrixInstruction"], + )) + + if "CustomKernel" in config: + custom_kernel = config["CustomKernel"] + if not isinstance(custom_kernel, dict): + missing.append("CustomKernel (mapping)") + else: + ck_missing = _requiredFieldsMissing(custom_kernel, ["args", "macrotile", "threads", "grid"]) + missing.extend(f"CustomKernel.{field}" for field in ck_missing) + + if missing: + kind = "External" if is_external else "Tensile" + return False, _missingMetadataMessage(kind, name, filepath, missing) + + return True, f"Kernel '{name}' metadata is valid" diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md index 18d69d85be73..15b46a4cdb74 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md @@ -1,21 +1,132 @@ -# Custom kernel validation +# Custom kernels -In the context of TensileCreateLibrary, Custom kernel meta data is taken from the logic -file where the custom kernel is referenced. The metadata from the logic file can be -overwritten by specifying the parameters of interest in the `custom.config` section of -the kernel assembly file. The majority of the override parameters are validated at build -time when building a custom kernel with exception of the nine element MatrixInstruction. -While this validation is no longer applied during the build process it can be applied by -using the **TensileLogic** script as follows: +Each custom kernel `.s` file embeds its Tensile-side metadata directly inside +the `.amdgpu_metadata` YAML section, under a top-level `custom.config:` key. +Co-locating provenance and build instructions with the kernel they describe +makes kernels self-describing: the same file can be loaded through a logic +file, a benchmark `CustomKernels:` list, or a CI gate without consulting any +external manifest. +## Subdirectories + +| Directory | Origin | +| ------------- | ------------------------------------------------- | +| `tensile/` | Kernels emitted by Tensile's own assembly writer. | +| `aiter/` | External: AITER-sourced GEMM kernels. | +| `ck/` | External: Composable Kernel-sourced kernels. | +| `rocroller/` | External: rocRoller-sourced kernels. | +| `wave/` | External: Wave (handwritten) kernels. | + +Loader behavior is the same in every subdirectory; the split is purely +organizational. + +## What `custom.config` looks like + +Tensile-generated kernels (no `Source:` block) need only the runtime +requirement: + +```yaml +custom.config: + InternalSupportParams: + KernArgsVersion: 0 ``` -Tensile/bin/TensileLogic --check-only-custom-kernels + +Their `ProblemType`, `MatrixInstruction`, and tuning state come from the +consuming logic file or test YAML and are merged on top of `custom.config` at +load time. Most Tensile-generated kernels also embed those fields for +forensic value, but they are not required. + +External kernels must additionally carry full provenance and the Tensile-side +interface, because Tensile cannot regenerate them and benchmark/test YAMLs +need a stable handle: + +```yaml +custom.config: + Source: + Origin: aiter + Repository: https://github.com/... + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: { ... } + CustomKernel: + args: [ { type: address, semantic: AddressD, padding: 8 }, ... ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + MatrixInstruction: [16, 16, 32, 1] + EnableMatrixInstruction: True + MIWaveTile: [8, 8] + WavefrontSize: 64 +``` + +`Source`, `Version`, and `Features` are presence-checked but otherwise +provenance only — they are read by the validator, not by the runtime. + +## Adding a new external kernel + +The `Tensile.AddCustomConfig` helper extracts the Tensile-side interface from +a benchmark test YAML and injects a `custom.config` block into the `.s` file: + +```bash +python -m Tensile.AddCustomConfig \ + Tensile/CustomKernels/aiter/.s \ + --yaml Tensile/Tests/custom/.yaml ``` -where `` is a path to a logic file containing a solution where -`CustomKernel` references the custom kernel requiring validation. +Useful flags: + +| Flag | Purpose | +| ---------------- | -------------------------------------------------------------------- | +| `--yaml ` | Tensile test YAML to pull `ProblemType` / `CustomKernel` / `MI` from | +| `--origin ` | Override auto-detected origin (defaults to parent directory name) | +| `--repository` | Source repository URL | +| `--version` | Kernel version string (defaults to `1.0.0`) | +| `--dry-run` | Print the block that would be inserted without modifying the file | + +Without `--yaml` the tool injects a provenance-only block; the kernel won't +be usable through the `CustomKernels:` list path until the interface is +filled in by hand. + +The tool refuses to operate on a file that already contains a `custom.config` +block; if you need to regenerate one, delete the existing block first. + +## Validation + +Two ways to validate: + +1. **CI gate** (recommended for pull-request checks): + + ```bash + python -m Tensile.ValidateMetadata --strict + ``` + + Walks the `CustomKernels/` tree, validates every `.s` file, exits non-zero + on any failure. Without `--strict`, failures are reported as warnings only + and the exit code is `0`. + +2. **Build-time** (off by default): + + Set the YAML toggle `GlobalParameters.ValidateMetadata: True` in your + benchmark configuration, or pass `--validate-metadata` to `Tensile`. With + the flag on, `buildAssemblyCodeObjectFiles` validates every kernel that + participates in the build and prints `Tensile::WARNING: ...` for any + missing or invalid `custom.config` while letting the build proceed. + +### Validation rules + +| Kind | Required in `custom.config` | +| -------------------- | -------------------------------------------------------------------------------------------------------------------- | +| Tensile-generated | `InternalSupportParams.KernArgsVersion` | +| External (`Source:`) | All of: `Source.Origin`, `Features` (mapping), `InternalSupportParams.KernArgsVersion`, `Version`, `ProblemType`, `MatrixInstruction`, `CustomKernel` with `args` / `macrotile` / `threads` / `grid` | diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s index 6d7d1ef5ec2b..13dd170b4ca5 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s @@ -2203,6 +2203,58 @@ label_0EFC: // ===== AMDGPU Metadata ===== .amdgpu_metadata --- +custom.config: + Source: + Origin: aiter + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: b + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + CustomKernel: + args: [ { type: address, semantic: AddressD, padding: 8 }, + { type: address, semantic: AddressC, padding: 8 }, + { type: address, semantic: AddressB, padding: 8 }, + { type: address, semantic: AddressA, padding: 8 }, + { type: float32, semantic: Alpha, padding: 12 }, + { type: float32, semantic: Beta, padding: 12 }, + { type: uint32, semantic: StrideD0Bytes, padding: 12 }, + { type: uint32, semantic: StrideD1, padding: 12 }, + { type: uint32, semantic: StrideC0Bytes, padding: 12 }, + { type: uint32, semantic: StrideC1, padding: 12 }, + { type: uint32, semantic: StrideB0Bytes, padding: 12 }, + { type: uint32, semantic: StrideB1, padding: 12 }, + { type: uint32, semantic: StrideA0Bytes, padding: 12 }, + { type: uint32, semantic: StrideA1, padding: 12 }, + { type: uint32, semantic: SizeFree1, padding: 12 }, + { type: uint32, semantic: SizeFree0, padding: 12 }, + { type: uint32, semantic: SizeSum, padding: 12 }, + { type: uint32, semantic: SplitK, padding: 12 }, + { type: uint32, semantic: OutputBF16, padding: 12 } ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + MatrixInstruction: [16, 16, 32, 1] + EnableMatrixInstruction: True + MIWaveTile: [8, 8] + WavefrontSize: 64 amdhsa.kernels: - .args: - .actual_access: read_write diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s index 8ba6f9e65413..f66508f824b2 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s @@ -3444,6 +3444,68 @@ label_19CC: // ===== AMDGPU Metadata ===== .amdgpu_metadata --- +custom.config: + Source: + Origin: aiter + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: F4 + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + SwizzleTensorA: True + SwizzleTensorB: False + MXBlockA: 32 + MXBlockB: 32 + CustomKernel: + args: [ { type: address, semantic: AddressD, padding: 8 }, + { type: address, semantic: AddressC, padding: 8 }, + { type: address, semantic: AddressB, padding: 8 }, + { type: address, semantic: AddressA, padding: 8 }, + { type: float32, semantic: Alpha, padding: 12 }, + { type: float32, semantic: Beta, padding: 12 }, + { type: uint32, semantic: StrideD0, padding: 12 }, + { type: uint32, semantic: StrideD1, padding: 12 }, + { type: uint32, semantic: StrideC0, padding: 12 }, + { type: uint32, semantic: StrideC1, padding: 12 }, + { type: uint32, semantic: StrideB0, padding: 12 }, + { type: uint32, semantic: StrideB1, padding: 12 }, + { type: uint32, semantic: StrideA0, padding: 12 }, + { type: uint32, semantic: StrideA1, padding: 12 }, + { type: uint32, semantic: SizeFree1, padding: 12 }, + { type: uint32, semantic: SizeFree0, padding: 12 }, + { type: uint32, semantic: SizeSum, padding: 12 }, + { type: address, semantic: AddressMXScaleB, padding: 8 }, + { type: address, semantic: AddressMXScaleA, padding: 8 }, + { type: uint32, semantic: StrideScaleB0, padding: 12 }, + { type: uint32, semantic: StrideScaleB1, padding: 12 }, + { type: uint32, semantic: StrideScaleA0, padding: 12 }, + { type: uint32, semantic: StrideScaleA1, padding: 12 }, + { type: uint32, semantic: SplitK, padding: 12 } ] + macrotile: [256, 256, 256] + padProblemSizeToTile: [true, true] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + MatrixInstruction: [16, 16, 128, 1] + EnableMatrixInstruction: True + MIWaveTile: [8, 8] + WavefrontSize: 64 amdhsa.kernels: - .args: - .actual_access: read_write diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s index c81b2cc61262..6145ac7a5fae 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s @@ -177370,6 +177370,57 @@ __hip_cuid_189e97bb64f986de: .addrsig_sym __hip_cuid_189e97bb64f986de .amdgpu_metadata --- +custom.config: + Source: + Origin: ck + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + CustomKernel: + args: [ { type: address, semantic: AddressB }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressD }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeSum }, + { type: uint32, semantic: StrideB0 }, + { type: uint32, semantic: StrideA0 }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: SizeFree2 }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: Padding } ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesXYBatch, One, One] + MatrixInstruction: [32, 32, 8, 1] + EnableMatrixInstruction: True + MIWaveTile: [4, 4] + WavefrontSize: 64 amdhsa.kernels: - .agpr_count: 0 .args: [] diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s index c6c34d8f0397..6f136f83ae61 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s @@ -80508,6 +80508,54 @@ s_endpgm // End of RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WG .amdgpu_metadata --- +custom.config: + Source: + Origin: rocroller + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + CustomKernel: + args: [ { type: int64, semantic: StrideA1 }, + { type: address, semantic: AddressA }, + { type: int64, semantic: StrideB1 }, + { type: address, semantic: AddressB }, + { type: int64, semantic: StrideC1 }, + { type: address, semantic: AddressC }, + { type: float32, semantic: Alpha }, + { type: float32, semantic: Beta }, + { type: int64, semantic: StrideA0 }, + { type: int64, semantic: SizeSum }, + { type: int64, semantic: StrideB0 }, + { type: int64, semantic: StrideC0 }, + { type: int64, semantic: StrideD0 }, + { type: int64, semantic: StrideD1 }, + { type: address, semantic: AddressD } ] + macrotile: [64, 64, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, Batch] + MatrixInstruction: [16, 16, 16, 1] + EnableMatrixInstruction: True + MIWaveTile: [2, 2] + WavefrontSize: 64 amdhsa.version: [1, 2] amdhsa.kernels: - .name: RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s index 8359e145f020..a183e01d7c66 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s @@ -48,6 +48,78 @@ custom.config: InternalSupportParams: KernArgsVersion: 2 + ProblemType: + OperationType: GEMM + DataType: h + DestDataType: h + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 0 + TransposeB: 1 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + CustomKernel: + args: [ { type: uint32, semantic: GemmCount }, + { type: uint32, semantic: TensileInternalArg0 }, + { type: uint32, semantic: TensileInternalArg1 }, + { type: uint32, semantic: NumWorkGroups }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeFree2 }, + { type: uint32, semantic: SizeSum }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressC }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressB }, + { type: address, semantic: AddressWorkspace }, + { type: address, semantic: AddressSynchronizer }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideD1 }, + { type: uint32, semantic: StrideC0 }, + { type: uint32, semantic: StrideC1 }, + { type: uint32, semantic: StrideA0 }, + { type: uint32, semantic: StrideA1 }, + { type: uint32, semantic: StrideB0 }, + { type: uint32, semantic: StrideB1 }, + { type: float32, semantic: Alpha }, + { type: float32, semantic: Beta }, + { type: uint32, semantic: ItersPerTile }, + { type: uint32, semantic: MagicNumberItersPerTile }, + { type: uint32, semantic: MagicShiftItersPerTile }, + { type: uint32, semantic: TotalIters }, + { type: uint32, semantic: SKItersPerWG }, + { type: uint32, semantic: SKGrid }, + { type: uint32, semantic: SKTilesAndSplit } ] + macrotile: [128, 256, 64] + threads: [256, 1, 1] + grid: [TilesXYBatch, One, One] + workspaceType: StreamK + workspaceSizePerElemC: 4 + workspaceSizePerElemBias: 4 + MatrixInstruction: [16, 16, 16, 1] + EnableMatrixInstruction: True + EnableF32XdlMathOp: False + MFMA_BF16_1K: False + MIBlock: [16, 16, 16, 1, 1, 1] + MatrixInstM: 16 + MatrixInstN: 16 + MatrixInstK: 16 + MatrixInstB: 1 + MatrixInstBM: 1 + MatrixInstBN: 1 + MIInputPerThread: 4 + MIInputPerThreadA: 4 + MIInputPerThreadB: 4 + MIInputPerThreadMetadata: 4 + MIWaveGroup: [1, 4] + MIWaveTile: [8, 4] + ThreadTile: [16, 8] + WorkGroup: [8, 32, 1] + DepthU: 64 + WavefrontSize: 64 amdhsa.version: - 1 - 1 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s index 1fb2f5326555..e064e8210d5f 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s @@ -1930,6 +1930,48 @@ wave_bf16_gemm_256x256x64: .section ".note.GNU-stack","",@progbits .amdgpu_metadata --- +custom.config: + Source: + Origin: wave + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: b + DestDataType: s + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: True + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + CustomKernel: + args: [ { type: address, semantic: AddressB }, + { type: address, semantic: AddressA }, + { type: address, semantic: AddressD }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: Padding }, + { type: uint32, semantic: SizeSum }, + { type: uint32, semantic: Padding } ] + macrotile: [256, 256, 64] + threads: [256, 4, 1] + grid: [TilesY, TilesX, One] + MatrixInstruction: [16, 16, 32, 1] + EnableMatrixInstruction: True + MIWaveTile: [4, 4] + WavefrontSize: 64 amdhsa.kernels: - .agpr_count: 0 .args: diff --git a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py index 25479ad3cfbf..20ca03f221c3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py +++ b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py @@ -390,7 +390,7 @@ def parseLibraryLogicData( problemType = ProblemType(data["ProblemType"], printIndexAssignmentInfo) # unpack solution - def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Solution: + def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Optional[Solution]: if solutionState["KernelLanguage"] == "Assembly": solutionState["ISA"] = gfxToIsa(data["ArchitectureName"]) solutionState["CUCount"] = data["CUCount"] @@ -409,7 +409,12 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Solution: isp = {} if "InternalSupportParams" in solutionState: isp = solutionState["InternalSupportParams"] - customConfig = getCustomKernelConfig(customKernelName, isp) + try: + customConfig = getCustomKernelConfig(customKernelName, isp) + except (RuntimeError, KeyError, TypeError) as e: + printWarning(f"Skipping custom kernel '{customKernelName}': " + f"missing or invalid custom.config ({e})") + return None for key, value in customConfig.items(): solutionState[key] = value @@ -445,7 +450,11 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Solution: return solutionObject resetTypeMismatchCollector() - solutions = [solutionStateToSolution(solutionState, assembler, isaInfoMap) for solutionState in data["Solutions"]] + allSolutions = [solutionStateToSolution(solutionState, assembler, isaInfoMap) for solutionState in data["Solutions"]] + skipped = sum(1 for s in allSolutions if s is None) + if skipped: + printWarning(f"Skipped {skipped} solution(s) due to missing or invalid custom.config") + solutions = [s for s in allSolutions if s is not None] typeMismatches = getTypeMismatchCollector() newLibrary, _ = SolutionLibrary.MasterSolutionLibrary.FromOriginalState( diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index f30a5550115a..430bdc0f2baf 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -36,7 +36,7 @@ from Tensile.Common import assignParameterWithDefault, IsaInfo, \ print2, printExit, printWarning, \ roundUp, INDEX_CHARS, IsaVersion, SemanticVersion, \ - roundUpToNearestMultiple + roundUpToNearestMultiple, deriveWaveParams from Tensile.Common.DataType import DataType from Tensile.Common.GlobalParameters import defaultSolution, \ defaultInternalSupportParams @@ -1173,7 +1173,21 @@ def _assignCustomKernelParameters(state): if state["ProblemType"]["UseBias"] and state["ProblemType"]["Gradient"]: state["_WorkspaceSizePerElemBias"] = ck.get("workspaceSizePerElemBias", 0) - state["MIWaveGroup"] = [0, 0] + mi = state.get("MatrixInstruction", []) + state.setdefault("EnableMatrixInstruction", isinstance(mi, list) and len(mi) >= 4) + + if state["EnableMatrixInstruction"]: + wavefrontSize = state.get("WavefrontSize", 64) + macrotile = [state["MacroTile0"], state["MacroTile1"]] + waveGroup, waveTile = deriveWaveParams(mi, state["NumThreads"], macrotile, wavefrontSize) + if "MIWaveTile" not in state: + state["MIWaveTile"] = waveTile + if "MIWaveGroup" not in state or state["MIWaveGroup"] == [0, 0]: + state["MIWaveGroup"] = waveGroup + else: + state.setdefault("MIWaveTile", [0, 0]) + state["MIWaveGroup"] = [0, 0] + state["LocalSplitU"] = 1 state["GlobalReadVectorWidthA"] = 1 state["GlobalReadVectorWidthB"] = 1 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tensile.py b/projects/hipblaslt/tensilelite/Tensile/Tensile.py index db46c65b2260..815b391eb714 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tensile.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tensile.py @@ -203,6 +203,8 @@ def splitExtraParameters(par): help="set PrintLevel=2") argParser.add_argument("--debug", dest="debug", action="store_true", \ help="set PrintLevel=2 and CMakeBuildType=Debug") + argParser.add_argument("--validate-metadata", dest="ValidateMetadata", action="store_true", \ + help="enable build-time validation of custom kernel metadata (custom.config blocks)") argParser.add_argument("--cxx-compiler", dest="CxxCompiler", \ action="store", default=ToolchainDefaults.CXX_COMPILER, help="select which C++/HIP compiler to use") argParser.add_argument("--c-compiler", dest="CCompiler", \ @@ -243,6 +245,9 @@ def argUpdatedGlobalParameters(args): if args.debug: print1("# Command-line override: Debug") rv["CMakeBuildType"] = "Debug" + if args.ValidateMetadata: + print1("# Command-line override: ValidateMetadata") + rv["ValidateMetadata"] = True if args.client_lock: rv["ClientExecutionLockPath"] = args.client_lock if args.prebuilt_client: diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py index b029ab93867f..21645aa9fe4b 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py @@ -27,7 +27,7 @@ from pathlib import Path from typing import Dict, Tuple -from Tensile.Common import print1, IsaVersion, IsaInfo +from Tensile.Common import print1, printWarning, IsaVersion, IsaInfo from Tensile.SolutionStructs.Validators.MatrixInstruction import matrixInstructionToMIParameters from Tensile.CustomKernels import isCustomKernelConfig, getCustomKernelConfig @@ -54,7 +54,11 @@ def handleCustomKernel(sol: dict, isaInfoMap: Dict[IsaVersion, IsaInfo]) -> Tupl else: name = sol.get("CustomKernelName", "") dir = CUSTOM_KERNEL_PATH - config = getCustomKernelConfig(name, {}, dir) + try: + config = getCustomKernelConfig(name, {}, dir) + except (RuntimeError, KeyError, TypeError) as e: + printWarning(f"Skipping custom kernel '{name}': missing or invalid custom.config ({e})") + return sol, False sol.update(config) mi = sol["MatrixInstruction"] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index 61f39cef914a..6c7ddfe732e8 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -9,13 +9,10 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 CSVExportWinner: 1 CSVMergeSameProblemID: 1 Device: 0 - PrintSolutionRejectionReason: True - DeviceLDS: 163840 - MaxLDS: 163840 + ValidateMetadata: True BenchmarkProblems: - @@ -33,7 +30,7 @@ BenchmarkProblems: Activation: False UseScaleAlphaVec: 0 - - # BenchmarkProblemSizeGroup - Standard - All problem + - # BenchmarkProblemSizeGroup InitialSolutionParameters: BenchmarkCommonParameters: - KernelLanguage: ["Assembly"] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml index 905b014c0545..c9792be7c01e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -9,13 +9,10 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 CSVExportWinner: 1 CSVMergeSameProblemID: 1 Device: 0 - PrintSolutionRejectionReason: True - DeviceLDS: 163840 - MaxLDS: 163840 + ValidateMetadata: True BenchmarkProblems: - diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 506ca656db5b..b47a8b512498 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -9,16 +9,10 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 CSVExportWinner: 1 CSVMergeSameProblemID: 1 Device: 0 - PrintSolutionRejectionReason: True - - # PrintTensorA: 1 - # PrintTensorB: 1 - # PrintTensorD: 2 - # PrintTensorRef: 2 + ValidateMetadata: True BenchmarkProblems: - @@ -33,18 +27,17 @@ BenchmarkProblems: UseBeta: True Batched: True UseBias: 0 - Batched: True Activation: False UseScaleAlphaVec: 0 - - # BenchmarkProblemSizeGroup - Standard - All problem + - # BenchmarkProblemSizeGroup InitialSolutionParameters: BenchmarkCommonParameters: - KernelLanguage: ["Assembly"] ForkParameters: - CustomKernel: - name: "c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942" - args: [ { type: address, semantic: AddressB }, + args: [ { type: address, semantic: AddressB }, { type: address, semantic: AddressA }, { type: address, semantic: AddressD }, { type: address, semantic: AddressD }, @@ -62,20 +55,18 @@ BenchmarkProblems: { type: uint32, semantic: Padding }, { type: uint32, semantic: Padding }, { type: uint32, semantic: Padding } ] - # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] macrotile: [256, 256, 64] threads: [256, 1, 1] grid: [TilesXYBatch, One, One] + - MatrixInstruction: + - [32, 32, 8, 1, 1, 4, 4, 2, 2] BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: - # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] - # - Exact: [256, 256, 1, 256] - Exact: [2048, 4096, 1, 1024] - # - Exact: [3328, 4096, 1, 4096] LibraryLogic: ScheduleName: "aquavanjaram" DeviceNames: ["Device 0049", "Device 0050"] ArchitectureName: "gfx942" - LibraryType: "GridBased" \ No newline at end of file + LibraryType: "GridBased" diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index 0f1c584e8a91..e362f669b8e2 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -9,16 +9,10 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 CSVExportWinner: 1 CSVMergeSameProblemID: 1 Device: 0 - PrintSolutionRejectionReason: True - - # PrintTensorA: 1 - # PrintTensorB: 1 - # PrintTensorD: 2 - # PrintTensorRef: 2 + ValidateMetadata: True BenchmarkProblems: - @@ -36,14 +30,14 @@ BenchmarkProblems: Activation: False UseScaleAlphaVec: 0 - - # BenchmarkProblemSizeGroup - Standard - All problem + - # BenchmarkProblemSizeGroup InitialSolutionParameters: BenchmarkCommonParameters: - KernelLanguage: ["Assembly"] ForkParameters: - CustomKernel: - name: "RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e" - args: [ { type: int64, semantic: StrideA1 }, + args: [ { type: int64, semantic: StrideA1 }, { type: address, semantic: AddressA }, { type: int64, semantic: StrideB1 }, { type: address, semantic: AddressB }, @@ -51,21 +45,19 @@ BenchmarkProblems: { type: address, semantic: AddressC }, { type: float32, semantic: Alpha }, { type: float32, semantic: Beta }, - { type: int64, semantic: StrideA0 }, + { type: int64, semantic: StrideA0 }, { type: int64, semantic: SizeSum }, { type: int64, semantic: StrideB0 }, { type: int64, semantic: StrideC0 }, { type: int64, semantic: StrideD0 }, - { type: int64, semantic: StrideD1 }, + { type: int64, semantic: StrideD1 }, { type: address, semantic: AddressD } ] macrotile: [64, 64, 64] threads: [256, 1, 1] grid: [TilesX, TilesY, Batch] - MatrixInstruction: - - [16,16,16, 1, 1, 2,2, 2,2] # 256 x 128 + - [16,16,16, 1, 1, 2,2, 2,2] - PreloadKernArgs: [False] - # - PrefetchGlobalRead: [2] - # - PrefetchLocalRead: [1] - DepthU: [64] - VectorWidthA: [-1] - VectorWidthB: [-1] @@ -97,18 +89,13 @@ BenchmarkProblems: - NonTemporalB: [0] - DirectToVgprA: [1] - DirectToVgprB: [0] - # - WorkGroup: [[32,4,4]] - BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: - # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] - # - Exact: [256, 256, 1, 256] - Exact: [2048, 4096, 1, 1024] - # - Exact: [3328, 4096, 1, 4096] LibraryLogic: ScheduleName: "aquavanjaram" DeviceNames: ["Device 0049", "Device 0050"] ArchitectureName: "gfx942" - LibraryType: "GridBased" \ No newline at end of file + LibraryType: "GridBased" diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml index 227d5e6ca0fe..e16c13c66712 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml @@ -14,11 +14,7 @@ GlobalParameters: CSVMergeSameProblemID: 1 Device: 0 PrintSolutionRejectionReason: True - - # PrintTensorA: 1 - # PrintTensorB: 1 - # PrintTensorD: 2 - # PrintTensorRef: 2 + ValidateMetadata: True BenchmarkProblems: - @@ -75,7 +71,6 @@ BenchmarkProblems: { type: uint32, semantic: SKItersPerWG }, { type: uint32, semantic: SKGrid }, { type: uint32, semantic: SKTilesAndSplit } ] - # args: [address AddressB, int64 AddressA, float8 AddressD, bfloat16 AddressD, uint64 SizeFree1, uint64 SizeFree0, boolean SizeSum, uint32 StrideB0, uint32 StrideA0, uint32 StrideD0, uint32 StrideD0, uint32 SizeFree2, pointer DebugPattern, pointer DebugPattern, int16 DebugPattern, int32 DebugPattern, uint32 DebugPattern, float64 DebugPattern] macrotile: [128, 256, 64] threads: [256, 1, 1] grid: [TilesXYBatch, One, One] @@ -85,11 +80,7 @@ BenchmarkProblems: BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: - # - Exact: [3328, 4096, 1, 4096, 4096, 4096, 4096, 4096] - # - Exact: [256, 256, 1, 256] - # - Exact: [2048, 4096, 1, 1024] - Exact: [4103, 4103, 1, 1031] - # - Exact: [3328, 4096, 1, 4096] LibraryLogic: ScheduleName: "aquavanjaram" diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml index a8fa67f59c47..76eaca9e23cf 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml @@ -9,13 +9,10 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 CSVExportWinner: 1 CSVMergeSameProblemID: 1 Device: 0 - PrintSolutionRejectionReason: True - DeviceLDS: 163840 - MaxLDS: 163840 + ValidateMetadata: True BenchmarkProblems: - diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py new file mode 100644 index 000000000000..9011d9b8dad9 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -0,0 +1,192 @@ +################################################################################ +# +# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +################################################################################ + +from textwrap import dedent, indent + +import pytest + +from Tensile.AddCustomConfig import ( + _parse_tensile_yaml, + _read_asm_file, + build_custom_config_yaml, + inject_custom_config, +) +from Tensile.CustomKernels import getCustomKernelConfig, validateCustomKernelMetadata +from Tensile.Toolchain.Assembly import validateCustomKernelMetadataAtBuild +from Tensile.ValidateMetadata import validate_all + + +def write_kernel(path, config): + path.parent.mkdir(parents=True, exist_ok=True) + config_block = indent(dedent(config).strip(), " ") + path.write_text( + ".amdgpu_metadata\n" + "---\n" + "custom.config:\n" + f"{config_block}\n" + "amdhsa.kernels:\n" + f" - .name: {path.stem}\n" + " .max_flat_workgroup_size: 64\n" + " .args:\n" + " - .name: D\n" + " .size: 8\n" + " .offset: 0\n" + " .value_kind: global_buffer\n" + "...\n" + ) + + +def test_validate_external_requires_full_custom_kernel_fields(tmp_path): + write_kernel(tmp_path / "external.s", """\ + Source: + Origin: test + Version: 1.0.0 + Features: {} + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + CustomKernel: + args: [] + macrotile: [16, 16, 16] + threads: [64, 1, 1] + """) + + valid, msg = validateCustomKernelMetadata("external", str(tmp_path)) + + assert not valid + assert "CustomKernel.grid" in msg + + +def test_validate_tensile_kernel_only_needs_kern_args_version(tmp_path): + """Tensile-generated kernels carry only InternalSupportParams.KernArgsVersion; + ProblemType and tuning state come from the consuming logic file or test YAML.""" + write_kernel(tmp_path / "tensile.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + + valid, msg = validateCustomKernelMetadata("tensile", str(tmp_path)) + + assert valid, msg + + +def test_validate_tensile_kernel_missing_kern_args_version_fails(tmp_path): + write_kernel(tmp_path / "tensile.s", """\ + InternalSupportParams: {} + """) + + valid, msg = validateCustomKernelMetadata("tensile", str(tmp_path)) + + assert not valid + assert "InternalSupportParams.KernArgsVersion" in msg + + +def test_build_validation_passes_for_minimal_tensile_kernel(tmp_path): + write_kernel(tmp_path / "tensile.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + kernels = [{"CustomKernel": {"name": "tensile"}}] + + assert validateCustomKernelMetadataAtBuild(kernels, str(tmp_path)) == 0 + + +def test_validate_all_uses_recursive_loader_discovery(tmp_path): + write_kernel(tmp_path / "nested" / "kernel.s", """\ + Source: + Origin: test + InternalSupportParams: + KernArgsVersion: 0 + """) + + errors, warnings = validate_all(str(tmp_path), strict=True) + + assert len(errors) == 1 + assert warnings == [] + assert "nested" in errors[0] + + +def test_get_custom_kernel_config_infers_metadata_only_kernel(tmp_path): + write_kernel(tmp_path / "metadata_only.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + """) + + config = getCustomKernelConfig("metadata_only", {}, str(tmp_path)) + + assert config["CustomKernel"]["name"] == "metadata_only" + assert config["CustomKernel"]["args"][0]["semantic"] == "AddressD" + assert config["CustomKernel"]["threads"] == [64, 1, 1] + + +def test_parse_tensile_yaml_fails_when_kernel_not_found(tmp_path): + yaml_path = tmp_path / "custom.yaml" + yaml_path.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - CustomKernel: + - name: present_kernel + args: [] + macrotile: [16, 16, 16] + threads: [64, 1, 1] + grid: [TilesX, TilesY, Batch] + """)) + + with pytest.raises(RuntimeError, match="Kernel 'missing_kernel' not found"): + _parse_tensile_yaml(str(yaml_path), "missing_kernel") + + +def test_read_asm_file_reports_invalid_metadata_yaml(tmp_path): + asm_path = tmp_path / "bad.s" + asm_path.write_text(dedent("""\ + .amdgpu_metadata + --- + custom.config: [ + ... + """)) + + with pytest.raises(RuntimeError, match="Failed to parse .amdgpu_metadata YAML"): + _read_asm_file(str(asm_path)) + + +def test_inject_custom_config_dry_run_does_not_modify_file(tmp_path, capsys): + asm_path = tmp_path / "dry_run.s" + asm_path.write_text(dedent("""\ + .amdgpu_metadata + --- + amdhsa.kernels: [] + ... + """)) + before = asm_path.read_text() + file_info = _read_asm_file(str(asm_path)) + config_yaml = build_custom_config_yaml("test", None) + + assert inject_custom_config(file_info, str(asm_path), config_yaml, dry_run=True) + assert asm_path.read_text() == before + assert "custom.config block that would be inserted" in capsys.readouterr().out diff --git a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Assembly.py b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Assembly.py index a8b91e8d6210..3105b4b918d9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Assembly.py +++ b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Assembly.py @@ -30,8 +30,11 @@ from pathlib import Path from typing import List, Union, NamedTuple -from Tensile.Common import print2 +from Tensile.Common import print1, print2, printWarning +from Tensile.Common.GlobalParameters import globalParameters from Tensile.Common.Architectures import isaToGfx +from Tensile.CustomKernels import validateCustomKernelMetadata +from Tensile import CUSTOM_KERNEL_PATH from ..SolutionStructs import Solution from .Component import Assembler, Linker, Bundler @@ -49,6 +52,38 @@ def makeAssemblyToolchain(assembler_path, bundler_path, co_version, build_id_kin return AssemblyToolchain(compiler, linker, bundler) +def validateCustomKernelMetadataAtBuild(kernels, directory=CUSTOM_KERNEL_PATH): + """Validates embedded metadata for all custom kernels in the build. + + Logs warnings for kernels with missing or invalid custom.config and a + single summary line at the end. + + Returns the number of validation issues found. + """ + issues = 0 + validated = set() + + for k in kernels: + ck = k.get("CustomKernel", None) + if not ck or not ck.get("name"): + continue + + name = ck["name"] + if name in validated: + continue + validated.add(name) + + valid, msg = validateCustomKernelMetadata(name, directory) + if not valid: + printWarning(f"Metadata validation: {msg}") + issues += 1 + + if validated: + print1(f"Metadata: validated {len(validated)} custom kernel(s), {issues} issue(s)") + + return issues + + def buildAssemblyCodeObjectFiles( linker: Linker, bundler: Bundler, @@ -68,6 +103,9 @@ def buildAssemblyCodeObjectFiles( compress: Whether to compress the code object files. """ + if globalParameters["ValidateMetadata"]: + validateCustomKernelMetadataAtBuild(kernels) + extObj = ".o" extCo = ".co" extCoRaw = ".co.raw" diff --git a/projects/hipblaslt/tensilelite/Tensile/ValidateMetadata.py b/projects/hipblaslt/tensilelite/Tensile/ValidateMetadata.py new file mode 100644 index 000000000000..bb84a84efa2a --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/ValidateMetadata.py @@ -0,0 +1,112 @@ +################################################################################ +# +# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# +################################################################################ + +"""CI enforcement script for custom kernel metadata validation. + +Validates that all custom kernel .s files contain a custom.config block +inside their .amdgpu_metadata YAML section. + +Exit codes: + 0 - All kernels pass validation + 1 - One or more validation failures + +Usage: + python -m Tensile.ValidateMetadata [--strict] [--custom-kernels-root DIR] + + --strict Treat missing or incomplete metadata as errors. + Without --strict, validation failures produce warnings only. +""" + +import argparse +import os +import sys + +from Tensile.CustomKernels import iterCustomKernelFiles, validateCustomKernelMetadata + + +def validate_all(root, strict=False): + """Validates all kernels under a directory for embedded metadata. + + With ``strict=True``, validation failures are returned as errors; + otherwise they are returned as warnings. + + Returns (errors, warnings) as lists of message strings. + """ + errors = [] + warnings = [] + + for path in iterCustomKernelFiles(root): + kernel_dir = os.path.dirname(path) + name = os.path.basename(path)[:-2] + + valid, msg = validateCustomKernelMetadata(name, kernel_dir) + if not valid: + (errors if strict else warnings).append(f"{path}: {msg}") + + return errors, warnings + + +def main(): + parser = argparse.ArgumentParser( + description="Validate custom kernel embedded metadata for CI enforcement" + ) + parser.add_argument( + "--strict", + action="store_true", + help="Treat missing metadata as errors", + ) + parser.add_argument( + "--custom-kernels-root", + type=str, + help="Root CustomKernels directory (default: auto-detect)", + ) + args = parser.parse_args() + + if args.custom_kernels_root: + root = args.custom_kernels_root + else: + root = os.path.join(os.path.dirname(os.path.abspath(__file__)), "CustomKernels") + + if not os.path.isdir(root): + print(f"ERROR: CustomKernels directory not found: {root}", file=sys.stderr) + sys.exit(1) + + errors, warnings = validate_all(root, strict=args.strict) + + for w in warnings: + print(f"WARNING: {w}") + for e in errors: + print(f"ERROR: {e}") + + total_kernels = sum(1 for _ in iterCustomKernelFiles(root)) + + print(f"\nSummary: {total_kernels} kernel(s), {len(errors)} error(s), {len(warnings)} warning(s)") + + if errors: + sys.exit(1) + sys.exit(0) + + +if __name__ == "__main__": + main() diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index bbe68a77978c..acebeb7423ab 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include From cdd427af9f7d77927566e4fae9ab4de8c1ca4c1c Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Thu, 30 Apr 2026 15:00:06 -0700 Subject: [PATCH 30/58] [hipblaslt][G-F-A] Fix GFA regressions (#6973) --- .../tensilelite/Tensile/Contractions.py | 6 +- .../Tensile/SolutionStructs/Solution.py | 14 +++ .../include/Tensile/ContractionSolution.hpp | 5 + .../Serialization/ContractionSolution.hpp | 1 + .../tensilelite/src/ContractionSolution.cpp | 98 ++++++++++++++++--- 5 files changed, 109 insertions(+), 15 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index 4054df1d340e..a4eb43b1a21b 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -614,7 +614,8 @@ class CustomKernel: 'grid', 'workspaceType', 'workspaceSizePerElemC', - 'workspaceSizePerElemBias'] + 'workspaceSizePerElemBias', + 'generated'] @classmethod def FromOriginalState(cls, d): @@ -625,7 +626,8 @@ def FromOriginalState(cls, d): grid=d['grid'], workspaceType=d.get('workspaceType', 'None'), workspaceSizePerElemC=d.get('workspaceSizePerElemC', 0), - workspaceSizePerElemBias=d.get('workspaceSizePerElemBias', 0)) + workspaceSizePerElemBias=d.get('workspaceSizePerElemBias', 0), + generated=d.get('generated', False)) def __init__(self, **kwargs): for (key, value) in list(kwargs.items()): diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 430bdc0f2baf..37ceb463ba88 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -1154,7 +1154,21 @@ def _assignCustomKernelParameters(state): state["MacroTile1"] = ck["macrotile"][1] state["DepthU"] = ck["macrotile"][2] + # Derive _GlobalAccumulation from GlobalSplitUAlgorithm so the C++ + # runtime sees a non-zero sizeMapping.globalAccumulation for GSU>1 + # solutions. Without this the legacy beta-only kernel + # (`Cijk_
_BiasS`) was launched and not found in the library. state["_GlobalAccumulation"] = None + if state.get("StreamK", 0) > 0 and state.get("StreamKAtomic", 0) == 0: + state["_GlobalAccumulation"] = 'PartialsBuffer' + elif state.get("GlobalSplitUAlgorithm", "") == 'SingleBuffer': + computeName = state["ProblemType"]["ComputeDataType"].toName() + if computeName != state["ProblemType"]["DestDataType"].toName(): + state["_GlobalAccumulation"] = 'SingleBuffer' + elif state.get("GlobalSplitUAlgorithm", "") == 'MultipleBuffer': + state["_GlobalAccumulation"] = 'MultipleBuffer' + elif state.get("GlobalSplitUAlgorithm", "") == 'MultipleBufferSingleKernel': + state["_GlobalAccumulation"] = 'MultipleBufferSingleKernel' state["CUOccupancy"] = -1 state["MathClocksUnrolledLoop"] = 0 state["PackedC0IndicesX"] = [] diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index acebeb7423ab..00e8cc71fc62 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -211,6 +211,11 @@ namespace TensileLite CustomWorkspaceType workspaceType; size_t workspaceSizePerElemC; size_t workspaceSizePerElemBias; + // True when this CustomKernel was auto-populated for a Tensile-generated + // kernel (vs. a hand-written custom kernel). Generated kernels still + // rely on sizeMapping for workspace/Stream-K decisions, so several code + // paths must treat them like the legacy non-custom case. + bool generated = false; }; template diff --git a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp index 86bc5855db6e..62ac97ea3d71 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/Serialization/ContractionSolution.hpp @@ -88,6 +88,7 @@ namespace TensileLite iot::mapOptional(io, "workspaceType", s.workspaceType); iot::mapOptional(io, "workspaceSizePerElemC", s.workspaceSizePerElemC); iot::mapOptional(io, "workspaceSizePerElemBias", s.workspaceSizePerElemBias); + iot::mapOptional(io, "generated", s.generated); } const static bool flow = false; diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index cdebef1a2575..85c8f088c3c6 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -918,8 +918,9 @@ namespace TensileLite args.template append("magicNumberItersPerTile", magicNumberItersPerTile); args.template append("magicShiftItersPerTile", magicShiftItersPerTile); - // Custom kernels still use totalIters - if(!customKernel.name.empty()) + // Hand-written custom kernels still use totalIters; Tensile-generated + // kernels follow the legacy non-custom layout. + if(!customKernel.name.empty() && !customKernel.generated) { args.template append("totalIters", totalIters); } @@ -1796,6 +1797,27 @@ namespace TensileLite uint32_t debugPattern = 0xDB000001; bool appendedInternalArgs = false; + // For multi-buffer GSU and Stream-K parallel reduction, the kernel + // writes to the GSU/SK workspace and expects strides derived from + // d.sizes() (matching the legacy `strideW_D`/`strideW_C` layout used + // in singleCallArgs on develop). Outside those modes the regular + // tensor strides apply. + bool gsuWSStride + = gsu > 1 && sizeMapping.globalAccumulation != 3 && sizeMapping.streamK == 0; + bool skWSStride + = sizeMapping.streamK > 0 && sk.reduction == origami::reduction_t::parallel; + bool useWSStride = gsuWSStride || skWSStride; + size_t startStrideCD = problemType.useInitialStridesCD ? 0 : 1; + + auto wsStrideForIdx = [&](size_t idx) -> size_t { + // Mirrors the develop accumulator: stride[startStrideCD] = sizes[0], + // and each subsequent stride multiplies in the next size. + size_t s = startStrideCD ? problem.d().sizes()[0] : 1; + for(size_t i = startStrideCD; i < idx; ++i) + s *= problem.d().sizes()[i]; + return s; + }; + if(T_Debug) std::cout << "Custom call arguments:" << std::endl; @@ -1847,22 +1869,34 @@ namespace TensileLite rv.args.appendCustomType("StrideB2", problem.b().strides()[3], arg.type); break; case CustomArgSemantic::StrideC0: - rv.args.appendCustomType("StrideC0", problem.c().strides()[1], arg.type); + rv.args.appendCustomType("StrideC0", + useWSStride ? wsStrideForIdx(1) : problem.c().strides()[1], + arg.type); break; case CustomArgSemantic::StrideC1: - rv.args.appendCustomType("StrideC1", problem.c().strides()[2], arg.type); + rv.args.appendCustomType("StrideC1", + useWSStride ? wsStrideForIdx(2) : problem.c().strides()[2], + arg.type); break; case CustomArgSemantic::StrideC2: - rv.args.appendCustomType("StrideC2", problem.c().strides()[3], arg.type); + rv.args.appendCustomType("StrideC2", + useWSStride ? wsStrideForIdx(3) : problem.c().strides()[3], + arg.type); break; case CustomArgSemantic::StrideD0: - rv.args.appendCustomType("StrideD0", problem.d().strides()[1], arg.type); + rv.args.appendCustomType("StrideD0", + useWSStride ? wsStrideForIdx(1) : problem.d().strides()[1], + arg.type); break; case CustomArgSemantic::StrideD1: - rv.args.appendCustomType("StrideD1", problem.d().strides()[2], arg.type); + rv.args.appendCustomType("StrideD1", + useWSStride ? wsStrideForIdx(2) : problem.d().strides()[2], + arg.type); break; case CustomArgSemantic::StrideD2: - rv.args.appendCustomType("StrideD2", problem.d().strides()[3], arg.type); + rv.args.appendCustomType("StrideD2", + useWSStride ? wsStrideForIdx(3) : problem.d().strides()[3], + arg.type); break; case CustomArgSemantic::StrideE0: rv.args.appendCustomType("StrideE0", problem.tensor(ContractionProblemGemm::TENSOR::E).strides()[1], arg.type); @@ -2074,7 +2108,15 @@ namespace TensileLite case CustomArgSemantic::GemmInfo: { uint32_t gemmCount = 1; - gemmCount = gemmCount & 0x3FFFFFFF; + // Encode argType (high 2 bits) so the kernel can distinguish + // single/strided-batched (0) from general-batched POINTER_ARRAY (3). + // Matches the legacy generateSingleCall encoding used by the + // assembly kernel's ArgType branch (cf. KernelWriterAssembly.py). + uint32_t argType = (problem.batchMode() + == ContractionProblemGemm::BATCHMODE::POINTER_ARRAY) + ? 3u + : static_cast(KERNELARGTYPE::NORMAL); + gemmCount = (gemmCount & 0x3FFFFFFF) | (argType << 30); rv.args.template append("gemm_count", gemmCount); break; } @@ -3475,7 +3517,7 @@ namespace TensileLite { sk.reduction = getSKReduction(problem, hardware); size_t tiles = 0; - if (customKernel.name.empty()) + if (customKernel.name.empty() || customKernel.generated) tiles = problem.getNumTiles(sizeMapping, 1); else { @@ -3885,14 +3927,30 @@ namespace TensileLite size_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : sizeMapping.globalSplitU; + // Tensile-generated kernels populate `customKernel` for codegen + // metadata only; their workspace decisions still come from sizeMapping + // (matches the legacy single-branch behavior on develop). Some + // handwritten kernels do not carry workspace metadata but can still be + // selected for non-grouped GSU>1 multi-buffer runs. Treat those as + // SplitK for workspace sizing only; keep grouped GEMM on its existing + // path to avoid changing grouped solution selection/host-arg sizing. + bool useLegacyWorkspaceLogic = customKernel.name.empty() || customKernel.generated; + bool inferSplitKWorkspaceForCustom = !useLegacyWorkspaceLogic + && !problem.groupedGemm() + && customKernel.workspaceType == CustomWorkspaceType::None + && customKernel.workspaceSizePerElemC == 0 + && sizeMapping.globalAccumulation != 0 + && sizeMapping.streamK == 0; CustomWorkspaceType workspaceType = CustomWorkspaceType::None; - if(customKernel.name.empty()) + if(useLegacyWorkspaceLogic) { if(sizeMapping.streamK > 0 && sizeMapping.streamKAtomic == 0) workspaceType = CustomWorkspaceType::StreamKWithReduction; else workspaceType = CustomWorkspaceType::SplitK; } + else if(inferSplitKWorkspaceForCustom) + workspaceType = CustomWorkspaceType::SplitK; else workspaceType = customKernel.workspaceType; @@ -3907,7 +3965,7 @@ namespace TensileLite } const bool streamKDP = Debug::Instance().useStreamKDataParrallel(); size_t tiles = 0; - if (customKernel.name.empty()) + if (useLegacyWorkspaceLogic) tiles = problem.getNumTiles(sizeMapping, 1); else { @@ -3962,7 +4020,21 @@ namespace TensileLite size_t tiles = problem.getNumTiles(sizeMapping, gsu) * batch; size_t tileSize = 0; size_t workspaceSizePerElemBias = 0; - if(customKernel.name.empty()) + bool inferWorkspaceSizeForCustom = !problem.groupedGemm() + && !customKernel.name.empty() + && !customKernel.generated + && customKernel.workspaceType == CustomWorkspaceType::None + && customKernel.workspaceSizePerElemC == 0 + && sizeMapping.globalAccumulation != 0 + && sizeMapping.streamK == 0; + if(inferWorkspaceSizeForCustom) + { + tileSize = customKernel.macrotile.x * customKernel.macrotile.y + * problem.computeTypeElementSize(); + workspaceSizePerElemBias = 0; + } + // Generated kernels still rely on sizeMapping for workspace sizing. + else if(customKernel.name.empty() || customKernel.generated) { tileSize = sizeMapping.macroTile.x * sizeMapping.macroTile.y * sizeMapping.workspaceSizePerElemC; workspaceSizePerElemBias = sizeMapping.workspaceSizePerElemBias; From dcff092b64e2ca79bf1506f948552b06d76ac957 Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Thu, 7 May 2026 17:32:07 -0700 Subject: [PATCH 31/58] [hipblaslt][G-F-A] Add problem size predicates for custom kernels (#7186) --- .../tensilelite/Tensile/AddCustomConfig.py | 25 +++ .../tensilelite/Tensile/BenchmarkProblems.py | 18 +-- .../tensilelite/Tensile/ClientWriter.py | 33 +--- .../Tensile/Common/ValidParameters.py | 6 +- .../tensilelite/Tensile/CustomKernels.py | 6 +- .../_ZN5aiter24bf16gemm_bf16_tn_256x256E.s | 2 + ...emm_bf16_per1x32Fp4_BpreShuffle_256x256E.s | 3 +- .../Tests/custom/custom_aiter_bf16.yaml | 3 +- .../Tensile/Tests/custom/custom_aiter_f4.yaml | 3 +- .../Tests/unit/test_CustomKernelMetadata.py | 150 +++++++++++++++++- .../client/include/ProgressListener.hpp | 3 - .../client/include/ReferenceValidator.hpp | 3 - .../hipblaslt/tensilelite/client/main.cpp | 4 - .../client/src/ProgressListener.cpp | 28 +--- .../client/src/ReferenceValidator.cpp | 47 +----- 15 files changed, 200 insertions(+), 134 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py b/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py index 7569f3dfe3f9..8dd40353eca9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py +++ b/projects/hipblaslt/tensilelite/Tensile/AddCustomConfig.py @@ -57,6 +57,7 @@ import sys from Tensile.Common.Utilities import deriveWaveParams +from Tensile.Common.ValidParameters import checkParametersAreValid, validParameters FEATURE_FLAGS = [ @@ -67,6 +68,12 @@ "SupportsGSU", ] +PREDICATE_FORK_PARAMETER_KEYS = ( + "AssertFree0ElementMultiple", + "AssertFree1ElementMultiple", + "AssertSummationElementMultiple", +) + def _parse_tensile_yaml(path, kernel_name=None): """Extract ProblemType, CustomKernel, and MatrixInstruction from a Tensile test YAML. @@ -126,6 +133,19 @@ def _parse_tensile_yaml(path, kernel_name=None): if wf_list: config["WavefrontSize"] = wf_list[0] + for pred_key in PREDICATE_FORK_PARAMETER_KEYS: + if pred_key not in entry: + continue + values = entry[pred_key] + if not isinstance(values, list) or len(values) != 1: + raise RuntimeError( + f"Custom kernel predicate '{pred_key}' must be a single-valued " + f"ForkParameter (got {values!r}); a custom kernel must commit " + f"to one constraint, not a search space." + ) + checkParametersAreValid((pred_key, values), validParameters) + config[pred_key] = values[0] + if kernel_name and "CustomKernel" not in config: raise RuntimeError( f"Kernel '{kernel_name}' not found in {path}. " @@ -244,6 +264,11 @@ def build_custom_config_yaml(origin, config, repository=None, version="1.0.0"): _, mi_wave_tile = deriveWaveParams(mi, num_threads, macrotile, wavefront_size) lines.append(f" MIWaveTile: {_fmt_yaml_inline(mi_wave_tile)}") + if config: + for pred_key in PREDICATE_FORK_PARAMETER_KEYS: + if pred_key in config: + lines.append(f" {pred_key}: {_fmt_yaml_inline(config[pred_key])}") + lines.append(f" WavefrontSize: {wavefront_size}") return "\n".join(lines) diff --git a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py index af5e5a384b00..61eba879b938 100644 --- a/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py +++ b/projects/hipblaslt/tensilelite/Tensile/BenchmarkProblems.py @@ -325,18 +325,6 @@ def writeBenchmarkFiles( for f in codeObjectFiles] with timing_context("python_benchpost_client_config"): - # If the custom kernel declares padProblemSizeToTile, extract - # the macrotile dims and per-axis flags so problemSizeParams() - # can pad M/N to tile boundaries. - macroTile = None - for sol in solutions: - if "CustomKernel" in sol and sol["CustomKernel"]: - ck = sol["CustomKernel"] - padFlags = ck.get("padProblemSizeToTile", None) - if padFlags: - macroTile = (sol["MacroTile0"], sol["MacroTile1"], padFlags) - break - if "TileAwareSelection" in problemType and problemType["TileAwareSelection"]: maxMacroTile0 = 0 maxMacroTile1 = 0 @@ -362,14 +350,12 @@ def writeBenchmarkFiles( writeClientConfig(True, solutions, idealProblemSizes, biasTypeArgs, \ factorDimArgs, activationArgs, icacheFlushArgs, stepName, stepBaseDir, \ newLibrary, codeObjectFiles, True, deviceId, gfxName, \ - libraryFile=newLibraryFileFull, probSolMap=probSolMap, - macroTile=macroTile) + libraryFile=newLibraryFileFull, probSolMap=probSolMap) else: writeClientConfig(True, solutions, problemSizes, biasTypeArgs, \ factorDimArgs, activationArgs, icacheFlushArgs, stepName, stepBaseDir, \ newLibrary, codeObjectFiles, False, deviceId, gfxName, \ - libraryFile=newLibraryFileFull, probSolMap=probSolMap, - macroTile=macroTile) + libraryFile=newLibraryFileFull, probSolMap=probSolMap) if len(solutions) == 0: printExit("write solutions and kernels results 0 valid soultion.") diff --git a/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py b/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py index 50e212813544..0c3aa7d18d42 100644 --- a/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/ClientWriter.py @@ -394,10 +394,7 @@ def checkConstStride(constStrideMap, keyIdx): return finalVal -def _ceilTo(val, multiple): - return ((val + multiple - 1) // multiple) * multiple - -def problemSizeParams(problemType, problem, factorDim, macroTile=None): +def problemSizeParams(problemType, problem, factorDim): numIndices = len(problemType.indices) rv = [] @@ -465,27 +462,8 @@ def problemSizeParams(problemType, problem, factorDim, macroTile=None): ', '.join(map(str, problem.sizes)))) sizes = list(problem.sizes[:numIndices]) - originalSizes = None - # When a custom kernel declares padProblemSizeToTile: [padM, padN], - # pad the requested dimensions to macrotile boundaries. Save the - # original sizes so the client can report/validate the unpadded region. - if macroTile is not None: - mt0, mt1, padFlags = macroTile - padM = _ceilTo(sizes[0], mt0) if padFlags[0] else sizes[0] - padN = _ceilTo(sizes[1], mt1) if padFlags[1] else sizes[1] - if padM != sizes[0] or padN != sizes[1]: - originalSizes = list(sizes) - sizes[0] = padM - sizes[1] = padN - if cstrides and cstrides[1] != -1: - cstrides[1] = max(cstrides[1], padM) - if dstrides and dstrides[1] != -1: - dstrides[1] = max(dstrides[1], padM) - problemSizeArg = ('problem-size', ','.join(map(str, sizes))) rv.insert(0, problemSizeArg) - if originalSizes is not None: - rv.append(('original-problem-size', ','.join(map(str, originalSizes)))) rv.append(('a-strides', ",".join(map(str, astrides)))) rv.append(('b-strides', ",".join(map(str, bstrides)))) @@ -574,7 +552,7 @@ def pruneModeName(mode): if mode == 5: return 'Prune0X0X' if mode == 6: return 'Prune00XX' -def writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, problemType, sourceDir, codeObjectFiles, resultsFileName, parametersFilePath, deviceId: int, gfxName: str, libraryFile=None, probSolMap={}, macroTile=None): +def writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, problemType, sourceDir, codeObjectFiles, resultsFileName, parametersFilePath, deviceId: int, gfxName: str, libraryFile=None, probSolMap={}): assert os.path.exists(sourceDir), f"sourceDir={sourceDir} does not exist" @@ -645,7 +623,7 @@ def param(key, value): probIdx = 0 for problem in problemSizes.problems: - for key,value in problemSizeParams(problemType, problem, factorDimArgs.factorDims, macroTile): + for key,value in problemSizeParams(problemType, problem, factorDimArgs.factorDims): param(key,value) if probIdx in probSolMap: solutionIdx = probSolMap[probIdx] @@ -752,8 +730,7 @@ def writeClientConfig( gfxName: str, configBase = "ClientParameters", libraryFile = None, - probSolMap = {}, - macroTile = None + probSolMap = {} ): sourceDir = os.path.join(stepBaseDir, "source") @@ -773,7 +750,7 @@ def writeClientConfig( resultsFileName = os.path.join(stepBaseDir, "../Data", stepName+".csv") newSolution = next(iter(newLibrary.solutions.values())) - writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, newSolution.problemType, sourceDir, codeObjectFiles, resultsFileName, filename, deviceId, gfxName, libraryFile, probSolMap, macroTile) + writeClientConfigIni(forBenchmark, problemSizes, biasTypeArgs, factorDimArgs, activationArgs, icacheFlushArgs, newSolution.problemType, sourceDir, codeObjectFiles, resultsFileName, filename, deviceId, gfxName, libraryFile, probSolMap) return filename diff --git a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py index b4689976db8a..dddfe713a09e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py +++ b/projects/hipblaslt/tensilelite/Tensile/Common/ValidParameters.py @@ -444,7 +444,7 @@ def makeValidMatrixInstructions(): # - Tail loop can be unrolled up to InnerUnroll amount if AssertSummationElementMultiple%InnerUnroll==0 # # 1 indicates no assertion (since all sizes are multiples of 1) - "AssertSummationElementMultiple": [1, 2, 4, 8, 16, 32, 64, 128], + "AssertSummationElementMultiple": [1, 2, 4, 8, 16, 32, 64, 128, 256], # Kernel generator will assume that the FreeIndex[0] size is some multiple of the element size # and uses this to optimize the kernel. # FreeIndex[0] is usually letter "I" @@ -462,7 +462,7 @@ def makeValidMatrixInstructions(): # (since C matrix is always coalesced in Free0 index direction and this assertion guarantees the index element multiple) # # 1 indicates no assertion (since all sizes are multiples of 1) - "AssertFree0ElementMultiple": [1, 2, 4, 8, 16, 32], + "AssertFree0ElementMultiple": [1, 2, 4, 8, 16, 32, 64, 128, 256], # Kernel generator will assume that the FreeIndex[1] size is some multiple of the element size # and uses this to optimize the kernel. # FreeIndex[1] is usually letter "J" @@ -470,7 +470,7 @@ def makeValidMatrixInstructions(): # Optimizations enabled by AssertFree1ElementMultiple>1: # - See above AssertFree0ElementMultiple "Load optimizations" # 1 indicates no assertion (since all sizes are multiples of 1) - "AssertFree1ElementMultiple": [1, 2, 4, 8, 16, 32], + "AssertFree1ElementMultiple": [1, 2, 4, 8, 16, 32, 64, 128, 256], # Address-interleave restriction: # If >0, require tiles1=(Free1Size / MT1) to have lowbit(tiles1)>1 (i.e. G>1). # This matches the kernel's initBInterleaveG logic: diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 090421418d73..93ad8bbeeaa8 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -353,7 +353,11 @@ def getCustomKernelConfig( if k in mergedValid: checkParametersAreValid((k, [v]), mergedValid) - metadata_keys = [k for k in kernelConfig if k not in mergedValid and k not in _PASSTHROUGH_KEYS] + metadata_keys = [ + k for k in kernelConfig + if k not in mergedValid + and k not in _PASSTHROUGH_KEYS + ] for k in metadata_keys: kernelConfig.pop(k) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s index 13dd170b4ca5..a3c1baa8fda4 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s @@ -2254,6 +2254,8 @@ custom.config: MatrixInstruction: [16, 16, 32, 1] EnableMatrixInstruction: True MIWaveTile: [8, 8] + AssertFree0ElementMultiple: 256 + AssertFree1ElementMultiple: 256 WavefrontSize: 64 amdhsa.kernels: - .args: diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s index f66508f824b2..8739f5dd22f3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s @@ -3499,12 +3499,13 @@ custom.config: { type: uint32, semantic: StrideScaleA1, padding: 12 }, { type: uint32, semantic: SplitK, padding: 12 } ] macrotile: [256, 256, 256] - padProblemSizeToTile: [true, true] threads: [256, 1, 1] grid: [TilesX, TilesY, One] MatrixInstruction: [16, 16, 128, 1] EnableMatrixInstruction: True MIWaveTile: [8, 8] + AssertFree0ElementMultiple: 256 + AssertFree1ElementMultiple: 256 WavefrontSize: 64 amdhsa.kernels: - .args: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index 6c7ddfe732e8..e5f5d6d89b68 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -57,11 +57,12 @@ BenchmarkProblems: { type: uint32, semantic: SplitK, padding: 12 }, { type: uint32, semantic: OutputBF16, padding: 12 } ] macrotile: [256, 256, 64] - padProblemSizeToTile: [true, true] # M, N threads: [256, 1, 1] grid: [TilesX, TilesY, One] - MatrixInstruction: - [16,16,32,1, 1, 8,8, 2,2] # 256 x 256 + - AssertFree0ElementMultiple: [256] + - AssertFree1ElementMultiple: [256] - PreloadKernArgs: [False] - DepthU: [64] - VectorWidthA: [-1] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml index c9792be7c01e..721d85174568 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -66,11 +66,12 @@ BenchmarkProblems: { type: uint32, semantic: StrideScaleA1, padding: 12 }, { type: uint32, semantic: SplitK, padding: 12 } ] macrotile: [256, 256, 256] - padProblemSizeToTile: [true, true] # M, N threads: [256, 1, 1] grid: [TilesX, TilesY, One] - MatrixInstruction: - [16, 16, 128, 1, 1, 8, 8, 2, 2] # 256 x 256 + - AssertFree0ElementMultiple: [256] + - AssertFree1ElementMultiple: [256] - PreloadKernArgs: [False] - DepthU: [256] - VectorWidthA: [-1] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py index 9011d9b8dad9..5bf15b316413 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -22,17 +22,25 @@ # ################################################################################ +import os from textwrap import dedent, indent import pytest +import Tensile from Tensile.AddCustomConfig import ( _parse_tensile_yaml, _read_asm_file, build_custom_config_yaml, inject_custom_config, ) -from Tensile.CustomKernels import getCustomKernelConfig, validateCustomKernelMetadata +from Tensile.Contractions import ProblemPredicate +from Tensile.Common.ValidParameters import checkParametersAreValid, validParameters +from Tensile.CustomKernels import ( + getCustomKernelConfig, + iterCustomKernelFiles, + validateCustomKernelMetadata, +) from Tensile.Toolchain.Assembly import validateCustomKernelMetadataAtBuild from Tensile.ValidateMetadata import validate_all @@ -190,3 +198,143 @@ def test_inject_custom_config_dry_run_does_not_modify_file(tmp_path, capsys): assert inject_custom_config(file_info, str(asm_path), config_yaml, dry_run=True) assert asm_path.read_text() == before assert "custom.config block that would be inserted" in capsys.readouterr().out + + +# --------------------------------------------------------------------------- # +# Custom-kernel predicates +# --------------------------------------------------------------------------- # + + +def test_valid_parameters_accept_size_multiple_256(): + checkParametersAreValid(("AssertFree0ElementMultiple", [256]), validParameters) + checkParametersAreValid(("AssertFree1ElementMultiple", [256]), validParameters) + checkParametersAreValid(("AssertSummationElementMultiple", [256]), validParameters) + + +def test_get_custom_kernel_config_preserves_size_multiple_predicate(tmp_path): + """AssertFree0/1ElementMultiple: 256 must survive custom.config loading + so AITER kernels can emit runtime size-multiple predicates.""" + write_kernel(tmp_path / "with_predicate.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + AssertFree0ElementMultiple: 256 + AssertFree1ElementMultiple: 256 + """) + + config = getCustomKernelConfig("with_predicate", {}, str(tmp_path)) + + assert config["AssertFree0ElementMultiple"] == 256 + assert config["AssertFree1ElementMultiple"] == 256 + + +def test_get_custom_kernel_config_rejects_bad_predicate_value(tmp_path): + write_kernel(tmp_path / "bad_predicate.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + AssertFree0ElementMultiple: -1 + """) + + with pytest.raises(Exception, match="AssertFree0ElementMultiple"): + getCustomKernelConfig("bad_predicate", {}, str(tmp_path)) + + +def test_problem_predicate_emits_size_multiple_for_assert_free0(): + pred = ProblemPredicate.FromOriginalKeyPair(("AssertFree0ElementMultiple", 256)) + + assert pred is not None + assert pred.tag == "Free0SizeMultiple" + assert pred.value == 256 + + +def test_problem_predicate_emits_size_multiple_for_assert_free1(): + pred = ProblemPredicate.FromOriginalKeyPair(("AssertFree1ElementMultiple", 256)) + + assert pred is not None + assert pred.tag == "Free1SizeMultiple" + assert pred.value == 256 + + +def test_problem_predicate_drops_value_one(): + """value==1 means "no constraint" and must not produce a runtime predicate.""" + assert ProblemPredicate.FromOriginalKeyPair(("AssertFree0ElementMultiple", 1)) is None + + +def _write_minimal_yaml_with_predicate(yaml_path, predicate_value): + yaml_path.write_text(dedent(f"""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - CustomKernel: + - name: predicated_kernel + args: [] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + - AssertFree0ElementMultiple: {predicate_value} + """)) + + +def test_parse_tensile_yaml_copies_single_valued_predicate(tmp_path): + yaml_path = tmp_path / "predicate.yaml" + _write_minimal_yaml_with_predicate(yaml_path, "[256]") + + config = _parse_tensile_yaml(str(yaml_path), "predicated_kernel") + + assert config["AssertFree0ElementMultiple"] == 256 + + +def test_parse_tensile_yaml_rejects_multi_valued_predicate(tmp_path): + yaml_path = tmp_path / "multi_predicate.yaml" + _write_minimal_yaml_with_predicate(yaml_path, "[128, 256]") + + with pytest.raises(RuntimeError, match="single-valued ForkParameter"): + _parse_tensile_yaml(str(yaml_path), "predicated_kernel") + + +def test_parse_tensile_yaml_rejects_scalar_predicate(tmp_path): + yaml_path = tmp_path / "scalar_predicate.yaml" + _write_minimal_yaml_with_predicate(yaml_path, "256") + + with pytest.raises(RuntimeError, match="single-valued ForkParameter"): + _parse_tensile_yaml(str(yaml_path), "predicated_kernel") + + +def test_parse_tensile_yaml_rejects_bad_predicate_value(tmp_path): + yaml_path = tmp_path / "bad_predicate.yaml" + _write_minimal_yaml_with_predicate(yaml_path, "[0]") + + with pytest.raises(Exception, match="Invalid parameter value: AssertFree0ElementMultiple"): + _parse_tensile_yaml(str(yaml_path), "predicated_kernel") + + +def test_build_custom_config_yaml_emits_predicate_after_mi(): + config = { + "ProblemType": {"OperationType": "GEMM"}, + "MatrixInstruction": [16, 16, 16, 1], + "CustomKernel": { + "args": [], + "macrotile": [256, 256, 64], + "threads": [256, 1, 1], + "grid": ["TilesX", "TilesY", "One"], + }, + "AssertFree0ElementMultiple": 256, + "AssertFree1ElementMultiple": 256, + "WavefrontSize": 64, + } + + rendered = build_custom_config_yaml(origin="test", config=config) + + mi_idx = rendered.index("MatrixInstruction:") + f0_idx = rendered.index("AssertFree0ElementMultiple:") + f1_idx = rendered.index("AssertFree1ElementMultiple:") + wf_idx = rendered.index("WavefrontSize:") + + assert mi_idx < f0_idx < wf_idx + assert mi_idx < f1_idx < wf_idx + assert "AssertFree0ElementMultiple: 256" in rendered + assert "AssertFree1ElementMultiple: 256" in rendered diff --git a/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp b/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp index d35bb4d83bc6..5a9816a1dfb1 100644 --- a/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp +++ b/projects/hipblaslt/tensilelite/client/include/ProgressListener.hpp @@ -95,9 +95,6 @@ namespace TensileLite size_t m_benchmarkRun = 0; bool m_runOnce = false; - - std::vector> m_originalProblemSizes; - size_t m_currentProblemIdx = 0; }; } // namespace Client } // namespace TensileLite diff --git a/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp b/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp index 48f9920891a0..c3a65cf33aba 100644 --- a/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp +++ b/projects/hipblaslt/tensilelite/client/include/ReferenceValidator.hpp @@ -151,9 +151,6 @@ namespace TensileLite bool m_printTensorAmaxD; bool m_printAny; - std::vector> m_originalProblemSizes; - size_t m_currentProblemIdx = 0; - int m_numBenchmarkRuns = 0; bool m_validatedSolution = false; diff --git a/projects/hipblaslt/tensilelite/client/main.cpp b/projects/hipblaslt/tensilelite/client/main.cpp index c1f4a91ff0d7..f104882a93b8 100644 --- a/projects/hipblaslt/tensilelite/client/main.cpp +++ b/projects/hipblaslt/tensilelite/client/main.cpp @@ -300,9 +300,6 @@ namespace TensileLite ("problem-size,p", vector_default_empty(), "Specify a problem size. Comma-separated list of " "sizes, in the order of the Einstein notation.") - ("original-problem-size", vector_default_empty(), "Original problem sizes before macrotile padding. " - "When present, validation uses these sizes to slice output.") - ("prob-sol-map", vector_default_empty(), "[probIdx, solIdx]") ("a-strides", vector_default_empty(), "Unspecified means default stride " @@ -856,7 +853,6 @@ namespace TensileLite fix_data_types(args); parse_arg_ints(args, "problem-size"); - parse_arg_ints(args, "original-problem-size"); parse_arg_ints(args, "a-strides"); parse_arg_ints(args, "b-strides"); parse_arg_ints(args, "c-strides"); diff --git a/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp b/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp index faed2f5b560f..9a5524c59aa5 100644 --- a/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp +++ b/projects/hipblaslt/tensilelite/client/src/ProgressListener.cpp @@ -39,13 +39,6 @@ namespace TensileLite ProgressListener::ProgressListener(po::variables_map const& args) : m_runOnce(args["selection-only"].as()) { - if(args.count("original-problem-size")) - { - auto const& parsed - = args["original-problem-size"].as>>(); - if(!parsed.empty()) - m_originalProblemSizes = parsed; - } } bool ProgressListener::needMoreBenchmarkRuns() const @@ -115,21 +108,7 @@ namespace TensileLite else if(auto gemmProblem = dynamic_cast(problem)) { writeReport(*gemmProblem); - // Report the original (unpadded) problem sizes when macrotile padding - // was applied, also override LDD/LDC to keep strides consistent. - if(m_currentProblemIdx < m_originalProblemSizes.size()) - { - auto const& origSizes = m_originalProblemSizes[m_currentProblemIdx]; - m_reporter->report(ResultKey::ProblemSizes, origSizes); - if(origSizes.size() >= 1 - && origSizes[0] != gemmProblem->d().sizes()[0]) - { - m_reporter->report(ResultKey::LDD, origSizes[0]); - m_reporter->report(ResultKey::LDC, origSizes[0]); - } - } - else - m_reporter->report(ResultKey::ProblemSizes, gemmProblem->problemSizes()); + m_reporter->report(ResultKey::ProblemSizes, gemmProblem->problemSizes()); } else { @@ -137,10 +116,7 @@ namespace TensileLite } } - void ProgressListener::postProblem() - { - m_currentProblemIdx++; - } + void ProgressListener::postProblem() {} void ProgressListener::preSolution(ContractionSolution* const solution) { diff --git a/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp b/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp index 3adbfe414a96..dacc965a0cb7 100644 --- a/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp +++ b/projects/hipblaslt/tensilelite/client/src/ReferenceValidator.cpp @@ -61,14 +61,6 @@ namespace TensileLite || m_printTensorRef || m_printTensorBias || m_printTensorAmaxD; m_enabled = m_elementsToValidate != 0 || m_printAny; - - if(args.count("original-problem-size")) - { - auto const& parsed - = args["original-problem-size"].as>>(); - if(!parsed.empty()) - m_originalProblemSizes = parsed; - } } bool ReferenceValidator::needMoreBenchmarkRuns() const @@ -493,41 +485,7 @@ namespace TensileLite throw std::runtime_error("Unrecognized output tensor."); } - // When macrotile padding was applied, the actual GPU tensor D is larger - // than the user-requested problem. Validate only the original (unpadded) - // region so that padding artefacts don't cause false mismatches. TensorDescriptor const* validationTensor = &tensor; - TensorDescriptor slicedTensor; - - if(static_cast(i) - == ContractionProblemGemm::TENSOR::D - && m_currentProblemIdx < m_originalProblemSizes.size()) - { - auto const& origSizes = m_originalProblemSizes[m_currentProblemIdx]; - if(origSizes.size() >= 2 - && (origSizes[0] != tensor.sizes()[0] - || origSizes[1] != tensor.sizes()[1])) - { - auto newSizes = tensor.sizes(); - newSizes[0] = origSizes[0]; - newSizes[1] = origSizes[1]; - slicedTensor = TensorDescriptor(tensor.getName().c_str(), - tensor.dataType(), - newSizes.begin(), - newSizes.end(), - tensor.strides().begin(), - tensor.strides().end()); - slicedTensor.setAsOutput(tensor.isOutput()); - validationTensor = &slicedTensor; - - if(m_elementsToValidate > 0 - && m_elementsToValidate - < slicedTensor.totalLogicalElements()) - validationStride = NextPrime( - slicedTensor.totalAllocatedElements() - / m_elementsToValidate); - } - } if(Debug::Instance().printTensorInfo()) std::cout << "Validating tensor " << validationTensor->getName() @@ -894,10 +852,7 @@ namespace TensileLite m_errorInSolution = false; } - void ReferenceValidator::postProblem() - { - m_currentProblemIdx++; - } + void ReferenceValidator::postProblem() {} void ReferenceValidator::finalizeReport() {} From d59d76f1d7b80b3f1aa0ed85c0c30f599d01018d Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Thu, 4 Jun 2026 21:48:39 +0000 Subject: [PATCH 32/58] Fix regressions on the yaml tests --- projects/hipblaslt/tensilelite/Tensile/Contractions.py | 2 +- projects/hipblaslt/tensilelite/src/ContractionSolution.cpp | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Contractions.py b/projects/hipblaslt/tensilelite/Tensile/Contractions.py index 976fcde93f64..b6788cc04cbc 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Contractions.py +++ b/projects/hipblaslt/tensilelite/Tensile/Contractions.py @@ -774,7 +774,7 @@ def convertSFCWGMListToHex(value): LocalSplitU = d["LocalSplitU"], DirectToLdsA = dtlA, DirectToLdsB = dtlB, - ExpertSchedulingMode = d['ExpertSchedulingMode'], + ExpertSchedulingMode = d.get('ExpertSchedulingMode', 0), clusterDim = d['ClusterDim'] ) @classmethod diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index ab2161a7e5ac..142c3f47c242 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1967,7 +1967,7 @@ namespace TensileLite break; case CustomArgSemantic::StrideScaleA0: { - size_t scaleStride = problem.boundSize(0) / problem.mxBlockA(); + size_t scaleStride = problem.mxsa().strides()[1]; rv.args.appendCustomType("StrideScaleA0", scaleStride, arg.type); break; } @@ -1981,7 +1981,7 @@ namespace TensileLite } case CustomArgSemantic::StrideScaleB0: { - size_t scaleStride = problem.boundSize(0) / problem.mxBlockB(); + size_t scaleStride = problem.mxsb().strides()[1]; rv.args.appendCustomType("StrideScaleB0", scaleStride, arg.type); break; } From a64b0477233d1b7584b62884b3fd2c9bd2ae4758 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Fri, 12 Jun 2026 14:46:39 -0500 Subject: [PATCH 33/58] Fix merge conflicts --- .../Tensile/Toolchain/Component.py | 27 ++++++++++++++++++- .../include/Tensile/ContractionSolution.hpp | 3 ++- .../tensilelite/src/ContractionSolution.cpp | 20 +++++++------- 3 files changed, 39 insertions(+), 11 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py index fd5a986f444a..1d2f3cc5d42e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py +++ b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py @@ -25,7 +25,7 @@ from os import name as os_name from os import environ from pathlib import Path -from re import search, IGNORECASE +from re import search, sub, IGNORECASE from shlex import split from subprocess import check_output, STDOUT, CalledProcessError, PIPE, run from typing import List @@ -159,6 +159,30 @@ def __init__(self, component_path: Path, co_version: str, debug: bool=False): "-c", ] + @staticmethod + def _retargetAssemblySource(targetGfx: str, srcPath: str): + path = Path(srcPath) + try: + src = path.read_text() + except UnicodeDecodeError: + return + + target = f"amdgcn-amd-amdhsa--{targetGfx}" + updated = sub( + r'(\.amdgcn_target\s+")amdgcn-amd-amdhsa--gfx[0-9a-fA-F]+([^"]*")', + rf'\1{target}\2', + src, + ) + updated = sub( + r'(amdhsa\.target:\s*)amdgcn-amd-amdhsa--gfx[0-9a-fA-F]+([^\s]*)', + rf'\1{target}\2', + updated, + ) + + if updated != src: + print2(f"Retargeting assembly source {path.name} to {targetGfx}") + path.write_text(updated) + def __call__(self, targetGfx: str, wavefrontSize: int, srcPath: str, destPath: str): """Assemble an assembly source file into an object file. Args: @@ -168,6 +192,7 @@ def __call__(self, targetGfx: str, wavefrontSize: int, srcPath: str, destPath: s srcPath: The path to the assembly source file. destPath: The destination path for the generated object file. """ + self._retargetAssemblySource(targetGfx, srcPath) args = self._default_args # Enable true16 syntax on targets that support +real-true16. if targetGfx in ("gfx1250", "gfx1201", "gfx1200", "gfx1100"): diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 4e5b50285003..ed424ab282e3 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -630,7 +630,8 @@ namespace TensileLite size_t autoStaggerUMapping, size_t autoStaggerU, size_t autoStaggerUStrideShift, - uint32_t autoGsuVal) const; + uint32_t autoGsuVal, + AdaptiveGemmNTAB ntab) const; // Common kernel related arguments (e.g. gemm_count, arg type, MT, GSU...) template diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 54babceba8ff..46cb436fbdf8 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1599,7 +1599,8 @@ namespace TensileLite size_t autoStaggerUMapping, size_t autoStaggerU, size_t autoStaggerUStrideShift, - uint32_t autoGsuVal) const + uint32_t autoGsuVal, + AdaptiveGemmNTAB ntab) const { uint32_t gsu = param.gsu() > 0 ? param.gsu() : autoGsuVal; bool gsuc = false; // initialized false @@ -1742,8 +1743,9 @@ namespace TensileLite size_t autoWGMXCCCHUNK, size_t autoStaggerUMapping, size_t autoStaggerU, - size_t autoStaggerUStrideShift, - uint32_t autoGsuVal) const + size_t autoStaggerUStrideShift, + uint32_t autoGsuVal, + AdaptiveGemmNTAB ntab) const { if constexpr(!Legacy) { @@ -1755,7 +1757,7 @@ namespace TensileLite uint32_t internalArg0; uint32_t internalArg1; - calculateInternalArgs(internalArg0, internalArg1, hardware, param, autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal); + calculateInternalArgs(internalArg0, internalArg1, hardware, param, autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); args.template append("internalArgs", internalArg0); @@ -1955,7 +1957,7 @@ namespace TensileLite dim = tiles.x * tiles.y * tiles.z * (gsu > 0 ? gsu : 1); break; case CustomGridSize::StreamKWithBatch: - dim = sk.grid * tiles.z; + dim = customKernel.generated ? sk.grid : sk.grid * tiles.z; break; case CustomGridSize::StreamKNoBatch: dim = sk.grid; @@ -1996,9 +1998,10 @@ namespace TensileLite auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] = calculateAutoWGM(problem, &hardware, sk.grid); auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); + AdaptiveGemmNTAB ntab = calculateAdaptiveGemmNTAB(problem, &hardware); uint32_t internalArg0 = 0; uint32_t internalArg1 = 0; - calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal); + calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); uint32_t debugPattern = 0xDB000001; bool appendedInternalArgs = false; @@ -2339,7 +2342,7 @@ namespace TensileLite &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, - autoStaggerUStrideShift, autoGsuVal); + autoStaggerUStrideShift, autoGsuVal, ntab); appendedInternalArgs = true; break; } @@ -4179,6 +4182,7 @@ namespace TensileLite gsu = 1; } const bool streamKDP = Debug::Instance().useStreamKDataParrallel(); + const bool forceDPOnly = sizeMapping.streamKForceDPOnly != 0; size_t tiles = 0; if (useLegacyWorkspaceLogic) tiles = problem.getNumTiles(sizeMapping, 1); @@ -4189,8 +4193,6 @@ namespace TensileLite tiles = dimTiles.x * dimTiles.y * dimTiles.z; } - const bool forceDPOnly = sizeMapping.streamKForceDPOnly != 0; - auto tiles = problem.getNumTiles(sizeMapping, 1); if(tiles > 0) // Grouped GEMM reports 0 tiles { auto reductionStrat = origami::reduction_t::tree; From 1e040eed229cb15c303ad831b9ef7a0ea6858d5b Mon Sep 17 00:00:00 2001 From: jinchen <49575973+jinchen62@users.noreply.github.com> Date: Mon, 15 Jun 2026 13:27:08 -0700 Subject: [PATCH 34/58] [hipblaslt][G-F-A] Demo calling triton fp4 kernel (#8336) Triton kernel is compiled from https://github.com/ROCm/aiter/tree/main/aiter/ops/triton/gemm/basic by the [script](https://gist.github.com/jinchen62/4316c7719b7a00bb901a965447c60586). Tensile log https://gist.github.com/jinchen62/7da14a7763e1e2b5594249d79715e777 --- .../Tensile/CustomKernels/README.md | 28 + ...kdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s | 9003 +++++++++++++++++ .../Tests/custom/custom_triton_f4.yaml | 82 + .../include/Tensile/ContractionSolution.hpp | 4 + .../tensilelite/src/ContractionSolution.cpp | 17 + 5 files changed, 9134 insertions(+) create mode 100644 projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md index 15b46a4cdb74..bc89b2df770e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/README.md @@ -21,10 +21,38 @@ external manifest. | `ck/` | External: Composable Kernel-sourced kernels. | | `rocroller/` | External: rocRoller-sourced kernels. | | `wave/` | External: Wave (handwritten) kernels. | +| `triton/` | External: Triton-compiled GEMM kernels. | Loader behavior is the same in every subdirectory; the split is purely organizational. +## Triton-sourced kernels + +The `triton/` subdirectory holds GEMM kernels compiled from Triton +(`@triton.jit`). Only the `.s` file and its test YAML are committed. +The Triton kernel `.py` comes from aiter and is a local input +to the generation step; it is not maintained in this repository. + +Triton-specific concerns for the compile step / YAML argument map: + +- **Static LDS**: Triton emits *dynamic* LDS (`group_segment_fixed_size: 0` + + `sharedMemBytes` at launch), but the custom-call path launches with + `sharedMemBytes = 0`. Rewrite the kernel's LDS into a static group segment + (size = Triton's `metadata.shared`) so the driver allocates it, exactly like + the other custom kernels. +- **Trailing scratch pointers**: Triton appends `global_scratch` and + `profile_scratch` kernarg pointers; when they are unused, represent their + 16-byte footprint as trailing `padding` on the last real Triton argument. +- **Layout**: for the `Cijk_Alik_Bljk` (TN) contraction both operands are + K-contiguous; pass packed-byte leading strides via `StrideA0Bytes` / + `StrideB0Bytes` for sub-byte (FP4) data. +- **Native aiter signatures**: use `ConstantOne` for fixed unit-stride Triton + arguments in the constrained custom-kernel layout. Use a named semantic such + as `StrideCK` when the value depends on split-K. For packed FP4 kernels that + take the summation size in bytes, use `SizeSumDiv2`. +- Strip the `.amdgcn_target` / `.amdhsa_code_object_version` directives from the + emitted assembly so Tensile's assembler flags drive target + COV. + ## What `custom.config` looks like Tensile-generated kernels (no `Source:` block) need only the runtime diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s new file mode 100644 index 000000000000..e32dd99566e1 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s @@ -0,0 +1,9003 @@ + .text + .globl _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 ; -- Begin function _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 + .p2align 8 + .type _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1,@function +_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1: ; @_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 +.Lfunc_begin0: + .cfi_sections .debug_frame + .cfi_startproc +; %bb.659: + .file 1 "/home/jincheye" "compile_native_aiter_afp4_recovered.py" + .loc 1 89 0 prologue_end ; compile_native_aiter_afp4_recovered.py:89:0 + s_load_dwordx2 s[2:3], s[0:1], 0x0 + s_load_dwordx8 s[4:11], s[0:1], 0x8 + s_load_dwordx4 s[12:15], s[0:1], 0x28 + s_waitcnt lgkmcnt(0) + s_branch .LBB0_0 + .loc 1 0 0 is_stmt 0 ; :0:0 +.Ltmp0: + .p2align 8 +; %bb.660: +.LBB0_0: + .cfi_escape 0x0f, 0x04, 0x30, 0x36, 0xe9, 0x02 ; CFA is 0 in private_wave aspace + .cfi_undefined 16 + ; implicit-def: $vgpr255 : SGPR spill to VGPR lane + s_mov_b32 s30, s13 + v_writelane_b32 v255, s6, 0 + s_mov_b32 s88, s12 + s_nop 0 + v_writelane_b32 v255, s7, 1 +.Ltmp1: + .file 2 "/home/jincheye/triton/python/triton/language" "standard.py" + .loc 2 43 13 is_stmt 1 ; standard.py:43:13 @[ compile_native_aiter_afp4_recovered.py:104:15 ] + s_add_i32 s6, s12, 0xff + .loc 2 43 12 is_stmt 0 ; standard.py:43:12 @[ compile_native_aiter_afp4_recovered.py:104:15 ] + s_ashr_i32 s7, s6, 31 + s_lshr_b32 s7, s7, 24 + s_add_i32 s6, s6, s7 + s_ashr_i32 s13, s6, 8 +.Ltmp2: + .loc 2 43 13 ; standard.py:43:13 @[ compile_native_aiter_afp4_recovered.py:104:42 ] + s_add_i32 s6, s30, 0xff + .loc 2 43 12 ; standard.py:43:12 @[ compile_native_aiter_afp4_recovered.py:104:42 ] + s_ashr_i32 s7, s6, 31 + s_lshr_b32 s7, s7, 24 + s_add_i32 s6, s6, s7 + s_ashr_i32 s17, s6, 8 +.Ltmp3: + .loc 1 104 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:104:15 + s_mul_i32 s6, s17, s13 +.Ltmp4: + .loc 1 67 21 ; compile_native_aiter_afp4_recovered.py:67:21 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_add_i32 s7, s6, 7 + .loc 1 67 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:67:20 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_ashr_i32 s12, s7, 31 + s_lshr_b32 s12, s12, 29 + s_add_i32 s7, s7, s12 + s_ashr_i32 s18, s7, 3 + .loc 1 68 17 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:68:17 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_ashr_i32 s7, s6, 31 + s_lshr_b32 s7, s7, 29 + s_add_i32 s7, s6, s7 + s_and_b32 s7, s7, -8 + s_sub_i32 s6, s6, s7 + .loc 1 69 17 ; compile_native_aiter_afp4_recovered.py:69:17 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_cmp_lg_u32 s6, 0 + s_cselect_b32 s6, s6, 8 + .loc 1 71 17 ; compile_native_aiter_afp4_recovered.py:71:17 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_ashr_i32 s7, s16, 31 + s_lshr_b32 s7, s7, 29 + s_add_i32 s20, s16, s7 + .loc 1 70 11 ; compile_native_aiter_afp4_recovered.py:70:11 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_and_b32 s7, s20, -8 + s_sub_i32 s16, s16, s7 + .loc 1 72 8 ; compile_native_aiter_afp4_recovered.py:72:8 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_cmp_ge_i32 s16, s6 +.Ltmp5: + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + v_readfirstlane_b32 s12, v0 +.Ltmp6: + .loc 1 72 8 ; compile_native_aiter_afp4_recovered.py:72:8 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_cbranch_scc0 .LBB0_2 +; %bb.1: + .loc 1 74 12 ; compile_native_aiter_afp4_recovered.py:74:12 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_mul_i32 s7, s6, s18 + .loc 1 74 40 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:74:40 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_sub_i32 s6, s16, s6 + .loc 1 74 60 ; compile_native_aiter_afp4_recovered.py:74:60 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_add_i32 s19, s18, -1 + .loc 1 74 39 ; compile_native_aiter_afp4_recovered.py:74:39 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_mul_i32 s6, s6, s19 + .loc 1 74 12 ; compile_native_aiter_afp4_recovered.py:74:12 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_add_i32 s19, s6, s7 + s_ashr_i32 s6, s20, 3 + s_cbranch_execz .LBB0_3 + s_branch .LBB0_4 +.LBB0_2: + ; implicit-def: $sgpr19 + .loc 1 0 12 ; compile_native_aiter_afp4_recovered.py:0:12 + s_ashr_i32 s6, s20, 3 +.LBB0_3: + .loc 1 73 16 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:73:16 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_mul_i32 s19, s18, s16 +.Ltmp7: +.LBB0_4: + .loc 1 79 24 ; compile_native_aiter_afp4_recovered.py:79:24 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + s_lshl_b32 s7, s17, 3 + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + s_abs_i32 s16, s7 + v_cvt_f32_u32_e32 v1, s16 +.Ltmp8: + .loc 1 0 0 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0 @[ compile_native_aiter_afp4_recovered.py:105:11 ] + s_add_i32 s6, s19, s6 +.Ltmp9: + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + s_sub_i32 s19, 0, s16 + .loc 1 83 28 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:83:28 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + s_abs_i32 s18, s6 + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_rcp_f32_e32 v1, v1 + s_xor_b32 s17, s6, s7 + s_ashr_i32 s17, s17, 31 +.Ltmp10: + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + v_and_b32_e32 v15, 31, v0 +.Ltmp11: + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_mul_f32_e32 v1, 0x4f7ffffe, v1 + v_cvt_u32_f32_e32 v1, v1 +.Ltmp12: + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + s_and_b32 s31, s12, 0x80 +.Ltmp13: + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + s_mov_b32 s85, 0 +.Ltmp14: + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + v_and_b32_e32 v16, 32, v0 +.Ltmp15: + .loc 1 80 16 ; compile_native_aiter_afp4_recovered.py:80:16 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_mul_lo_u32 v2, s19, v1 + v_mul_hi_u32 v2, v1, v2 + v_add_u32_e32 v1, v1, v2 + v_mul_hi_u32 v1, s18, v1 + v_mul_lo_u32 v2, v1, s16 + v_sub_u32_e32 v2, s18, v2 + v_add_u32_e32 v3, 1, v1 + v_subrev_u32_e32 v4, s16, v2 + v_cmp_le_u32_e32 vcc, s16, v2 + v_accvgpr_write_b32 a67, v15 + s_nop 0 + v_cndmask_b32_e32 v1, v1, v3, vcc + v_cndmask_b32_e32 v2, v2, v4, vcc + v_add_u32_e32 v3, 1, v1 + v_cmp_le_u32_e32 vcc, s16, v2 + s_nop 1 + v_cndmask_b32_e32 v1, v1, v3, vcc + v_xor_b32_e32 v1, s17, v1 + v_subrev_u32_e32 v1, s17, v1 + .loc 1 81 19 ; compile_native_aiter_afp4_recovered.py:81:19 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_lshlrev_b32_e32 v2, 3, v1 + .loc 1 82 24 ; compile_native_aiter_afp4_recovered.py:82:24 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_sub_u32_e32 v3, s13, v2 + .loc 1 82 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:82:20 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_min_i32_e32 v3, 8, v3 + .loc 1 83 28 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:83:28 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_sub_u32_e32 v4, 0, v3 + v_max_i32_e32 v4, v3, v4 + v_cvt_f32_u32_e32 v5, v4 + v_sub_u32_e32 v6, 0, v4 + s_ashr_i32 s13, s6, 31 + .loc 1 84 14 ; compile_native_aiter_afp4_recovered.py:84:14 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_mul_lo_u32 v1, v1, s7 + .loc 1 83 28 ; compile_native_aiter_afp4_recovered.py:83:28 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_rcp_f32_e32 v5, v5 + .loc 1 84 14 ; compile_native_aiter_afp4_recovered.py:84:14 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_sub_u32_e32 v1, s6, v1 + .loc 1 84 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:84:13 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_xor_b32_e32 v3, v1, v3 + v_ashrrev_i32_e32 v3, 31, v3 + .loc 1 83 28 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:83:28 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_mul_f32_e32 v5, 0x4f7ffffe, v5 + v_cvt_u32_f32_e32 v5, v5 +.Ltmp16: + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + s_and_b32 s7, s12, 64 + s_lshr_b32 s33, s7, 1 + .loc 1 122 11 ; compile_native_aiter_afp4_recovered.py:122:11 + s_cmp_lt_i32 s14, 1 +.Ltmp17: + .loc 1 83 28 ; compile_native_aiter_afp4_recovered.py:83:28 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_mul_lo_u32 v6, v6, v5 + v_mul_hi_u32 v6, v5, v6 + v_add_u32_e32 v5, v5, v6 + v_mul_hi_u32 v6, s18, v5 + v_mul_lo_u32 v6, v6, v4 + v_sub_u32_e32 v6, s18, v6 + v_sub_u32_e32 v7, v6, v4 + v_cmp_ge_u32_e32 vcc, v6, v4 + s_nop 1 + v_cndmask_b32_e32 v6, v6, v7, vcc + v_sub_u32_e32 v7, v6, v4 + v_cmp_ge_u32_e32 vcc, v6, v4 + s_nop 1 + v_cndmask_b32_e32 v6, v6, v7, vcc + v_xor_b32_e32 v6, s13, v6 + v_subrev_u32_e32 v6, s13, v6 + .loc 1 83 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:83:13 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_add_u32_e32 v2, v2, v6 + .loc 1 84 13 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:84:13 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_sub_u32_e32 v6, 0, v1 + v_max_i32_e32 v1, v1, v6 + v_mul_hi_u32 v5, v1, v5 + v_mul_lo_u32 v6, v5, v4 + v_sub_u32_e32 v1, v1, v6 + v_add_u32_e32 v6, 1, v5 + v_sub_u32_e32 v7, v1, v4 + v_cmp_ge_u32_e32 vcc, v1, v4 +.Ltmp18: + .loc 1 111 16 ; compile_native_aiter_afp4_recovered.py:111:16 + v_lshlrev_b32_e32 v12, 8, v2 + v_ashrrev_i32_e32 v11, 31, v12 +.Ltmp19: + .loc 1 84 13 ; compile_native_aiter_afp4_recovered.py:84:13 @[ compile_native_aiter_afp4_recovered.py:108:20 ] + v_cndmask_b32_e32 v5, v5, v6, vcc + v_cndmask_b32_e32 v1, v1, v7, vcc + v_add_u32_e32 v6, 1, v5 + v_cmp_ge_u32_e32 vcc, v1, v4 + v_accvgpr_write_b32 a63, v11 + v_accvgpr_write_b32 a64, v12 + v_cndmask_b32_e32 v1, v5, v6, vcc + v_xor_b32_e32 v1, v1, v3 + v_sub_u32_e32 v1, v1, v3 +.Ltmp20: + .loc 1 112 16 ; compile_native_aiter_afp4_recovered.py:112:16 + v_lshlrev_b32_e32 v14, 8, v1 + v_ashrrev_i32_e32 v13, 31, v14 + v_accvgpr_write_b32 a65, v13 + .loc 1 122 11 ; compile_native_aiter_afp4_recovered.py:122:11 + s_cbranch_scc1 .LBB0_145 +; %bb.5: ; %.lr.ph + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + s_abs_i32 s24, s30 + v_cvt_f32_u32_e32 v2, s24 + .loc 1 124 13 ; compile_native_aiter_afp4_recovered.py:124:13 + s_bfe_i32 s13, s14, 0x1001e + s_lshl_b32 s6, s14, 1 + s_lshr_b32 s13, s13, 27 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_rcp_f32_e32 v2, v2 + .loc 1 124 13 ; compile_native_aiter_afp4_recovered.py:124:13 + s_add_i32 s6, s6, s13 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_b32 s13, s12, 0xc0 + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + v_and_b32_e32 v4, 63, v0 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_mul_f32_e32 v2, 0x4f7ffffe, v2 + v_cvt_u32_f32_e32 v2, v2 + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + v_or_b32_e32 v1, s13, v4 + v_lshrrev_b32_e32 v8, 1, v1 + v_or_b32_e32 v5, 0x80, v8 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + s_sub_i32 s21, 0, s24 + .loc 1 112 16 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:112:16 + v_or_b32_e32 v3, v14, v5 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_mul_lo_u32 v6, s21, v2 + v_add_u32_e32 v3, v3, v13 + v_mul_hi_u32 v6, v2, v6 + v_xor_b32_e32 v3, v3, v13 + v_add_u32_e32 v9, v2, v6 + v_mul_hi_u32 v2, v3, v9 + v_mul_lo_u32 v2, v2, s24 + v_sub_u32_e32 v2, v3, v2 + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + s_load_dwordx2 s[82:83], s[0:1], 0x38 + s_load_dword s23, s[0:1], 0x40 + s_load_dwordx4 s[16:19], s[0:1], 0x50 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + .loc 1 117 67 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:117:67 + v_and_b32_e32 v22, 1, v0 + .loc 1 118 67 ; compile_native_aiter_afp4_recovered.py:118:67 + s_waitcnt lgkmcnt(0) + v_mul_lo_u32 v6, s19, v22 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v13 + v_sub_u32_e32 v2, v2, v13 + .loc 1 118 35 ; compile_native_aiter_afp4_recovered.py:118:35 + v_mul_lo_u32 v2, v2, s18 + .loc 1 118 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:118:20 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_ashrrev_i32_e32 v7, 31, v6 + v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7] + v_accvgpr_write_b32 a71, v3 + v_accvgpr_write_b32 a70, v2 + .loc 1 112 16 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:112:16 + v_or_b32_e32 v2, v14, v8 + .loc 1 112 15 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:112:15 + v_add_u32_e32 v2, v2, v13 + v_xor_b32_e32 v2, v2, v13 + v_mul_hi_u32 v3, v2, v9 + v_mul_lo_u32 v3, v3, s24 + v_sub_u32_e32 v2, v2, v3 + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + s_abs_i32 s21, s88 + v_cvt_f32_u32_e32 v10, s21 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_rcp_f32_e32 v10, v10 + .loc 1 124 13 ; compile_native_aiter_afp4_recovered.py:124:13 + s_ashr_i32 s84, s6, 5 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v13 + v_sub_u32_e32 v2, v2, v13 + .loc 1 118 35 ; compile_native_aiter_afp4_recovered.py:118:35 + v_mul_lo_u32 v2, v2, s18 + .loc 1 118 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:118:20 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[10:11], 0, v[2:3] + v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7] + v_accvgpr_write_b32 a79, v3 + v_accvgpr_write_b32 a78, v2 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_f32_e32 v3, 0x4f7ffffe, v10 + v_cvt_u32_f32_e32 v3, v3 + s_sub_i32 s10, 0, s21 + .loc 1 111 16 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:111:16 + v_or_b32_e32 v2, v12, v5 + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v2, v2, v11 + v_mul_lo_u32 v5, s10, v3 + v_mul_hi_u32 v5, v3, v5 + v_xor_b32_e32 v2, v2, v11 + v_add_u32_e32 v5, v3, v5 + v_mul_hi_u32 v3, v2, v5 + v_mul_lo_u32 v3, v3, s21 + v_sub_u32_e32 v2, v2, v3 + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + .loc 1 117 67 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:117:67 + v_mul_lo_u32 v6, s17, v22 + .loc 1 117 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:117:20 + v_ashrrev_i32_e32 v7, 31, v6 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + .loc 1 139 25 ; compile_native_aiter_afp4_recovered.py:139:25 + s_lshl_b32 s6, s19, 1 + .loc 1 138 25 ; compile_native_aiter_afp4_recovered.py:138:25 + s_lshl_b32 s12, s17, 1 + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v11 + v_sub_u32_e32 v2, v2, v11 + .loc 1 117 35 ; compile_native_aiter_afp4_recovered.py:117:35 + v_mul_lo_u32 v2, v2, s16 + .loc 1 117 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:117:20 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[8:9], 0, v[2:3] + v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7] + v_accvgpr_write_b32 a73, v3 + v_accvgpr_write_b32 a72, v2 + .loc 1 111 16 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:16 + v_or_b32_e32 v2, v12, v8 + .loc 1 111 15 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v2, v2, v11 + v_xor_b32_e32 v2, v2, v11 + v_mul_hi_u32 v3, v2, v5 + v_mul_lo_u32 v3, v3, s21 + v_sub_u32_e32 v2, v2, v3 + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + .loc 1 137 19 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:137:19 + s_lshl_b32 s20, s83, 5 + .loc 1 136 19 ; compile_native_aiter_afp4_recovered.py:136:19 + s_lshl_b32 s22, s82, 5 + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + v_lshlrev_b32_e32 v20, 3, v0 + v_lshlrev_b32_e32 v19, 7, v0 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v11 + v_sub_u32_e32 v2, v2, v11 + .loc 1 117 35 ; compile_native_aiter_afp4_recovered.py:117:35 + v_mul_lo_u32 v2, v2, s16 + .loc 1 117 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:117:20 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[2:3], s[8:9], 0, v[2:3] + v_lshl_add_u64 v[2:3], v[2:3], 0, v[6:7] + v_accvgpr_write_b32 a75, v3 + v_accvgpr_write_b32 a74, v2 + .loc 1 112 16 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:112:16 + v_or_b32_e32 v2, v14, v1 + .loc 1 112 15 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:112:15 + v_add_u32_e32 v2, v2, v13 + v_xor_b32_e32 v2, v2, v13 + v_mul_hi_u32 v3, v2, v9 + v_mul_lo_u32 v3, v3, s24 + v_sub_u32_e32 v2, v2, v3 + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + .loc 1 116 22 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s8, s83, 31 + .loc 1 116 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s9, s8, 31 + .loc 1 112 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:112:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s24, v2 + v_cmp_le_u32_e32 vcc, s24, v2 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_add_u32 s10, s4, s8 + s_addc_u32 s11, s5, s9 + .loc 1 112 15 ; compile_native_aiter_afp4_recovered.py:112:15 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v13 + v_sub_u32_e32 v2, v2, v13 + .loc 1 116 52 ; compile_native_aiter_afp4_recovered.py:116:52 + v_mul_lo_u32 v2, v2, s23 + .loc 1 116 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:116:14 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[242:243], s[10:11], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s10, s83, 30 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s11, s10, 31 + s_add_u32 s16, s4, s10 + s_addc_u32 s17, s5, s11 + v_lshl_add_u64 v[244:245], s[16:17], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s16, s83, 29 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s17, s16, 31 + s_add_u32 s18, s4, s16 + s_addc_u32 s19, s5, s17 + v_lshl_add_u64 v[6:7], s[18:19], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s18, s83, 28 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s19, s18, 31 + s_add_u32 s24, s4, s18 + v_accvgpr_write_b32 a61, v7 + s_addc_u32 s25, s5, s19 + v_accvgpr_write_b32 a60, v6 + v_lshl_add_u64 v[6:7], s[24:25], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s24, s83, 27 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s25, s24, 31 + s_add_u32 s26, s4, s24 + v_accvgpr_write_b32 a119, v7 + s_addc_u32 s27, s5, s25 + v_accvgpr_write_b32 a118, v6 + v_lshl_add_u64 v[6:7], s[26:27], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s26, s83, 26 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s27, s26, 31 + s_add_u32 s28, s4, s26 + v_accvgpr_write_b32 a59, v7 + s_addc_u32 s29, s5, s27 + v_accvgpr_write_b32 a58, v6 + v_lshl_add_u64 v[6:7], s[28:29], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s28, s83, 25 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s29, s28, 31 + s_add_u32 s34, s4, s28 + v_accvgpr_write_b32 a121, v7 + s_addc_u32 s35, s5, s29 + v_accvgpr_write_b32 a120, v6 + v_lshl_add_u64 v[6:7], s[34:35], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s34, s83, 24 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s35, s34, 31 + s_add_u32 s36, s4, s34 + v_accvgpr_write_b32 a57, v7 + s_addc_u32 s37, s5, s35 + v_accvgpr_write_b32 a56, v6 + v_lshl_add_u64 v[6:7], s[36:37], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s36, s83, 23 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s37, s36, 31 + s_add_u32 s38, s4, s36 + v_accvgpr_write_b32 a123, v7 + s_addc_u32 s39, s5, s37 + v_accvgpr_write_b32 a122, v6 + v_lshl_add_u64 v[6:7], s[38:39], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s38, s83, 22 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s39, s38, 31 + s_add_u32 s40, s4, s38 + v_accvgpr_write_b32 a55, v7 + s_addc_u32 s41, s5, s39 + v_accvgpr_write_b32 a54, v6 + v_lshl_add_u64 v[6:7], s[40:41], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s40, s83, 21 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s41, s40, 31 + s_add_u32 s42, s4, s40 + v_accvgpr_write_b32 a125, v7 + s_addc_u32 s43, s5, s41 + v_accvgpr_write_b32 a124, v6 + v_lshl_add_u64 v[6:7], s[42:43], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s42, s83, 20 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s43, s42, 31 + s_add_u32 s44, s4, s42 + v_accvgpr_write_b32 a53, v7 + s_addc_u32 s45, s5, s43 + v_accvgpr_write_b32 a52, v6 + v_lshl_add_u64 v[6:7], s[44:45], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s44, s83, 19 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s45, s44, 31 + s_add_u32 s46, s4, s44 + v_accvgpr_write_b32 a127, v7 + s_addc_u32 s47, s5, s45 + v_accvgpr_write_b32 a126, v6 + v_lshl_add_u64 v[6:7], s[46:47], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s46, s83, 18 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s47, s46, 31 + s_add_u32 s48, s4, s46 + v_accvgpr_write_b32 a51, v7 + s_addc_u32 s49, s5, s47 + v_accvgpr_write_b32 a50, v6 + v_lshl_add_u64 v[6:7], s[48:49], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s48, s83, 17 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s49, s48, 31 + s_add_u32 s50, s4, s48 + v_accvgpr_write_b32 a129, v7 + s_addc_u32 s51, s5, s49 + v_accvgpr_write_b32 a128, v6 + v_lshl_add_u64 v[6:7], s[50:51], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_lshl_b32 s50, s83, 4 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s51, s50, 31 + s_add_u32 s52, s4, s50 + v_accvgpr_write_b32 a49, v7 + s_addc_u32 s53, s5, s51 + v_accvgpr_write_b32 a48, v6 + v_lshl_add_u64 v[6:7], s[52:53], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s52, s83, 15 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s53, s52, 31 + s_add_u32 s54, s4, s52 + v_accvgpr_write_b32 a191, v7 + s_addc_u32 s55, s5, s53 + v_accvgpr_write_b32 a190, v6 + v_lshl_add_u64 v[6:7], s[54:55], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s54, s83, 14 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s55, s54, 31 + s_add_u32 s56, s4, s54 + v_accvgpr_write_b32 a47, v7 + s_addc_u32 s57, s5, s55 + v_accvgpr_write_b32 a46, v6 + v_lshl_add_u64 v[6:7], s[56:57], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s56, s83, 13 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s57, s56, 31 + s_add_u32 s58, s4, s56 + v_accvgpr_write_b32 a193, v7 + s_addc_u32 s59, s5, s57 + v_accvgpr_write_b32 a192, v6 + v_lshl_add_u64 v[6:7], s[58:59], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s58, s83, 12 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s59, s58, 31 + s_add_u32 s60, s4, s58 + v_accvgpr_write_b32 a45, v7 + s_addc_u32 s61, s5, s59 + v_accvgpr_write_b32 a44, v6 + v_lshl_add_u64 v[6:7], s[60:61], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s60, s83, 11 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s61, s60, 31 + s_add_u32 s62, s4, s60 + v_accvgpr_write_b32 a195, v7 + s_addc_u32 s63, s5, s61 + v_accvgpr_write_b32 a194, v6 + v_lshl_add_u64 v[6:7], s[62:63], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s62, s83, 10 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s63, s62, 31 + s_add_u32 s64, s4, s62 + v_accvgpr_write_b32 a43, v7 + s_addc_u32 s65, s5, s63 + v_accvgpr_write_b32 a42, v6 + v_lshl_add_u64 v[6:7], s[64:65], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s64, s83, 9 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s65, s64, 31 + s_add_u32 s66, s4, s64 + v_accvgpr_write_b32 a197, v7 + s_addc_u32 s67, s5, s65 + v_accvgpr_write_b32 a196, v6 + v_lshl_add_u64 v[6:7], s[66:67], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_lshl_b32 s66, s83, 3 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s67, s66, 31 + s_add_u32 s68, s4, s66 + v_accvgpr_write_b32 a41, v7 + s_addc_u32 s69, s5, s67 + v_accvgpr_write_b32 a40, v6 + v_lshl_add_u64 v[6:7], s[68:69], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s68, s83, 7 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s69, s68, 31 + s_add_u32 s70, s4, s68 + v_accvgpr_write_b32 a199, v7 + s_addc_u32 s71, s5, s69 + v_accvgpr_write_b32 a198, v6 + v_lshl_add_u64 v[6:7], s[70:71], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s70, s83, 6 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s71, s70, 31 + s_add_u32 s72, s4, s70 + v_accvgpr_write_b32 a39, v7 + s_addc_u32 s73, s5, s71 + v_accvgpr_write_b32 a38, v6 + v_lshl_add_u64 v[6:7], s[72:73], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s72, s83, 5 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s73, s72, 31 + s_add_u32 s74, s4, s72 + v_accvgpr_write_b32 a201, v7 + s_addc_u32 s75, s5, s73 + v_accvgpr_write_b32 a200, v6 + v_lshl_add_u64 v[6:7], s[74:75], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_lshl_b32 s74, s83, 2 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s75, s74, 31 + s_add_u32 s76, s4, s74 + v_accvgpr_write_b32 a37, v7 + s_addc_u32 s77, s5, s75 + v_accvgpr_write_b32 a36, v6 + v_lshl_add_u64 v[6:7], s[76:77], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_mul_i32 s76, s83, 3 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s77, s76, 31 + s_add_u32 s78, s4, s76 + v_accvgpr_write_b32 a203, v7 + s_addc_u32 s79, s5, s77 + v_accvgpr_write_b32 a202, v6 + v_lshl_add_u64 v[6:7], s[78:79], 0, v[2:3] + .loc 1 116 22 ; compile_native_aiter_afp4_recovered.py:116:22 + s_lshl_b32 s78, s83, 1 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_ashr_i32 s79, s78, 31 + s_add_u32 s80, s4, s78 + v_accvgpr_write_b32 a35, v7 + s_addc_u32 s81, s5, s79 + v_accvgpr_write_b32 a34, v6 + v_lshl_add_u64 v[6:7], s[80:81], 0, v[2:3] + s_ashr_i32 s81, s83, 31 + s_add_u32 s86, s4, s83 + v_accvgpr_write_b32 a205, v7 + s_addc_u32 s87, s5, s81 + v_accvgpr_write_b32 a204, v6 + v_lshl_add_u64 v[6:7], s[86:87], 0, v[2:3] + v_lshl_add_u64 v[252:253], s[4:5], 0, v[2:3] + .loc 1 111 39 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:39 + v_lshrrev_b32_e32 v2, 5, v1 + v_accvgpr_write_b32 a33, v7 + v_or_b32_e32 v2, v12, v2 + v_accvgpr_write_b32 a32, v6 + .loc 1 111 15 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v6, v2, v11 + v_add_u32_e32 v2, 0xf8, v6 + v_xor_b32_e32 v2, v2, v11 + v_mul_hi_u32 v3, v2, v5 + v_mul_lo_u32 v3, v3, s21 + v_sub_u32_e32 v2, v2, v3 + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + v_add_u32_e32 v7, 0xf0, v6 + v_xor_b32_e32 v7, v7, v11 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_subrev_u32_e32 v3, s21, v2 + v_cmp_le_u32_e32 vcc, s21, v2 + v_and_b32_e32 v20, 0x78, v20 + v_and_b32_e32 v21, 16, v0 + v_cndmask_b32_e32 v2, v2, v3, vcc + v_xor_b32_e32 v2, v2, v11 + v_sub_u32_e32 v2, v2, v11 + .loc 1 115 22 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v2, v2, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[2:3] + .loc 1 115 53 ; compile_native_aiter_afp4_recovered.py:115:53 + v_mul_lo_u32 v2, s82, v15 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v3, 31, v2 + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + v_accvgpr_write_b32 a77, v9 + v_accvgpr_write_b32 a76, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_add_u32_e32 v254, 0, v1 + v_mov_b32_e32 v10, 0x770 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_bitop3_b32 v10, s13, v10, v4 bitop3:0x36 + v_mov_b32_e32 v12, 0x990 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xe8, v6 + v_accvgpr_write_b32 a81, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a80, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_bitop3_b32 v12, s13, v12, v4 bitop3:0x36 + v_mov_b32_e32 v13, 0xaa0 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_accvgpr_write_b32 a66, v14 + v_bitop3_b32 v13, s13, v13, v4 bitop3:0x36 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xe0, v6 + v_accvgpr_write_b32 a83, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a82, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v14, 0xbb0 + v_bitop3_b32 v14, s13, v14, v4 bitop3:0x36 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v15, 0xcc0 + v_accvgpr_write_b32 a68, v16 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xd8, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[192:193], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_bitop3_b32 v15, s13, v15, v4 bitop3:0x36 + v_mov_b32_e32 v17, 0xee0 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_bitop3_b32 v17, s13, v17, v4 bitop3:0x36 + v_mov_b32_e32 v18, 0xff0 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xd0, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[194:195], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_bitop3_b32 v18, s13, v18, v4 bitop3:0x36 + s_lshr_b32 s5, s31, 6 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v208, 0 + .loc 1 116 14 ; compile_native_aiter_afp4_recovered.py:116:14 + s_mov_b32 s80, s83 + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xc8, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[196:197], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_accvgpr_write_b32 a69, v22 + s_ashr_i32 s23, s22, 31 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + s_movk_i32 s4, 0xff + v_mov_b32_e32 v209, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xc0, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[198:199], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v210, v208 + v_mov_b32_e32 v211, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v212, v208 + v_mov_b32_e32 v213, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xb8, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[200:201], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v214, v208 + v_mov_b32_e32 v215, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v216, v208 + v_mov_b32_e32 v217, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xb0, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[202:203], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v218, v208 + v_mov_b32_e32 v219, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v220, v208 + v_mov_b32_e32 v221, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xa8, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[204:205], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v222, v208 + v_mov_b32_e32 v223, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v23, v208 + v_mov_b32_e32 v24, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0xa0, v6 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_xor_b32_e32 v7, v7, v11 + .loc 1 115 14 ; compile_native_aiter_afp4_recovered.py:115:14 + v_lshl_add_u64 v[206:207], v[8:9], 0, v[2:3] + .loc 1 111 15 ; compile_native_aiter_afp4_recovered.py:111:15 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v25, v208 + v_mov_b32_e32 v26, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v27, v208 + v_mov_b32_e32 v28, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x98, v6 + v_accvgpr_write_b32 a131, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a130, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v29, v208 + v_mov_b32_e32 v30, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v31, v208 + v_mov_b32_e32 v224, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x90, v6 + v_accvgpr_write_b32 a133, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a132, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v225, v208 + v_mov_b32_e32 v226, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v227, v208 + v_mov_b32_e32 v228, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x88, v6 + v_accvgpr_write_b32 a135, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a134, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v229, v208 + v_mov_b32_e32 v230, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v231, v208 + v_mov_b32_e32 v232, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x80, v6 + v_accvgpr_write_b32 a137, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a136, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v233, v208 + v_mov_b32_e32 v234, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v235, v208 + v_mov_b32_e32 v236, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x78, v6 + v_accvgpr_write_b32 a139, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a138, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v237, v208 + v_mov_b32_e32 v238, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v239, v208 + v_mov_b32_e32 v176, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x70, v6 + v_accvgpr_write_b32 a141, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a140, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v177, v208 + v_mov_b32_e32 v178, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v179, v208 + v_mov_b32_e32 v180, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x68, v6 + v_accvgpr_write_b32 a143, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a142, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v181, v208 + v_mov_b32_e32 v182, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v183, v208 + v_mov_b32_e32 v184, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x60, v6 + v_accvgpr_write_b32 a145, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a144, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v185, v208 + v_mov_b32_e32 v186, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v187, v208 + v_mov_b32_e32 v188, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x58, v6 + v_accvgpr_write_b32 a147, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a146, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v189, v208 + v_mov_b32_e32 v190, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v191, v208 + v_mov_b32_e32 v160, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x50, v6 + v_accvgpr_write_b32 a149, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a148, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v161, v208 + v_mov_b32_e32 v162, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v163, v208 + v_mov_b32_e32 v164, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 0x48, v6 + v_accvgpr_write_b32 a151, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a150, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v165, v208 + v_mov_b32_e32 v166, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v167, v208 + v_mov_b32_e32 v168, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 64, v6 + v_accvgpr_write_b32 a153, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a152, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v169, v208 + v_mov_b32_e32 v170, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v171, v208 + v_mov_b32_e32 v172, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 56, v6 + v_accvgpr_write_b32 a155, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a154, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v173, v208 + v_mov_b32_e32 v174, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v175, v208 + v_mov_b32_e32 v144, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 48, v6 + v_accvgpr_write_b32 a157, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a156, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v145, v208 + v_mov_b32_e32 v146, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v147, v208 + v_mov_b32_e32 v148, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 40, v6 + v_accvgpr_write_b32 a159, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a158, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v149, v208 + v_mov_b32_e32 v150, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v151, v208 + v_mov_b32_e32 v152, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 32, v6 + v_accvgpr_write_b32 a161, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a160, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v153, v208 + v_mov_b32_e32 v154, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v155, v208 + v_mov_b32_e32 v156, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 24, v6 + v_accvgpr_write_b32 a163, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a162, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v157, v208 + v_mov_b32_e32 v158, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v159, v208 + v_mov_b32_e32 v128, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 16, v6 + v_accvgpr_write_b32 a167, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a166, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v129, v208 + v_mov_b32_e32 v130, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mov_b32_e32 v131, v208 + v_mov_b32_e32 v132, v208 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[8:9], v[8:9], 0, v[2:3] + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_add_u32_e32 v7, 8, v6 + v_accvgpr_write_b32 a169, v9 + v_xor_b32_e32 v7, v7, v11 + v_accvgpr_write_b32 a168, v8 + v_mul_hi_u32 v8, v7, v5 + v_mul_lo_u32 v8, v8, s21 + v_sub_u32_e32 v7, v7, v8 + v_xor_b32_e32 v6, v6, v11 + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_mul_hi_u32 v5, v6, v5 + v_mul_lo_u32 v5, v5, s21 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_subrev_u32_e32 v8, s21, v7 + v_cmp_le_u32_e32 vcc, s21, v7 + v_sub_u32_e32 v5, v6, v5 + v_subrev_u32_e32 v6, s21, v5 + v_cndmask_b32_e32 v7, v7, v8, vcc + v_cmp_le_u32_e32 vcc, s21, v5 + v_xor_b32_e32 v7, v7, v11 + v_sub_u32_e32 v7, v7, v11 + v_cndmask_b32_e32 v5, v5, v6, vcc + v_subrev_u32_e32 v6, s21, v5 + v_cmp_le_u32_e32 vcc, s21, v5 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v8, v7, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v9, 31, v8 + .loc 1 111 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:111:15 + v_cndmask_b32_e32 v5, v5, v6, vcc + v_xor_b32_e32 v5, v5, v11 + v_sub_u32_e32 v5, v5, v11 + .loc 1 115 22 ; compile_native_aiter_afp4_recovered.py:115:22 + v_mul_lo_u32 v6, v5, s15 + .loc 1 115 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:115:14 + v_ashrrev_i32_e32 v7, 31, v6 + v_lshl_add_u64 v[8:9], s[2:3], 0, v[8:9] + v_lshl_add_u64 v[6:7], s[2:3], 0, v[6:7] + v_lshl_add_u64 v[248:249], v[8:9], 0, v[2:3] + v_lshl_add_u64 v[250:251], v[6:7], 0, v[2:3] + v_lshlrev_b32_e32 v3, 5, v0 + v_bfe_i32 v5, v0, 3, 1 + s_movk_i32 s3, 0x1700 + v_lshlrev_b32_e32 v0, 1, v0 + v_and_b32_e32 v3, 0x2e0, v3 + v_and_b32_e32 v5, 0x110, v5 + v_lshrrev_b32_e32 v6, 1, v16 + v_and_or_b32 v19, v19, s3, v20 + v_and_b32_e32 v0, 0x7c, v0 + v_bitop3_b32 v3, v5, v6, v3 bitop3:0x36 + s_lshl3_add_u32 s2, s31, 0 + v_mov_b32_e32 v5, 0x220 + v_bitop3_b32 v19, s33, v19, v21 bitop3:0x36 + v_lshlrev_b32_e32 v21, 7, v22 + s_lshl_b32 s3, s7, 2 + v_add_u32_e32 v0, 0, v0 + v_bitop3_b32 v5, s13, v5, v4 bitop3:0x36 + v_mov_b32_e32 v6, 0x330 + v_add3_u32 v0, v0, v21, s3 + v_lshlrev_b32_e32 v21, 2, v1 + v_add_u32_e32 v1, s2, v3 + v_bitop3_b32 v6, s13, v6, v4 bitop3:0x36 + v_mov_b32_e32 v7, 0x440 + v_accvgpr_write_b32 a170, v1 + v_add_u32_e32 v1, 0, v5 + v_bitop3_b32 v7, s13, v7, v4 bitop3:0x36 + v_mov_b32_e32 v8, 0x550 + v_accvgpr_write_b32 a171, v1 + v_add_u32_e32 v1, 0, v6 + v_bitop3_b32 v8, s13, v8, v4 bitop3:0x36 + v_mov_b32_e32 v9, 0x660 + v_accvgpr_write_b32 a172, v1 + v_add_u32_e32 v1, 0, v7 + v_bitop3_b32 v9, s13, v9, v4 bitop3:0x36 + v_accvgpr_write_b32 a173, v1 + v_add_u32_e32 v1, 0, v8 + v_mov_b32_e32 v11, 0x880 + v_accvgpr_write_b32 a174, v1 + v_add_u32_e32 v1, 0, v9 + v_bitop3_b32 v11, s13, v11, v4 bitop3:0x36 + v_accvgpr_write_b32 a175, v1 + v_add_u32_e32 v1, 0, v10 + v_accvgpr_write_b32 a176, v1 + v_add_u32_e32 v1, 0, v11 + v_accvgpr_write_b32 a177, v1 + v_add_u32_e32 v1, 0, v12 + v_accvgpr_write_b32 a178, v1 + v_add_u32_e32 v1, 0, v13 + v_mov_b32_e32 v16, 0xdd0 + v_accvgpr_write_b32 a179, v1 + v_add_u32_e32 v1, 0, v14 + v_bitop3_b32 v16, s13, v16, v4 bitop3:0x36 + v_accvgpr_write_b32 a180, v1 + v_add_u32_e32 v1, 0, v15 + v_accvgpr_write_b32 a181, v1 + v_add_u32_e32 v1, 0, v16 + v_mov_b32_e32 v2, 0x110 + v_accvgpr_write_b32 a182, v1 + v_add_u32_e32 v1, 0, v17 + v_bitop3_b32 v2, s13, v2, v4 bitop3:0x36 + s_lshl_b32 s3, s31, 1 + v_lshl_add_u32 v4, v4, 2, 0 + v_accvgpr_write_b32 a183, v1 + v_add_u32_e32 v1, 0, v18 + v_add_u32_e32 v0, s5, v0 + v_xor_b32_e32 v20, 64, v19 + v_and_b32_e32 v21, 0x1fc, v21 + v_accvgpr_write_b32 a184, v1 + v_add_u32_e32 v1, 0, v19 + v_accvgpr_write_b32 a187, v0 + v_add_u32_e32 v0, s3, v4 + v_accvgpr_write_b32 a185, v1 + v_add_u32_e32 v1, 0, v20 + v_accvgpr_write_b32 a188, v0 + v_add_u32_e32 v0, 0, v21 + v_mov_b32_e32 v15, v208 + v_add_u32_e32 v240, 0, v2 + v_accvgpr_write_b32 a186, v1 + v_accvgpr_write_b32 a189, v0 + v_mov_b32_e32 v0, v208 + v_mov_b32_e32 v1, v208 + v_mov_b32_e32 v2, v208 + v_mov_b32_e32 v3, v208 + v_mov_b32_e32 v4, v208 + v_mov_b32_e32 v5, v208 + v_mov_b32_e32 v6, v208 + v_mov_b32_e32 v7, v208 + v_mov_b32_e32 v8, v208 + v_mov_b32_e32 v9, v208 + v_mov_b32_e32 v10, v208 + v_mov_b32_e32 v11, v208 + v_mov_b32_e32 v12, v208 + v_mov_b32_e32 v13, v208 + v_mov_b32_e32 v14, v208 + v_accvgpr_write_b32 a117, v15 + v_accvgpr_write_b32 a99, v15 + s_ashr_i32 s21, s20, 31 + s_ashr_i32 s13, s12, 31 + s_ashr_i32 s7, s6, 31 + s_mov_b32 s5, 0x7050604 + s_mov_b32 s15, 0 + v_mov_b32_e32 v16, v208 + v_mov_b32_e32 v17, v208 + v_mov_b32_e32 v18, v208 + v_mov_b32_e32 v19, v208 + v_mov_b32_e32 v20, v208 + v_mov_b32_e32 v21, v208 + v_mov_b32_e32 v22, v208 + v_accvgpr_write_b32 a116, v14 + v_accvgpr_write_b32 a115, v13 + v_accvgpr_write_b32 a114, v12 + v_accvgpr_write_b32 a113, v11 + v_accvgpr_write_b32 a112, v10 + v_accvgpr_write_b32 a111, v9 + v_accvgpr_write_b32 a110, v8 + v_accvgpr_write_b32 a109, v7 + v_accvgpr_write_b32 a108, v6 + v_accvgpr_write_b32 a107, v5 + v_accvgpr_write_b32 a106, v4 + v_accvgpr_write_b32 a105, v3 + v_accvgpr_write_b32 a104, v2 + v_accvgpr_write_b32 a103, v1 + v_accvgpr_write_b32 a102, v0 + v_accvgpr_write_b32 a98, v14 + v_accvgpr_write_b32 a97, v13 + v_accvgpr_write_b32 a96, v12 + v_accvgpr_write_b32 a95, v11 + v_accvgpr_write_b32 a94, v10 + v_accvgpr_write_b32 a93, v9 + v_accvgpr_write_b32 a92, v8 + v_accvgpr_write_b32 a91, v7 + v_accvgpr_write_b32 a90, v6 + v_accvgpr_write_b32 a89, v5 + v_accvgpr_write_b32 a88, v4 + v_accvgpr_write_b32 a87, v3 + v_accvgpr_write_b32 a86, v2 + v_accvgpr_write_b32 a85, v1 + v_accvgpr_write_b32 a84, v0 + v_mov_b32_e32 v133, v208 + v_mov_b32_e32 v134, v208 + v_mov_b32_e32 v135, v208 + v_mov_b32_e32 v136, v208 + v_mov_b32_e32 v137, v208 + v_mov_b32_e32 v138, v208 + v_mov_b32_e32 v139, v208 + v_mov_b32_e32 v140, v208 + v_mov_b32_e32 v141, v208 + v_mov_b32_e32 v142, v208 + v_mov_b32_e32 v143, v208 + v_mov_b32_e32 v112, v208 + v_mov_b32_e32 v113, v208 + v_mov_b32_e32 v114, v208 + v_mov_b32_e32 v115, v208 + v_mov_b32_e32 v116, v208 + v_mov_b32_e32 v117, v208 + v_mov_b32_e32 v118, v208 + v_mov_b32_e32 v119, v208 + v_mov_b32_e32 v120, v208 + v_mov_b32_e32 v121, v208 + v_mov_b32_e32 v122, v208 + v_mov_b32_e32 v123, v208 + v_mov_b32_e32 v124, v208 + v_mov_b32_e32 v125, v208 + v_mov_b32_e32 v126, v208 + v_mov_b32_e32 v127, v208 + v_mov_b32_e32 v96, v208 + v_mov_b32_e32 v97, v208 + v_mov_b32_e32 v98, v208 + v_mov_b32_e32 v99, v208 + v_mov_b32_e32 v100, v208 + v_mov_b32_e32 v101, v208 + v_mov_b32_e32 v102, v208 + v_mov_b32_e32 v103, v208 + v_mov_b32_e32 v104, v208 + v_mov_b32_e32 v105, v208 + v_mov_b32_e32 v106, v208 + v_mov_b32_e32 v107, v208 + v_mov_b32_e32 v108, v208 + v_mov_b32_e32 v109, v208 + v_mov_b32_e32 v110, v208 + v_mov_b32_e32 v111, v208 + v_mov_b32_e32 v80, v208 + v_mov_b32_e32 v81, v208 + v_mov_b32_e32 v82, v208 + v_mov_b32_e32 v83, v208 + v_mov_b32_e32 v84, v208 + v_mov_b32_e32 v85, v208 + v_mov_b32_e32 v86, v208 + v_mov_b32_e32 v87, v208 + v_mov_b32_e32 v88, v208 + v_mov_b32_e32 v89, v208 + v_mov_b32_e32 v90, v208 + v_mov_b32_e32 v91, v208 + v_mov_b32_e32 v92, v208 + v_mov_b32_e32 v93, v208 + v_mov_b32_e32 v94, v208 + v_mov_b32_e32 v95, v208 + v_mov_b32_e32 v64, v208 + v_mov_b32_e32 v65, v208 + v_mov_b32_e32 v66, v208 + v_mov_b32_e32 v67, v208 + v_mov_b32_e32 v68, v208 + v_mov_b32_e32 v69, v208 + v_mov_b32_e32 v70, v208 + v_mov_b32_e32 v71, v208 + v_mov_b32_e32 v72, v208 + v_mov_b32_e32 v73, v208 + v_mov_b32_e32 v74, v208 + v_mov_b32_e32 v75, v208 + v_mov_b32_e32 v76, v208 + v_mov_b32_e32 v77, v208 + v_mov_b32_e32 v78, v208 + v_mov_b32_e32 v79, v208 + v_mov_b32_e32 v48, v208 + v_mov_b32_e32 v49, v208 + v_mov_b32_e32 v50, v208 + v_mov_b32_e32 v51, v208 + v_mov_b32_e32 v52, v208 + v_mov_b32_e32 v53, v208 + v_mov_b32_e32 v54, v208 + v_mov_b32_e32 v55, v208 + v_mov_b32_e32 v56, v208 + v_mov_b32_e32 v57, v208 + v_mov_b32_e32 v58, v208 + v_mov_b32_e32 v59, v208 + v_mov_b32_e32 v60, v208 + v_mov_b32_e32 v61, v208 + v_mov_b32_e32 v62, v208 + v_mov_b32_e32 v63, v208 + v_mov_b32_e32 v32, v208 + v_mov_b32_e32 v33, v208 + v_mov_b32_e32 v34, v208 + v_mov_b32_e32 v35, v208 + v_mov_b32_e32 v36, v208 + v_mov_b32_e32 v37, v208 + v_mov_b32_e32 v38, v208 + v_mov_b32_e32 v39, v208 + v_mov_b32_e32 v40, v208 + v_mov_b32_e32 v41, v208 + v_mov_b32_e32 v42, v208 + v_mov_b32_e32 v43, v208 + v_mov_b32_e32 v44, v208 + v_mov_b32_e32 v45, v208 + v_mov_b32_e32 v46, v208 + v_mov_b32_e32 v47, v208 + s_branch .LBB0_8 + .loc 1 0 14 ; :0:14 +.Ltmp21: + .p2align 5, , 4 +.LBB0_6: ; in Loop: Header=BB0_8 Depth=1 + v_accvgpr_read_b32 v193, a165 + v_accvgpr_read_b32 v192, a164 + .loc 1 129 13 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a62, v[192:193], off +.LBB0_7: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v192, a170 + .loc 1 128 13 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:128:13 + s_waitcnt vmcnt(63) expcnt(7) lgkmcnt(15) + s_barrier + s_waitcnt vmcnt(0) + ds_write_b8 v254, a0 + ds_write_b8 v254, a2 offset:512 + ds_write_b8 v254, a4 offset:1024 + ds_write_b8 v254, a6 offset:1536 + ds_write_b8 v254, a8 offset:2048 + ds_write_b8 v254, a10 offset:2560 + ds_write_b8 v254, a12 offset:3072 + ds_write_b8 v254, a14 offset:3584 + ds_write_b8 v254, a16 offset:4096 + ds_write_b8 v254, a18 offset:4608 + ds_write_b8 v254, a20 offset:5120 + ds_write_b8 v254, a22 offset:5632 + ds_write_b8 v254, a24 offset:6144 + ds_write_b8 v254, a26 offset:6656 + ds_write_b8 v254, a28 offset:7168 + ds_write_b8 v254, a30 offset:7680 + ds_write_b8 v240, v243 + ds_write_b8 v240, a1 offset:512 + ds_write_b8 v240, a3 offset:1024 + ds_write_b8 v240, a5 offset:1536 + ds_write_b8 v240, a7 offset:2048 + ds_write_b8 v240, a9 offset:2560 + ds_write_b8 v240, a11 offset:3072 + ds_write_b8 v240, a13 offset:3584 + ds_write_b8 v240, a15 offset:4096 + ds_write_b8 v240, a17 offset:4608 + ds_write_b8 v240, a19 offset:5120 + ds_write_b8 v240, a21 offset:5632 + ds_write_b8 v240, a23 offset:6144 + ds_write_b8 v240, a25 offset:6656 + ds_write_b8 v240, a27 offset:7168 + ds_write_b8 v240, a29 offset:7680 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b128 a[16:19], v192 + ds_read_b128 a[20:23], v192 offset:2048 + ds_read_b128 a[24:27], v192 offset:4096 + ds_read_b128 a[0:3], v192 offset:6144 + v_accvgpr_read_b32 v192, a171 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b8 v192, a33 + ds_write_b8 v192, a49 offset:4096 + v_accvgpr_read_b32 v192, a172 + ds_write_b8 v192, a34 + ds_write_b8 v192, a50 offset:4096 + v_accvgpr_read_b32 v192, a173 + ds_write_b8 v192, a35 + ds_write_b8 v192, a51 offset:4096 + v_accvgpr_read_b32 v192, a174 + ds_write_b8 v192, a36 + ds_write_b8 v192, a52 offset:4096 + v_accvgpr_read_b32 v192, a175 + ds_write_b8 v192, a37 + ds_write_b8 v192, a53 offset:4096 + v_accvgpr_read_b32 v192, a176 + ds_write_b8 v192, a38 + ds_write_b8 v192, a54 offset:4096 + v_accvgpr_read_b32 v192, a177 + ds_write_b8 v192, a39 + ds_write_b8 v192, a55 offset:4096 + v_accvgpr_read_b32 v192, a178 + ds_write_b8 v192, a40 + ds_write_b8 v192, a56 offset:4096 + v_accvgpr_read_b32 v192, a179 + ds_write_b8 v192, a41 + ds_write_b8 v192, a57 offset:4096 + v_accvgpr_read_b32 v192, a180 + ds_write_b8 v192, a42 + ds_write_b8 v192, a58 offset:4096 + v_accvgpr_read_b32 v192, a181 + ds_write_b8 v192, a43 + ds_write_b8 v192, a59 offset:4096 + v_accvgpr_read_b32 v192, a182 + ds_write_b8 v192, a44 + ds_write_b8 v192, a60 offset:4096 + v_accvgpr_read_b32 v192, a183 + ds_write_b8 v192, a45 + ds_write_b8 v192, a61 offset:4096 + v_accvgpr_read_b32 v192, a184 + ds_write_b8 v192, a46 + ds_write_b8 v192, a62 offset:4096 + v_accvgpr_read_b32 v192, a185 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + v_lshlrev_b16_e32 v245, 8, v245 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + ds_write_b8 v254, a31 + ds_write_b8 v254, a47 offset:4096 + ds_write_b8 v240, a32 + ds_write_b8 v240, a48 offset:4096 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b64_tr_b8 a[28:29], v192 + ds_read_b64_tr_b8 a[30:31], v192 offset:2176 + ds_read_b64_tr_b8 a[8:9], v192 offset:128 + ds_read_b64_tr_b8 a[10:11], v192 offset:2048 + v_accvgpr_read_b32 v192, a186 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + v_bitop3_b16 v242, v242, v245, s4 bitop3:0xec + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + ds_read_b64_tr_b8 a[12:13], v192 + ds_read_b64_tr_b8 a[14:15], v192 offset:2176 + ds_read_b64_tr_b8 a[4:5], v192 offset:128 + ds_read_b64_tr_b8 a[6:7], v192 offset:2048 + v_accvgpr_read_b32 v192, a187 + v_accvgpr_read_b32 v193, a188 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v192, v242 + s_waitcnt lgkmcnt(0) + s_barrier + ds_read_b32 v242, v193 + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + v_lshlrev_b16_e32 v241, 8, v241 + v_bitop3_b16 v241, v244, v241, s4 bitop3:0xec + s_waitcnt lgkmcnt(0) + s_barrier + ds_write_b16 v192, v241 + v_accvgpr_read_b32 v192, a189 + s_waitcnt lgkmcnt(0) + s_barrier + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_perm_b32 v241, v242, v242, s5 + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + ds_read_b32 v242, v192 + v_accvgpr_read_b32 v193, a169 + v_accvgpr_read_b32 v192, a168 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a168, v192 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + s_waitcnt lgkmcnt(0) + v_perm_b32 v242, v242, v242, s5 + v_accvgpr_write_b32 a169, v193 + v_accvgpr_read_b32 v193, a167 + v_mfma_scale_f32_32x32x64_f8f6f4 v[208:223], a[28:31], a[16:19], v[208:223], v242, v241 op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v192, a166 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a166, v192 + v_accvgpr_write_b32 a167, v193 + v_accvgpr_read_b32 v193, a163 + v_accvgpr_read_b32 v192, a162 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[16:31], a[12:15], a[16:19], v[16:31], v242, v241 op_sel:[1,0,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_accvgpr_write_b32 a162, v192 + v_accvgpr_write_b32 a163, v193 + v_accvgpr_read_b32 v193, a161 + v_accvgpr_read_b32 v192, a160 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a160, v192 + v_accvgpr_write_b32 a161, v193 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[224:239], a[8:11], a[16:19], v[224:239], v242, v241 op_sel_hi:[1,0,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v193, a159 + v_accvgpr_read_b32 v192, a158 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + .loc 1 137 9 ; compile_native_aiter_afp4_recovered.py:137:9 + v_lshl_add_u64 v[252:253], v[252:253], 0, s[20:21] + v_accvgpr_write_b32 a158, v192 + v_accvgpr_write_b32 a159, v193 + v_accvgpr_read_b32 v193, a157 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 a[102:117], a[4:7], a[16:19], a[102:117], v242, v241 op_sel:[1,0,0] op_sel_hi:[1,0,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v192, a156 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a156, v192 + v_accvgpr_write_b32 a157, v193 + v_accvgpr_read_b32 v193, a155 + v_accvgpr_read_b32 v192, a154 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 a[84:99], a[28:31], a[20:23], a[84:99], v242, v241 op_sel:[0,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_accvgpr_write_b32 a154, v192 + v_accvgpr_write_b32 a155, v193 + v_accvgpr_read_b32 v193, a153 + v_accvgpr_read_b32 v192, a152 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a152, v192 + v_accvgpr_write_b32 a153, v193 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[176:191], a[12:15], a[20:23], v[176:191], v242, v241 op_sel:[1,1,0] op_sel_hi:[0,0,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v193, a151 + v_accvgpr_read_b32 v192, a150 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a150, v192 + v_accvgpr_write_b32 a151, v193 + v_accvgpr_read_b32 v193, a149 + v_accvgpr_read_b32 v192, a148 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[160:175], a[8:11], a[20:23], v[160:175], v242, v241 op_sel:[0,1,0] op_sel_hi:[1,0,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a148, v192 + v_accvgpr_write_b32 a149, v193 + v_accvgpr_read_b32 v193, a147 + v_accvgpr_read_b32 v192, a146 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a146, v192 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[144:159], a[4:7], a[20:23], v[144:159], v242, v241 op_sel:[1,1,0] op_sel_hi:[1,0,0] cbsz:4 blgp:4 + v_accvgpr_write_b32 a147, v193 + v_accvgpr_read_b32 v193, a145 + v_accvgpr_read_b32 v192, a144 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a144, v192 + v_accvgpr_write_b32 a145, v193 + v_accvgpr_read_b32 v193, a143 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[128:143], a[28:31], a[24:27], v[128:143], v242, v241 op_sel_hi:[0,1,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v192, a142 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_write_b32 a142, v192 + v_accvgpr_write_b32 a143, v193 + v_accvgpr_read_b32 v193, a141 + v_accvgpr_read_b32 v192, a140 + v_accvgpr_read_b32 v207, a129 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[112:127], a[12:15], a[24:27], v[112:127], v242, v241 op_sel:[1,0,0] op_sel_hi:[0,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v206, a128 + v_accvgpr_write_b32 a140, v192 + v_accvgpr_write_b32 a141, v193 + v_accvgpr_read_b32 v193, a139 + v_accvgpr_read_b32 v192, a138 + v_accvgpr_read_b32 v205, a127 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[96:111], a[8:11], a[24:27], v[96:111], v242, v241 op_sel_hi:[1,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v204, a126 + v_accvgpr_write_b32 a138, v192 + v_accvgpr_write_b32 a139, v193 + v_accvgpr_read_b32 v193, a137 + v_accvgpr_read_b32 v192, a136 + v_accvgpr_read_b32 v203, a125 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[80:95], a[4:7], a[24:27], v[80:95], v242, v241 op_sel:[1,0,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v202, a124 + v_accvgpr_write_b32 a136, v192 + v_accvgpr_write_b32 a137, v193 + v_accvgpr_read_b32 v193, a135 + v_accvgpr_read_b32 v192, a134 + v_accvgpr_read_b32 v201, a123 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[64:79], a[28:31], a[0:3], v[64:79], v242, v241 op_sel:[0,1,0] op_sel_hi:[0,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v200, a122 + v_accvgpr_write_b32 a134, v192 + v_accvgpr_write_b32 a135, v193 + v_accvgpr_read_b32 v193, a133 + v_accvgpr_read_b32 v192, a132 + v_accvgpr_read_b32 v199, a121 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[48:63], a[12:15], a[0:3], v[48:63], v242, v241 op_sel:[1,1,0] op_sel_hi:[0,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v198, a120 + v_accvgpr_write_b32 a132, v192 + v_accvgpr_write_b32 a133, v193 + v_accvgpr_read_b32 v193, a131 + v_accvgpr_read_b32 v192, a130 + v_accvgpr_read_b32 v197, a119 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[32:47], a[8:11], a[0:3], v[32:47], v242, v241 op_sel:[0,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + v_accvgpr_read_b32 v196, a118 + v_accvgpr_write_b32 a130, v192 + v_accvgpr_read_b32 v195, a101 + .loc 1 140 9 ; compile_native_aiter_afp4_recovered.py:140:9 + s_add_i32 s15, s15, 1 + v_accvgpr_write_b32 a131, v193 + v_accvgpr_read_b32 v194, a100 + .loc 1 135 23 ; compile_native_aiter_afp4_recovered.py:135:23 + v_mfma_scale_f32_32x32x64_f8f6f4 v[0:15], a[4:7], a[0:3], v[0:15], v242, v241 op_sel:[1,1,0] op_sel_hi:[1,1,0] cbsz:4 blgp:4 + v_accvgpr_read_b32 v243, a83 + v_accvgpr_read_b32 v242, a82 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[22:23] + v_accvgpr_write_b32 a82, v242 + v_accvgpr_write_b32 a83, v243 + v_accvgpr_read_b32 v243, a81 + v_accvgpr_read_b32 v242, a80 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[22:23] + v_accvgpr_write_b32 a80, v242 + v_accvgpr_write_b32 a81, v243 + v_accvgpr_read_b32 v243, a77 + v_accvgpr_read_b32 v242, a76 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[22:23] + v_accvgpr_write_b32 a76, v242 + v_accvgpr_write_b32 a77, v243 + v_accvgpr_read_b32 v243, a75 + v_accvgpr_read_b32 v242, a74 + .loc 1 138 9 ; compile_native_aiter_afp4_recovered.py:138:9 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[12:13] + v_accvgpr_write_b32 a74, v242 + v_accvgpr_write_b32 a75, v243 + v_accvgpr_read_b32 v243, a73 + v_accvgpr_read_b32 v242, a72 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[12:13] + v_accvgpr_write_b32 a72, v242 + v_accvgpr_write_b32 a73, v243 + v_accvgpr_read_b32 v243, a79 + v_accvgpr_read_b32 v242, a78 + .loc 1 139 9 ; compile_native_aiter_afp4_recovered.py:139:9 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[6:7] + v_accvgpr_write_b32 a78, v242 + v_accvgpr_write_b32 a79, v243 + v_accvgpr_read_b32 v243, a71 + v_accvgpr_read_b32 v242, a70 + v_lshl_add_u64 v[242:243], v[242:243], 0, s[6:7] + v_accvgpr_write_b32 a70, v242 + v_accvgpr_write_b32 a71, v243 + .loc 1 137 9 ; compile_native_aiter_afp4_recovered.py:137:9 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[80:81] + v_accvgpr_write_b32 a32, v242 + v_accvgpr_write_b32 a33, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[78:79] + v_accvgpr_write_b32 a204, v242 + v_accvgpr_write_b32 a205, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[76:77] + v_accvgpr_write_b32 a34, v242 + v_accvgpr_write_b32 a35, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[74:75] + v_accvgpr_write_b32 a202, v242 + v_accvgpr_write_b32 a203, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[72:73] + v_accvgpr_write_b32 a36, v242 + v_accvgpr_write_b32 a37, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[70:71] + v_accvgpr_write_b32 a200, v242 + v_accvgpr_write_b32 a201, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[68:69] + v_accvgpr_write_b32 a38, v242 + v_accvgpr_write_b32 a39, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[66:67] + v_accvgpr_write_b32 a198, v242 + v_accvgpr_write_b32 a199, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[64:65] + v_accvgpr_write_b32 a40, v242 + v_accvgpr_write_b32 a41, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[62:63] + v_accvgpr_write_b32 a196, v242 + v_accvgpr_write_b32 a197, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[60:61] + v_accvgpr_write_b32 a42, v242 + v_accvgpr_write_b32 a43, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[58:59] + v_accvgpr_write_b32 a194, v242 + v_accvgpr_write_b32 a195, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[56:57] + v_accvgpr_write_b32 a44, v242 + v_accvgpr_write_b32 a45, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[54:55] + v_accvgpr_write_b32 a192, v242 + v_accvgpr_write_b32 a193, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[52:53] + v_accvgpr_write_b32 a46, v242 + v_accvgpr_write_b32 a47, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[50:51] + v_accvgpr_write_b32 a190, v242 + v_accvgpr_write_b32 a191, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[48:49] + v_accvgpr_write_b32 a48, v242 + v_accvgpr_write_b32 a49, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[46:47] + v_accvgpr_write_b32 a128, v242 + v_accvgpr_write_b32 a129, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[44:45] + v_accvgpr_write_b32 a50, v242 + v_accvgpr_write_b32 a51, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[42:43] + v_accvgpr_write_b32 a126, v242 + v_accvgpr_write_b32 a127, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[40:41] + v_accvgpr_write_b32 a52, v242 + v_accvgpr_write_b32 a53, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[38:39] + v_accvgpr_write_b32 a124, v242 + v_accvgpr_write_b32 a125, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[36:37] + v_accvgpr_write_b32 a54, v242 + v_accvgpr_write_b32 a55, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[34:35] + v_accvgpr_write_b32 a122, v242 + v_accvgpr_write_b32 a123, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[28:29] + v_accvgpr_write_b32 a56, v242 + v_accvgpr_write_b32 a57, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[26:27] + v_accvgpr_write_b32 a120, v242 + v_accvgpr_write_b32 a121, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[24:25] + v_accvgpr_write_b32 a58, v242 + v_accvgpr_write_b32 a59, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[18:19] + v_accvgpr_write_b32 a118, v242 + v_accvgpr_write_b32 a119, v243 + v_lshl_add_u64 v[242:243], v[252:253], 0, s[16:17] + v_mov_b64_e32 v[192:193], v[246:247] + .loc 1 122 11 ; compile_native_aiter_afp4_recovered.py:122:11 + s_lshl_b32 s85, s15, 5 + v_accvgpr_write_b32 a60, v242 + .loc 1 136 9 ; compile_native_aiter_afp4_recovered.py:136:9 + v_lshl_add_u64 v[250:251], v[250:251], 0, s[22:23] + v_lshl_add_u64 v[248:249], v[248:249], 0, s[22:23] + v_lshl_add_u64 v[206:207], v[206:207], 0, s[22:23] + v_lshl_add_u64 v[204:205], v[204:205], 0, s[22:23] + v_lshl_add_u64 v[202:203], v[202:203], 0, s[22:23] + v_lshl_add_u64 v[200:201], v[200:201], 0, s[22:23] + v_lshl_add_u64 v[198:199], v[198:199], 0, s[22:23] + v_lshl_add_u64 v[196:197], v[196:197], 0, s[22:23] + v_lshl_add_u64 v[194:195], v[194:195], 0, s[22:23] + v_lshl_add_u64 v[192:193], v[192:193], 0, s[22:23] + .loc 1 122 11 ; compile_native_aiter_afp4_recovered.py:122:11 + s_cmp_lt_i32 s85, s14 + v_accvgpr_write_b32 a61, v243 + .loc 1 137 9 ; compile_native_aiter_afp4_recovered.py:137:9 + v_lshl_add_u64 v[244:245], v[252:253], 0, s[10:11] + v_lshl_add_u64 v[242:243], v[252:253], 0, s[8:9] + .loc 1 122 11 ; compile_native_aiter_afp4_recovered.py:122:11 + s_cbranch_scc0 .LBB0_146 +.LBB0_8: ; =>This Inner Loop Header: Depth=1 + .loc 1 0 11 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:11 + v_accvgpr_write_b32 a100, v244 + .loc 1 124 41 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:124:41 + s_lshl_b32 s2, s15, 1 + v_accvgpr_write_b32 a101, v245 + v_accvgpr_write_b32 a164, v242 + .loc 1 124 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:124:13 + s_sub_i32 s2, s84, s2 + v_accvgpr_read_b32 v241, a69 + .loc 1 126 20 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:126:20 + v_mov_b32_e32 v245, 0x7f + v_accvgpr_write_b32 a165, v243 + .loc 1 123 22 ; compile_native_aiter_afp4_recovered.py:123:22 + v_cmp_gt_i32_e32 vcc, s2, v241 + v_mov_b32_e32 v242, v245 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_10 +; %bb.9: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:20 + v_accvgpr_read_b32 v243, a75 + v_accvgpr_read_b32 v242, a74 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + global_load_ubyte v242, v[242:243], off +.LBB0_10: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + s_or_b64 exec, exec, s[2:3] + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_12 +; %bb.11: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + v_accvgpr_read_b32 v245, a73 + v_accvgpr_read_b32 v244, a72 + .loc 1 126 20 ; compile_native_aiter_afp4_recovered.py:126:20 + global_load_ubyte v245, v[244:245], off +.LBB0_12: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + s_or_b64 exec, exec, s[2:3] + .loc 1 127 20 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:127:20 + v_mov_b32_e32 v241, 0x7f + v_mov_b32_e32 v244, v241 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_14 +; %bb.13: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:20 + v_accvgpr_read_b32 v247, a79 + v_accvgpr_read_b32 v246, a78 + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + global_load_ubyte v244, v[246:247], off +.LBB0_14: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + s_or_b64 exec, exec, s[2:3] + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_16 +; %bb.15: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + v_accvgpr_read_b32 v247, a71 + v_accvgpr_read_b32 v246, a70 + .loc 1 127 20 ; compile_native_aiter_afp4_recovered.py:127:20 + global_load_ubyte v241, v[246:247], off +.LBB0_16: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 20 ; compile_native_aiter_afp4_recovered.py:0:20 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 52 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:128:52 + s_sub_i32 s82, s14, s85 + v_accvgpr_read_b32 v243, a67 + .loc 1 128 34 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:128:34 + v_cmp_gt_i32_e32 vcc, s82, v243 + v_mov_b32_e32 v243, 0 + v_accvgpr_write_b32 a0, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_18 +; %bb.17: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a0, v[250:251], off +.LBB0_18: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_20 +; %bb.19: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte v243, v[248:249], off +.LBB0_20: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a1, 0 + v_accvgpr_write_b32 a2, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_22 +; %bb.21: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a169 + v_accvgpr_read_b32 v246, a168 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a2, v[246:247], off +.LBB0_22: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_24 +; %bb.23: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a167 + v_accvgpr_read_b32 v246, a166 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a1, v[246:247], off +.LBB0_24: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a3, 0 + v_accvgpr_write_b32 a4, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_26 +; %bb.25: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a163 + v_accvgpr_read_b32 v246, a162 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a4, v[246:247], off +.LBB0_26: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_28 +; %bb.27: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a161 + v_accvgpr_read_b32 v246, a160 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a3, v[246:247], off +.LBB0_28: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a5, 0 + v_accvgpr_write_b32 a6, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_30 +; %bb.29: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a159 + v_accvgpr_read_b32 v246, a158 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a6, v[246:247], off +.LBB0_30: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_32 +; %bb.31: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a157 + v_accvgpr_read_b32 v246, a156 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a5, v[246:247], off +.LBB0_32: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a7, 0 + v_accvgpr_write_b32 a8, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_34 +; %bb.33: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a155 + v_accvgpr_read_b32 v246, a154 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a8, v[246:247], off +.LBB0_34: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_36 +; %bb.35: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a153 + v_accvgpr_read_b32 v246, a152 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a7, v[246:247], off +.LBB0_36: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a9, 0 + v_accvgpr_write_b32 a10, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_38 +; %bb.37: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a151 + v_accvgpr_read_b32 v246, a150 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a10, v[246:247], off +.LBB0_38: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_40 +; %bb.39: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a149 + v_accvgpr_read_b32 v246, a148 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a9, v[246:247], off +.LBB0_40: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a11, 0 + v_accvgpr_write_b32 a12, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_42 +; %bb.41: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a147 + v_accvgpr_read_b32 v246, a146 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a12, v[246:247], off +.LBB0_42: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_44 +; %bb.43: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a145 + v_accvgpr_read_b32 v246, a144 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a11, v[246:247], off +.LBB0_44: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a13, 0 + v_accvgpr_write_b32 a14, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_46 +; %bb.45: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a143 + v_accvgpr_read_b32 v246, a142 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a14, v[246:247], off +.LBB0_46: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_48 +; %bb.47: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a141 + v_accvgpr_read_b32 v246, a140 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a13, v[246:247], off +.LBB0_48: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a15, 0 + v_accvgpr_write_b32 a16, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_50 +; %bb.49: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a139 + v_accvgpr_read_b32 v246, a138 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a16, v[246:247], off +.LBB0_50: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_52 +; %bb.51: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a137 + v_accvgpr_read_b32 v246, a136 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a15, v[246:247], off +.LBB0_52: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a17, 0 + v_accvgpr_write_b32 a18, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_54 +; %bb.53: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a135 + v_accvgpr_read_b32 v246, a134 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a18, v[246:247], off +.LBB0_54: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_56 +; %bb.55: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a133 + v_accvgpr_read_b32 v246, a132 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a17, v[246:247], off +.LBB0_56: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a19, 0 + v_accvgpr_write_b32 a20, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_58 +; %bb.57: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a131 + v_accvgpr_read_b32 v246, a130 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a20, v[246:247], off +.LBB0_58: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_60 +; %bb.59: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a19, v[206:207], off +.LBB0_60: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a21, 0 + v_accvgpr_write_b32 a22, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_62 +; %bb.61: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a22, v[204:205], off +.LBB0_62: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_64 +; %bb.63: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a21, v[202:203], off +.LBB0_64: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a23, 0 + v_accvgpr_write_b32 a24, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_66 +; %bb.65: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a24, v[200:201], off +.LBB0_66: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_68 +; %bb.67: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a23, v[198:199], off +.LBB0_68: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a25, 0 + v_accvgpr_write_b32 a26, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_70 +; %bb.69: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a26, v[196:197], off +.LBB0_70: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_72 +; %bb.71: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a25, v[194:195], off +.LBB0_72: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a27, 0 + v_accvgpr_write_b32 a28, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_74 +; %bb.73: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a28, v[192:193], off +.LBB0_74: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_76 +; %bb.75: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a83 + v_accvgpr_read_b32 v246, a82 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a27, v[246:247], off +.LBB0_76: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + v_accvgpr_write_b32 a29, 0 + v_accvgpr_write_b32 a30, 0 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execnz .LBB0_110 +; %bb.77: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execnz .LBB0_111 +.LBB0_78: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + s_or_b64 exec, exec, s[2:3] + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 1 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_112 +.LBB0_79: ; in Loop: Header=BB0_8 Depth=1 + global_load_ubyte a31, v[252:253], off + .loc 1 131 18 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 2 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_113 +.LBB0_80: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a33 + v_accvgpr_read_b32 v246, a32 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a32, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 3 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_114 +.LBB0_81: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a33, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 4 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_115 +.LBB0_82: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a34, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 5 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_116 +.LBB0_83: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a35, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 6 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_117 +.LBB0_84: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a36, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 7 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_118 +.LBB0_85: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a37, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 8 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_119 +.LBB0_86: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a38, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 9 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_120 +.LBB0_87: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a39, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 10 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_121 +.LBB0_88: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a40, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 11 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_122 +.LBB0_89: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a41, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 12 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_123 +.LBB0_90: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a42, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 13 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_124 +.LBB0_91: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a43, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 14 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_125 +.LBB0_92: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a44, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 15 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_126 +.LBB0_93: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a45, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 16 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_127 +.LBB0_94: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a46, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 17 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_128 +.LBB0_95: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a47, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 18 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_129 +.LBB0_96: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a48, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 19 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_130 +.LBB0_97: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a49, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 20 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_131 +.LBB0_98: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a50, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 21 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_132 +.LBB0_99: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a51, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 22 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_133 +.LBB0_100: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a52, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 23 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_134 +.LBB0_101: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a53, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 24 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_135 +.LBB0_102: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a54, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 25 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_136 +.LBB0_103: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a55, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 26 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_137 +.LBB0_104: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a56, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 27 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_138 +.LBB0_105: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a57, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 28 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_139 +.LBB0_106: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a58, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 29 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_140 +.LBB0_107: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a59, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 30 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_141 +.LBB0_108: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a60, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 31 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_142 +.LBB0_109: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a61, 0 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_branch .LBB0_143 + .loc 1 0 13 ; :0:13 +.Ltmp22: + .p2align 5, , 4 +.LBB0_110: ; in Loop: Header=BB0_8 Depth=1 + v_accvgpr_read_b32 v247, a81 + v_accvgpr_read_b32 v246, a80 + .loc 1 128 13 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a30, v[246:247], off + s_or_b64 exec, exec, s[2:3] + s_and_saveexec_b64 s[2:3], vcc + s_cbranch_execz .LBB0_78 +.LBB0_111: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a77 + v_accvgpr_read_b32 v246, a76 + .loc 1 128 13 ; compile_native_aiter_afp4_recovered.py:128:13 + global_load_ubyte a29, v[246:247], off + s_or_b64 exec, exec, s[2:3] + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 1 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_79 +.LBB0_112: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a31, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 2 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_80 +.LBB0_113: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a32, 0 + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 3 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_81 +.LBB0_114: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a205 + v_accvgpr_read_b32 v246, a204 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a33, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 4 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_82 +.LBB0_115: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a35 + v_accvgpr_read_b32 v246, a34 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a34, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 5 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_83 +.LBB0_116: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a203 + v_accvgpr_read_b32 v246, a202 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a35, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 6 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_84 +.LBB0_117: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a37 + v_accvgpr_read_b32 v246, a36 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a36, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 7 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_85 +.LBB0_118: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a201 + v_accvgpr_read_b32 v246, a200 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a37, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 8 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_86 +.LBB0_119: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a39 + v_accvgpr_read_b32 v246, a38 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a38, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 9 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_87 +.LBB0_120: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a199 + v_accvgpr_read_b32 v246, a198 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a39, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 10 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_88 +.LBB0_121: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a41 + v_accvgpr_read_b32 v246, a40 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a40, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 11 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_89 +.LBB0_122: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a197 + v_accvgpr_read_b32 v246, a196 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a41, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 12 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_90 +.LBB0_123: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a43 + v_accvgpr_read_b32 v246, a42 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a42, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 13 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_91 +.LBB0_124: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a195 + v_accvgpr_read_b32 v246, a194 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a43, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 14 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_92 +.LBB0_125: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a45 + v_accvgpr_read_b32 v246, a44 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a44, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 15 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_93 +.LBB0_126: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a193 + v_accvgpr_read_b32 v246, a192 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a45, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 16 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_94 +.LBB0_127: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a47 + v_accvgpr_read_b32 v246, a46 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a46, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 17 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_95 +.LBB0_128: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a191 + v_accvgpr_read_b32 v246, a190 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a47, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 18 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_96 +.LBB0_129: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a49 + v_accvgpr_read_b32 v246, a48 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a48, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 19 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_97 +.LBB0_130: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a129 + v_accvgpr_read_b32 v246, a128 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a49, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 20 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_98 +.LBB0_131: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a51 + v_accvgpr_read_b32 v246, a50 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a50, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 21 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_99 +.LBB0_132: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a127 + v_accvgpr_read_b32 v246, a126 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a51, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 22 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_100 +.LBB0_133: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a53 + v_accvgpr_read_b32 v246, a52 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a52, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 23 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_101 +.LBB0_134: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a125 + v_accvgpr_read_b32 v246, a124 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a53, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 24 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_102 +.LBB0_135: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a55 + v_accvgpr_read_b32 v246, a54 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a54, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 25 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_103 +.LBB0_136: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a123 + v_accvgpr_read_b32 v246, a122 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a55, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 26 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_104 +.LBB0_137: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a57 + v_accvgpr_read_b32 v246, a56 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a56, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 27 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_105 +.LBB0_138: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a121 + v_accvgpr_read_b32 v246, a120 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a57, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 28 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_106 +.LBB0_139: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a59 + v_accvgpr_read_b32 v246, a58 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a58, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 29 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_107 +.LBB0_140: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a119 + v_accvgpr_read_b32 v246, a118 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a59, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 30 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_108 +.LBB0_141: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a61 + v_accvgpr_read_b32 v246, a60 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a60, v[246:247], off + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 31 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc1 .LBB0_109 +.LBB0_142: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_read_b32 v247, a101 + v_accvgpr_read_b32 v246, a100 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + global_load_ubyte a61, v[246:247], off +.LBB0_143: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a128, v206 + v_accvgpr_write_b32 a126, v204 + v_accvgpr_write_b32 a124, v202 + v_accvgpr_write_b32 a122, v200 + v_accvgpr_write_b32 a120, v198 + v_accvgpr_write_b32 a118, v196 + v_accvgpr_write_b32 a100, v194 + v_accvgpr_write_b32 a129, v207 + v_accvgpr_write_b32 a127, v205 + v_accvgpr_write_b32 a125, v203 + v_accvgpr_write_b32 a123, v201 + v_accvgpr_write_b32 a121, v199 + v_accvgpr_write_b32 a119, v197 + v_accvgpr_write_b32 a101, v195 + v_mov_b64_e32 v[246:247], v[192:193] + .loc 1 131 18 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:131:18 + s_cmp_lt_i32 s82, 32 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_cbranch_scc0 .LBB0_6 +; %bb.144: ; in Loop: Header=BB0_8 Depth=1 + .loc 1 0 13 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:13 + v_accvgpr_write_b32 a62, 0 + .loc 1 129 13 ; compile_native_aiter_afp4_recovered.py:129:13 + s_branch .LBB0_7 +.LBB0_145: + .loc 1 0 13 ; compile_native_aiter_afp4_recovered.py:0:13 + v_mov_b32_e32 v15, 0 + v_mov_b32_e32 v31, v15 + v_accvgpr_write_b32 a68, v16 + v_mov_b32_e32 v30, v15 + v_mov_b32_e32 v29, v15 + v_mov_b32_e32 v28, v15 + v_mov_b32_e32 v27, v15 + v_mov_b32_e32 v26, v15 + v_mov_b32_e32 v25, v15 + v_mov_b32_e32 v24, v15 + v_mov_b32_e32 v23, v15 + v_mov_b32_e32 v22, v15 + v_mov_b32_e32 v21, v15 + v_mov_b32_e32 v20, v15 + v_mov_b32_e32 v19, v15 + v_mov_b32_e32 v18, v15 + v_mov_b32_e32 v17, v15 + v_mov_b32_e32 v16, v15 + v_accvgpr_write_b32 a99, v31 + v_accvgpr_write_b32 a117, v31 + v_accvgpr_write_b32 a66, v14 + v_mov_b32_e32 v14, v15 + v_mov_b32_e32 v13, v15 + v_mov_b32_e32 v12, v15 + v_mov_b32_e32 v11, v15 + v_mov_b32_e32 v10, v15 + v_mov_b32_e32 v9, v15 + v_mov_b32_e32 v8, v15 + v_mov_b32_e32 v7, v15 + v_mov_b32_e32 v6, v15 + v_mov_b32_e32 v5, v15 + v_mov_b32_e32 v4, v15 + v_mov_b32_e32 v3, v15 + v_mov_b32_e32 v2, v15 + v_mov_b32_e32 v1, v15 + v_mov_b32_e32 v0, v15 + v_mov_b32_e32 v47, v15 + v_mov_b32_e32 v46, v15 + v_mov_b32_e32 v45, v15 + v_mov_b32_e32 v44, v15 + v_mov_b32_e32 v43, v15 + v_mov_b32_e32 v42, v15 + v_mov_b32_e32 v41, v15 + v_mov_b32_e32 v40, v15 + v_mov_b32_e32 v39, v15 + v_mov_b32_e32 v38, v15 + v_mov_b32_e32 v37, v15 + v_mov_b32_e32 v36, v15 + v_mov_b32_e32 v35, v15 + v_mov_b32_e32 v34, v15 + v_mov_b32_e32 v33, v15 + v_mov_b32_e32 v32, v15 + v_mov_b32_e32 v63, v15 + v_mov_b32_e32 v62, v15 + v_mov_b32_e32 v61, v15 + v_mov_b32_e32 v60, v15 + v_mov_b32_e32 v59, v15 + v_mov_b32_e32 v58, v15 + v_mov_b32_e32 v57, v15 + v_mov_b32_e32 v56, v15 + v_mov_b32_e32 v55, v15 + v_mov_b32_e32 v54, v15 + v_mov_b32_e32 v53, v15 + v_mov_b32_e32 v52, v15 + v_mov_b32_e32 v51, v15 + v_mov_b32_e32 v50, v15 + v_mov_b32_e32 v49, v15 + v_mov_b32_e32 v48, v15 + v_mov_b32_e32 v79, v15 + v_mov_b32_e32 v78, v15 + v_mov_b32_e32 v77, v15 + v_mov_b32_e32 v76, v15 + v_mov_b32_e32 v75, v15 + v_mov_b32_e32 v74, v15 + v_mov_b32_e32 v73, v15 + v_mov_b32_e32 v72, v15 + v_mov_b32_e32 v71, v15 + v_mov_b32_e32 v70, v15 + v_mov_b32_e32 v69, v15 + v_mov_b32_e32 v68, v15 + v_mov_b32_e32 v67, v15 + v_mov_b32_e32 v66, v15 + v_mov_b32_e32 v65, v15 + v_mov_b32_e32 v64, v15 + v_mov_b32_e32 v95, v15 + v_mov_b32_e32 v94, v15 + v_mov_b32_e32 v93, v15 + v_mov_b32_e32 v92, v15 + v_mov_b32_e32 v91, v15 + v_mov_b32_e32 v90, v15 + v_mov_b32_e32 v89, v15 + v_mov_b32_e32 v88, v15 + v_mov_b32_e32 v87, v15 + v_mov_b32_e32 v86, v15 + v_mov_b32_e32 v85, v15 + v_mov_b32_e32 v84, v15 + v_mov_b32_e32 v83, v15 + v_mov_b32_e32 v82, v15 + v_mov_b32_e32 v81, v15 + v_mov_b32_e32 v80, v15 + v_mov_b32_e32 v111, v15 + v_mov_b32_e32 v110, v15 + v_mov_b32_e32 v109, v15 + v_mov_b32_e32 v108, v15 + v_mov_b32_e32 v107, v15 + v_mov_b32_e32 v106, v15 + v_mov_b32_e32 v105, v15 + v_mov_b32_e32 v104, v15 + v_mov_b32_e32 v103, v15 + v_mov_b32_e32 v102, v15 + v_mov_b32_e32 v101, v15 + v_mov_b32_e32 v100, v15 + v_mov_b32_e32 v99, v15 + v_mov_b32_e32 v98, v15 + v_mov_b32_e32 v97, v15 + v_mov_b32_e32 v96, v15 + v_mov_b32_e32 v127, v15 + v_mov_b32_e32 v126, v15 + v_mov_b32_e32 v125, v15 + v_mov_b32_e32 v124, v15 + v_mov_b32_e32 v123, v15 + v_mov_b32_e32 v122, v15 + v_mov_b32_e32 v121, v15 + v_mov_b32_e32 v120, v15 + v_mov_b32_e32 v119, v15 + v_mov_b32_e32 v118, v15 + v_mov_b32_e32 v117, v15 + v_mov_b32_e32 v116, v15 + v_mov_b32_e32 v115, v15 + v_mov_b32_e32 v114, v15 + v_mov_b32_e32 v113, v15 + v_mov_b32_e32 v112, v15 + v_mov_b32_e32 v143, v15 + v_mov_b32_e32 v142, v15 + v_mov_b32_e32 v141, v15 + v_mov_b32_e32 v140, v15 + v_mov_b32_e32 v139, v15 + v_mov_b32_e32 v138, v15 + v_mov_b32_e32 v137, v15 + v_mov_b32_e32 v136, v15 + v_mov_b32_e32 v135, v15 + v_mov_b32_e32 v134, v15 + v_mov_b32_e32 v133, v15 + v_mov_b32_e32 v132, v15 + v_mov_b32_e32 v131, v15 + v_mov_b32_e32 v130, v15 + v_mov_b32_e32 v129, v15 + v_mov_b32_e32 v128, v15 + v_mov_b32_e32 v159, v15 + v_mov_b32_e32 v158, v15 + v_mov_b32_e32 v157, v15 + v_mov_b32_e32 v156, v15 + v_mov_b32_e32 v155, v15 + v_mov_b32_e32 v154, v15 + v_mov_b32_e32 v153, v15 + v_mov_b32_e32 v152, v15 + v_mov_b32_e32 v151, v15 + v_mov_b32_e32 v150, v15 + v_mov_b32_e32 v149, v15 + v_mov_b32_e32 v148, v15 + v_mov_b32_e32 v147, v15 + v_mov_b32_e32 v146, v15 + v_mov_b32_e32 v145, v15 + v_mov_b32_e32 v144, v15 + v_mov_b32_e32 v175, v15 + v_mov_b32_e32 v174, v15 + v_mov_b32_e32 v173, v15 + v_mov_b32_e32 v172, v15 + v_mov_b32_e32 v171, v15 + v_mov_b32_e32 v170, v15 + v_mov_b32_e32 v169, v15 + v_mov_b32_e32 v168, v15 + v_mov_b32_e32 v167, v15 + v_mov_b32_e32 v166, v15 + v_mov_b32_e32 v165, v15 + v_mov_b32_e32 v164, v15 + v_mov_b32_e32 v163, v15 + v_mov_b32_e32 v162, v15 + v_mov_b32_e32 v161, v15 + v_mov_b32_e32 v160, v15 + v_mov_b32_e32 v191, v15 + v_mov_b32_e32 v190, v15 + v_mov_b32_e32 v189, v15 + v_mov_b32_e32 v188, v15 + v_mov_b32_e32 v187, v15 + v_mov_b32_e32 v186, v15 + v_mov_b32_e32 v185, v15 + v_mov_b32_e32 v184, v15 + v_mov_b32_e32 v183, v15 + v_mov_b32_e32 v182, v15 + v_mov_b32_e32 v181, v15 + v_mov_b32_e32 v180, v15 + v_mov_b32_e32 v179, v15 + v_mov_b32_e32 v178, v15 + v_mov_b32_e32 v177, v15 + v_mov_b32_e32 v176, v15 + v_accvgpr_write_b32 a98, v30 + v_accvgpr_write_b32 a97, v29 + v_accvgpr_write_b32 a96, v28 + v_accvgpr_write_b32 a95, v27 + v_accvgpr_write_b32 a94, v26 + v_accvgpr_write_b32 a93, v25 + v_accvgpr_write_b32 a92, v24 + v_accvgpr_write_b32 a91, v23 + v_accvgpr_write_b32 a90, v22 + v_accvgpr_write_b32 a89, v21 + v_accvgpr_write_b32 a88, v20 + v_accvgpr_write_b32 a87, v19 + v_accvgpr_write_b32 a86, v18 + v_accvgpr_write_b32 a85, v17 + v_accvgpr_write_b32 a84, v16 + v_accvgpr_write_b32 a116, v30 + v_accvgpr_write_b32 a115, v29 + v_accvgpr_write_b32 a114, v28 + v_accvgpr_write_b32 a113, v27 + v_accvgpr_write_b32 a112, v26 + v_accvgpr_write_b32 a111, v25 + v_accvgpr_write_b32 a110, v24 + v_accvgpr_write_b32 a109, v23 + v_accvgpr_write_b32 a108, v22 + v_accvgpr_write_b32 a107, v21 + v_accvgpr_write_b32 a106, v20 + v_accvgpr_write_b32 a105, v19 + v_accvgpr_write_b32 a104, v18 + v_accvgpr_write_b32 a103, v17 + v_accvgpr_write_b32 a102, v16 + v_mov_b32_e32 v239, v15 + v_mov_b32_e32 v238, v15 + v_mov_b32_e32 v237, v15 + v_mov_b32_e32 v236, v15 + v_mov_b32_e32 v235, v15 + v_mov_b32_e32 v234, v15 + v_mov_b32_e32 v233, v15 + v_mov_b32_e32 v232, v15 + v_mov_b32_e32 v231, v15 + v_mov_b32_e32 v230, v15 + v_mov_b32_e32 v229, v15 + v_mov_b32_e32 v228, v15 + v_mov_b32_e32 v227, v15 + v_mov_b32_e32 v226, v15 + v_mov_b32_e32 v225, v15 + v_mov_b32_e32 v224, v15 + v_mov_b32_e32 v223, v15 + v_mov_b32_e32 v222, v15 + v_mov_b32_e32 v221, v15 + v_mov_b32_e32 v220, v15 + v_mov_b32_e32 v219, v15 + v_mov_b32_e32 v218, v15 + v_mov_b32_e32 v217, v15 + v_mov_b32_e32 v216, v15 + v_mov_b32_e32 v215, v15 + v_mov_b32_e32 v214, v15 + v_mov_b32_e32 v213, v15 + v_mov_b32_e32 v212, v15 + v_mov_b32_e32 v211, v15 + v_mov_b32_e32 v210, v15 + v_mov_b32_e32 v209, v15 + v_mov_b32_e32 v208, v15 +.LBB0_146: ; %Flow525 + s_load_dwordx2 s[34:35], s[0:1], 0x48 + .loc 1 145 22 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v254, v16, v17 + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + s_lshr_b32 s0, s31, 2 + v_accvgpr_read_b32 v16, a67 + v_or_b32_e32 v194, s0, v16 + v_accvgpr_read_b32 v16, a68 + v_lshrrev_b32_e32 v16, 2, v16 + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v253, v18, v19 + .loc 1 111 39 ; compile_native_aiter_afp4_recovered.py:111:39 + v_or_b32_e32 v19, s33, v16 + v_accvgpr_read_b32 v16, a64 + .loc 1 142 15 ; compile_native_aiter_afp4_recovered.py:142:15 + v_or_b32_e32 v16, v16, v194 + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v252, v20, v21 + .loc 1 144 22 ; compile_native_aiter_afp4_recovered.py:144:22 + s_waitcnt lgkmcnt(0) + v_mad_i64_i32 v[20:21], s[0:1], v16, s34, 0 + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v241, v210, v211 + v_cvt_pk_bf16_f32 v240, v212, v213 + v_cvt_pk_bf16_f32 v213, v216, v217 + v_cvt_pk_bf16_f32 v212, v218, v219 + v_cvt_pk_bf16_f32 v211, v220, v221 + v_cvt_pk_bf16_f32 v210, v222, v223 + v_cvt_pk_bf16_f32 v249, v26, v27 + v_cvt_pk_bf16_f32 v246, v224, v225 + v_cvt_pk_bf16_f32 v245, v226, v227 + v_cvt_pk_bf16_f32 v244, v228, v229 + v_cvt_pk_bf16_f32 v243, v230, v231 + v_accvgpr_read_b32 v27, a66 + v_accvgpr_read_b32 v231, a117 + .loc 1 144 14 ; compile_native_aiter_afp4_recovered.py:144:14 + v_readlane_b32 s0, v255, 0 + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v242, v208, v209 + .loc 1 143 15 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v208, v27, v19 + v_accvgpr_read_b32 v230, a116 + v_accvgpr_read_b32 v229, a115 + v_accvgpr_read_b32 v228, a114 + v_accvgpr_read_b32 v227, a113 + v_accvgpr_read_b32 v226, a112 + v_accvgpr_read_b32 v225, a111 + v_accvgpr_read_b32 v224, a110 + v_accvgpr_read_b32 v223, a109 + v_accvgpr_read_b32 v222, a108 + v_accvgpr_read_b32 v221, a107 + v_accvgpr_read_b32 v220, a106 + v_accvgpr_read_b32 v219, a105 + v_accvgpr_read_b32 v218, a104 + v_accvgpr_read_b32 v217, a103 + v_accvgpr_read_b32 v216, a102 + .loc 1 144 14 ; compile_native_aiter_afp4_recovered.py:144:14 + v_readlane_b32 s1, v255, 1 + .loc 1 145 67 ; compile_native_aiter_afp4_recovered.py:145:67 + s_ashr_i32 s89, s88, 31 + .loc 1 145 22 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v250, v24, v25 + v_cvt_pk_bf16_f32 v248, v28, v29 + v_cvt_pk_bf16_f32 v247, v30, v31 + v_cvt_pk_bf16_f32 v26, v232, v233 + v_cvt_pk_bf16_f32 v25, v234, v235 + v_cvt_pk_bf16_f32 v24, v236, v237 + v_cvt_pk_bf16_f32 v236, v238, v239 + v_accvgpr_read_b32 v209, a65 + v_cvt_pk_bf16_f32 v239, v216, v217 + v_cvt_pk_bf16_f32 v238, v218, v219 + v_cvt_pk_bf16_f32 v237, v220, v221 + v_cvt_pk_bf16_f32 v235, v222, v223 + v_cvt_pk_bf16_f32 v234, v224, v225 + v_cvt_pk_bf16_f32 v233, v226, v227 + v_cvt_pk_bf16_f32 v232, v228, v229 + v_cvt_pk_bf16_f32 v199, v230, v231 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[192:193], v[20:21], 1, s[0:1] + .loc 1 144 53 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[20:21], s[0:1], v208, s35, 0 + v_writelane_b32 v255, s88, 2 + .loc 1 145 92 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:145:92 + s_ashr_i32 s31, s30, 31 + v_accvgpr_read_b32 v231, a99 + v_mov_b64_e32 v[28:29], v[32:33] + .loc 1 145 22 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v214, v214, v215 + v_cvt_pk_bf16_f32 v251, v22, v23 + v_accvgpr_read_b32 v17, a63 + v_accvgpr_write_b32 a2, v20 + v_writelane_b32 v255, s89, 3 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[208:209] + v_accvgpr_read_b32 v230, a98 + v_accvgpr_read_b32 v229, a97 + v_accvgpr_read_b32 v228, a96 + v_accvgpr_read_b32 v227, a95 + v_accvgpr_read_b32 v226, a94 + v_accvgpr_read_b32 v225, a93 + v_accvgpr_read_b32 v224, a92 + v_accvgpr_read_b32 v223, a91 + v_accvgpr_read_b32 v222, a90 + v_accvgpr_read_b32 v221, a89 + v_accvgpr_read_b32 v220, a88 + v_accvgpr_read_b32 v219, a87 + v_accvgpr_read_b32 v218, a86 + v_accvgpr_read_b32 v217, a85 + v_accvgpr_read_b32 v216, a84 + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v215, v188, v189 + v_cvt_pk_bf16_f32 v23, v190, v191 + v_cvt_pk_bf16_f32 v191, v134, v135 + v_cvt_pk_bf16_f32 v189, v138, v139 + v_mov_b64_e32 v[30:31], v[34:35] + v_mov_b64_e32 v[32:33], v[36:37] + v_mov_b64_e32 v[34:35], v[38:39] + v_mov_b64_e32 v[36:37], v[40:41] + v_mov_b64_e32 v[38:39], v[42:43] + v_mov_b64_e32 v[40:41], v[44:45] + v_mov_b64_e32 v[42:43], v[46:47] + v_cvt_pk_bf16_f32 v139, v0, v1 + v_cvt_pk_bf16_f32 v135, v8, v9 + v_cvt_pk_bf16_f32 v134, v10, v11 + v_cvt_pk_bf16_f32 v1, v12, v13 + v_cvt_pk_bf16_f32 v0, v14, v15 + v_accvgpr_write_b32 a3, v21 + .loc 1 145 67 ; compile_native_aiter_afp4_recovered.py:145:67 + v_cmp_gt_i64_e32 vcc, s[88:89], v[16:17] + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_cvt_pk_bf16_f32 v198, v216, v217 + v_cvt_pk_bf16_f32 v197, v218, v219 + v_cvt_pk_bf16_f32 v196, v220, v221 + v_cvt_pk_bf16_f32 v195, v222, v223 + v_cvt_pk_bf16_f32 v17, v224, v225 + v_cvt_pk_bf16_f32 v225, v226, v227 + v_cvt_pk_bf16_f32 v223, v228, v229 + v_cvt_pk_bf16_f32 v222, v230, v231 + v_cvt_pk_bf16_f32 v221, v176, v177 + v_cvt_pk_bf16_f32 v220, v178, v179 + v_cvt_pk_bf16_f32 v219, v180, v181 + v_cvt_pk_bf16_f32 v218, v182, v183 + v_cvt_pk_bf16_f32 v217, v184, v185 + v_cvt_pk_bf16_f32 v216, v186, v187 + v_cvt_pk_bf16_f32 v22, v160, v161 + v_cvt_pk_bf16_f32 v21, v162, v163 + v_cvt_pk_bf16_f32 v20, v164, v165 + v_cvt_pk_bf16_f32 v18, v166, v167 + v_cvt_pk_bf16_f32 v209, v168, v169 + v_cvt_pk_bf16_f32 v207, v170, v171 + v_cvt_pk_bf16_f32 v206, v172, v173 + v_cvt_pk_bf16_f32 v205, v174, v175 + v_cvt_pk_bf16_f32 v204, v144, v145 + v_cvt_pk_bf16_f32 v203, v146, v147 + v_cvt_pk_bf16_f32 v202, v148, v149 + v_cvt_pk_bf16_f32 v201, v150, v151 + v_cvt_pk_bf16_f32 v200, v152, v153 + v_cvt_pk_bf16_f32 v231, v154, v155 + v_cvt_pk_bf16_f32 v230, v156, v157 + v_cvt_pk_bf16_f32 v229, v158, v159 + v_cvt_pk_bf16_f32 v228, v128, v129 + v_cvt_pk_bf16_f32 v227, v130, v131 + v_cvt_pk_bf16_f32 v224, v132, v133 + v_cvt_pk_bf16_f32 v190, v136, v137 + v_cvt_pk_bf16_f32 v188, v140, v141 + v_cvt_pk_bf16_f32 v187, v142, v143 + v_cvt_pk_bf16_f32 v186, v112, v113 + v_cvt_pk_bf16_f32 v185, v114, v115 + v_cvt_pk_bf16_f32 v184, v116, v117 + v_cvt_pk_bf16_f32 v183, v118, v119 + v_cvt_pk_bf16_f32 v182, v120, v121 + v_cvt_pk_bf16_f32 v181, v122, v123 + v_cvt_pk_bf16_f32 v180, v124, v125 + v_cvt_pk_bf16_f32 v179, v126, v127 + v_cvt_pk_bf16_f32 v178, v96, v97 + v_cvt_pk_bf16_f32 v177, v98, v99 + v_cvt_pk_bf16_f32 v176, v100, v101 + v_cvt_pk_bf16_f32 v175, v102, v103 + v_cvt_pk_bf16_f32 v174, v104, v105 + v_cvt_pk_bf16_f32 v173, v106, v107 + v_cvt_pk_bf16_f32 v172, v108, v109 + v_cvt_pk_bf16_f32 v171, v110, v111 + v_cvt_pk_bf16_f32 v170, v80, v81 + v_cvt_pk_bf16_f32 v169, v82, v83 + v_cvt_pk_bf16_f32 v168, v84, v85 + v_cvt_pk_bf16_f32 v167, v86, v87 + v_cvt_pk_bf16_f32 v166, v88, v89 + v_cvt_pk_bf16_f32 v165, v90, v91 + v_cvt_pk_bf16_f32 v164, v92, v93 + v_cvt_pk_bf16_f32 v226, v94, v95 + v_cvt_pk_bf16_f32 v163, v64, v65 + v_cvt_pk_bf16_f32 v162, v66, v67 + v_cvt_pk_bf16_f32 v161, v68, v69 + v_cvt_pk_bf16_f32 v160, v70, v71 + v_cvt_pk_bf16_f32 v159, v72, v73 + v_cvt_pk_bf16_f32 v158, v74, v75 + v_cvt_pk_bf16_f32 v157, v76, v77 + v_cvt_pk_bf16_f32 v156, v78, v79 + v_cvt_pk_bf16_f32 v155, v48, v49 + v_cvt_pk_bf16_f32 v154, v50, v51 + v_cvt_pk_bf16_f32 v153, v52, v53 + v_cvt_pk_bf16_f32 v152, v54, v55 + v_cvt_pk_bf16_f32 v151, v56, v57 + v_cvt_pk_bf16_f32 v150, v58, v59 + v_cvt_pk_bf16_f32 v149, v60, v61 + v_cvt_pk_bf16_f32 v148, v62, v63 + v_cvt_pk_bf16_f32 v147, v28, v29 + v_cvt_pk_bf16_f32 v146, v30, v31 + v_cvt_pk_bf16_f32 v145, v32, v33 + v_cvt_pk_bf16_f32 v144, v34, v35 + v_cvt_pk_bf16_f32 v143, v36, v37 + v_cvt_pk_bf16_f32 v142, v38, v39 + v_cvt_pk_bf16_f32 v141, v40, v41 + v_cvt_pk_bf16_f32 v140, v42, v43 + v_cvt_pk_bf16_f32 v138, v2, v3 + v_cvt_pk_bf16_f32 v137, v4, v5 + v_cvt_pk_bf16_f32 v136, v6, v7 + v_writelane_b32 v255, s0, 4 + v_permlane32_swap_b32_e32 v135, v1 + v_permlane32_swap_b32_e32 v134, v0 + v_permlane32_swap_b32_e32 v242, v240 + v_permlane32_swap_b32_e32 v241, v214 + v_permlane32_swap_b32_e32 v213, v211 + v_writelane_b32 v255, s1, 5 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[0:1], vcc, s[0:1] + .loc 1 145 22 ; compile_native_aiter_afp4_recovered.py:145:22 + v_permlane32_swap_b32_e32 v212, v210 + v_accvgpr_write_b32 a1, v1 + v_accvgpr_write_b32 a0, v0 + v_permlane32_swap_b32_e32 v254, v252 + v_permlane32_swap_b32_e32 v253, v251 + v_permlane32_swap_b32_e32 v250, v248 + v_permlane32_swap_b32_e32 v249, v247 + v_permlane32_swap_b32_e32 v246, v244 + v_permlane32_swap_b32_e32 v245, v243 + v_permlane32_swap_b32_e32 v26, v24 + v_permlane32_swap_b32_e32 v25, v236 + v_permlane32_swap_b32_e32 v239, v237 + v_permlane32_swap_b32_e32 v238, v235 + v_permlane32_swap_b32_e32 v234, v232 + v_permlane32_swap_b32_e32 v233, v199 + v_permlane32_swap_b32_e32 v198, v196 + v_permlane32_swap_b32_e32 v197, v195 + v_permlane32_swap_b32_e32 v17, v223 + v_permlane32_swap_b32_e32 v225, v222 + v_permlane32_swap_b32_e32 v221, v219 + v_permlane32_swap_b32_e32 v220, v218 + v_permlane32_swap_b32_e32 v217, v215 + v_permlane32_swap_b32_e32 v216, v23 + v_permlane32_swap_b32_e32 v22, v20 + v_permlane32_swap_b32_e32 v21, v18 + v_permlane32_swap_b32_e32 v209, v206 + v_permlane32_swap_b32_e32 v207, v205 + v_permlane32_swap_b32_e32 v204, v202 + v_permlane32_swap_b32_e32 v203, v201 + v_permlane32_swap_b32_e32 v200, v230 + v_permlane32_swap_b32_e32 v231, v229 + v_permlane32_swap_b32_e32 v228, v224 + v_permlane32_swap_b32_e32 v227, v191 + v_permlane32_swap_b32_e32 v190, v188 + v_permlane32_swap_b32_e32 v189, v187 + v_permlane32_swap_b32_e32 v186, v184 + v_permlane32_swap_b32_e32 v185, v183 + v_permlane32_swap_b32_e32 v182, v180 + v_permlane32_swap_b32_e32 v181, v179 + v_permlane32_swap_b32_e32 v178, v176 + v_permlane32_swap_b32_e32 v177, v175 + v_permlane32_swap_b32_e32 v174, v172 + v_permlane32_swap_b32_e32 v173, v171 + v_permlane32_swap_b32_e32 v170, v168 + v_permlane32_swap_b32_e32 v169, v167 + v_permlane32_swap_b32_e32 v166, v164 + v_permlane32_swap_b32_e32 v165, v226 + v_permlane32_swap_b32_e32 v163, v161 + v_permlane32_swap_b32_e32 v162, v160 + v_permlane32_swap_b32_e32 v159, v157 + v_permlane32_swap_b32_e32 v158, v156 + v_permlane32_swap_b32_e32 v155, v153 + v_permlane32_swap_b32_e32 v154, v152 + v_permlane32_swap_b32_e32 v151, v149 + v_permlane32_swap_b32_e32 v150, v148 + v_permlane32_swap_b32_e32 v147, v145 + v_permlane32_swap_b32_e32 v146, v144 + v_permlane32_swap_b32_e32 v143, v141 + v_permlane32_swap_b32_e32 v142, v140 + v_permlane32_swap_b32_e32 v139, v137 + v_permlane32_swap_b32_e32 v138, v136 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[2:3], s[0:1] + s_cbranch_execz .LBB0_148 +; %bb.147: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v0, a2 + v_accvgpr_read_b32 v1, a3 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v242, off +.LBB0_148: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[2:3] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 1 + v_accvgpr_read_b32 v131, a65 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[0:1], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + v_accvgpr_write_b32 a5, v1 + v_accvgpr_write_b32 a4, v0 + v_writelane_b32 v255, s0, 6 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 7 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_150 +; %bb.149: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v0, a4 + v_accvgpr_read_b32 v1, a5 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v242, off +.LBB0_150: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 2 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[0:1], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + v_accvgpr_write_b32 a7, v1 + v_accvgpr_write_b32 a6, v0 + v_writelane_b32 v255, s0, 8 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 9 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_152 +; %bb.151: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v0, a6 + v_accvgpr_read_b32 v1, a7 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v241, off +.LBB0_152: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 3 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[4:5], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 10 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 11 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_154 +; %bb.153: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[4:5], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v241, off +.LBB0_154: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 4 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[6:7], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 12 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 13 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_156 +; %bb.155: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[6:7], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v240, off +.LBB0_156: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 5 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[8:9], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 14 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 15 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_158 +; %bb.157: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[8:9], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v240, off +.LBB0_158: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 6 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[10:11], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 16 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 17 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_160 +; %bb.159: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[10:11], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v214, off +.LBB0_160: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 7 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[12:13], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 18 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 19 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_162 +; %bb.161: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[12:13], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v214, off +.LBB0_162: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 16 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[14:15], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 20 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 21 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_164 +; %bb.163: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[14:15], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v213, off +.LBB0_164: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 17 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[0:1], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 22 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 23 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_166 +; %bb.165: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[2:3], v[0:1], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[2:3], v213, off +.LBB0_166: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 18 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[2:3], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 24 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 25 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_168 +; %bb.167: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[28:29], v[2:3], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[28:29], v212, off +.LBB0_168: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 19 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[132:133], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 26 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 27 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_170 +; %bb.169: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[28:29], v[132:133], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[28:29], v212, off +.LBB0_170: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 20 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[212:213], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 28 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 29 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_172 +; %bb.171: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[28:29], v[212:213], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[28:29], v211, off +.LBB0_172: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 21 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[28:29], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 30 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 31 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_174 +; %bb.173: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[30:31], v[28:29], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[30:31], v211, off +.LBB0_174: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 22 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[30:31], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 32 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 33 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_176 +; %bb.175: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[32:33], v[30:31], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[32:33], v210, off +.LBB0_176: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 23 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[32:33], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 34 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 35 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_178 +; %bb.177: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[34:35], v[32:33], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[34:35], v210, off +.LBB0_178: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or3_b32 v130, v19, v27, 64 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[34:35], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 36 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 37 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_180 +; %bb.179: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[36:37], v[34:35], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[36:37], v254, off +.LBB0_180: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x41, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[36:37], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + s_nop 1 + v_writelane_b32 v255, s0, 38 + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[0:1] + s_nop 0 + v_writelane_b32 v255, s1, 39 + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_182 +; %bb.181: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[38:39], v[36:37], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[38:39], v254, off +.LBB0_182: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x42, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[40:41], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[38:39], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[40:41] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_184 +; %bb.183: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[40:41], v[38:39], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[40:41], v253, off +.LBB0_184: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x43, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[42:43], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[40:41], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[42:43] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_186 +; %bb.185: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[42:43], v[40:41], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[42:43], v253, off +.LBB0_186: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x44, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[44:45], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[42:43], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[44:45] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_188 +; %bb.187: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[44:45], v[42:43], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[44:45], v252, off +.LBB0_188: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x45, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[46:47], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[44:45], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[46:47] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_190 +; %bb.189: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[46:47], v[44:45], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[46:47], v252, off +.LBB0_190: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x46, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[48:49], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[46:47], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[48:49] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_192 +; %bb.191: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[48:49], v[46:47], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[48:49], v251, off +.LBB0_192: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x47, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[50:51], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[48:49], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[50:51] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_194 +; %bb.193: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[50:51], v[48:49], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[50:51], v251, off +.LBB0_194: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x50, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[52:53], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[50:51], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[52:53] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_196 +; %bb.195: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[52:53], v[50:51], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[52:53], v250, off +.LBB0_196: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x51, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[54:55], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[52:53], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[54:55] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_198 +; %bb.197: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[54:55], v[52:53], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[54:55], v250, off +.LBB0_198: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x52, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[56:57], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[54:55], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[56:57] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_200 +; %bb.199: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[56:57], v[54:55], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[56:57], v249, off +.LBB0_200: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x53, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[58:59], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[56:57], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[58:59] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_202 +; %bb.201: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[58:59], v[56:57], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[58:59], v249, off +.LBB0_202: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x54, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[60:61], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[58:59], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[60:61] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_204 +; %bb.203: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[60:61], v[58:59], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[60:61], v248, off +.LBB0_204: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x55, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[62:63], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[60:61], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[62:63] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_206 +; %bb.205: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[62:63], v[60:61], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[62:63], v248, off +.LBB0_206: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x56, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[64:65], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[62:63], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[64:65] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_208 +; %bb.207: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[64:65], v[62:63], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[64:65], v247, off +.LBB0_208: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x57, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[66:67], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[64:65], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[66:67] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_210 +; %bb.209: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[66:67], v[64:65], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[66:67], v247, off +.LBB0_210: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x80, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[68:69], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[66:67], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[68:69] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_212 +; %bb.211: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[68:69], v[66:67], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[68:69], v246, off +.LBB0_212: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x81, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[70:71], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[68:69], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[70:71] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_214 +; %bb.213: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[70:71], v[68:69], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[70:71], v246, off +.LBB0_214: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x82, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[72:73], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[70:71], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[72:73] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_216 +; %bb.215: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[72:73], v[70:71], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[72:73], v245, off +.LBB0_216: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x83, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[74:75], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[72:73], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[74:75] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_218 +; %bb.217: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[74:75], v[72:73], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[74:75], v245, off +.LBB0_218: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x84, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[76:77], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[74:75], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[76:77] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_220 +; %bb.219: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[76:77], v[74:75], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[76:77], v244, off +.LBB0_220: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x85, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[78:79], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[76:77], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[78:79] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_222 +; %bb.221: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[78:79], v[76:77], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[78:79], v244, off +.LBB0_222: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x86, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[80:81], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[78:79], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[80:81] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_224 +; %bb.223: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[80:81], v[78:79], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[80:81], v243, off +.LBB0_224: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x87, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[82:83], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[80:81], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[82:83] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_226 +; %bb.225: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[82:83], v[80:81], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[82:83], v243, off +.LBB0_226: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x90, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[84:85], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[82:83], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[84:85] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_228 +; %bb.227: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[84:85], v[82:83], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[84:85], v26, off +.LBB0_228: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x91, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[86:87], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[84:85], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[86:87] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_230 +; %bb.229: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[86:87], v[84:85], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[86:87], v26, off +.LBB0_230: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x92, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[88:89], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[86:87], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[88:89] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_232 +; %bb.231: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[26:27], v[86:87], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[26:27], v25, off +.LBB0_232: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x93, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[90:91], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[88:89], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[90:91] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_234 +; %bb.233: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[26:27], v[88:89], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[26:27], v25, off +.LBB0_234: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x94, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[92:93], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[90:91], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[92:93] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_236 +; %bb.235: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[26:27], v[90:91], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[26:27], v24, off +.LBB0_236: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x95, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[94:95], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[92:93], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[94:95] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_238 +; %bb.237: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[26:27], v[92:93], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[26:27], v24, off +.LBB0_238: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x96, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[94:95], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[96:97], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_mov_b64 s[0:1], exec + s_and_b64 s[2:3], s[0:1], s[2:3] + v_accvgpr_read_b32 v27, a63 + s_mov_b64 exec, s[2:3] + s_cbranch_execz .LBB0_240 +; %bb.239: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[94:95], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v236, off +.LBB0_240: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0x97, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[98:99], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[96:97], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[98:99] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_242 +; %bb.241: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[96:97], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v236, off +.LBB0_242: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc0, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[6:7], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[98:99], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[6:7] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_244 +; %bb.243: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[98:99], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v239, off +.LBB0_244: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc1, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[12:13], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[100:101], s[0:1], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[12:13] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_246 +; %bb.245: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[100:101], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v239, off +.LBB0_246: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc2, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[102:103], s[0:1], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[0:1], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[4:5], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[2:3], s[4:5] + s_cbranch_execz .LBB0_248 +; %bb.247: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[102:103], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v238, off +.LBB0_248: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[2:3] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc3, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[104:105], s[2:3], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[2:3], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[8:9], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[4:5], s[8:9] + s_cbranch_execz .LBB0_250 +; %bb.249: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[104:105], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v238, off +.LBB0_250: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[4:5] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc4, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[106:107], s[4:5], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[4:5], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[10:11], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[8:9], s[10:11] + s_cbranch_execz .LBB0_252 +; %bb.251: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[106:107], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v237, off +.LBB0_252: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[8:9] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc5, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[108:109], s[8:9], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[8:9], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[14:15], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[10:11], s[14:15] + s_cbranch_execz .LBB0_254 +; %bb.253: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[108:109], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v237, off +.LBB0_254: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[10:11] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc6, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[110:111], s[10:11], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[10:11], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[16:17], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[14:15], s[16:17] + s_cbranch_execz .LBB0_256 +; %bb.255: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[110:111], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v235, off +.LBB0_256: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[14:15] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xc7, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[112:113], s[14:15], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[14:15], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[18:19], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[16:17], s[18:19] + s_cbranch_execz .LBB0_258 +; %bb.257: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[112:113], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v235, off +.LBB0_258: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[16:17] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd0, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[114:115], s[16:17], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[16:17], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[20:21], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[18:19], s[20:21] + s_cbranch_execz .LBB0_260 +; %bb.259: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[114:115], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v234, off +.LBB0_260: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[18:19] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd1, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[116:117], s[18:19], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[18:19], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[22:23], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[20:21], s[22:23] + s_cbranch_execz .LBB0_262 +; %bb.261: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[116:117], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v234, off +.LBB0_262: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[20:21] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd2, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[118:119], s[20:21], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[20:21], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[24:25], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[22:23], s[24:25] + s_cbranch_execz .LBB0_264 +; %bb.263: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[118:119], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v233, off +.LBB0_264: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[22:23] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd3, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[120:121], s[22:23], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[22:23], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[26:27], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[24:25], s[26:27] + s_cbranch_execz .LBB0_266 +; %bb.265: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[120:121], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v233, off +.LBB0_266: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[24:25] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd4, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[122:123], s[24:25], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[24:25], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[28:29], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[26:27], s[28:29] + s_cbranch_execz .LBB0_268 +; %bb.267: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[122:123], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v232, off +.LBB0_268: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[26:27] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd5, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[124:125], s[26:27], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[26:27], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[28:29], s[36:37] + s_cbranch_execz .LBB0_270 +; %bb.269: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[124:125], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v232, off +.LBB0_270: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[28:29] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd6, v208 + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[126:127], s[28:29], v130, s35, 0 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[28:29], s[30:31], v[130:131] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_272 +; %bb.271: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[126:127], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v199, off +.LBB0_272: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 143 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:143:15 + v_or_b32_e32 v130, 0xd7, v208 + .loc 1 145 92 ; compile_native_aiter_afp4_recovered.py:145:92 + v_cmp_gt_i64_e64 s[30:31], s[30:31], v[130:131] + .loc 1 144 53 ; compile_native_aiter_afp4_recovered.py:144:53 + v_mad_i64_i32 v[128:129], s[36:37], v130, s35, 0 + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[30:31] + .loc 1 145 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_274 +; %bb.273: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[128:129], 1, v[192:193] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v199, off +.LBB0_274: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + v_accvgpr_read_b32 v19, a64 + .loc 1 142 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:142:15 + v_or3_b32 v26, v194, v19, 64 + .loc 1 144 22 ; compile_native_aiter_afp4_recovered.py:144:22 + v_mad_i64_i32 v[24:25], s[36:37], v26, s34, 0 + .loc 1 144 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:144:14 + v_readlane_b32 s36, v255, 0 + v_readlane_b32 s37, v255, 1 + s_nop 1 + v_lshl_add_u64 v[130:131], v[24:25], 1, s[36:37] + .loc 1 145 67 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:145:67 + v_readlane_b32 s36, v255, 2 + v_readlane_b32 s37, v255, 3 + s_nop 1 + v_cmp_gt_i64_e32 vcc, s[36:37], v[26:27] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 4 + v_readlane_b32 s37, v255, 5 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_276 +; %bb.275: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v25, a3 + v_accvgpr_read_b32 v24, a2 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[24:25], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v198, off +.LBB0_276: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 6 + v_readlane_b32 s37, v255, 7 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_278 +; %bb.277: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v25, a5 + v_accvgpr_read_b32 v24, a4 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[24:25], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v198, off +.LBB0_278: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 8 + v_readlane_b32 s37, v255, 9 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_280 +; %bb.279: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v25, a7 + v_accvgpr_read_b32 v24, a6 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[24:25], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v197, off +.LBB0_280: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 10 + v_readlane_b32 s37, v255, 11 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_282 +; %bb.281: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[4:5], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v197, off +.LBB0_282: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 12 + v_readlane_b32 s37, v255, 13 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_284 +; %bb.283: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[6:7], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v196, off +.LBB0_284: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 14 + v_readlane_b32 s37, v255, 15 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_286 +; %bb.285: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[8:9], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v196, off +.LBB0_286: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 16 + v_readlane_b32 s37, v255, 17 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_288 +; %bb.287: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[10:11], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v195, off +.LBB0_288: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 18 + v_readlane_b32 s37, v255, 19 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_290 +; %bb.289: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[12:13], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v195, off +.LBB0_290: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 20 + v_readlane_b32 s37, v255, 21 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_292 +; %bb.291: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[14:15], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v17, off +.LBB0_292: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 22 + v_readlane_b32 s37, v255, 23 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_294 +; %bb.293: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[0:1], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v17, off +.LBB0_294: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 24 + v_readlane_b32 s37, v255, 25 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_296 +; %bb.295: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[2:3], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v225, off +.LBB0_296: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 26 + v_readlane_b32 s37, v255, 27 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_298 +; %bb.297: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[132:133], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v225, off +.LBB0_298: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 28 + v_readlane_b32 s37, v255, 29 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_300 +; %bb.299: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[212:213], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v223, off +.LBB0_300: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 30 + v_readlane_b32 s37, v255, 31 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_302 +; %bb.301: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[28:29], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v223, off +.LBB0_302: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 32 + v_readlane_b32 s37, v255, 33 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_304 +; %bb.303: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[30:31], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v222, off +.LBB0_304: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 34 + v_readlane_b32 s37, v255, 35 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_306 +; %bb.305: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[32:33], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v222, off +.LBB0_306: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 36 + v_readlane_b32 s37, v255, 37 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_308 +; %bb.307: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[34:35], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v221, off +.LBB0_308: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 38 + v_readlane_b32 s37, v255, 39 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_520 +; %bb.309: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_521 +.LBB0_310: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_522 +.LBB0_311: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_523 +.LBB0_312: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_524 +.LBB0_313: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_525 +.LBB0_314: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_526 +.LBB0_315: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_527 +.LBB0_316: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_528 +.LBB0_317: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_529 +.LBB0_318: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_530 +.LBB0_319: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_531 +.LBB0_320: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_532 +.LBB0_321: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_533 +.LBB0_322: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_534 +.LBB0_323: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_535 +.LBB0_324: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_536 +.LBB0_325: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_537 +.LBB0_326: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_538 +.LBB0_327: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_539 +.LBB0_328: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_540 +.LBB0_329: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_541 +.LBB0_330: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_542 +.LBB0_331: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_543 +.LBB0_332: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_544 +.LBB0_333: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_545 +.LBB0_334: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_546 +.LBB0_335: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_547 +.LBB0_336: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_548 +.LBB0_337: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_549 +.LBB0_338: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_550 +.LBB0_339: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_551 +.LBB0_340: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_552 +.LBB0_341: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_553 +.LBB0_342: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_554 +.LBB0_343: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_555 +.LBB0_344: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_556 +.LBB0_345: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_557 +.LBB0_346: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_558 +.LBB0_347: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_559 +.LBB0_348: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_560 +.LBB0_349: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_561 +.LBB0_350: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_562 +.LBB0_351: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_563 +.LBB0_352: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_564 +.LBB0_353: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_565 +.LBB0_354: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_356 +.LBB0_355: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[128:129], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v229, off +.LBB0_356: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 142 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:142:15 + v_or_b32_e32 v26, 0x80, v16 + .loc 1 144 22 ; compile_native_aiter_afp4_recovered.py:144:22 + v_mad_i64_i32 v[18:19], s[36:37], v26, s34, 0 + .loc 1 144 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:144:14 + v_readlane_b32 s36, v255, 0 + v_readlane_b32 s37, v255, 1 + s_nop 1 + v_lshl_add_u64 v[130:131], v[18:19], 1, s[36:37] + .loc 1 145 67 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:145:67 + v_readlane_b32 s36, v255, 2 + v_readlane_b32 s37, v255, 3 + s_nop 1 + v_cmp_gt_i64_e32 vcc, s[36:37], v[26:27] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 4 + v_readlane_b32 s37, v255, 5 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_358 +; %bb.357: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a3 + v_accvgpr_read_b32 v18, a2 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v228, off +.LBB0_358: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 6 + v_readlane_b32 s37, v255, 7 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_360 +; %bb.359: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a5 + v_accvgpr_read_b32 v18, a4 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v228, off +.LBB0_360: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 8 + v_readlane_b32 s37, v255, 9 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_362 +; %bb.361: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a7 + v_accvgpr_read_b32 v18, a6 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v227, off +.LBB0_362: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 10 + v_readlane_b32 s37, v255, 11 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_364 +; %bb.363: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[4:5], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v227, off +.LBB0_364: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 12 + v_readlane_b32 s37, v255, 13 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_366 +; %bb.365: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[6:7], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v224, off +.LBB0_366: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 14 + v_readlane_b32 s37, v255, 15 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_368 +; %bb.367: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[8:9], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v224, off +.LBB0_368: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 16 + v_readlane_b32 s37, v255, 17 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_370 +; %bb.369: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[10:11], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v191, off +.LBB0_370: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 18 + v_readlane_b32 s37, v255, 19 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_372 +; %bb.371: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[12:13], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v191, off +.LBB0_372: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 20 + v_readlane_b32 s37, v255, 21 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_374 +; %bb.373: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[14:15], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v190, off +.LBB0_374: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 22 + v_readlane_b32 s37, v255, 23 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_376 +; %bb.375: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[0:1], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v190, off +.LBB0_376: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 24 + v_readlane_b32 s37, v255, 25 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_378 +; %bb.377: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[2:3], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v189, off +.LBB0_378: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 26 + v_readlane_b32 s37, v255, 27 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_380 +; %bb.379: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[132:133], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v189, off +.LBB0_380: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 28 + v_readlane_b32 s37, v255, 29 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_382 +; %bb.381: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[212:213], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v188, off +.LBB0_382: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 30 + v_readlane_b32 s37, v255, 31 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_384 +; %bb.383: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[28:29], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v188, off +.LBB0_384: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 32 + v_readlane_b32 s37, v255, 33 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_386 +; %bb.385: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[30:31], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v187, off +.LBB0_386: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 34 + v_readlane_b32 s37, v255, 35 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_388 +; %bb.387: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[32:33], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v187, off +.LBB0_388: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 36 + v_readlane_b32 s37, v255, 37 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_390 +; %bb.389: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[34:35], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v186, off +.LBB0_390: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s36, v255, 38 + v_readlane_b32 s37, v255, 39 + s_and_b64 s[38:39], vcc, s[36:37] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_566 +; %bb.391: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_567 +.LBB0_392: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_568 +.LBB0_393: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_569 +.LBB0_394: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_570 +.LBB0_395: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_571 +.LBB0_396: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_572 +.LBB0_397: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_573 +.LBB0_398: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_574 +.LBB0_399: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_575 +.LBB0_400: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_576 +.LBB0_401: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_577 +.LBB0_402: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_578 +.LBB0_403: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_579 +.LBB0_404: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_580 +.LBB0_405: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_581 +.LBB0_406: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_582 +.LBB0_407: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_583 +.LBB0_408: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_584 +.LBB0_409: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_585 +.LBB0_410: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_586 +.LBB0_411: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_587 +.LBB0_412: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_588 +.LBB0_413: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_589 +.LBB0_414: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_590 +.LBB0_415: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_591 +.LBB0_416: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_592 +.LBB0_417: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_593 +.LBB0_418: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_594 +.LBB0_419: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_595 +.LBB0_420: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_596 +.LBB0_421: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_597 +.LBB0_422: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_598 +.LBB0_423: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_599 +.LBB0_424: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_600 +.LBB0_425: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_601 +.LBB0_426: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_602 +.LBB0_427: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_603 +.LBB0_428: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_604 +.LBB0_429: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_605 +.LBB0_430: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_606 +.LBB0_431: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_607 +.LBB0_432: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_608 +.LBB0_433: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_609 +.LBB0_434: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_610 +.LBB0_435: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_611 +.LBB0_436: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_438 +.LBB0_437: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[128:129], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v226, off +.LBB0_438: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[36:37] + .loc 1 142 15 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:142:15 + v_or_b32_e32 v26, 0xc0, v16 + .loc 1 144 22 ; compile_native_aiter_afp4_recovered.py:144:22 + v_mad_i64_i32 v[16:17], s[34:35], v26, s34, 0 + .loc 1 144 14 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:144:14 + v_readlane_b32 s34, v255, 0 + v_readlane_b32 s35, v255, 1 + s_nop 1 + v_lshl_add_u64 v[16:17], v[16:17], 1, s[34:35] + .loc 1 145 67 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:145:67 + v_readlane_b32 s34, v255, 2 + v_readlane_b32 s35, v255, 3 + s_nop 1 + v_cmp_gt_i64_e32 vcc, s[34:35], v[26:27] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 4 + v_readlane_b32 s35, v255, 5 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_440 +; %bb.439: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a3 + v_accvgpr_read_b32 v18, a2 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v163, off +.LBB0_440: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 6 + v_readlane_b32 s35, v255, 7 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_442 +; %bb.441: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a5 + v_accvgpr_read_b32 v18, a4 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v163, off +.LBB0_442: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 8 + v_readlane_b32 s35, v255, 9 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_444 +; %bb.443: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + v_accvgpr_read_b32 v19, a7 + v_accvgpr_read_b32 v18, a6 + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[18:19], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v162, off +.LBB0_444: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 10 + v_readlane_b32 s35, v255, 11 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_446 +; %bb.445: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[4:5], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[4:5], v162, off +.LBB0_446: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 12 + v_readlane_b32 s35, v255, 13 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_448 +; %bb.447: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[6:7], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[4:5], v161, off +.LBB0_448: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 14 + v_readlane_b32 s35, v255, 15 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_450 +; %bb.449: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[8:9], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[4:5], v161, off +.LBB0_450: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 16 + v_readlane_b32 s35, v255, 17 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_452 +; %bb.451: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[10:11], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[4:5], v160, off +.LBB0_452: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 18 + v_readlane_b32 s35, v255, 19 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_454 +; %bb.453: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[12:13], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[4:5], v160, off +.LBB0_454: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 20 + v_readlane_b32 s35, v255, 21 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_456 +; %bb.455: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[4:5], v[14:15], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[4:5], v159, off +.LBB0_456: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 22 + v_readlane_b32 s35, v255, 23 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_458 +; %bb.457: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[0:1], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v159, off +.LBB0_458: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 24 + v_readlane_b32 s35, v255, 25 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_460 +; %bb.459: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[2:3], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v158, off +.LBB0_460: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 26 + v_readlane_b32 s35, v255, 27 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_462 +; %bb.461: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[132:133], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v158, off +.LBB0_462: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 28 + v_readlane_b32 s35, v255, 29 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_464 +; %bb.463: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[212:213], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v157, off +.LBB0_464: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 30 + v_readlane_b32 s35, v255, 31 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_466 +; %bb.465: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[28:29], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v157, off +.LBB0_466: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 32 + v_readlane_b32 s35, v255, 33 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_468 +; %bb.467: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[30:31], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v156, off +.LBB0_468: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 34 + v_readlane_b32 s35, v255, 35 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_470 +; %bb.469: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[32:33], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v156, off +.LBB0_470: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 36 + v_readlane_b32 s35, v255, 37 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_472 +; %bb.471: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[34:35], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v155, off +.LBB0_472: + .loc 1 0 5 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + v_readlane_b32 s34, v255, 38 + v_readlane_b32 s35, v255, 39 + s_and_b64 s[36:37], vcc, s[34:35] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_612 +; %bb.473: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_613 +.LBB0_474: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_614 +.LBB0_475: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_615 +.LBB0_476: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_616 +.LBB0_477: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_617 +.LBB0_478: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_618 +.LBB0_479: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_619 +.LBB0_480: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_620 +.LBB0_481: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_621 +.LBB0_482: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_622 +.LBB0_483: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_623 +.LBB0_484: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_624 +.LBB0_485: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_625 +.LBB0_486: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_626 +.LBB0_487: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_627 +.LBB0_488: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_628 +.LBB0_489: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_629 +.LBB0_490: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_630 +.LBB0_491: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_631 +.LBB0_492: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_632 +.LBB0_493: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_633 +.LBB0_494: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_634 +.LBB0_495: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_635 +.LBB0_496: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_636 +.LBB0_497: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_637 +.LBB0_498: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_638 +.LBB0_499: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_639 +.LBB0_500: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_640 +.LBB0_501: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_641 +.LBB0_502: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execnz .LBB0_642 +.LBB0_503: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[34:35], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[6:7], s[34:35] + s_cbranch_execnz .LBB0_643 +.LBB0_504: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[6:7] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[12:13], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[6:7], s[12:13] + s_cbranch_execnz .LBB0_644 +.LBB0_505: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[6:7] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[6:7], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[6:7] + s_cbranch_execnz .LBB0_645 +.LBB0_506: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_646 +.LBB0_507: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_647 +.LBB0_508: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_648 +.LBB0_509: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_649 +.LBB0_510: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_650 +.LBB0_511: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_651 +.LBB0_512: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_652 +.LBB0_513: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_653 +.LBB0_514: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_654 +.LBB0_515: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_655 +.LBB0_516: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_656 +.LBB0_517: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execnz .LBB0_657 +.LBB0_518: + .loc 1 0 5 ; compile_native_aiter_afp4_recovered.py:0:5 + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[0:1], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[2:3], s[0:1] + s_cbranch_execnz .LBB0_658 +.LBB0_519: + .loc 1 89 1 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:89:1 + s_endpgm +.LBB0_520: + .loc 1 144 14 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[36:37], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v221, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_310 +.LBB0_521: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[38:39], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v220, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_311 +.LBB0_522: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[40:41], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v220, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_312 +.LBB0_523: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[42:43], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v219, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_313 +.LBB0_524: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[44:45], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v219, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_314 +.LBB0_525: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[46:47], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v218, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_315 +.LBB0_526: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[48:49], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v218, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_316 +.LBB0_527: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[50:51], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v217, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_317 +.LBB0_528: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[52:53], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v217, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_318 +.LBB0_529: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[54:55], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v216, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_319 +.LBB0_530: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[56:57], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v216, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_320 +.LBB0_531: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[58:59], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v215, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_321 +.LBB0_532: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[60:61], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v215, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_322 +.LBB0_533: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[62:63], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v23, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_323 +.LBB0_534: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[64:65], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v23, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_324 +.LBB0_535: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[66:67], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[24:25], v22, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_325 +.LBB0_536: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[24:25], v[68:69], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[24:25], v22, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_326 +.LBB0_537: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[22:23], v[70:71], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[22:23], v21, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_327 +.LBB0_538: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[22:23], v[72:73], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[22:23], v21, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_328 +.LBB0_539: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[22:23], v[74:75], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[22:23], v20, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_329 +.LBB0_540: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[22:23], v[76:77], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[22:23], v20, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_330 +.LBB0_541: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[20:21], v[78:79], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[20:21], v18, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_331 +.LBB0_542: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[20:21], v[80:81], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[20:21], v18, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_332 +.LBB0_543: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[82:83], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v209, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_333 +.LBB0_544: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[84:85], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v209, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_334 +.LBB0_545: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[86:87], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v207, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_335 +.LBB0_546: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[88:89], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v207, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_336 +.LBB0_547: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[90:91], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v206, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_337 +.LBB0_548: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[92:93], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v206, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_338 +.LBB0_549: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[94:95], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v205, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_339 +.LBB0_550: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[96:97], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v205, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_340 +.LBB0_551: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[98:99], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v204, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_341 +.LBB0_552: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[100:101], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v204, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_342 +.LBB0_553: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[102:103], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v203, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_343 +.LBB0_554: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[104:105], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v203, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_344 +.LBB0_555: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[106:107], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v202, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_345 +.LBB0_556: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[108:109], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v202, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_346 +.LBB0_557: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[110:111], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v201, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_347 +.LBB0_558: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[112:113], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v201, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_348 +.LBB0_559: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[114:115], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v200, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_349 +.LBB0_560: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[116:117], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v200, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_350 +.LBB0_561: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[118:119], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v231, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_351 +.LBB0_562: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[120:121], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v231, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_352 +.LBB0_563: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[122:123], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v230, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_353 +.LBB0_564: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[124:125], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v230, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_354 +.LBB0_565: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[126:127], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v229, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_355 + s_branch .LBB0_356 +.LBB0_566: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[36:37], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v186, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_392 +.LBB0_567: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[38:39], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v185, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_393 +.LBB0_568: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[40:41], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v185, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_394 +.LBB0_569: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[42:43], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v184, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_395 +.LBB0_570: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[44:45], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v184, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_396 +.LBB0_571: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[46:47], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v183, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_397 +.LBB0_572: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[48:49], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v183, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_398 +.LBB0_573: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[50:51], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v182, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_399 +.LBB0_574: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[52:53], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v182, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_400 +.LBB0_575: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[54:55], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v181, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_401 +.LBB0_576: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[56:57], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v181, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_402 +.LBB0_577: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[58:59], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v180, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_403 +.LBB0_578: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[60:61], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v180, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_404 +.LBB0_579: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[62:63], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v179, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_405 +.LBB0_580: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[64:65], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v179, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_406 +.LBB0_581: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[66:67], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v178, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_407 +.LBB0_582: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[68:69], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v178, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_408 +.LBB0_583: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[70:71], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v177, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_409 +.LBB0_584: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[72:73], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v177, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_410 +.LBB0_585: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[74:75], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v176, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_411 +.LBB0_586: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[76:77], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v176, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_412 +.LBB0_587: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[78:79], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v175, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_413 +.LBB0_588: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[80:81], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v175, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_414 +.LBB0_589: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[82:83], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v174, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_415 +.LBB0_590: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[84:85], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v174, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_416 +.LBB0_591: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[86:87], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v173, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_417 +.LBB0_592: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[88:89], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v173, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_418 +.LBB0_593: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[90:91], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v172, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_419 +.LBB0_594: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[92:93], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v172, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_420 +.LBB0_595: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[94:95], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v171, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_421 +.LBB0_596: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[96:97], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v171, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_422 +.LBB0_597: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[98:99], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v170, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_423 +.LBB0_598: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[100:101], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v170, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_424 +.LBB0_599: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[102:103], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v169, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_425 +.LBB0_600: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[104:105], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v169, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_426 +.LBB0_601: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[106:107], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v168, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_427 +.LBB0_602: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[108:109], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v168, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_428 +.LBB0_603: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[110:111], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v167, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_429 +.LBB0_604: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[112:113], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v167, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_430 +.LBB0_605: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[114:115], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v166, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_431 +.LBB0_606: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[116:117], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v166, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_432 +.LBB0_607: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[118:119], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v165, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_433 +.LBB0_608: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[120:121], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v165, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_434 +.LBB0_609: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[122:123], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v164, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_435 +.LBB0_610: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[124:125], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[18:19], v164, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execz .LBB0_436 +.LBB0_611: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[18:19], v[126:127], 1, v[130:131] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[18:19], v226, off + s_or_b64 exec, exec, s[36:37] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[38:39], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[36:37], s[38:39] + s_cbranch_execnz .LBB0_437 + s_branch .LBB0_438 +.LBB0_612: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[36:37], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v155, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[40:41] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_474 +.LBB0_613: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[38:39], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v154, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[42:43] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_475 +.LBB0_614: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[40:41], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v154, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[44:45] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_476 +.LBB0_615: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[42:43], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v153, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[46:47] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_477 +.LBB0_616: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[44:45], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v153, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[48:49] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_478 +.LBB0_617: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[46:47], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v152, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[50:51] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_479 +.LBB0_618: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[48:49], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v152, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[52:53] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_480 +.LBB0_619: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[50:51], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v151, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[54:55] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_481 +.LBB0_620: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[52:53], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v151, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[56:57] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_482 +.LBB0_621: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[54:55], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v150, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[58:59] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_483 +.LBB0_622: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[56:57], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v150, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[60:61] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_484 +.LBB0_623: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[58:59], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v149, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[62:63] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_485 +.LBB0_624: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[60:61], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v149, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[64:65] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_486 +.LBB0_625: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[62:63], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v148, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[66:67] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_487 +.LBB0_626: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[64:65], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v148, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[68:69] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_488 +.LBB0_627: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[66:67], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v147, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[70:71] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_489 +.LBB0_628: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[68:69], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v147, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[72:73] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_490 +.LBB0_629: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[70:71], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v146, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[74:75] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_491 +.LBB0_630: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[72:73], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v146, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[76:77] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_492 +.LBB0_631: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[74:75], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v145, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[78:79] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_493 +.LBB0_632: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[76:77], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v145, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[80:81] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_494 +.LBB0_633: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[78:79], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v144, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[82:83] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_495 +.LBB0_634: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[80:81], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v144, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[84:85] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_496 +.LBB0_635: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[82:83], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v143, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[86:87] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_497 +.LBB0_636: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[84:85], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v143, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[88:89] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_498 +.LBB0_637: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[86:87], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v142, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[90:91] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_499 +.LBB0_638: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[88:89], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v142, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[92:93] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_500 +.LBB0_639: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[90:91], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v141, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[94:95] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_501 +.LBB0_640: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[92:93], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v141, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[96:97] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_502 +.LBB0_641: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[94:95], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v140, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[36:37], vcc, s[98:99] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[34:35], s[36:37] + s_cbranch_execz .LBB0_503 +.LBB0_642: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[96:97], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v140, off + s_or_b64 exec, exec, s[34:35] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[34:35], vcc, s[6:7] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[6:7], s[34:35] + s_cbranch_execz .LBB0_504 +.LBB0_643: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[98:99], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v139, off + s_or_b64 exec, exec, s[6:7] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[12:13], vcc, s[12:13] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[6:7], s[12:13] + s_cbranch_execz .LBB0_505 +.LBB0_644: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[100:101], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v139, off + s_or_b64 exec, exec, s[6:7] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[6:7], vcc, s[0:1] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[6:7] + s_cbranch_execz .LBB0_506 +.LBB0_645: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[102:103], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v138, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[2:3] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_507 +.LBB0_646: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[104:105], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v138, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[4:5] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_508 +.LBB0_647: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[106:107], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v137, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[8:9] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_509 +.LBB0_648: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[108:109], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v137, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[10:11] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_510 +.LBB0_649: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[110:111], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v136, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[14:15] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_511 +.LBB0_650: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[112:113], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v136, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_512 +.LBB0_651: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[114:115], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v135, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[18:19] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_513 +.LBB0_652: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[116:117], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v135, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[20:21] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_514 +.LBB0_653: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[118:119], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], v134, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[22:23] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_515 +.LBB0_654: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[120:121], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], v134, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[24:25] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_516 +.LBB0_655: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[122:123], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], a1, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[26:27] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_517 +.LBB0_656: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[124:125], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], a1, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[2:3], vcc, s[28:29] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[0:1], s[2:3] + s_cbranch_execz .LBB0_518 +.LBB0_657: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[126:127], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short v[0:1], a0, off + s_or_b64 exec, exec, s[0:1] + .loc 1 145 66 is_stmt 0 ; compile_native_aiter_afp4_recovered.py:145:66 + s_and_b64 s[0:1], vcc, s[30:31] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + s_and_saveexec_b64 s[2:3], s[0:1] + s_cbranch_execz .LBB0_519 +.LBB0_658: + .loc 1 144 14 is_stmt 1 ; compile_native_aiter_afp4_recovered.py:144:14 + v_lshl_add_u64 v[0:1], v[128:129], 1, v[16:17] + .loc 1 145 5 ; compile_native_aiter_afp4_recovered.py:145:5 + global_store_short_d16_hi v[0:1], a0, off + .loc 1 89 1 ; compile_native_aiter_afp4_recovered.py:89:1 + s_endpgm +.Ltmp23: +.Lfunc_end0: + .size _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1, .Lfunc_end0-_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 + .cfi_endproc + .section .rodata,"a",@progbits + .p2align 6, 0x0 + .amdhsa_kernel _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 + .amdhsa_group_segment_fixed_size 8192 + .amdhsa_private_segment_fixed_size 0 + .amdhsa_kernarg_size 112 + .amdhsa_user_sgpr_count 16 + .amdhsa_user_sgpr_dispatch_ptr 0 + .amdhsa_user_sgpr_queue_ptr 0 + .amdhsa_user_sgpr_kernarg_segment_ptr 1 + .amdhsa_user_sgpr_dispatch_id 0 + .amdhsa_user_sgpr_kernarg_preload_length 14 + .amdhsa_user_sgpr_kernarg_preload_offset 0 + .amdhsa_user_sgpr_private_segment_size 0 + .amdhsa_uses_dynamic_stack 0 + .amdhsa_enable_private_segment 0 + .amdhsa_system_sgpr_workgroup_id_x 1 + .amdhsa_system_sgpr_workgroup_id_y 0 + .amdhsa_system_sgpr_workgroup_id_z 0 + .amdhsa_system_sgpr_workgroup_info 0 + .amdhsa_system_vgpr_workitem_id 0 + .amdhsa_next_free_vgpr 462 + .amdhsa_next_free_sgpr 100 + .amdhsa_accum_offset 256 + .amdhsa_reserve_vcc 1 + .amdhsa_reserve_xnack_mask 1 + .amdhsa_float_round_mode_32 0 + .amdhsa_float_round_mode_16_64 0 + .amdhsa_float_denorm_mode_32 3 + .amdhsa_float_denorm_mode_16_64 3 + .amdhsa_dx10_clamp 1 + .amdhsa_ieee_mode 1 + .amdhsa_fp16_overflow 0 + .amdhsa_tg_split 0 + .amdhsa_exception_fp_ieee_invalid_op 0 + .amdhsa_exception_fp_denorm_src 0 + .amdhsa_exception_fp_ieee_div_zero 0 + .amdhsa_exception_fp_ieee_overflow 0 + .amdhsa_exception_fp_ieee_underflow 0 + .amdhsa_exception_fp_ieee_inexact 0 + .amdhsa_exception_int_div_zero 0 + .end_amdhsa_kernel + .text + ; -- End function + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.num_vgpr, 256 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.num_agpr, 206 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.numbered_sgpr, 100 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.num_named_barrier, 0 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.private_seg_size, 0 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.uses_vcc, 1 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.uses_flat_scratch, 0 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.has_dyn_sized_stack, 0 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.has_recursion, 0 + .set .L_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.has_indirect_call, 0 + .section .AMDGPU.csdata,"",@progbits +; Kernel info: +; codeLenInByte = 30840 +; TotalNumSgprs: 106 +; NumVgprs: 256 +; NumAgprs: 206 +; TotalNumVgprs: 462 +; ScratchSize: 0 +; MemoryBound: 0 +; FloatMode: 240 +; IeeeMode: 1 +; LDSByteSize: 0 bytes/workgroup (compile time only) +; SGPRBlocks: 13 +; VGPRBlocks: 57 +; NumSGPRsForWavesPerEU: 106 +; NumVGPRsForWavesPerEU: 462 +; AccumOffset: 256 +; Occupancy: 1 +; WaveLimiterHint : 0 +; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0 +; COMPUTE_PGM_RSRC2:USER_SGPR: 16 +; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0 +; COMPUTE_PGM_RSRC2:TGID_X_EN: 1 +; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0 +; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0 +; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0 +; COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: 63 +; COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: 0 + .text + .p2alignl 6, 3212836864 + .fill 256, 4, 3212836864 + .section .AMDGPU.gpr_maximums,"",@progbits + .set amdgpu.max_num_vgpr, 0 + .set amdgpu.max_num_agpr, 0 + .set amdgpu.max_num_sgpr, 0 + .set amdgpu.max_num_named_barrier, 0 + .text + .section .debug_abbrev,"",@progbits + .byte 1 ; Abbreviation Code + .byte 17 ; DW_TAG_compile_unit + .byte 1 ; DW_CHILDREN_yes + .byte 37 ; DW_AT_producer + .byte 14 ; DW_FORM_strp + .byte 19 ; DW_AT_language + .byte 5 ; DW_FORM_data2 + .byte 3 ; DW_AT_name + .byte 14 ; DW_FORM_strp + .byte 16 ; DW_AT_stmt_list + .byte 23 ; DW_FORM_sec_offset + .byte 27 ; DW_AT_comp_dir + .byte 14 ; DW_FORM_strp + .byte 17 ; DW_AT_low_pc + .byte 1 ; DW_FORM_addr + .byte 18 ; DW_AT_high_pc + .byte 6 ; DW_FORM_data4 + .byte 0 ; EOM(1) + .byte 0 ; EOM(2) + .byte 2 ; Abbreviation Code + .byte 46 ; DW_TAG_subprogram + .byte 0 ; DW_CHILDREN_no + .byte 3 ; DW_AT_name + .byte 14 ; DW_FORM_strp + .byte 32 ; DW_AT_inline + .byte 11 ; DW_FORM_data1 + .byte 0 ; EOM(1) + .byte 0 ; EOM(2) + .byte 3 ; Abbreviation Code + .byte 46 ; DW_TAG_subprogram + .byte 1 ; DW_CHILDREN_yes + .byte 17 ; DW_AT_low_pc + .byte 1 ; DW_FORM_addr + .byte 18 ; DW_AT_high_pc + .byte 6 ; DW_FORM_data4 + .byte 49 ; DW_AT_abstract_origin + .byte 19 ; DW_FORM_ref4 + .byte 0 ; EOM(1) + .byte 0 ; EOM(2) + .byte 4 ; Abbreviation Code + .byte 29 ; DW_TAG_inlined_subroutine + .byte 0 ; DW_CHILDREN_no + .byte 49 ; DW_AT_abstract_origin + .byte 19 ; DW_FORM_ref4 + .byte 17 ; DW_AT_low_pc + .byte 1 ; DW_FORM_addr + .byte 18 ; DW_AT_high_pc + .byte 6 ; DW_FORM_data4 + .byte 88 ; DW_AT_call_file + .byte 11 ; DW_FORM_data1 + .byte 89 ; DW_AT_call_line + .byte 11 ; DW_FORM_data1 + .byte 87 ; DW_AT_call_column + .byte 11 ; DW_FORM_data1 + .byte 0 ; EOM(1) + .byte 0 ; EOM(2) + .byte 5 ; Abbreviation Code + .byte 29 ; DW_TAG_inlined_subroutine + .byte 0 ; DW_CHILDREN_no + .byte 49 ; DW_AT_abstract_origin + .byte 19 ; DW_FORM_ref4 + .byte 85 ; DW_AT_ranges + .byte 23 ; DW_FORM_sec_offset + .byte 88 ; DW_AT_call_file + .byte 11 ; DW_FORM_data1 + .byte 89 ; DW_AT_call_line + .byte 11 ; DW_FORM_data1 + .byte 87 ; DW_AT_call_column + .byte 11 ; DW_FORM_data1 + .byte 0 ; EOM(1) + .byte 0 ; EOM(2) + .byte 0 ; EOM(3) + .section .debug_info,"",@progbits +.Lcu_begin0: + .long .Ldebug_info_end0-.Ldebug_info_start0 ; Length of Unit +.Ldebug_info_start0: + .short 4 ; DWARF version number + .long .debug_abbrev ; Offset Into Abbrev. Section + .byte 8 ; Address Size (in bytes) + .byte 1 ; Abbrev [1] 0xb:0x78 DW_TAG_compile_unit + .long .Linfo_string0 ; DW_AT_producer + .short 2 ; DW_AT_language + .long .Linfo_string1 ; DW_AT_name + .long .Lline_table_start0 ; DW_AT_stmt_list + .long .Linfo_string2 ; DW_AT_comp_dir + .quad .Lfunc_begin0 ; DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 ; DW_AT_high_pc + .byte 2 ; Abbrev [2] 0x2a:0x6 DW_TAG_subprogram + .long .Linfo_string3 ; DW_AT_name + .byte 1 ; DW_AT_inline + .byte 3 ; Abbrev [3] 0x30:0x52 DW_TAG_subprogram + .quad .Lfunc_begin0 ; DW_AT_low_pc + .long .Lfunc_end0-.Lfunc_begin0 ; DW_AT_high_pc + .long 42 ; DW_AT_abstract_origin + .byte 4 ; Abbrev [4] 0x41:0x14 DW_TAG_inlined_subroutine + .long 42 ; DW_AT_abstract_origin + .quad .Ltmp1 ; DW_AT_low_pc + .long .Ltmp2-.Ltmp1 ; DW_AT_high_pc + .byte 1 ; DW_AT_call_file + .byte 104 ; DW_AT_call_line + .byte 15 ; DW_AT_call_column + .byte 4 ; Abbrev [4] 0x55:0x14 DW_TAG_inlined_subroutine + .long 42 ; DW_AT_abstract_origin + .quad .Ltmp2 ; DW_AT_low_pc + .long .Ltmp3-.Ltmp2 ; DW_AT_high_pc + .byte 1 ; DW_AT_call_file + .byte 104 ; DW_AT_call_line + .byte 42 ; DW_AT_call_column + .byte 5 ; Abbrev [5] 0x69:0xc DW_TAG_inlined_subroutine + .long 42 ; DW_AT_abstract_origin + .long .Ldebug_ranges0 ; DW_AT_ranges + .byte 1 ; DW_AT_call_file + .byte 105 ; DW_AT_call_line + .byte 11 ; DW_AT_call_column + .byte 5 ; Abbrev [5] 0x75:0xc DW_TAG_inlined_subroutine + .long 42 ; DW_AT_abstract_origin + .long .Ldebug_ranges1 ; DW_AT_ranges + .byte 1 ; DW_AT_call_file + .byte 108 ; DW_AT_call_line + .byte 20 ; DW_AT_call_column + .byte 0 ; End Of Children Mark + .byte 0 ; End Of Children Mark +.Ldebug_info_end0: + .section .debug_ranges,"",@progbits +.Ldebug_ranges0: + .quad .Ltmp4-.Lfunc_begin0 + .quad .Ltmp5-.Lfunc_begin0 + .quad .Ltmp6-.Lfunc_begin0 + .quad .Ltmp7-.Lfunc_begin0 + .quad .Ltmp8-.Lfunc_begin0 + .quad .Ltmp9-.Lfunc_begin0 + .quad 0 + .quad 0 +.Ldebug_ranges1: + .quad .Ltmp7-.Lfunc_begin0 + .quad .Ltmp8-.Lfunc_begin0 + .quad .Ltmp9-.Lfunc_begin0 + .quad .Ltmp10-.Lfunc_begin0 + .quad .Ltmp11-.Lfunc_begin0 + .quad .Ltmp12-.Lfunc_begin0 + .quad .Ltmp13-.Lfunc_begin0 + .quad .Ltmp14-.Lfunc_begin0 + .quad .Ltmp15-.Lfunc_begin0 + .quad .Ltmp16-.Lfunc_begin0 + .quad .Ltmp17-.Lfunc_begin0 + .quad .Ltmp18-.Lfunc_begin0 + .quad .Ltmp19-.Lfunc_begin0 + .quad .Ltmp20-.Lfunc_begin0 + .quad 0 + .quad 0 + .section .debug_str,"MS",@progbits,1 +.Linfo_string0: + .asciz "triton" ; string offset=0 ; triton +.Linfo_string1: + .asciz "compile_native_aiter_afp4_recovered.py" ; string offset=7 ; compile_native_aiter_afp4_recovered.py +.Linfo_string2: + .asciz "/home/jincheye" ; string offset=46 ; /home/jincheye +.Linfo_string3: + .asciz "_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1" ; string offset=61 ; _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 + .section ".note.GNU-stack","",@progbits + .amdgpu_metadata +--- +custom.config: + Source: + Origin: triton + Version: 1.0.0 + Features: + SupportsUserArgs: false + SupportsBias: false + SupportsActivation: false + SupportsScaleAlpha: false + SupportsGSU: false + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: + OperationType: GEMM + DataType: F4 + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: False + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + SwizzleTensorA: False + SwizzleTensorB: False + MXBlockA: 32 + MXBlockB: 32 + CustomKernel: + args: [ { type: address, semantic: AddressA }, + { type: address, semantic: AddressB }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressMXScaleA }, + { type: address, semantic: AddressMXScaleB }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeSumDiv2 }, + { type: uint32, semantic: StrideA0Bytes }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideB0Bytes }, + { type: uint32, semantic: StrideCK }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideScaleA0 }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideScaleB0 }, + { type: uint32, semantic: ConstantOne, padding: 16 } ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesXY, One, One] + MatrixInstruction: [16, 16, 128, 1] + EnableMatrixInstruction: True + MIWaveTile: [8, 8] + AssertSummationElementMultiple: 32 + WavefrontSize: 64 +amdhsa.kernels: + - .agpr_count: 206 + .args: + - .address_space: global + .offset: 0 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 8 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 16 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 24 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 32 + .size: 8 + .value_kind: global_buffer + - .offset: 40 + .size: 4 + .value_kind: by_value + - .offset: 44 + .size: 4 + .value_kind: by_value + - .offset: 48 + .size: 4 + .value_kind: by_value + - .offset: 52 + .size: 4 + .value_kind: by_value + - .offset: 56 + .size: 4 + .value_kind: by_value + - .offset: 60 + .size: 4 + .value_kind: by_value + - .offset: 64 + .size: 4 + .value_kind: by_value + - .offset: 68 + .size: 4 + .value_kind: by_value + - .offset: 72 + .size: 4 + .value_kind: by_value + - .offset: 76 + .size: 4 + .value_kind: by_value + - .offset: 80 + .size: 4 + .value_kind: by_value + - .offset: 84 + .size: 4 + .value_kind: by_value + - .offset: 88 + .size: 4 + .value_kind: by_value + - .offset: 92 + .size: 4 + .value_kind: by_value + - .address_space: global + .offset: 96 + .size: 8 + .value_kind: global_buffer + - .address_space: global + .offset: 104 + .size: 8 + .value_kind: global_buffer + .group_segment_fixed_size: 8192 + .kernarg_segment_align: 8 + .kernarg_segment_size: 112 + .max_flat_workgroup_size: 256 + .name: _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 + .private_segment_fixed_size: 0 + .sgpr_count: 106 + .sgpr_spill_count: 40 + .symbol: _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.kd + .uniform_work_group_size: 1 + .uses_dynamic_stack: false + .vgpr_count: 462 + .vgpr_spill_count: 0 + .wavefront_size: 64 +amdhsa.target: amdgcn-amd-amdhsa--gfx950 +amdhsa.version: + - 1 + - 2 +... + + .end_amdgpu_metadata + .section .debug_line,"",@progbits +.Lline_table_start0: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml new file mode 100644 index 000000000000..b999bbf12f81 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml @@ -0,0 +1,82 @@ +TestParameters: + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + +GlobalParameters: + MinimumRequiredVersion: 5.0.0 + SleepPercent: 50 + NumElementsToValidate: -1 + DataInitTypeBeta: 0 + DataInitTypeAlpha: 1 + DataInitTypeA: 3 + DataInitTypeB: 3 + CSVExportWinner: 1 + CSVMergeSameProblemID: 1 + Device: 0 + ValidateMetadata: True + +BenchmarkProblems: + - + - # ProblemType + OperationType: GEMM + DataType: F4 + DestDataType: b + ComputeDataType: s + HighPrecisionAccumulate: True + TransposeA: 1 + TransposeB: 0 + UseBeta: False + Batched: True + UseBias: 0 + Activation: False + UseScaleAlphaVec: 0 + SwizzleTensorA: False + SwizzleTensorB: False + MXBlockA: 32 + MXBlockB: 32 + + - # BenchmarkProblemSizeGroup + InitialSolutionParameters: + BenchmarkCommonParameters: + - KernelLanguage: ["Assembly"] + ForkParameters: + - CustomKernel: + - name: "_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1" + args: [ { type: address, semantic: AddressA }, + { type: address, semantic: AddressB }, + { type: address, semantic: AddressD }, + { type: address, semantic: AddressMXScaleA }, + { type: address, semantic: AddressMXScaleB }, + { type: uint32, semantic: SizeFree0 }, + { type: uint32, semantic: SizeFree1 }, + { type: uint32, semantic: SizeSumDiv2 }, + { type: uint32, semantic: StrideA0Bytes }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideB0Bytes }, + { type: uint32, semantic: StrideCK }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideD0 }, + { type: uint32, semantic: StrideScaleA0 }, + { type: uint32, semantic: ConstantOne }, + { type: uint32, semantic: StrideScaleB0 }, + { type: uint32, semantic: ConstantOne, padding: 16 } ] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesXY, One, One] + - MatrixInstruction: + - [16, 16, 128, 1, 1, 8, 8, 2, 2] + - PreloadKernArgs: [False] + - DepthU: [64] + - AssertSummationElementMultiple: [32] + - WorkGroupMappingXCC: [8] + - GlobalSplitU: [1] + BenchmarkJoinParameters: + BenchmarkFinalParameters: + - ProblemSizes: + - Exact: [4096, 4096, 1, 8192] + +LibraryLogic: + ScheduleName: "gfx950" + DeviceNames: ["Device 0049", "Device 0050"] + ArchitectureName: "gfx950" + LibraryType: "GridBased" diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index ed424ab282e3..af6a5ff7cbf1 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -62,6 +62,7 @@ namespace TensileLite X_MACRO(SizeFree2) \ X_MACRO(SizeFree3) \ X_MACRO(SizeSum) \ + X_MACRO(SizeSumDiv2) \ X_MACRO(SizeSum1) \ X_MACRO(SizeSum2) \ X_MACRO(StrideA0) \ @@ -88,11 +89,14 @@ namespace TensileLite X_MACRO(StrideD0Bytes) \ X_MACRO(StrideMetadata0) \ X_MACRO(StrideMetadata1) \ + X_MACRO(StrideCK) \ X_MACRO(Alpha) \ X_MACRO(Beta) \ X_MACRO(SplitK) \ X_MACRO(OutputBF16) \ X_MACRO(Padding) \ + X_MACRO(ConstantZero) \ + X_MACRO(ConstantOne) \ X_MACRO(DebugPattern) \ /* Pointer args */ \ X_MACRO(AddressA) \ diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 3407ed7d24ec..74cede7538fc 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -2053,6 +2053,9 @@ namespace TensileLite case CustomArgSemantic::SizeSum: rv.args.appendCustomType("SizeSum", problem.problemSizes()[problem.problemSizes().size() - 1], arg.type); break; + case CustomArgSemantic::SizeSumDiv2: + rv.args.appendCustomType("SizeSumDiv2", problem.problemSizes()[problem.problemSizes().size() - 1] / 2, arg.type); + break; case CustomArgSemantic::SizeSum1: rv.args.appendCustomType("SizeSum1", problem.problemSizes()[problem.problemSizes().size() - 2], arg.type); break; @@ -2163,6 +2166,14 @@ namespace TensileLite case CustomArgSemantic::StrideMetadata1: rv.args.appendCustomType("StrideMetadata1", problem.metadata().strides()[2], arg.type); break; + case CustomArgSemantic::StrideCK: + { + size_t splitKStride = 0; + if(gsu > 1) + splitKStride = problem.d().sizes()[0] * problem.d().sizes()[1]; + rv.args.appendCustomType("StrideCK", splitKStride, arg.type); + break; + } case CustomArgSemantic::Alpha: rv.args.append("Alpha", inputs.alpha, problem.alphaType()); if(problem.alphaType() == rocisa::DataType::Half) @@ -2195,6 +2206,12 @@ namespace TensileLite case CustomArgSemantic::Padding: rv.args.template append("Padding", 0); break; + case CustomArgSemantic::ConstantZero: + rv.args.appendCustomType("ConstantZero", 0, arg.type); + break; + case CustomArgSemantic::ConstantOne: + rv.args.appendCustomType("ConstantOne", 1, arg.type); + break; case CustomArgSemantic::DebugPattern: rv.args.template append("DebugPattern", debugPattern); ++debugPattern; From 33d16b2bbdc5c52c11c80de7fbc21feb4a0782a1 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Tue, 16 Jun 2026 01:58:40 -0500 Subject: [PATCH 35/58] Fix unit test regressions --- .../unit/test_custom_kernel_occupancy.py | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_occupancy.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_occupancy.py index d445116e6f49..4862c931a26c 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_occupancy.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_occupancy.py @@ -44,6 +44,15 @@ # helpers # --------------------------------------------------------------------------- +def _custom_kernel_files(pattern): + return sorted(_CUSTOM_KERNEL_DIR.rglob(pattern)) + + +def _find_custom_kernel(stem): + matches = _custom_kernel_files(f"{stem}.s") + return matches[0] if matches else None + + def _make_asm(next_free_vgpr, next_free_sgpr, group_seg_size, accum_offset=None, kernel_name="test_kernel"): """Return a minimal .amdhsa_kernel block with the given directives.""" @@ -252,9 +261,9 @@ class TestComputeOccupancyRealCustomKernels: ids=[c[0].split("Custom_")[1][:40] for c in _CASES]) def test_real_kernel_occupancy(self, stem, isa, threads, expected): """Parser on a real .s file should return the expected occupancy.""" - s_path = _CUSTOM_KERNEL_DIR / f"{stem}.s" - if not s_path.exists(): - pytest.skip(f"File not found: {s_path.name}") + s_path = _find_custom_kernel(stem) + if s_path is None: + pytest.skip(f"File not found: {stem}.s") asm_source = s_path.read_text() kernel = {"ISA": list(isa), "NumThreads": threads, "KernelLanguage": "Assembly"} @@ -271,7 +280,7 @@ def test_real_kernel_occupancy(self, stem, isa, threads, expected): def test_all_gfx950_kernels_have_positive_occupancy(self): """Every gfx950 custom .s file should yield CUOccupancy >= 1 (never None/-1).""" - files = sorted(_CUSTOM_KERNEL_DIR.glob("*gfx950*.s")) + files = _custom_kernel_files("*gfx950*.s") assert len(files) > 0, "No gfx950 custom kernels found in CustomKernels/" for f in files: asm = f.read_text() @@ -282,7 +291,7 @@ def test_all_gfx950_kernels_have_positive_occupancy(self): def test_all_gfx942_kernels_have_positive_occupancy(self): """Every gfx942 custom .s file should yield CUOccupancy >= 1 (never None/-1).""" - files = sorted(_CUSTOM_KERNEL_DIR.glob("*gfx942*.s")) + files = _custom_kernel_files("*gfx942*.s") assert len(files) > 0, "No gfx942 custom kernels found in CustomKernels/" for f in files: asm = f.read_text() From 2dd945f85378a96f586b8469d9ea7942bd339569 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 8 Jul 2026 22:39:14 +0000 Subject: [PATCH 36/58] Fix test regressions --- .../tensilelite/Tensile/KernelWriter.py | 5 ++++- .../Tensile/Tests/custom/custom_aiter_bf16.yaml | 16 ++++++++-------- .../Tensile/Tests/custom/custom_aiter_f4.yaml | 16 ++++++++-------- .../Tensile/Tests/custom/custom_ck.yaml | 8 ++++---- .../Tensile/Tests/custom/custom_rr.yaml | 16 ++++++++-------- .../Tensile/Tests/custom/custom_tensile_sk.yaml | 9 ++++----- .../Tensile/Tests/custom/custom_triton_f4.yaml | 8 ++++---- .../Tensile/Tests/custom/custom_wave_bf16.yaml | 16 ++++++++-------- .../tensilelite/src/ContractionSolution.cpp | 12 +++++++++++- .../hipblaslt/tensilelite/tests/CuCount_test.cpp | 1 + 10 files changed, 60 insertions(+), 47 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py index 6c0e95723b5e..54d4617acc12 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py @@ -10815,7 +10815,10 @@ def _reg(argType, semantic, index=0): _reg("address", "AmaxSync") # -- MBSK (MultipleBufferSingleKernel) ------------------------------------- - if kernel["GlobalSplitUAlgorithm"] == 'MultipleBufferSingleKernel': + # Must match the canonical condition used by Signature.py and elsewhere in + # this file (e.g. the ExpertSchedulingMode gate above): AdaptiveGemmGSUA=1 + # also requires these trailing args, even for plain MultipleBuffer mode. + if kernel["GlobalSplitUAlgorithm"] == 'MultipleBufferSingleKernel' or kernel["AdaptiveGemmGSUA"] == 1: _reg("address", "AddressTD") _reg("address", "Synchronizer") _reg("uint32", "GSUSync") diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index e5f5d6d89b68..aa94d6d81937 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: b ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: True Batched: True UseBias: 0 @@ -84,17 +84,17 @@ BenchmarkProblems: - WorkGroupMappingXCCGroup: [-1] - GlobalSplitU: [1] - GlobalSplitUAlgorithm: ["MultipleBuffer"] - - GlobalReadPerMfma: [1] + - GlobalReadPerMfma: [1.0] - LocalWritePerMfma: [-1] - StoreRemapVectorWidth: [0] - StoreVectorWidth: [-1] - - SourceSwap: [1] + - SourceSwap: [true] - NumElementsPerBatchStore: [16] - ClusterLocalRead: [1] - NonTemporalA: [0] - NonTemporalB: [0] - - DirectToVgprA: [1] - - DirectToVgprB: [0] + - DirectToVgprA: [true] + - DirectToVgprB: [false] BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml index 721d85174568..7bc7aaa6e35b 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: b ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: True Batched: True UseBias: 0 @@ -93,17 +93,17 @@ BenchmarkProblems: - WorkGroupMappingXCCGroup: [-1] - GlobalSplitU: [1] - GlobalSplitUAlgorithm: ["MultipleBuffer"] - - GlobalReadPerMfma: [1] + - GlobalReadPerMfma: [1.0] - LocalWritePerMfma: [-1] - StoreRemapVectorWidth: [0] - StoreVectorWidth: [-1] - - SourceSwap: [1] + - SourceSwap: [true] - NumElementsPerBatchStore: [16] - ClusterLocalRead: [1] - NonTemporalA: [0] - NonTemporalB: [0] - - DirectToVgprA: [1] - - DirectToVgprB: [0] + - DirectToVgprA: [true] + - DirectToVgprB: [false] BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index b47a8b512498..7a7f96225b20 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: h ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: True Batched: True UseBias: 0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index e362f669b8e2..9caaaeea8a81 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: h ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: True Batched: True UseBias: 0 @@ -78,17 +78,17 @@ BenchmarkProblems: - WorkGroupMappingXCCGroup: [-1] - GlobalSplitU: [1] - GlobalSplitUAlgorithm: ["MultipleBuffer"] - - GlobalReadPerMfma: [1] + - GlobalReadPerMfma: [1.0] - LocalWritePerMfma: [-1] - StoreRemapVectorWidth: [0] - StoreVectorWidth: [-1] - - SourceSwap: [1] + - SourceSwap: [true] - NumElementsPerBatchStore: [16] - ClusterLocalRead: [1] - NonTemporalA: [0] - NonTemporalB: [0] - - DirectToVgprA: [1] - - DirectToVgprB: [0] + - DirectToVgprA: [true] + - DirectToVgprB: [false] BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml index e16c13c66712..5aa6a512df64 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml @@ -9,9 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - NewClient: 2 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 PrintSolutionRejectionReason: True ValidateMetadata: True @@ -24,8 +23,8 @@ BenchmarkProblems: DestDataType: h ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 0 - TransposeB: 1 + TransposeA: false + TransposeB: true UseBeta: True Batched: True UseBias: 0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml index b999bbf12f81..1cb179e7bb86 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: b ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: False Batched: True UseBias: 0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml index 76eaca9e23cf..4a1725e3824d 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml @@ -9,8 +9,8 @@ GlobalParameters: DataInitTypeAlpha: 1 DataInitTypeA: 3 DataInitTypeB: 3 - CSVExportWinner: 1 - CSVMergeSameProblemID: 1 + CSVExportWinner: true + CSVMergeSameProblemID: true Device: 0 ValidateMetadata: True @@ -22,8 +22,8 @@ BenchmarkProblems: DestDataType: s ComputeDataType: s HighPrecisionAccumulate: True - TransposeA: 1 - TransposeB: 0 + TransposeA: true + TransposeB: false UseBeta: True Batched: True UseBias: 0 @@ -72,17 +72,17 @@ BenchmarkProblems: - WorkGroupMappingXCCGroup: [-1] - GlobalSplitU: [1] - GlobalSplitUAlgorithm: ["MultipleBuffer"] - - GlobalReadPerMfma: [1] + - GlobalReadPerMfma: [1.0] - LocalWritePerMfma: [-1] - StoreRemapVectorWidth: [0] - StoreVectorWidth: [-1] - - SourceSwap: [1] + - SourceSwap: [true] - NumElementsPerBatchStore: [16] - ClusterLocalRead: [1] - NonTemporalA: [0] - NonTemporalB: [0] - - DirectToVgprA: [1] - - DirectToVgprB: [0] + - DirectToVgprA: [true] + - DirectToVgprB: [false] BenchmarkJoinParameters: BenchmarkFinalParameters: - ProblemSizes: diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index fbb4c2e6f3be..863534c831f5 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1969,6 +1969,10 @@ namespace TensileLite uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); uint32_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : autoGsuVal; + // Runtime-effective accumulation mode; AdaptiveGemmGSUA can downgrade this from + // the solution's compiled sizeMapping.globalAccumulation (e.g. MBSK -> MultipleBuffer + // for small/low-tile problems). + size_t adaptiveGlobalAccumulation = problem.getAccumulation(hardware, sizeMapping, gsu); uint32_t skItersPerTile = 0; uint32_t skTotalIters = 0; @@ -2428,9 +2432,15 @@ namespace TensileLite rv.args.template append("AmaxWS", inputs.ws); break; case CustomArgSemantic::AmaxSync: - case CustomArgSemantic::Synchronizer: rv.args.template append(toString(arg.semantic), inputs.Synchronizer); break; + case CustomArgSemantic::Synchronizer: + // Real buffer only in MBSK mode; otherwise the reduction happens in a + // separate kernel and the pointer must be null. + rv.args.template append( + "Synchronizer", + adaptiveGlobalAccumulation == 3 ? inputs.Synchronizer : nullptr); + break; case CustomArgSemantic::DebugBuffer: rv.args.template append("DebugBuffer", nullptr); break; diff --git a/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp b/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp index f6dd955b2a92..01d9fced9add 100644 --- a/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp +++ b/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp @@ -326,6 +326,7 @@ namespace kGfx950AnalyticalCuCount, 163840, 8, + 1, 1.0, 1.0, 1.0, From db160dc1dc116325dd671a8cfd19df55157fbf7d Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Sat, 11 Jul 2026 03:08:00 +0000 Subject: [PATCH 37/58] Revert change of CuCount_test --- projects/hipblaslt/tensilelite/tests/CuCount_test.cpp | 1 - 1 file changed, 1 deletion(-) diff --git a/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp b/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp index dcb3401e318b..3307bad84089 100644 --- a/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp +++ b/projects/hipblaslt/tensilelite/tests/CuCount_test.cpp @@ -327,7 +327,6 @@ namespace 163840, 262144, // rf_capacity: 65536 regs * 4 bytes 8, - 1, 1.0, 1.0, 1.0, From 6e6f3f4e4e5ac7e00766cc58b9ebb3516317d0c7 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Sat, 11 Jul 2026 04:01:22 +0000 Subject: [PATCH 38/58] Fix test_custom_kernels_char --- .../test_custom_kernels_char.ambr | 27 +++----- .../CustomKernels/test_custom_kernels_char.py | 37 ++++++++-- .../Tests/unit/characterization/DECISIONS.md | 52 +++++++++++++- ...02-custom-kernels-embedded-yaml-parsing.md | 68 +++++++++++++++++++ 4 files changed, 159 insertions(+), 25 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/adr/0002-custom-kernels-embedded-yaml-parsing.md diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/__snapshots__/test_custom_kernels_char.ambr b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/__snapshots__/test_custom_kernels_char.ambr index c32aa4dd0056..98110a8c0983 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/__snapshots__/test_custom_kernels_char.ambr +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/__snapshots__/test_custom_kernels_char.ambr @@ -5,24 +5,6 @@ 'beta', ]) # --- -# name: test_get_config_and_assembly_split - dict({ - 'assembly': ''' - s_nop 0 - s_endpgm - - ''', - 'config': ''' - - custom.config: - InternalSupportParams: - KernArgsVersion: 2 - - - - ''', - }) -# --- # name: test_get_custom_kernel_config_ok dict({ 'CustomKernelName': 'k', @@ -40,3 +22,12 @@ }), }) # --- +# name: test_read_embedded_yaml_parses_custom_config + dict({ + 'custom.config': dict({ + 'InternalSupportParams': dict({ + 'KernArgsVersion': 2, + }), + }), + }) +# --- diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/test_custom_kernels_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/test_custom_kernels_char.py index 58a42a0c7cb4..7ff80d4213bc 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/test_custom_kernels_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/CustomKernels/test_custom_kernels_char.py @@ -4,7 +4,7 @@ ################################################################################ """Characterization tests for ``Tensile.CustomKernels``: the custom-kernel -.s-file config/assembly parsing and validation, driven over crafted .s files in +.s-file embedded-YAML parsing and validation, driven over crafted .s files in a tmp directory.""" import contextlib @@ -16,7 +16,7 @@ getCustomKernelFilepath, getAllCustomKernelNames, getCustomKernelContents, - getCustomKernelConfigAndAssembly, + _readEmbeddedYaml, readCustomKernelConfig, getCustomKernelConfig, ) @@ -33,6 +33,28 @@ s_endpgm """ +# getCustomKernelConfig's no-explicit-CustomKernel path auto-infers one from +# amdhsa.kernels[0].args (see _buildCustomKernelFromMetadata), so -- unlike the +# other fixtures in this file -- it needs a real amdhsa.kernels entry, mirroring +# the write_kernel() helper in Tests/unit/test_CustomKernelMetadata.py. +_VALID_S_WITH_KERNEL_META = """\ +--- +custom.config: + InternalSupportParams: + KernArgsVersion: 2 +amdhsa.kernels: + - .name: k + .max_flat_workgroup_size: 256 + .args: + - .name: D + .size: 8 + .offset: 0 + .value_kind: global_buffer +... +s_nop 0 +s_endpgm +""" + def _write(d, name, contents): p = d / (name + ".s") @@ -81,10 +103,13 @@ def test_get_custom_kernel_contents_missing_raises(tmp_path): getCustomKernelContents("nope", directory=str(tmp_path)) -def test_get_config_and_assembly_split(tmp_path, snapshot): +def test_read_embedded_yaml_parses_custom_config(tmp_path, snapshot): + # getCustomKernelConfigAndAssembly (raw '---'/'...' line-splitter, returning + # a (config_text, assembly_text) tuple) was replaced by _readEmbeddedYaml + # (parses the .amdgpu_metadata YAML block and returns the parsed dict) as + # part of Gemm-From-Anywhere; see adr/0002-custom-kernels-embedded-yaml-parsing.md. _write(tmp_path, "k", _VALID_S) - config, assembly = getCustomKernelConfigAndAssembly("k", directory=str(tmp_path)) - assert {"config": config, "assembly": assembly} == snapshot + assert _readEmbeddedYaml("k", directory=str(tmp_path)) == snapshot def test_read_custom_kernel_config_ok(tmp_path, snapshot): @@ -99,7 +124,7 @@ def test_read_custom_kernel_config_bad_yaml_raises(tmp_path): def test_get_custom_kernel_config_ok(tmp_path, snapshot): - _write(tmp_path, "k", _VALID_S) + _write(tmp_path, "k", _VALID_S_WITH_KERNEL_META) with _isolate_valid_parameters(): cfg = getCustomKernelConfig("k", {"Extra": 9}, directory=str(tmp_path)) assert { diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md index 505ca066d3c0..71dc867e5f4e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md @@ -346,4 +346,54 @@ No other equivalent mutants are accepted yet; widening rounds append their accepted equivalents/pragmas here, each with its one-line reason. ## D16 — BufferLoad/BufferStore promoted to Required Parameters -**Context** kernel basename hash changes across all archs; assembly verified unchanged/correct; no err or kernel-count changes." \ No newline at end of file +**Context** kernel basename hash changes across all archs; assembly verified unchanged/correct; no err or kernel-count changes." + +## D17 — CustomKernels: re-target at `_readEmbeddedYaml` after Gemm-From-Anywhere removed `getCustomKernelConfigAndAssembly` + +**ADR:** [`adr/0002-custom-kernels-embedded-yaml-parsing.md`](adr/0002-custom-kernels-embedded-yaml-parsing.md). + +**Context:** `test_custom_kernels_char.py` (added on `develop` by #7989) pinned +`getCustomKernelConfigAndAssembly`, a raw `---`/`...` line-splitter returning +`(config_text, assembly_text)`. The Gemm-From-Anywhere branch's rewrite of +`CustomKernels.py` (proper `.amdgpu_metadata` YAML parsing for the external- +kernel `custom.config` schema) dropped that function in favor of a private +`_readEmbeddedYaml` returning a parsed dict — the two branches diverged before +#7989 merged to `develop`, so this was never reconciled. The stale import +caused a pytest **collection** error, which (per pytest's default behavior) +aborted the entire `-m unit` run before any test executed — silently hiding +every other test in the suite behind this one file, not just this module. + +**Decision:** Point the test at the real replacement (`_readEmbeddedYaml`, +pinning its parsed-dict return) instead of restoring the removed function. +Also gave `test_get_custom_kernel_config_ok` its own fixture with a minimal +`amdhsa.kernels` entry (`_VALID_S_WITH_KERNEL_META`), matching the convention +in `Tests/unit/test_CustomKernelMetadata.py::write_kernel`, since +`getCustomKernelConfig`'s new no-explicit-`CustomKernel` auto-infer path +requires one (real kernel `.s` files always have one; only the bare-minimum +test fixture didn't). + +**Why:** Same-purpose replacement (pin how the module reads its embedded +YAML), not a scope cut; add-only (no production code touched); private-helper +characterization already has precedent in this same branch +(`test_CustomKernelMetadata.py` imports `_parse_tensile_yaml`/`_read_asm_file` +directly). + +**Rejected alternatives:** +- *Restore `getCustomKernelConfigAndAssembly`* — rejected per explicit + direction: don't reintroduce what Gemm-From-Anywhere deliberately removed. +- *Delete the test instead of replacing it* — rejected: loses real coverage of + the embedded-YAML parsing path with no offsetting gain. + +**Validation:** `test_custom_kernels_char.py` — 11 passed, byte-identical +`.ambr` across two additional `--snapshot-update`-free re-runs. + +**Residual scope (not fixed here):** unblocking collection let the full +`-m unit` suite actually run for the first time on this branch's diff, and it +surfaced 12 pre-existing failures unrelated to this file — stale goldens in +`ValidParameters` (parameter roster: `CustomKernelName` → `CustomKernel`), +`TensileLogic/HandleCustomKernel` (`hasCustomKernel` no longer matches a bare +`CustomKernelName:` key — needs a human check for whether this is a real +detection regression on a live code path or an intentional narrowing), +`ToolchainComponent`, `TensileMain`, `TensileCreateLibraryRun`, and +`PublicInputSurface`. Each needs its own "intended vs. regression" triage +per the governance in `README.md`; tracked separately from this decision." \ No newline at end of file diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/adr/0002-custom-kernels-embedded-yaml-parsing.md b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/adr/0002-custom-kernels-embedded-yaml-parsing.md new file mode 100644 index 000000000000..bc2b8a6ca4a7 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/adr/0002-custom-kernels-embedded-yaml-parsing.md @@ -0,0 +1,68 @@ +# ADR 0002: Re-target `CustomKernels` characterization at `_readEmbeddedYaml`, not the removed `getCustomKernelConfigAndAssembly` + +Status: Accepted +Defect: none — behavior is intended + +## Context +`test_custom_kernels_char.py` (added on `develop` by #7989) pinned +`Tensile.CustomKernels.getCustomKernelConfigAndAssembly`: a naive line-scanner +that split a `.s` file on bare `---`/`...` markers and returned a +`(config_text, assembly_text)` tuple of raw strings, with blank-line padding +in `config_text` to keep YAML error line numbers aligned. + +The Gemm-From-Anywhere branch rewrote `CustomKernels.py` to parse the +`.amdgpu_metadata` YAML block properly (supporting the richer external-kernel +`custom.config` schema — `Source`, `Features`, `CustomKernel.args`, etc.) via +a new private helper, `_readEmbeddedYaml`, which returns the **parsed dict** +(typically `{"custom.config": {...}, "amdhsa.kernels": [...]}`) instead of +raw text. `getCustomKernelConfigAndAssembly` was dropped entirely; nothing in +the rewritten module still needs a raw `(config_text, assembly_text)` split. +This branch diverged from `develop` before #7989 landed there, so the two +changes were never reconciled against each other until now: the +characterization test's import of the now-nonexistent symbol failed at +collection time, which aborted the *entire* `-m unit` run (pytest halts a run +on any collection error unless `--continue-on-collection-errors` is passed), +silently hiding every other test in the suite behind it. + +Separately, fixing the import exposed that `test_get_custom_kernel_config_ok` +also relied on a minimal `_VALID_S` fixture with no `amdhsa.kernels` entry. +`getCustomKernelConfig`'s no-explicit-`CustomKernel` path (used for +Tensile-generated kernels, which per `CustomKernels/README.md` only need to +embed `InternalSupportParams.KernArgsVersion`) now auto-infers a `CustomKernel` +block from `amdhsa.kernels[0].args` via `_buildCustomKernelFromMetadata` — a +capability that does not exist on `develop`. Real kernel `.s` files always +carry a real `amdhsa.kernels` section (it is mandatory AMDGPU code-object +metadata), so this only affects the test's synthetic fixture, not production +kernels; `Tests/unit/test_CustomKernelMetadata.py`'s own `write_kernel()` +helper (added by this same branch) already includes one for exactly this +reason. + +## Decision +1. Replace the `getCustomKernelConfigAndAssembly` import/test with a new + `test_read_embedded_yaml_parses_custom_config`, pinning `_readEmbeddedYaml`'s + parsed-dict return instead of the removed raw-text split. This is a + same-purpose replacement (pin how the module reads its embedded YAML), not + a scope cut, and it does not restore any removed production code. +2. Give `test_get_custom_kernel_config_ok` its own fixture + (`_VALID_S_WITH_KERNEL_META`) carrying a minimal, realistic + `amdhsa.kernels` entry, matching the convention already established by + `write_kernel()` in `test_CustomKernelMetadata.py`, rather than enriching + the shared `_VALID_S` used by five other tests that don't need it. + +## Consequences +The suite is add-only-compatible (no production code touched) and the two +changed/added `.ambr` entries were reviewed line-by-line in the PR that +carries this ADR. `_readEmbeddedYaml` is private (`_`-prefixed); characterizing +it directly follows existing precedent in this same PR +(`test_CustomKernelMetadata.py` already imports `_parse_tensile_yaml` / +`_read_asm_file` from `Tensile.AddCustomConfig`). + +This ADR covers only the `CustomKernels` module's own collection failure. +Fixing it unblocked the rest of the `-m unit` suite to actually run (it had +never executed on this branch's diff, since the collection error aborted the +session before any test executed) and surfaced other, separate stale-golden +failures elsewhere in the suite (e.g. `ValidParameters`, `HandleCustomKernel`, +`ToolchainComponent`, `TensileMain`, `TensileCreateLibraryRun`, +`PublicInputSurface`) tracking other intentional and possibly-unintentional +behavior changes made over the life of this branch. Those are out of scope +for this ADR and are tracked separately. From a66769f88aad34de0446c3a35f06643a4d9024ae Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Sat, 11 Jul 2026 04:48:26 +0000 Subject: [PATCH 39/58] Fix regressions and add new tests --- .../TensileLogic/HandleCustomKernel.py | 8 +- .../Tests/unit/characterization/DECISIONS.md | 99 +++++++++++++++++-- .../test_pchaos_Tensile_L239_char.py | 6 ++ .../test_run_helpers_char.py | 18 +++- .../test_handlecustomkernel_char.ambr | 3 + .../test_handlecustomkernel_char.py | 9 ++ .../TensileMain/test_tensile_helpers_char.py | 13 +++ .../test_toolchain_component_char.py | 34 +++++++ .../__snapshots__/test_builders_char.ambr | 10 +- .../Tensile/Toolchain/Component.py | 6 +- 10 files changed, 190 insertions(+), 16 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py index c3e6d107920c..10fdcc5b0495 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py @@ -87,6 +87,12 @@ def hasCustomKernel(file: Path) -> bool: """ Check if the given logic file contains at least one custom kernel. + Matches both the legacy flat ``CustomKernelName: `` key and the + ``CustomKernel:`` mapping key (holding a ``name``/``args``/``macrotile``/... + block) that replaced it -- handleCustomKernel() still accepts either shape, + so this pre-filter must recognize both or it silently drops solutions from + logic files written in the older style. + Args: file: Path to a logic file. @@ -96,7 +102,7 @@ def hasCustomKernel(file: Path) -> bool: with open(file, "r") as f: for line in f: l = line.strip() - if l.startswith("name:") and not l.endswith("''"): + if l.startswith(("CustomKernelName:", "CustomKernel:")) and not l.endswith("''"): return True return False diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md index 71dc867e5f4e..7d6d80cb2f92 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/DECISIONS.md @@ -389,11 +389,94 @@ directly). **Residual scope (not fixed here):** unblocking collection let the full `-m unit` suite actually run for the first time on this branch's diff, and it -surfaced 12 pre-existing failures unrelated to this file — stale goldens in -`ValidParameters` (parameter roster: `CustomKernelName` → `CustomKernel`), -`TensileLogic/HandleCustomKernel` (`hasCustomKernel` no longer matches a bare -`CustomKernelName:` key — needs a human check for whether this is a real -detection regression on a live code path or an intentional narrowing), -`ToolchainComponent`, `TensileMain`, `TensileCreateLibraryRun`, and -`PublicInputSurface`. Each needs its own "intended vs. regression" triage -per the governance in `README.md`; tracked separately from this decision." \ No newline at end of file +surfaced 12 pre-existing failures unrelated to this file. Triaged and closed +in D18 below. + +## D18 — Triage of the 12 failures D17 unblocked: 2 real regressions fixed, 10 stale-fixture goldens/asserts updated + +**Context:** D17 fixed a pytest *collection* error that had aborted the entire +`-m unit` run before any test executed, on this branch's diff, since it +diverged from `develop`. With collection fixed, the suite ran for the first +time and surfaced 12 failures across 6 files, all in code this branch itself +touched. Each was triaged individually per the "did you intend to change this +behavior?" protocol in `README.md` — no blanket `--snapshot-update`, no +fixing-via-the-test of anything that was a real code bug. + +**Two were real regressions; fixed the source, not the tests/goldens:** + +- **`TensileLogic/HandleCustomKernel.hasCustomKernel`** — the line-scanner's + marker pattern was changed from `CustomKernelName:` (legacy flat key) to + `name:` (matching the new `CustomKernel:` mapping's nested name field), but + `handleCustomKernel()` itself still explicitly accepts *either* shape + (`sol["CustomKernel"]["name"]` or `sol.get("CustomKernelName", "")`). The + narrowed scanner is reachable from a live gating call site + (`TensileLogic/Run.py:105`, `if check.OnlyCustomKernels and + hasCustomKernel(file): ...`) that decides whether a logic file's solutions + get loaded at all under `--only-custom-kernels`-style checks — so a legacy + `CustomKernelName:`-keyed logic file would have its custom-kernel solutions + silently dropped from that check. Fixed by matching *both* + `CustomKernelName:` and `CustomKernel:` (the distinctive parent keys for + each schema — not the generic, collision-prone bare `name:`), restoring the + original (unchanged) golden's expectation. Added + `test_has_custom_kernel_true_new_style_mapping` since the new-style path had + zero prior coverage. +- **`Toolchain.Component.Assembler._retargetAssemblySource`** — new, + unconditional preprocessing step on every single assembly compile (rewrites + a mismatched `.amdgcn_target`/`amdhsa.target` directive in the source to + match the actual build target — the mechanism the `CustomKernels/README.md` + Triton section describes). It called `path.read_text()` with no handling + for a missing/unreadable file (only `UnicodeDecodeError` was caught), so any + `srcPath` that doesn't exist yet crashes `Assembler.__call__` with a + confusing traceback instead of reaching the actual compiler invocation + right after, which would raise its own clear "no such file" error through + the already-exercised `_invoke`/`CalledProcessError` path. Widened the catch + to `(UnicodeDecodeError, OSError)`. Also added + `test_retarget_assembly_source_rewrites_mismatched_target` and + `..._leaves_matching_target_untouched` — the regex rewrite itself had zero + test coverage anywhere in the repo before this. + +**Everything else was a stale test double, not a code bug — production +behavior is correct; the fixtures just don't auto-default new fields the way +their real counterparts do:** + +- **`ValidParameters::test_valid_parameters_{key_roster,structure}`** — clean, + intentional, single-line-diff changes in `Common/ValidParameters.py`: + `CustomKernelName` renamed to `CustomKernel` (matches the mapping-typed + parameter everywhere else in this branch), and + `AssertFree0/1ElementMultiple` / `AssertSummationElementMultiple` extended + with `64`/`128`/`256` (larger custom-kernel tile sizes). Updated both + goldens; reviewed the diff line-by-line (see the `.ambr` diff in the PR). +- **`TensileMain::test_arg_updated_global_parameters_*`** and + **`PublicInputSurface::test_platform_*_branch_*`** — two independently + hand-rolled fake-`args` builders (`_args()` / `_make_args()`, one using + `SimpleNamespace`, one using `argparse.Namespace` directly) both predate the + new `--validate-metadata` flag (`Tensile.py`'s `argUpdatedGlobalParameters` + now reads `args.ValidateMetadata`). A *real* `argparse` parser always + supplies a `store_true` flag's default (`False`), so this can't happen + outside a test; added `ValidateMetadata=False` to both builders. Extended + `TensileMain`'s "all overrides" test to actually cover + `ValidateMetadata=True` (previously untested) and added a explicit + default-omitted case; `PublicInputSurface`'s file is narrowly scoped to the + unrelated `platform` predicate per its own docstring, so left it at the + minimal fixture fix. +- **`TensileCreateLibraryRun::test_pass_post_kernel_info_to_solution`** — same + shape of issue: `KernelCodeGenResult` gained a `customKernelDef: + Optional[dict] = None` field (a real instance always has it via the + `NamedTuple` default), but the test's `SimpleNamespace` stand-in doesn't + auto-default missing attributes the way a `NamedTuple` does. Added + `customKernelDef=None`/`=` to the two cases and a new test, + `..._carries_custom_kernel_def`, pinning the previously-uncovered + `solution._state["CustomKernel"] = result.customKernelDef` assignment. + +**Validation:** every touched file re-run individually (all green) plus two +full, `--snapshot-update`-free `-m unit` runs of the whole suite (see the PR +description for the exact before/after counts). + +**Rejected alternatives:** +- *Blanket `--snapshot-update` across the whole suite* — forbidden by this + file's own cardinal rule; would have silently accepted the two real + regressions above instead of fixing them. +- *Leave `hasCustomKernel`/`_retargetAssemblySource` as-is and just fix the + two tests* — rejected: both are reachable from real call sites, and + "fixing" the test to assert the buggy behavior would have pinned a real + regression as if it were intended, exactly what this suite exists to catch. \ No newline at end of file diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py index 22cdf134a779..5c4799f3f244 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py @@ -45,6 +45,12 @@ def _make_args(**overrides): RuntimeLanguage=None, CodeObjectVersion=None, debug=False, + # --validate-metadata: action="store_true", so a real argparse Namespace + # always carries this (default False), unrelated to the `platform` + # predicate under test here -- see + # TensileMain/test_tensile_helpers_char.py for dedicated ValidateMetadata + # coverage. + ValidateMetadata=False, client_lock=None, prebuilt_client=None, MXScaleFormat=0, diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileCreateLibraryRun/test_run_helpers_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileCreateLibraryRun/test_run_helpers_char.py index d7c7f392f5ae..aafa54d58388 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileCreateLibraryRun/test_run_helpers_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileCreateLibraryRun/test_run_helpers_char.py @@ -147,13 +147,29 @@ def test_remove_invalid_solutions_and_kernels(monkeypatch): # --------------------------------------------------------------------------- def test_pass_post_kernel_info_to_solution(monkeypatch): monkeypatch.setattr(M, "getKernelNameMin", lambda k, split: k["name"]) - results = [SimpleNamespace(cuoccupancy=11, pgr=22, mathclk=33)] + # customKernelDef mirrors KernelCodeGenResult's `= None` NamedTuple default: + # a real result always has it (None unless the kernel was custom), so a + # SimpleNamespace standing in for one must set it explicitly. + results = [SimpleNamespace(cuoccupancy=11, pgr=22, mathclk=33, customKernelDef=None)] kernels = [{"name": "k0"}] sol = _Sol([{"name": "k0"}], state={}) M.passPostKernelInfoToSolution(results, kernels, [sol], splitGSU=False) assert sol._state["CUOccupancy"] == 11 assert sol._state["PrefetchGlobalRead"] == 22 assert sol._state["MathClocksUnrolledLoop"] == 33 + assert "CustomKernel" not in sol._state + + +def test_pass_post_kernel_info_to_solution_carries_custom_kernel_def(monkeypatch): + # When a kernel is custom, its CustomKernel definition rides along into + # solution._state so downstream library serialization can see it. + monkeypatch.setattr(M, "getKernelNameMin", lambda k, split: k["name"]) + ckDef = {"name": "k0", "args": []} + results = [SimpleNamespace(cuoccupancy=11, pgr=22, mathclk=33, customKernelDef=ckDef)] + kernels = [{"name": "k0"}] + sol = _Sol([{"name": "k0"}], state={}) + M.passPostKernelInfoToSolution(results, kernels, [sol], splitGSU=False) + assert sol._state["CustomKernel"] is ckDef # --------------------------------------------------------------------------- diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/__snapshots__/test_handlecustomkernel_char.ambr b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/__snapshots__/test_handlecustomkernel_char.ambr index aaa15eb04e98..c0555ad554f3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/__snapshots__/test_handlecustomkernel_char.ambr +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/__snapshots__/test_handlecustomkernel_char.ambr @@ -52,6 +52,9 @@ # name: test_has_custom_kernel_true True # --- +# name: test_has_custom_kernel_true_new_style_mapping + True +# --- # name: test_prepare_custom_kernel_config ''' - MatrixInstruction: [16, 16, 16, 1] diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/test_handlecustomkernel_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/test_handlecustomkernel_char.py index 05332b95b5ff..563338870598 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/test_handlecustomkernel_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileLogic/test_handlecustomkernel_char.py @@ -86,6 +86,15 @@ def test_has_custom_kernel_false_empty_name(tmp_path, snapshot): assert hasCustomKernel(f) == snapshot +def test_has_custom_kernel_true_new_style_mapping(tmp_path, snapshot): + # The CustomKernel: mapping (name/args/macrotile/...) that replaced the + # flat CustomKernelName: string must be detected too -- both are live + # inputs to handleCustomKernel(). See adr/0003-hascustomkernel-dual-schema.md. + f = tmp_path / "withck_new.yaml" + f.write_text("- foo\n CustomKernel:\n name: MyKernel\n args: []\n", encoding="utf-8") + assert hasCustomKernel(f) == snapshot + + # --- handleCustomKernel ----------------------------------------------------- def test_handle_non_custom_returns_false(snapshot): diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileMain/test_tensile_helpers_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileMain/test_tensile_helpers_char.py index 37745f31cacf..b0413ce3dafe 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileMain/test_tensile_helpers_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/TensileMain/test_tensile_helpers_char.py @@ -47,6 +47,9 @@ def test_add_common_arguments_global_parameters_eval(): def _args(**over): base = dict( platform=None, RuntimeLanguage=None, CodeObjectVersion=None, debug=False, + # --validate-metadata: action="store_true", so a real argparse Namespace + # always carries this (default False) -- kept here for the same reason. + ValidateMetadata=False, client_lock=None, prebuilt_client=None, MXScaleFormat=0, global_parameters=[], ) base.update(over) @@ -57,6 +60,7 @@ def test_arg_updated_global_parameters_all_overrides(monkeypatch): monkeypatch.delenv("PyTestBuildArchNames", raising=False) args = _args( platform=2, RuntimeLanguage="HIP", CodeObjectVersion="5", debug=True, + ValidateMetadata=True, client_lock="/lock", prebuilt_client="/client", MXScaleFormat=1, global_parameters=[("K", "V")], ) @@ -65,12 +69,21 @@ def test_arg_updated_global_parameters_all_overrides(monkeypatch): assert rv["RuntimeLanguage"] == "HIP" assert rv["CodeObjectVersion"] == "5" assert rv["CMakeBuildType"] == "Debug" + assert rv["ValidateMetadata"] is True assert rv["ClientExecutionLockPath"] == "/lock" assert rv["PrebuiltClient"] == "/client" assert rv["MXScaleFormat"] == 1 assert rv["K"] == "V" +def test_arg_updated_global_parameters_validate_metadata_false_omitted(monkeypatch): + # store_true default (False) must NOT add a ValidateMetadata override -- + # only an explicit --validate-metadata should touch globalParameters. + monkeypatch.delenv("PyTestBuildArchNames", raising=False) + rv = M.argUpdatedGlobalParameters(_args(ValidateMetadata=False)) + assert "ValidateMetadata" not in rv + + def test_arg_updated_global_parameters_empty(monkeypatch): monkeypatch.delenv("PyTestBuildArchNames", raising=False) assert M.argUpdatedGlobalParameters(_args()) == {} diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainComponent/test_toolchain_component_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainComponent/test_toolchain_component_char.py index cdc3ae81c3c3..c743a9b60c54 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainComponent/test_toolchain_component_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainComponent/test_toolchain_component_char.py @@ -136,6 +136,40 @@ def test_assembler_call_true16_and_no_wavefront64(fixed_version, captured_invoke assert "+real-true16" in args +def test_assembler_call_missing_source_does_not_crash(fixed_version, captured_invoke): + # srcPath need not exist for arg-construction purposes here (stubbed + # _invoke never touches it). _retargetAssemblySource is opportunistic and + # must not raise when the source can't be read -- the real assembler + # invocation is what should surface a genuinely-missing source, not this + # pre-processing helper. + asm = C.Assembler(Path("/x/amdclang++"), co_version="5") + asm("gfx942", 64, "does-not-exist.s", "out.o") + assert captured_invoke[0][-3:] == ["does-not-exist.s", "-o", "out.o"] + + +def test_retarget_assembly_source_rewrites_mismatched_target(tmp_path): + src = tmp_path / "k.s" + src.write_text( + '\t.amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc+:xnack-"\n' + "\tamdhsa.target: amdgcn-amd-amdhsa--gfx900:sramecc+:xnack-\n" + "s_endpgm\n" + ) + C.Assembler._retargetAssemblySource("gfx942", str(src)) + updated = src.read_text() + assert '.amdgcn_target "amdgcn-amd-amdhsa--gfx942:sramecc+:xnack-"' in updated + assert "amdhsa.target: amdgcn-amd-amdhsa--gfx942:sramecc+:xnack-" in updated + + +def test_retarget_assembly_source_leaves_matching_target_untouched(tmp_path): + src = tmp_path / "k.s" + original = '\t.amdgcn_target "amdgcn-amd-amdhsa--gfx942"\ns_endpgm\n' + src.write_text(original) + mtime_before = src.stat().st_mtime_ns + C.Assembler._retargetAssemblySource("gfx942", str(src)) + assert src.read_text() == original + assert src.stat().st_mtime_ns == mtime_before # untouched -> no write happened + + # --------------------------------------------------------------------------- # Compiler # --------------------------------------------------------------------------- diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ValidParameters/__snapshots__/test_builders_char.ambr b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ValidParameters/__snapshots__/test_builders_char.ambr index ecd821e9313e..f9d95fa1b6f4 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ValidParameters/__snapshots__/test_builders_char.ambr +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ValidParameters/__snapshots__/test_builders_char.ambr @@ -1376,7 +1376,7 @@ 'ClusterLocalRead', 'CompactLoopStore', 'ConvertAfterDS', - 'CustomKernelName', + 'CustomKernel', 'DebugPersistentKernelLoopForever', 'DebugStreamK', 'DepthU', @@ -1596,7 +1596,7 @@ 2, 4, ]), - 'len': 6, + 'len': 9, 'type': 'list', }), 'AssertFree1ElementMultiple': dict({ @@ -1605,7 +1605,7 @@ 2, 4, ]), - 'len': 6, + 'len': 9, 'type': 'list', }), 'AssertSummationElementMultiple': dict({ @@ -1614,7 +1614,7 @@ 2, 4, ]), - 'len': 8, + 'len': 9, 'type': 'list', }), 'BufferLoad': dict({ @@ -1675,7 +1675,7 @@ 'len': 2, 'type': 'list', }), - 'CustomKernelName': dict({ + 'CustomKernel': dict({ 'type': 'int', 'value': -1, }), diff --git a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py index 1d2f3cc5d42e..54299330ab40 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py +++ b/projects/hipblaslt/tensilelite/Tensile/Toolchain/Component.py @@ -164,7 +164,11 @@ def _retargetAssemblySource(targetGfx: str, srcPath: str): path = Path(srcPath) try: src = path.read_text() - except UnicodeDecodeError: + except (UnicodeDecodeError, OSError): + # Opportunistic rewrite: a source that can't be read here (missing, + # unreadable, not text) is left alone -- the assembler invocation + # right after this will raise its own clear error if srcPath is + # genuinely bad, rather than a confusing traceback from this helper. return target = f"amdgcn-amd-amdhsa--{targetGfx}" From b0aab3313051e2bd7e40c4a0331ee1c0ae44a17f Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 15 Jul 2026 05:16:42 +0000 Subject: [PATCH 40/58] Add host-side unit coverage for the flagged TensileLite modules --- .../Tests/unit/test_CustomKernelMetadata.py | 455 ++++++++++++++++++ .../Tests/unit/test_custom_kernel_cli.py | 216 +++++++++ 2 files changed, 671 insertions(+) create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py index 5bf15b316413..00c33ea7c64a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -28,7 +28,11 @@ import pytest import Tensile +import Tensile.TensileLogic.HandleCustomKernel as hck_mod from Tensile.AddCustomConfig import ( + _fmt_yaml_args, + _fmt_yaml_inline, + _fmt_yaml_scalar, _parse_tensile_yaml, _read_asm_file, build_custom_config_yaml, @@ -37,6 +41,8 @@ from Tensile.Contractions import ProblemPredicate from Tensile.Common.ValidParameters import checkParametersAreValid, validParameters from Tensile.CustomKernels import ( + _buildCustomKernelFromMetadata, + _metadataArgToCustomArg, getCustomKernelConfig, iterCustomKernelFiles, validateCustomKernelMetadata, @@ -338,3 +344,452 @@ def test_build_custom_config_yaml_emits_predicate_after_mi(): assert mi_idx < f1_idx < wf_idx assert "AssertFree0ElementMultiple: 256" in rendered assert "AssertFree1ElementMultiple: 256" in rendered + + +# --------------------------------------------------------------------------- # +# AddCustomConfig YAML formatting helpers +# --------------------------------------------------------------------------- # + + +def test_fmt_yaml_scalar_bool_none_int(): + assert _fmt_yaml_scalar(True) == "true" + assert _fmt_yaml_scalar(False) == "false" + assert _fmt_yaml_scalar(None) == "null" + assert _fmt_yaml_scalar(7) == "7" + + +def test_fmt_yaml_inline_list_dict_scalar_nested(): + assert _fmt_yaml_inline([1, 2, 3]) == "[1, 2, 3]" + assert _fmt_yaml_inline({"a": 1, "b": True}) == "{ a: 1, b: true }" + assert _fmt_yaml_inline("TilesX") == "TilesX" + assert _fmt_yaml_inline([{"k": [1, 2]}]) == "[{ k: [1, 2] }]" + + +def test_fmt_yaml_args_empty_single_multiple(): + assert _fmt_yaml_args([]) == "args: []" + + single = _fmt_yaml_args([{"type": "address", "semantic": "AddressD"}]) + assert single == " args: [ { type: address, semantic: AddressD } ]" + + three = _fmt_yaml_args([ + {"type": "address", "semantic": "AddressD"}, + {"type": "uint32", "semantic": "SizeFree0"}, + {"type": "uint32", "semantic": "SizeFree1"}, + ]) + lines = three.split("\n") + assert len(lines) == 3 + assert lines[0].startswith(" args: [ { type: address, semantic: AddressD },") + assert lines[1].strip() == "{ type: uint32, semantic: SizeFree0 }," # middle arm + assert lines[2].strip() == "{ type: uint32, semantic: SizeFree1 } ]" + + +# --------------------------------------------------------------------------- # +# build_custom_config_yaml variants +# --------------------------------------------------------------------------- # + + +def test_build_config_provenance_only(): + out = build_custom_config_yaml("aiter", None, repository="http://x", version="2.0") + assert "Origin: aiter" in out + assert "Repository: http://x" in out + assert "Version: 2.0" in out + assert "SupportsBias: false" in out + assert "KernArgsVersion: 0" in out + assert "WavefrontSize: 64" in out + assert "ProblemType:" not in out + assert "CustomKernel:" not in out + assert "MatrixInstruction:" not in out + + +def test_build_config_features_and_isp_overrides(): + config = { + "Features": {"SupportsBias": True}, + "InternalSupportParams": {"KernArgsVersion": 2, "UseUniversalArgs": True}, + "WavefrontSize": 32, + } + out = build_custom_config_yaml("wave", config) + assert "SupportsBias: true" in out + assert "SupportsUserArgs: false" in out # defaulted flag + assert "KernArgsVersion: 2" in out + assert "UseUniversalArgs: True" in out + assert "WavefrontSize: 32" in out + + +def test_build_config_mi_without_macrotile_no_enable(): + out = build_custom_config_yaml("aiter", {"MatrixInstruction": [16, 16, 16, 1]}) + assert "MatrixInstruction: [16, 16, 16, 1]" in out + assert "EnableMatrixInstruction" not in out + assert "MIWaveTile" not in out + + +def test_build_config_full_mi_emits_wavetile(): + config = { + "MatrixInstruction": [16, 16, 16, 1], + "CustomKernel": {"macrotile": [256, 256, 64], "threads": [256, 1, 1]}, + "WavefrontSize": 64, + } + out = build_custom_config_yaml("aiter", config) + assert "EnableMatrixInstruction: True" in out + assert "MIWaveTile:" in out + + +# --------------------------------------------------------------------------- # +# _parse_tensile_yaml error / edge branches +# --------------------------------------------------------------------------- # + + +def test_parse_tensile_yaml_malformed_raises(tmp_path): + p = tmp_path / "bad.yaml" + p.write_text("BenchmarkProblems: [\n") + with pytest.raises(RuntimeError, match="Failed to parse Tensile YAML"): + _parse_tensile_yaml(str(p)) + + +def test_parse_tensile_yaml_missing_benchmark_problems(tmp_path): + p = tmp_path / "nobp.yaml" + p.write_text("GlobalParameters: {}\n") + with pytest.raises(RuntimeError, match="does not contain BenchmarkProblems"): + _parse_tensile_yaml(str(p)) + + +def test_parse_tensile_yaml_no_custom_kernel(tmp_path): + p = tmp_path / "nock.yaml" + p.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - MatrixInstruction: + - [16, 16, 16, 1] + """)) + with pytest.raises(RuntimeError, match="No CustomKernel entry found"): + _parse_tensile_yaml(str(p)) + + +def test_parse_tensile_yaml_first_kernel_with_mi_and_wavefront(tmp_path): + p = tmp_path / "ok.yaml" + p.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - CustomKernel: + - name: first_kernel + args: [] + macrotile: [16, 16, 16] + threads: [64, 1, 1] + grid: [TilesX, TilesY, Batch] + - MatrixInstruction: + - [16, 16, 16, 1] + - WavefrontSize: + - 32 + """)) + + config = _parse_tensile_yaml(str(p)) # kernel_name=None -> first kernel + + assert "CustomKernel" in config + assert "name" not in config["CustomKernel"] + assert config["MatrixInstruction"] == [16, 16, 16, 1] + assert config["WavefrontSize"] == 32 + + +# --------------------------------------------------------------------------- # +# _read_asm_file detection + edges +# --------------------------------------------------------------------------- # + + +def test_read_asm_file_detects_threads_and_wavefront(tmp_path): + p = tmp_path / "k.s" + p.write_text(dedent("""\ + .amdgpu_metadata + --- + amdhsa.kernels: + - .name: k + .reqd_workgroup_size: [256, 1, 1] + .wavefront_size: 64 + ... + """)) + + info = _read_asm_file(str(p)) + + assert info["detected"]["threads"] == [256, 1, 1] + assert info["detected"]["wavefront_size"] == 64 + assert info["has_custom_config"] is False + assert info["insert_idx"] is not None + assert info["origin"] == tmp_path.name + + +def test_read_asm_file_flags_existing_custom_config(tmp_path): + p = tmp_path / "k.s" + p.write_text(dedent("""\ + .amdgpu_metadata + --- + custom.config: + InternalSupportParams: + KernArgsVersion: 0 + amdhsa.kernels: [] + ... + """)) + + assert _read_asm_file(str(p))["has_custom_config"] is True + + +def test_read_asm_file_no_metadata_section(tmp_path): + p = tmp_path / "k.s" + p.write_text("s_nop 0\ns_endpgm\n") + + info = _read_asm_file(str(p)) + + assert info["insert_idx"] is None + assert info["detected"] == {} + + +# --------------------------------------------------------------------------- # +# inject_custom_config real write + no-section +# --------------------------------------------------------------------------- # + + +def test_inject_custom_config_writes_block(tmp_path): + p = tmp_path / "k.s" + p.write_text(dedent("""\ + .amdgpu_metadata + --- + amdhsa.kernels: [] + ... + """)) + info = _read_asm_file(str(p)) + + assert inject_custom_config(info, str(p), build_custom_config_yaml("test", None)) + assert "custom.config:" in p.read_text() + + +def test_inject_custom_config_no_section_returns_false(tmp_path, capsys): + p = tmp_path / "k.s" + p.write_text("s_nop 0\n") + info = _read_asm_file(str(p)) + + assert inject_custom_config(info, str(p), "custom.config:\n x: 1") is False + assert "No .amdgpu_metadata" in capsys.readouterr().err + + +# --------------------------------------------------------------------------- # +# CustomKernels._metadataArgToCustomArg semantic mapping +# --------------------------------------------------------------------------- # + + +def _meta_arg(name, size=4, value_kind="by_value"): + return {".name": name, ".size": size, ".value_kind": value_kind} + + +def test_metadata_arg_global_buffer_is_address(): + assert _metadataArgToCustomArg(_meta_arg("D", 8, "global_buffer")) == { + "type": "address", "semantic": "AddressD" + } + + +def test_metadata_arg_size8_is_float64(): + assert _metadataArgToCustomArg(_meta_arg("beta", 8)) == { + "type": "float64", "semantic": "Beta" + } + + +def test_metadata_arg_default_uint32(): + assert _metadataArgToCustomArg(_meta_arg("alpha", 4)) == { + "type": "uint32", "semantic": "Alpha" + } + + +def test_metadata_arg_activation_index(): + assert _metadataArgToCustomArg(_meta_arg("activationAlpha", 4)) == { + "type": "float32", "semantic": "ActivationArg" + } + assert _metadataArgToCustomArg(_meta_arg("activationBeta", 8)) == { + "type": "float64", "semantic": "ActivationArg", "index": 1 + } + + +def test_metadata_arg_regex_semantics(): + assert _metadataArgToCustomArg(_meta_arg("SizesFree0"))["semantic"] == "SizeFree0" + assert _metadataArgToCustomArg(_meta_arg("SizesSum0"))["semantic"] == "SizeSum" + assert _metadataArgToCustomArg(_meta_arg("SizesSum1"))["semantic"] == "SizeSum1" + assert _metadataArgToCustomArg(_meta_arg("strideA0"))["semantic"] == "StrideA0" + assert _metadataArgToCustomArg(_meta_arg("strideMetadata0"))["semantic"] == "StrideMetadata0" + assert _metadataArgToCustomArg(_meta_arg("StrideE0"))["semantic"] == "StrideE0" + + +def test_metadata_arg_magic_size_index(): + a = _metadataArgToCustomArg(_meta_arg("MagicNumberSizeI")) + assert a["semantic"] == "MagicNumberSize" and a["index"] == 0 + b = _metadataArgToCustomArg(_meta_arg("MagicShiftSizeJ")) + assert b["semantic"] == "MagicShiftSize" and b["index"] == 1 + + +def test_metadata_arg_missing_field_raises(): + with pytest.raises(RuntimeError, match="missing required field"): + _metadataArgToCustomArg({".name": "D"}) + + +def test_metadata_arg_unknown_name_raises(): + with pytest.raises(RuntimeError, match="Unknown amdgpu_metadata arg name"): + _metadataArgToCustomArg(_meta_arg("totallyBogusArg")) + + +# --------------------------------------------------------------------------- # +# validate_all (non-strict) + validateCustomKernelMetadataAtBuild branches +# --------------------------------------------------------------------------- # + + +def test_validate_all_non_strict_reports_warnings(tmp_path): + write_kernel(tmp_path / "bad.s", """\ + Source: + Origin: test + InternalSupportParams: + KernArgsVersion: 0 + """) + + errors, warnings = validate_all(str(tmp_path), strict=False) + + assert errors == [] + assert len(warnings) == 1 + + +def test_validate_at_build_counts_issues_and_dedups(tmp_path): + write_kernel(tmp_path / "good.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + write_kernel(tmp_path / "bad.s", """\ + InternalSupportParams: {} + """) + kernels = [ + {"CustomKernel": {"name": "good"}}, + {"CustomKernel": {"name": "bad"}}, + {"CustomKernel": {"name": "good"}}, # duplicate -> validated once + {"SomethingElse": 1}, # no CustomKernel -> skipped + {"CustomKernel": {"name": ""}}, # empty name -> skipped + ] + + assert validateCustomKernelMetadataAtBuild(kernels, str(tmp_path)) == 1 + + +# --------------------------------------------------------------------------- # +# HandleCustomKernel branch coverage +# --------------------------------------------------------------------------- # + + +def test_handle_custom_kernel_uses_mapping_name(monkeypatch): + monkeypatch.setattr( + hck_mod, "getCustomKernelConfig", + lambda name, isp, directory: {"MatrixInstruction": [16, 16, 16, 1]}, + ) + sol = {"CustomKernel": {"name": "k0"}} + + out, is_custom = hck_mod.handleCustomKernel(sol, {}) + + assert is_custom is True + assert out["MatrixInstruction"] == [16, 16, 16, 1] + + +def test_handle_custom_kernel_skips_on_config_error(monkeypatch, capsys): + def _raise(name, isp, directory): + raise RuntimeError("missing custom.config") + + monkeypatch.setattr(hck_mod, "getCustomKernelConfig", _raise) + sol = {"CustomKernelName": "k0"} + + out, is_custom = hck_mod.handleCustomKernel(sol, {}) + + assert is_custom is False + assert out is sol + + +# --------------------------------------------------------------------------- # +# CustomKernels._buildCustomKernelFromMetadata: grid selection + error branches +# --------------------------------------------------------------------------- # + +_D_ARG = {".name": "D", ".size": 8, ".value_kind": "global_buffer"} +_NUMWG_ARG = {".name": "numWG", ".size": 4, ".value_kind": "by_value"} + + +def _kernel_yaml(args, name="k"): + return {"amdhsa.kernels": [{".name": name, ".max_flat_workgroup_size": 256, ".args": args}]} + + +def test_build_from_metadata_no_kernels_raises(): + with pytest.raises(RuntimeError, match="no amdhsa.kernels entries"): + _buildCustomKernelFromMetadata("k", {}, {"MatrixInstruction": [16, 16, 16, 1]}) + + +def test_build_from_metadata_no_args_raises(): + full = {"amdhsa.kernels": [{".name": "k"}]} + with pytest.raises(RuntimeError, match="no .args"): + _buildCustomKernelFromMetadata("k", full, {"MatrixInstruction": [16, 16, 16, 1]}) + + +def test_build_from_metadata_streamk_batched_grid(): + ck = _buildCustomKernelFromMetadata( + "k", _kernel_yaml([_D_ARG]), + {"MatrixInstruction": [16, 16, 16, 1], "StreamK": 2, "ProblemType": {"Batched": True}}, + ) + assert ck["grid"][0] == "StreamKWithBatch" + + +def test_build_from_metadata_numworkgroups_grid(): + ck = _buildCustomKernelFromMetadata( + "k", _kernel_yaml([_NUMWG_ARG, _D_ARG]), + {"MatrixInstruction": [16, 16, 16, 1]}, + ) + assert ck["grid"][0] == "TilesXYBatchGSU" + + +def test_build_from_metadata_default_multidim_grid(): + ck = _buildCustomKernelFromMetadata( + "k", _kernel_yaml([_D_ARG]), {"MatrixInstruction": [16, 16, 16, 1]} + ) + assert ck["grid"] == ["TilesX", "TilesY", "Batch"] + + +def test_build_from_metadata_macrotile_name_fallback(): + # No MatrixInstruction -> computed macrotile is 0, so it falls back to the + # MTxxx token parsed out of the kernel name. + ck = _buildCustomKernelFromMetadata("foo_MT128x256x64_bar", _kernel_yaml([_D_ARG]), {}) + assert ck["macrotile"] == [128, 256, 64] + + +# --------------------------------------------------------------------------- # +# validateCustomKernelMetadata edge branches +# --------------------------------------------------------------------------- # + + +def test_validate_metadata_no_custom_config_reports_unreadable(tmp_path): + p = tmp_path / "raw.s" + p.write_text(".amdgpu_metadata\n---\namdhsa.kernels: []\n...\n") # no custom.config + + valid, msg = validateCustomKernelMetadata("raw", str(tmp_path)) + + assert not valid + assert "Cannot read custom.config" in msg + + +def test_validate_metadata_internal_support_params_not_mapping(tmp_path): + write_kernel(tmp_path / "k.s", """\ + InternalSupportParams: not_a_dict + """) + + valid, msg = validateCustomKernelMetadata("k", str(tmp_path)) + + assert not valid + assert "InternalSupportParams (mapping)" in msg + + +def test_validate_metadata_custom_kernel_not_mapping(tmp_path): + write_kernel(tmp_path / "k.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + CustomKernel: not_a_dict + """) + + valid, msg = validateCustomKernelMetadata("k", str(tmp_path)) + + assert not valid + assert "CustomKernel (mapping)" in msg diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py new file mode 100644 index 000000000000..9143ea807d4b --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py @@ -0,0 +1,216 @@ +# Copyright Advanced Micro Devices, Inc., or its affiliates. +# SPDX-License-Identifier: MIT + +"""CLI-entrypoint coverage for the custom-kernel tooling: the ``main()`` +functions of ``Tensile.AddCustomConfig`` and ``Tensile.ValidateMetadata``. + +Both are driven by argparse over ``sys.argv`` and terminate via ``sys.exit``; +these tests monkeypatch ``sys.argv`` and assert exit codes + stdout/stderr, +using real .s files written into ``tmp_path``. +""" + +import sys +from textwrap import dedent, indent + +import pytest + +import Tensile.AddCustomConfig as acc +import Tensile.ValidateMetadata as vm + + +META_EMPTY = dedent("""\ + .amdgpu_metadata + --- + amdhsa.kernels: [] + ... + """) + + +def _write_kernel_s(path, config_block): + """Write a minimal custom-kernel .s file with an embedded custom.config.""" + body = indent(dedent(config_block).strip(), " ") + path.write_text( + ".amdgpu_metadata\n" + "---\n" + "custom.config:\n" + f"{body}\n" + "amdhsa.kernels:\n" + f" - .name: {path.stem}\n" + " .max_flat_workgroup_size: 64\n" + " .args:\n" + " - .name: D\n" + " .size: 8\n" + " .offset: 0\n" + " .value_kind: global_buffer\n" + "...\n" + ) + + +# --------------------------------------------------------------------------- # +# AddCustomConfig.main() +# --------------------------------------------------------------------------- # + + +def test_addcustomconfig_main_file_not_found(monkeypatch, capsys): + monkeypatch.setattr(sys, "argv", ["prog", "/no/such/file.s"]) + + with pytest.raises(SystemExit) as e: + acc.main() + + assert e.value.code == 1 + assert "File not found" in capsys.readouterr().err + + +def test_addcustomconfig_main_provenance_only_injects(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.s" + p.write_text(META_EMPTY) + monkeypatch.setattr(sys, "argv", ["prog", str(p)]) + + acc.main() # returns normally (no sys.exit on success) + + assert "custom.config:" in p.read_text() + assert "Injected custom.config" in capsys.readouterr().out + + +def test_addcustomconfig_main_dry_run_non_s_warns(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.txt" + p.write_text(META_EMPTY) + monkeypatch.setattr(sys, "argv", ["prog", str(p), "--dry-run"]) + + acc.main() + + out = capsys.readouterr() + assert "does not end with .s" in out.err + assert "custom.config block that would be inserted" in out.out + assert p.read_text() == META_EMPTY # dry-run leaves the file untouched + + +def test_addcustomconfig_main_already_has_config(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.s" + _write_kernel_s(p, """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + monkeypatch.setattr(sys, "argv", ["prog", str(p)]) + + with pytest.raises(SystemExit) as e: + acc.main() + + assert e.value.code == 1 + assert "already has a custom.config" in capsys.readouterr().err + + +def test_addcustomconfig_main_yaml_parse_error(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.s" + p.write_text(META_EMPTY) + bad_yaml = tmp_path / "bad.yaml" + bad_yaml.write_text("BenchmarkProblems: [\n") + monkeypatch.setattr(sys, "argv", ["prog", str(p), "--yaml", str(bad_yaml)]) + + with pytest.raises(SystemExit) as e: + acc.main() + + assert e.value.code == 1 + assert "ERROR" in capsys.readouterr().err + + +def test_addcustomconfig_main_read_error_exits(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.s" + p.write_text(dedent("""\ + .amdgpu_metadata + --- + custom.config: [ + ... + """)) + monkeypatch.setattr(sys, "argv", ["prog", str(p)]) + + with pytest.raises(SystemExit) as e: + acc.main() + + assert e.value.code == 1 + + +def test_addcustomconfig_main_with_yaml_injects_interface(tmp_path, monkeypatch): + # main() derives the kernel name from the .s basename, so it must match a + # CustomKernel name declared in the YAML. + p = tmp_path / "mykernel.s" + p.write_text(META_EMPTY) + y = tmp_path / "t.yaml" + y.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - CustomKernel: + - name: mykernel + args: [] + macrotile: [256, 256, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + - MatrixInstruction: + - [16, 16, 16, 1] + """)) + monkeypatch.setattr(sys, "argv", ["prog", str(p), "--yaml", str(y)]) + + acc.main() + + text = p.read_text() + assert "custom.config:" in text + assert "ProblemType:" in text + assert "CustomKernel:" in text + + +# --------------------------------------------------------------------------- # +# ValidateMetadata.main() +# --------------------------------------------------------------------------- # + + +def test_validatemetadata_main_root_not_found(monkeypatch, capsys): + monkeypatch.setattr(sys, "argv", ["prog", "--custom-kernels-root", "/no/such/dir"]) + + with pytest.raises(SystemExit) as e: + vm.main() + + assert e.value.code == 1 + assert "not found" in capsys.readouterr().err + + +def test_validatemetadata_main_clean_exits_zero(tmp_path, monkeypatch, capsys): + _write_kernel_s(tmp_path / "good.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + monkeypatch.setattr(sys, "argv", ["prog", "--custom-kernels-root", str(tmp_path)]) + + with pytest.raises(SystemExit) as e: + vm.main() + + assert e.value.code == 0 + assert "0 error(s)" in capsys.readouterr().out + + +def test_validatemetadata_main_strict_bad_exits_one(tmp_path, monkeypatch, capsys): + _write_kernel_s(tmp_path / "bad.s", """\ + InternalSupportParams: {} + """) + monkeypatch.setattr(sys, "argv", + ["prog", "--custom-kernels-root", str(tmp_path), "--strict"]) + + with pytest.raises(SystemExit) as e: + vm.main() + + assert e.value.code == 1 + assert "1 error(s)" in capsys.readouterr().out + + +def test_validatemetadata_main_non_strict_bad_exits_zero(tmp_path, monkeypatch, capsys): + _write_kernel_s(tmp_path / "bad.s", """\ + InternalSupportParams: {} + """) + monkeypatch.setattr(sys, "argv", ["prog", "--custom-kernels-root", str(tmp_path)]) + + with pytest.raises(SystemExit) as e: + vm.main() + + assert e.value.code == 0 + assert "1 warning(s)" in capsys.readouterr().out From 1201074aa4eef7a001864124981675ca736bd20b Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 15 Jul 2026 22:21:42 +0000 Subject: [PATCH 41/58] add more unit tests --- .../Tests/unit/test_custom_kernel_host.py | 217 ++++++++++++++ .../unit/test_library_io_custom_kernel.py | 110 ++++++++ .../Tests/unit/test_register_kernel_args.py | 264 ++++++++++++++++++ 3 files changed, 591 insertions(+) create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py new file mode 100644 index 000000000000..7c12b00e24af --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py @@ -0,0 +1,217 @@ +# Copyright Advanced Micro Devices, Inc., or its affiliates. +# SPDX-License-Identifier: MIT + +"""Host-side custom-kernel plumbing coverage: the pure/near-pure helpers the +custom-kernel path adds across Solution, Naming, BenchmarkProblems, and the +Toolchain assembler. + +These live in a direct ``Tests/unit`` module (not under ``characterization/``) +so the coverage lane credits them against the changed source lines. +""" + +import pytest + +from Tensile.BenchmarkProblems import _hashableProblemTypeKV +from Tensile.Common.DataType import DataType +from Tensile.SolutionStructs.Naming import _getName, getKernelFileBase +from Tensile.SolutionStructs.Solution import Solution +from Tensile.Toolchain.Component import Assembler + + +# --------------------------------------------------------------------------- # +# Solution._assignCustomKernelParameters +# --------------------------------------------------------------------------- # + + +def _ck_state(**over): + problem_type = { + "ComputeDataType": DataType("s"), + "DestDataType": DataType("s"), + "UseBias": False, + "Gradient": False, + } + problem_type.update(over.pop("ProblemType", {})) + state = { + "CustomKernel": {"name": "k", "macrotile": [128, 256, 64], "threads": [256, 1, 1]}, + "StreamK": 0, + "StreamKAtomic": 0, + "GlobalSplitUAlgorithm": "", + "ProblemType": problem_type, + "DirectToLds": 0, + "MatrixInstruction": [16, 16, 16, 1], + "WavefrontSize": 64, + } + state.update(over) + return state + + +def test_assign_custom_kernel_params_basic_derivation(): + state = _ck_state() + Solution._assignCustomKernelParameters(state) + + assert state["MacroTile0"] == 128 + assert state["MacroTile1"] == 256 + assert state["DepthU"] == 64 + assert state["NumThreads"] == 256 + assert state["NumElementsPerThread"] == (128 * 256) // 256 + assert state["CUOccupancy"] == -1 + assert state["MathClocksUnrolledLoop"] == 0 + assert state["PackedC0IndicesX"] == [] + assert state["ThreadTile0"] == 0 and state["ThreadTile1"] == 0 + assert state["LocalSplitU"] == 1 + assert state["GlobalReadVectorWidthA"] == 1 + assert state["GlobalReadVectorWidthB"] == 1 + assert state["StoreVectorWidth"] == 1 + assert state["_GlobalAccumulation"] is None # GlobalSplitUAlgorithm == "" + + +def test_assign_custom_kernel_params_enable_mi_sets_wave_params(): + state = _ck_state() + Solution._assignCustomKernelParameters(state) + + assert state["EnableMatrixInstruction"] is True + assert isinstance(state["MIWaveTile"], list) + assert isinstance(state["MIWaveGroup"], list) + + +def test_assign_custom_kernel_params_no_mi_zeroes_wave_params(): + state = _ck_state(MatrixInstruction=[]) + Solution._assignCustomKernelParameters(state) + + assert state["EnableMatrixInstruction"] is False + assert state["MIWaveTile"] == [0, 0] + assert state["MIWaveGroup"] == [0, 0] + + +@pytest.mark.parametrize("dtl,expect_a,expect_b", [ + (0, False, False), + (1, True, True), + (2, True, False), + (3, False, True), +]) +def test_assign_custom_kernel_params_direct_to_lds(dtl, expect_a, expect_b): + state = _ck_state(DirectToLds=dtl) + Solution._assignCustomKernelParameters(state) + assert state["DirectToLdsA"] is expect_a + assert state["DirectToLdsB"] is expect_b + + +def test_assign_custom_kernel_params_streamk_partials_accumulation(): + state = _ck_state(StreamK=2, StreamKAtomic=0) + Solution._assignCustomKernelParameters(state) + assert state["_GlobalAccumulation"] == "PartialsBuffer" + + +def test_assign_custom_kernel_params_single_buffer_accumulation(): + # SingleBuffer only sets accumulation when compute dtype != dest dtype. + state = _ck_state( + GlobalSplitUAlgorithm="SingleBuffer", + ProblemType={"ComputeDataType": DataType("s"), "DestDataType": DataType("h")}, + ) + Solution._assignCustomKernelParameters(state) + assert state["_GlobalAccumulation"] == "SingleBuffer" + + +def test_assign_custom_kernel_params_multiple_buffer_accumulation(): + state = _ck_state(GlobalSplitUAlgorithm="MultipleBuffer") + Solution._assignCustomKernelParameters(state) + assert state["_GlobalAccumulation"] == "MultipleBuffer" + + +def test_assign_custom_kernel_params_mbsk_accumulation(): + state = _ck_state(GlobalSplitUAlgorithm="MultipleBufferSingleKernel") + Solution._assignCustomKernelParameters(state) + assert state["_GlobalAccumulation"] == "MultipleBufferSingleKernel" + + +def test_assign_custom_kernel_params_bias_gradient_workspace(): + state = _ck_state( + ProblemType={ + "ComputeDataType": DataType("s"), "DestDataType": DataType("s"), + "UseBias": True, "Gradient": True, + }, + ) + state["CustomKernel"]["workspaceSizePerElemBias"] = 4 + Solution._assignCustomKernelParameters(state) + assert state["_WorkspaceSizePerElemBias"] == 4 + + +# --------------------------------------------------------------------------- # +# Naming: custom-kernel name short-circuits +# --------------------------------------------------------------------------- # + + +def test_get_kernel_file_base_custom_mapping_name(): + assert getKernelFileBase(False, {"CustomKernel": {"name": "my_ck"}}) == "my_ck" + + +def test_get_kernel_file_base_legacy_name(): + assert getKernelFileBase(False, {"CustomKernelName": "legacy_ck"}) == "legacy_ck" + + +def test_get_kernel_file_base_generated_falls_back_to_legacy(): + # A "generated" CustomKernel mapping is not treated as handwritten, so the + # legacy CustomKernelName wins. + kernel = {"CustomKernel": {"name": "gen", "generated": True}, "CustomKernelName": "legacy"} + assert getKernelFileBase(False, kernel) == "legacy" + + +def test_get_name_custom_mapping_name(): + assert _getName({"CustomKernel": {"name": "ck_map"}}, frozenset(), False, False) == "ck_map" + + +def test_get_name_legacy_name(): + assert _getName({"CustomKernelName": "ck_legacy"}, frozenset(), False, False) == "ck_legacy" + + +# --------------------------------------------------------------------------- # +# BenchmarkProblems._hashableProblemTypeKV +# --------------------------------------------------------------------------- # + + +def test_hashable_kv_list_becomes_tuple(): + assert _hashableProblemTypeKV("Index", [0, 1, 2]) == ("Index", (0, 1, 2)) + + +def test_hashable_kv_hashable_passthrough(): + assert _hashableProblemTypeKV("DataType", "s") == ("DataType", "s") + + +def test_hashable_kv_unhashable_uses_repr(): + key, value = _hashableProblemTypeKV("Meta", {"a": 1}) + assert key == "Meta" + assert value == repr({"a": 1}) + + +# --------------------------------------------------------------------------- # +# Toolchain.Component.Assembler._retargetAssemblySource (direct-unit coverage) +# --------------------------------------------------------------------------- # + + +def test_retarget_rewrites_mismatched_target(tmp_path): + src = tmp_path / "k.s" + src.write_text( + '\t.amdgcn_target "amdgcn-amd-amdhsa--gfx900:sramecc+:xnack-"\n' + "\tamdhsa.target: amdgcn-amd-amdhsa--gfx900:sramecc+:xnack-\n" + "s_endpgm\n" + ) + Assembler._retargetAssemblySource("gfx942", str(src)) + updated = src.read_text() + assert '.amdgcn_target "amdgcn-amd-amdhsa--gfx942:sramecc+:xnack-"' in updated + assert "amdhsa.target: amdgcn-amd-amdhsa--gfx942:sramecc+:xnack-" in updated + + +def test_retarget_leaves_matching_target_untouched(tmp_path): + src = tmp_path / "k.s" + original = '\t.amdgcn_target "amdgcn-amd-amdhsa--gfx942"\ns_endpgm\n' + src.write_text(original) + mtime_before = src.stat().st_mtime_ns + Assembler._retargetAssemblySource("gfx942", str(src)) + assert src.read_text() == original + assert src.stat().st_mtime_ns == mtime_before # no rewrite -> no write + + +def test_retarget_missing_source_does_not_raise(): + # Opportunistic rewrite: an unreadable/missing source is left alone rather + # than crashing before the real assembler invocation. + Assembler._retargetAssemblySource("gfx942", "/no/such/file.s") diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py new file mode 100644 index 000000000000..dbd9fd655c9b --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py @@ -0,0 +1,110 @@ +# Copyright Advanced Micro Devices, Inc., or its affiliates. +# SPDX-License-Identifier: MIT + +"""Direct-lane coverage for the custom-kernel branch of +``LibraryIO.parseLibraryLogicData``. + +The heavy parse path (live ``Solution`` construction) is driven against the +vendored production logic file used by the LibraryIO characterization suite, +with a real ``amdclang++`` assembler + per-ISA capability map. Unlike the +characterization copy, these live in a direct ``Tests/unit`` module so the +coverage lane credits the changed lines, and they exercise the *new* branches: +the ``CustomKernel`` mapping-name detection and the skip-on-missing-config path +(which returns ``None`` and drops the solution). +""" + +import copy +from pathlib import Path +from typing import List + +import pytest + +import Tensile.LibraryIO as L +from Tensile.Common.Architectures import SUPPORTED_ISA +from Tensile.Common.Capabilities import makeIsaInfoMap +from Tensile.Toolchain.Assembly import makeAssemblyToolchain +from Tensile.Toolchain.Validators import validateToolchain, ToolchainDefaults + + +_FIXTURE = (Path(__file__).parent / "characterization" / "LibraryIO" + / "data" / "logic_gfx942_HSS_BH.yaml") + + +@pytest.fixture(scope="module") +def cxx_compiler(): + return validateToolchain("amdclang++") + + +@pytest.fixture(scope="module") +def isa_info_map(cxx_compiler): + return makeIsaInfoMap(SUPPORTED_ISA, cxx_compiler) + + +@pytest.fixture(scope="module") +def assembler(cxx_compiler): + bundler = validateToolchain(ToolchainDefaults.OFFLOAD_BUNDLER) + return makeAssemblyToolchain(cxx_compiler, bundler, "default").assembler + + +def _raw_dict(): + data = L.read(str(_FIXTURE), True) + assert isinstance(data, List) + return L.parseLibraryLogicList(copy.deepcopy(data), str(_FIXTURE)) + + +def test_custom_kernel_legacy_name_is_resolved(assembler, isa_info_map, monkeypatch): + # Legacy flat CustomKernelName + an (empty) config -> the merge branch runs + # and the solution constructs normally (no handwritten-kernel path). + seen = [] + monkeypatch.setattr(L, "getCustomKernelConfig", lambda name, isp: seen.append(name) or {}) + data = _raw_dict() + data["Solutions"][0]["CustomKernelName"] = "synthetic_legacy_kernel" + # Present InternalSupportParams -> the isp-extraction branch also runs. + data["Solutions"][0]["InternalSupportParams"] = {"KernelLanguage": "Assembly"} + + logic = L.parseLibraryLogicData( + data, str(_FIXTURE), assembler, False, False, False, isa_info_map, False + ) + + assert "synthetic_legacy_kernel" in seen + assert len(logic.solutions) >= 1 + + +def test_custom_kernel_mapping_name_skipped_on_missing_config( + assembler, isa_info_map, monkeypatch, capsys): + # A solution using the new CustomKernel: { name: ... } mapping form whose + # config can't be read is dropped (returns None), emitting a per-kernel and + # an aggregate "Skipped N" warning. Appending (rather than replacing) keeps + # the vendored fixture's solution-index table intact so only the new, + # dropped kernel is exercised. + def _raise(name, isp): + raise RuntimeError("no custom.config") + + monkeypatch.setattr(L, "getCustomKernelConfig", _raise) + data = _raw_dict() + total = len(data["Solutions"]) + data["Solutions"].append( + {"KernelLanguage": "Assembly", "CustomKernel": {"name": "map_broken_kernel"}} + ) + + logic = L.parseLibraryLogicData( + data, str(_FIXTURE), assembler, False, False, False, isa_info_map, False + ) + + out = capsys.readouterr().out + assert "map_broken_kernel" in out # mapping-name resolved + assert "Skipped 1 solution(s)" in out # aggregate skip warning + assert len(logic.solutions) == total # only the appended kernel dropped + + +def test_custom_kernel_bad_matrix_instruction_raises(assembler, isa_info_map, monkeypatch): + monkeypatch.setattr( + L, "getCustomKernelConfig", lambda name, isp: {"MatrixInstruction": [1, 2, 3]} + ) + data = _raw_dict() + data["Solutions"][0]["CustomKernelName"] = "bad_mi_kernel" + + with pytest.raises(ValueError): + L.parseLibraryLogicData( + data, str(_FIXTURE), assembler, False, False, False, isa_info_map, False + ) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py new file mode 100644 index 000000000000..2686297ea354 --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py @@ -0,0 +1,264 @@ +# Copyright Advanced Micro Devices, Inc., or its affiliates. +# SPDX-License-Identifier: MIT + +"""Coverage for ``KernelWriter._registerKernelArgs`` — the pure argument-metadata +builder that produces the ``CustomKernel.args`` list for Tensile-generated +kernels (the kernarg-buffer layout the C++ runtime packs against). + +Scope / what this does and does NOT guarantee: + +* It drives the *real* method body over controlled ``self.states`` / ``kernel`` + inputs and pins the arg **ordering** and per-feature **inclusion** (Sparse -> + AddressMetadata, StreamK -> SK scalar args, MBSK -> trailing sync args, ...). + That layout is a real contract: the code must match ``Signature.py`` and the + assembly prologue, so a reordered/dropped arg is a genuine regression this + catches. +* It is a change-detector for that logic, **not** a cross-check against the live + ``Signature.py`` kernarg emission — feeding fabricated ``states`` cannot prove + the two stay consistent. That end-to-end consistency is exercised by the + ``Tests/custom/*.yaml`` kernels that build + dispatch on real hardware. + +``_registerKernelArgs`` reads only attributes/inputs (no rocisa/asm emission), so +it is called unbound with a stub ``self`` — no GPU, assembler, or kernel build. +""" + +from types import SimpleNamespace + +import pytest + +from Tensile.Activation import ActivationType +from Tensile.Common import DataDirection +from Tensile.KernelWriter import KernelWriter + + +def _writer(useBias=DataDirection.NONE, needBiasType=False, bpeCinternal=4, + numActivationArgSize=1, debugKernel=False, + numSgprSizesFree=2, numSgprSizesSum=1, strides=2): + ns = SimpleNamespace + states = ns( + numSgprSizesFree=numSgprSizesFree, numSgprSizesSum=numSgprSizesSum, + d=ns(numSgprStrides=strides), c=ns(numSgprStrides=strides), + a=ns(numSgprStrides=strides), b=ns(numSgprStrides=strides), + mxsa=ns(numSgprStrides=1), mxsb=ns(numSgprStrides=1), + m=ns(numSgprStrides=1), e=ns(numSgprStrides=strides), + bpeCinternal=bpeCinternal, useBias=useBias, needBiasType=needBiasType, + numActivationArgSize=numActivationArgSize, kernelName="tensile_kernel", + ) + return ns(states=states, debugConfig=ns(debugKernel=debugKernel), kernelArgDefs=[]) + + +def _kernel(**over): + problem_type = { + "MXBlockA": False, "MXBlockB": False, "Sparse": False, "UseBeta": True, + "UseScaleAB": False, "UseScaleCD": False, "UseScaleAlphaVec": 0, "UseE": False, + "ActivationType": ActivationType("none"), "OutputAmaxD": False, "UseBias": 0, + } + problem_type.update(over.pop("ProblemType", {})) + kernel = { + "InternalSupportParams": {"KernArgsVersion": 1}, + "ProblemType": problem_type, + "StreamK": 0, "StreamKAtomic": 0, + "PackedC0IdxChars": ["I"], "PackedC0IndicesX": [0], + "PackedC1IdxChars": ["J"], "PackedC1IndicesX": [1], + "GlobalSplitUAlgorithm": "SingleBuffer", "AdaptiveGemmGSUA": 0, + "ActivationFused": False, + } + kernel.update(over) + return kernel + + +def _register(writer, kernel): + KernelWriter._registerKernelArgs(writer, kernel) + return writer.kernelArgDefs + + +def _sems(writer, kernel): + return [a["semantic"] for a in _register(writer, kernel)] + + +# --------------------------------------------------------------------------- # +# Base layout + header +# --------------------------------------------------------------------------- # + + +def test_base_layout_exact_ordering(): + assert _sems(_writer(), _kernel()) == [ + "GemmInfo", "InternalArgs", "InternalArgs1", "NumWorkGroups", + "SizeFree0", "SizeFree1", "SizeSum", + "AddressD", "AddressC", "AddressA", "AddressB", + "StrideD0", "StrideD1", "StrideC0", "StrideC1", + "StrideA0", "StrideA1", "StrideB0", "StrideB1", + "Alpha", "Beta", + ] + + +def test_kernargs_version0_omits_v1_header(): + sems = _sems(_writer(), _kernel(InternalSupportParams={"KernArgsVersion": 0})) + assert sems[:2] == ["GemmInfo", "InternalArgs"] + assert "InternalArgs1" not in sems + assert "NumWorkGroups" not in sems + + +def test_debug_buffer_between_sizes_and_addresses(): + sems = _sems(_writer(debugKernel=True), _kernel()) + assert sems.index("SizeSum") < sems.index("DebugBuffer") < sems.index("AddressD") + + +# --------------------------------------------------------------------------- # +# Tensor-address / stride variants +# --------------------------------------------------------------------------- # + + +def test_mxblock_adds_scale_addresses_and_strides(): + sems = _sems(_writer(), _kernel(ProblemType={"MXBlockA": True, "MXBlockB": True})) + assert sems[sems.index("AddressA") + 1] == "AddressMXScaleA" + assert sems[sems.index("AddressB") + 1] == "AddressMXScaleB" + assert "StrideScaleA0" in sems and "StrideScaleB0" in sems + + +def test_sparse_adds_metadata_address_and_strides(): + sems = _sems(_writer(), _kernel(ProblemType={"Sparse": True})) + assert "AddressMetadata" in sems + assert "StrideMetadata0" in sems + + +def test_packed_magic_divisors_carry_index(): + kernel = _kernel(PackedC0IdxChars=["I", "J"], PackedC0IndicesX=[2, 3]) + defs = _register(_writer(), kernel) + magics = [a for a in defs if a["semantic"] in ("MagicNumberSize", "MagicShiftSize")] + # one (number, shift) pair for the (n-1) leading packed chars + assert [a["semantic"] for a in magics] == ["MagicNumberSize", "MagicShiftSize"] + assert all(a["index"] == 2 for a in magics) + + +def test_packed_c1_magic_divisors(): + # The PackedC1 loop is independent of PackedC0; exercise it directly. + kernel = _kernel(PackedC1IdxChars=["J", "K"], PackedC1IndicesX=[4, 5]) + defs = _register(_writer(), kernel) + magics = [a for a in defs if a["semantic"] in ("MagicNumberSize", "MagicShiftSize")] + assert [a["semantic"] for a in magics] == ["MagicNumberSize", "MagicShiftSize"] + assert all(a["index"] == 4 for a in magics) + + +# --------------------------------------------------------------------------- # +# Alpha / Beta +# --------------------------------------------------------------------------- # + + +def test_no_beta_when_use_beta_false(): + sems = _sems(_writer(), _kernel(ProblemType={"UseBeta": False})) + assert "Alpha" in sems and "Beta" not in sems + + +def test_alpha_beta_wide_compute_are_float64(): + defs = _register(_writer(bpeCinternal=8), _kernel()) + types = {a["semantic"]: a["type"] for a in defs} + assert types["Alpha"] == "float64" and types["Beta"] == "float64" + + +def test_alpha_narrow_compute_is_uint32(): + defs = _register(_writer(bpeCinternal=4), _kernel()) + types = {a["semantic"]: a["type"] for a in defs} + assert types["Alpha"] == "uint32" + + +# --------------------------------------------------------------------------- # +# StreamK scalar args +# --------------------------------------------------------------------------- # + + +def test_streamk_two_tile_adds_workspace_and_all_scalar_args(): + sems = _sems(_writer(), _kernel(StreamK=2, StreamKAtomic=0)) + for expected in ["AddressWorkspace", "AddressFlags", "ItersPerTile", + "MagicNumberItersPerTile", "MagicShiftItersPerTile", + "SKItersPerWG", "SKGrid", "SKTilesAndSplit"]: + assert expected in sems + + +def test_streamk_basic_omits_grid_and_split(): + sems = _sems(_writer(), _kernel(StreamK=1, StreamKAtomic=0)) + assert "SKItersPerWG" in sems + assert "SKGrid" not in sems and "SKTilesAndSplit" not in sems + + +def test_streamk_atomic_omits_workspace_addresses(): + sems = _sems(_writer(), _kernel(StreamK=2, StreamKAtomic=1)) + assert "AddressWorkspace" not in sems and "AddressFlags" not in sems + + +# --------------------------------------------------------------------------- # +# Scale / bias / factordim / E / activation / amax / MBSK +# --------------------------------------------------------------------------- # + + +def test_scale_addresses(): + sems = _sems(_writer(), _kernel( + ProblemType={"UseScaleAB": True, "UseScaleCD": True, "UseScaleAlphaVec": 1})) + for expected in ["AddressScaleA", "AddressScaleB", "AddressScaleC", + "AddressScaleD", "AddressScaleAlphaVec"]: + assert expected in sems + + +def test_bias_address_with_type(): + sems = _sems(_writer(useBias=DataDirection.READ, needBiasType=True), _kernel()) + assert "AddressBias" in sems and "BiasType" in sems and "StrideBias" in sems + + +def test_bias_address_without_type(): + sems = _sems(_writer(useBias=DataDirection.READ, needBiasType=False), _kernel()) + assert "AddressBias" in sems + assert "BiasType" not in sems and "StrideBias" not in sems + + +def test_factordim_from_scale_alpha_vec(): + assert "FactorDim" in _sems(_writer(), _kernel(ProblemType={"UseScaleAlphaVec": 3})) + + +def test_factordim_from_bias(): + sems = _sems(_writer(needBiasType=True), _kernel(ProblemType={"UseBias": 3})) + assert "FactorDim" in sems + + +def test_use_e_adds_address_and_strides(): + sems = _sems(_writer(), _kernel(ProblemType={"UseE": True})) + assert "AddressE" in sems and "StrideE0" in sems + + +def test_activation_args_and_type_arg(): + kernel = _kernel(ProblemType={"ActivationType": ActivationType("all")}, ActivationFused=True) + sems = _sems(_writer(), kernel) + assert sems.count("ActivationArg") == 2 # activationAlpha, activationBeta + assert "ActivationTypeArg" in sems # 'all' -> runtime type selector + + +def test_activation_skipped_when_not_fused(): + kernel = _kernel(ProblemType={"ActivationType": ActivationType("all")}, ActivationFused=False) + sems = _sems(_writer(), kernel) + assert "ActivationArg" not in sems + + +def test_activation_non_all_omits_type_arg(): + # A specific fused activation with its own arg(s) emits ActivationArg but no + # runtime ActivationTypeArg (that is only for the 'all'/'hipblaslt_all' enums). + kernel = _kernel(ProblemType={"ActivationType": ActivationType("leakyrelu")}, + ActivationFused=True) + sems = _sems(_writer(), kernel) + assert sems.count("ActivationArg") == 1 + assert "ActivationTypeArg" not in sems + + +def test_amax_output_addresses(): + sems = _sems(_writer(), _kernel(ProblemType={"OutputAmaxD": True})) + for expected in ["AddressAmaxOut", "AmaxWS", "AmaxSync"]: + assert expected in sems + + +def test_mbsk_trailing_args_from_algorithm(): + sems = _sems(_writer(), _kernel(GlobalSplitUAlgorithm="MultipleBufferSingleKernel")) + assert sems[-3:] == ["AddressTD", "Synchronizer", "GSUSync"] + + +def test_mbsk_trailing_args_from_adaptive_gsua(): + sems = _sems(_writer(), _kernel(AdaptiveGemmGSUA=1)) + for expected in ["AddressTD", "Synchronizer", "GSUSync"]: + assert expected in sems From f5d5d4f391c8ea35064d034b0eaf08fafdd0bd9d Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Thu, 16 Jul 2026 19:42:05 +0000 Subject: [PATCH 42/58] Revert removal of generateSingleCall --- .../include/Tensile/ContractionSolution.hpp | 12 ++ .../tensilelite/src/ContractionSolution.cpp | 167 +++++++++++++++++- 2 files changed, 175 insertions(+), 4 deletions(-) diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 6fadf1639e12..aaa282c80697 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -688,6 +688,18 @@ namespace TensileLite Hardware const& hardware, StreamKSettings const& sk) const; + // Temporary: the proven per-feature argument-packing path, restored from + // develop and used for all Tensile-generated kernels while the generic + // generateCustomCall path is validated for newer features (subtile, + // gfx950, StreamK work-stealing). Handwritten/external custom kernels + // still go through generateCustomCall. See gating in solve(). + template + KernelInvocation generateSingleCall(Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk, + GSUSettings const& gsuSettings) const; + template KernelInvocation generateSingleCallGroupedGemm(std::vector const& problems, GroupedInputs const& inputs, diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 2e41a3cd0cff..253b8060766a 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -1945,6 +1945,142 @@ namespace TensileLite numWorkGroups.y = CeilDivide(numWorkGroups.y, sizeMapping.macroTile.y); } + // Temporary: restored from develop. Builds the kernarg buffer via the + // hand-written per-feature path (singleCallArgs) rather than the generic + // CustomKernel.args iteration in generateCustomCall. Used for all + // Tensile-generated kernels (see gating in solve()) so their launch + // arguments are byte-identical to develop while generateCustomCall is + // validated for newer features. + template + KernelInvocation + ContractionSolution::generateSingleCall(ContractionSolution::Problem const& problem, + ContractionInputs const& inputs, + Hardware const& hardware, + StreamKSettings const& sk, + GSUSettings const& gsuSettings) const + { + KernelInvocation rv; + + rv.isSingleCall = true; + + rv.args = KernelArguments(T_Debug); + + rv.args.reserve(1024, 128); + + rv.kernelName = kernelName; + + calculateGrid(rv.workGroupSize, rv.numWorkGroups, problem); + + dim3 problemNumGroupTiles = rv.numWorkGroups; + + uint32_t autoGsuVal = calculateAutoGSU(problem, &hardware); + uint32_t gsu = problem.getParams().gsu() > 0 ? problem.getParams().gsu() : autoGsuVal; + if(gsu > 0) + rv.numWorkGroups.y *= gsu; + + if(sizeMapping.streamK != 0) + { + rv.numWorkGroups.x = sk.grid; + rv.numWorkGroups.y = 1; + rv.numWorkGroups.z = 1; + } + + bool enableCluster = (sizeMapping.clusterDim.x > 1 || sizeMapping.clusterDim.y > 1); + if(!enableCluster) + { + if(internalArgsSupport.version >= 1) + { + rv.numWorkGroups.x *= (rv.numWorkGroups.y * rv.numWorkGroups.z); + rv.numWorkGroups.y = 1; + rv.numWorkGroups.z = 1; + } + } + + rv.clusterDim = sizeMapping.clusterDim; + + rv.numWorkItems.x = rv.workGroupSize.x * rv.numWorkGroups.x; + rv.numWorkItems.y = rv.workGroupSize.y * rv.numWorkGroups.y; + rv.numWorkItems.z = rv.workGroupSize.z * rv.numWorkGroups.z; + + rv.sharedMemBytes = 0; + + if(internalArgsSupport.useUniversalArgs) + { + auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] + = calculateAutoWGM(problem, &hardware, sk.grid); + auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] + = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); + if(T_Debug) + { + std::cout << "WGM: " << autoWGM << ", WGMXCC: " << autoWGMXCC + << ", WGMXCCCHUNK: " << autoWGMXCCCHUNK << std::endl; + std::cout << "StaggerUMapping: " << autoStaggerUMapping + << ", StaggerU: " << autoStaggerU + << ", StaggerUStrideShift: " << autoStaggerUStrideShift << std::endl; + } + AdaptiveGemmNTAB ntab = calculateAdaptiveGemmNTAB(problem, &hardware); + if(problem.batchMode() == ContractionProblemGemm::BATCHMODE::POINTER_ARRAY) + { + kernelArgs( 1, + 3, + rv.args, + getNumWorkGroups(rv), + &hardware, + problem.getParams(), + autoWGM, + autoWGMXCC, + autoWGMXCCCHUNK, + autoStaggerUMapping, + autoStaggerU, + autoStaggerUStrideShift, + autoGsuVal, + ntab); + } + else + { + kernelArgs( 1, + 0, + rv.args, + getNumWorkGroups(rv), + &hardware, + problem.getParams(), + autoWGM, + autoWGMXCC, + autoWGMXCCCHUNK, + autoStaggerUMapping, + autoStaggerU, + autoStaggerUStrideShift, + autoGsuVal, + ntab); + } + } + singleCallArgs( + problem, inputs, 0, &hardware, problemNumGroupTiles, rv.numWorkGroups, rv.args, sk); + + if(gsuSettings.globalAccumulation == 3 || sizeMapping.adaptiveGemmGSUA == 1) // MBSK or MB with AdaptiveGemmGSUA + { + rv.args.append("dstD", inputs.d); + // MBSK: synchronizer address, MB: null address + rv.args.append("Synchronizer", + gsuSettings.globalAccumulation == 3 + ? inputs.Synchronizer + : NULL); + rv.args.append("GSUSync", 0); + } + + if(problemType.stochasticRounding) + { + // generate seed from random generator + std::random_device rd; + std::mt19937 gen(rd()); + std::uniform_int_distribution distribution(0, 0xFFFFFFFF); + uint32_t seed = distribution(gen); + rv.args.append("RNDSeed", seed); + } + rv.codeObjectFile = codeObjectFilename.load(); + return rv; + } + template KernelInvocation ContractionSolution::generateCustomCall(ContractionSolution::Problem const& problem, ContractionInputs const& inputs, @@ -2066,7 +2202,12 @@ namespace TensileLite dim = tiles.x * tiles.y * tiles.z * (gsu > 0 ? gsu : 1); break; case CustomGridSize::StreamKWithBatch: - dim = customKernel.generated ? sk.grid : sk.grid * tiles.z; + // generateCustomCall is only used for handwritten/external + // custom kernels; Tensile-generated kernels are routed to + // generateSingleCall in solve(). For a batched handwritten + // Stream-K custom kernel, sk.grid is per-batch and must be + // expanded by the batch tile count. + dim = sk.grid * tiles.z; break; case CustomGridSize::StreamKNoBatch: dim = sk.grid; @@ -3929,10 +4070,28 @@ namespace TensileLite GSUSettings gsuSettings; gsuSettings.globalAccumulation = problem.getAccumulation(hardware, sizeMapping, gsu); - if(debug) - rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + // Temporary gating: only genuine handwritten/external custom kernels use + // the generic generateCustomCall path (they have no other path). All + // Tensile-generated kernels — including newer features like subtile, + // gfx950, and StreamK work-stealing whose argument shapes have not been + // fully validated through generateCustomCall — go through the proven + // generateSingleCall path restored from develop, so their launch + // arguments stay byte-identical to develop. + bool useCustomCall = !customKernel.name.empty() && !customKernel.generated; + if(useCustomCall) + { + if(debug) + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + else + rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + } else - rv.push_back(generateCustomCall(problem, inputs, hardware, sk)); + { + if(debug) + rv.push_back(generateSingleCall(problem, inputs, hardware, sk, gsuSettings)); + else + rv.push_back(generateSingleCall(problem, inputs, hardware, sk, gsuSettings)); + } if((gsu > 1 && gsuSettings.globalAccumulation && gsuSettings.globalAccumulation != 3) || sk.reduction == origami::reduction_t::parallel) From aba9851233aac09a038d62ce7d99fdbba20f366e Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Mon, 20 Jul 2026 18:08:45 +0000 Subject: [PATCH 43/58] Add more unit tests --- .../Tests/unit/test_CustomKernelMetadata.py | 168 ++++++++++++++++++ .../Tests/unit/test_custom_kernel_cli.py | 84 +++++++++ .../Tests/unit/test_custom_kernel_host.py | 20 +++ 3 files changed, 272 insertions(+) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py index 00c33ea7c64a..500011f231ee 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -44,7 +44,10 @@ _buildCustomKernelFromMetadata, _metadataArgToCustomArg, getCustomKernelConfig, + getCustomKernelFilepath, + isCustomKernelConfig, iterCustomKernelFiles, + readCustomKernelConfig, validateCustomKernelMetadata, ) from Tensile.Toolchain.Assembly import validateCustomKernelMetadataAtBuild @@ -793,3 +796,168 @@ def test_validate_metadata_custom_kernel_not_mapping(tmp_path): assert not valid assert "CustomKernel (mapping)" in msg + + +# --------------------------------------------------------------------------- # +# Remaining CustomKernels branch coverage +# --------------------------------------------------------------------------- # + + +def test_is_custom_kernel_config_generated_is_false(): + # A generated (Tensile-emitted) CustomKernel mapping is NOT treated as a + # handwritten custom kernel. + assert isCustomKernelConfig({"CustomKernel": {"name": "k", "generated": True}}) is False + assert isCustomKernelConfig({"CustomKernel": {"name": "k"}}) is True + + +def test_get_custom_kernel_filepath_recursive_fallback(tmp_path): + # When no flat /.s exists, the loader searches subdirectories. + nested = tmp_path / "aiter" + nested.mkdir() + write_kernel(nested / "k.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + """) + assert getCustomKernelFilepath("k", str(tmp_path)) == str(nested / "k.s") + + +def test_read_custom_kernel_config_non_mapping_raises(tmp_path): + p = tmp_path / "k.s" + p.write_text(".amdgpu_metadata\n---\ncustom.config:\n - 1\n - 2\n...\ns_nop 0\n") + with pytest.raises(RuntimeError, match="must be a YAML mapping"): + readCustomKernelConfig("k", str(tmp_path)) + + +def test_build_from_metadata_non_dict_yaml_raises(): + with pytest.raises(RuntimeError, match="no parseable .amdgpu_metadata"): + _buildCustomKernelFromMetadata("k", None, {"MatrixInstruction": [16, 16, 16, 1]}) + + +def test_build_from_metadata_mi_length9_derives_wave_from_mi(): + # MI of length >= 9 carries MIWaveTile (mi[5:7]) / MIWaveGroup (mi[7:9]) + # inline, so macrotile is computed from them. + full = {"amdhsa.kernels": [{".name": "k", ".max_flat_workgroup_size": 256, + ".args": [{".name": "D", ".size": 8, ".value_kind": "global_buffer"}]}]} + ck = _buildCustomKernelFromMetadata("k", full, {"MatrixInstruction": [16, 16, 16, 1, 1, 4, 4, 2, 2]}) + # macrotile0 = mi0 * wt0 * wg0 = 16 * 4 * 2 = 128 + assert ck["macrotile"][0] == 16 * 4 * 2 + assert ck["macrotile"][1] == 16 * 4 * 2 + + +def test_get_custom_kernel_config_strips_unknown_metadata_key(tmp_path): + # A non-tunable, non-passthrough key (e.g. provenance) is dropped from the + # solution dict rather than fed to the solution. + write_kernel(tmp_path / "k.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + Version: 9.9.9 + """) + config = getCustomKernelConfig("k", {}, str(tmp_path)) + assert "Version" not in config + + +def test_get_custom_kernel_config_respects_explicit_custom_kernel(tmp_path): + # An explicit CustomKernel block is used verbatim (no auto-inference). + write_kernel(tmp_path / "k.s", """\ + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + CustomKernel: + args: [] + macrotile: [128, 128, 64] + threads: [256, 1, 1] + grid: [TilesX, TilesY, One] + """) + config = getCustomKernelConfig("k", {}, str(tmp_path)) + assert config["CustomKernel"]["macrotile"] == [128, 128, 64] + assert config["CustomKernel"]["grid"] == ["TilesX", "TilesY", "One"] + + +def test_validate_metadata_tensile_missing_internal_support_params(tmp_path): + write_kernel(tmp_path / "k.s", """\ + ProblemType: {} + """) + valid, msg = validateCustomKernelMetadata("k", str(tmp_path)) + assert not valid + assert "InternalSupportParams" in msg + + +def test_validate_metadata_external_source_missing_origin(tmp_path): + write_kernel(tmp_path / "k.s", """\ + Source: + Repository: http://x + Features: {} + Version: 1.0.0 + InternalSupportParams: + KernArgsVersion: 0 + ProblemType: {} + MatrixInstruction: [16, 16, 16, 1] + CustomKernel: + args: [] + macrotile: [16, 16, 16] + threads: [64, 1, 1] + grid: [TilesX, TilesY, Batch] + """) + valid, msg = validateCustomKernelMetadata("k", str(tmp_path)) + assert not valid + assert "Source.Origin" in msg + + +# --------------------------------------------------------------------------- # +# _parse_tensile_yaml: skip malformed ForkParameter entries +# --------------------------------------------------------------------------- # + + +def test_build_from_metadata_no_universal_args_skips_header_reorder(): + full = {"amdhsa.kernels": [{".name": "k", ".max_flat_workgroup_size": 256, + ".args": [{".name": "D", ".size": 8, ".value_kind": "global_buffer"}]}]} + ck = _buildCustomKernelFromMetadata("k", full, { + "MatrixInstruction": [16, 16, 16, 1], + "InternalSupportParams": {"UseUniversalArgs": False}, + }) + assert ck["args"][0]["semantic"] == "AddressD" + + +def test_get_custom_kernel_filepath_iterates_past_nonmatching(tmp_path): + nested = tmp_path / "aiter" + nested.mkdir() + # 'aaa.s' sorts before 'k.s' and does not match, so the search loop must + # skip it before matching 'k.s'. + write_kernel(nested / "aaa.s", "InternalSupportParams:\n KernArgsVersion: 0") + write_kernel(nested / "k.s", "InternalSupportParams:\n KernArgsVersion: 0") + assert getCustomKernelFilepath("k", str(tmp_path)).endswith("/k.s") + + +def test_read_asm_file_comment_only_metadata_returns_no_detection(tmp_path): + # yaml_lines non-empty but parses to None (comment only) -> the "no metadata" + # early return. + p = tmp_path / "k.s" + p.write_text(".amdgpu_metadata\n---\n# only a comment\n...\ns_nop 0\n") + info = _read_asm_file(str(p)) + assert info["detected"] == {} + assert info["insert_idx"] is not None + + +def test_parse_tensile_yaml_skips_non_dict_and_nameless_entries(tmp_path): + # A non-dict fork entry and a CustomKernel entry without a name are skipped; + # the first named kernel still resolves. + p = tmp_path / "t.yaml" + p.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - "a bare string entry" + - CustomKernel: + - args: [] + - name: real_kernel + args: [] + macrotile: [16, 16, 16] + threads: [64, 1, 1] + grid: [TilesX, TilesY, Batch] + """)) + config = _parse_tensile_yaml(str(p), "real_kernel") + assert "CustomKernel" in config diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py index 9143ea807d4b..812456cb3b8f 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py @@ -160,6 +160,78 @@ def test_addcustomconfig_main_with_yaml_injects_interface(tmp_path, monkeypatch) assert "CustomKernel:" in text +_META_WITH_DETECTED = dedent("""\ + .amdgpu_metadata + --- + amdhsa.kernels: + - .name: mykernel + .reqd_workgroup_size: [128, 1, 1] + .wavefront_size: 64 + .args: + - .name: D + .size: 8 + .offset: 0 + .value_kind: global_buffer + ... + """) + + +def test_addcustomconfig_main_autodetects_threads_and_wavefront(tmp_path, monkeypatch, capsys): + p = tmp_path / "k.s" + p.write_text(_META_WITH_DETECTED) + monkeypatch.setattr(sys, "argv", ["prog", str(p)]) + + acc.main() + + out = capsys.readouterr().out + assert "Auto-detected" in out + assert "wavefront_size=64" in out + assert "threads=[128, 1, 1]" in out + assert "custom.config:" in p.read_text() + + +def test_addcustomconfig_main_merges_detected_into_yaml_config(tmp_path, monkeypatch): + # The YAML CustomKernel omits threads/WavefrontSize; main() fills them from + # the .s .reqd_workgroup_size / .wavefront_size auto-detection. + p = tmp_path / "mykernel.s" + p.write_text(_META_WITH_DETECTED) + y = tmp_path / "t.yaml" + y.write_text(dedent("""\ + BenchmarkProblems: + - + - OperationType: GEMM + - ForkParameters: + - CustomKernel: + - name: mykernel + args: [] + macrotile: [256, 256, 64] + grid: [TilesX, TilesY, One] + - MatrixInstruction: + - [16, 16, 16, 1] + """)) + monkeypatch.setattr(sys, "argv", ["prog", str(p), "--yaml", str(y)]) + + acc.main() + + text = p.read_text() + assert "threads: [128, 1, 1]" in text + assert "WavefrontSize: 64" in text + + +def test_addcustomconfig_main_inject_failure_exits(tmp_path, monkeypatch, capsys): + # A .s with no .amdgpu_metadata section has no insert point, so injection + # fails and main() exits non-zero. + p = tmp_path / "k.s" + p.write_text("s_nop 0\ns_endpgm\n") + monkeypatch.setattr(sys, "argv", ["prog", str(p)]) + + with pytest.raises(SystemExit) as e: + acc.main() + + assert e.value.code == 1 + assert "No .amdgpu_metadata" in capsys.readouterr().err + + # --------------------------------------------------------------------------- # # ValidateMetadata.main() # --------------------------------------------------------------------------- # @@ -214,3 +286,15 @@ def test_validatemetadata_main_non_strict_bad_exits_zero(tmp_path, monkeypatch, assert e.value.code == 0 assert "1 warning(s)" in capsys.readouterr().out + + +def test_validatemetadata_main_default_root_uses_shipped_kernels(monkeypatch, capsys): + # With no --custom-kernels-root, main() auto-detects the shipped + # Tensile/CustomKernels directory and validates the real kernels. + monkeypatch.setattr(sys, "argv", ["prog"]) + + with pytest.raises(SystemExit) as e: + vm.main() + + assert e.value.code == 0 + assert "Summary:" in capsys.readouterr().out diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py index 7c12b00e24af..e5a9ebc793e9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py @@ -13,6 +13,7 @@ from Tensile.BenchmarkProblems import _hashableProblemTypeKV from Tensile.Common.DataType import DataType +from Tensile.Common.Utilities import deriveWaveParams from Tensile.SolutionStructs.Naming import _getName, getKernelFileBase from Tensile.SolutionStructs.Solution import Solution from Tensile.Toolchain.Component import Assembler @@ -215,3 +216,22 @@ def test_retarget_missing_source_does_not_raise(): # Opportunistic rewrite: an unreadable/missing source is left alone rather # than crashing before the real assembler invocation. Assembler._retargetAssemblySource("gfx942", "/no/such/file.s") + + +# --------------------------------------------------------------------------- # +# deriveWaveParams: non-perfect-square wave count exercises the wgM search loop +# --------------------------------------------------------------------------- # + + +def test_derive_wave_params_non_square_wave_count(): + # num_threads=320, wavefront=64 -> num_waves=5 (not a perfect square), so + # the wgM-decrement loop runs until wgM divides num_waves (2 -> 1). + wave_group, wave_tile = deriveWaveParams([16, 16, 16, 1], 320, [256, 256], 64) + assert wave_group == [1, 5] + assert wave_tile == [max(1, 256 // (16 * 1)), max(1, 256 // (16 * 5))] + + +def test_derive_wave_params_square_wave_count(): + # num_threads=256, wavefront=64 -> num_waves=4 (perfect square) -> wgM=2. + wave_group, _ = deriveWaveParams([16, 16, 16, 1], 256, [256, 256], 64) + assert wave_group == [2, 2] From 51acde5335037bdba0a708f0871d6cd79c291dc5 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Mon, 20 Jul 2026 20:51:27 +0000 Subject: [PATCH 44/58] add pytestmark to the unit tests --- .../tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py | 2 ++ .../tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py | 2 ++ .../tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py | 2 ++ .../Tensile/Tests/unit/test_library_io_custom_kernel.py | 2 ++ .../tensilelite/Tensile/Tests/unit/test_register_kernel_args.py | 2 ++ 5 files changed, 10 insertions(+) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py index 500011f231ee..2ed065fb399f 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -53,6 +53,8 @@ from Tensile.Toolchain.Assembly import validateCustomKernelMetadataAtBuild from Tensile.ValidateMetadata import validate_all +pytestmark = pytest.mark.unit + def write_kernel(path, config): path.parent.mkdir(parents=True, exist_ok=True) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py index 812456cb3b8f..1ed786cb67e9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_cli.py @@ -17,6 +17,8 @@ import Tensile.AddCustomConfig as acc import Tensile.ValidateMetadata as vm +pytestmark = pytest.mark.unit + META_EMPTY = dedent("""\ .amdgpu_metadata diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py index e5a9ebc793e9..0c8c29385ddc 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py @@ -18,6 +18,8 @@ from Tensile.SolutionStructs.Solution import Solution from Tensile.Toolchain.Component import Assembler +pytestmark = pytest.mark.unit + # --------------------------------------------------------------------------- # # Solution._assignCustomKernelParameters diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py index dbd9fd655c9b..8130ec4f0727 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_library_io_custom_kernel.py @@ -25,6 +25,8 @@ from Tensile.Toolchain.Assembly import makeAssemblyToolchain from Tensile.Toolchain.Validators import validateToolchain, ToolchainDefaults +pytestmark = pytest.mark.unit + _FIXTURE = (Path(__file__).parent / "characterization" / "LibraryIO" / "data" / "logic_gfx942_HSS_BH.yaml") diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py index 2686297ea354..ac66e787b01e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_register_kernel_args.py @@ -30,6 +30,8 @@ from Tensile.Common import DataDirection from Tensile.KernelWriter import KernelWriter +pytestmark = pytest.mark.unit + def _writer(useBias=DataDirection.NONE, needBiasType=False, bpeCinternal=4, numActivationArgSize=1, debugKernel=False, From 531175e70161cc055629b5677bfd54b2741e0a2a Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Tue, 4 Aug 2026 20:44:18 +0000 Subject: [PATCH 45/58] fix regressions --- .../src/amd_detail/rocblaslt/src/tensile_host.cpp | 4 ++-- projects/hipblaslt/tensilelite/Tensile/LibraryIO.py | 2 +- .../__snapshots__/test_logiccontract_char.ambr | 12 ------------ .../tensilelite/src/ContractionSolution.cpp | 5 +++-- 4 files changed, 6 insertions(+), 17 deletions(-) diff --git a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/tensile_host.cpp b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/tensile_host.cpp index b9a458bc5dfc..926bf01e2473 100644 --- a/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/tensile_host.cpp +++ b/projects/hipblaslt/library/src/amd_detail/rocblaslt/src/tensile_host.cpp @@ -4509,12 +4509,12 @@ rocblaslt_status getAllSolutions(MyProblem& if constexpr(std::is_same::value) { if(prob.batchMode() == TensileLite::ContractionProblemGemm::BATCHMODE::POINTER_ARRAY - && !solution->sizeMapping.customKernelName.empty()) + && !solution->customKernel.name.empty() && !solution->customKernel.generated) { if(get_logger_layer_mode() & rocblaslt_layer_mode_log_info) { std::ostringstream msg; - msg << "Skipping custom kernel " << solution->sizeMapping.customKernelName + msg << "Skipping custom kernel " << solution->customKernel.name << " - does not support batch_mode=POINTER_ARRAY" << std::endl; log_info(__func__, msg.str()); } diff --git a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py index e15235147d01..665ff9190a35 100644 --- a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py +++ b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py @@ -665,7 +665,7 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Optional[So if "KernelLanguage" not in solutionState.keys(): solutionState["KernelLanguage"] = defaultSolution["KernelLanguage"] if "CustomKernelName" not in solutionState.keys(): - solutionState["CustomKernelName"] = defaultSolution["CustomKernelName"] + solutionState["CustomKernelName"] = defaultSolution.get("CustomKernelName", "") if solutionState["KernelLanguage"] == "Assembly": solutionState["ISA"] = gfxToIsa(data["ArchitectureName"]) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/LibraryIO/__snapshots__/test_logiccontract_char.ambr b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/LibraryIO/__snapshots__/test_logiccontract_char.ambr index ba2399238213..9452bd779a5e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/LibraryIO/__snapshots__/test_logiccontract_char.ambr +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/LibraryIO/__snapshots__/test_logiccontract_char.ambr @@ -25,7 +25,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -273,7 +272,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -509,7 +507,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -760,7 +757,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -1028,7 +1024,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -1276,7 +1271,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -1538,7 +1532,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -1789,7 +1782,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -2040,7 +2032,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -2279,7 +2270,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -2530,7 +2520,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, @@ -2780,7 +2769,6 @@ 'ClusterLocalRead': 1, 'CompactLoopStore': False, 'ConvertAfterDS': False, - 'CustomKernelName': '', 'DebugPersistentKernelLoopForever': False, 'DebugStreamK': 0, 'DepthU': -1, diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index f8766db84615..76f6edf8c332 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -2211,7 +2211,7 @@ namespace TensileLite // Batch offset support for General Batched GEMM (SupportUserArgs kernels). // Appended at the tail, after the dstD/Synchronizer block, to match the // kernel signature order (see Signature.py). - if(!problemType.groupedGemm && sizeMapping.customKernelName.empty()) + if(!problemType.groupedGemm && (customKernel.name.empty() || customKernel.generated)) { rv.args.append("batchOffsetD", inputs.batchOffsetD); rv.args.append("batchOffsetC", inputs.batchOffsetC); @@ -3499,7 +3499,8 @@ namespace TensileLite } // Adding the batchmode kernel argument for post GSU kernel to determine // how to index the batch dimension in Strided Batch versus General Batched. - if(problemType.groupedGemm == false && sizeMapping.customKernelName.empty()) + if(problemType.groupedGemm == false + && (customKernel.name.empty() || customKernel.generated)) { ContractionProblemGemm::BATCHMODE batchMode = problem.batchMode(); args.template append("batchMode", static_cast(batchMode)); From 1a9fa5b3ae857941a7f942383dc1fd96e52ef8a6 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 5 Aug 2026 17:30:09 +0000 Subject: [PATCH 46/58] add custom yaml skip archs --- .../tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml | 2 +- .../tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml | 2 +- .../hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml | 2 +- .../hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml | 2 +- .../tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml | 3 +-- .../tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml | 2 +- .../tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml | 2 +- 7 files changed, 7 insertions(+), 8 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml index aa94d6d81937..a1b109e39bdc 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_bf16.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx942, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml index 7bc7aaa6e35b..9b8f12261fe0 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_aiter_f4.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx942, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml index 7a7f96225b20..a52ecc1065ff 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_ck.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx950, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml index 9caaaeea8a81..e2a5e1fd5824 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_rr.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx950, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml index 5aa6a512df64..22d17513dfd9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported yet + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx950, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 @@ -28,7 +28,6 @@ BenchmarkProblems: UseBeta: True Batched: True UseBias: 0 - Batched: True Activation: False UseScaleAlphaVec: 0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml index 1cb179e7bb86..316b2a399cde 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_triton_f4.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx942, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml index 4a1725e3824d..37b71d6ea722 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_wave_bf16.yaml @@ -1,5 +1,5 @@ TestParameters: - marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201] # not supported by arch + marks: [skip-gfx900, skip-gfx906, skip-gfx908, skip-gfx90a, skip-gfx940, skip-gfx941, skip-gfx942, skip-gfx1010, skip-gfx1011, skip-gfx1012, skip-gfx1030, skip-gfx1100, skip-gfx1101, skip-gfx1102, skip-gfx1200, skip-gfx1201, skip-gfx1250] # not supported by arch GlobalParameters: MinimumRequiredVersion: 5.0.0 From 9cd280674e76a4dcd2e7adb2bd14d1e5ae85805b Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 5 Aug 2026 19:48:27 +0000 Subject: [PATCH 47/58] fix CI --- projects/hipblaslt/tensilelite/CMakeLists.txt | 29 +++++++++++++++---- .../ToolchainAssembly/test_assembly_char.py | 24 +++++++++++++++ .../tensilelite/src/ContractionSolution.cpp | 27 ++++++++++++++--- 3 files changed, 71 insertions(+), 9 deletions(-) diff --git a/projects/hipblaslt/tensilelite/CMakeLists.txt b/projects/hipblaslt/tensilelite/CMakeLists.txt index 2508d5fb585b..21c3862dc80a 100644 --- a/projects/hipblaslt/tensilelite/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/CMakeLists.txt @@ -88,14 +88,29 @@ if(TENSILELITE_ENABLE_HOST) $ ) - if(NOT TARGET roc::mxDataGenerator) + # mxDataGenerator supplies the gfx950 pre-swizzled MX scale padding helper behind + # the StrideScaleA1/StrideScaleB1 custom-kernel semantics. Treat it as optional: + # HIPBLASLT_ENABLE_MXDATAGENERATOR is OFF on Windows, and shared/mxdatagenerator + # is absent from checkouts that vendor only projects/hipblaslt (hipSPARSELt CI), + # so probe for it instead of hard-requiring it. + set(TENSILELITE_HOST_MXDATAGENERATOR ${HIPBLASLT_ENABLE_MXDATAGENERATOR}) + if(TENSILELITE_HOST_MXDATAGENERATOR AND NOT TARGET roc::mxDataGenerator) + set(_mxdatagen_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../shared/mxdatagenerator") if(HIPBLASLT_ENABLE_THEROCK) - find_package(mxDataGenerator REQUIRED) + find_package(mxDataGenerator QUIET) + if(NOT mxDataGenerator_FOUND) + set(TENSILELITE_HOST_MXDATAGENERATOR OFF) + endif() + elseif(EXISTS "${_mxdatagen_src}/CMakeLists.txt") + add_subdirectory("${_mxdatagen_src}" "${CMAKE_CURRENT_BINARY_DIR}/mxdatagenerator") else() - add_subdirectory("${CMAKE_CURRENT_SOURCE_DIR}/../../../shared/mxdatagenerator" - "${CMAKE_CURRENT_BINARY_DIR}/mxdatagenerator") + set(TENSILELITE_HOST_MXDATAGENERATOR OFF) endif() endif() + if(NOT TENSILELITE_HOST_MXDATAGENERATOR) + message(STATUS "tensilelite-host: mxDataGenerator not available; " + "pre-swizzled MX scale strides (StrideScaleA1/B1) are disabled") + endif() target_link_libraries(tensilelite-host PUBLIC @@ -104,10 +119,14 @@ if(TENSILELITE_ENABLE_HOST) $ PRIVATE hip::device - roc::mxDataGenerator ZLIB::ZLIB ) + if(TENSILELITE_HOST_MXDATAGENERATOR) + target_link_libraries(tensilelite-host PRIVATE roc::mxDataGenerator) + target_compile_definitions(tensilelite-host PRIVATE HIPBLASLT_ENABLE_MXDATAGENERATOR) + endif() + include(CheckCXXSourceCompiles) set(CMAKE_REQUIRED_INCLUDES ${HIP_INCLUDE_DIRS}) set(CMAKE_REQUIRED_LIBRARIES hip::device) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainAssembly/test_assembly_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainAssembly/test_assembly_char.py index 0925a891df63..6d3cb61b863b 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainAssembly/test_assembly_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/ToolchainAssembly/test_assembly_char.py @@ -11,6 +11,7 @@ import pytest +import Tensile.Toolchain.Assembly as A from Tensile.Toolchain.Assembly import buildAssemblyCodeObjectFiles pytestmark = pytest.mark.unit @@ -73,3 +74,26 @@ def test_build_empty_kernels(tmp_path, snapshot): asmDir.mkdir(); destDir.mkdir() out = buildAssemblyCodeObjectFiles(_StubLinker(), _StubBundler(), [], destDir, asmDir) assert out == snapshot + + +@pytest.mark.parametrize("validate", [False, True]) +def test_build_honors_validate_metadata(tmp_path, monkeypatch, validate): + """The ValidateMetadata global gates the build-time metadata check. + + Guards the wiring only: validateCustomKernelMetadataAtBuild is stubbed so this + stays a pure unit test (no CustomKernels/ directory reads), and the assertion is + that the gate is honored in both directions and does not disturb the returned + code-object list. + """ + asmDir, destDir = tmp_path / "asm", tmp_path / "dest" + asmDir.mkdir(); destDir.mkdir() + + seen = [] + monkeypatch.setattr(A, "validateCustomKernelMetadataAtBuild", lambda kernels: seen.append(len(kernels))) + monkeypatch.setitem(A.globalParameters, "ValidateMetadata", validate) + + kernels = [_kernel("k0")] + out = buildAssemblyCodeObjectFiles(_StubLinker(), _StubBundler(), kernels, destDir, asmDir) + + assert seen == ([1] if validate else []) + assert sorted(p.name for p in out) == ["TensileLibrary_gfx942.co"] diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 76f6edf8c332..1f47fc89dfb4 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -37,7 +37,9 @@ #include #include +#if HIPBLASLT_ENABLE_MXDATAGENERATOR #include +#endif #include #include @@ -59,6 +61,25 @@ namespace TensileLite { + namespace + { + // Batch stride for pre-swizzled gfx950 MX scales. The padding rule lives in + // mxDataGenerator, which is an optional dependency (see tensilelite/CMakeLists.txt), + // so fail loudly rather than silently substituting an unpadded stride that would + // make the kernel read the wrong scale block. + size_t preSwizzledScaleBatchStride([[maybe_unused]] TensorDescriptor const& t, + [[maybe_unused]] char const* semantic) + { +#if HIPBLASLT_ENABLE_MXDATAGENERATOR + return DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); +#else + throw std::runtime_error(concatenate( + semantic, + " requires mxDataGenerator; rebuild with HIPBLASLT_ENABLE_MXDATAGENERATOR=ON")); +#endif + } + } + std::string toString(CustomArgSemantic arg) { static const std::array(CustomArgSemantic::COUNT)> CustomArgSemanticStrings = { @@ -2525,9 +2546,8 @@ namespace TensileLite } case CustomArgSemantic::StrideScaleA1: { - auto const& t = problem.mxsa(); size_t batchStride - = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + = preSwizzledScaleBatchStride(problem.mxsa(), "StrideScaleA1"); rv.args.appendCustomType("StrideScaleA1", batchStride, arg.type); break; } @@ -2539,9 +2559,8 @@ namespace TensileLite } case CustomArgSemantic::StrideScaleB1: { - auto const& t = problem.mxsb(); size_t batchStride - = DGen::preSwizzleScalesGFX950PaddedSize(t.sizes()[1], t.sizes()[0]); + = preSwizzledScaleBatchStride(problem.mxsb(), "StrideScaleB1"); rv.args.appendCustomType("StrideScaleB1", batchStride, arg.type); break; } From 091b94bfd68dd2fc1986e1b8cd4666aaf310d245 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Thu, 6 Aug 2026 01:48:34 +0000 Subject: [PATCH 48/58] fix ci and add tests --- .../tensilelite/Tensile/KernelWriter.py | 12 --- .../Tensile/KernelWriterAssembly.py | 6 ++ .../unit/test_define_multi_sgpr_index.py | 74 +++++++++++++++++++ 3 files changed, 80 insertions(+), 12 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_define_multi_sgpr_index.py diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py index 1dd3056eeec7..fb2cf18a0ae7 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriter.py @@ -10163,18 +10163,6 @@ def _mxsTileSpanActive(tc): self.states.numStoreSgprNameSizes.append(1) storeSgprLoad += self.states.numActivationTypeArgSize + self.states.numactivationArgTotalSize - if self.states.useGateResidual: - self.states.numSgprAddressGate = self.states.rpga # 64-bit - self.states.numStoreSgprNames.append("AddressGate") - self.states.numStoreSgprNameSizes.append(self.states.numSgprAddressGate) - self.states.GateType = 1 - self.states.GateStride = self.states.gate.numSgprStrides - self.states.numStoreSgprNames.append("GateType") - self.states.numStoreSgprNameSizes.append(self.states.GateType) - self.states.numStoreSgprNames.append("GateStride") - self.states.numStoreSgprNameSizes.append(self.states.GateStride) - storeSgprLoad += self.states.numSgprAddressGate + self.states.GateType + self.states.GateStride - self.states.numStoreSgprToLoad = storeSgprLoad if self.db["InitLds"] : print ("\n***WARNING: InitLds enabled, may impact performance\n") if self.db["InitSgpr"] : print ("\n***WARNING: InitSgpr enabled, may impact performance\n") diff --git a/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py b/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py index 6db2b03772b5..ca5aef7a57e1 100644 --- a/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py +++ b/projects/hipblaslt/tensilelite/Tensile/KernelWriterAssembly.py @@ -611,6 +611,12 @@ def defineSgpr(self, name, numSgprs, align=1): def defineMultiSgprIndex(self, names: List[str], numSgprs: List[int], align=1): assert(len(names) == len(numSgprs)) + # checkOutMulti only aligns the start of the whole block, so a repeated name + # remaps self.sgprs[name] to its later index, which is aligned only by luck. + # A 64-bit arg landing on an odd SGPR then fails assembly with "invalid + # register alignment" far from the duplicate that caused it. + assert len(set(names)) == len(names), \ + "duplicate sgpr arg names: %s" % sorted({n for n in names if names.count(n) > 1}) sgprIdxVec = self.sgprPool.checkOutMulti(numSgprs, align, tags=names) #self.sgprIdx = roundUpToNearestMultiple(self.sgprIdx,align) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_define_multi_sgpr_index.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_define_multi_sgpr_index.py new file mode 100644 index 000000000000..acf192cd12fd --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_define_multi_sgpr_index.py @@ -0,0 +1,74 @@ +################################################################################ +# Copyright (C) 2026 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: MIT +################################################################################ + +"""Unit tests for ``KernelWriterAssembly.defineMultiSgprIndex``. + +``defineMultiSgprIndex`` maps epilogue kernel-arg names onto a single +``checkOutMulti`` block. Only the *start* of that block is aligned, so the +name -> index mapping has to be one-to-one: a repeated name silently rebinds +``self.sgprs[name]`` to the later index, which is aligned only by luck. A +64-bit arg (e.g. ``AddressGate``) that lands on an odd SGPR then fails +assembly with "invalid register alignment", far from the duplicate registration +that caused it. +""" + +import pytest + +from rocisa.enum import RegisterType +from rocisa.register import RegisterPool + +from Tensile.KernelWriterAssembly import KernelWriterAssembly + +pytestmark = pytest.mark.unit + + +class _Writer: + """Minimal stand-in exposing only what defineMultiSgprIndex touches.""" + + def __init__(self, size=64): + self.sgprPool = RegisterPool(8, RegisterType.Sgpr, False) + self.sgprPool.add(0, size, "init") + self.sgprs = {} + + +def _define(writer, names, sizes, align=4): + return KernelWriterAssembly.defineMultiSgprIndex(writer, names, sizes, align=align) + + +def test_maps_each_name_to_its_own_index(): + """Names are packed back-to-back; only the block start honors align.""" + writer = _Writer() + names = ["AddressGate", "GateType", "GateStride"] + + idxVec = _define(writer, names, [2, 1, 1]) + + assert idxVec[0] % 4 == 0, "block start must honor the requested alignment" + # Packed sequentially, so interior entries are not individually aligned -- + # this is exactly why a duplicate name is dangerous. + assert idxVec == [idxVec[0], idxVec[0] + 2, idxVec[0] + 3] + assert {n: writer.sgprs[n] for n in names} == dict(zip(names, idxVec)) + + +def test_rejects_duplicate_names(): + """Regression: the gate-residual args were once registered twice. + + The second registration rebound AddressGate to an odd SGPR and broke + assembly of hipSPARSELt gate-residual kernels. Duplicates must be rejected + up front, naming the offender. + """ + writer = _Writer() + names = ["AddressGate", "GateType", "GateStride", + "AddressGate", "GateType", "GateStride"] + + with pytest.raises(AssertionError, match="AddressGate"): + _define(writer, names, [2, 1, 1, 2, 1, 1]) + + assert writer.sgprs == {}, "nothing should be bound when the input is rejected" + + +def test_rejects_mismatched_name_and_size_counts(): + writer = _Writer() + with pytest.raises(AssertionError): + _define(writer, ["AddressGate", "GateType"], [2]) From fe11d5746191333f014aa37cda099a7985a99182 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Fri, 7 Aug 2026 18:46:33 +0000 Subject: [PATCH 49/58] fix merge conflicts --- .../include/Tensile/ContractionSolution.hpp | 1 + .../hipblaslt/tensilelite/src/ContractionSolution.cpp | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 91336f52aa70..612b6a1b02e1 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -662,6 +662,7 @@ namespace TensileLite int32_t autoWGM, size_t autoWGMXCC, size_t autoWGMXCCCHUNK, + size_t autoWGMXCCSPLITK, size_t autoStaggerUMapping, size_t autoStaggerU, size_t autoStaggerUStrideShift, diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 76009a582cd3..4075ed28a494 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -2028,6 +2028,7 @@ namespace TensileLite int32_t autoWGM, size_t autoWGMXCC, size_t autoWGMXCCCHUNK, + size_t autoWGMXCCSPLITK, size_t autoStaggerUMapping, size_t autoStaggerU, size_t autoStaggerUStrideShift, @@ -2044,7 +2045,7 @@ namespace TensileLite uint32_t internalArg0; uint32_t internalArg1; - calculateInternalArgs(internalArg0, internalArg1, hardware, param, autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); + calculateInternalArgs(internalArg0, internalArg1, hardware, param, autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoWGMXCCSPLITK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); args.template append("internalArgs", internalArg0); @@ -2453,12 +2454,13 @@ namespace TensileLite rv.sharedMemBytes = 0; - auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] = calculateAutoWGM(problem, &hardware, sk.grid); + auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoWGMXCCSPLITK] + = calculateAutoWGM(problem, &hardware, sk.grid); auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); AdaptiveGemmNTAB ntab = calculateAdaptiveGemmNTAB(problem, &hardware); uint32_t internalArg0 = 0; uint32_t internalArg1 = 0; - calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); + calculateInternalArgs(internalArg0, internalArg1, &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoWGMXCCSPLITK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); uint32_t debugPattern = 0xDB000001; bool appendedInternalArgs = false; @@ -2812,13 +2814,14 @@ namespace TensileLite break; case CustomArgSemantic::InternalArgs: { - auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK] + auto [autoWGM, autoWGMXCC, autoWGMXCCCHUNK, autoWGMXCCSPLITK] = calculateAutoWGM(problem, &hardware, sk.grid); auto [autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift] = calculateAutoStaggerU(problem, &hardware, sk.grid, autoWGM); kernelArgs(1, 0, rv.args, getNumWorkGroups(rv), &hardware, problem.getParams(), autoWGM, autoWGMXCC, autoWGMXCCCHUNK, + autoWGMXCCSPLITK, autoStaggerUMapping, autoStaggerU, autoStaggerUStrideShift, autoGsuVal, ntab); appendedInternalArgs = true; From 21ca404357553d63a5a4f1372d5fa43f962f6c6e Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Tue, 11 Aug 2026 01:16:45 +0000 Subject: [PATCH 50/58] address comments --- .../tensilelite/Tensile/CustomKernels.py | 9 +- .../tensilelite/Tensile/LibraryIO.py | 6 +- .../Tensile/SolutionStructs/Naming.py | 11 +- .../Tensile/SolutionStructs/Solution.py | 5 +- .../TensileLogic/HandleCustomKernel.py | 5 +- .../test_CustomKernels_config_detection.py | 54 ++++++ .../include/Tensile/ContractionSolution.hpp | 14 +- .../tensilelite/src/ContractionSolution.cpp | 53 ++++-- .../hipblaslt/tensilelite/src/DataTypes.cpp | 4 + .../tensilelite/tests/CMakeLists.txt | 1 + .../tensilelite/tests/CustomKernel_test.cpp | 167 ++++++++++++++++++ .../tensilelite/tests/DataTypes_test.cpp | 18 ++ 12 files changed, 310 insertions(+), 37 deletions(-) create mode 100644 projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_config_detection.py create mode 100644 projects/hipblaslt/tensilelite/tests/CustomKernel_test.cpp diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index f7d843d520af..e13f7b1f99dd 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -99,10 +99,11 @@ _PASSTHROUGH_KEYS = {"ProblemType", "InternalSupportParams", "KernelLanguage", "CustomKernelName"} def isCustomKernelConfig(config): - if "CustomKernel" in config and config["CustomKernel"]["name"]: - if config["CustomKernel"].get("generated", False): - return False - return True + # CustomKernel may be absent, None, or the -1 placeholder for an unset parameter, + # so check that it is a populated dict before reaching into it. + ck = config.get("CustomKernel") + if isinstance(ck, dict) and ck.get("name"): + return not ck.get("generated", False) return bool(config.get("CustomKernelName", "")) def getCustomKernelFilepath(name, directory=CUSTOM_KERNEL_PATH): diff --git a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py index 665ff9190a35..9c4371324961 100644 --- a/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py +++ b/projects/hipblaslt/tensilelite/Tensile/LibraryIO.py @@ -675,9 +675,9 @@ def solutionStateToSolution(solutionState, assembler, isaInfoMap) -> Optional[So solutionState["AssignedProblemIndependentDerivedParameters"] = False solutionState["AssignedDerivedParameters"] = False customKernelName = None - if "CustomKernel" in solutionState and solutionState["CustomKernel"]["name"] \ - and not solutionState["CustomKernel"].get("generated", False): - customKernelName = solutionState["CustomKernel"]["name"] + ck = solutionState.get("CustomKernel") + if isinstance(ck, dict) and ck.get("name") and not ck.get("generated", False): + customKernelName = ck["name"] elif solutionState.get("CustomKernelName", ""): customKernelName = solutionState["CustomKernelName"] diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py index 26f5ecc73b02..22b2ead285a7 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Naming.py @@ -154,8 +154,9 @@ def getParameterValueAbbreviation(key, value): def _getName(state, requiredParameters: frozenset, splitGSU: bool, ignoreInternalArgs): - if "CustomKernel" in state and state["CustomKernel"]["name"]: - return state["CustomKernel"]["name"] + ck = state.get("CustomKernel") + if isinstance(ck, dict) and ck.get("name"): + return ck["name"] if state.get("CustomKernelName", ""): return state["CustomKernelName"] @@ -254,9 +255,9 @@ def shortenFileBase(splitGSU, kernel): def getKernelFileBase(splitGSU: bool, kernel): - if "CustomKernel" in kernel and kernel["CustomKernel"]["name"] \ - and not kernel["CustomKernel"].get("generated", False): - fileBase = kernel["CustomKernel"]["name"] + ck = kernel.get("CustomKernel") + if isinstance(ck, dict) and ck.get("name") and not ck.get("generated", False): + fileBase = ck["name"] elif kernel.get("CustomKernelName", ""): fileBase = kernel["CustomKernelName"] else: diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 456587a4877b..f43f98f04e4e 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -4879,9 +4879,10 @@ def subCheckLdsBlockSizePerPad(tc, idx): else: reject(state, printRejectionReason, "%s's padded address is inconsistent"%tc) + ck = state.get("CustomKernel") isActualCustomKernel = bool(state.get("CustomKernelName", "")) or \ - ("CustomKernel" in state and state["CustomKernel"]["name"] != "" - and not state["CustomKernel"].get("generated", False)) + (isinstance(ck, dict) and bool(ck.get("name")) + and not ck.get("generated", False)) if(not isActualCustomKernel): checkLdsBlockSizePerPad("A") checkLdsBlockSizePerPad("B") diff --git a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py index 10fdcc5b0495..2e37367a1812 100644 --- a/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py +++ b/projects/hipblaslt/tensilelite/Tensile/TensileLogic/HandleCustomKernel.py @@ -49,8 +49,9 @@ def handleCustomKernel(sol: dict, isaInfoMap: Dict[IsaVersion, IsaInfo]) -> Tupl if not isCustomKernelConfig(sol): return sol, False - if "CustomKernel" in sol and sol["CustomKernel"]["name"]: - name = sol["CustomKernel"]["name"] + ck = sol.get("CustomKernel") + if isinstance(ck, dict) and ck.get("name"): + name = ck["name"] else: name = sol.get("CustomKernelName", "") dir = CUSTOM_KERNEL_PATH diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_config_detection.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_config_detection.py new file mode 100644 index 000000000000..7942c41d2d3b --- /dev/null +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_config_detection.py @@ -0,0 +1,54 @@ +# Copyright Advanced Micro Devices, Inc., or its affiliates. +# SPDX-License-Identifier: MIT +"""Unit tests for detecting a custom-kernel solution config.""" + +import pytest + +from Tensile.Common.ValidParameters import validParameters +from Tensile.CustomKernels import isCustomKernelConfig +from Tensile.SolutionStructs.Naming import getKernelFileBase + +pytestmark = pytest.mark.unit + + +# "CustomKernel" is seeded with the -1 placeholder for an unset parameter, and a +# partially populated solution can carry None, a stray scalar, or a dict with no +# name. None of those are subscriptable, so detection has to type-check first. +MALFORMED = [-1, None, "a_kernel_name", {}] + + +def test_unset_custom_kernel_placeholder_is_not_a_dict(): + assert not isinstance(validParameters["CustomKernel"], dict) + + +@pytest.mark.parametrize("value", MALFORMED) +def test_malformed_custom_kernel_is_not_a_custom_kernel_config(value): + assert isCustomKernelConfig({"CustomKernel": value}) is False + + +def test_malformed_custom_kernel_still_honors_the_legacy_name(): + assert isCustomKernelConfig({"CustomKernel": -1, "CustomKernelName": "legacy"}) is True + + +def test_well_formed_custom_kernel_is_detected(): + assert isCustomKernelConfig({"CustomKernel": {"name": "a_kernel_name"}}) is True + + +def test_generated_custom_kernel_is_not_treated_as_a_custom_kernel(): + assert ( + isCustomKernelConfig({"CustomKernel": {"name": "a_kernel_name", "generated": True}}) + is False + ) + + +def test_kernel_file_base_falls_back_when_custom_kernel_is_malformed(): + assert getKernelFileBase(False, {"CustomKernel": -1, "CustomKernelName": "legacy"}) == "legacy" + + +def test_generated_custom_kernel_does_not_name_the_output_file(): + kernel = { + "CustomKernel": {"name": "a_kernel_name", "generated": True}, + "CustomKernelName": "legacy", + } + + assert getKernelFileBase(False, kernel) == "legacy" diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 612b6a1b02e1..d89502743b65 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -209,14 +209,16 @@ namespace TensileLite struct CustomKernel { + // Every member needs a default: mapOptional leaves absent keys untouched, so an + // incomplete logic file would otherwise deserialize into indeterminate values. std::string name; std::vector args; - dim3 macrotile; - dim3 threads; - vector3 grid; - CustomWorkspaceType workspaceType; - size_t workspaceSizePerElemC; - size_t workspaceSizePerElemBias; + dim3 macrotile{0, 0, 0}; + dim3 threads{0, 0, 0}; + vector3 grid{CustomGridSize::One, CustomGridSize::One, CustomGridSize::One}; + CustomWorkspaceType workspaceType = CustomWorkspaceType::None; + size_t workspaceSizePerElemC = 0; + size_t workspaceSizePerElemBias = 0; // True when this CustomKernel was auto-populated for a Tensile-generated // kernel (vs. a hand-written custom kernel). Generated kernels still // rely on sizeMapping for workspace/Stream-K decisions, so several code diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index 4075ed28a494..45d83a1e4158 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -2515,11 +2515,24 @@ namespace TensileLite case CustomArgSemantic::SizeSumDiv2: rv.args.appendCustomType("SizeSumDiv2", problem.problemSizes()[problem.problemSizes().size() - 1] / 2, arg.type); break; + // size() is unsigned, so a problem with too few dimensions would wrap the + // index to a huge value and read out of bounds; fall back to 1 (an + // identity summation extent) instead. case CustomArgSemantic::SizeSum1: - rv.args.appendCustomType("SizeSum1", problem.problemSizes()[problem.problemSizes().size() - 2], arg.type); + rv.args.appendCustomType( + "SizeSum1", + problem.problemSizes().size() >= 2 + ? problem.problemSizes()[problem.problemSizes().size() - 2] + : 1, + arg.type); break; case CustomArgSemantic::SizeSum2: - rv.args.appendCustomType("SizeSum2", problem.problemSizes()[problem.problemSizes().size() - 3], arg.type); + rv.args.appendCustomType( + "SizeSum2", + problem.problemSizes().size() >= 3 + ? problem.problemSizes()[problem.problemSizes().size() - 3] + : 1, + arg.type); break; case CustomArgSemantic::StrideA0: rv.args.appendCustomType("StrideA0", problem.a().strides()[1], arg.type); @@ -2631,24 +2644,28 @@ namespace TensileLite rv.args.appendCustomType("StrideCK", splitKStride, arg.type); break; } + // The lowercase names are load-bearing: KernelArguments::append matches + // on "alpha"/"beta" to promote a sub-32-bit compute type to 32 bits, which + // is what a custom kernel's declared 32-bit scalar slot expects. Spelling + // them any other way emits the narrow type instead and shifts every + // argument that follows. case CustomArgSemantic::Alpha: - rv.args.append("Alpha", inputs.alpha, problem.alphaType()); - if(problem.alphaType() == rocisa::DataType::Half) - rv.args.append("Alpha_2", inputs.alpha, problem.alphaType()); + rv.args.append("alpha", inputs.alpha, problem.alphaType()); break; case CustomArgSemantic::Beta: - rv.args.append("Beta", inputs.beta, problem.betaType()); - if(problem.betaType() == rocisa::DataType::Half) - rv.args.append("Beta_2", inputs.beta, problem.betaType()); + rv.args.append("beta", inputs.beta, problem.betaType()); break; case CustomArgSemantic::SplitK: { - // AITER kernel expects log2(GSU) rather than the raw GSU value - uint32_t gsu = sizeMapping.globalSplitU; - uint32_t splitK = 0; - if(gsu > 1) + // AITER kernel expects log2(GSU) rather than the raw GSU value. + // Derive it from the runtime-effective gsu, not sizeMapping's + // compiled-in value: a user-specified or adaptively-downgraded GSU + // must agree with the grid/workspace sizing and with StrideCK above. + uint32_t remaining = gsu; + uint32_t splitK = 0; + if(remaining > 1) { - while(gsu >>= 1) + while(remaining >>= 1) splitK++; } rv.args.appendCustomType("SplitK", splitK, arg.type); @@ -2866,9 +2883,13 @@ namespace TensileLite break; // ---- Packed batch dimension divisors ---- + // arg.index comes from the kernel's custom.config, so it is untrusted; + // fall back to a dimension of 1 rather than indexing out of bounds. case CustomArgSemantic::MagicNumberSize: { - uint32_t dimSize = problem.problemSizes()[arg.index]; + uint32_t dimSize = arg.index < problem.problemSizes().size() + ? problem.problemSizes()[arg.index] + : 1; uint32_t magicShift; uint32_t magicNum = magicNumber(sizeMapping.magicDivAlg, dimSize, &magicShift); rv.args.template append("MagicNumberSize", magicNum); @@ -2876,7 +2897,9 @@ namespace TensileLite } case CustomArgSemantic::MagicShiftSize: { - uint32_t dimSize = problem.problemSizes()[arg.index]; + uint32_t dimSize = arg.index < problem.problemSizes().size() + ? problem.problemSizes()[arg.index] + : 1; uint32_t magicShift; magicNumber(sizeMapping.magicDivAlg, dimSize, &magicShift); rv.args.template append("MagicShiftSize", magicShift); diff --git a/projects/hipblaslt/tensilelite/src/DataTypes.cpp b/projects/hipblaslt/tensilelite/src/DataTypes.cpp index 00fbd8abd2e1..f77d94590353 100644 --- a/projects/hipblaslt/tensilelite/src/DataTypes.cpp +++ b/projects/hipblaslt/tensilelite/src/DataTypes.cpp @@ -509,6 +509,10 @@ namespace TensileLite return CustomArgType::int8; else if(str == toString(CustomArgType::uint8)) return CustomArgType::uint8; + else if(str == toString(CustomArgType::int16)) + return CustomArgType::int16; + else if(str == toString(CustomArgType::uint16)) + return CustomArgType::uint16; else if(str == toString(CustomArgType::int32)) return CustomArgType::int32; else if(str == toString(CustomArgType::uint32)) diff --git a/projects/hipblaslt/tensilelite/tests/CMakeLists.txt b/projects/hipblaslt/tensilelite/tests/CMakeLists.txt index 00458f198c12..57395f1477fd 100644 --- a/projects/hipblaslt/tensilelite/tests/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/tests/CMakeLists.txt @@ -23,6 +23,7 @@ target_sources(tensilelite-tests "${CMAKE_CURRENT_SOURCE_DIR}/AlmostEqual_test.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/ContractionSelectionLibrary_test.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/CuCount_test.cpp" + "${CMAKE_CURRENT_SOURCE_DIR}/CustomKernel_test.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/DataTypes_test.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/DataInit_test.cpp" "${CMAKE_CURRENT_SOURCE_DIR}/ExactLogicLibrary_test.cpp" diff --git a/projects/hipblaslt/tensilelite/tests/CustomKernel_test.cpp b/projects/hipblaslt/tensilelite/tests/CustomKernel_test.cpp new file mode 100644 index 000000000000..37bdebee436d --- /dev/null +++ b/projects/hipblaslt/tensilelite/tests/CustomKernel_test.cpp @@ -0,0 +1,167 @@ +/******************************************************************************* + * + * MIT License + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + *******************************************************************************/ + +#include +#include + +#include + +#include + +#include "FallbackTestUtils.hpp" + +using namespace TensileLite; +using TensileLite::testing::dummyProblem; +using TensileLite::testing::makeDevice; + +// generateKernelCall rejects a solution whose metadata was never populated by +// testing threads.x / macrotile.x against zero. Every field is deserialized with +// mapOptional and vector3 leaves its components uninitialized by default, so that +// guard only means anything if an unpopulated CustomKernel really does hold zeros. +TEST(CustomKernelTest, DefaultsTripTheUninitializedMetadataGuard) +{ + CustomKernel kernel; + + EXPECT_EQ(kernel.threads.x, 0u); + EXPECT_EQ(kernel.macrotile.x, 0u); +} + +namespace +{ + // Just enough metadata to get past the guards in generateCustomCall, carrying a + // single argument so the emitted buffer holds exactly that value. + void configureProbeKernel(ContractionSolution& solution, CustomArgDefinition arg) + { + solution.sizeMapping.macroTile = TensileLite::dim3(128, 128, 1); + solution.sizeMapping.depthU = 64; + // Pin the work-group mapping: the auto path reads it off a HipAMDGPU, which a + // plain AMDGPU test device is not. + solution.sizeMapping.workGroupMapping = 1; + solution.sizeMapping.workGroupMappingXCC = 1; + + solution.customKernel.name = "probe"; + solution.customKernel.macrotile = TensileLite::dim3(128, 128, 64); + solution.customKernel.threads = TensileLite::dim3(256, 1, 1); + solution.customKernel.grid + = {CustomGridSize::TilesX, CustomGridSize::TilesY, CustomGridSize::One}; + solution.customKernel.args = {arg}; + } + + AMDGPU probeDevice() + { + return makeDevice(TensileLite::testing::_MI350_CHIP_ID, + TensileLite::testing::_SPX_CU, + "mi350spx"); + } + + uint32_t emittedSplitK(int16_t compiledGsu, int16_t runtimeGsu) + { + ContractionSolution solution; + configureProbeKernel(solution, {CustomArgType::uint32, CustomArgSemantic::SplitK}); + solution.sizeMapping.globalSplitU = compiledGsu; + + auto problem = dummyProblem(); + problem.setParams().setGSU(runtimeGsu); + + auto device = probeDevice(); + ContractionInputs inputs; + StreamKSettings sk; + + auto invocation = solution.generateCustomCall(problem, inputs, device, sk); + + EXPECT_EQ(invocation.args.size(), sizeof(uint32_t)); + uint32_t splitK = 0; + std::memcpy(&splitK, invocation.args.data(), sizeof(splitK)); + return splitK; + } + + std::vector emittedScalar(CustomArgSemantic semantic, + rocisa::DataType computeType, + ConstantVariant value) + { + ContractionSolution solution; + configureProbeKernel(solution, {CustomArgType::float32, semantic}); + solution.sizeMapping.globalSplitU = 1; + + auto problem = dummyProblem(); + problem.setAlphaType(computeType); + problem.setBetaType(computeType); + + auto device = probeDevice(); + ContractionInputs inputs; + inputs.alpha = value; + inputs.beta = value; + StreamKSettings sk; + + auto invocation = solution.generateCustomCall(problem, inputs, device, sk); + + auto const* bytes = static_cast(invocation.args.data()); + return std::vector(bytes, bytes + invocation.args.size()); + } +} + +// The kernel wants log2(GSU). Taking it from the solution's compiled-in +// globalSplitU disagrees with the grid and workspace sizing, which are built from +// the runtime-effective GSU, so a user-supplied GSU has to win here too. +TEST(CustomKernelTest, SplitKFollowsTheRuntimeGsu) +{ + EXPECT_EQ(emittedSplitK(/*compiled*/ 1, /*runtime*/ 8), 3u); + EXPECT_EQ(emittedSplitK(/*compiled*/ 1, /*runtime*/ 4), 2u); + EXPECT_EQ(emittedSplitK(/*compiled*/ 8, /*runtime*/ 1), 0u); +} + +// With no runtime override the effective GSU falls back to the compiled value, so +// the emitted argument is unchanged for kernels that never set one. +TEST(CustomKernelTest, SplitKFallsBackToTheCompiledGsu) +{ + EXPECT_EQ(emittedSplitK(/*compiled*/ 1, /*runtime*/ 0), 0u); + EXPECT_EQ(emittedSplitK(/*compiled*/ 16, /*runtime*/ 0), 4u); +} + +// A custom kernel declares alpha and beta as 32-bit slots, so a narrower compute +// type has to be widened before it is written or every argument after it shifts. +// KernelArguments only widens an argument spelled exactly "alpha" or "beta". +TEST(CustomKernelTest, ScalarsFillTheDeclaredThirtyTwoBitSlot) +{ + for(auto semantic : {CustomArgSemantic::Alpha, CustomArgSemantic::Beta}) + { + EXPECT_EQ(emittedScalar(semantic, rocisa::DataType::Float, 1.5f).size(), + sizeof(float)); + + auto const fromHalf + = emittedScalar(semantic, rocisa::DataType::Half, static_cast(1.5f)); + ASSERT_EQ(fromHalf.size(), sizeof(float)); + + float widened = 0.0f; + std::memcpy(&widened, fromHalf.data(), sizeof(widened)); + EXPECT_EQ(widened, 1.5f); + + EXPECT_EQ( + emittedScalar(semantic, rocisa::DataType::BFloat16, static_cast(1.5f)) + .size(), + sizeof(float)); + } +} diff --git a/projects/hipblaslt/tensilelite/tests/DataTypes_test.cpp b/projects/hipblaslt/tensilelite/tests/DataTypes_test.cpp index 8683d47ca9ba..1e258e982f2f 100644 --- a/projects/hipblaslt/tensilelite/tests/DataTypes_test.cpp +++ b/projects/hipblaslt/tensilelite/tests/DataTypes_test.cpp @@ -148,3 +148,21 @@ INSTANTIATE_TEST_SUITE_P(DataTypesTest, rocisa::DataType::Int8, rocisa::DataType::Int8x4, rocisa::DataType::Int32)); + +// A CustomArgType that toString() emits but fromStringCustomArgType() cannot parse +// makes that type unusable in a custom kernel's custom.config, and only fails once +// someone writes a config using it. Walk the whole enum so new types stay covered. +TEST(DataTypesTest, CustomArgTypeRoundTrip) +{ + using TensileLite::CustomArgType; + + for(int i = 0; i < static_cast(CustomArgType::CustomArgType_Count); i++) + { + auto const value = static_cast(i); + std::string name = TensileLite::toString(value); + + EXPECT_FALSE(name.empty()) << "CustomArgType " << i << " has no string form"; + EXPECT_EQ(TensileLite::fromStringCustomArgType(name), value) + << "round trip failed for \"" << name << "\""; + } +} From 381722fc71038219ad04d5ec36945356a9ce0e73 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 19 Aug 2026 18:15:38 +0000 Subject: [PATCH 51/58] fix regression of test from develop --- .../unit/test_vgpr_overflow_force_generate.py | 25 ++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_vgpr_overflow_force_generate.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_vgpr_overflow_force_generate.py index fb91f7a0e6e5..a361d7eb27c6 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_vgpr_overflow_force_generate.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_vgpr_overflow_force_generate.py @@ -209,28 +209,47 @@ def _getKernelSource(self, warnings): return namespace["_getKernelSource"] def _writer(self, error, forceGenerateKernel): + # _getKernelSource also records the kernel's own CustomKernel metadata, so a + # SimpleNamespace standing in for a real writer must carry what that path + # reads: the arg-registration hook, the kernel name and the collected arg + # definitions. A real KernelWriter always has all three. return SimpleNamespace( _initKernel=lambda kernel, tPA, tPB: None, + _registerKernelArgs=lambda kernel: None, + states=SimpleNamespace(kernelName="test_kernel"), + kernelArgDefs=[], stringIdx=0, kernelBody=lambda kernel, tPA, tPB: (error, "s_endpgm\n"), kernelBodySubtile=lambda kernel, tPA, tPB: (error, "s_endpgm\n"), debugConfig=SimpleNamespace(forceGenerateKernel=forceGenerateKernel), ) + def _kernel(self): + # The solution keys that same metadata is built from; a real Solution always + # has them. StreamK is off, so the Stream-K grid branch is not taken here. + return { + "UseSubtileImpl": False, + "StreamK": 0, + "MacroTile0": 128, + "MacroTile1": 128, + "DepthU": 32, + "NumThreads": 256, + } + def test_overflowing_kernel_is_rejected_by_default(self): # Default behaviour is unchanged from before the fix: an overflowing # kernel still fails the build, just from here instead of _initKernel. getKernelSource = self._getKernelSource([]) with pytest.raises(RuntimeError): getKernelSource(self._writer(error=1, forceGenerateKernel=False), - {"UseSubtileImpl": False}) + self._kernel()) def test_force_generate_kernel_keeps_the_source(self): # The behaviour the early raise made unreachable. warnings = [] getKernelSource = self._getKernelSource(warnings) source = getKernelSource(self._writer(error=1, forceGenerateKernel=True), - {"UseSubtileImpl": False}) + self._kernel()) assert "s_endpgm" in source assert any("ForceGenerateKernel" in str(w) for w in warnings), ( "saving the source of a rejected kernel must be announced" @@ -240,6 +259,6 @@ def test_clean_kernel_is_unaffected(self): warnings = [] getKernelSource = self._getKernelSource(warnings) source = getKernelSource(self._writer(error=0, forceGenerateKernel=False), - {"UseSubtileImpl": False}) + self._kernel()) assert "s_endpgm" in source assert warnings == [] From 8155d1880e3d4b5375947497b65d77d879f12c28 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Sat, 22 Aug 2026 06:41:30 +0000 Subject: [PATCH 52/58] fix mxDataGenerator headers --- projects/hipblaslt/tensilelite/CMakeLists.txt | 23 +++++++++++++++---- .../include/Tensile/ContractionSolution.hpp | 6 ----- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/projects/hipblaslt/tensilelite/CMakeLists.txt b/projects/hipblaslt/tensilelite/CMakeLists.txt index 21c3862dc80a..103e647f33bd 100644 --- a/projects/hipblaslt/tensilelite/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/CMakeLists.txt @@ -91,9 +91,10 @@ if(TENSILELITE_ENABLE_HOST) # mxDataGenerator supplies the gfx950 pre-swizzled MX scale padding helper behind # the StrideScaleA1/StrideScaleB1 custom-kernel semantics. Treat it as optional: # HIPBLASLT_ENABLE_MXDATAGENERATOR is OFF on Windows, and shared/mxdatagenerator - # is absent from checkouts that vendor only projects/hipblaslt (hipSPARSELt CI), - # so probe for it instead of hard-requiring it. + # is absent from checkouts that vendor only projects/hipblaslt, so probe for it + # instead of hard-requiring it. set(TENSILELITE_HOST_MXDATAGENERATOR ${HIPBLASLT_ENABLE_MXDATAGENERATOR}) + set(_mxdatagen_target roc::mxDataGenerator) if(TENSILELITE_HOST_MXDATAGENERATOR AND NOT TARGET roc::mxDataGenerator) set(_mxdatagen_src "${CMAKE_CURRENT_SOURCE_DIR}/../../../shared/mxdatagenerator") if(HIPBLASLT_ENABLE_THEROCK) @@ -101,8 +102,20 @@ if(TENSILELITE_ENABLE_HOST) if(NOT mxDataGenerator_FOUND) set(TENSILELITE_HOST_MXDATAGENERATOR OFF) endif() - elseif(EXISTS "${_mxdatagen_src}/CMakeLists.txt") - add_subdirectory("${_mxdatagen_src}" "${CMAKE_CURRENT_BINARY_DIR}/mxdatagenerator") + elseif(EXISTS "${_mxdatagen_src}/lib/include/mxDataGenerator/PreSwizzle.hpp") + # Consume the header-only helper directly rather than add_subdirectory()ing + # mxDataGenerator: its CMakeLists emits install() rules unconditionally and + # EXCLUDE_FROM_ALL does not suppress them, so vendoring it here republishes + # its 25 headers and 3 package files from whatever install tree embeds this + # subdirectory. hipSPARSELt embeds it, which put those files in TheRock's + # blas artifact alongside support's own copy (rocm-libraries#11105). + find_package(OpenMP REQUIRED) + add_library(tensilelite-mxdatagenerator-headers INTERFACE) + target_include_directories(tensilelite-mxdatagenerator-headers + INTERFACE $) + target_link_libraries(tensilelite-mxdatagenerator-headers + INTERFACE OpenMP::OpenMP_CXX) + set(_mxdatagen_target tensilelite-mxdatagenerator-headers) else() set(TENSILELITE_HOST_MXDATAGENERATOR OFF) endif() @@ -123,7 +136,7 @@ if(TENSILELITE_ENABLE_HOST) ) if(TENSILELITE_HOST_MXDATAGENERATOR) - target_link_libraries(tensilelite-host PRIVATE roc::mxDataGenerator) + target_link_libraries(tensilelite-host PRIVATE ${_mxdatagen_target}) target_compile_definitions(tensilelite-host PRIVATE HIPBLASLT_ENABLE_MXDATAGENERATOR) endif() diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 1e202f22dc3b..62dfa1f22a1e 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -373,12 +373,6 @@ namespace TensileLite std::array waveGroup; }; - struct CustomKernel - { - std::string name; - bool generated = false; - }; - struct StreamKSettings { origami::reduction_t reduction = origami::reduction_t::tree; From 2babe5c3ae36f12344aae73ce9c6d5bb6e9d8c40 Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Thu, 27 Aug 2026 20:45:41 +0000 Subject: [PATCH 53/58] fix merge regressions --- .../_ZN5aiter24bf16gemm_bf16_tn_256x256E.s | 3 +- ...emm_bf16_per1x32Fp4_BpreShuffle_256x256E.s | 3 +- ..._gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s | 1 + ...leSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s | 1 + ...kdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s | 2 + .../wave/wave_bf16_gemm_256x256x64.s | 1 + .../test_pchaos_Tensile_L239_char.py | 95 +++++++++---------- .../test_custom_kernel_staggeru_metadata.py | 16 +++- 8 files changed, 64 insertions(+), 58 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s index a3c1baa8fda4..7fcc5cbdfa7f 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter24bf16gemm_bf16_tn_256x256E.s @@ -3,7 +3,7 @@ // clang -x assembler -target amdgcn-amd-amdhsa -mcpu=gfx950 -c file.s -o file.o // ld.lld -shared -o file.co file.o -// Note: Target is specified via -mcpu= command line flag +.amdgcn_target "amdgcn-amd-amdhsa--gfx950" .set .amdgcn.next_free_vgpr, 0 .set .amdgcn.next_free_sgpr, 0 @@ -2252,6 +2252,7 @@ custom.config: threads: [256, 1, 1] grid: [TilesX, TilesY, One] MatrixInstruction: [16, 16, 32, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [8, 8] AssertFree0ElementMultiple: 256 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s index 8739f5dd22f3..6f48c3cfc4ec 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/aiter/_ZN5aiter42f4gemm_bf16_per1x32Fp4_BpreShuffle_256x256E.s @@ -3,7 +3,7 @@ // clang -x assembler -target amdgcn-amd-amdhsa -mcpu=gfx950 -c file.s -o file.o // ld.lld -shared -o file.co file.o -// Note: Target is specified via -mcpu= command line flag +.amdgcn_target "amdgcn-amd-amdhsa--gfx950" .set .amdgcn.next_free_vgpr, 0 .set .amdgcn.next_free_sgpr, 0 @@ -3502,6 +3502,7 @@ custom.config: threads: [256, 1, 1] grid: [TilesX, TilesY, One] MatrixInstruction: [16, 16, 128, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [8, 8] AssertFree0ElementMultiple: 256 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s index 6145ac7a5fae..2108b034b6b9 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/ck/c_ck_gemm_basic_hip_amdgcn_amd_amdhsa_gfx942.s @@ -177418,6 +177418,7 @@ custom.config: threads: [256, 1, 1] grid: [TilesXYBatch, One, One] MatrixInstruction: [32, 32, 8, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [4, 4] WavefrontSize: 64 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s index 6f136f83ae61..02b5384aa8d3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/rocroller/RRGEMM_TN_half_half_half_half_float_WGTS64x64x64_WGS128x2_WGMXCC0_LABufferToLDS_LBBufferToLDS_SD1_LSABufferToVGPR_LSBBufferToVGPR_UNROLL0x0_SwizzleScale00_SwizzleTileSize0x0X0x0_PF4x1m1_M_98fd6c3c16c08d0e.s @@ -80553,6 +80553,7 @@ custom.config: threads: [256, 1, 1] grid: [TilesX, TilesY, Batch] MatrixInstruction: [16, 16, 16, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [2, 2] WavefrontSize: 64 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s index e32dd99566e1..cc08bf0ee808 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/triton/_gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1.s @@ -1,3 +1,4 @@ + .amdgcn_target "amdgcn-amd-amdhsa--gfx950" .text .globl _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 ; -- Begin function _gemm_afp4wfp4_kernel_BLOCK_SIZE_M_256_BLOCK_SIZE_N_256_BLOCK_SIZE_K_64_GROUP_SIZE_M_8_num_warps_4_num_stages_2_waves_per_eu_0_matrix_instr_nonkdim_16_cache_modifier_NONE_NUM_KSPLIT_1 .p2align 8 @@ -8901,6 +8902,7 @@ custom.config: threads: [256, 1, 1] grid: [TilesXY, One, One] MatrixInstruction: [16, 16, 128, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [8, 8] AssertSummationElementMultiple: 32 diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s index e064e8210d5f..44af1f649bbe 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/wave/wave_bf16_gemm_256x256x64.s @@ -1969,6 +1969,7 @@ custom.config: threads: [256, 4, 1] grid: [TilesY, TilesX, One] MatrixInstruction: [16, 16, 32, 1] + StaggerU: 0 EnableMatrixInstruction: True MIWaveTile: [4, 4] WavefrontSize: 64 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py index 5c4799f3f244..2b8b319afb4a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/characterization/PublicInputSurface/test_pchaos_Tensile_L239_char.py @@ -3,25 +3,22 @@ # SPDX-License-Identifier: MIT ################################################################################ -"""PublicInputSurface characterization: ``if args.platform:`` in -``Tensile/Tensile.py`` at line 239, inside ``argUpdatedGlobalParameters``. +"""PublicInputSurface characterization: OpenCL platform selection in +``Tensile/Tensile.py``'s ``argUpdatedGlobalParameters``. -Branch 765305e2fbcf1ee08927bffdac198278bded30ee. +This file used to pin the ``if args.platform:`` branch, which stored +``rv["Platform"] = args.platform`` from the ``-p / --platform`` CLI flag. That +flag and that branch are gone: OpenCL is no longer a supported runtime, so the +option was dropped from ``addCommonArguments`` and the assignment was replaced +by an explicit refusal. -The predicate is a bare Python truthiness test on the CLI integer flag -``-p / --platform`` (type=int, no default => None when omitted): +What is pinned now: - * TRUE branch -> ``args.platform`` is a nonzero int (e.g. 1); the block - prints a Command-line override message and stores - ``rv["Platform"] = args.platform``. - * FALSE branch -> ``args.platform`` is 0 (explicit) or None (omitted); - the block is skipped and ``rv`` does NOT get a - ``"Platform"`` key. - -Witnesses confirmed via z3 (sat on both sides) and in-container argparse replay: - TRUE: platform=1 -> rv contains "Platform" - FALSE: platform=0 -> rv does NOT contain "Platform" - FALSE: platform=None (omitted) -> rv does NOT contain "Platform" + * ``-p / --platform`` is not a recognised option any more. + * ``args.platform`` is never read, so a namespace still carrying it produces + no ``"Platform"`` key rather than an error. + * ``Platform`` can still reach ``rv`` through ``--global-parameters``, and + that path exits via ``printExit`` instead of silently configuring OpenCL. These tests pin ACTUAL observed behavior; they do not assert anything aspirational. @@ -41,13 +38,14 @@ def _make_args(**overrides): """Return a Namespace matching the fields consumed by argUpdatedGlobalParameters.""" defaults = dict( + # Retained deliberately: the point of the first test below is that this + # field is now inert, so the namespace still offers it. platform=None, RuntimeLanguage=None, CodeObjectVersion=None, debug=False, # --validate-metadata: action="store_true", so a real argparse Namespace - # always carries this (default False), unrelated to the `platform` - # predicate under test here -- see + # always carries this (default False) -- see # TensileMain/test_tensile_helpers_char.py for dedicated ValidateMetadata # coverage. ValidateMetadata=False, @@ -61,55 +59,48 @@ def _make_args(**overrides): # --------------------------------------------------------------------------- -# Unit: pure predicate truthiness (no Tensile import; no side-effects) +# The flag is gone from the public CLI surface # --------------------------------------------------------------------------- -def test_platform_predicate_true_nonzero_int(): - """bool(1) is True -> the TRUE branch is taken.""" - assert bool(1) is True - +def test_platform_flag_is_no_longer_a_recognised_option(): + """``--platform`` is left over as an unknown argument rather than parsed.""" + from Tensile.Tensile import addCommonArguments -def test_platform_predicate_false_zero(): - """bool(0) is False -> the FALSE branch is taken.""" - assert bool(0) is False + parser = argparse.ArgumentParser() + addCommonArguments(parser) + _, unknown = parser.parse_known_args(["--platform", "1"]) + assert "--platform" in unknown -def test_platform_predicate_false_none(): - """bool(None) is False -> the FALSE branch is taken when -p is omitted.""" - assert bool(None) is False + assert "platform" not in {action.dest for action in parser._actions} # --------------------------------------------------------------------------- -# Integration: call argUpdatedGlobalParameters directly, pin rv["Platform"] +# argUpdatedGlobalParameters no longer reads args.platform at all # --------------------------------------------------------------------------- -def test_platform_true_branch_sets_rv_key(capsys): - """TRUE branch (platform=1): rv contains 'Platform' == 1.""" - from Tensile.Tensile import argUpdatedGlobalParameters - - args = _make_args(platform=1) - rv = argUpdatedGlobalParameters(args) - assert "Platform" in rv, "Expected 'Platform' key in rv for truthy platform" - assert rv["Platform"] == 1 - - -def test_platform_false_branch_zero_no_rv_key(): - """FALSE branch (platform=0): rv does NOT contain 'Platform'.""" +@pytest.mark.parametrize("platform", [1, 0, None], ids=["nonzero", "zero", "omitted"]) +def test_args_platform_is_ignored(platform): + """Whatever the namespace carries, no 'Platform' key is produced.""" from Tensile.Tensile import argUpdatedGlobalParameters - args = _make_args(platform=0) - rv = argUpdatedGlobalParameters(args) + rv = argUpdatedGlobalParameters(_make_args(platform=platform)) assert "Platform" not in rv, ( - "Expected no 'Platform' key in rv for falsy platform=0; got rv={}".format(rv) + "args.platform is no longer consulted; got rv={}".format(rv) ) -def test_platform_false_branch_none_no_rv_key(): - """FALSE branch (platform=None, omitted): rv does NOT contain 'Platform'.""" +# --------------------------------------------------------------------------- +# The one surviving route to a Platform key is refused outright +# --------------------------------------------------------------------------- + +def test_platform_via_global_parameters_exits(capsys): + """--global-parameters Platform=1 reaches rv, and is rejected there.""" from Tensile.Tensile import argUpdatedGlobalParameters - args = _make_args(platform=None) - rv = argUpdatedGlobalParameters(args) - assert "Platform" not in rv, ( - "Expected no 'Platform' key in rv for falsy platform=None; got rv={}".format(rv) - ) + args = _make_args(global_parameters=[("Platform", 1)]) + with pytest.raises(SystemExit) as excinfo: + argUpdatedGlobalParameters(args) + + assert excinfo.value.code == -1 + assert "OpenCL platform selection is no longer supported" in capsys.readouterr().out diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_staggeru_metadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_staggeru_metadata.py index baac2aa661f4..0ff81ec1990a 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_staggeru_metadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_staggeru_metadata.py @@ -72,7 +72,12 @@ def _findTool(name: str) -> Optional[str]: # suite where a change to a custom kernel will actually run it. MAX_WORKERS = min(32, (os.cpu_count() or 4) * 2) -_TARGET = re.compile(r'^\.amdgcn_target\s+"amdgcn-amd-amdhsa--([a-z0-9]+)', re.MULTILINE) +# Tensile emits the directive in column 0, but kernels that reach CustomKernels/ from +# other toolchains do not: llc and hipcc both indent it. Leading whitespace is legal +# assembly, so accept it rather than reformatting generated sources. +_TARGET = re.compile( + r'^[ \t]*\.amdgcn_target\s+"amdgcn-amd-amdhsa--([a-z0-9]+)', re.MULTILINE +) # One decoded instruction, recognised by the address/encoding comment # llvm-objdump appends; labels, section headers and blank lines lack it. @@ -489,7 +494,7 @@ def test_compiled_stagger_stays_reachable_by_the_host_clamp(name): # adding or retuning a custom kernel forces the reconciliation to be redone # rather than shifting the ground truth underneath the gate. EXPECTED_CENSUS = { - "kernels": 119, + "kernels": 126, # Explicit non-zero StaggerU: 24 at 8 and 4 at 4. "declaredNonZero": 28, # Of those, the ones with no packed unpack at all: StaggerU is a literal @@ -497,9 +502,12 @@ def test_compiled_stagger_stays_reachable_by_the_host_clamp(name): # SupportCustomStaggerU: False and why the gate refuses them. "declaredNonZeroWithLiteralStagger": 24, "declaredNonZeroReadingPackedArgument": 4, - "declaredZero": 60, + # Includes the six kernels built outside Tensile (aiter, ck, rocroller, + # triton, wave), which declare StaggerU: 0 because they do not implement + # the in-loop wrap at all; the disassembly confirms none of them staggers. + "declaredZero": 66, # No StaggerU key at all, so they inherit the default of 32. - "undeclared": 31, + "undeclared": 32, } From 87159af2cf0e675a190c44a04cde9d1e35f0442b Mon Sep 17 00:00:00 2001 From: Alex Brown Date: Fri, 11 Sep 2026 18:11:43 -0500 Subject: [PATCH 54/58] Fix some unit tests after merge conflicts --- .../tensilelite/Tensile/CustomKernels.py | 5 ++-- .../Tests/unit/test_CustomKernelMetadata.py | 2 +- .../Tests/unit/test_CustomKernels_ordering.py | 8 ++++++ .../unit/test_CustomKernels_resources.py | 1 - .../Tensile/Tests/unit/test_resources.py | 25 ++++++++++++++++--- .../tensilelite/Tensile/resources.py | 21 +++++++++++++--- 6 files changed, 51 insertions(+), 11 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 446acbbb0867..67c2c878c1b1 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -146,7 +146,8 @@ def getAllCustomKernelNames(directory=None): return custom_kernel_names() # Sorted in alphabetical order so that custom-kernel enumeration (notably the CustomKernels: ["*"] # wildcard) does not depend on os.listdir order, which varies with the - # filesystem and with how the package was installed. + # filesystem and with how the package was installed. iterCustomKernelFiles + # walks vendor subdirectories (aiter/, tensile/, ...). return sorted(os.path.basename(path)[:-2] for path in iterCustomKernelFiles(directory)) def getCustomKernelContents(name, directory=None): @@ -158,7 +159,7 @@ def getCustomKernelContents(name, directory=None): except Exception as error: raise RuntimeError(f"Failed to find custom kernel: {name}") from error try: - with open(os.path.join(directory, f"{name}.s")) as f: + with open(getCustomKernelFilepath(name, directory)) as f: return f.read() except OSError as e: raise RuntimeError("Failed to find custom kernel: {}".format(os.path.join(directory, name))) from e diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py index 2ed065fb399f..ef24ca41acb4 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernelMetadata.py @@ -685,7 +685,7 @@ def test_validate_at_build_counts_issues_and_dedups(tmp_path): def test_handle_custom_kernel_uses_mapping_name(monkeypatch): monkeypatch.setattr( hck_mod, "getCustomKernelConfig", - lambda name, isp, directory: {"MatrixInstruction": [16, 16, 16, 1]}, + lambda name, isp, directory=None: {"MatrixInstruction": [16, 16, 16, 1]}, ) sol = {"CustomKernel": {"name": "k0"}} diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_ordering.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_ordering.py index 47c8317a2280..6c0fa0f148ec 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_ordering.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_ordering.py @@ -32,6 +32,14 @@ def test_names_drop_the_dot_s_suffix_and_ignore_other_files(tmp_path): assert getAllCustomKernelNames(directory=str(tmp_path)) == ["kernel"] +def test_names_include_subdirectory_kernels(tmp_path): + (tmp_path / "tensile").mkdir() + (tmp_path / "top.s").write_text("s_endpgm\n", encoding="utf-8") + (tmp_path / "tensile" / "nested.s").write_text("s_endpgm\n", encoding="utf-8") + + assert getAllCustomKernelNames(directory=str(tmp_path)) == ["nested", "top"] + + def test_bundled_custom_kernel_names_are_sorted(): names = getAllCustomKernelNames() diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py index 18bfc315821b..ae736fc431d3 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py @@ -7,7 +7,6 @@ import Tensile.CustomKernels as CustomKernels - pytestmark = pytest.mark.unit KNOWN_CUSTOM_KERNEL = ( diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_resources.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_resources.py index 190eb1c504f1..e37d90eee509 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_resources.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_resources.py @@ -100,13 +100,25 @@ def test_copy_static_files_preflights_all_resources(tmp_path, monkeypatch): def test_custom_kernel_names_filters_suffixes_and_sorts_deterministically(monkeypatch): class Resource: - def __init__(self, name, is_file=True): + def __init__(self, name, is_file=True, children=None): self.name = name self._is_file = is_file + self._children = children or [] def is_file(self): return self._is_file + def is_dir(self): + return not self._is_file + + def iterdir(self): + return iter(self._children) + + nested = Resource( + "tensile", + is_file=False, + children=[Resource("z.s"), Resource("skip.txt")], + ) first_order = [ Resource("b.s"), Resource("a.s"), @@ -114,6 +126,7 @@ def is_file(self): Resource(".hidden.s"), Resource("note.txt"), Resource("directory.s", is_file=False), + nested, ] orders = [first_order, list(reversed(first_order))] @@ -123,7 +136,7 @@ def iterdir(self): monkeypatch.setattr(resources, "_custom_kernels", lambda: ResourceDir()) - expected = [".hidden", "a", "b", "foo.bar"] + expected = [".hidden", "a", "b", "foo.bar", "z"] assert resources.custom_kernel_names() == expected assert resources.custom_kernel_names() == expected @@ -131,8 +144,12 @@ def iterdir(self): def test_custom_kernel_text_uses_resource_root(tmp_path, monkeypatch): root = _fake_resource_tree(tmp_path, monkeypatch) (root / "CustomKernels" / "kernel.s").write_text("s_nop 0\n", encoding="utf-8") + nested = root / "CustomKernels" / "aiter" + nested.mkdir() + (nested / "nested.s").write_text("s_nop 1\n", encoding="utf-8") assert resources.custom_kernel_text("kernel") == "s_nop 0\n" + assert resources.custom_kernel_text("nested") == "s_nop 1\n" def test_custom_kernel_text_raises_for_missing_resource(tmp_path, monkeypatch): @@ -199,6 +216,7 @@ def test_resource_helpers_work_from_zip_package(tmp_path, monkeypatch): ) zip_file.writestr(f"{package}/CustomKernels/b.s", "kernel b\n") zip_file.writestr(f"{package}/CustomKernels/a.s", "kernel a\n") + zip_file.writestr(f"{package}/CustomKernels/tensile/nested.s", "kernel nested\n") zip_file.writestr(f"{package}/CustomKernels/readme.txt", "not a kernel\n") zip_file.writestr( f"{package}/TensileLogic/known_bugs.yaml", known_bugs @@ -212,8 +230,9 @@ def test_resource_helpers_work_from_zip_package(tmp_path, monkeypatch): try: assert zip_resources.__file__.startswith(f"{archive}/") assert isinstance(zip_resources._root(), ZipPath) - assert zip_resources.custom_kernel_names() == ["a", "b"] + assert zip_resources.custom_kernel_names() == ["a", "b", "nested"] assert zip_resources.custom_kernel_text("a") == "kernel a\n" + assert zip_resources.custom_kernel_text("nested") == "kernel nested\n" assert zip_resources.known_bugs_text() == known_bugs assert zip_resources.ductile_defaults_text() == defaults diff --git a/projects/hipblaslt/tensilelite/Tensile/resources.py b/projects/hipblaslt/tensilelite/Tensile/resources.py index 4d391d0f0152..f50bbfc75c53 100644 --- a/projects/hipblaslt/tensilelite/Tensile/resources.py +++ b/projects/hipblaslt/tensilelite/Tensile/resources.py @@ -83,6 +83,17 @@ def _custom_kernels() -> Traversable: return _resource("CustomKernels") +def _iter_custom_kernel_resources(root: Traversable = None): + """Yield bundled ``.s`` files, including those in vendor subdirectories.""" + item = _custom_kernels() if root is None else root + children = sorted(item.iterdir(), key=lambda resource: resource.name) + for resource in children: + if resource.is_file() and resource.name.endswith(".s"): + yield resource + elif resource.is_dir(): + yield from _iter_custom_kernel_resources(resource) + + def _validate_custom_kernel_resource_name(name: str) -> None: """Reject path-bearing names at the bundled-resource boundary.""" if "/" in name or "\\" in name or PureWindowsPath(name).drive: @@ -94,16 +105,18 @@ def _validate_custom_kernel_resource_name(name: str) -> None: def custom_kernel_names() -> List[str]: """Return bundled custom kernel names in deterministic order.""" return sorted( - resource.name[:-2] - for resource in _custom_kernels().iterdir() - if resource.is_file() and resource.name.endswith(".s") + resource.name[:-2] for resource in _iter_custom_kernel_resources() ) def custom_kernel_text(name: str) -> str: """Read a bundled custom kernel assembly resource.""" _validate_custom_kernel_resource_name(name) - return _resource_text("CustomKernels", f"{name}.s") + target = f"{name}.s" + for resource in _iter_custom_kernel_resources(): + if resource.name == target: + return resource.read_text(encoding="utf-8") + raise FileNotFoundError(target) def known_bugs_text() -> str: From 753608bc872f0e18128cafa94834a4756e0b75be Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Mon, 14 Sep 2026 18:13:03 +0000 Subject: [PATCH 55/58] fix regressions --- .../tensilelite/Tensile/CustomKernels.py | 10 +++++++ ...k_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s | 2 +- .../Tests/custom/custom_tensile_sk.yaml | 2 +- .../unit/test_CustomKernels_resources.py | 13 ++++++++ .../include/Tensile/ContractionSolution.hpp | 30 +++++++++---------- .../tensilelite/include/Tensile/DataTypes.hpp | 8 ++--- .../tensilelite/src/ContractionSolution.cpp | 19 ++++++++++-- 7 files changed, 61 insertions(+), 23 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py index 67c2c878c1b1..ca1933335262 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels.py @@ -124,7 +124,16 @@ def supportsUserSgprKernargPreload(rocmVersion): rocmVersion.major == 6 and rocmVersion.patch >= 32650 ) +_DEFAULT_CUSTOM_KERNEL_DIR = os.path.join(os.path.dirname(os.path.abspath(__file__)), "CustomKernels") + + +def _custom_kernel_dir(directory=None): + """Resolve the CustomKernels tree; None means the packaged source directory.""" + return _DEFAULT_CUSTOM_KERNEL_DIR if directory is None else directory + + def getCustomKernelFilepath(name, directory=None): + directory = _custom_kernel_dir(directory) flat = os.path.join(directory, (name + ".s")) if os.path.isfile(flat): return flat @@ -135,6 +144,7 @@ def getCustomKernelFilepath(name, directory=None): def iterCustomKernelFiles(directory=None): """Yield custom kernel assembly files using the same recursive discovery as the loader.""" + directory = _custom_kernel_dir(directory) for root, dirs, files in os.walk(directory): dirs.sort() for fname in sorted(files): diff --git a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s index a183e01d7c66..e4a6d46fb8c1 100644 --- a/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s +++ b/projects/hipblaslt/tensilelite/Tensile/CustomKernels/tensile/c_tensile_sk_Cijk_Ailk_Bjlk_HHS_BH_UserArgs_MT128x256x64_MI16x16x1.s @@ -95,7 +95,7 @@ custom.config: { type: uint32, semantic: SKTilesAndSplit } ] macrotile: [128, 256, 64] threads: [256, 1, 1] - grid: [TilesXYBatch, One, One] + grid: [StreamKWithBatch, One, One] workspaceType: StreamK workspaceSizePerElemC: 4 workspaceSizePerElemBias: 4 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml index 22d17513dfd9..e832ba1b01f4 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/custom/custom_tensile_sk.yaml @@ -71,7 +71,7 @@ BenchmarkProblems: { type: uint32, semantic: SKTilesAndSplit } ] macrotile: [128, 256, 64] threads: [256, 1, 1] - grid: [TilesXYBatch, One, One] + grid: [StreamKWithBatch, One, One] workspaceType: StreamK workspaceSizePerElemC: 4 workspaceSizePerElemBias: 4 diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py index ae736fc431d3..2709cb0722b5 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_CustomKernels_resources.py @@ -2,6 +2,7 @@ # SPDX-License-Identifier: MIT from types import SimpleNamespace +import os import pytest @@ -133,3 +134,15 @@ def test_real_default_custom_kernel_resource_is_available(): assert KNOWN_CUSTOM_KERNEL in names assert "custom.config" in CustomKernels.getCustomKernelContents(KNOWN_CUSTOM_KERNEL) + + +def test_get_custom_kernel_filepath_none_resolves_bundled_kernel(): + # ValidateMetadata during Tensile runs calls this with directory=None. + path = CustomKernels.getCustomKernelFilepath(KNOWN_CUSTOM_KERNEL) + assert os.path.basename(path) == KNOWN_CUSTOM_KERNEL + ".s" + assert os.path.isfile(path) + + +def test_validate_custom_kernel_metadata_default_directory(): + valid, msg = CustomKernels.validateCustomKernelMetadata(KNOWN_CUSTOM_KERNEL) + assert valid, msg diff --git a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp index 7117a75ada38..505a3d7785af 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/ContractionSolution.hpp @@ -159,10 +159,10 @@ namespace TensileLite COUNT, }; - std::string toString(CustomArgSemantic arg); - CustomArgSemantic fromStringCustomArgSemantic(std::string& str); - std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t); - std::istream& operator>>(std::istream& stream, CustomArgSemantic& t); + TENSILELITEHOST_EXPORT std::string toString(CustomArgSemantic arg); + TENSILELITEHOST_EXPORT CustomArgSemantic fromStringCustomArgSemantic(std::string& str); + TENSILELITEHOST_EXPORT std::ostream& operator<<(std::ostream& stream, const CustomArgSemantic& t); + TENSILELITEHOST_EXPORT std::istream& operator>>(std::istream& stream, CustomArgSemantic& t); struct CustomArgDefinition { @@ -172,9 +172,9 @@ namespace TensileLite size_t index = 0; }; - std::string toString(CustomArgDefinition arg); - std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t); - std::istream& operator>>(std::istream& stream, CustomArgDefinition& t); + TENSILELITEHOST_EXPORT std::string toString(CustomArgDefinition arg); + TENSILELITEHOST_EXPORT std::ostream& operator<<(std::ostream& stream, const CustomArgDefinition& t); + TENSILELITEHOST_EXPORT std::istream& operator>>(std::istream& stream, CustomArgDefinition& t); enum CustomGridSize { @@ -190,10 +190,10 @@ namespace TensileLite CustomGridSize_Count, }; - std::string toString(CustomGridSize mode); - CustomGridSize fromStringCustomGridSize(std::string& str); - std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t); - std::istream& operator>>(std::istream& stream, CustomGridSize& t); + TENSILELITEHOST_EXPORT std::string toString(CustomGridSize mode); + TENSILELITEHOST_EXPORT CustomGridSize fromStringCustomGridSize(std::string& str); + TENSILELITEHOST_EXPORT std::ostream& operator<<(std::ostream& stream, const CustomGridSize& t); + TENSILELITEHOST_EXPORT std::istream& operator>>(std::istream& stream, CustomGridSize& t); enum CustomWorkspaceType { @@ -204,10 +204,10 @@ namespace TensileLite CustomWorkspaceType_Count, }; - std::string toString(CustomWorkspaceType type); - CustomWorkspaceType fromStringCustomWorkspaceType(std::string& str); - std::ostream& operator<<(std::ostream& stream, const CustomWorkspaceType& t); - std::istream& operator>>(std::istream& stream, CustomWorkspaceType& t); + TENSILELITEHOST_EXPORT std::string toString(CustomWorkspaceType type); + TENSILELITEHOST_EXPORT CustomWorkspaceType fromStringCustomWorkspaceType(std::string& str); + TENSILELITEHOST_EXPORT std::ostream& operator<<(std::ostream& stream, const CustomWorkspaceType& t); + TENSILELITEHOST_EXPORT std::istream& operator>>(std::istream& stream, CustomWorkspaceType& t); struct CustomKernel { diff --git a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp index c6e131d96224..c70f4010427c 100644 --- a/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp +++ b/projects/hipblaslt/tensilelite/include/Tensile/DataTypes.hpp @@ -520,10 +520,10 @@ namespace TensileLite CustomArgType_Count, }; - std::string toString(CustomArgType arg); - CustomArgType fromStringCustomArgType(std::string& str); - std::ostream& operator<<(std::ostream& stream, const CustomArgType& t); - std::istream& operator>>(std::istream& stream, CustomArgType& t); + TENSILELITEHOST_EXPORT std::string toString(CustomArgType arg); + TENSILELITEHOST_EXPORT CustomArgType fromStringCustomArgType(std::string& str); + TENSILELITEHOST_EXPORT std::ostream& operator<<(std::ostream& stream, const CustomArgType& t); + TENSILELITEHOST_EXPORT std::istream& operator>>(std::istream& stream, CustomArgType& t); /** * @} diff --git a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp index f1c6b3b014ec..a3a97363e6f3 100644 --- a/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp +++ b/projects/hipblaslt/tensilelite/src/ContractionSolution.cpp @@ -5824,10 +5824,25 @@ namespace TensileLite Hardware const& hardware) const { StreamKSettings sk; - if(sizeMapping.streamK == 0) + const bool customStreamK + = customKernel.workspaceType == CustomWorkspaceType::StreamK + || customKernel.workspaceType == CustomWorkspaceType::StreamKWithReduction; + // Handwritten custom kernels advertise Stream-K via workspaceType, not + // sizeMapping.streamK. Without this, solve() enters the Stream-K path + // (customStreamK) then this helper returns grid=0 and hipLaunch fails + // with numWorkGroups=(0,1,1). + if(sizeMapping.streamK == 0 && !customStreamK) return sk; - auto tiles = problem.getNumTiles(sizeMapping, 1); + size_t tiles = 0; + if(handwrittenCustomKernel()) + { + dim3 dimTiles; + calculateTiles(dimTiles, problem); + tiles = dimTiles.x * dimTiles.y * dimTiles.z; + } + else + tiles = problem.getNumTiles(sizeMapping, 1); const bool effectiveDynamic = (sizeMapping.streamK == 5) ? streamK5EffectiveDynamic(problem, hardware) : false; From a8793401bfcabc0abdd6a983ed0b97a8e98eab5a Mon Sep 17 00:00:00 2001 From: jinchen62 Date: Wed, 16 Sep 2026 14:37:23 +0000 Subject: [PATCH 56/58] fix regressions --- .../Tensile/SolutionStructs/Solution.py | 26 ++++++++------ .../Tests/unit/test_custom_kernel_host.py | 36 ++++++++++++++++++- 2 files changed, 50 insertions(+), 12 deletions(-) diff --git a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py index 4890b3bb66f7..d89efa5fb633 100644 --- a/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py +++ b/projects/hipblaslt/tensilelite/Tensile/SolutionStructs/Solution.py @@ -42,7 +42,7 @@ from Tensile.Common.LdsPaddingLimits import B128_PAD_STEP_BYTES, LDS_PAD_STEP_BYTES, \ ldsBlockError, ldsPadError from Tensile.Common.TypeValidationErrors import ConfigTypeError -from Tensile.CustomKernels import supportsUserSgprKernargPreload +from Tensile.CustomKernels import isCustomKernelConfig, supportsUserSgprKernargPreload from Tensile.SolutionStructs.LdsPadding import get_fp4_mt_config, get_fp8_mt_config, get_mxs_mt_config, \ get_fp16_mt_config, get_fp32_mt_config, get_metadata_mt_config, \ get_fp4_valid_blocks, get_fp8_valid_blocks, \ @@ -234,6 +234,18 @@ def _validateSubtileGRKPartition(state, printRejectionReason): return True +def _supportStreamKPerTileExtraIters(state): + """Whether this solution's asm claims the Stream-K per-tile extra-iters capability. + + Newly generated SK3 / SK5 kernels emit both K-split mappings and honor bit 29 + of MagicShiftItersPerTile as the runtime USO selector. SK4, SK0, and + handwritten custom kernels do not. Detection goes through + ``isCustomKernelConfig`` because GFA dropped the flat ``CustomKernelName`` + key from defaultSolution; indexing it here KeyErrors on ordinary GFA states. + """ + return state["StreamK"] in (3, 5) and not isCustomKernelConfig(state) + + def _validateStreamKForceDPOnly(state, printRejectionReason): if state["StreamKForceDPOnly"]: if state["StreamK"] != 3: @@ -1935,12 +1947,8 @@ def assignDerivedParameters( # K-split mappings and honors bit 29 of MagicShiftItersPerTile as the # runtime selector". It is fully derived here, overriding whatever the # solution YAML said, because only the generator knows what it just emitted. - # Newly generated SK3 / SK5 kernels emit both mappings plus the bit-29 gate. - # SK4 (dynamic) and SK0 do not, and custom kernels are hand-written asm that - # this generator did not produce, so none of them may claim the capability. - isCustomKernel = bool(state["CustomKernelName"]) state["InternalSupportParams"]["SupportStreamKPerTileExtraIters"] = \ - (state["StreamK"] in (3, 5)) and not isCustomKernel + _supportStreamKPerTileExtraIters(state) if state["StreamK"] != 0: #state["AssertSummationElementMultiple"] = 1 # Cannot keep ASEM with Stream-K @@ -5195,11 +5203,7 @@ def subCheckLdsBlockSizePerPad(tc, idx): else: reject(state, printRejectionReason, "%s's padded address is inconsistent"%tc) - ck = state.get("CustomKernel") - isActualCustomKernel = bool(state.get("CustomKernelName", "")) or \ - (isinstance(ck, dict) and bool(ck.get("name")) - and not ck.get("generated", False)) - if(not isActualCustomKernel): + if not isCustomKernelConfig(state): checkLdsBlockSizePerPad("A") checkLdsBlockSizePerPad("B") diff --git a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py index 0c8c29385ddc..00df2aebf52c 100644 --- a/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py +++ b/projects/hipblaslt/tensilelite/Tensile/Tests/unit/test_custom_kernel_host.py @@ -15,7 +15,7 @@ from Tensile.Common.DataType import DataType from Tensile.Common.Utilities import deriveWaveParams from Tensile.SolutionStructs.Naming import _getName, getKernelFileBase -from Tensile.SolutionStructs.Solution import Solution +from Tensile.SolutionStructs.Solution import Solution, _supportStreamKPerTileExtraIters from Tensile.Toolchain.Component import Assembler pytestmark = pytest.mark.unit @@ -139,6 +139,40 @@ def test_assign_custom_kernel_params_bias_gradient_workspace(): assert state["_WorkspaceSizePerElemBias"] == 4 +# --------------------------------------------------------------------------- # +# Stream-K USO capability vs handwritten custom kernels +# --------------------------------------------------------------------------- # + + +@pytest.mark.parametrize( + "state, expected", + [ + # GFA ordinary SK3/SK5: CustomKernelName is absent, not empty. + ({"StreamK": 3}, True), + ({"StreamK": 5}, True), + ({"StreamK": 4}, False), + ({"StreamK": 0}, False), + ({"StreamK": 3, "CustomKernelName": ""}, True), + ({"StreamK": 3, "CustomKernelName": "handwritten"}, False), + ({"StreamK": 3, "CustomKernel": {"name": "handwritten"}}, False), + ({"StreamK": 3, "CustomKernel": {"name": "gen", "generated": True}}, True), + ({"StreamK": 3, "CustomKernel": -1}, True), + ], +) +def test_uso_capability_does_not_require_custom_kernel_name(state, expected): + assert _supportStreamKPerTileExtraIters(state) is expected + + +def test_uso_capability_assignment_survives_missing_custom_kernel_name(): + # The merge-time KeyError was state["CustomKernelName"] inside + # assignDerivedParameters. Drive the same assignment the derivation uses. + state = {"StreamK": 3, "InternalSupportParams": {}} + state["InternalSupportParams"]["SupportStreamKPerTileExtraIters"] = ( + _supportStreamKPerTileExtraIters(state) + ) + assert state["InternalSupportParams"]["SupportStreamKPerTileExtraIters"] is True + + # --------------------------------------------------------------------------- # # Naming: custom-kernel name short-circuits # --------------------------------------------------------------------------- # From 5b3aae7f8d5ac400312872635b463b4115e3a4fa Mon Sep 17 00:00:00 2001 From: "T.J. Alumbaugh" Date: Thu, 17 Sep 2026 16:04:07 -0600 Subject: [PATCH 57/58] fix(tensilelite): emit RPATH for tensilelite-client so the built host library wins (#12278) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit JIRA ID : AIHPBLAS-4086 Targets `GemmFromAnywhere` (#11155) rather than `develop`, so @jinchen62 can test it directly on that branch. ## Motivation The `preliminary(hipblaslt)` job on #11155 fails with **127 failed, 5 passed** in the tensilelite common tests, while the same tests pass locally on a gfx942 box. The entire 140MB CI log contains exactly one distinct error, repeated once per failed test: ``` .../caches/4463c0a054b3/source/library/gfx942/TensileLibrary.yaml:55:1: error: unknown key 'solutions' terminate called after throwing an instance of 'std::runtime_error' what(): Failed to load solution library → Aborted (core dumped), exit 134 ``` The `FileNotFoundError` on `00_Final.csv` that the `test_use_cache` tests report is purely downstream — the client aborted, so no benchmark CSV was ever written. **This is not a bug in #11155's logic.** It is a pre-existing library-shadowing bug in the test harness that #11155 is simply the first PR to expose, because it is the first to change the solution schema (`CustomKernelName` → `customKernel`). ## Technical Details 1. `tox.ini` builds `tensilelite-client` into `build_tmp/` and hands it to pytest via `--prebuilt-client`. 2. That client links `libtensilelite-host.so.1` — where the YAML deserializer (`src/llvm/Loading.cpp`) lives — and recorded a **`RUNPATH`**, not an `RPATH`. 3. **`RUNPATH` is searched after `LD_LIBRARY_PATH`.** `tox.ini` sets `LD_LIBRARY_PATH = {ROCM_PATH}/lib:...`, and the Jenkins job independently exports `LD_LIBRARY_PATH=/opt/rocm/lib`. 4. `tensilelite/CMakeLists.txt:170` installs the `tensilelite-host` target, so on a CI container with hipBLASLt installed, `/opt/rocm/lib/libtensilelite-host.so.1` exists. 5. The freshly built host library is therefore **silently bypassed**; the client runs against the older installed one, which does not understand the new schema. Why it cannot fail on a typical dev box: local `/opt/rocm/lib` has only `libhipblaslt.so*` and **no `libtensilelite-host.so`**, so the lookup falls through to `RUNPATH` and picks up the correct fresh build. The fix links the client with `-Wl,--disable-new-dtags`, emitting `RPATH`, which is searched *before* `LD_LIBRARY_PATH`. `tensilelite-client` has no `install()` rule — it is a build/test-only binary — so there is no packaging or install-time impact, and `CMAKE_INSTALL_RPATH` is untouched. ## Test Plan On a gfx942 box (ROCm 7.2.4), with a stale `libtensilelite-host.so.1` built from `develop`@merge-base placed first on `LD_LIBRARY_PATH` to emulate the CI container: 1. Direct client check: linker tag, library resolution, and a real run against the exact `ClientParameters.ini` from a failing cache dir. 2. End-to-end: CI's own pipeline — `tox -e py3` with `--cxx-flags-release=-O3`, sdist install, `invoke build-client` — scoped to the previously failing `use_cache` tests. 3. Negative control: revert the flag, relink, re-run with tox's exact `LD_LIBRARY_PATH`. ## Test Result Direct client check: | | linker tag | resolves to | client exit | |---|---|---|---| | before | RUNPATH | stale lib | **134**, `Failed to load solution library` | | after | RPATH | build-tree lib | **0** | End-to-end with the stale lib injected: **5 passed** (`test_use_cache.py::test_use_cache`, `test_compile_and_benchmark`, `test_use_cache_creates_cache_dir`, `test_use_cache_different_params`, `test_build_only.py::test_use_cache`) — all previously failing in CI. Negative control: with the flag reverted, the client picks the stale library and aborts 134 under tox's exact `LD_LIBRARY_PATH`. So the green run is attributable to the fix, not to the stale library never being on the path. Caveats, stated plainly: - Verification used a `develop`-built stand-in for the stale library, **not** the real ROCm-installed one from CI's container (which also runs Clang 24.0.0 vs 22.0.0 locally). The mechanism is proven; the exact CI binary was not reproducible off-box. Consequently my repro reports `unknown key 'customKernel'` where CI reports `unknown key 'solutions'` — same failure mode, different key, because the CI container's library is older than `develop`@merge-base. - The real confirmation is CI itself: if this hypothesis is right, `preliminary(hipblaslt)` on `GemmFromAnywhere` + this commit should go green. - **`cpu-gemm-driver` still has `RUNPATH`** and the identical latent hazard. Deliberately left alone to keep this change minimal; it is a one-line follow-up. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests. ## Risk level Low. Six lines in one `CMakeLists.txt`, affecting the link of a single non-installed test binary. The worst case is that `LD_LIBRARY_PATH` can no longer override the host library for `tensilelite-client` — which is precisely the behaviour being fixed, but worth noting if anyone deliberately relies on that override to A/B a library build. 🤖 Generated with [Claude Code](https://claude.com/claude-code) Co-authored-by: Claude --- projects/hipblaslt/tensilelite/client/CMakeLists.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/projects/hipblaslt/tensilelite/client/CMakeLists.txt b/projects/hipblaslt/tensilelite/client/CMakeLists.txt index fb3e18623eb3..c9c2412ca742 100644 --- a/projects/hipblaslt/tensilelite/client/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/client/CMakeLists.txt @@ -146,6 +146,12 @@ endif() add_executable(tensilelite-client "${CMAKE_CURRENT_SOURCE_DIR}/main.cpp") target_link_libraries(tensilelite-client PRIVATE tensilelite-client-common) +# Emit RPATH instead of RUNPATH. RUNPATH is searched after LD_LIBRARY_PATH, so a +# hipBLASLt installed under ${ROCM_PATH}/lib silently shadows the freshly built +# libtensilelite-host and the client then reads library files with a stale +# deserializer. RPATH is searched first and keeps the client on its own build. +target_link_options(tensilelite-client PRIVATE "-Wl,--disable-new-dtags") + add_executable(cpu-gemm-driver "${CMAKE_CURRENT_SOURCE_DIR}/cpu_gemm_driver.cpp") target_link_libraries(cpu-gemm-driver PRIVATE tensilelite-client-common) From d0e632213136b10b25c046e94c02c80b75549ada Mon Sep 17 00:00:00 2001 From: "T.J. Alumbaugh" Date: Fri, 18 Sep 2026 08:53:20 -0600 Subject: [PATCH 58/58] fix(tensilelite): keep -fopenmp off tensilelite-host so LLVM headers match the linked LLVM (#12295) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit JIRA ID : AIHPBLAS-4086 Targets `GemmFromAnywhere` (#11155) rather than `develop`, so @jinchen62 can take it directly on that branch. ## Motivation `preliminary(hipblaslt)` on #11155 fails with **127 failed, 8 passed, 1144 skipped** in the tensilelite common tests, while the same tests pass on a local gfx942 box. The entire ~140MB CI log contains exactly one distinct error, repeated once per failed test: ``` .../caches//source/library/gfx942/TensileLibrary.yaml:55:1: error: unknown key 'solutions' terminate called after throwing an instance of 'std::runtime_error' what(): Failed to load solution library → Aborted (core dumped), exit 134 ``` The `FileNotFoundError` on `00_Final.csv` that `test_use_cache` reports is a downstream symptom — the client aborted, so no benchmark CSV was written. **This is not a bug in the Gemm-From-Anywhere logic.** It is a build-configuration problem that this branch is the first to trigger. ## Technical Details `tensilelite-host` was being compiled against the **system LLVM 18** headers (`/usr/include/llvm` → `/usr/lib/llvm-18/include/llvm`) while linking **ROCm's LLVM 24** static libraries. LLVM 24 added `AliasMap` / `saveAliasHNode` to `llvm::yaml::Input`, so the class layouts differ. The compiled code touched `ValidKeys` / `Mapping` / `EC` at the wrong offsets, which is why the failure looked impossible against the source: `mapRequired("solutions")` runs, silently yields an empty vector, and the key is *then* reported as never-seen. How `-fopenmp` gets onto the host target: 1. This branch links `roc::mxDataGenerator` into `tensilelite-host`. 2. `roc::mxDataGenerator` links `OpenMP::OpenMP_CXX` (`shared/mxdatagenerator/CMakeLists.txt:14`), whose `INTERFACE_COMPILE_OPTIONS` carry `-fopenmp=libomp`. 3. `-fopenmp` makes clang add `${ROCM_PATH}/lib/llvm/bin/../include` as an **implicit system** include dir in order to locate `omp.h`. That is the same directory as the explicit `-I/opt/rocm/lib/llvm/include`, so the explicit user `-I` is demoted, and `` includes fall through to the system LLVM 18 tree. develop's `tensilelite-host` has no `-fopenmp` (verified: count 0 vs 1), which is why only this branch is affected. Evidence — preprocessed TU comparison of `src/llvm/Loading.cpp`, identical compiler (Clang 24) for both: | build | `/usr/include/llvm/` markers in TU | `YAMLTraits.h` resolved to | |---|---|---| | develop | 0 | `/opt/rocm/lib/llvm/include/...` (LLVM 24) | | this branch | **356** | `/usr/include/llvm/...` (**LLVM 18**) | Flag isolation via `-E` alone: ``` PR flags (-I + -fopenmp) -> 356 keep -fopenmp, drop explicit -I -> 356 keep -I, drop -fopenmp -> 0 <-- only correct configuration drop both -> 356 ``` **The fix:** consume mxDataGenerator's include directories explicitly, and take the target itself as a `$` dependency so its `INTERFACE_COMPILE_OPTIONS` never reach our compiles. The pre-swizzle helper is correct serially, so dropping `-fopenmp` there is safe. This branch also **reverts #12278** (`5b3aae7f8d5`). That commit was my earlier, incorrect diagnosis of this same failure — it claimed a `RUNPATH`/`LD_LIBRARY_PATH` shadowing of `libtensilelite-host.so`. The CI image contains no `libtensilelite-host` and no `libhipblaslt` at all, so there was nothing to shadow, and it did not fix anything. The RUNPATH issue it addressed is real but latent and unrelated; it can be re-proposed separately against `develop` on its own merits. ## Test Plan Reproduce and verify inside the actual CI container image (`mci-base/ubu24-stg1`, Clang 24, gfx942), which is required — the failure cannot reproduce on a ROCm 7.2.4 / Clang 22 host. 1. Confirm `-fopenmp` is gone from `tensilelite-host` (`grep -c fopenmp .../tensilelite-host.dir/flags.make`) while the mxdatagen include dir and `HIPBLASLT_ENABLE_MXDATAGENERATOR` are retained. 2. Run the previously failing client invocation directly against the generated `TensileLibrary.yaml`. 3. Clean build, full CI scope: `tox -e py3 -- -m common --durations=0`. ## Test Result 1. `-fopenmp` count on `tensilelite-host`: **0**; mxdatagen include dir present; `HIPBLASLT_ENABLE_MXDATAGENERATOR` still defined. 2. Client exits **0** on the previously failing `TensileLibrary.yaml` (the one containing `customKernel`). 3. Clean build, full CI scope: ``` ========= 132 passed, 1144 skipped, 64 warnings in 2592.60s (0:43:12) ========== congratulations :) ``` `unknown key 'solutions'` occurrences: **0**. `FAILED` lines: **0**. Same 1144 skip count as the CI run, so the same test scope — versus CI's `127 failed, 8 passed, 1144 skipped`. ## Submission Checklist - [x] Look over the contributing guidelines at https://github.com/ROCm/TheRock/blob/main/GOVERNANCE.md#pull-requests. ## Risk level Low. One `CMakeLists.txt` hunk changing how a single target consumes mxDataGenerator's usage requirements, plus a revert of a commit that was verified to have no effect on this failure. No source or kernel-generation changes. Two follow-ups deliberately **not** included here, to keep the change minimal: - `tensilelite-client-common` still receives `-fopenmp`. It does on `develop` too, and `develop` passes, so this matches known-good behaviour — but it is worth a hardening pass. - More broadly, **any** target on this image that picks up `-fopenmp` will compile `` from LLVM 18. A systemic fix would stop relying on an explicit `-I` outranking clang's implicit system include dirs. 🤖 Generated with [Claude Code](https://claude.com/claude-code) --------- Co-authored-by: Claude --- projects/hipblaslt/tensilelite/CMakeLists.txt | 29 +++++++++++++++++-- .../tensilelite/client/CMakeLists.txt | 6 ---- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/projects/hipblaslt/tensilelite/CMakeLists.txt b/projects/hipblaslt/tensilelite/CMakeLists.txt index 31c6f4e38c3c..a061589af760 100644 --- a/projects/hipblaslt/tensilelite/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/CMakeLists.txt @@ -117,8 +117,18 @@ if(TENSILELITE_ENABLE_HOST) add_library(tensilelite-mxdatagenerator-headers INTERFACE) target_include_directories(tensilelite-mxdatagenerator-headers INTERFACE $) + # LINK_ONLY: OpenMP::OpenMP_CXX carries -fopenmp in its INTERFACE_COMPILE_OPTIONS. + # Propagating that into tensilelite-host's compiles is not merely unnecessary + # (the pre-swizzle helper is correct serially) -- it is actively harmful. On the + # CI image, -fopenmp re-adds ${ROCM_PATH}/lib/llvm/include as an *implicit system* + # include dir to locate omp.h. That demotes the explicit -I for the same directory, + # and includes then fall through to the system LLVM 18 tree in + # /usr/include/llvm. tensilelite-host would compile LLVM YAMLIO against LLVM 18 + # headers while linking ROCm's LLVM 24 libraries -- an ABI mismatch that silently + # corrupts llvm::yaml::Input, making TensileLibrary.yaml fail to parse with + # "unknown key 'solutions'". Keep the link requirement, drop the compile options. target_link_libraries(tensilelite-mxdatagenerator-headers - INTERFACE OpenMP::OpenMP_CXX) + INTERFACE $) set(_mxdatagen_target tensilelite-mxdatagenerator-headers) else() set(TENSILELITE_HOST_MXDATAGENERATOR OFF) @@ -140,7 +150,22 @@ if(TENSILELITE_ENABLE_HOST) ) if(TENSILELITE_HOST_MXDATAGENERATOR) - target_link_libraries(tensilelite-host PRIVATE ${_mxdatagen_target}) + # Consume mxDataGenerator's include directories, but take the target itself as a + # LINK_ONLY dependency so its INTERFACE_COMPILE_OPTIONS do not reach our compiles. + # roc::mxDataGenerator links OpenMP::OpenMP_CXX (shared/mxdatagenerator/CMakeLists.txt), + # which carries -fopenmp. On the CI image -fopenmp makes clang re-add + # ${ROCM_PATH}/lib/llvm/include as an *implicit system* include dir (to find omp.h). + # That demotes the explicit -I for the same directory, and includes then + # fall through to the system LLVM 18 tree under /usr/include/llvm. tensilelite-host + # would compile llvm::yaml against LLVM 18 headers while linking ROCm's LLVM 24 + # libraries: an ABI mismatch that silently corrupts llvm::yaml::Input, so every + # TensileLibrary.yaml fails to load with "unknown key 'solutions'". + # The pre-swizzle helper is correct serially, so dropping -fopenmp here is safe. + get_target_property(_mxdatagen_incs ${_mxdatagen_target} INTERFACE_INCLUDE_DIRECTORIES) + if(_mxdatagen_incs) + target_include_directories(tensilelite-host PRIVATE ${_mxdatagen_incs}) + endif() + target_link_libraries(tensilelite-host PRIVATE $) target_compile_definitions(tensilelite-host PRIVATE HIPBLASLT_ENABLE_MXDATAGENERATOR) endif() diff --git a/projects/hipblaslt/tensilelite/client/CMakeLists.txt b/projects/hipblaslt/tensilelite/client/CMakeLists.txt index c9c2412ca742..fb3e18623eb3 100644 --- a/projects/hipblaslt/tensilelite/client/CMakeLists.txt +++ b/projects/hipblaslt/tensilelite/client/CMakeLists.txt @@ -146,12 +146,6 @@ endif() add_executable(tensilelite-client "${CMAKE_CURRENT_SOURCE_DIR}/main.cpp") target_link_libraries(tensilelite-client PRIVATE tensilelite-client-common) -# Emit RPATH instead of RUNPATH. RUNPATH is searched after LD_LIBRARY_PATH, so a -# hipBLASLt installed under ${ROCM_PATH}/lib silently shadows the freshly built -# libtensilelite-host and the client then reads library files with a stale -# deserializer. RPATH is searched first and keeps the client on its own build. -target_link_options(tensilelite-client PRIVATE "-Wl,--disable-new-dtags") - add_executable(cpu-gemm-driver "${CMAKE_CURRENT_SOURCE_DIR}/cpu_gemm_driver.cpp") target_link_libraries(cpu-gemm-driver PRIVATE tensilelite-client-common)